Lines Matching refs:LMEM_PCCCR_REG

205     LMEM_PCCCR_REG(base) = LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK;  in LMEM_EnableCodeCache()
206     LMEM_PCCCR_REG(base) |= LMEM_PCCCR_GO_MASK;  in LMEM_EnableCodeCache()
209     while (LMEM_PCCCR_REG(base) & LMEM_PCCCR_GO_MASK);  in LMEM_EnableCodeCache()
212     LMEM_PCCCR_REG(base) = (LMEM_PCCCR_ENWRBUF_MASK | LMEM_PCCCR_ENCACHE_MASK);  in LMEM_EnableCodeCache()
225     LMEM_PCCCR_REG(base) = 0x0;  in LMEM_DisableCodeCache()
238     LMEM_PCCCR_REG(base) |= LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK;  in LMEM_FlushCodeCache()
239     LMEM_PCCCR_REG(base) |= LMEM_PCCCR_GO_MASK;  in LMEM_FlushCodeCache()
242     while (LMEM_PCCCR_REG(base) & LMEM_PCCCR_GO_MASK);  in LMEM_FlushCodeCache()
294     LMEM_PCCCR_REG(base) |= LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK;  in LMEM_InvalidateCodeCache()
295     LMEM_PCCCR_REG(base) |= LMEM_PCCCR_GO_MASK;  in LMEM_InvalidateCodeCache()
298     while (LMEM_PCCCR_REG(base) & LMEM_PCCCR_GO_MASK);  in LMEM_InvalidateCodeCache()