Lines Matching refs:base
47 void ADC_Init(ADC_Type* base, const adc_init_config_t* initConfig) in ADC_Init() argument
52 ADC_Deinit(base); in ADC_Init()
55 ADC_SetSampleRate(base, initConfig->sampleRate); in ADC_Init()
59 ADC_LevelShifterEnable(base); in ADC_Init()
61 ADC_LevelShifterDisable(base); in ADC_Init()
64 while((ADC_ADC_CFG_REG(base) & ADC_ADC_CFG_ADC_PD_OK_MASK)); in ADC_Init()
74 void ADC_Deinit(ADC_Type* base) in ADC_Deinit() argument
77 ADC_SetConvertCmd(base, adcLogicChA, false); in ADC_Deinit()
78 ADC_SetConvertCmd(base, adcLogicChB, false); in ADC_Deinit()
79 ADC_SetConvertCmd(base, adcLogicChC, false); in ADC_Deinit()
80 ADC_SetConvertCmd(base, adcLogicChD, false); in ADC_Deinit()
83 ADC_CH_A_CFG1_REG(base) = 0x0; in ADC_Deinit()
84 ADC_CH_A_CFG2_REG(base) = ADC_CH_A_CFG2_CHA_AUTO_DIS_MASK; in ADC_Deinit()
85 ADC_CH_B_CFG1_REG(base) = 0x0; in ADC_Deinit()
86 ADC_CH_B_CFG2_REG(base) = ADC_CH_B_CFG2_CHB_AUTO_DIS_MASK; in ADC_Deinit()
87 ADC_CH_C_CFG1_REG(base) = 0x0; in ADC_Deinit()
88 ADC_CH_C_CFG2_REG(base) = ADC_CH_C_CFG2_CHC_AUTO_DIS_MASK; in ADC_Deinit()
89 ADC_CH_D_CFG1_REG(base) = 0x0; in ADC_Deinit()
90 ADC_CH_D_CFG2_REG(base) = ADC_CH_D_CFG2_CHD_AUTO_DIS_MASK; in ADC_Deinit()
91 ADC_CH_SW_CFG_REG(base) = 0x0; in ADC_Deinit()
92 ADC_TIMER_UNIT_REG(base) = 0x0; in ADC_Deinit()
93 ADC_DMA_FIFO_REG(base) = ADC_DMA_FIFO_DMA_WM_LVL(0xF); in ADC_Deinit()
94 ADC_INT_SIG_EN_REG(base) = 0x0; in ADC_Deinit()
95 ADC_INT_EN_REG(base) = 0x0; in ADC_Deinit()
96 ADC_INT_STATUS_REG(base) = 0x0; in ADC_Deinit()
97 ADC_ADC_CFG_REG(base) = ADC_ADC_CFG_ADC_EN_MASK; in ADC_Deinit()
106 void ADC_SetSampleRate(ADC_Type* base, uint32_t sampleRate) in ADC_SetSampleRate() argument
130 ADC_TIMER_UNIT_REG(base) = 0x0; in ADC_SetSampleRate()
131 …ADC_TIMER_UNIT_REG(base) = ADC_TIMER_UNIT_PRE_DIV(preDiv) | ADC_TIMER_UNIT_CORE_TIMER_UNIT(coreTim… in ADC_SetSampleRate()
143 void ADC_SetClockDownCmd(ADC_Type* base, bool clockDown) in ADC_SetClockDownCmd() argument
146 ADC_ADC_CFG_REG(base) |= ADC_ADC_CFG_ADC_CLK_DOWN_MASK; in ADC_SetClockDownCmd()
148 ADC_ADC_CFG_REG(base) &= ~ADC_ADC_CFG_ADC_CLK_DOWN_MASK; in ADC_SetClockDownCmd()
159 void ADC_SetPowerDownCmd(ADC_Type* base, bool powerDown) in ADC_SetPowerDownCmd() argument
163 ADC_ADC_CFG_REG(base) |= ADC_ADC_CFG_ADC_PD_MASK; in ADC_SetPowerDownCmd()
165 while((ADC_ADC_CFG_REG(base) & ADC_ADC_CFG_ADC_PD_OK_MASK)); in ADC_SetPowerDownCmd()
169 ADC_ADC_CFG_REG(base) &= ~ADC_ADC_CFG_ADC_PD_MASK; in ADC_SetPowerDownCmd()
183 void ADC_LogicChInit(ADC_Type* base, uint8_t logicCh, const adc_logic_ch_init_config_t* chInitConfi… in ADC_LogicChInit() argument
188 ADC_SelectInputCh(base, logicCh, chInitConfig->inputChannel); in ADC_LogicChInit()
192 ADC_SetConvertRate(base, logicCh, chInitConfig->convertRate); in ADC_LogicChInit()
197 ADC_SetAverageNum(base, logicCh, chInitConfig->averageNumber); in ADC_LogicChInit()
198 ADC_SetAverageCmd(base, logicCh, true); in ADC_LogicChInit()
208 void ADC_LogicChDeinit(ADC_Type* base, uint8_t logicCh) in ADC_LogicChDeinit() argument
215 ADC_CH_A_CFG1_REG(base) = 0x0; in ADC_LogicChDeinit()
216 ADC_CH_A_CFG2_REG(base) = 0x8000; in ADC_LogicChDeinit()
219 ADC_CH_B_CFG1_REG(base) = 0x0; in ADC_LogicChDeinit()
220 ADC_CH_B_CFG2_REG(base) = 0x8000; in ADC_LogicChDeinit()
223 ADC_CH_C_CFG1_REG(base) = 0x0; in ADC_LogicChDeinit()
224 ADC_CH_C_CFG2_REG(base) = 0x8000; in ADC_LogicChDeinit()
227 ADC_CH_D_CFG1_REG(base) = 0x0; in ADC_LogicChDeinit()
228 ADC_CH_D_CFG2_REG(base) = 0x8000; in ADC_LogicChDeinit()
231 ADC_CH_SW_CFG_REG(base) = 0x0; in ADC_LogicChDeinit()
244 void ADC_SelectInputCh(ADC_Type* base, uint8_t logicCh, uint8_t inputCh) in ADC_SelectInputCh() argument
251 ADC_CH_A_CFG1_REG(base) = (ADC_CH_A_CFG1_REG(base) & ~ADC_CH_A_CFG1_CHA_SEL_MASK) | \ in ADC_SelectInputCh()
255 ADC_CH_B_CFG1_REG(base) = (ADC_CH_B_CFG1_REG(base) & ~ADC_CH_B_CFG1_CHB_SEL_MASK) | \ in ADC_SelectInputCh()
259 ADC_CH_C_CFG1_REG(base) = (ADC_CH_C_CFG1_REG(base) & ~ADC_CH_C_CFG1_CHC_SEL_MASK) | \ in ADC_SelectInputCh()
263 ADC_CH_D_CFG1_REG(base) = (ADC_CH_D_CFG1_REG(base) & ~ADC_CH_D_CFG1_CHD_SEL_MASK) | \ in ADC_SelectInputCh()
267 ADC_CH_SW_CFG_REG(base) = (ADC_CH_SW_CFG_REG(base) & ~ADC_CH_SW_CFG_CH_SW_SEL_MASK) | \ in ADC_SelectInputCh()
281 void ADC_SetConvertRate(ADC_Type* base, uint8_t logicCh, uint32_t convertRate) in ADC_SetConvertRate() argument
286 …uint32_t sampleRate = (4000000 >> (2 + (ADC_TIMER_UNIT_REG(base) >> ADC_TIMER_UNIT_PRE_DIV_SHIFT))… in ADC_SetConvertRate()
287 ((ADC_TIMER_UNIT_REG(base) & ADC_TIMER_UNIT_CORE_TIMER_UNIT_MASK) + 1); in ADC_SetConvertRate()
295 ADC_CH_A_CFG1_REG(base) = (ADC_CH_A_CFG1_REG(base) & ~ADC_CH_A_CFG1_CHA_TIMER_MASK) | \ in ADC_SetConvertRate()
299 ADC_CH_B_CFG1_REG(base) = (ADC_CH_B_CFG1_REG(base) & ~ADC_CH_B_CFG1_CHB_TIMER_MASK) | \ in ADC_SetConvertRate()
303 ADC_CH_C_CFG1_REG(base) = (ADC_CH_C_CFG1_REG(base) & ~ADC_CH_C_CFG1_CHC_TIMER_MASK) | \ in ADC_SetConvertRate()
307 ADC_CH_D_CFG1_REG(base) = (ADC_CH_D_CFG1_REG(base) & ~ADC_CH_D_CFG1_CHD_TIMER_MASK) | \ in ADC_SetConvertRate()
322 void ADC_SetAverageCmd(ADC_Type* base, uint8_t logicCh, bool enable) in ADC_SetAverageCmd() argument
331 ADC_CH_A_CFG1_REG(base) |= ADC_CH_A_CFG1_CHA_AVG_EN_MASK; in ADC_SetAverageCmd()
334 ADC_CH_B_CFG1_REG(base) |= ADC_CH_B_CFG1_CHB_AVG_EN_MASK; in ADC_SetAverageCmd()
337 ADC_CH_C_CFG1_REG(base) |= ADC_CH_C_CFG1_CHC_AVG_EN_MASK; in ADC_SetAverageCmd()
340 ADC_CH_D_CFG1_REG(base) |= ADC_CH_D_CFG1_CHD_AVG_EN_MASK; in ADC_SetAverageCmd()
343 ADC_CH_SW_CFG_REG(base) |= ADC_CH_SW_CFG_CH_SW_AVG_EN_MASK; in ADC_SetAverageCmd()
354 ADC_CH_A_CFG1_REG(base) &= ~ADC_CH_A_CFG1_CHA_AVG_EN_MASK; in ADC_SetAverageCmd()
357 ADC_CH_B_CFG1_REG(base) &= ~ADC_CH_B_CFG1_CHB_AVG_EN_MASK; in ADC_SetAverageCmd()
360 ADC_CH_C_CFG1_REG(base) &= ~ADC_CH_C_CFG1_CHC_AVG_EN_MASK; in ADC_SetAverageCmd()
363 ADC_CH_D_CFG1_REG(base) &= ~ADC_CH_D_CFG1_CHD_AVG_EN_MASK; in ADC_SetAverageCmd()
366 ADC_CH_SW_CFG_REG(base) &= ~ADC_CH_SW_CFG_CH_SW_AVG_EN_MASK; in ADC_SetAverageCmd()
380 void ADC_SetAverageNum(ADC_Type* base, uint8_t logicCh, uint8_t avgNum) in ADC_SetAverageNum() argument
388 … ADC_CH_A_CFG2_REG(base) = (ADC_CH_A_CFG2_REG(base) & ~ADC_CH_A_CFG2_CHA_AVG_NUMBER_MASK) | \ in ADC_SetAverageNum()
392 … ADC_CH_B_CFG2_REG(base) = (ADC_CH_B_CFG2_REG(base) & ~ADC_CH_B_CFG2_CHB_AVG_NUMBER_MASK) | \ in ADC_SetAverageNum()
396 … ADC_CH_C_CFG2_REG(base) = (ADC_CH_C_CFG2_REG(base) & ~ADC_CH_C_CFG2_CHC_AVG_NUMBER_MASK) | \ in ADC_SetAverageNum()
400 … ADC_CH_D_CFG2_REG(base) = (ADC_CH_D_CFG2_REG(base) & ~ADC_CH_D_CFG2_CHD_AVG_NUMBER_MASK) | \ in ADC_SetAverageNum()
404 … ADC_CH_SW_CFG_REG(base) = (ADC_CH_SW_CFG_REG(base) & ~ADC_CH_SW_CFG_CH_SW_AVG_NUMBER_MASK) | \ in ADC_SetAverageNum()
421 void ADC_SetConvertCmd(ADC_Type* base, uint8_t logicCh, bool enable) in ADC_SetConvertCmd() argument
430 … ADC_CH_A_CFG1_REG(base) = (ADC_CH_A_CFG1_REG(base) & ~ADC_CH_A_CFG1_CHA_SINGLE_MASK) | in ADC_SetConvertCmd()
434 … ADC_CH_B_CFG1_REG(base) = (ADC_CH_B_CFG1_REG(base) & ~ADC_CH_B_CFG1_CHB_SINGLE_MASK) | in ADC_SetConvertCmd()
438 … ADC_CH_C_CFG1_REG(base) = (ADC_CH_C_CFG1_REG(base) & ~ADC_CH_C_CFG1_CHC_SINGLE_MASK) | in ADC_SetConvertCmd()
442 … ADC_CH_D_CFG1_REG(base) = (ADC_CH_D_CFG1_REG(base) & ~ADC_CH_D_CFG1_CHD_SINGLE_MASK) | in ADC_SetConvertCmd()
454 ADC_CH_A_CFG1_REG(base) &= ~ADC_CH_A_CFG1_CHA_EN_MASK; in ADC_SetConvertCmd()
457 ADC_CH_B_CFG1_REG(base) &= ~ADC_CH_B_CFG1_CHB_EN_MASK; in ADC_SetConvertCmd()
460 ADC_CH_C_CFG1_REG(base) &= ~ADC_CH_C_CFG1_CHC_EN_MASK; in ADC_SetConvertCmd()
463 ADC_CH_D_CFG1_REG(base) &= ~ADC_CH_D_CFG1_CHD_EN_MASK; in ADC_SetConvertCmd()
477 void ADC_TriggerSingleConvert(ADC_Type* base, uint8_t logicCh) in ADC_TriggerSingleConvert() argument
484 ADC_CH_A_CFG1_REG(base) |= ADC_CH_A_CFG1_CHA_SINGLE_MASK | ADC_CH_A_CFG1_CHA_EN_MASK; in ADC_TriggerSingleConvert()
487 ADC_CH_B_CFG1_REG(base) |= ADC_CH_B_CFG1_CHB_SINGLE_MASK | ADC_CH_B_CFG1_CHB_EN_MASK; in ADC_TriggerSingleConvert()
490 ADC_CH_C_CFG1_REG(base) |= ADC_CH_C_CFG1_CHC_SINGLE_MASK | ADC_CH_C_CFG1_CHC_EN_MASK; in ADC_TriggerSingleConvert()
493 ADC_CH_D_CFG1_REG(base) |= ADC_CH_D_CFG1_CHD_SINGLE_MASK | ADC_CH_D_CFG1_CHD_EN_MASK; in ADC_TriggerSingleConvert()
496 ADC_CH_SW_CFG_REG(base) |= ADC_CH_SW_CFG_START_CONV_MASK; in ADC_TriggerSingleConvert()
509 void ADC_StopConvert(ADC_Type* base, uint8_t logicCh) in ADC_StopConvert() argument
516 ADC_CH_A_CFG1_REG(base) &= ~ADC_CH_A_CFG1_CHA_EN_MASK; in ADC_StopConvert()
519 ADC_CH_B_CFG1_REG(base) &= ~ADC_CH_B_CFG1_CHB_EN_MASK; in ADC_StopConvert()
522 ADC_CH_C_CFG1_REG(base) &= ~ADC_CH_C_CFG1_CHC_EN_MASK; in ADC_StopConvert()
525 ADC_CH_D_CFG1_REG(base) &= ~ADC_CH_D_CFG1_CHD_EN_MASK; in ADC_StopConvert()
529 while (ADC_CH_SW_CFG_REG(base) & ADC_CH_SW_CFG_START_CONV_MASK); in ADC_StopConvert()
542 uint16_t ADC_GetConvertResult(ADC_Type* base, uint8_t logicCh) in ADC_GetConvertResult() argument
549 return ADC_CHA_B_CNV_RSLT_REG(base) & ADC_CHA_B_CNV_RSLT_CHA_CNV_RSLT_MASK; in ADC_GetConvertResult()
551 return ADC_CHA_B_CNV_RSLT_REG(base) >> ADC_CHA_B_CNV_RSLT_CHB_CNV_RSLT_SHIFT; in ADC_GetConvertResult()
553 return ADC_CHC_D_CNV_RSLT_REG(base) & ADC_CHC_D_CNV_RSLT_CHC_CNV_RSLT_MASK; in ADC_GetConvertResult()
555 return ADC_CHC_D_CNV_RSLT_REG(base) >> ADC_CHC_D_CNV_RSLT_CHD_CNV_RSLT_SHIFT; in ADC_GetConvertResult()
557 return ADC_CH_SW_CNV_RSLT_REG(base) & ADC_CH_SW_CNV_RSLT_CH_SW_CNV_RSLT_MASK; in ADC_GetConvertResult()
573 void ADC_SetCmpMode(ADC_Type* base, uint8_t logicCh, uint8_t cmpMode) in ADC_SetCmpMode() argument
581 … ADC_CH_A_CFG2_REG(base) = (ADC_CH_A_CFG2_REG(base) & ~ADC_CH_A_CFG2_CHA_CMP_MODE_MASK) | \ in ADC_SetCmpMode()
585 … ADC_CH_B_CFG2_REG(base) = (ADC_CH_B_CFG2_REG(base) & ~ADC_CH_B_CFG2_CHB_CMP_MODE_MASK) | \ in ADC_SetCmpMode()
589 … ADC_CH_C_CFG2_REG(base) = (ADC_CH_C_CFG2_REG(base) & ~ADC_CH_C_CFG2_CHC_CMP_MODE_MASK) | \ in ADC_SetCmpMode()
593 … ADC_CH_D_CFG2_REG(base) = (ADC_CH_D_CFG2_REG(base) & ~ADC_CH_D_CFG2_CHD_CMP_MODE_MASK) | \ in ADC_SetCmpMode()
608 void ADC_SetCmpHighThres(ADC_Type* base, uint8_t logicCh, uint16_t threshold) in ADC_SetCmpHighThres() argument
616 … ADC_CH_A_CFG2_REG(base) = (ADC_CH_A_CFG2_REG(base) & ~ADC_CH_A_CFG2_CHA_HIGH_THRES_MASK) | \ in ADC_SetCmpHighThres()
620 … ADC_CH_B_CFG2_REG(base) = (ADC_CH_B_CFG2_REG(base) & ~ADC_CH_B_CFG2_CHB_HIGH_THRES_MASK) | \ in ADC_SetCmpHighThres()
624 … ADC_CH_C_CFG2_REG(base) = (ADC_CH_C_CFG2_REG(base) & ~ADC_CH_C_CFG2_CHC_HIGH_THRES_MASK) | \ in ADC_SetCmpHighThres()
628 … ADC_CH_D_CFG2_REG(base) = (ADC_CH_D_CFG2_REG(base) & ~ADC_CH_D_CFG2_CHD_HIGH_THRES_MASK) | \ in ADC_SetCmpHighThres()
643 void ADC_SetCmpLowThres(ADC_Type* base, uint8_t logicCh, uint16_t threshold) in ADC_SetCmpLowThres() argument
651 … ADC_CH_A_CFG2_REG(base) = (ADC_CH_A_CFG2_REG(base) & ~ADC_CH_A_CFG2_CHA_LOW_THRES_MASK) | \ in ADC_SetCmpLowThres()
655 … ADC_CH_B_CFG2_REG(base) = (ADC_CH_B_CFG2_REG(base) & ~ADC_CH_B_CFG2_CHB_LOW_THRES_MASK) | \ in ADC_SetCmpLowThres()
659 … ADC_CH_C_CFG2_REG(base) = (ADC_CH_C_CFG2_REG(base) & ~ADC_CH_C_CFG2_CHC_LOW_THRES_MASK) | \ in ADC_SetCmpLowThres()
663 … ADC_CH_D_CFG2_REG(base) = (ADC_CH_D_CFG2_REG(base) & ~ADC_CH_D_CFG2_CHD_LOW_THRES_MASK) | \ in ADC_SetCmpLowThres()
678 void ADC_SetAutoDisableCmd(ADC_Type* base, uint8_t logicCh, bool enable) in ADC_SetAutoDisableCmd() argument
687 ADC_CH_A_CFG2_REG(base) |= ADC_CH_A_CFG2_CHA_AUTO_DIS_MASK; in ADC_SetAutoDisableCmd()
690 ADC_CH_B_CFG2_REG(base) |= ADC_CH_B_CFG2_CHB_AUTO_DIS_MASK; in ADC_SetAutoDisableCmd()
693 ADC_CH_C_CFG2_REG(base) |= ADC_CH_C_CFG2_CHC_AUTO_DIS_MASK; in ADC_SetAutoDisableCmd()
696 ADC_CH_D_CFG2_REG(base) |= ADC_CH_D_CFG2_CHD_AUTO_DIS_MASK; in ADC_SetAutoDisableCmd()
707 ADC_CH_A_CFG2_REG(base) &= ~ADC_CH_A_CFG2_CHA_AUTO_DIS_MASK; in ADC_SetAutoDisableCmd()
710 ADC_CH_B_CFG2_REG(base) &= ~ADC_CH_B_CFG2_CHB_AUTO_DIS_MASK; in ADC_SetAutoDisableCmd()
713 ADC_CH_C_CFG2_REG(base) &= ~ADC_CH_C_CFG2_CHC_AUTO_DIS_MASK; in ADC_SetAutoDisableCmd()
716 ADC_CH_D_CFG2_REG(base) &= ~ADC_CH_D_CFG2_CHD_AUTO_DIS_MASK; in ADC_SetAutoDisableCmd()
733 void ADC_SetIntCmd(ADC_Type* base, uint32_t intSource, bool enable) in ADC_SetIntCmd() argument
736 ADC_INT_EN_REG(base) |= intSource; in ADC_SetIntCmd()
738 ADC_INT_EN_REG(base) &= ~intSource; in ADC_SetIntCmd()
748 void ADC_SetIntSigCmd(ADC_Type* base, uint32_t intSignal, bool enable) in ADC_SetIntSigCmd() argument
751 ADC_INT_SIG_EN_REG(base) |= intSignal; in ADC_SetIntSigCmd()
753 ADC_INT_SIG_EN_REG(base) &= ~intSignal; in ADC_SetIntSigCmd()
765 void ADC_SetDmaReset(ADC_Type* base, bool active) in ADC_SetDmaReset() argument
768 ADC_DMA_FIFO_REG(base) |= ADC_DMA_FIFO_DMA_RST_MASK; in ADC_SetDmaReset()
770 ADC_DMA_FIFO_REG(base) &= ~ADC_DMA_FIFO_DMA_RST_MASK; in ADC_SetDmaReset()
779 void ADC_SetDmaCmd(ADC_Type* base, bool enable) in ADC_SetDmaCmd() argument
782 ADC_DMA_FIFO_REG(base) |= ADC_DMA_FIFO_DMA_EN_MASK; in ADC_SetDmaCmd()
784 ADC_DMA_FIFO_REG(base) &= ~ADC_DMA_FIFO_DMA_EN_MASK; in ADC_SetDmaCmd()
793 void ADC_SetDmaFifoCmd(ADC_Type* base, bool enable) in ADC_SetDmaFifoCmd() argument
796 ADC_DMA_FIFO_REG(base) |= ADC_DMA_FIFO_DMA_FIFO_EN_MASK; in ADC_SetDmaFifoCmd()
798 ADC_DMA_FIFO_REG(base) &= ~ADC_DMA_FIFO_DMA_FIFO_EN_MASK; in ADC_SetDmaFifoCmd()