Lines Matching refs:IOMUXC_BASE_PTR
26059 #define IOMUXC_BASE_PTR (IOMUXC) macro
26076 …fine IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_REG(IOMUXC_BASE_PTR)
26077 …fine IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_REG(IOMUXC_BASE_PTR)
26078 …fine IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_REG(IOMUXC_BASE_PTR)
26079 …fine IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_REG(IOMUXC_BASE_PTR)
26080 …fine IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_REG(IOMUXC_BASE_PTR)
26081 …fine IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_REG(IOMUXC_BASE_PTR)
26082 …fine IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_REG(IOMUXC_BASE_PTR)
26083 …fine IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15_REG(IOMUXC_BASE_PTR)
26084 …ine IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA00 IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA00_REG(IOMUXC_BASE_PTR)
26085 …ine IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA01 IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA01_REG(IOMUXC_BASE_PTR)
26086 …ine IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA02 IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA02_REG(IOMUXC_BASE_PTR)
26087 …ine IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA03 IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA03_REG(IOMUXC_BASE_PTR)
26088 …ine IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA04 IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA04_REG(IOMUXC_BASE_PTR)
26089 …ine IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA05 IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA05_REG(IOMUXC_BASE_PTR)
26090 …ine IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA06 IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA06_REG(IOMUXC_BASE_PTR)
26091 …ine IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA07 IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA07_REG(IOMUXC_BASE_PTR)
26092 …ine IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA08 IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA08_REG(IOMUXC_BASE_PTR)
26093 …ine IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA09 IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA09_REG(IOMUXC_BASE_PTR)
26094 …ine IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA10 IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA10_REG(IOMUXC_BASE_PTR)
26095 …ine IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA11 IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA11_REG(IOMUXC_BASE_PTR)
26096 …ine IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA12 IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA12_REG(IOMUXC_BASE_PTR)
26097 …ine IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA13 IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA13_REG(IOMUXC_BASE_PTR)
26098 …ine IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA14 IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA14_REG(IOMUXC_BASE_PTR)
26099 …ine IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA15 IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA15_REG(IOMUXC_BASE_PTR)
26100 …fine IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCLK IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCLK_REG(IOMUXC_BASE_PTR)
26101 …efine IOMUXC_SW_MUX_CTL_PAD_EPDC_SDLE IOMUXC_SW_MUX_CTL_PAD_EPDC_SDLE_REG(IOMUXC_BASE_PTR)
26102 …efine IOMUXC_SW_MUX_CTL_PAD_EPDC_SDOE IOMUXC_SW_MUX_CTL_PAD_EPDC_SDOE_REG(IOMUXC_BASE_PTR)
26103 …fine IOMUXC_SW_MUX_CTL_PAD_EPDC_SDSHR IOMUXC_SW_MUX_CTL_PAD_EPDC_SDSHR_REG(IOMUXC_BASE_PTR)
26104 …fine IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE0 IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE0_REG(IOMUXC_BASE_PTR)
26105 …fine IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE1 IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE1_REG(IOMUXC_BASE_PTR)
26106 …fine IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE2 IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE2_REG(IOMUXC_BASE_PTR)
26107 …fine IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE3 IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE3_REG(IOMUXC_BASE_PTR)
26108 …fine IOMUXC_SW_MUX_CTL_PAD_EPDC_GDCLK IOMUXC_SW_MUX_CTL_PAD_EPDC_GDCLK_REG(IOMUXC_BASE_PTR)
26109 …efine IOMUXC_SW_MUX_CTL_PAD_EPDC_GDOE IOMUXC_SW_MUX_CTL_PAD_EPDC_GDOE_REG(IOMUXC_BASE_PTR)
26110 …efine IOMUXC_SW_MUX_CTL_PAD_EPDC_GDRL IOMUXC_SW_MUX_CTL_PAD_EPDC_GDRL_REG(IOMUXC_BASE_PTR)
26111 …efine IOMUXC_SW_MUX_CTL_PAD_EPDC_GDSP IOMUXC_SW_MUX_CTL_PAD_EPDC_GDSP_REG(IOMUXC_BASE_PTR)
26112 …efine IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR0 IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR0_REG(IOMUXC_BASE_PTR)
26113 …efine IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR1 IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR1_REG(IOMUXC_BASE_PTR)
26114 …ne IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_COM IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_COM_REG(IOMUXC_BASE_PTR)
26115 …e IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_STAT IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_STAT_REG(IOMUXC_BASE_PTR)
26116 #define IOMUXC_SW_MUX_CTL_PAD_LCD_CLK IOMUXC_SW_MUX_CTL_PAD_LCD_CLK_REG(IOMUXC_BASE_PTR)
26117 …fine IOMUXC_SW_MUX_CTL_PAD_LCD_ENABLE IOMUXC_SW_MUX_CTL_PAD_LCD_ENABLE_REG(IOMUXC_BASE_PTR)
26118 …efine IOMUXC_SW_MUX_CTL_PAD_LCD_HSYNC IOMUXC_SW_MUX_CTL_PAD_LCD_HSYNC_REG(IOMUXC_BASE_PTR)
26119 …efine IOMUXC_SW_MUX_CTL_PAD_LCD_VSYNC IOMUXC_SW_MUX_CTL_PAD_LCD_VSYNC_REG(IOMUXC_BASE_PTR)
26120 …efine IOMUXC_SW_MUX_CTL_PAD_LCD_RESET IOMUXC_SW_MUX_CTL_PAD_LCD_RESET_REG(IOMUXC_BASE_PTR)
26121 …fine IOMUXC_SW_MUX_CTL_PAD_LCD_DATA00 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA00_REG(IOMUXC_BASE_PTR)
26122 …fine IOMUXC_SW_MUX_CTL_PAD_LCD_DATA01 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA01_REG(IOMUXC_BASE_PTR)
26123 …fine IOMUXC_SW_MUX_CTL_PAD_LCD_DATA02 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA02_REG(IOMUXC_BASE_PTR)
26124 …fine IOMUXC_SW_MUX_CTL_PAD_LCD_DATA03 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA03_REG(IOMUXC_BASE_PTR)
26125 …fine IOMUXC_SW_MUX_CTL_PAD_LCD_DATA04 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA04_REG(IOMUXC_BASE_PTR)
26126 …fine IOMUXC_SW_MUX_CTL_PAD_LCD_DATA05 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA05_REG(IOMUXC_BASE_PTR)
26127 …fine IOMUXC_SW_MUX_CTL_PAD_LCD_DATA06 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA06_REG(IOMUXC_BASE_PTR)
26128 …fine IOMUXC_SW_MUX_CTL_PAD_LCD_DATA07 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA07_REG(IOMUXC_BASE_PTR)
26129 …fine IOMUXC_SW_MUX_CTL_PAD_LCD_DATA08 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA08_REG(IOMUXC_BASE_PTR)
26130 …fine IOMUXC_SW_MUX_CTL_PAD_LCD_DATA09 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA09_REG(IOMUXC_BASE_PTR)
26131 …fine IOMUXC_SW_MUX_CTL_PAD_LCD_DATA10 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA10_REG(IOMUXC_BASE_PTR)
26132 …fine IOMUXC_SW_MUX_CTL_PAD_LCD_DATA11 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA11_REG(IOMUXC_BASE_PTR)
26133 …fine IOMUXC_SW_MUX_CTL_PAD_LCD_DATA12 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA12_REG(IOMUXC_BASE_PTR)
26134 …fine IOMUXC_SW_MUX_CTL_PAD_LCD_DATA13 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA13_REG(IOMUXC_BASE_PTR)
26135 …fine IOMUXC_SW_MUX_CTL_PAD_LCD_DATA14 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA14_REG(IOMUXC_BASE_PTR)
26136 …fine IOMUXC_SW_MUX_CTL_PAD_LCD_DATA15 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA15_REG(IOMUXC_BASE_PTR)
26137 …fine IOMUXC_SW_MUX_CTL_PAD_LCD_DATA16 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA16_REG(IOMUXC_BASE_PTR)
26138 …fine IOMUXC_SW_MUX_CTL_PAD_LCD_DATA17 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA17_REG(IOMUXC_BASE_PTR)
26139 …fine IOMUXC_SW_MUX_CTL_PAD_LCD_DATA18 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA18_REG(IOMUXC_BASE_PTR)
26140 …fine IOMUXC_SW_MUX_CTL_PAD_LCD_DATA19 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA19_REG(IOMUXC_BASE_PTR)
26141 …fine IOMUXC_SW_MUX_CTL_PAD_LCD_DATA20 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA20_REG(IOMUXC_BASE_PTR)
26142 …fine IOMUXC_SW_MUX_CTL_PAD_LCD_DATA21 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA21_REG(IOMUXC_BASE_PTR)
26143 …fine IOMUXC_SW_MUX_CTL_PAD_LCD_DATA22 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA22_REG(IOMUXC_BASE_PTR)
26144 …fine IOMUXC_SW_MUX_CTL_PAD_LCD_DATA23 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA23_REG(IOMUXC_BASE_PTR)
26145 …e IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_REG(IOMUXC_BASE_PTR)
26146 …e IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_REG(IOMUXC_BASE_PTR)
26147 …e IOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA IOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA_REG(IOMUXC_BASE_PTR)
26148 …e IOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA IOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA_REG(IOMUXC_BASE_PTR)
26149 …e IOMUXC_SW_MUX_CTL_PAD_UART3_RX_DATA IOMUXC_SW_MUX_CTL_PAD_UART3_RX_DATA_REG(IOMUXC_BASE_PTR)
26150 …e IOMUXC_SW_MUX_CTL_PAD_UART3_TX_DATA IOMUXC_SW_MUX_CTL_PAD_UART3_TX_DATA_REG(IOMUXC_BASE_PTR)
26151 …ine IOMUXC_SW_MUX_CTL_PAD_UART3_RTS_B IOMUXC_SW_MUX_CTL_PAD_UART3_RTS_B_REG(IOMUXC_BASE_PTR)
26152 …ine IOMUXC_SW_MUX_CTL_PAD_UART3_CTS_B IOMUXC_SW_MUX_CTL_PAD_UART3_CTS_B_REG(IOMUXC_BASE_PTR)
26153 #define IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL_REG(IOMUXC_BASE_PTR)
26154 #define IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA_REG(IOMUXC_BASE_PTR)
26155 #define IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL_REG(IOMUXC_BASE_PTR)
26156 #define IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA_REG(IOMUXC_BASE_PTR)
26157 #define IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL_REG(IOMUXC_BASE_PTR)
26158 #define IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA_REG(IOMUXC_BASE_PTR)
26159 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_REG(IOMUXC_BASE_PTR)
26160 #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_REG(IOMUXC_BASE_PTR)
26161 …ine IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_REG(IOMUXC_BASE_PTR)
26162 …ine IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_REG(IOMUXC_BASE_PTR)
26163 …ine IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO_REG(IOMUXC_BASE_PTR)
26164 …fine IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0 IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0_REG(IOMUXC_BASE_PTR)
26165 …ine IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK_REG(IOMUXC_BASE_PTR)
26166 …ine IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI_REG(IOMUXC_BASE_PTR)
26167 …ine IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO_REG(IOMUXC_BASE_PTR)
26168 …fine IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0 IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0_REG(IOMUXC_BASE_PTR)
26169 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CD_B IOMUXC_SW_MUX_CTL_PAD_SD1_CD_B_REG(IOMUXC_BASE_PTR)
26170 #define IOMUXC_SW_MUX_CTL_PAD_SD1_WP IOMUXC_SW_MUX_CTL_PAD_SD1_WP_REG(IOMUXC_BASE_PTR)
26171 …ine IOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B IOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B_REG(IOMUXC_BASE_PTR)
26172 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_REG(IOMUXC_BASE_PTR)
26173 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_REG(IOMUXC_BASE_PTR)
26174 …efine IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_REG(IOMUXC_BASE_PTR)
26175 …efine IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_REG(IOMUXC_BASE_PTR)
26176 …efine IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_REG(IOMUXC_BASE_PTR)
26177 …efine IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_REG(IOMUXC_BASE_PTR)
26178 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CD_B IOMUXC_SW_MUX_CTL_PAD_SD2_CD_B_REG(IOMUXC_BASE_PTR)
26179 #define IOMUXC_SW_MUX_CTL_PAD_SD2_WP IOMUXC_SW_MUX_CTL_PAD_SD2_WP_REG(IOMUXC_BASE_PTR)
26180 …ine IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B_REG(IOMUXC_BASE_PTR)
26181 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_REG(IOMUXC_BASE_PTR)
26182 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_REG(IOMUXC_BASE_PTR)
26183 …efine IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0 IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_REG(IOMUXC_BASE_PTR)
26184 …efine IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1 IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_REG(IOMUXC_BASE_PTR)
26185 …efine IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2 IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_REG(IOMUXC_BASE_PTR)
26186 …efine IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3 IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_REG(IOMUXC_BASE_PTR)
26187 #define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_REG(IOMUXC_BASE_PTR)
26188 #define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_REG(IOMUXC_BASE_PTR)
26189 …efine IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0 IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_REG(IOMUXC_BASE_PTR)
26190 …efine IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1 IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_REG(IOMUXC_BASE_PTR)
26191 …efine IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2 IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_REG(IOMUXC_BASE_PTR)
26192 …efine IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3 IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_REG(IOMUXC_BASE_PTR)
26193 …efine IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4 IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_REG(IOMUXC_BASE_PTR)
26194 …efine IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5 IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_REG(IOMUXC_BASE_PTR)
26195 …efine IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6 IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_REG(IOMUXC_BASE_PTR)
26196 …efine IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7 IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_REG(IOMUXC_BASE_PTR)
26197 …fine IOMUXC_SW_MUX_CTL_PAD_SD3_STROBE IOMUXC_SW_MUX_CTL_PAD_SD3_STROBE_REG(IOMUXC_BASE_PTR)
26198 …ine IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_B IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_B_REG(IOMUXC_BASE_PTR)
26199 …ne IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_DATA IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_DATA_REG(IOMUXC_BASE_PTR)
26200 …ne IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_BCLK IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_BCLK_REG(IOMUXC_BASE_PTR)
26201 …ne IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_SYNC IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_SYNC_REG(IOMUXC_BASE_PTR)
26202 …ne IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_DATA IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_DATA_REG(IOMUXC_BASE_PTR)
26203 …ne IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_SYNC IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_SYNC_REG(IOMUXC_BASE_PTR)
26204 …ne IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_BCLK IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_BCLK_REG(IOMUXC_BASE_PTR)
26205 …efine IOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK IOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK_REG(IOMUXC_BASE_PTR)
26206 …ne IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_SYNC IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_SYNC_REG(IOMUXC_BASE_PTR)
26207 …ne IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_BCLK IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_BCLK_REG(IOMUXC_BASE_PTR)
26208 …ne IOMUXC_SW_MUX_CTL_PAD_SAI2_RX_DATA IOMUXC_SW_MUX_CTL_PAD_SAI2_RX_DATA_REG(IOMUXC_BASE_PTR)
26209 …ne IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_DATA IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_DATA_REG(IOMUXC_BASE_PTR)
26210 …IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD0 IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD0_REG(IOMUXC_BASE_PTR)
26211 …IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD1 IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD1_REG(IOMUXC_BASE_PTR)
26212 …IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD2 IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD2_REG(IOMUXC_BASE_PTR)
26213 …IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD3 IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD3_REG(IOMUXC_BASE_PTR)
26214 …UXC_SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL_REG(IOMUXC_BASE_PTR)
26215 …IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RXC IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RXC_REG(IOMUXC_BASE_PTR)
26216 …IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD0 IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD0_REG(IOMUXC_BASE_PTR)
26217 …IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD1 IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD1_REG(IOMUXC_BASE_PTR)
26218 …IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD2 IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD2_REG(IOMUXC_BASE_PTR)
26219 …IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD3 IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD3_REG(IOMUXC_BASE_PTR)
26220 …UXC_SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL_REG(IOMUXC_BASE_PTR)
26221 …IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TXC IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TXC_REG(IOMUXC_BASE_PTR)
26222 …ne IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_REG(IOMUXC_BASE_PTR)
26223 …ne IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_REG(IOMUXC_BASE_PTR)
26224 …efine IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_REG(IOMUXC_BASE_PTR)
26225 …efine IOMUXC_SW_MUX_CTL_PAD_ENET1_COL IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_REG(IOMUXC_BASE_PTR)
26226 …fine IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_REG(IOMUXC_BASE_PTR)
26227 …fine IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_REG(IOMUXC_BASE_PTR)
26228 …fine IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_REG(IOMUXC_BASE_PTR)
26229 …fine IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_REG(IOMUXC_BASE_PTR)
26230 …fine IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_REG(IOMUXC_BASE_PTR)
26231 …fine IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_REG(IOMUXC_BASE_PTR)
26232 …fine IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_REG(IOMUXC_BASE_PTR)
26233 …fine IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_REG(IOMUXC_BASE_PTR)
26234 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_REG(IOMUXC_BASE_PTR)
26235 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_REG(IOMUXC_BASE_PTR)
26236 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_REG(IOMUXC_BASE_PTR)
26237 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_REG(IOMUXC_BASE_PTR)
26238 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_REG(IOMUXC_BASE_PTR)
26239 …ine IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_REG(IOMUXC_BASE_PTR)
26240 …ine IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00 IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_REG(IOMUXC_BASE_PTR)
26241 …ine IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01 IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_REG(IOMUXC_BASE_PTR)
26242 …ine IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02 IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_REG(IOMUXC_BASE_PTR)
26243 …ine IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03 IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_REG(IOMUXC_BASE_PTR)
26244 …ine IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04 IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_REG(IOMUXC_BASE_PTR)
26245 …ine IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05 IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_REG(IOMUXC_BASE_PTR)
26246 …ine IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06 IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_REG(IOMUXC_BASE_PTR)
26247 …ine IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07 IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_REG(IOMUXC_BASE_PTR)
26248 …ine IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08 IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_REG(IOMUXC_BASE_PTR)
26249 …ine IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09 IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_REG(IOMUXC_BASE_PTR)
26250 …ine IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10 IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_REG(IOMUXC_BASE_PTR)
26251 …ine IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11 IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_REG(IOMUXC_BASE_PTR)
26252 …ine IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12 IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_REG(IOMUXC_BASE_PTR)
26253 …ine IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13 IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_REG(IOMUXC_BASE_PTR)
26254 …ine IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14 IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_REG(IOMUXC_BASE_PTR)
26255 …ine IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15 IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_REG(IOMUXC_BASE_PTR)
26256 …fine IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_REG(IOMUXC_BASE_PTR)
26257 …efine IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_REG(IOMUXC_BASE_PTR)
26258 …efine IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_REG(IOMUXC_BASE_PTR)
26259 …fine IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_REG(IOMUXC_BASE_PTR)
26260 …fine IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0 IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_REG(IOMUXC_BASE_PTR)
26261 …fine IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1 IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_REG(IOMUXC_BASE_PTR)
26262 …fine IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2 IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_REG(IOMUXC_BASE_PTR)
26263 …fine IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3 IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_REG(IOMUXC_BASE_PTR)
26264 …fine IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_REG(IOMUXC_BASE_PTR)
26265 …efine IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_REG(IOMUXC_BASE_PTR)
26266 …efine IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_REG(IOMUXC_BASE_PTR)
26267 …efine IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_REG(IOMUXC_BASE_PTR)
26268 …efine IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0 IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_REG(IOMUXC_BASE_PTR)
26269 …efine IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1 IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_REG(IOMUXC_BASE_PTR)
26270 …ne IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_REG(IOMUXC_BASE_PTR)
26271 …e IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_REG(IOMUXC_BASE_PTR)
26272 #define IOMUXC_SW_PAD_CTL_PAD_LCD_CLK IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_REG(IOMUXC_BASE_PTR)
26273 …fine IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_REG(IOMUXC_BASE_PTR)
26274 …efine IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_REG(IOMUXC_BASE_PTR)
26275 …efine IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_REG(IOMUXC_BASE_PTR)
26276 …efine IOMUXC_SW_PAD_CTL_PAD_LCD_RESET IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_REG(IOMUXC_BASE_PTR)
26277 …fine IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_REG(IOMUXC_BASE_PTR)
26278 …fine IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_REG(IOMUXC_BASE_PTR)
26279 …fine IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_REG(IOMUXC_BASE_PTR)
26280 …fine IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_REG(IOMUXC_BASE_PTR)
26281 …fine IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_REG(IOMUXC_BASE_PTR)
26282 …fine IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_REG(IOMUXC_BASE_PTR)
26283 …fine IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_REG(IOMUXC_BASE_PTR)
26284 …fine IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_REG(IOMUXC_BASE_PTR)
26285 …fine IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_REG(IOMUXC_BASE_PTR)
26286 …fine IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_REG(IOMUXC_BASE_PTR)
26287 …fine IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_REG(IOMUXC_BASE_PTR)
26288 …fine IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_REG(IOMUXC_BASE_PTR)
26289 …fine IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_REG(IOMUXC_BASE_PTR)
26290 …fine IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_REG(IOMUXC_BASE_PTR)
26291 …fine IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_REG(IOMUXC_BASE_PTR)
26292 …fine IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_REG(IOMUXC_BASE_PTR)
26293 …fine IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_REG(IOMUXC_BASE_PTR)
26294 …fine IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_REG(IOMUXC_BASE_PTR)
26295 …fine IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_REG(IOMUXC_BASE_PTR)
26296 …fine IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_REG(IOMUXC_BASE_PTR)
26297 …fine IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_REG(IOMUXC_BASE_PTR)
26298 …fine IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_REG(IOMUXC_BASE_PTR)
26299 …fine IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_REG(IOMUXC_BASE_PTR)
26300 …fine IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_REG(IOMUXC_BASE_PTR)
26301 …e IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_REG(IOMUXC_BASE_PTR)
26302 …e IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_REG(IOMUXC_BASE_PTR)
26303 …e IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_REG(IOMUXC_BASE_PTR)
26304 …e IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_REG(IOMUXC_BASE_PTR)
26305 …e IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_REG(IOMUXC_BASE_PTR)
26306 …e IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_REG(IOMUXC_BASE_PTR)
26307 …ine IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_REG(IOMUXC_BASE_PTR)
26308 …ine IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_REG(IOMUXC_BASE_PTR)
26309 #define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_REG(IOMUXC_BASE_PTR)
26310 #define IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_REG(IOMUXC_BASE_PTR)
26311 #define IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_REG(IOMUXC_BASE_PTR)
26312 #define IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_REG(IOMUXC_BASE_PTR)
26313 #define IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_REG(IOMUXC_BASE_PTR)
26314 #define IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_REG(IOMUXC_BASE_PTR)
26315 #define IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_REG(IOMUXC_BASE_PTR)
26316 #define IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_REG(IOMUXC_BASE_PTR)
26317 …ine IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_REG(IOMUXC_BASE_PTR)
26318 …ine IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_REG(IOMUXC_BASE_PTR)
26319 …ine IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_REG(IOMUXC_BASE_PTR)
26320 …fine IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0 IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_REG(IOMUXC_BASE_PTR)
26321 …ine IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_REG(IOMUXC_BASE_PTR)
26322 …ine IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_REG(IOMUXC_BASE_PTR)
26323 …ine IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_REG(IOMUXC_BASE_PTR)
26324 …fine IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0 IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_REG(IOMUXC_BASE_PTR)
26325 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_REG(IOMUXC_BASE_PTR)
26326 #define IOMUXC_SW_PAD_CTL_PAD_SD1_WP IOMUXC_SW_PAD_CTL_PAD_SD1_WP_REG(IOMUXC_BASE_PTR)
26327 …ine IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_REG(IOMUXC_BASE_PTR)
26328 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_REG(IOMUXC_BASE_PTR)
26329 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_REG(IOMUXC_BASE_PTR)
26330 …efine IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0 IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_REG(IOMUXC_BASE_PTR)
26331 …efine IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1 IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_REG(IOMUXC_BASE_PTR)
26332 …efine IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2 IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_REG(IOMUXC_BASE_PTR)
26333 …efine IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3 IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_REG(IOMUXC_BASE_PTR)
26334 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_REG(IOMUXC_BASE_PTR)
26335 #define IOMUXC_SW_PAD_CTL_PAD_SD2_WP IOMUXC_SW_PAD_CTL_PAD_SD2_WP_REG(IOMUXC_BASE_PTR)
26336 …ine IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_REG(IOMUXC_BASE_PTR)
26337 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_REG(IOMUXC_BASE_PTR)
26338 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_REG(IOMUXC_BASE_PTR)
26339 …efine IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0 IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_REG(IOMUXC_BASE_PTR)
26340 …efine IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1 IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_REG(IOMUXC_BASE_PTR)
26341 …efine IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2 IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_REG(IOMUXC_BASE_PTR)
26342 …efine IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3 IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_REG(IOMUXC_BASE_PTR)
26343 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_REG(IOMUXC_BASE_PTR)
26344 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_REG(IOMUXC_BASE_PTR)
26345 …efine IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0 IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_REG(IOMUXC_BASE_PTR)
26346 …efine IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1 IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_REG(IOMUXC_BASE_PTR)
26347 …efine IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2 IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_REG(IOMUXC_BASE_PTR)
26348 …efine IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3 IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_REG(IOMUXC_BASE_PTR)
26349 …efine IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4 IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_REG(IOMUXC_BASE_PTR)
26350 …efine IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5 IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_REG(IOMUXC_BASE_PTR)
26351 …efine IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6 IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_REG(IOMUXC_BASE_PTR)
26352 …efine IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7 IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_REG(IOMUXC_BASE_PTR)
26353 …fine IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_REG(IOMUXC_BASE_PTR)
26354 …ine IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_REG(IOMUXC_BASE_PTR)
26355 …ne IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_REG(IOMUXC_BASE_PTR)
26356 …ne IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_REG(IOMUXC_BASE_PTR)
26357 …ne IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_REG(IOMUXC_BASE_PTR)
26358 …ne IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_REG(IOMUXC_BASE_PTR)
26359 …ne IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_REG(IOMUXC_BASE_PTR)
26360 …ne IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_REG(IOMUXC_BASE_PTR)
26361 …efine IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_REG(IOMUXC_BASE_PTR)
26362 …ne IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_REG(IOMUXC_BASE_PTR)
26363 …ne IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_REG(IOMUXC_BASE_PTR)
26364 …ne IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_REG(IOMUXC_BASE_PTR)
26365 …ne IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_REG(IOMUXC_BASE_PTR)
26366 …IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0 IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_REG(IOMUXC_BASE_PTR)
26367 …IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1 IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_REG(IOMUXC_BASE_PTR)
26368 …IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2 IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_REG(IOMUXC_BASE_PTR)
26369 …IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3 IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_REG(IOMUXC_BASE_PTR)
26370 …UXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_REG(IOMUXC_BASE_PTR)
26371 …IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_REG(IOMUXC_BASE_PTR)
26372 …IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0 IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_REG(IOMUXC_BASE_PTR)
26373 …IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1 IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_REG(IOMUXC_BASE_PTR)
26374 …IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2 IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_REG(IOMUXC_BASE_PTR)
26375 …IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3 IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_REG(IOMUXC_BASE_PTR)
26376 …UXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_REG(IOMUXC_BASE_PTR)
26377 …IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_REG(IOMUXC_BASE_PTR)
26378 …ne IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_REG(IOMUXC_BASE_PTR)
26379 …ne IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_REG(IOMUXC_BASE_PTR)
26380 …efine IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_REG(IOMUXC_BASE_PTR)
26381 …efine IOMUXC_SW_PAD_CTL_PAD_ENET1_COL IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_REG(IOMUXC_BASE_PTR)
26382 …efine IOMUXC_FLEXCAN1_RX_SELECT_INPUT IOMUXC_FLEXCAN1_RX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26383 …efine IOMUXC_FLEXCAN2_RX_SELECT_INPUT IOMUXC_FLEXCAN2_RX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26384 …ine IOMUXC_CCM_EXT_CLK_1_SELECT_INPUT IOMUXC_CCM_EXT_CLK_1_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26385 …ine IOMUXC_CCM_EXT_CLK_2_SELECT_INPUT IOMUXC_CCM_EXT_CLK_2_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26386 …ine IOMUXC_CCM_EXT_CLK_3_SELECT_INPUT IOMUXC_CCM_EXT_CLK_3_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26387 …ine IOMUXC_CCM_EXT_CLK_4_SELECT_INPUT IOMUXC_CCM_EXT_CLK_4_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26388 …ne IOMUXC_CCM_PMIC_READY_SELECT_INPUT IOMUXC_CCM_PMIC_READY_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26389 #define IOMUXC_CSI_DATA2_SELECT_INPUT IOMUXC_CSI_DATA2_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26390 #define IOMUXC_CSI_DATA3_SELECT_INPUT IOMUXC_CSI_DATA3_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26391 #define IOMUXC_CSI_DATA4_SELECT_INPUT IOMUXC_CSI_DATA4_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26392 #define IOMUXC_CSI_DATA5_SELECT_INPUT IOMUXC_CSI_DATA5_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26393 #define IOMUXC_CSI_DATA6_SELECT_INPUT IOMUXC_CSI_DATA6_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26394 #define IOMUXC_CSI_DATA7_SELECT_INPUT IOMUXC_CSI_DATA7_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26395 #define IOMUXC_CSI_DATA8_SELECT_INPUT IOMUXC_CSI_DATA8_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26396 #define IOMUXC_CSI_DATA9_SELECT_INPUT IOMUXC_CSI_DATA9_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26397 #define IOMUXC_CSI_HSYNC_SELECT_INPUT IOMUXC_CSI_HSYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26398 #define IOMUXC_CSI_PIXCLK_SELECT_INPUT IOMUXC_CSI_PIXCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26399 #define IOMUXC_CSI_VSYNC_SELECT_INPUT IOMUXC_CSI_VSYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26400 …efine IOMUXC_ECSPI1_SCLK_SELECT_INPUT IOMUXC_ECSPI1_SCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26401 …efine IOMUXC_ECSPI1_MISO_SELECT_INPUT IOMUXC_ECSPI1_MISO_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26402 …efine IOMUXC_ECSPI1_MOSI_SELECT_INPUT IOMUXC_ECSPI1_MOSI_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26403 …fine IOMUXC_ECSPI1_SS0_B_SELECT_INPUT IOMUXC_ECSPI1_SS0_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26404 …efine IOMUXC_ECSPI2_SCLK_SELECT_INPUT IOMUXC_ECSPI2_SCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26405 …efine IOMUXC_ECSPI2_MISO_SELECT_INPUT IOMUXC_ECSPI2_MISO_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26406 …efine IOMUXC_ECSPI2_MOSI_SELECT_INPUT IOMUXC_ECSPI2_MOSI_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26407 …fine IOMUXC_ECSPI2_SS0_B_SELECT_INPUT IOMUXC_ECSPI2_SS0_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26408 …efine IOMUXC_ECSPI3_SCLK_SELECT_INPUT IOMUXC_ECSPI3_SCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26409 …efine IOMUXC_ECSPI3_MISO_SELECT_INPUT IOMUXC_ECSPI3_MISO_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26410 …efine IOMUXC_ECSPI3_MOSI_SELECT_INPUT IOMUXC_ECSPI3_MOSI_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26411 …fine IOMUXC_ECSPI3_SS0_B_SELECT_INPUT IOMUXC_ECSPI3_SS0_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26412 …efine IOMUXC_ECSPI4_SCLK_SELECT_INPUT IOMUXC_ECSPI4_SCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26413 …efine IOMUXC_ECSPI4_MISO_SELECT_INPUT IOMUXC_ECSPI4_MISO_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26414 …efine IOMUXC_ECSPI4_MOSI_SELECT_INPUT IOMUXC_ECSPI4_MOSI_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26415 …fine IOMUXC_ECSPI4_SS0_B_SELECT_INPUT IOMUXC_ECSPI4_SS0_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26416 …IOMUXC_CCM_ENET1_REF_CLK_SELECT_INPUT IOMUXC_CCM_ENET1_REF_CLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26417 #define IOMUXC_ENET1_MDIO_SELECT_INPUT IOMUXC_ENET1_MDIO_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26418 …fine IOMUXC_ENET1_RX_CLK_SELECT_INPUT IOMUXC_ENET1_RX_CLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26419 …IOMUXC_CCM_ENET2_REF_CLK_SELECT_INPUT IOMUXC_CCM_ENET2_REF_CLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26420 #define IOMUXC_ENET2_MDIO_SELECT_INPUT IOMUXC_ENET2_MDIO_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26421 …fine IOMUXC_ENET2_RX_CLK_SELECT_INPUT IOMUXC_ENET2_RX_CLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26422 …fine IOMUXC_EPDC_PWR_IRQ_SELECT_INPUT IOMUXC_EPDC_PWR_IRQ_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26423 …ine IOMUXC_EPDC_PWR_STAT_SELECT_INPUT IOMUXC_EPDC_PWR_STAT_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26424 …ne IOMUXC_FLEXTIMER1_CH0_SELECT_INPUT IOMUXC_FLEXTIMER1_CH0_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26425 …ne IOMUXC_FLEXTIMER1_CH1_SELECT_INPUT IOMUXC_FLEXTIMER1_CH1_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26426 …ne IOMUXC_FLEXTIMER1_CH2_SELECT_INPUT IOMUXC_FLEXTIMER1_CH2_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26427 …ne IOMUXC_FLEXTIMER1_CH3_SELECT_INPUT IOMUXC_FLEXTIMER1_CH3_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26428 …ne IOMUXC_FLEXTIMER1_CH4_SELECT_INPUT IOMUXC_FLEXTIMER1_CH4_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26429 …ne IOMUXC_FLEXTIMER1_CH5_SELECT_INPUT IOMUXC_FLEXTIMER1_CH5_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26430 …ne IOMUXC_FLEXTIMER1_CH6_SELECT_INPUT IOMUXC_FLEXTIMER1_CH6_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26431 …ne IOMUXC_FLEXTIMER1_CH7_SELECT_INPUT IOMUXC_FLEXTIMER1_CH7_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26432 …ne IOMUXC_FLEXTIMER1_PHA_SELECT_INPUT IOMUXC_FLEXTIMER1_PHA_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26433 …ne IOMUXC_FLEXTIMER1_PHB_SELECT_INPUT IOMUXC_FLEXTIMER1_PHB_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26434 …ne IOMUXC_FLEXTIMER2_CH0_SELECT_INPUT IOMUXC_FLEXTIMER2_CH0_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26435 …ne IOMUXC_FLEXTIMER2_CH1_SELECT_INPUT IOMUXC_FLEXTIMER2_CH1_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26436 …ne IOMUXC_FLEXTIMER2_CH2_SELECT_INPUT IOMUXC_FLEXTIMER2_CH2_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26437 …ne IOMUXC_FLEXTIMER2_CH3_SELECT_INPUT IOMUXC_FLEXTIMER2_CH3_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26438 …ne IOMUXC_FLEXTIMER2_CH4_SELECT_INPUT IOMUXC_FLEXTIMER2_CH4_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26439 …ne IOMUXC_FLEXTIMER2_CH5_SELECT_INPUT IOMUXC_FLEXTIMER2_CH5_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26440 …ne IOMUXC_FLEXTIMER2_CH6_SELECT_INPUT IOMUXC_FLEXTIMER2_CH6_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26441 …ne IOMUXC_FLEXTIMER2_CH7_SELECT_INPUT IOMUXC_FLEXTIMER2_CH7_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26442 …ne IOMUXC_FLEXTIMER2_PHA_SELECT_INPUT IOMUXC_FLEXTIMER2_PHA_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26443 …ne IOMUXC_FLEXTIMER2_PHB_SELECT_INPUT IOMUXC_FLEXTIMER2_PHB_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26444 #define IOMUXC_I2C1_SCL_SELECT_INPUT IOMUXC_I2C1_SCL_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26445 #define IOMUXC_I2C1_SDA_SELECT_INPUT IOMUXC_I2C1_SDA_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26446 #define IOMUXC_I2C2_SCL_SELECT_INPUT IOMUXC_I2C2_SCL_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26447 #define IOMUXC_I2C2_SDA_SELECT_INPUT IOMUXC_I2C2_SDA_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26448 #define IOMUXC_I2C3_SCL_SELECT_INPUT IOMUXC_I2C3_SCL_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26449 #define IOMUXC_I2C3_SDA_SELECT_INPUT IOMUXC_I2C3_SDA_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26450 #define IOMUXC_I2C4_SCL_SELECT_INPUT IOMUXC_I2C4_SCL_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26451 #define IOMUXC_I2C4_SDA_SELECT_INPUT IOMUXC_I2C4_SDA_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26452 #define IOMUXC_KPP_COL0_SELECT_INPUT IOMUXC_KPP_COL0_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26453 #define IOMUXC_KPP_COL1_SELECT_INPUT IOMUXC_KPP_COL1_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26454 #define IOMUXC_KPP_COL2_SELECT_INPUT IOMUXC_KPP_COL2_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26455 #define IOMUXC_KPP_COL3_SELECT_INPUT IOMUXC_KPP_COL3_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26456 #define IOMUXC_KPP_COL4_SELECT_INPUT IOMUXC_KPP_COL4_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26457 #define IOMUXC_KPP_COL5_SELECT_INPUT IOMUXC_KPP_COL5_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26458 #define IOMUXC_KPP_COL6_SELECT_INPUT IOMUXC_KPP_COL6_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26459 #define IOMUXC_KPP_COL7_SELECT_INPUT IOMUXC_KPP_COL7_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26460 #define IOMUXC_KPP_ROW0_SELECT_INPUT IOMUXC_KPP_ROW0_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26461 #define IOMUXC_KPP_ROW1_SELECT_INPUT IOMUXC_KPP_ROW1_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26462 #define IOMUXC_KPP_ROW2_SELECT_INPUT IOMUXC_KPP_ROW2_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26463 #define IOMUXC_KPP_ROW3_SELECT_INPUT IOMUXC_KPP_ROW3_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26464 #define IOMUXC_KPP_ROW4_SELECT_INPUT IOMUXC_KPP_ROW4_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26465 #define IOMUXC_KPP_ROW5_SELECT_INPUT IOMUXC_KPP_ROW5_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26466 #define IOMUXC_KPP_ROW6_SELECT_INPUT IOMUXC_KPP_ROW6_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26467 #define IOMUXC_KPP_ROW7_SELECT_INPUT IOMUXC_KPP_ROW7_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26468 #define IOMUXC_LCD_BUSY_SELECT_INPUT IOMUXC_LCD_BUSY_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26469 #define IOMUXC_LCD_DATA00_SELECT_INPUT IOMUXC_LCD_DATA00_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26470 #define IOMUXC_LCD_DATA01_SELECT_INPUT IOMUXC_LCD_DATA01_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26471 #define IOMUXC_LCD_DATA02_SELECT_INPUT IOMUXC_LCD_DATA02_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26472 #define IOMUXC_LCD_DATA03_SELECT_INPUT IOMUXC_LCD_DATA03_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26473 #define IOMUXC_LCD_DATA04_SELECT_INPUT IOMUXC_LCD_DATA04_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26474 #define IOMUXC_LCD_DATA05_SELECT_INPUT IOMUXC_LCD_DATA05_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26475 #define IOMUXC_LCD_DATA06_SELECT_INPUT IOMUXC_LCD_DATA06_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26476 #define IOMUXC_LCD_DATA07_SELECT_INPUT IOMUXC_LCD_DATA07_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26477 #define IOMUXC_LCD_DATA08_SELECT_INPUT IOMUXC_LCD_DATA08_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26478 #define IOMUXC_LCD_DATA09_SELECT_INPUT IOMUXC_LCD_DATA09_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26479 #define IOMUXC_LCD_DATA10_SELECT_INPUT IOMUXC_LCD_DATA10_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26480 #define IOMUXC_LCD_DATA11_SELECT_INPUT IOMUXC_LCD_DATA11_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26481 #define IOMUXC_LCD_DATA12_SELECT_INPUT IOMUXC_LCD_DATA12_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26482 #define IOMUXC_LCD_DATA13_SELECT_INPUT IOMUXC_LCD_DATA13_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26483 #define IOMUXC_LCD_DATA14_SELECT_INPUT IOMUXC_LCD_DATA14_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26484 #define IOMUXC_LCD_DATA15_SELECT_INPUT IOMUXC_LCD_DATA15_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26485 #define IOMUXC_LCD_DATA16_SELECT_INPUT IOMUXC_LCD_DATA16_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26486 #define IOMUXC_LCD_DATA17_SELECT_INPUT IOMUXC_LCD_DATA17_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26487 #define IOMUXC_LCD_DATA18_SELECT_INPUT IOMUXC_LCD_DATA18_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26488 #define IOMUXC_LCD_DATA19_SELECT_INPUT IOMUXC_LCD_DATA19_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26489 #define IOMUXC_LCD_DATA20_SELECT_INPUT IOMUXC_LCD_DATA20_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26490 #define IOMUXC_LCD_DATA21_SELECT_INPUT IOMUXC_LCD_DATA21_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26491 #define IOMUXC_LCD_DATA22_SELECT_INPUT IOMUXC_LCD_DATA22_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26492 #define IOMUXC_LCD_DATA23_SELECT_INPUT IOMUXC_LCD_DATA23_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26493 #define IOMUXC_LCD_VSYNC_SELECT_INPUT IOMUXC_LCD_VSYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26494 …fine IOMUXC_SAI1_RX_BCLK_SELECT_INPUT IOMUXC_SAI1_RX_BCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26495 …fine IOMUXC_SAI1_RX_DATA_SELECT_INPUT IOMUXC_SAI1_RX_DATA_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26496 …fine IOMUXC_SAI1_RX_SYNC_SELECT_INPUT IOMUXC_SAI1_RX_SYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26497 …fine IOMUXC_SAI1_TX_BCLK_SELECT_INPUT IOMUXC_SAI1_TX_BCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26498 …fine IOMUXC_SAI1_TX_SYNC_SELECT_INPUT IOMUXC_SAI1_TX_SYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26499 …fine IOMUXC_SAI2_RX_BCLK_SELECT_INPUT IOMUXC_SAI2_RX_BCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26500 …fine IOMUXC_SAI2_RX_DATA_SELECT_INPUT IOMUXC_SAI2_RX_DATA_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26501 …fine IOMUXC_SAI2_RX_SYNC_SELECT_INPUT IOMUXC_SAI2_RX_SYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26502 …fine IOMUXC_SAI2_TX_BCLK_SELECT_INPUT IOMUXC_SAI2_TX_BCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26503 …fine IOMUXC_SAI2_TX_SYNC_SELECT_INPUT IOMUXC_SAI2_TX_SYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26504 …fine IOMUXC_SAI3_RX_BCLK_SELECT_INPUT IOMUXC_SAI3_RX_BCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26505 …fine IOMUXC_SAI3_RX_DATA_SELECT_INPUT IOMUXC_SAI3_RX_DATA_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26506 …fine IOMUXC_SAI3_RX_SYNC_SELECT_INPUT IOMUXC_SAI3_RX_SYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26507 …fine IOMUXC_SAI3_TX_BCLK_SELECT_INPUT IOMUXC_SAI3_TX_BCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26508 …fine IOMUXC_SAI3_TX_SYNC_SELECT_INPUT IOMUXC_SAI3_TX_SYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26509 …fine IOMUXC_SDMA_EVENTS0_SELECT_INPUT IOMUXC_SDMA_EVENTS0_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26510 …fine IOMUXC_SDMA_EVENTS1_SELECT_INPUT IOMUXC_SDMA_EVENTS1_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26511 …ine IOMUXC_SIM1_PORT1_PD_SELECT_INPUT IOMUXC_SIM1_PORT1_PD_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26512 …e IOMUXC_SIM1_PORT1_TRXD_SELECT_INPUT IOMUXC_SIM1_PORT1_TRXD_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26513 …ine IOMUXC_SIM2_PORT1_PD_SELECT_INPUT IOMUXC_SIM2_PORT1_PD_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26514 …e IOMUXC_SIM2_PORT1_TRXD_SELECT_INPUT IOMUXC_SIM2_PORT1_TRXD_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26515 …efine IOMUXC_UART1_RTS_B_SELECT_INPUT IOMUXC_UART1_RTS_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26516 …ine IOMUXC_UART1_RX_DATA_SELECT_INPUT IOMUXC_UART1_RX_DATA_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26517 …efine IOMUXC_UART2_RTS_B_SELECT_INPUT IOMUXC_UART2_RTS_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26518 …ine IOMUXC_UART2_RX_DATA_SELECT_INPUT IOMUXC_UART2_RX_DATA_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26519 …efine IOMUXC_UART3_RTS_B_SELECT_INPUT IOMUXC_UART3_RTS_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26520 …ine IOMUXC_UART3_RX_DATA_SELECT_INPUT IOMUXC_UART3_RX_DATA_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26521 …efine IOMUXC_UART4_RTS_B_SELECT_INPUT IOMUXC_UART4_RTS_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26522 …ine IOMUXC_UART4_RX_DATA_SELECT_INPUT IOMUXC_UART4_RX_DATA_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26523 …efine IOMUXC_UART5_RTS_B_SELECT_INPUT IOMUXC_UART5_RTS_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26524 …ine IOMUXC_UART5_RX_DATA_SELECT_INPUT IOMUXC_UART5_RX_DATA_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26525 …efine IOMUXC_UART6_RTS_B_SELECT_INPUT IOMUXC_UART6_RTS_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26526 …ine IOMUXC_UART6_RX_DATA_SELECT_INPUT IOMUXC_UART6_RX_DATA_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26527 …efine IOMUXC_UART7_RTS_B_SELECT_INPUT IOMUXC_UART7_RTS_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26528 …ine IOMUXC_UART7_RX_DATA_SELECT_INPUT IOMUXC_UART7_RX_DATA_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26529 …efine IOMUXC_USB_OTG2_OC_SELECT_INPUT IOMUXC_USB_OTG2_OC_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26530 …efine IOMUXC_USB_OTG1_OC_SELECT_INPUT IOMUXC_USB_OTG1_OC_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26531 …efine IOMUXC_USB_OTG2_ID_SELECT_INPUT IOMUXC_USB_OTG2_ID_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26532 …efine IOMUXC_USB_OTG1_ID_SELECT_INPUT IOMUXC_USB_OTG1_ID_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26533 #define IOMUXC_SD3_CD_B_SELECT_INPUT IOMUXC_SD3_CD_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
26534 #define IOMUXC_SD3_WP_SELECT_INPUT IOMUXC_SD3_WP_SELECT_INPUT_REG(IOMUXC_BASE_PTR)