Lines Matching refs:IOMUXC_BASE_PTR
22672 #define IOMUXC_BASE_PTR (IOMUXC) macro
22689 …fine IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00_REG(IOMUXC_BASE_PTR)
22690 …fine IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01_REG(IOMUXC_BASE_PTR)
22691 …fine IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02_REG(IOMUXC_BASE_PTR)
22692 …fine IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03_REG(IOMUXC_BASE_PTR)
22693 …fine IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04_REG(IOMUXC_BASE_PTR)
22694 …fine IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05_REG(IOMUXC_BASE_PTR)
22695 …fine IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06_REG(IOMUXC_BASE_PTR)
22696 …fine IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07_REG(IOMUXC_BASE_PTR)
22697 …fine IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_REG(IOMUXC_BASE_PTR)
22698 …fine IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_REG(IOMUXC_BASE_PTR)
22699 …fine IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_REG(IOMUXC_BASE_PTR)
22700 …fine IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_REG(IOMUXC_BASE_PTR)
22701 …fine IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_REG(IOMUXC_BASE_PTR)
22702 …fine IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_REG(IOMUXC_BASE_PTR)
22703 …fine IOMUXC_SW_MUX_CTL_PAD_CSI_DATA00 IOMUXC_SW_MUX_CTL_PAD_CSI_DATA00_REG(IOMUXC_BASE_PTR)
22704 …fine IOMUXC_SW_MUX_CTL_PAD_CSI_DATA01 IOMUXC_SW_MUX_CTL_PAD_CSI_DATA01_REG(IOMUXC_BASE_PTR)
22705 …fine IOMUXC_SW_MUX_CTL_PAD_CSI_DATA02 IOMUXC_SW_MUX_CTL_PAD_CSI_DATA02_REG(IOMUXC_BASE_PTR)
22706 …fine IOMUXC_SW_MUX_CTL_PAD_CSI_DATA03 IOMUXC_SW_MUX_CTL_PAD_CSI_DATA03_REG(IOMUXC_BASE_PTR)
22707 …fine IOMUXC_SW_MUX_CTL_PAD_CSI_DATA04 IOMUXC_SW_MUX_CTL_PAD_CSI_DATA04_REG(IOMUXC_BASE_PTR)
22708 …fine IOMUXC_SW_MUX_CTL_PAD_CSI_DATA05 IOMUXC_SW_MUX_CTL_PAD_CSI_DATA05_REG(IOMUXC_BASE_PTR)
22709 …fine IOMUXC_SW_MUX_CTL_PAD_CSI_DATA06 IOMUXC_SW_MUX_CTL_PAD_CSI_DATA06_REG(IOMUXC_BASE_PTR)
22710 …fine IOMUXC_SW_MUX_CTL_PAD_CSI_DATA07 IOMUXC_SW_MUX_CTL_PAD_CSI_DATA07_REG(IOMUXC_BASE_PTR)
22711 …efine IOMUXC_SW_MUX_CTL_PAD_CSI_HSYNC IOMUXC_SW_MUX_CTL_PAD_CSI_HSYNC_REG(IOMUXC_BASE_PTR)
22712 #define IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK_REG(IOMUXC_BASE_PTR)
22713 …fine IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK_REG(IOMUXC_BASE_PTR)
22714 …efine IOMUXC_SW_MUX_CTL_PAD_CSI_VSYNC IOMUXC_SW_MUX_CTL_PAD_CSI_VSYNC_REG(IOMUXC_BASE_PTR)
22715 …efine IOMUXC_SW_MUX_CTL_PAD_ENET1_COL IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_REG(IOMUXC_BASE_PTR)
22716 …efine IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_REG(IOMUXC_BASE_PTR)
22717 …efine IOMUXC_SW_MUX_CTL_PAD_ENET1_MDC IOMUXC_SW_MUX_CTL_PAD_ENET1_MDC_REG(IOMUXC_BASE_PTR)
22718 …fine IOMUXC_SW_MUX_CTL_PAD_ENET1_MDIO IOMUXC_SW_MUX_CTL_PAD_ENET1_MDIO_REG(IOMUXC_BASE_PTR)
22719 …ne IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_REG(IOMUXC_BASE_PTR)
22720 …ne IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_REG(IOMUXC_BASE_PTR)
22721 …efine IOMUXC_SW_MUX_CTL_PAD_ENET2_COL IOMUXC_SW_MUX_CTL_PAD_ENET2_COL_REG(IOMUXC_BASE_PTR)
22722 …efine IOMUXC_SW_MUX_CTL_PAD_ENET2_CRS IOMUXC_SW_MUX_CTL_PAD_ENET2_CRS_REG(IOMUXC_BASE_PTR)
22723 …ne IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_CLK IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_CLK_REG(IOMUXC_BASE_PTR)
22724 …ne IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK_REG(IOMUXC_BASE_PTR)
22725 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL0 IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_REG(IOMUXC_BASE_PTR)
22726 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL1 IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_REG(IOMUXC_BASE_PTR)
22727 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL2 IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_REG(IOMUXC_BASE_PTR)
22728 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL3 IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_REG(IOMUXC_BASE_PTR)
22729 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL4 IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_REG(IOMUXC_BASE_PTR)
22730 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0 IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_REG(IOMUXC_BASE_PTR)
22731 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1 IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_REG(IOMUXC_BASE_PTR)
22732 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2 IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_REG(IOMUXC_BASE_PTR)
22733 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3 IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_REG(IOMUXC_BASE_PTR)
22734 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4 IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_REG(IOMUXC_BASE_PTR)
22735 #define IOMUXC_SW_MUX_CTL_PAD_LCD1_CLK IOMUXC_SW_MUX_CTL_PAD_LCD1_CLK_REG(IOMUXC_BASE_PTR)
22736 …ine IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA00 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA00_REG(IOMUXC_BASE_PTR)
22737 …ine IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA01 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA01_REG(IOMUXC_BASE_PTR)
22738 …ine IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA02 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA02_REG(IOMUXC_BASE_PTR)
22739 …ine IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA03 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA03_REG(IOMUXC_BASE_PTR)
22740 …ine IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA04 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA04_REG(IOMUXC_BASE_PTR)
22741 …ine IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA05 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA05_REG(IOMUXC_BASE_PTR)
22742 …ine IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA06 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA06_REG(IOMUXC_BASE_PTR)
22743 …ine IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA07 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA07_REG(IOMUXC_BASE_PTR)
22744 …ine IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA08 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA08_REG(IOMUXC_BASE_PTR)
22745 …ine IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA09 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA09_REG(IOMUXC_BASE_PTR)
22746 …ine IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA10 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA10_REG(IOMUXC_BASE_PTR)
22747 …ine IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA11 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA11_REG(IOMUXC_BASE_PTR)
22748 …ine IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA12 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA12_REG(IOMUXC_BASE_PTR)
22749 …ine IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA13 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA13_REG(IOMUXC_BASE_PTR)
22750 …ine IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA14 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA14_REG(IOMUXC_BASE_PTR)
22751 …ine IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA15 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA15_REG(IOMUXC_BASE_PTR)
22752 …ine IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA16 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA16_REG(IOMUXC_BASE_PTR)
22753 …ine IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA17 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA17_REG(IOMUXC_BASE_PTR)
22754 …ine IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA18 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA18_REG(IOMUXC_BASE_PTR)
22755 …ine IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA19 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA19_REG(IOMUXC_BASE_PTR)
22756 …ine IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA20 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA20_REG(IOMUXC_BASE_PTR)
22757 …ine IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA21 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA21_REG(IOMUXC_BASE_PTR)
22758 …ine IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA22 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA22_REG(IOMUXC_BASE_PTR)
22759 …ine IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA23 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA23_REG(IOMUXC_BASE_PTR)
22760 …ine IOMUXC_SW_MUX_CTL_PAD_LCD1_ENABLE IOMUXC_SW_MUX_CTL_PAD_LCD1_ENABLE_REG(IOMUXC_BASE_PTR)
22761 …fine IOMUXC_SW_MUX_CTL_PAD_LCD1_HSYNC IOMUXC_SW_MUX_CTL_PAD_LCD1_HSYNC_REG(IOMUXC_BASE_PTR)
22762 …fine IOMUXC_SW_MUX_CTL_PAD_LCD1_RESET IOMUXC_SW_MUX_CTL_PAD_LCD1_RESET_REG(IOMUXC_BASE_PTR)
22763 …fine IOMUXC_SW_MUX_CTL_PAD_LCD1_VSYNC IOMUXC_SW_MUX_CTL_PAD_LCD1_VSYNC_REG(IOMUXC_BASE_PTR)
22764 #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_REG(IOMUXC_BASE_PTR)
22765 …fine IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B_REG(IOMUXC_BASE_PTR)
22766 …fine IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B_REG(IOMUXC_BASE_PTR)
22767 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_REG(IOMUXC_BASE_PTR)
22768 …ine IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_REG(IOMUXC_BASE_PTR)
22769 …ine IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_REG(IOMUXC_BASE_PTR)
22770 …ine IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_REG(IOMUXC_BASE_PTR)
22771 …ine IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_REG(IOMUXC_BASE_PTR)
22772 …ine IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_REG(IOMUXC_BASE_PTR)
22773 …ine IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_REG(IOMUXC_BASE_PTR)
22774 …ine IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_REG(IOMUXC_BASE_PTR)
22775 …ine IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_REG(IOMUXC_BASE_PTR)
22776 …efine IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B_REG(IOMUXC_BASE_PTR)
22777 …ne IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B_REG(IOMUXC_BASE_PTR)
22778 …efine IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B_REG(IOMUXC_BASE_PTR)
22779 …efine IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_REG(IOMUXC_BASE_PTR)
22780 …ne IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA0 IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA0_REG(IOMUXC_BASE_PTR)
22781 …ne IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA1 IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA1_REG(IOMUXC_BASE_PTR)
22782 …ne IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA2 IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA2_REG(IOMUXC_BASE_PTR)
22783 …ne IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA3 IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA3_REG(IOMUXC_BASE_PTR)
22784 …fine IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DQS IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DQS_REG(IOMUXC_BASE_PTR)
22785 …ine IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SCLK IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SCLK_REG(IOMUXC_BASE_PTR)
22786 …ne IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS0_B IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS0_B_REG(IOMUXC_BASE_PTR)
22787 …ne IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS1_B IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS1_B_REG(IOMUXC_BASE_PTR)
22788 …ne IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA0 IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA0_REG(IOMUXC_BASE_PTR)
22789 …ne IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA1 IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA1_REG(IOMUXC_BASE_PTR)
22790 …ne IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA2 IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA2_REG(IOMUXC_BASE_PTR)
22791 …ne IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA3 IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA3_REG(IOMUXC_BASE_PTR)
22792 …fine IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DQS IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DQS_REG(IOMUXC_BASE_PTR)
22793 …ine IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SCLK IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SCLK_REG(IOMUXC_BASE_PTR)
22794 …ne IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS0_B IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS0_B_REG(IOMUXC_BASE_PTR)
22795 …ne IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS1_B IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS1_B_REG(IOMUXC_BASE_PTR)
22796 …fine IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD0 IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD0_REG(IOMUXC_BASE_PTR)
22797 …fine IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD1 IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD1_REG(IOMUXC_BASE_PTR)
22798 …fine IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD2 IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD2_REG(IOMUXC_BASE_PTR)
22799 …fine IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD3 IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD3_REG(IOMUXC_BASE_PTR)
22800 …e IOMUXC_SW_MUX_CTL_PAD_RGMII1_RX_CTL IOMUXC_SW_MUX_CTL_PAD_RGMII1_RX_CTL_REG(IOMUXC_BASE_PTR)
22801 …fine IOMUXC_SW_MUX_CTL_PAD_RGMII1_RXC IOMUXC_SW_MUX_CTL_PAD_RGMII1_RXC_REG(IOMUXC_BASE_PTR)
22802 …fine IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD0 IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD0_REG(IOMUXC_BASE_PTR)
22803 …fine IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD1 IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD1_REG(IOMUXC_BASE_PTR)
22804 …fine IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD2 IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD2_REG(IOMUXC_BASE_PTR)
22805 …fine IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD3 IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD3_REG(IOMUXC_BASE_PTR)
22806 …e IOMUXC_SW_MUX_CTL_PAD_RGMII1_TX_CTL IOMUXC_SW_MUX_CTL_PAD_RGMII1_TX_CTL_REG(IOMUXC_BASE_PTR)
22807 …fine IOMUXC_SW_MUX_CTL_PAD_RGMII1_TXC IOMUXC_SW_MUX_CTL_PAD_RGMII1_TXC_REG(IOMUXC_BASE_PTR)
22808 …fine IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD0 IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD0_REG(IOMUXC_BASE_PTR)
22809 …fine IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD1 IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD1_REG(IOMUXC_BASE_PTR)
22810 …fine IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD2 IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD2_REG(IOMUXC_BASE_PTR)
22811 …fine IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD3 IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD3_REG(IOMUXC_BASE_PTR)
22812 …e IOMUXC_SW_MUX_CTL_PAD_RGMII2_RX_CTL IOMUXC_SW_MUX_CTL_PAD_RGMII2_RX_CTL_REG(IOMUXC_BASE_PTR)
22813 …fine IOMUXC_SW_MUX_CTL_PAD_RGMII2_RXC IOMUXC_SW_MUX_CTL_PAD_RGMII2_RXC_REG(IOMUXC_BASE_PTR)
22814 …fine IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD0 IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD0_REG(IOMUXC_BASE_PTR)
22815 …fine IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD1 IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD1_REG(IOMUXC_BASE_PTR)
22816 …fine IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD2 IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD2_REG(IOMUXC_BASE_PTR)
22817 …fine IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD3 IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD3_REG(IOMUXC_BASE_PTR)
22818 …e IOMUXC_SW_MUX_CTL_PAD_RGMII2_TX_CTL IOMUXC_SW_MUX_CTL_PAD_RGMII2_TX_CTL_REG(IOMUXC_BASE_PTR)
22819 …fine IOMUXC_SW_MUX_CTL_PAD_RGMII2_TXC IOMUXC_SW_MUX_CTL_PAD_RGMII2_TXC_REG(IOMUXC_BASE_PTR)
22820 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_REG(IOMUXC_BASE_PTR)
22821 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_REG(IOMUXC_BASE_PTR)
22822 …efine IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_REG(IOMUXC_BASE_PTR)
22823 …efine IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_REG(IOMUXC_BASE_PTR)
22824 …efine IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_REG(IOMUXC_BASE_PTR)
22825 …efine IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_REG(IOMUXC_BASE_PTR)
22826 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_REG(IOMUXC_BASE_PTR)
22827 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_REG(IOMUXC_BASE_PTR)
22828 …efine IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0 IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_REG(IOMUXC_BASE_PTR)
22829 …efine IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1 IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_REG(IOMUXC_BASE_PTR)
22830 …efine IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2 IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_REG(IOMUXC_BASE_PTR)
22831 …efine IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3 IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_REG(IOMUXC_BASE_PTR)
22832 #define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_REG(IOMUXC_BASE_PTR)
22833 #define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_REG(IOMUXC_BASE_PTR)
22834 …efine IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0 IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_REG(IOMUXC_BASE_PTR)
22835 …efine IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1 IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_REG(IOMUXC_BASE_PTR)
22836 …efine IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2 IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_REG(IOMUXC_BASE_PTR)
22837 …efine IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3 IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_REG(IOMUXC_BASE_PTR)
22838 …efine IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4 IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_REG(IOMUXC_BASE_PTR)
22839 …efine IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5 IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_REG(IOMUXC_BASE_PTR)
22840 …efine IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6 IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_REG(IOMUXC_BASE_PTR)
22841 …efine IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7 IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_REG(IOMUXC_BASE_PTR)
22842 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_REG(IOMUXC_BASE_PTR)
22843 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_REG(IOMUXC_BASE_PTR)
22844 …efine IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0 IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_REG(IOMUXC_BASE_PTR)
22845 …efine IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1 IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_REG(IOMUXC_BASE_PTR)
22846 …efine IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2 IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_REG(IOMUXC_BASE_PTR)
22847 …efine IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3 IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_REG(IOMUXC_BASE_PTR)
22848 …efine IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4 IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_REG(IOMUXC_BASE_PTR)
22849 …efine IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5 IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_REG(IOMUXC_BASE_PTR)
22850 …efine IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6 IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_REG(IOMUXC_BASE_PTR)
22851 …efine IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7 IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_REG(IOMUXC_BASE_PTR)
22852 …ine IOMUXC_SW_MUX_CTL_PAD_SD4_RESET_B IOMUXC_SW_MUX_CTL_PAD_SD4_RESET_B_REG(IOMUXC_BASE_PTR)
22853 …fine IOMUXC_SW_MUX_CTL_PAD_USB_H_DATA IOMUXC_SW_MUX_CTL_PAD_USB_H_DATA_REG(IOMUXC_BASE_PTR)
22854 …ne IOMUXC_SW_MUX_CTL_PAD_USB_H_STROBE IOMUXC_SW_MUX_CTL_PAD_USB_H_STROBE_REG(IOMUXC_BASE_PTR)
22855 …ine IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00 IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_REG(IOMUXC_BASE_PTR)
22856 …ine IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01 IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_REG(IOMUXC_BASE_PTR)
22857 …ine IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_REG(IOMUXC_BASE_PTR)
22858 …ine IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_REG(IOMUXC_BASE_PTR)
22859 …ine IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_REG(IOMUXC_BASE_PTR)
22860 …ine IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_REG(IOMUXC_BASE_PTR)
22861 …ine IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_REG(IOMUXC_BASE_PTR)
22862 …ine IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_REG(IOMUXC_BASE_PTR)
22863 …ine IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_REG(IOMUXC_BASE_PTR)
22864 …ine IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_REG(IOMUXC_BASE_PTR)
22865 …ine IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10 IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_REG(IOMUXC_BASE_PTR)
22866 …ine IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11 IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_REG(IOMUXC_BASE_PTR)
22867 …ine IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12 IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_REG(IOMUXC_BASE_PTR)
22868 …ine IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13 IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_REG(IOMUXC_BASE_PTR)
22869 …ine IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14 IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_REG(IOMUXC_BASE_PTR)
22870 …ine IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15 IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_REG(IOMUXC_BASE_PTR)
22871 …efine IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_REG(IOMUXC_BASE_PTR)
22872 …efine IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_REG(IOMUXC_BASE_PTR)
22873 …efine IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_REG(IOMUXC_BASE_PTR)
22874 …efine IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_REG(IOMUXC_BASE_PTR)
22875 …fine IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_REG(IOMUXC_BASE_PTR)
22876 …fine IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_REG(IOMUXC_BASE_PTR)
22877 …fine IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_REG(IOMUXC_BASE_PTR)
22878 …fine IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_REG(IOMUXC_BASE_PTR)
22879 …ine IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_REG(IOMUXC_BASE_PTR)
22880 …efine IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_REG(IOMUXC_BASE_PTR)
22881 …efine IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_REG(IOMUXC_BASE_PTR)
22882 …fine IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_REG(IOMUXC_BASE_PTR)
22883 …fine IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_REG(IOMUXC_BASE_PTR)
22884 …fine IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_REG(IOMUXC_BASE_PTR)
22885 …ine IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_REG(IOMUXC_BASE_PTR)
22886 …ine IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_REG(IOMUXC_BASE_PTR)
22887 …e IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_REG(IOMUXC_BASE_PTR)
22888 …ne IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_REG(IOMUXC_BASE_PTR)
22889 …ne IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_REG(IOMUXC_BASE_PTR)
22890 …ne IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_REG(IOMUXC_BASE_PTR)
22891 …ne IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_REG(IOMUXC_BASE_PTR)
22892 …fine IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_REG(IOMUXC_BASE_PTR)
22893 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_REG(IOMUXC_BASE_PTR)
22894 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_REG(IOMUXC_BASE_PTR)
22895 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_REG(IOMUXC_BASE_PTR)
22896 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_REG(IOMUXC_BASE_PTR)
22897 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_REG(IOMUXC_BASE_PTR)
22898 …ine IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_REG(IOMUXC_BASE_PTR)
22899 …fine IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_REG(IOMUXC_BASE_PTR)
22900 …fine IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_REG(IOMUXC_BASE_PTR)
22901 …fine IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_REG(IOMUXC_BASE_PTR)
22902 …fine IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_REG(IOMUXC_BASE_PTR)
22903 …fine IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_REG(IOMUXC_BASE_PTR)
22904 …fine IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_REG(IOMUXC_BASE_PTR)
22905 …fine IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_REG(IOMUXC_BASE_PTR)
22906 …fine IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_REG(IOMUXC_BASE_PTR)
22907 …fine IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_REG(IOMUXC_BASE_PTR)
22908 …fine IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_REG(IOMUXC_BASE_PTR)
22909 …fine IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_REG(IOMUXC_BASE_PTR)
22910 …fine IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_REG(IOMUXC_BASE_PTR)
22911 …fine IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_REG(IOMUXC_BASE_PTR)
22912 …fine IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_REG(IOMUXC_BASE_PTR)
22913 …fine IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00 IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_REG(IOMUXC_BASE_PTR)
22914 …fine IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01 IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_REG(IOMUXC_BASE_PTR)
22915 …fine IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02 IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_REG(IOMUXC_BASE_PTR)
22916 …fine IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03 IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_REG(IOMUXC_BASE_PTR)
22917 …fine IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04 IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_REG(IOMUXC_BASE_PTR)
22918 …fine IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05 IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_REG(IOMUXC_BASE_PTR)
22919 …fine IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06 IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_REG(IOMUXC_BASE_PTR)
22920 …fine IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07 IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_REG(IOMUXC_BASE_PTR)
22921 …efine IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_REG(IOMUXC_BASE_PTR)
22922 #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_REG(IOMUXC_BASE_PTR)
22923 …fine IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_REG(IOMUXC_BASE_PTR)
22924 …efine IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_REG(IOMUXC_BASE_PTR)
22925 …efine IOMUXC_SW_PAD_CTL_PAD_ENET1_COL IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_REG(IOMUXC_BASE_PTR)
22926 …efine IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_REG(IOMUXC_BASE_PTR)
22927 …efine IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_REG(IOMUXC_BASE_PTR)
22928 …fine IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_REG(IOMUXC_BASE_PTR)
22929 …ne IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_REG(IOMUXC_BASE_PTR)
22930 …ne IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_REG(IOMUXC_BASE_PTR)
22931 …efine IOMUXC_SW_PAD_CTL_PAD_ENET2_COL IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_REG(IOMUXC_BASE_PTR)
22932 …efine IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_REG(IOMUXC_BASE_PTR)
22933 …ne IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_REG(IOMUXC_BASE_PTR)
22934 …ne IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_REG(IOMUXC_BASE_PTR)
22935 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0 IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_REG(IOMUXC_BASE_PTR)
22936 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1 IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_REG(IOMUXC_BASE_PTR)
22937 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2 IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_REG(IOMUXC_BASE_PTR)
22938 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3 IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_REG(IOMUXC_BASE_PTR)
22939 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4 IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_REG(IOMUXC_BASE_PTR)
22940 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0 IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_REG(IOMUXC_BASE_PTR)
22941 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1 IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_REG(IOMUXC_BASE_PTR)
22942 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2 IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_REG(IOMUXC_BASE_PTR)
22943 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3 IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_REG(IOMUXC_BASE_PTR)
22944 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4 IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_REG(IOMUXC_BASE_PTR)
22945 #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_REG(IOMUXC_BASE_PTR)
22946 …ine IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_REG(IOMUXC_BASE_PTR)
22947 …ine IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_REG(IOMUXC_BASE_PTR)
22948 …ine IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_REG(IOMUXC_BASE_PTR)
22949 …ine IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_REG(IOMUXC_BASE_PTR)
22950 …ine IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_REG(IOMUXC_BASE_PTR)
22951 …ine IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_REG(IOMUXC_BASE_PTR)
22952 …ine IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_REG(IOMUXC_BASE_PTR)
22953 …ine IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_REG(IOMUXC_BASE_PTR)
22954 …ine IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_REG(IOMUXC_BASE_PTR)
22955 …ine IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_REG(IOMUXC_BASE_PTR)
22956 …ine IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_REG(IOMUXC_BASE_PTR)
22957 …ine IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_REG(IOMUXC_BASE_PTR)
22958 …ine IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_REG(IOMUXC_BASE_PTR)
22959 …ine IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_REG(IOMUXC_BASE_PTR)
22960 …ine IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_REG(IOMUXC_BASE_PTR)
22961 …ine IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_REG(IOMUXC_BASE_PTR)
22962 …ine IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_REG(IOMUXC_BASE_PTR)
22963 …ine IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_REG(IOMUXC_BASE_PTR)
22964 …ine IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_REG(IOMUXC_BASE_PTR)
22965 …ine IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_REG(IOMUXC_BASE_PTR)
22966 …ine IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_REG(IOMUXC_BASE_PTR)
22967 …ine IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_REG(IOMUXC_BASE_PTR)
22968 …ine IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_REG(IOMUXC_BASE_PTR)
22969 …ine IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_REG(IOMUXC_BASE_PTR)
22970 …ine IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_REG(IOMUXC_BASE_PTR)
22971 …fine IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_REG(IOMUXC_BASE_PTR)
22972 …fine IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_REG(IOMUXC_BASE_PTR)
22973 …fine IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_REG(IOMUXC_BASE_PTR)
22974 #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_REG(IOMUXC_BASE_PTR)
22975 …fine IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_REG(IOMUXC_BASE_PTR)
22976 …fine IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_REG(IOMUXC_BASE_PTR)
22977 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_REG(IOMUXC_BASE_PTR)
22978 …ine IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00 IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_REG(IOMUXC_BASE_PTR)
22979 …ine IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01 IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_REG(IOMUXC_BASE_PTR)
22980 …ine IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02 IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_REG(IOMUXC_BASE_PTR)
22981 …ine IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03 IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_REG(IOMUXC_BASE_PTR)
22982 …ine IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04 IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_REG(IOMUXC_BASE_PTR)
22983 …ine IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05 IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_REG(IOMUXC_BASE_PTR)
22984 …ine IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06 IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_REG(IOMUXC_BASE_PTR)
22985 …ine IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07 IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_REG(IOMUXC_BASE_PTR)
22986 …efine IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_REG(IOMUXC_BASE_PTR)
22987 …ne IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_REG(IOMUXC_BASE_PTR)
22988 …efine IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_REG(IOMUXC_BASE_PTR)
22989 …efine IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_REG(IOMUXC_BASE_PTR)
22990 …ne IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0 IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_REG(IOMUXC_BASE_PTR)
22991 …ne IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1 IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_REG(IOMUXC_BASE_PTR)
22992 …ne IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2 IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_REG(IOMUXC_BASE_PTR)
22993 …ne IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3 IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_REG(IOMUXC_BASE_PTR)
22994 …fine IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_REG(IOMUXC_BASE_PTR)
22995 …ine IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_REG(IOMUXC_BASE_PTR)
22996 …ne IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_REG(IOMUXC_BASE_PTR)
22997 …ne IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_REG(IOMUXC_BASE_PTR)
22998 …ne IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0 IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_REG(IOMUXC_BASE_PTR)
22999 …ne IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1 IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_REG(IOMUXC_BASE_PTR)
23000 …ne IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2 IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_REG(IOMUXC_BASE_PTR)
23001 …ne IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3 IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_REG(IOMUXC_BASE_PTR)
23002 …fine IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_REG(IOMUXC_BASE_PTR)
23003 …ine IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_REG(IOMUXC_BASE_PTR)
23004 …ne IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_REG(IOMUXC_BASE_PTR)
23005 …ne IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_REG(IOMUXC_BASE_PTR)
23006 …fine IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0 IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_REG(IOMUXC_BASE_PTR)
23007 …fine IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1 IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_REG(IOMUXC_BASE_PTR)
23008 …fine IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2 IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_REG(IOMUXC_BASE_PTR)
23009 …fine IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3 IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_REG(IOMUXC_BASE_PTR)
23010 …e IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_REG(IOMUXC_BASE_PTR)
23011 …fine IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_REG(IOMUXC_BASE_PTR)
23012 …fine IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0 IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_REG(IOMUXC_BASE_PTR)
23013 …fine IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1 IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_REG(IOMUXC_BASE_PTR)
23014 …fine IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2 IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_REG(IOMUXC_BASE_PTR)
23015 …fine IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3 IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_REG(IOMUXC_BASE_PTR)
23016 …e IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_REG(IOMUXC_BASE_PTR)
23017 …fine IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_REG(IOMUXC_BASE_PTR)
23018 …fine IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0 IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_REG(IOMUXC_BASE_PTR)
23019 …fine IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1 IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_REG(IOMUXC_BASE_PTR)
23020 …fine IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2 IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_REG(IOMUXC_BASE_PTR)
23021 …fine IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3 IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_REG(IOMUXC_BASE_PTR)
23022 …e IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_REG(IOMUXC_BASE_PTR)
23023 …fine IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_REG(IOMUXC_BASE_PTR)
23024 …fine IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0 IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_REG(IOMUXC_BASE_PTR)
23025 …fine IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1 IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_REG(IOMUXC_BASE_PTR)
23026 …fine IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2 IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_REG(IOMUXC_BASE_PTR)
23027 …fine IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3 IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_REG(IOMUXC_BASE_PTR)
23028 …e IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_REG(IOMUXC_BASE_PTR)
23029 …fine IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_REG(IOMUXC_BASE_PTR)
23030 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_REG(IOMUXC_BASE_PTR)
23031 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_REG(IOMUXC_BASE_PTR)
23032 …efine IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0 IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_REG(IOMUXC_BASE_PTR)
23033 …efine IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1 IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_REG(IOMUXC_BASE_PTR)
23034 …efine IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2 IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_REG(IOMUXC_BASE_PTR)
23035 …efine IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3 IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_REG(IOMUXC_BASE_PTR)
23036 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_REG(IOMUXC_BASE_PTR)
23037 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_REG(IOMUXC_BASE_PTR)
23038 …efine IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0 IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_REG(IOMUXC_BASE_PTR)
23039 …efine IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1 IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_REG(IOMUXC_BASE_PTR)
23040 …efine IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2 IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_REG(IOMUXC_BASE_PTR)
23041 …efine IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3 IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_REG(IOMUXC_BASE_PTR)
23042 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_REG(IOMUXC_BASE_PTR)
23043 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_REG(IOMUXC_BASE_PTR)
23044 …efine IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0 IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_REG(IOMUXC_BASE_PTR)
23045 …efine IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1 IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_REG(IOMUXC_BASE_PTR)
23046 …efine IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2 IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_REG(IOMUXC_BASE_PTR)
23047 …efine IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3 IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_REG(IOMUXC_BASE_PTR)
23048 …efine IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4 IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_REG(IOMUXC_BASE_PTR)
23049 …efine IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5 IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_REG(IOMUXC_BASE_PTR)
23050 …efine IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6 IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_REG(IOMUXC_BASE_PTR)
23051 …efine IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7 IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_REG(IOMUXC_BASE_PTR)
23052 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_REG(IOMUXC_BASE_PTR)
23053 #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_REG(IOMUXC_BASE_PTR)
23054 …efine IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0 IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_REG(IOMUXC_BASE_PTR)
23055 …efine IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1 IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_REG(IOMUXC_BASE_PTR)
23056 …efine IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2 IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_REG(IOMUXC_BASE_PTR)
23057 …efine IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3 IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_REG(IOMUXC_BASE_PTR)
23058 …efine IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4 IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_REG(IOMUXC_BASE_PTR)
23059 …efine IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5 IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_REG(IOMUXC_BASE_PTR)
23060 …efine IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6 IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_REG(IOMUXC_BASE_PTR)
23061 …efine IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7 IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_REG(IOMUXC_BASE_PTR)
23062 …ine IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_REG(IOMUXC_BASE_PTR)
23063 …fine IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_REG(IOMUXC_BASE_PTR)
23064 …ne IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_REG(IOMUXC_BASE_PTR)
23065 #define IOMUXC_SW_PAD_CTL_GRP_ADDDS IOMUXC_SW_PAD_CTL_GRP_ADDDS_REG(IOMUXC_BASE_PTR)
23066 …ine IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_REG(IOMUXC_BASE_PTR)
23067 #define IOMUXC_SW_PAD_CTL_GRP_DDRPKE IOMUXC_SW_PAD_CTL_GRP_DDRPKE_REG(IOMUXC_BASE_PTR)
23068 #define IOMUXC_SW_PAD_CTL_GRP_DDRPK IOMUXC_SW_PAD_CTL_GRP_DDRPK_REG(IOMUXC_BASE_PTR)
23069 #define IOMUXC_SW_PAD_CTL_GRP_DDRHYS IOMUXC_SW_PAD_CTL_GRP_DDRHYS_REG(IOMUXC_BASE_PTR)
23070 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE IOMUXC_SW_PAD_CTL_GRP_DDRMODE_REG(IOMUXC_BASE_PTR)
23071 #define IOMUXC_SW_PAD_CTL_GRP_B0DS IOMUXC_SW_PAD_CTL_GRP_B0DS_REG(IOMUXC_BASE_PTR)
23072 #define IOMUXC_SW_PAD_CTL_GRP_B1DS IOMUXC_SW_PAD_CTL_GRP_B1DS_REG(IOMUXC_BASE_PTR)
23073 #define IOMUXC_SW_PAD_CTL_GRP_CTLDS IOMUXC_SW_PAD_CTL_GRP_CTLDS_REG(IOMUXC_BASE_PTR)
23074 #define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_REG(IOMUXC_BASE_PTR)
23075 #define IOMUXC_SW_PAD_CTL_GRP_B2DS IOMUXC_SW_PAD_CTL_GRP_B2DS_REG(IOMUXC_BASE_PTR)
23076 #define IOMUXC_SW_PAD_CTL_GRP_B3DS IOMUXC_SW_PAD_CTL_GRP_B3DS_REG(IOMUXC_BASE_PTR)
23077 …IOMUXC_ANATOP_USB_OTG_ID_SELECT_INPUT IOMUXC_ANATOP_USB_OTG_ID_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23078 …IOMUXC_ANATOP_USB_UH1_ID_SELECT_INPUT IOMUXC_ANATOP_USB_UH1_ID_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23079 …AUDMUX_P3_INPUT_DA_AMX_SELECT_INPUT IOMUXC_AUDMUX_P3_INPUT_DA_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23080 …AUDMUX_P3_INPUT_DB_AMX_SELECT_INPUT IOMUXC_AUDMUX_P3_INPUT_DB_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23081 …_P3_INPUT_RXCLK_AMX_SELECT_INPUT IOMUXC_AUDMUX_P3_INPUT_RXCLK_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23082 …UX_P3_INPUT_RXFS_AMX_SELECT_INPUT IOMUXC_AUDMUX_P3_INPUT_RXFS_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23083 …_P3_INPUT_TXCLK_AMX_SELECT_INPUT IOMUXC_AUDMUX_P3_INPUT_TXCLK_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23084 …UX_P3_INPUT_TXFS_AMX_SELECT_INPUT IOMUXC_AUDMUX_P3_INPUT_TXFS_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23085 …AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT IOMUXC_AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23086 …AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT IOMUXC_AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23087 …_P4_INPUT_RXCLK_AMX_SELECT_INPUT IOMUXC_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23088 …UX_P4_INPUT_RXFS_AMX_SELECT_INPUT IOMUXC_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23089 …_P4_INPUT_TXCLK_AMX_SELECT_INPUT IOMUXC_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23090 …UX_P4_INPUT_TXFS_AMX_SELECT_INPUT IOMUXC_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23091 …AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT IOMUXC_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23092 …AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT IOMUXC_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23093 …_P5_INPUT_RXCLK_AMX_SELECT_INPUT IOMUXC_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23094 …UX_P5_INPUT_RXFS_AMX_SELECT_INPUT IOMUXC_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23095 …_P5_INPUT_TXCLK_AMX_SELECT_INPUT IOMUXC_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23096 …UX_P5_INPUT_TXFS_AMX_SELECT_INPUT IOMUXC_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23097 …AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT IOMUXC_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23098 …AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT IOMUXC_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23099 …_P6_INPUT_RXCLK_AMX_SELECT_INPUT IOMUXC_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23100 …UX_P6_INPUT_RXFS_AMX_SELECT_INPUT IOMUXC_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23101 …_P6_INPUT_TXCLK_AMX_SELECT_INPUT IOMUXC_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23102 …UX_P6_INPUT_TXFS_AMX_SELECT_INPUT IOMUXC_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23103 …OMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT IOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23104 …OMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23105 …IC_VFUNCIONAL_READY_SELECT_INPUT IOMUXC_CCM_PMIC_VFUNCIONAL_READY_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23106 … IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_0 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_0_REG(IOMUXC_BASE_PTR)
23107 … IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_1 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_1_REG(IOMUXC_BASE_PTR)
23108 … IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_2 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_2_REG(IOMUXC_BASE_PTR)
23109 … IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_3 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_3_REG(IOMUXC_BASE_PTR)
23110 … IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_4 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_4_REG(IOMUXC_BASE_PTR)
23111 … IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_5 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_5_REG(IOMUXC_BASE_PTR)
23112 … IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_6 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_6_REG(IOMUXC_BASE_PTR)
23113 … IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_7 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_7_REG(IOMUXC_BASE_PTR)
23114 … IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_8 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_8_REG(IOMUXC_BASE_PTR)
23115 … IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_9 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_9_REG(IOMUXC_BASE_PTR)
23116 …IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_11 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_11_REG(IOMUXC_BASE_PTR)
23117 …IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_12 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_12_REG(IOMUXC_BASE_PTR)
23118 …IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_13 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_13_REG(IOMUXC_BASE_PTR)
23119 …IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_14 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_14_REG(IOMUXC_BASE_PTR)
23120 …IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_15 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_15_REG(IOMUXC_BASE_PTR)
23121 …IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_16 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_16_REG(IOMUXC_BASE_PTR)
23122 …IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_17 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_17_REG(IOMUXC_BASE_PTR)
23123 …IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_18 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_18_REG(IOMUXC_BASE_PTR)
23124 …IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_19 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_19_REG(IOMUXC_BASE_PTR)
23125 …IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_20 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_20_REG(IOMUXC_BASE_PTR)
23126 …IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_21 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_21_REG(IOMUXC_BASE_PTR)
23127 …IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_22 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_22_REG(IOMUXC_BASE_PTR)
23128 …IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_23 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_23_REG(IOMUXC_BASE_PTR)
23129 …IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_10 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_10_REG(IOMUXC_BASE_PTR)
23130 …OMUXC_CSI1_IPP_CSI_HSYNC_SELECT_INPUT IOMUXC_CSI1_IPP_CSI_HSYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23131 …MUXC_CSI1_IPP_CSI_PIXCLK_SELECT_INPUT IOMUXC_CSI1_IPP_CSI_PIXCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23132 …OMUXC_CSI1_IPP_CSI_VSYNC_SELECT_INPUT IOMUXC_CSI1_IPP_CSI_VSYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23133 …I1_TVDECODER_IN_FIELD_SELECT_INPUT IOMUXC_CSI1_TVDECODER_IN_FIELD_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23134 …ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT IOMUXC_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23135 …MUXC_ECSPI1_IPP_IND_MISO_SELECT_INPUT IOMUXC_ECSPI1_IPP_IND_MISO_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23136 …MUXC_ECSPI1_IPP_IND_MOSI_SELECT_INPUT IOMUXC_ECSPI1_IPP_IND_MOSI_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23137 …C_ECSPI1_IPP_IND_SS_B_SELECT_INPUT_0 IOMUXC_ECSPI1_IPP_IND_SS_B_SELECT_INPUT_0_REG(IOMUXC_BASE_PTR)
23138 …ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT IOMUXC_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23139 …MUXC_ECSPI2_IPP_IND_MISO_SELECT_INPUT IOMUXC_ECSPI2_IPP_IND_MISO_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23140 …MUXC_ECSPI2_IPP_IND_MOSI_SELECT_INPUT IOMUXC_ECSPI2_IPP_IND_MOSI_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23141 …C_ECSPI2_IPP_IND_SS_B_SELECT_INPUT_0 IOMUXC_ECSPI2_IPP_IND_SS_B_SELECT_INPUT_0_REG(IOMUXC_BASE_PTR)
23142 …ECSPI3_IPP_CSPI_CLK_IN_SELECT_INPUT IOMUXC_ECSPI3_IPP_CSPI_CLK_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23143 …MUXC_ECSPI3_IPP_IND_MISO_SELECT_INPUT IOMUXC_ECSPI3_IPP_IND_MISO_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23144 …MUXC_ECSPI3_IPP_IND_MOSI_SELECT_INPUT IOMUXC_ECSPI3_IPP_IND_MOSI_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23145 …C_ECSPI3_IPP_IND_SS_B_SELECT_INPUT_0 IOMUXC_ECSPI3_IPP_IND_SS_B_SELECT_INPUT_0_REG(IOMUXC_BASE_PTR)
23146 …ECSPI4_IPP_CSPI_CLK_IN_SELECT_INPUT IOMUXC_ECSPI4_IPP_CSPI_CLK_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23147 …MUXC_ECSPI4_IPP_IND_MISO_SELECT_INPUT IOMUXC_ECSPI4_IPP_IND_MISO_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23148 …MUXC_ECSPI4_IPP_IND_MOSI_SELECT_INPUT IOMUXC_ECSPI4_IPP_IND_MOSI_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23149 …C_ECSPI4_IPP_IND_SS_B_SELECT_INPUT_0 IOMUXC_ECSPI4_IPP_IND_SS_B_SELECT_INPUT_0_REG(IOMUXC_BASE_PTR)
23150 …ECSPI5_IPP_CSPI_CLK_IN_SELECT_INPUT IOMUXC_ECSPI5_IPP_CSPI_CLK_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23151 …MUXC_ECSPI5_IPP_IND_MISO_SELECT_INPUT IOMUXC_ECSPI5_IPP_IND_MISO_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23152 …MUXC_ECSPI5_IPP_IND_MOSI_SELECT_INPUT IOMUXC_ECSPI5_IPP_IND_MOSI_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23153 …C_ECSPI5_IPP_IND_SS_B_SELECT_INPUT_0 IOMUXC_ECSPI5_IPP_IND_SS_B_SELECT_INPUT_0_REG(IOMUXC_BASE_PTR)
23154 …OMUXC_ENET1_IPG_CLK_RMII_SELECT_INPUT IOMUXC_ENET1_IPG_CLK_RMII_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23155 …ET1_IPP_IND_MAC0_MDIO_SELECT_INPUT IOMUXC_ENET1_IPP_IND_MAC0_MDIO_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23156 …1_IPP_IND_MAC0_RXCLK_SELECT_INPUT IOMUXC_ENET1_IPP_IND_MAC0_RXCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23157 …OMUXC_ENET2_IPG_CLK_RMII_SELECT_INPUT IOMUXC_ENET2_IPG_CLK_RMII_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23158 …ET2_IPP_IND_MAC0_MDIO_SELECT_INPUT IOMUXC_ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23159 …2_IPP_IND_MAC0_RXCLK_SELECT_INPUT IOMUXC_ENET2_IPP_IND_MAC0_RXCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23160 … IOMUXC_ESAI_IPP_IND_FSR_SELECT_INPUT IOMUXC_ESAI_IPP_IND_FSR_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23161 … IOMUXC_ESAI_IPP_IND_FST_SELECT_INPUT IOMUXC_ESAI_IPP_IND_FST_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23162 …IOMUXC_ESAI_IPP_IND_HCKR_SELECT_INPUT IOMUXC_ESAI_IPP_IND_HCKR_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23163 …IOMUXC_ESAI_IPP_IND_HCKT_SELECT_INPUT IOMUXC_ESAI_IPP_IND_HCKT_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23164 …IOMUXC_ESAI_IPP_IND_SCKR_SELECT_INPUT IOMUXC_ESAI_IPP_IND_SCKR_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23165 …IOMUXC_ESAI_IPP_IND_SCKT_SELECT_INPUT IOMUXC_ESAI_IPP_IND_SCKT_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23166 …IOMUXC_ESAI_IPP_IND_SDO0_SELECT_INPUT IOMUXC_ESAI_IPP_IND_SDO0_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23167 …IOMUXC_ESAI_IPP_IND_SDO1_SELECT_INPUT IOMUXC_ESAI_IPP_IND_SDO1_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23168 …ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT IOMUXC_ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23169 …ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT IOMUXC_ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23170 …ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT IOMUXC_ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23171 …ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT IOMUXC_ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23172 …e IOMUXC_I2C1_IPP_SCL_IN_SELECT_INPUT IOMUXC_I2C1_IPP_SCL_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23173 …e IOMUXC_I2C1_IPP_SDA_IN_SELECT_INPUT IOMUXC_I2C1_IPP_SDA_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23174 …e IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23175 …e IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23176 …e IOMUXC_I2C3_IPP_SCL_IN_SELECT_INPUT IOMUXC_I2C3_IPP_SCL_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23177 …e IOMUXC_I2C3_IPP_SDA_IN_SELECT_INPUT IOMUXC_I2C3_IPP_SDA_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23178 …e IOMUXC_I2C4_IPP_SCL_IN_SELECT_INPUT IOMUXC_I2C4_IPP_SCL_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23179 …e IOMUXC_I2C4_IPP_SDA_IN_SELECT_INPUT IOMUXC_I2C4_IPP_SDA_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23180 …IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_5 IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_5_REG(IOMUXC_BASE_PTR)
23181 …IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_6 IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_6_REG(IOMUXC_BASE_PTR)
23182 …IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_7 IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_7_REG(IOMUXC_BASE_PTR)
23183 …IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_5 IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_5_REG(IOMUXC_BASE_PTR)
23184 …IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_6 IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_6_REG(IOMUXC_BASE_PTR)
23185 …IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_7 IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_7_REG(IOMUXC_BASE_PTR)
23186 #define IOMUXC_LCD1_BUSY_SELECT_INPUT IOMUXC_LCD1_BUSY_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23187 #define IOMUXC_LCD2_BUSY_SELECT_INPUT IOMUXC_LCD2_BUSY_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23188 …ne IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23189 …e IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23190 …ne IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23191 …I1_IPP_IND_SAI_RXBCLK_SELECT_INPUT IOMUXC_SAI1_IPP_IND_SAI_RXBCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23192 …PP_IND_SAI_RXDATA_SELECT_INPUT_0 IOMUXC_SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_0_REG(IOMUXC_BASE_PTR)
23193 …I1_IPP_IND_SAI_RXSYNC_SELECT_INPUT IOMUXC_SAI1_IPP_IND_SAI_RXSYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23194 …I1_IPP_IND_SAI_TXBCLK_SELECT_INPUT IOMUXC_SAI1_IPP_IND_SAI_TXBCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23195 …I1_IPP_IND_SAI_TXSYNC_SELECT_INPUT IOMUXC_SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23196 …I2_IPP_IND_SAI_RXBCLK_SELECT_INPUT IOMUXC_SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23197 …PP_IND_SAI_RXDATA_SELECT_INPUT_0 IOMUXC_SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_0_REG(IOMUXC_BASE_PTR)
23198 …I2_IPP_IND_SAI_RXSYNC_SELECT_INPUT IOMUXC_SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23199 …I2_IPP_IND_SAI_TXBCLK_SELECT_INPUT IOMUXC_SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23200 …I2_IPP_IND_SAI_TXSYNC_SELECT_INPUT IOMUXC_SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23201 …ne IOMUXC_SDMA_EVENTS_SELECT_INPUT_14 IOMUXC_SDMA_EVENTS_SELECT_INPUT_14_REG(IOMUXC_BASE_PTR)
23202 …ne IOMUXC_SDMA_EVENTS_SELECT_INPUT_15 IOMUXC_SDMA_EVENTS_SELECT_INPUT_15_REG(IOMUXC_BASE_PTR)
23203 …e IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23204 …ine IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23205 …UXC_UART1_IPP_UART_RTS_B_SELECT_INPUT IOMUXC_UART1_IPP_UART_RTS_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23206 …UART1_IPP_UART_RXD_MUX_SELECT_INPUT IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23207 …UXC_UART2_IPP_UART_RTS_B_SELECT_INPUT IOMUXC_UART2_IPP_UART_RTS_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23208 …UART2_IPP_UART_RXD_MUX_SELECT_INPUT IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23209 …UXC_UART3_IPP_UART_RTS_B_SELECT_INPUT IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23210 …UART3_IPP_UART_RXD_MUX_SELECT_INPUT IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23211 …UXC_UART4_IPP_UART_RTS_B_SELECT_INPUT IOMUXC_UART4_IPP_UART_RTS_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23212 …UART4_IPP_UART_RXD_MUX_SELECT_INPUT IOMUXC_UART4_IPP_UART_RXD_MUX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23213 …UXC_UART5_IPP_UART_RTS_B_SELECT_INPUT IOMUXC_UART5_IPP_UART_RTS_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23214 …UART5_IPP_UART_RXD_MUX_SELECT_INPUT IOMUXC_UART5_IPP_UART_RXD_MUX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23215 …UXC_UART6_IPP_UART_RTS_B_SELECT_INPUT IOMUXC_UART6_IPP_UART_RTS_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23216 …UART6_IPP_UART_RXD_MUX_SELECT_INPUT IOMUXC_UART6_IPP_UART_RXD_MUX_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23217 …MUXC_USB_IPP_IND_OTG2_OC_SELECT_INPUT IOMUXC_USB_IPP_IND_OTG2_OC_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23218 …OMUXC_USB_IPP_IND_OTG_OC_SELECT_INPUT IOMUXC_USB_IPP_IND_OTG_OC_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23219 …MUXC_USDHC1_IPP_CARD_DET_SELECT_INPUT IOMUXC_USDHC1_IPP_CARD_DET_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23220 … IOMUXC_USDHC1_IPP_WP_ON_SELECT_INPUT IOMUXC_USDHC1_IPP_WP_ON_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23221 …MUXC_USDHC2_IPP_CARD_DET_SELECT_INPUT IOMUXC_USDHC2_IPP_CARD_DET_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23222 … IOMUXC_USDHC2_IPP_WP_ON_SELECT_INPUT IOMUXC_USDHC2_IPP_WP_ON_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23223 …MUXC_USDHC4_IPP_CARD_DET_SELECT_INPUT IOMUXC_USDHC4_IPP_CARD_DET_SELECT_INPUT_REG(IOMUXC_BASE_PTR)
23224 … IOMUXC_USDHC4_IPP_WP_ON_SELECT_INPUT IOMUXC_USDHC4_IPP_WP_ON_SELECT_INPUT_REG(IOMUXC_BASE_PTR)