331             if (State->CurrentTxFifoSlot > (State->ExpectedFifoWrites - State->TxIndex))  in Spi_Ip_TransferProcess()
333                 State->CurrentTxFifoSlot = State->ExpectedFifoWrites - State->TxIndex;  in Spi_Ip_TransferProcess()
451     State->TxIndex = State->ExpectedFifoWrites;  in Spi_Ip_TxDmaTcdSGConfig()
671     State->TxIndex = NumberDmaIterWrite;  in Spi_Ip_DmaConfig()
852     uint16 NumberDmaIterWrite = State->ExpectedFifoWrites - State->TxIndex;  in Spi_Ip_DmaContinueTransfer()
886     State->TxIndex += NumberDmaIterWrite;  in Spi_Ip_DmaContinueTransfer()
1031                 Data = *((const uint8*)(&State->TxBuffer[State->TxIndex]));  in Spi_Ip_WriteTxFifo()
1035                 Data = *((const uint16*)(&State->TxBuffer[2u * State->TxIndex]));  in Spi_Ip_WriteTxFifo()
1042                 if ((uint16)0u == (State->TxIndex%2u))  in Spi_Ip_WriteTxFifo()
1056         State->TxIndex++;  in Spi_Ip_WriteTxFifo()
1475         State->TxIndex = 0u;  in Spi_Ip_SyncTransmit()
1549             if (State->CurrentTxFifoSlot > (State->ExpectedFifoWrites - State->TxIndex))  in Spi_Ip_SyncTransmit()
1551                 State->CurrentTxFifoSlot = State->ExpectedFifoWrites - State->TxIndex;  in Spi_Ip_SyncTransmit()
1649         State->TxIndex = 0u;  in Spi_Ip_AsyncTransmit()
1726 						if (State->CurrentTxFifoSlot > (State->ExpectedFifoWrites - State->TxIndex))  in Spi_Ip_AsyncTransmit()
1728 							State->CurrentTxFifoSlot = State->ExpectedFifoWrites - State->TxIndex;  in Spi_Ip_AsyncTransmit()
1751                         if (NumberOfWrites > (State->ExpectedFifoWrites - State->TxIndex))  in Spi_Ip_AsyncTransmit()
1753                             NumberOfWrites = State->ExpectedFifoWrites - State->TxIndex;  in Spi_Ip_AsyncTransmit()
1912         State->TxIndex = 0u;  in Spi_Ip_DmaFastConfig()