240     uint16 NumberOfWrites,
254     uint16 NumberOfWrites,
287     uint16 NumberOfWrites;  in Spi_Ip_TransferProcess()  local
316 …           NumberOfWrites = (uint16)((Base->SREX) & SPI_SREX_CMDCTR_MASK) >> SPI_SREX_CMDCTR_SHIFT;  in Spi_Ip_TransferProcess()
317                 NumberOfWrites = SPI_IP_FIFO_SIZE_U16 - NumberOfWrites;  in Spi_Ip_TransferProcess()
319                 if ((NumberOfWrites != 0u) && (State->ExpectedCmdFifoWrites != 0u))  in Spi_Ip_TransferProcess()
321                     Spi_Ip_WriteCmdFifo(NumberOfWrites, Instance);  in Spi_Ip_TransferProcess()
1016     uint16 NumberOfWrites,  in Spi_Ip_WriteTxFifo()  argument
1025     for (Count=0; Count < NumberOfWrites; Count++)  in Spi_Ip_WriteTxFifo()
1139     uint16 NumberOfWrites,  in Spi_Ip_WriteCmdFifo()  argument
1146     uint16 ActualNumberOfWrites = NumberOfWrites;   in Spi_Ip_WriteCmdFifo()
1430     uint16 NumberOfWrites;  in Spi_Ip_SyncTransmit()  local
1529 …           NumberOfWrites = (uint16)((Base->SREX) & SPI_SREX_CMDCTR_MASK) >> SPI_SREX_CMDCTR_SHIFT;  in Spi_Ip_SyncTransmit()
1530                 NumberOfWrites = SPI_IP_FIFO_SIZE_U16 - NumberOfWrites;  in Spi_Ip_SyncTransmit()
1532                 if ((NumberOfWrites != 0u) && (State->ExpectedCmdFifoWrites != 0u))  in Spi_Ip_SyncTransmit()
1534                     Spi_Ip_WriteCmdFifo(NumberOfWrites, Instance);  in Spi_Ip_SyncTransmit()
1613     uint16 NumberOfWrites = 0u;  in Spi_Ip_AsyncTransmit()  local
1741 …                   NumberOfWrites = (uint16)((Base->SR) & SPI_SR_TXCTR_MASK) >> SPI_SR_TXCTR_SHIFT;  in Spi_Ip_AsyncTransmit()
1742                         if (NumberOfWrites < SPI_IP_FIFO_SIZE_U16)  in Spi_Ip_AsyncTransmit()
1744                             NumberOfWrites = SPI_IP_FIFO_SIZE_U16 - NumberOfWrites;  in Spi_Ip_AsyncTransmit()
1748                             NumberOfWrites = 0u;  in Spi_Ip_AsyncTransmit()
1751                         if (NumberOfWrites > (State->ExpectedFifoWrites - State->TxIndex))  in Spi_Ip_AsyncTransmit()
1753                             NumberOfWrites = State->ExpectedFifoWrites - State->TxIndex;  in Spi_Ip_AsyncTransmit()
1756                         Spi_Ip_WriteTxFifo(NumberOfWrites, Instance);  in Spi_Ip_AsyncTransmit()
1758                         State->CurrentTxFifoSlot -= NumberOfWrites;  in Spi_Ip_AsyncTransmit()