331             if (State->CurrentTxFifoSlot > (State->ExpectedFifoWrites - State->TxIndex))  in Spi_Ip_TransferProcess()
333                 State->CurrentTxFifoSlot = State->ExpectedFifoWrites - State->TxIndex;  in Spi_Ip_TransferProcess()
451     State->TxIndex = State->ExpectedFifoWrites;  in Spi_Ip_TxDmaTcdSGConfig()
478     DmaTcdList[5u].Value = State->ExpectedFifoWrites; /* iteration count */  in Spi_Ip_TxDmaTcdSGConfig()
634     uint16 NumberDmaIterWrite = State->ExpectedFifoWrites;  in Spi_Ip_DmaConfig()
852     uint16 NumberDmaIterWrite = State->ExpectedFifoWrites - State->TxIndex;  in Spi_Ip_DmaContinueTransfer()
1180         State->ExpectedFifoWrites = Length;  in Spi_Ip_UpdateTxRxCounter()
1184         State->ExpectedFifoWrites = Length/2u;  in Spi_Ip_UpdateTxRxCounter()
1186     State->ExpectedFifoReads = State->ExpectedFifoWrites;  in Spi_Ip_UpdateTxRxCounter()
1189         State->ExpectedFifoReads = State->ExpectedFifoWrites/2u;  in Spi_Ip_UpdateTxRxCounter()
1549             if (State->CurrentTxFifoSlot > (State->ExpectedFifoWrites - State->TxIndex))  in Spi_Ip_SyncTransmit()
1551                 State->CurrentTxFifoSlot = State->ExpectedFifoWrites - State->TxIndex;  in Spi_Ip_SyncTransmit()
1655             State->ExpectedFifoWrites = Length;  in Spi_Ip_AsyncTransmit()
1659             State->ExpectedFifoWrites = Length/2u;  in Spi_Ip_AsyncTransmit()
1662         State->ExpectedFifoReads = State->ExpectedFifoWrites;  in Spi_Ip_AsyncTransmit()
1665             State->ExpectedFifoReads = State->ExpectedFifoWrites/2u;  in Spi_Ip_AsyncTransmit()
1726 						if (State->CurrentTxFifoSlot > (State->ExpectedFifoWrites - State->TxIndex))  in Spi_Ip_AsyncTransmit()
1728 							State->CurrentTxFifoSlot = State->ExpectedFifoWrites - State->TxIndex;  in Spi_Ip_AsyncTransmit()
1751                         if (NumberOfWrites > (State->ExpectedFifoWrites - State->TxIndex))  in Spi_Ip_AsyncTransmit()
1753                             NumberOfWrites = State->ExpectedFifoWrites - State->TxIndex;  in Spi_Ip_AsyncTransmit()
1917             State->ExpectedFifoWrites = FastTransferCfg[Count].Length;  in Spi_Ip_DmaFastConfig()
1921             State->ExpectedFifoWrites = FastTransferCfg[Count].Length/2u;  in Spi_Ip_DmaFastConfig()
1923         State->ExpectedFifoReads = State->ExpectedFifoWrites;  in Spi_Ip_DmaFastConfig()
1926             State->ExpectedFifoReads = State->ExpectedFifoWrites/2u;  in Spi_Ip_DmaFastConfig()