Lines Matching refs:ExpectedFifoReads

343         if ((State->RxIndex == State->ExpectedFifoReads) || ((boolean)TRUE == ErrorFlag))  in Spi_Ip_TransferProcess()
543     State->RxIndex = State->ExpectedFifoReads;  in Spi_Ip_RxDmaTcdSGConfig()
587     DmaTcdList[5u].Value = State->ExpectedFifoReads; /* iteration count */  in Spi_Ip_RxDmaTcdSGConfig()
1078     if (ActualNumberOfReads > (State->ExpectedFifoReads - State->RxIndex))  in Spi_Ip_ReceiveData()
1080         ActualNumberOfReads = State->ExpectedFifoReads - State->RxIndex;  in Spi_Ip_ReceiveData()
1186     State->ExpectedFifoReads = State->ExpectedFifoWrites;  in Spi_Ip_UpdateTxRxCounter()
1189         State->ExpectedFifoReads = State->ExpectedFifoWrites/2u;  in Spi_Ip_UpdateTxRxCounter()
1191     State->ExpectedCmdFifoWrites = State->ExpectedFifoReads;  in Spi_Ip_UpdateTxRxCounter()
1260                 if (State->ExpectedFifoReads != State->RxIndex)  in Spi_Ip_IrqDmaHandler()
1573                 if (State->RxIndex == State->ExpectedFifoReads)  in Spi_Ip_SyncTransmit()
1662         State->ExpectedFifoReads = State->ExpectedFifoWrites;  in Spi_Ip_AsyncTransmit()
1665             State->ExpectedFifoReads = State->ExpectedFifoWrites/2u;  in Spi_Ip_AsyncTransmit()
1667         State->ExpectedCmdFifoWrites = State->ExpectedFifoReads;  in Spi_Ip_AsyncTransmit()
1923         State->ExpectedFifoReads = State->ExpectedFifoWrites;  in Spi_Ip_DmaFastConfig()
1926             State->ExpectedFifoReads = State->ExpectedFifoWrites/2u;  in Spi_Ip_DmaFastConfig()
1928         State->ExpectedCmdFifoWrites = State->ExpectedFifoReads;  in Spi_Ip_DmaFastConfig()