331             if (State->CurrentTxFifoSlot > (State->ExpectedFifoWrites - State->TxIndex))  in Spi_Ip_TransferProcess()
333                 State->CurrentTxFifoSlot = State->ExpectedFifoWrites - State->TxIndex;  in Spi_Ip_TransferProcess()
335             if(State->CurrentTxFifoSlot != 0u)  in Spi_Ip_TransferProcess()
337                 Spi_Ip_WriteTxFifo(State->CurrentTxFifoSlot, Instance);  in Spi_Ip_TransferProcess()
339                 State->CurrentTxFifoSlot = 0u;  in Spi_Ip_TransferProcess()
1087         State->CurrentTxFifoSlot += NumberOfReads*2u;  in Spi_Ip_ReceiveData()
1091         State->CurrentTxFifoSlot += NumberOfReads;  in Spi_Ip_ReceiveData()
1521         State->CurrentTxFifoSlot = SPI_IP_FIFO_SIZE_U16;  in Spi_Ip_SyncTransmit()
1549             if (State->CurrentTxFifoSlot > (State->ExpectedFifoWrites - State->TxIndex))  in Spi_Ip_SyncTransmit()
1551                 State->CurrentTxFifoSlot = State->ExpectedFifoWrites - State->TxIndex;  in Spi_Ip_SyncTransmit()
1553             if (State->CurrentTxFifoSlot != 0u)  in Spi_Ip_SyncTransmit()
1555                 Spi_Ip_WriteTxFifo(State->CurrentTxFifoSlot, Instance);  in Spi_Ip_SyncTransmit()
1557                 State->CurrentTxFifoSlot = 0u;  in Spi_Ip_SyncTransmit()
1670         State->CurrentTxFifoSlot = SPI_IP_FIFO_SIZE_U16;  in Spi_Ip_AsyncTransmit()
1726 						if (State->CurrentTxFifoSlot > (State->ExpectedFifoWrites - State->TxIndex))  in Spi_Ip_AsyncTransmit()
1728 							State->CurrentTxFifoSlot = State->ExpectedFifoWrites - State->TxIndex;  in Spi_Ip_AsyncTransmit()
1730 						if (State->CurrentTxFifoSlot != 0u)  in Spi_Ip_AsyncTransmit()
1732 							Spi_Ip_WriteTxFifo(State->CurrentTxFifoSlot, Instance);  in Spi_Ip_AsyncTransmit()
1734 							State->CurrentTxFifoSlot = 0u;  in Spi_Ip_AsyncTransmit()
1758                         State->CurrentTxFifoSlot -= NumberOfWrites;  in Spi_Ip_AsyncTransmit()