Lines Matching refs:Base
283 SPI_Type* Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_TransferProcess() local
293 SrStatusRegister = Base->SR; in Spi_Ip_TransferProcess()
294 Base->SR &= 0xFFFF0000u; in Spi_Ip_TransferProcess()
304 … NumberOfReads = (uint16)(((Base->SR) & SPI_SR_RXCTR_MASK) >> SPI_SR_RXCTR_SHIFT); in Spi_Ip_TransferProcess()
316 … NumberOfWrites = (uint16)((Base->SREX) & SPI_SREX_CMDCTR_MASK) >> SPI_SREX_CMDCTR_SHIFT; in Spi_Ip_TransferProcess()
350 Base->MCR |= SPI_MCR_HALT_MASK; in Spi_Ip_TransferProcess()
354 Base->RSER = 0U; in Spi_Ip_TransferProcess()
371 SPI_Type* Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_CmdDmaTcdSGInit() local
388 DmaTcdList[1u].Value = (uint32)&Base->PUSHR.FIFO.CMD; /* dest address write*/ in Spi_Ip_CmdDmaTcdSGInit()
410 SPI_Type* Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_TxDmaTcdSGInit() local
427 DmaTcdList[1u].Value = (uint32)&Base->PUSHR.FIFO.TX; /* dest address write*/ in Spi_Ip_TxDmaTcdSGInit()
504 SPI_Type* Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_RxDmaTcdSGInit() local
520 DmaTcdList[0u].Value = (uint32)&Base->POPR; /* src address read */ in Spi_Ip_RxDmaTcdSGInit()
631 SPI_Type* Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_DmaConfig() local
745 DmaTcdList[1u].Value = (uint32)&Base->PUSHR.FIFO.TX; /* dest address write*/ in Spi_Ip_DmaConfig()
788 DmaTcdList[0u].Value = (uint32)&Base->POPR; /* src address read */ in Spi_Ip_DmaConfig()
980 const SPI_Type* Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_ReadRxFifo() local
986 Data = Base->POPR; in Spi_Ip_ReadRxFifo()
1021 SPI_Type* Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_WriteTxFifo() local
1057 Base->PUSHR.FIFO.TX = (uint16)Data; in Spi_Ip_WriteTxFifo()
1144 SPI_Type* Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_WriteCmdFifo() local
1156 Base->PUSHR.FIFO.CMD = State->PushrCmd & (~((uint16)(SPI_PUSHR_CONT_MASK>>16u))); in Spi_Ip_WriteCmdFifo()
1160 Base->PUSHR.FIFO.CMD = State->PushrCmd; in Spi_Ip_WriteCmdFifo()
1239 SPI_Type* Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_IrqDmaHandler() local
1250 SrStatusRegister = Base->SR; in Spi_Ip_IrqDmaHandler()
1251 Base->SR &= 0xFFFF0000u; in Spi_Ip_IrqDmaHandler()
1278 Base->MCR |= SPI_MCR_HALT_MASK; in Spi_Ip_IrqDmaHandler()
1282 Base->RSER = 0U; in Spi_Ip_IrqDmaHandler()
1320 SPI_Type* Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_SetUserAccess() local
1322 SET_USER_ACCESS_ALLOWED((uint32)Base,SPI_IP_PROT_MEM_U32); in Spi_Ip_SetUserAccess()
1336 SPI_Type* Base; in Spi_Ip_Init() local
1346 Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_Init()
1357 Base->MCR |= SPI_MCR_HALT_MASK; in Spi_Ip_Init()
1358 Base->MCR = PhyUnitConfigPtr->Mcr; in Spi_Ip_Init()
1385 SPI_Type* Base; in Spi_Ip_DeInit() local
1392 Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_DeInit()
1404 Base->MCR |= SPI_MCR_HALT_MASK; in Spi_Ip_DeInit()
1406 Base->MCR |= SPI_MCR_CLR_TXF_MASK | SPI_MCR_CLR_RXF_MASK; in Spi_Ip_DeInit()
1407 Base->MCR = 0x4001u; in Spi_Ip_DeInit()
1408 Base->MODE.CTAR[0] = 0x78000000u; in Spi_Ip_DeInit()
1409 Base->SR = 0xFFFF0000u; in Spi_Ip_DeInit()
1410 Base->RSER = 0u; in Spi_Ip_DeInit()
1411 Base->CTARE[0] = 0x1u; in Spi_Ip_DeInit()
1427 SPI_Type *Base; in Spi_Ip_SyncTransmit() local
1452 Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_SyncTransmit()
1469 Base->MCR |= SPI_MCR_CLR_TXF_MASK | SPI_MCR_CLR_RXF_MASK; in Spi_Ip_SyncTransmit()
1471 Base->SR = 0xFFFF0000u; in Spi_Ip_SyncTransmit()
1494 …Base->MODE.CTAR[0u] = ExternalDevice->Ctar[State->ClockMode] | SPI_CTAR_FMSZ(((uint32)State->Exter… in Spi_Ip_SyncTransmit()
1496 …Base->MODE.CTAR[0u] = ExternalDevice->Ctar | SPI_CTAR_FMSZ(((uint32)State->ExternalDevice->DeviceP… in Spi_Ip_SyncTransmit()
1501 …Base->CTARE[0u] = SPI_CTARE_FMSZE((((uint32)State->ExternalDevice->DeviceParams->FrameSize - 1u) >… in Spi_Ip_SyncTransmit()
1502 Base->PUSHR.FIFO.CMD = (PushrCmd | (uint16)(SPI_PUSHR_CTAS(0U)>>16u)); in Spi_Ip_SyncTransmit()
1504 …Base->CTARE[1u] = SPI_CTARE_FMSZE((((uint32)State->ExternalDevice->DeviceParams->FrameSize - 1u) >… in Spi_Ip_SyncTransmit()
1505 …Base->PUSHR.FIFO.CMD = (PushrCmd | (uint16)(SPI_PUSHR_CTAS(1U)>>16u)) & (~((uint16)(SPI_PUSHR_CONT… in Spi_Ip_SyncTransmit()
1508 …Base->MODE.CTAR[1u] = ExternalDevice->Ctar[State->ClockMode] | SPI_CTAR_FMSZ(((uint32)State->Exter… in Spi_Ip_SyncTransmit()
1510 …Base->MODE.CTAR[1u] = ExternalDevice->Ctar | SPI_CTAR_FMSZ(((uint32)State->ExternalDevice->DeviceP… in Spi_Ip_SyncTransmit()
1515 …Base->CTARE[0u] = ExternalDevice->Ctare | SPI_CTARE_FMSZE((((uint32)State->ExternalDevice->DeviceP… in Spi_Ip_SyncTransmit()
1529 … NumberOfWrites = (uint16)((Base->SREX) & SPI_SREX_CMDCTR_MASK) >> SPI_SREX_CMDCTR_SHIFT; in Spi_Ip_SyncTransmit()
1560 if(((Base->MCR) & SPI_MCR_HALT_MASK) == SPI_MCR_HALT_MASK) in Spi_Ip_SyncTransmit()
1562 Base->MCR &= ~SPI_MCR_HALT_MASK; in Spi_Ip_SyncTransmit()
1567 NumberOfReads = (uint16)(((Base->SR) & SPI_SR_RXCTR_MASK) >> SPI_SR_RXCTR_SHIFT); in Spi_Ip_SyncTransmit()
1591 Base->MCR |= SPI_MCR_HALT_MASK; in Spi_Ip_SyncTransmit()
1607 SPI_Type* Base; in Spi_Ip_AsyncTransmit() local
1631 Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_AsyncTransmit()
1672 Base->MCR |= SPI_MCR_CLR_TXF_MASK | SPI_MCR_CLR_RXF_MASK; in Spi_Ip_AsyncTransmit()
1674 Base->SR &= 0xFFFF0000u; in Spi_Ip_AsyncTransmit()
1681 …Base->MODE.CTAR[0u] = ExternalDevice->Ctar[State->ClockMode] | SPI_CTAR_FMSZ(((uint32)State->Exter… in Spi_Ip_AsyncTransmit()
1683 …Base->MODE.CTAR[0u] = ExternalDevice->Ctar | SPI_CTAR_FMSZ(((uint32)State->ExternalDevice->DeviceP… in Spi_Ip_AsyncTransmit()
1685 …Base->CTARE[0u] = ExternalDevice->Ctare | SPI_CTARE_FMSZE((((uint32)State->ExternalDevice->DeviceP… in Spi_Ip_AsyncTransmit()
1691 …Base->MODE.CTAR[0u] = (ExternalDevice->Ctar[State->ClockMode] & (~SPI_CTAR_SLAVE_FMSZ_MASK)) | SPI… in Spi_Ip_AsyncTransmit()
1693 …Base->MODE.CTAR[0u] = (ExternalDevice->Ctar & (~SPI_CTAR_SLAVE_FMSZ_MASK)) | SPI_CTAR_SLAVE_FMSZ((… in Spi_Ip_AsyncTransmit()
1706 Base->RSER = 0U; in Spi_Ip_AsyncTransmit()
1710 Base->RSER = SPI_RSER_TCF_RE(1) | SPI_RSER_TFUF_RE(1) | SPI_RSER_RFOF_RE(1); in Spi_Ip_AsyncTransmit()
1718 … NumberOfCmdWrites = (uint16)((Base->SREX) & SPI_SREX_CMDCTR_MASK) >> SPI_SREX_CMDCTR_SHIFT; in Spi_Ip_AsyncTransmit()
1741 … NumberOfWrites = (uint16)((Base->SR) & SPI_SR_TXCTR_MASK) >> SPI_SR_TXCTR_SHIFT; in Spi_Ip_AsyncTransmit()
1789 …Base->RSER = SPI_RSER_CMDFFF_RE(1) | SPI_RSER_CMDFFF_DIRS(1) | SPI_RSER_TFFF_RE(1) | SPI_RSER_TFFF… in Spi_Ip_AsyncTransmit()
1794 Base->MCR &= ~SPI_MCR_HALT_MASK; in Spi_Ip_AsyncTransmit()
1807 SPI_Type* Base; in Spi_Ip_AsyncTransmitFast() local
1821 Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_AsyncTransmitFast()
1859 Base->MCR |= SPI_MCR_CLR_TXF_MASK | SPI_MCR_CLR_RXF_MASK; in Spi_Ip_AsyncTransmitFast()
1861 Base->SR &= 0xFFFF0000u; in Spi_Ip_AsyncTransmitFast()
1877 …Base->MODE.CTAR[0u] = FastTransferCfg[0u].ExternalDevice->Ctar[State->ClockMode] | SPI_CTAR_FMSZ((… in Spi_Ip_AsyncTransmitFast()
1879 …Base->MODE.CTAR[0u] = FastTransferCfg[0u].ExternalDevice->Ctar | SPI_CTAR_FMSZ(((uint32)State->Ext… in Spi_Ip_AsyncTransmitFast()
1881 …Base->CTARE[0u] = FastTransferCfg[0u].ExternalDevice->Ctare | SPI_CTARE_FMSZE((((uint32)State->Ext… in Spi_Ip_AsyncTransmitFast()
1884 …Base->RSER = SPI_RSER_CMDFFF_RE(1u) | SPI_RSER_CMDFFF_DIRS(1u) | SPI_RSER_TFFF_RE(1u) | SPI_RSER_T… in Spi_Ip_AsyncTransmitFast()
1887 Base->MCR &= ~SPI_MCR_HALT_MASK; in Spi_Ip_AsyncTransmitFast()
2154 SPI_Type* Base; in Spi_Ip_Cancel() local
2160 Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_Cancel()
2169 Base->MCR |= SPI_MCR_HALT_MASK; in Spi_Ip_Cancel()
2171 Base->RSER = 0U; in Spi_Ip_Cancel()
2187 Base->MCR |= (SPI_MCR_CLR_RXF_MASK | SPI_MCR_CLR_TXF_MASK); in Spi_Ip_Cancel()
2204 SPI_Type* Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_IrqHandler() local
2211 IrqFlags = Base->SR & (SPI_SR_TCF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFUF_MASK); in Spi_Ip_IrqHandler()
2212 … IrqFlags &= Base->RSER & (SPI_RSER_TCF_RE_MASK | SPI_RSER_RFOF_RE_MASK | SPI_RSER_TFUF_RE_MASK); in Spi_Ip_IrqHandler()
2226 Base->SR &= 0xFFFF0000u; in Spi_Ip_IrqHandler()