321     const enet_buffer_config_t *buffCfg = bufferConfig;  in ENET_TxDescriptorsInit()  local
323     if (buffCfg == NULL)  in ENET_TxDescriptorsInit()
329     if (buffCfg->txRingLen < ENET_MIN_RINGLEN)  in ENET_TxDescriptorsInit()
335         (uint32_t)buffCfg->txDescStartAddrAlign & ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK;  in ENET_TxDescriptorsInit()
337         (uint32_t)buffCfg->txDescTailAddrAlign & ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK;  in ENET_TxDescriptorsInit()
340         ((uint32_t)buffCfg->txRingLen - 1U) & ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK;  in ENET_TxDescriptorsInit()
343     txbdPtr = (enet_tx_bd_struct_t *)(buffCfg->txDescStartAddrAlign);  in ENET_TxDescriptorsInit()
344     for (j = 0; j < buffCfg->txRingLen; j++)  in ENET_TxDescriptorsInit()
366     const enet_buffer_config_t *buffCfg = bufferConfig;  in ENET_RxDescriptorsInit()  local
369     if (buffCfg == NULL)  in ENET_RxDescriptorsInit()
391     if (buffCfg->rxRingLen < ENET_MIN_RINGLEN)  in ENET_RxDescriptorsInit()
398         (uint32_t)buffCfg->rxDescStartAddrAlign & ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK;  in ENET_RxDescriptorsInit()
400         (uint32_t)buffCfg->rxDescTailAddrAlign & ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK;  in ENET_RxDescriptorsInit()
402         ((uint32_t)buffCfg->rxRingLen - 1U) & ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK;  in ENET_RxDescriptorsInit()
404     reg |= ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ(buffCfg->rxBuffSizeAlign >> ENET_RXBUFF_IGNORELSB_BITS);  in ENET_RxDescriptorsInit()
408     rxbdPtr = (enet_rx_bd_struct_t *)(buffCfg->rxDescStartAddrAlign);  in ENET_RxDescriptorsInit()
410     for (j = 0; j < buffCfg->rxRingLen; j++)  in ENET_RxDescriptorsInit()
422             rxbdPtr->rdes0 = buffCfg->rxBufferStartAddr[index];  in ENET_RxDescriptorsInit()
426                 rxbdPtr->rdes2 = buffCfg->rxBufferStartAddr[index + 1U];  in ENET_RxDescriptorsInit()