Lines Matching refs:U
114 0U, /* clkConfigId */
117 0U, /* ircoscsCount */
126 0U, /* pcfsCount */
135 0U, /* enable */
136 0U, /* Enable regulator */
137 0U, /* Ircosc range */
138 0U, /* Ircosc enable in VLP mode */
139 0U, /* Ircosc enable in STOP mode */
144 0U, /* enable */
145 0U, /* Enable regulator */
146 0U, /* Ircosc range */
147 0U, /* Ircosc enable in VLP mode */
148 0U, /* Ircosc enable in STOP mode */
155 #if CLOCK_IP_XOSCS_NO > 0U
161 0U, /* bypassOption: Xosc use crystal */
164 0U, /* Gain value */
165 0U, /* Monitor type */
173 #if CLOCK_IP_PLLS_NO > 0U
178 0U, /* Bypass */
180 0U, /* multiplier */
181 0U, /* postdivider */
182 0U, /* numeratorFracLoopDiv */
185 … 0U, /* Modulation type: Spread spectrum modulation not bypassed */
186 0U, /* modulationPeriod */
187 0U, /* incrementStep */
188 0U, /* sigmaDelta */
189 0U, /* ditherControl */
190 0U, /* ditherControlValue */
191 0U, /* Monitor type */
193 0U,
194 0U,
195 0U,
205 0U, /* Bypass */
207 0U, /* multiplier */
208 0U, /* postdivider */
209 0U, /* numeratorFracLoopDiv */
211 0U, /* ModulationBypass */
212 0U, /* Modulation type: Spread spectrum modulation bypassed */
213 0U, /* modulationPeriod */
214 0U, /* incrementStep */
215 0U, /* sigmaDelta */
216 0U, /* ditherControl */
217 0U, /* ditherControlValue */
218 0U, /* Monitor type */
220 0U,
221 0U,
222 0U,
232 0U, /* Bypass */
234 0U, /* multiplier */
235 0U, /* postdivider */
236 0U, /* numeratorFracLoopDiv */
239 … 0U, /* Modulation type: Spread spectrum modulation not bypassed */
240 0U, /* modulationPeriod */
241 0U, /* incrementStep */
242 0U, /* sigmaDelta */
243 0U, /* ditherControl */
244 0U, /* ditherControlValue */
245 0U, /* Monitor type */
247 0U,
248 0U,
249 0U,
259 0U, /* Bypass */
262 0U, /* postdivider */
263 0U, /* numeratorFracLoopDiv */
264 0U, /* mulFactorDiv */
265 0U, /* ModulationBypass */
266 0U, /* Modulation type: Spread spectrum modulation bypassed */
267 0U, /* modulationPeriod */
268 0U, /* incrementStep */
269 0U, /* sigmaDelta */
270 0U, /* ditherControl */
271 0U, /* ditherControlValue */
272 0U, /* Monitor type */
274 0U,
275 0U,
276 0U,
286 0U, /* Bypass */
289 0U, /* postdivider */
290 0U, /* numeratorFracLoopDiv */
291 0U, /* mulFactorDiv */
292 0U, /* ModulationBypass */
293 0U, /* Modulation type: Spread spectrum modulation bypassed */
294 0U, /* modulationPeriod */
295 0U, /* incrementStep */
296 0U, /* sigmaDelta */
297 0U, /* ditherControl */
298 0U, /* ditherControlValue */
299 0U, /* Monitor type */
301 0U,
302 0U,
303 0U,
315 #if CLOCK_IP_SELECTORS_NO > 0U
768 #if CLOCK_IP_DIVIDERS_NO > 0U
773 0U,
783 0U,
793 0U,
803 0U,
813 0U,
823 0U,
831 0U, /* value */
833 0U,
841 0U, /* value */
843 0U,
853 0U,
861 0U, /* value */
863 0U,
873 0U,
881 0U, /* value */
883 0U,
891 0U, /* value */
893 0U,
903 0U,
911 0U, /* value */
913 0U,
923 0U,
933 0U,
943 0U,
953 0U,
963 0U,
973 0U,
983 0U,
993 0U,
1003 0U,
1013 0U,
1023 0U,
1033 0U,
1043 0U,
1053 0U,
1063 0U,
1073 0U,
1083 0U,
1093 0U,
1103 0U,
1113 0U,
1123 0U,
1133 0U,
1143 0U,
1153 0U,
1163 0U,
1173 0U,
1183 0U,
1193 0U,
1203 0U,
1213 0U,
1223 0U,
1233 0U,
1243 0U,
1253 0U,
1263 0U,
1273 0U,
1283 0U,
1293 0U,
1303 0U,
1313 0U,
1323 0U,
1333 0U,
1343 0U,
1353 0U,
1363 0U,
1373 0U,
1383 0U,
1393 0U,
1403 0U,
1413 0U,
1423 0U,
1433 0U,
1443 0U,
1453 0U,
1463 0U,
1473 0U,
1483 0U,
1493 0U,
1503 0U,
1513 0U,
1523 0U,
1533 0U,
1543 0U,
1553 0U,
1563 0U,
1573 0U,
1583 0U,
1593 0U,
1603 0U,
1613 0U,
1622 #if CLOCK_IP_DIVIDER_TRIGGERS_NO > 0U
1643 #if CLOCK_IP_FRACTIONAL_DIVIDERS_NO > 0U
1682 0U, /* fractional part */
1770 0U, /* fractional part */
1781 #if CLOCK_IP_EXT_CLKS_NO > 0U
1842 #if CLOCK_IP_GATES_NO > 0U
2454 0U,
2455 0U,
2457 0U,
2461 0U,
2462 0U,
2464 0U,
2468 0U,
2469 0U,
2471 0U,
2475 0U,
2476 0U,
2478 0U,
2482 0U,
2483 0U,
2485 0U,
2489 0U,
2490 0U,
2492 0U,
2496 0U,
2497 0U,
2499 0U,
2503 0U,
2504 0U,
2506 0U,
2510 0U,
2511 0U,
2513 0U,
2517 0U,
2518 0U,
2520 0U,
2524 0U,
2525 0U,
2527 0U,
2532 #if CLOCK_IP_CMUS_NO > 0U
2535 0U, /*Enable/disable clock monitor SMU__CMU_FC */
2544 0U, /* Start index in register values array */
2545 0U, /* End index in register values array */
2552 0U, /*Enable/disable clock monitor CMU_FC_0 */
2561 0U, /* Start index in register values array */
2562 0U, /* End index in register values array */
2569 0U, /*Enable/disable clock monitor CMU_FC_1 */
2578 0U, /* Start index in register values array */
2579 0U, /* End index in register values array */
2586 0U, /*Enable/disable clock monitor CMU_FC_2A */
2595 0U, /* Start index in register values array */
2596 0U, /* End index in register values array */
2603 0U, /*Enable/disable clock monitor CMU_FC_2B */
2612 0U, /* Start index in register values array */
2613 0U, /* End index in register values array */
2620 0U, /*Enable/disable clock monitor CMU_FC_2C */
2629 0U, /* Start index in register values array */
2630 0U, /* End index in register values array */
2637 0U, /*Enable/disable clock monitor CMU_FC_3 */
2646 0U, /* Start index in register values array */
2647 0U, /* End index in register values array */
2654 0U, /*Enable/disable clock monitor CMU_FC_4 */
2663 0U, /* Start index in register values array */
2664 0U, /* End index in register values array */
2671 0U, /*Enable/disable clock monitor CMU_FC_5 */
2680 0U, /* Start index in register values array */
2681 0U, /* End index in register values array */
2688 0U, /*Enable/disable clock monitor CMU_FC_6 */
2697 0U, /* Start index in register values array */
2698 0U, /* End index in register values array */
2705 0U, /*Enable/disable clock monitor CE_CMU_FC_0 */
2714 0U, /* Start index in register values array */
2715 0U, /* End index in register values array */
2722 0U, /*Enable/disable clock monitor CE_CMU_FC_1 */
2731 0U, /* Start index in register values array */
2732 0U, /* End index in register values array */
2739 0U, /*Enable/disable clock monitor CE_CMU_FC_2 */
2748 0U, /* Start index in register values array */
2749 0U, /* End index in register values array */
2756 0U, /*Enable/disable clock monitor CMU_FC_DEBUG_1 */
2765 0U, /* Start index in register values array */
2766 0U, /* End index in register values array */
2773 0U, /*Enable/disable clock monitor CMU_FC_DEBUG_2 */
2782 0U, /* Start index in register values array */
2783 0U, /* End index in register values array */
2790 0U,
2791 0U,
2792 0U,
2794 0U, /* Start index in register values array */
2795 0U, /* End index in register values array */
2802 0U,
2803 0U,
2804 0U,
2806 0U, /* Start index in register values array */
2807 0U, /* End index in register values array */
2814 0U,
2815 0U,
2816 0U,
2818 0U, /* Start index in register values array */
2819 0U, /* End index in register values array */
2826 0U,
2827 0U,
2828 0U,
2830 0U, /* Start index in register values array */
2831 0U, /* End index in register values array */
2838 0U,
2839 0U,
2840 0U,
2842 0U, /* Start index in register values array */
2843 0U, /* End index in register values array */
2850 0U,
2851 0U,
2852 0U,
2854 0U, /* Start index in register values array */
2855 0U, /* End index in register values array */
2862 0U,
2863 0U,
2864 0U,
2866 0U, /* Start index in register values array */
2867 0U, /* End index in register values array */
2874 0U,
2875 0U,
2876 0U,
2878 0U, /* Start index in register values array */
2879 0U, /* End index in register values array */
2886 0U,
2887 0U,
2888 0U,
2890 0U, /* Start index in register values array */
2891 0U, /* End index in register values array */
2898 0U,
2899 0U,
2900 0U,
2902 0U, /* Start index in register values array */
2903 0U, /* End index in register values array */
2910 0U,
2914 0U,
2922 0U,