42 #define MMAU__A10 0xF0004010UL /*!< Accumulator register pair A10        */  macro
412     *((uint64_t volatile *)(MMAU__REGRW | MMAU__A10)) = dval;  in MMAU_ulda_d()
429     return *((uint64_t volatile *)(MMAU__UMUL | MMAU__A10));  in MMAU_d_umul_ll()
447     return *((uint64_t volatile *)(MMAU__UMULD | MMAU__A10));  in MMAU_d_umul_dl()
466     return *((uint64_t volatile *)(MMAU__UMULD | MMAU__A10 | MMAU__SAT));  in MMAU_d_umuls_dl()
483     return *((uint64_t volatile *)(MMAU__UMULDA | MMAU__A10));  in MMAU_d_umula_l()
502     return *((uint64_t volatile *)(MMAU__UMULDA | MMAU__A10 | MMAU__SAT));  in MMAU_d_umulas_l()
522     return *((uint64_t volatile *)(MMAU__UMAC | MMAU__A10));  in MMAU_d_umac_ll()
543     return *((uint64_t volatile *)(MMAU__UMAC | MMAU__A10 | MMAU__SAT));  in MMAU_d_umacs_ll()
564     return *((uint64_t volatile *)(MMAU__UMACD | MMAU__A10));  in MMAU_d_umac_dl()
586     return *((uint64_t volatile *)(MMAU__UMACD | MMAU__A10 | MMAU__SAT));  in MMAU_d_umacs_dl()
607     return *((uint64_t volatile *)(MMAU__UMACDA | MMAU__A10));  in MMAU_d_umaca_dl()
629     return *((uint64_t volatile *)(MMAU__UMACDA | MMAU__A10 | MMAU__SAT));  in MMAU_d_umacas_dl()
665     return *((uint64_t volatile *)(MMAU__UDIVD | MMAU__A10));  in MMAU_d_udiv_dl()
683     return *((uint64_t volatile *)(MMAU__UDIVDD | MMAU__A10));  in MMAU_d_udiv_dd()
700     return *((uint64_t volatile *)(MMAU__UDIVDA | MMAU__A10));  in MMAU_d_udiva_l()
717     return *((uint64_t volatile *)(MMAU__UDIVDDA | MMAU__A10));  in MMAU_d_udiva_d()
798     *((int64_t volatile *)(MMAU__REGRW | MMAU__A10)) = dval;  in MMAU_slda_d()
815     return *((int64_t volatile *)(MMAU__SMUL | MMAU__A10));  in MMAU_d_smul_ll()
833     return *((int64_t volatile *)(MMAU__SMULD | MMAU__A10));  in MMAU_d_smul_dl()
852     return *((int64_t volatile *)(MMAU__SMULD | MMAU__A10 | MMAU__SAT));  in MMAU_d_smuls_dl()
869     return *((int64_t volatile *)(MMAU__SMULDA | MMAU__A10));  in MMAU_d_smula_l()
888     return *((int64_t volatile *)(MMAU__SMULDA | MMAU__A10 | MMAU__SAT));  in MMAU_d_smulas_l()
908     return *((int64_t volatile *)(MMAU__SMAC | MMAU__A10));  in MMAU_d_smac_ll()
929     return *((int64_t volatile *)(MMAU__SMAC | MMAU__A10 | MMAU__SAT));  in MMAU_d_smacs_ll()
950     return *((int64_t volatile *)(MMAU__SMACD | MMAU__A10));  in MMAU_d_smac_dl()
974     return *((int64_t volatile *)(MMAU__SMACD | MMAU__A10 | MMAU__SAT));  in MMAU_d_smacs_dl()
994     return *((int64_t volatile *)(MMAU__SMACDA | MMAU__A10));  in MMAU_d_smaca_dl()
1018     return *((int64_t volatile *)(MMAU__SMACDA | MMAU__A10 | MMAU__SAT));  in MMAU_d_smacas_dl()
1073     return *((int64_t volatile *)(MMAU__SDIVD | MMAU__A10));  in MMAU_d_sdiv_dl()
1092     return *((int64_t volatile *)(MMAU__SDIVD | MMAU__A10 | MMAU__SAT));  in MMAU_d_sdivs_dl()
1110     return *((int64_t volatile *)(MMAU__SDIVDD | MMAU__A10));  in MMAU_d_sdiv_dd()
1129     return *((int64_t volatile *)(MMAU__SDIVDD | MMAU__A10 | MMAU__SAT));  in MMAU_d_sdivs_dd()
1146     return *((int64_t volatile *)(MMAU__SDIVDA | MMAU__A10));  in MMAU_d_sdiva_l()
1164     return *((int64_t volatile *)(MMAU__SDIVDA | MMAU__A10 | MMAU__SAT));  in MMAU_d_sdivas_l()
1181     return *((int64_t volatile *)(MMAU__SDIVDDA | MMAU__A10));  in MMAU_d_sdiva_d()
1199     return *((int64_t volatile *)(MMAU__SDIVDDA | MMAU__A10 | MMAU__SAT));  in MMAU_d_sdivas_d()
1219     *((frac64_t volatile *)(MMAU__REGRW | MMAU__A10)) = dval;  in MMAU_lda_d()
1273     return *((frac64_t volatile *)(MMAU__QMUL | MMAU__A10));  in MMAU_d_mul_ll()
1294     return *((frac64_t volatile *)(MMAU__QMUL | MMAU__A10 | MMAU__SAT));  in MMAU_d_muls_ll()
1312     return *((frac64_t volatile *)(MMAU__QMULD | MMAU__A10));  in MMAU_d_mul_dl()
1333     return *((frac64_t volatile *)(MMAU__QMULD | MMAU__A10 | MMAU__SAT));  in MMAU_d_muls_dl()
1350     return *((frac64_t volatile *)(MMAU__QMULDA | MMAU__A10));  in MMAU_d_mula_l()
1371     return *((frac64_t volatile *)(MMAU__QMULDA | MMAU__A10 | MMAU__SAT));  in MMAU_d_mulas_l()
1466     return *((frac64_t volatile *)(MMAU__QMAC | MMAU__A10));  in MMAU_d_mac_ll()
1489     return *((frac64_t volatile *)(MMAU__QMAC | MMAU__A10 | MMAU__SAT));  in MMAU_d_macs_ll()
1510     return *((frac64_t volatile *)(MMAU__QMACD | MMAU__A10));  in MMAU_d_mac_dl()
1534     return *((frac64_t volatile *)(MMAU__QMACD | MMAU__A10 | MMAU__SAT));  in MMAU_d_macs_dl()
1555     return *((frac64_t volatile *)(MMAU__QMACDA | MMAU__A10));  in MMAU_d_maca_dl()
1579     return *((frac64_t volatile *)(MMAU__QMACDA | MMAU__A10 | MMAU__SAT));  in MMAU_d_macas_dl()
1782     return *((frac64_t volatile *)(MMAU__QDIVD | MMAU__A10));  in MMAU_d_div_dl()
1803     return *((frac64_t volatile *)(MMAU__QDIVD | MMAU__A10 | MMAU__SAT));  in MMAU_d_divs_dl()
1820     return *((frac64_t volatile *)(MMAU__QDIVDA | MMAU__A10));  in MMAU_d_diva_l()