424                       const ftm_chnl_pwm_signal_param_t *chnlParams,  in FTM_SetupPwm()  argument
430     assert(NULL != chnlParams);  in FTM_SetupPwm()
467         if (((uint8_t)chnlParams->chnlNumber >= (uint8_t)FSL_FEATURE_FTM_CHANNEL_COUNTn(base)) ||  in FTM_SetupPwm()
473         if (chnlParams->dutyCyclePercent > 100U)  in FTM_SetupPwm()
478         if (chnlParams->dutyCyclePercent == 100U)  in FTM_SetupPwm()
485             cnv = (mod * chnlParams->dutyCyclePercent) / 100U;  in FTM_SetupPwm()
491             reg = base->CONTROLS[chnlParams->chnlNumber].CnSC;  in FTM_SetupPwm()
495             reg |= (uint32_t)chnlParams->level << FTM_CnSC_ELSA_SHIFT;  in FTM_SetupPwm()
501             base->CONTROLS[chnlParams->chnlNumber].CnSC = reg;  in FTM_SetupPwm()
503             base->CONTROLS[chnlParams->chnlNumber].CnV = cnv;  in FTM_SetupPwm()
506             FTM_SetPwmOutputEnable(base, chnlParams->chnlNumber, true);  in FTM_SetupPwm()
512 …   if (((uint32_t)chnlParams->chnlNumber) >= ((uint32_t)FSL_FEATURE_FTM_CHANNEL_COUNTn(base) / 2U))  in FTM_SetupPwm()
528                 if ((chnlParams->firstEdgeDelayPercent + chnlParams->dutyCyclePercent) > 100U)  in FTM_SetupPwm()
533                 cnvFirstEdge = (mod * chnlParams->firstEdgeDelayPercent) / 100U;  in FTM_SetupPwm()
537             reg = base->CONTROLS[((uint32_t)chnlParams->chnlNumber) * 2U].CnSC;  in FTM_SetupPwm()
541             reg |= (uint32_t)chnlParams->level << FTM_CnSC_ELSA_SHIFT;  in FTM_SetupPwm()
544             base->CONTROLS[((uint32_t)chnlParams->chnlNumber) * 2U].CnSC = reg;  in FTM_SetupPwm()
547             reg = base->CONTROLS[(((uint32_t)chnlParams->chnlNumber) * 2U) + 1U].CnSC;  in FTM_SetupPwm()
551             reg |= (uint32_t)chnlParams->level << FTM_CnSC_ELSA_SHIFT;  in FTM_SetupPwm()
554             base->CONTROLS[(((uint32_t)chnlParams->chnlNumber) * 2U) + 1U].CnSC = reg;  in FTM_SetupPwm()
558 …<< (FTM_COMBINE_COMBINE0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * (uint32_t)chnlParams->chnlNumber)));  in FTM_SetupPwm()
561             base->CONTROLS[((uint32_t)chnlParams->chnlNumber) * 2U].CnV        = cnvFirstEdge;  in FTM_SetupPwm()
562             base->CONTROLS[(((uint32_t)chnlParams->chnlNumber) * 2U) + 1U].CnV = cnvFirstEdge + cnv;  in FTM_SetupPwm()
566 …   FTM_SetPwmOutputEnable(base, (ftm_chnl_t)(uint8_t)((uint8_t)chnlParams->chnlNumber * 2U), true);  in FTM_SetupPwm()
567 …FTM_SetPwmOutputEnable(base, (ftm_chnl_t)(uint8_t)((uint8_t)chnlParams->chnlNumber * 2U + 1U), tru…  in FTM_SetupPwm()
571 …         FTM_SetComplementaryEnable(base, chnlParams->chnlNumber, chnlParams->enableComplementary);  in FTM_SetupPwm()
573             FTM_SetDeadTimeEnable(base, chnlParams->chnlNumber, chnlParams->enableDeadtime);  in FTM_SetupPwm()
575         chnlParams++;  in FTM_SetupPwm()
691                           const ftm_chnl_pwm_config_param_t *chnlParams,  in FTM_SetupPwmMode()  argument
695     assert(chnlParams != NULL);  in FTM_SetupPwmMode()
728             reg = base->CONTROLS[chnlParams->chnlNumber].CnSC;  in FTM_SetupPwmMode()
732             reg |= (uint32_t)chnlParams->level << FTM_CnSC_ELSA_SHIFT;  in FTM_SetupPwmMode()
738             base->CONTROLS[chnlParams->chnlNumber].CnSC = reg;  in FTM_SetupPwmMode()
740             base->CONTROLS[chnlParams->chnlNumber].CnV = chnlParams->dutyValue;  in FTM_SetupPwmMode()
743             FTM_SetPwmOutputEnable(base, chnlParams->chnlNumber, true);  in FTM_SetupPwmMode()
749 … if (((uint32_t)chnlParams->chnlNumber) >= (((uint32_t)FSL_FEATURE_FTM_CHANNEL_COUNTn(base)) / 2U))  in FTM_SetupPwmMode()
760                 cnvFirstEdge = (mod - chnlParams->dutyValue) / 2U;  in FTM_SetupPwmMode()
765                 if (chnlParams->firstEdgeValue > mod)  in FTM_SetupPwmMode()
769                 cnvFirstEdge = chnlParams->firstEdgeValue;  in FTM_SetupPwmMode()
773             if (chnlParams->dutyValue == 0U)  in FTM_SetupPwmMode()
780             reg = base->CONTROLS[((uint32_t)chnlParams->chnlNumber) * 2U].CnSC;  in FTM_SetupPwmMode()
784             reg |= (uint32_t)chnlParams->level << FTM_CnSC_ELSA_SHIFT;  in FTM_SetupPwmMode()
787             base->CONTROLS[((uint32_t)chnlParams->chnlNumber) * 2U].CnSC = reg;  in FTM_SetupPwmMode()
790             reg = base->CONTROLS[(((uint32_t)chnlParams->chnlNumber) * 2U) + 1U].CnSC;  in FTM_SetupPwmMode()
794             reg |= (uint32_t)chnlParams->level << FTM_CnSC_ELSA_SHIFT;  in FTM_SetupPwmMode()
797             base->CONTROLS[(((uint32_t)chnlParams->chnlNumber) * 2U) + 1U].CnSC = reg;  in FTM_SetupPwmMode()
801 …<< (FTM_COMBINE_COMBINE0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * (uint32_t)chnlParams->chnlNumber)));  in FTM_SetupPwmMode()
804             base->CONTROLS[((uint32_t)chnlParams->chnlNumber) * 2U].CnV        = cnvFirstEdge;  in FTM_SetupPwmMode()
805 …base->CONTROLS[(((uint32_t)chnlParams->chnlNumber) * 2U) + 1U].CnV = cnvFirstEdge + chnlParams->du…  in FTM_SetupPwmMode()
809 …   FTM_SetPwmOutputEnable(base, (ftm_chnl_t)(uint8_t)((uint8_t)chnlParams->chnlNumber * 2U), true);  in FTM_SetupPwmMode()
810 …FTM_SetPwmOutputEnable(base, (ftm_chnl_t)(uint8_t)((uint8_t)chnlParams->chnlNumber * 2U + 1U), tru…  in FTM_SetupPwmMode()
814 …         FTM_SetComplementaryEnable(base, chnlParams->chnlNumber, chnlParams->enableComplementary);  in FTM_SetupPwmMode()
816             FTM_SetDeadTimeEnable(base, chnlParams->chnlNumber, chnlParams->enableDeadtime);  in FTM_SetupPwmMode()
818         chnlParams++;  in FTM_SetupPwmMode()