Lines Matching refs:PLL0SSCG1

1038     if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) != 0UL) /* normal mode */  in pllFindSel()
1165     if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) != 0UL)  in findPll0MMult()
1168 …(float)(uint32_t)((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EX…  in findPll0MMult()
1172         mMult_int   = ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U);  in findPll0MMult()
1605         Setup.pllsscg[1] = SYSCON->PLL0SSCG1;  in CLOCK_GetPLL0OutClockRate()
1710     SYSCON->PLL0SSCG1 = pSetup->pllsscg[1];  in CLOCK_SetupPLL0Prec()
1711     SYSCON->PLL0SSCG1 =  in CLOCK_SetupPLL0Prec()
1719         if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) != 0UL) /* normal mode */  in CLOCK_SetupPLL0Prec()
1791     SYSCON->PLL0SSCG1 = pSetup->pllsscg[1];  in CLOCK_SetPLL0Freq()
1792     SYSCON->PLL0SSCG1 =  in CLOCK_SetPLL0Freq()
1800         if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) != 0UL) /* normal mode */  in CLOCK_SetPLL0Freq()
1967 …SYSCON->PLL0SSCG1 = mdec | (1UL << SYSCON_PLL0SSCG1_MREQ_SHIFT); /* select non sscg MDEC value, as…  in CLOCK_SetupPLL0Mult()