Lines Matching refs:flexioBase
65 return FLEXIO_GetInstance(base->flexioBase); in FLEXIO_SPI_GetInstance()
204 ctrlReg = base->flexioBase->CTRL; in FLEXIO_SPI_MasterInit()
213 base->flexioBase->CTRL = ctrlReg; in FLEXIO_SPI_MasterInit()
236 FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig); in FLEXIO_SPI_MasterInit()
256 FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig); in FLEXIO_SPI_MasterInit()
282 FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig); in FLEXIO_SPI_MasterInit()
302 FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[1], &timerConfig); in FLEXIO_SPI_MasterInit()
312 base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = 0; in FLEXIO_SPI_MasterDeinit()
313 base->flexioBase->SHIFTCTL[base->shifterIndex[0]] = 0; in FLEXIO_SPI_MasterDeinit()
314 base->flexioBase->SHIFTCFG[base->shifterIndex[1]] = 0; in FLEXIO_SPI_MasterDeinit()
315 base->flexioBase->SHIFTCTL[base->shifterIndex[1]] = 0; in FLEXIO_SPI_MasterDeinit()
316 base->flexioBase->TIMCFG[base->timerIndex[0]] = 0; in FLEXIO_SPI_MasterDeinit()
317 base->flexioBase->TIMCMP[base->timerIndex[0]] = 0; in FLEXIO_SPI_MasterDeinit()
318 base->flexioBase->TIMCTL[base->timerIndex[0]] = 0; in FLEXIO_SPI_MasterDeinit()
319 base->flexioBase->TIMCFG[base->timerIndex[1]] = 0; in FLEXIO_SPI_MasterDeinit()
320 base->flexioBase->TIMCMP[base->timerIndex[1]] = 0; in FLEXIO_SPI_MasterDeinit()
321 base->flexioBase->TIMCTL[base->timerIndex[1]] = 0; in FLEXIO_SPI_MasterDeinit()
408 ctrlReg = base->flexioBase->CTRL; in FLEXIO_SPI_SlaveInit()
417 base->flexioBase->CTRL = ctrlReg; in FLEXIO_SPI_SlaveInit()
439 FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig); in FLEXIO_SPI_SlaveInit()
459 FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig); in FLEXIO_SPI_SlaveInit()
489 FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig); in FLEXIO_SPI_SlaveInit()
543 FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[0]); in FLEXIO_SPI_EnableInterrupts()
547 FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[1]); in FLEXIO_SPI_EnableInterrupts()
565 FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[0]); in FLEXIO_SPI_DisableInterrupts()
569 FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[1]); in FLEXIO_SPI_DisableInterrupts()
585 FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1UL << base->shifterIndex[0], enable); in FLEXIO_SPI_EnableDMA()
590 FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1UL << base->shifterIndex[1], enable); in FLEXIO_SPI_EnableDMA()
605 uint32_t shifterStatus = FLEXIO_GetShifterStatusFlags(base->flexioBase); in FLEXIO_SPI_GetStatusFlags()
628 FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1UL << base->shifterIndex[0]); in FLEXIO_SPI_ClearStatusFlags()
632 FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1UL << base->shifterIndex[1]); in FLEXIO_SPI_ClearStatusFlags()
647 FLEXIO_Type *flexioBase = base->flexioBase; in FLEXIO_SPI_MasterSetBaudRate() local
653 timerCmp = (uint16_t)(flexioBase->TIMCMP[base->timerIndex[0]]); in FLEXIO_SPI_MasterSetBaudRate()
657 flexioBase->TIMCMP[base->timerIndex[0]] = timerCmp; in FLEXIO_SPI_MasterSetBaudRate()
772 uint16_t timerCmp = (uint16_t)(base->flexioBase->TIMCMP[base->timerIndex[0]]); in FLEXIO_SPI_MasterTransferBlocking()
817 base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; in FLEXIO_SPI_MasterTransferBlocking()
969 uint16_t timerCmp = (uint16_t)base->flexioBase->TIMCMP[base->timerIndex[0]]; in FLEXIO_SPI_MasterTransferNonBlocking()
1020 base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; in FLEXIO_SPI_MasterTransferNonBlocking()
1265 base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; in FLEXIO_SPI_SlaveTransferNonBlocking()