Lines Matching refs:BME_UBFX32

239 #define ADC_BRD_SC1_ADCH(base, index) (BME_UBFX32(&ADC_SC1_REG(base, index), ADC_SC1_ADCH_SHIFT, AD…
260 #define ADC_BRD_SC1_DIFF(base, index) (BME_UBFX32(&ADC_SC1_REG(base, index), ADC_SC1_DIFF_SHIFT, AD…
280 #define ADC_BRD_SC1_AIEN(base, index) (BME_UBFX32(&ADC_SC1_REG(base, index), ADC_SC1_AIEN_SHIFT, AD…
307 #define ADC_BRD_SC1_COCO(base, index) (BME_UBFX32(&ADC_SC1_REG(base, index), ADC_SC1_COCO_SHIFT, AD…
358 #define ADC_BRD_CFG1_ADICLK(base) (BME_UBFX32(&ADC_CFG1_REG(base), ADC_CFG1_ADICLK_SHIFT, ADC_CFG1_…
383 #define ADC_BRD_CFG1_MODE(base) (BME_UBFX32(&ADC_CFG1_REG(base), ADC_CFG1_MODE_SHIFT, ADC_CFG1_MODE…
408 #define ADC_BRD_CFG1_ADLSMP(base) (BME_UBFX32(&ADC_CFG1_REG(base), ADC_CFG1_ADLSMP_SHIFT, ADC_CFG1_…
429 #define ADC_BRD_CFG1_ADIV(base) (BME_UBFX32(&ADC_CFG1_REG(base), ADC_CFG1_ADIV_SHIFT, ADC_CFG1_ADIV…
450 #define ADC_BRD_CFG1_ADLPC(base) (BME_UBFX32(&ADC_CFG1_REG(base), ADC_CFG1_ADLPC_SHIFT, ADC_CFG1_AD…
505 #define ADC_BRD_CFG2_ADLSTS(base) (BME_UBFX32(&ADC_CFG2_REG(base), ADC_CFG2_ADLSTS_SHIFT, ADC_CFG2_…
527 #define ADC_BRD_CFG2_ADHSC(base) (BME_UBFX32(&ADC_CFG2_REG(base), ADC_CFG2_ADHSC_SHIFT, ADC_CFG2_AD…
554 #define ADC_BRD_CFG2_ADACKEN(base) (BME_UBFX32(&ADC_CFG2_REG(base), ADC_CFG2_ADACKEN_SHIFT, ADC_CFG…
573 #define ADC_BRD_CFG2_MUXSEL(base) (BME_UBFX32(&ADC_CFG2_REG(base), ADC_CFG2_MUXSEL_SHIFT, ADC_CFG2_…
638 #define ADC_BRD_R_D(base, index) (BME_UBFX32(&ADC_R_REG(base, index), ADC_R_D_SHIFT, ADC_R_D_WIDTH))
681 #define ADC_BRD_CV1_CV(base) (BME_UBFX32(&ADC_CV1_REG(base), ADC_CV1_CV_SHIFT, ADC_CV1_CV_WIDTH))
728 #define ADC_BRD_CV2_CV(base) (BME_UBFX32(&ADC_CV2_REG(base), ADC_CV2_CV_SHIFT, ADC_CV2_CV_WIDTH))
783 #define ADC_BRD_SC2_REFSEL(base) (BME_UBFX32(&ADC_SC2_REG(base), ADC_SC2_REFSEL_SHIFT, ADC_SC2_REFS…
801 #define ADC_BRD_SC2_DMAEN(base) (BME_UBFX32(&ADC_SC2_REG(base), ADC_SC2_DMAEN_SHIFT, ADC_SC2_DMAEN_…
823 #define ADC_BRD_SC2_ACREN(base) (BME_UBFX32(&ADC_SC2_REG(base), ADC_SC2_ACREN_SHIFT, ADC_SC2_ACREN_…
847 #define ADC_BRD_SC2_ACFGT(base) (BME_UBFX32(&ADC_SC2_REG(base), ADC_SC2_ACFGT_SHIFT, ADC_SC2_ACFGT_…
866 #define ADC_BRD_SC2_ACFE(base) (BME_UBFX32(&ADC_SC2_REG(base), ADC_SC2_ACFE_SHIFT, ADC_SC2_ACFE_WID…
889 #define ADC_BRD_SC2_ADTRG(base) (BME_UBFX32(&ADC_SC2_REG(base), ADC_SC2_ADTRG_SHIFT, ADC_SC2_ADTRG_…
910 #define ADC_BRD_SC2_ADACT(base) (BME_UBFX32(&ADC_SC2_REG(base), ADC_SC2_ADACT_SHIFT, ADC_SC2_ADACT_…
956 #define ADC_BRD_SC3_AVGS(base) (BME_UBFX32(&ADC_SC3_REG(base), ADC_SC3_AVGS_SHIFT, ADC_SC3_AVGS_WID…
975 #define ADC_BRD_SC3_AVGE(base) (BME_UBFX32(&ADC_SC3_REG(base), ADC_SC3_AVGE_SHIFT, ADC_SC3_AVGE_WID…
996 #define ADC_BRD_SC3_ADCO(base) (BME_UBFX32(&ADC_SC3_REG(base), ADC_SC3_ADCO_SHIFT, ADC_SC3_ADCO_WID…
1017 #define ADC_BRD_SC3_CALF(base) (BME_UBFX32(&ADC_SC3_REG(base), ADC_SC3_CALF_SHIFT, ADC_SC3_CALF_WID…
1037 #define ADC_BRD_SC3_CAL(base) (BME_UBFX32(&ADC_SC3_REG(base), ADC_SC3_CAL_SHIFT, ADC_SC3_CAL_WIDTH))
1106 #define ADC_BRD_OFS_OFS(base) (BME_UBFX32(&ADC_OFS_REG(base), ADC_OFS_OFS_SHIFT, ADC_OFS_OFS_WIDTH))
1158 #define ADC_BRD_PG_PG(base)  (BME_UBFX32(&ADC_PG_REG(base), ADC_PG_PG_SHIFT, ADC_PG_PG_WIDTH))
1208 #define ADC_BRD_MG_MG(base)  (BME_UBFX32(&ADC_MG_REG(base), ADC_MG_MG_SHIFT, ADC_MG_MG_WIDTH))
1266 #define ADC_BRD_CLPD_CLPD(base) (BME_UBFX32(&ADC_CLPD_REG(base), ADC_CLPD_CLPD_SHIFT, ADC_CLPD_CLPD…
1308 #define ADC_BRD_CLPS_CLPS(base) (BME_UBFX32(&ADC_CLPS_REG(base), ADC_CLPS_CLPS_SHIFT, ADC_CLPS_CLPS…
1350 #define ADC_BRD_CLP4_CLP4(base) (BME_UBFX32(&ADC_CLP4_REG(base), ADC_CLP4_CLP4_SHIFT, ADC_CLP4_CLP4…
1392 #define ADC_BRD_CLP3_CLP3(base) (BME_UBFX32(&ADC_CLP3_REG(base), ADC_CLP3_CLP3_SHIFT, ADC_CLP3_CLP3…
1434 #define ADC_BRD_CLP2_CLP2(base) (BME_UBFX32(&ADC_CLP2_REG(base), ADC_CLP2_CLP2_SHIFT, ADC_CLP2_CLP2…
1476 #define ADC_BRD_CLP1_CLP1(base) (BME_UBFX32(&ADC_CLP1_REG(base), ADC_CLP1_CLP1_SHIFT, ADC_CLP1_CLP1…
1518 #define ADC_BRD_CLP0_CLP0(base) (BME_UBFX32(&ADC_CLP0_REG(base), ADC_CLP0_CLP0_SHIFT, ADC_CLP0_CLP0…
1576 #define ADC_BRD_CLMD_CLMD(base) (BME_UBFX32(&ADC_CLMD_REG(base), ADC_CLMD_CLMD_SHIFT, ADC_CLMD_CLMD…
1618 #define ADC_BRD_CLMS_CLMS(base) (BME_UBFX32(&ADC_CLMS_REG(base), ADC_CLMS_CLMS_SHIFT, ADC_CLMS_CLMS…
1660 #define ADC_BRD_CLM4_CLM4(base) (BME_UBFX32(&ADC_CLM4_REG(base), ADC_CLM4_CLM4_SHIFT, ADC_CLM4_CLM4…
1702 #define ADC_BRD_CLM3_CLM3(base) (BME_UBFX32(&ADC_CLM3_REG(base), ADC_CLM3_CLM3_SHIFT, ADC_CLM3_CLM3…
1744 #define ADC_BRD_CLM2_CLM2(base) (BME_UBFX32(&ADC_CLM2_REG(base), ADC_CLM2_CLM2_SHIFT, ADC_CLM2_CLM2…
1786 #define ADC_BRD_CLM1_CLM1(base) (BME_UBFX32(&ADC_CLM1_REG(base), ADC_CLM1_CLM1_SHIFT, ADC_CLM1_CLM1…
1828 #define ADC_BRD_CLM0_CLM0(base) (BME_UBFX32(&ADC_CLM0_REG(base), ADC_CLM0_CLM0_SHIFT, ADC_CLM0_CLM0…
3723 #define DCDC_BRD_REG0_DCDC_DISABLE_AUTO_CLK_SWITCH(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG…
3738 #define DCDC_BRD_REG0_DCDC_SEL_CLK(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_DCDC_SEL_CLK_S…
3754 #define DCDC_BRD_REG0_DCDC_PWD_OSC_INT(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_DCDC_PWD_O…
3770 #define DCDC_BRD_REG0_DCDC_LP_DF_CMP_ENABLE(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_DCDC_…
3786 #define DCDC_BRD_REG0_DCDC_VBAT_DIV_CTRL(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_DCDC_VBA…
3808 #define DCDC_BRD_REG0_DCDC_LP_STATE_HYS_L(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_DCDC_LP…
3830 #define DCDC_BRD_REG0_DCDC_LP_STATE_HYS_H(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_DCDC_LP…
3845 #define DCDC_BRD_REG0_HYST_LP_COMP_ADJ(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_HYST_LP_CO…
3860 #define DCDC_BRD_REG0_HYST_LP_CMP_DISABLE(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_HYST_LP…
3875 #define DCDC_BRD_REG0_OFFSET_RSNS_LP_ADJ(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_OFFSET_R…
3890 #define DCDC_BRD_REG0_OFFSET_RSNS_LP_DISABLE(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_OFFS…
3905 #define DCDC_BRD_REG0_DCDC_LESS_I(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_DCDC_LESS_I_SHI…
3920 #define DCDC_BRD_REG0_PWD_CMP_OFFSET(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_PWD_CMP_OFFS…
3935 #define DCDC_BRD_REG0_DCDC_XTALOK_DISABLE(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_DCDC_XT…
3950 #define DCDC_BRD_REG0_PSWITCH_STATUS(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_PSWITCH_STAT…
3962 #define DCDC_BRD_REG0_VLPS_CONFIG_DCDC_HP(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_VLPS_CO…
3979 #define DCDC_BRD_REG0_VLPR_VLPW_CONFIG_DCDC_HP(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_VL…
3997 #define DCDC_BRD_REG0_DCDC_STS_DC_OK(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_DCDC_STS_DC_…
4035 #define DCDC_BRD_REG1_POSLIMIT_BUCK_IN(base) (BME_UBFX32(&DCDC_REG1_REG(base), DCDC_REG1_POSLIMIT_B…
4052 #define DCDC_BRD_REG1_POSLIMIT_BOOST_IN(base) (BME_UBFX32(&DCDC_REG1_REG(base), DCDC_REG1_POSLIMIT_…
4068 #define DCDC_BRD_REG1_DCDC_LOOPCTRL_CM_HST_THRESH(base) (BME_UBFX32(&DCDC_REG1_REG(base), DCDC_REG1…
4084 #define DCDC_BRD_REG1_DCDC_LOOPCTRL_DF_HST_THRESH(base) (BME_UBFX32(&DCDC_REG1_REG(base), DCDC_REG1…
4100 #define DCDC_BRD_REG1_DCDC_LOOPCTRL_EN_CM_HYST(base) (BME_UBFX32(&DCDC_REG1_REG(base), DCDC_REG1_DC…
4116 #define DCDC_BRD_REG1_DCDC_LOOPCTRL_EN_DF_HYST(base) (BME_UBFX32(&DCDC_REG1_REG(base), DCDC_REG1_DC…
4158 #define DCDC_BRD_REG2_DCDC_LOOPCTRL_DC_C(base) (BME_UBFX32(&DCDC_REG2_REG(base), DCDC_REG2_DCDC_LOO…
4177 #define DCDC_BRD_REG2_DCDC_LOOPCTRL_DC_FF(base) (BME_UBFX32(&DCDC_REG2_REG(base), DCDC_REG2_DCDC_LO…
4193 #define DCDC_BRD_REG2_DCDC_LOOPCTRL_HYST_SIGN(base) (BME_UBFX32(&DCDC_REG2_REG(base), DCDC_REG2_DCD…
4210 #define DCDC_BRD_REG2_DCDC_LOOPCTRL_TOGGLE_DIF(base) (BME_UBFX32(&DCDC_REG2_REG(base), DCDC_REG2_DC…
4227 #define DCDC_BRD_REG2_DCDC_BATTMONITOR_EN_BATADJ(base) (BME_UBFX32(&DCDC_REG2_REG(base), DCDC_REG2_…
4244 #define DCDC_BRD_REG2_DCDC_BATTMONITOR_BATT_VAL(base) (BME_UBFX32(&DCDC_REG2_REG(base), DCDC_REG2_D…
4293 #define DCDC_BRD_REG3_DCDC_VDD1P8CTRL_TRG(base) (BME_UBFX32(&DCDC_REG3_REG(base), DCDC_REG3_DCDC_VD…
4313 #define DCDC_BRD_REG3_DCDC_VDD1P45CTRL_TRG_BUCK(base) (BME_UBFX32(&DCDC_REG3_REG(base), DCDC_REG3_D…
4338 #define DCDC_BRD_REG3_DCDC_VDD1P45CTRL_TRG_BOOST(base) (BME_UBFX32(&DCDC_REG3_REG(base), DCDC_REG3_…
4354 #define DCDC_BRD_REG3_DCDC_VDD1P45CTRL_ADJTN(base) (BME_UBFX32(&DCDC_REG3_REG(base), DCDC_REG3_DCDC…
4369 #define DCDC_BRD_REG3_DCDC_MINPWR_DC_HALFCLK_LIMP(base) (BME_UBFX32(&DCDC_REG3_REG(base), DCDC_REG3…
4384 #define DCDC_BRD_REG3_DCDC_MINPWR_DOUBLE_FETS_LIMP(base) (BME_UBFX32(&DCDC_REG3_REG(base), DCDC_REG…
4399 #define DCDC_BRD_REG3_DCDC_MINPWR_HALF_FETS_LIMP(base) (BME_UBFX32(&DCDC_REG3_REG(base), DCDC_REG3_…
4414 #define DCDC_BRD_REG3_DCDC_MINPWR_DC_HALFCLK(base) (BME_UBFX32(&DCDC_REG3_REG(base), DCDC_REG3_DCDC…
4429 #define DCDC_BRD_REG3_DCDC_MINPWR_DOUBLE_FETS(base) (BME_UBFX32(&DCDC_REG3_REG(base), DCDC_REG3_DCD…
4444 #define DCDC_BRD_REG3_DCDC_MINPWR_HALF_FETS(base) (BME_UBFX32(&DCDC_REG3_REG(base), DCDC_REG3_DCDC_…
4459 #define DCDC_BRD_REG3_DCDC_VDD1P45CTRL_DISABLE_STEP(base) (BME_UBFX32(&DCDC_REG3_REG(base), DCDC_RE…
4474 #define DCDC_BRD_REG3_DCDC_VDD1P8CTRL_DISABLE_STEP(base) (BME_UBFX32(&DCDC_REG3_REG(base), DCDC_REG…
4512 #define DCDC_BRD_REG4_DCDC_SW_SHUTDOWN(base) (BME_UBFX32(&DCDC_REG4_REG(base), DCDC_REG4_DCDC_SW_SH…
4531 #define DCDC_BRD_REG4_UNLOCK(base) (BME_UBFX32(&DCDC_REG4_REG(base), DCDC_REG4_UNLOCK_SHIFT, DCDC_R…
4571 #define DCDC_BRD_REG6_PSWITCH_INT_RISE_EN(base) (BME_UBFX32(&DCDC_REG6_REG(base), DCDC_REG6_PSWITCH…
4586 #define DCDC_BRD_REG6_PSWITCH_INT_FALL_EN(base) (BME_UBFX32(&DCDC_REG6_REG(base), DCDC_REG6_PSWITCH…
4601 #define DCDC_BRD_REG6_PSWITCH_INT_CLEAR(base) (BME_UBFX32(&DCDC_REG6_REG(base), DCDC_REG6_PSWITCH_I…
4616 #define DCDC_BRD_REG6_PSWITCH_INT_MUTE(base) (BME_UBFX32(&DCDC_REG6_REG(base), DCDC_REG6_PSWITCH_IN…
4631 #define DCDC_BRD_REG6_PSWITCH_INT_STS(base) (BME_UBFX32(&DCDC_REG6_REG(base), DCDC_REG6_PSWITCH_INT…
4686 #define DCDC_BRD_REG7_INTEGRATOR_VALUE_SEL(base) (BME_UBFX32(&DCDC_REG7_REG(base), DCDC_REG7_INTEGR…
4702 #define DCDC_BRD_REG7_PULSE_RUN_SPEEDUP(base) (BME_UBFX32(&DCDC_REG7_REG(base), DCDC_REG7_PULSE_RUN…
4856 #define DMA_BRD_DSR_BCR_DONE(base, index) (BME_UBFX32(&DMA_DSR_BCR_REG(base, index), DMA_DSR_BCR_DO…
4875 #define DMA_BRD_DSR_BCR_BSY(base, index) (BME_UBFX32(&DMA_DSR_BCR_REG(base, index), DMA_DSR_BCR_BSY…
4890 #define DMA_BRD_DSR_BCR_REQ(base, index) (BME_UBFX32(&DMA_DSR_BCR_REG(base, index), DMA_DSR_BCR_REQ…
4906 #define DMA_BRD_DSR_BCR_BED(base, index) (BME_UBFX32(&DMA_DSR_BCR_REG(base, index), DMA_DSR_BCR_BED…
4922 #define DMA_BRD_DSR_BCR_BES(base, index) (BME_UBFX32(&DMA_DSR_BCR_REG(base, index), DMA_DSR_BCR_BES…
4942 #define DMA_BRD_DSR_BCR_CE(base, index) (BME_UBFX32(&DMA_DSR_BCR_REG(base, index), DMA_DSR_BCR_CE_S…
5006 #define DMA_BRD_DCR_LCH2(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_LCH2_SHIFT, DM…
5028 #define DMA_BRD_DCR_LCH1(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_LCH1_SHIFT, DM…
5060 #define DMA_BRD_DCR_LINKCC(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_LINKCC_SHIFT…
5080 #define DMA_BRD_DCR_D_REQ(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_D_REQ_SHIFT, …
5120 #define DMA_BRD_DCR_DMOD(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_DMOD_SHIFT, DM…
5177 #define DMA_BRD_DCR_SMOD(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_SMOD_SHIFT, DM…
5214 #define DMA_BRD_DCR_DSIZE(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_DSIZE_SHIFT, …
5234 #define DMA_BRD_DCR_DINC(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_DINC_SHIFT, DM…
5256 #define DMA_BRD_DCR_SSIZE(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_SSIZE_SHIFT, …
5275 #define DMA_BRD_DCR_SINC(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_SINC_SHIFT, DM…
5295 #define DMA_BRD_DCR_EADREQ(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_EADREQ_SHIFT…
5319 #define DMA_BRD_DCR_AA(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_AA_SHIFT, DMA_DC…
5337 #define DMA_BRD_DCR_CS(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_CS_SHIFT, DMA_DC…
5357 #define DMA_BRD_DCR_ERQ(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_ERQ_SHIFT, DMA_…
5377 #define DMA_BRD_DCR_EINT(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_EINT_SHIFT, DM…
9913 #define LPTMR_BRD_CSR_TEN(base) (BME_UBFX32(&LPTMR_CSR_REG(base), LPTMR_CSR_TEN_SHIFT, LPTMR_CSR_TE…
9933 #define LPTMR_BRD_CSR_TMS(base) (BME_UBFX32(&LPTMR_CSR_REG(base), LPTMR_CSR_TMS_SHIFT, LPTMR_CSR_TM…
9954 #define LPTMR_BRD_CSR_TFC(base) (BME_UBFX32(&LPTMR_CSR_REG(base), LPTMR_CSR_TFC_SHIFT, LPTMR_CSR_TF…
9976 #define LPTMR_BRD_CSR_TPP(base) (BME_UBFX32(&LPTMR_CSR_REG(base), LPTMR_CSR_TPP_SHIFT, LPTMR_CSR_TP…
10000 #define LPTMR_BRD_CSR_TPS(base) (BME_UBFX32(&LPTMR_CSR_REG(base), LPTMR_CSR_TPS_SHIFT, LPTMR_CSR_TP…
10019 #define LPTMR_BRD_CSR_TIE(base) (BME_UBFX32(&LPTMR_CSR_REG(base), LPTMR_CSR_TIE_SHIFT, LPTMR_CSR_TI…
10039 #define LPTMR_BRD_CSR_TCF(base) (BME_UBFX32(&LPTMR_CSR_REG(base), LPTMR_CSR_TCF_SHIFT, LPTMR_CSR_TC…
10088 #define LPTMR_BRD_PSR_PCS(base) (BME_UBFX32(&LPTMR_PSR_REG(base), LPTMR_PSR_PCS_SHIFT, LPTMR_PSR_PC…
10110 #define LPTMR_BRD_PSR_PBYP(base) (BME_UBFX32(&LPTMR_PSR_REG(base), LPTMR_PSR_PBYP_SHIFT, LPTMR_PSR_…
10161 #define LPTMR_BRD_PSR_PRESCALE(base) (BME_UBFX32(&LPTMR_PSR_REG(base), LPTMR_PSR_PRESCALE_SHIFT, LP…
10205 #define LPTMR_BRD_CMR_COMPARE(base) (BME_UBFX32(&LPTMR_CMR_REG(base), LPTMR_CMR_COMPARE_SHIFT, LPTM…
10243 #define LPTMR_BRD_CNR_COUNTER(base) (BME_UBFX32(&LPTMR_CNR_REG(base), LPTMR_CNR_COUNTER_SHIFT, LPTM…
10304 #define LPUART_BRD_BAUD_SBR(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_SBR_SHIFT, LPUART…
10324 #define LPUART_BRD_BAUD_SBNS(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_SBNS_SHIFT, LPUA…
10345 #define LPUART_BRD_BAUD_RXEDGIE(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_RXEDGIE_SHIFT…
10365 #define LPUART_BRD_BAUD_LBKDIE(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_LBKDIE_SHIFT, …
10386 #define LPUART_BRD_BAUD_RESYNCDIS(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_RESYNCDIS_S…
10411 #define LPUART_BRD_BAUD_BOTHEDGE(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_BOTHEDGE_SHI…
10432 #define LPUART_BRD_BAUD_MATCFG(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_MATCFG_SHIFT, …
10452 #define LPUART_BRD_BAUD_RDMAE(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_RDMAE_SHIFT, LP…
10472 #define LPUART_BRD_BAUD_TDMAE(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_TDMAE_SHIFT, LP…
10490 #define LPUART_BRD_BAUD_OSR(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_OSR_SHIFT, LPUART…
10510 #define LPUART_BRD_BAUD_M10(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_M10_SHIFT, LPUART…
10528 #define LPUART_BRD_BAUD_MAEN2(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_MAEN2_SHIFT, LP…
10546 #define LPUART_BRD_BAUD_MAEN1(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_MAEN1_SHIFT, LP…
10591 #define LPUART_BRD_STAT_MA2F(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_MA2F_SHIFT, LPUA…
10611 #define LPUART_BRD_STAT_MA1F(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_MA1F_SHIFT, LPUA…
10633 #define LPUART_BRD_STAT_PF(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_PF_SHIFT, LPUART_S…
10655 #define LPUART_BRD_STAT_FE(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_FE_SHIFT, LPUART_S…
10679 #define LPUART_BRD_STAT_NF(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_NF_SHIFT, LPUART_S…
10706 #define LPUART_BRD_STAT_OR(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_OR_SHIFT, LPUART_S…
10737 #define LPUART_BRD_STAT_IDLE(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_IDLE_SHIFT, LPUA…
10765 #define LPUART_BRD_STAT_RDRF(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_RDRF_SHIFT, LPUA…
10786 #define LPUART_BRD_STAT_TC(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_TC_SHIFT, LPUART_S…
10809 #define LPUART_BRD_STAT_TDRE(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_TDRE_SHIFT, LPUA…
10825 #define LPUART_BRD_STAT_RAF(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_RAF_SHIFT, LPUART…
10845 #define LPUART_BRD_STAT_LBKDE(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_LBKDE_SHIFT, LP…
10870 #define LPUART_BRD_STAT_BRK13(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_BRK13_SHIFT, LP…
10896 #define LPUART_BRD_STAT_RWUID(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_RWUID_SHIFT, LP…
10917 #define LPUART_BRD_STAT_RXINV(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_RXINV_SHIFT, LP…
10945 #define LPUART_BRD_STAT_MSBF(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_MSBF_SHIFT, LPUA…
10965 #define LPUART_BRD_STAT_RXEDGIF(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_RXEDGIF_SHIFT…
10985 #define LPUART_BRD_STAT_LBKDIF(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_LBKDIF_SHIFT, …
11036 #define LPUART_BRD_CTRL_PT(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_PT_SHIFT, LPUART_C…
11056 #define LPUART_BRD_CTRL_PE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_PE_SHIFT, LPUART_C…
11082 #define LPUART_BRD_CTRL_ILT(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_ILT_SHIFT, LPUART…
11103 #define LPUART_BRD_CTRL_WAKE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_WAKE_SHIFT, LPUA…
11120 #define LPUART_BRD_CTRL_M(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_M_SHIFT, LPUART_CTR…
11143 #define LPUART_BRD_CTRL_RSRC(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_RSRC_SHIFT, LPUA…
11160 #define LPUART_BRD_CTRL_DOZEEN(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_DOZEEN_SHIFT, …
11182 #define LPUART_BRD_CTRL_LOOPS(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_LOOPS_SHIFT, LP…
11208 #define LPUART_BRD_CTRL_IDLECFG(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_IDLECFG_SHIFT…
11225 #define LPUART_BRD_CTRL_MA2IE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_MA2IE_SHIFT, LP…
11242 #define LPUART_BRD_CTRL_MA1IE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_MA1IE_SHIFT, LP…
11266 #define LPUART_BRD_CTRL_SBK(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_SBK_SHIFT, LPUART…
11293 #define LPUART_BRD_CTRL_RWU(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_RWU_SHIFT, LPUART…
11313 #define LPUART_BRD_CTRL_RE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_RE_SHIFT, LPUART_C…
11335 #define LPUART_BRD_CTRL_TE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_TE_SHIFT, LPUART_C…
11354 #define LPUART_BRD_CTRL_ILIE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_ILIE_SHIFT, LPUA…
11373 #define LPUART_BRD_CTRL_RIE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_RIE_SHIFT, LPUART…
11393 #define LPUART_BRD_CTRL_TCIE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_TCIE_SHIFT, LPUA…
11412 #define LPUART_BRD_CTRL_TIE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_TIE_SHIFT, LPUART…
11432 #define LPUART_BRD_CTRL_PEIE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_PEIE_SHIFT, LPUA…
11452 #define LPUART_BRD_CTRL_FEIE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_FEIE_SHIFT, LPUA…
11471 #define LPUART_BRD_CTRL_NEIE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_NEIE_SHIFT, LPUA…
11491 #define LPUART_BRD_CTRL_ORIE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_ORIE_SHIFT, LPUA…
11512 #define LPUART_BRD_CTRL_TXINV(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_TXINV_SHIFT, LP…
11534 #define LPUART_BRD_CTRL_TXDIR(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_TXDIR_SHIFT, LP…
11555 #define LPUART_BRD_CTRL_R9T8(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_R9T8_SHIFT, LPUA…
11576 #define LPUART_BRD_CTRL_R8T9(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_R8T9_SHIFT, LPUA…
11621 #define LPUART_BRD_DATA_R0T0(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_R0T0_SHIFT, LPUA…
11636 #define LPUART_BRD_DATA_R1T1(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_R1T1_SHIFT, LPUA…
11651 #define LPUART_BRD_DATA_R2T2(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_R2T2_SHIFT, LPUA…
11666 #define LPUART_BRD_DATA_R3T3(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_R3T3_SHIFT, LPUA…
11681 #define LPUART_BRD_DATA_R4T4(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_R4T4_SHIFT, LPUA…
11696 #define LPUART_BRD_DATA_R5T5(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_R5T5_SHIFT, LPUA…
11711 #define LPUART_BRD_DATA_R6T6(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_R6T6_SHIFT, LPUA…
11726 #define LPUART_BRD_DATA_R7T7(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_R7T7_SHIFT, LPUA…
11741 #define LPUART_BRD_DATA_R8T8(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_R8T8_SHIFT, LPUA…
11756 #define LPUART_BRD_DATA_R9T9(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_R9T9_SHIFT, LPUA…
11777 #define LPUART_BRD_DATA_IDLINE(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_IDLINE_SHIFT, …
11793 #define LPUART_BRD_DATA_RXEMPT(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_RXEMPT_SHIFT, …
11814 #define LPUART_BRD_DATA_FRETSC(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_FRETSC_SHIFT, …
11834 #define LPUART_BRD_DATA_PARITYE(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_PARITYE_SHIFT…
11850 #define LPUART_BRD_DATA_NOISY(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_NOISY_SHIFT, LP…
11890 #define LPUART_BRD_MATCH_MA1(base) (BME_UBFX32(&LPUART_MATCH_REG(base), LPUART_MATCH_MA1_SHIFT, LPU…
11909 #define LPUART_BRD_MATCH_MA2(base) (BME_UBFX32(&LPUART_MATCH_REG(base), LPUART_MATCH_MA2_SHIFT, LPU…
11960 #define LPUART_BRD_MODIR_TXCTSE(base) (BME_UBFX32(&LPUART_MODIR_REG(base), LPUART_MODIR_TXCTSE_SHIF…
11982 #define LPUART_BRD_MODIR_TXRTSE(base) (BME_UBFX32(&LPUART_MODIR_REG(base), LPUART_MODIR_TXRTSE_SHIF…
12003 #define LPUART_BRD_MODIR_TXRTSPOL(base) (BME_UBFX32(&LPUART_MODIR_REG(base), LPUART_MODIR_TXRTSPOL_…
12023 #define LPUART_BRD_MODIR_RXRTSE(base) (BME_UBFX32(&LPUART_MODIR_REG(base), LPUART_MODIR_RXRTSE_SHIF…
12043 #define LPUART_BRD_MODIR_TXCTSC(base) (BME_UBFX32(&LPUART_MODIR_REG(base), LPUART_MODIR_TXCTSC_SHIF…
12062 #define LPUART_BRD_MODIR_TXCTSSRC(base) (BME_UBFX32(&LPUART_MODIR_REG(base), LPUART_MODIR_TXCTSSRC_…
12084 #define LPUART_BRD_MODIR_TNP(base) (BME_UBFX32(&LPUART_MODIR_REG(base), LPUART_MODIR_TNP_SHIFT, LPU…
12103 #define LPUART_BRD_MODIR_IREN(base) (BME_UBFX32(&LPUART_MODIR_REG(base), LPUART_MODIR_IREN_SHIFT, L…
12182 #define LTC_BRD_MD_ENC(base) (BME_UBFX32(&LTC_MD_REG(base), LTC_MD_ENC_SHIFT, LTC_MD_ENC_WIDTH))
12203 #define LTC_BRD_MD_ICV_TEST(base) (BME_UBFX32(&LTC_MD_REG(base), LTC_MD_ICV_TEST_SHIFT, LTC_MD_ICV_…
12229 #define LTC_BRD_MD_AS(base)  (BME_UBFX32(&LTC_MD_REG(base), LTC_MD_AS_SHIFT, LTC_MD_AS_WIDTH))
12253 #define LTC_BRD_MD_AAI(base) (BME_UBFX32(&LTC_MD_REG(base), LTC_MD_AAI_SHIFT, LTC_MD_AAI_WIDTH))
12272 #define LTC_BRD_MD_ALG(base) (BME_UBFX32(&LTC_MD_REG(base), LTC_MD_ALG_SHIFT, LTC_MD_ALG_WIDTH))
12354 #define LTC_BRD_DS_DS(base)  (BME_UBFX32(&LTC_DS_REG(base), LTC_DS_DS_SHIFT, LTC_DS_DS_WIDTH))
12400 #define LTC_BRD_ICVS_ICVS(base) (BME_UBFX32(&LTC_ICVS_REG(base), LTC_ICVS_ICVS_SHIFT, LTC_ICVS_ICVS…
12506 #define LTC_BRD_CTL_IM(base) (BME_UBFX32(&LTC_CTL_REG(base), LTC_CTL_IM_SHIFT, LTC_CTL_IM_WIDTH))
12527 #define LTC_BRD_CTL_IFE(base) (BME_UBFX32(&LTC_CTL_REG(base), LTC_CTL_IFE_SHIFT, LTC_CTL_IFE_WIDTH))
12549 #define LTC_BRD_CTL_IFR(base) (BME_UBFX32(&LTC_CTL_REG(base), LTC_CTL_IFR_SHIFT, LTC_CTL_IFR_WIDTH))
12570 #define LTC_BRD_CTL_OFE(base) (BME_UBFX32(&LTC_CTL_REG(base), LTC_CTL_OFE_SHIFT, LTC_CTL_OFE_WIDTH))
12592 #define LTC_BRD_CTL_OFR(base) (BME_UBFX32(&LTC_CTL_REG(base), LTC_CTL_OFR_SHIFT, LTC_CTL_OFR_WIDTH))
12613 #define LTC_BRD_CTL_IFS(base) (BME_UBFX32(&LTC_CTL_REG(base), LTC_CTL_IFS_SHIFT, LTC_CTL_IFS_WIDTH))
12634 #define LTC_BRD_CTL_OFS(base) (BME_UBFX32(&LTC_CTL_REG(base), LTC_CTL_OFS_SHIFT, LTC_CTL_OFS_WIDTH))
12656 #define LTC_BRD_CTL_KIS(base) (BME_UBFX32(&LTC_CTL_REG(base), LTC_CTL_KIS_SHIFT, LTC_CTL_KIS_WIDTH))
12678 #define LTC_BRD_CTL_KOS(base) (BME_UBFX32(&LTC_CTL_REG(base), LTC_CTL_KOS_SHIFT, LTC_CTL_KOS_WIDTH))
12700 #define LTC_BRD_CTL_CIS(base) (BME_UBFX32(&LTC_CTL_REG(base), LTC_CTL_CIS_SHIFT, LTC_CTL_CIS_WIDTH))
12722 #define LTC_BRD_CTL_COS(base) (BME_UBFX32(&LTC_CTL_REG(base), LTC_CTL_COS_SHIFT, LTC_CTL_COS_WIDTH))
12745 #define LTC_BRD_CTL_KAL(base) (BME_UBFX32(&LTC_CTL_REG(base), LTC_CTL_KAL_SHIFT, LTC_CTL_KAL_WIDTH))
12901 #define LTC_BRD_STA_AB(base) (BME_UBFX32(&LTC_STA_REG(base), LTC_STA_AB_SHIFT, LTC_STA_AB_WIDTH))
12913 #define LTC_BRD_STA_DI(base) (BME_UBFX32(&LTC_STA_REG(base), LTC_STA_DI_SHIFT, LTC_STA_DI_WIDTH))
12935 #define LTC_BRD_STA_EI(base) (BME_UBFX32(&LTC_STA_REG(base), LTC_STA_EI_SHIFT, LTC_STA_EI_WIDTH))
12991 #define LTC_BRD_ESTA_ERRID1(base) (BME_UBFX32(&LTC_ESTA_REG(base), LTC_ESTA_ERRID1_SHIFT, LTC_ESTA_…
13009 #define LTC_BRD_ESTA_CL1(base) (BME_UBFX32(&LTC_ESTA_REG(base), LTC_ESTA_CL1_SHIFT, LTC_ESTA_CL1_WI…
13056 #define LTC_BRD_AADSZ_AADSZ(base) (BME_UBFX32(&LTC_AADSZ_REG(base), LTC_AADSZ_AADSZ_SHIFT, LTC_AADS…
13071 #define LTC_BRD_AADSZ_AL(base) (BME_UBFX32(&LTC_AADSZ_REG(base), LTC_AADSZ_AL_SHIFT, LTC_AADSZ_AL_W…
13168 #define LTC_BRD_FIFOSTA_IFL(base) (BME_UBFX32(&LTC_FIFOSTA_REG(base), LTC_FIFOSTA_IFL_SHIFT, LTC_FI…
13179 #define LTC_BRD_FIFOSTA_IFF(base) (BME_UBFX32(&LTC_FIFOSTA_REG(base), LTC_FIFOSTA_IFF_SHIFT, LTC_FI…
13191 #define LTC_BRD_FIFOSTA_OFL(base) (BME_UBFX32(&LTC_FIFOSTA_REG(base), LTC_FIFOSTA_OFL_SHIFT, LTC_FI…
13202 #define LTC_BRD_FIFOSTA_OFF(base) (BME_UBFX32(&LTC_FIFOSTA_REG(base), LTC_FIFOSTA_OFF_SHIFT, LTC_FI…
13278 #define LTC_BRD_VID1_MIN_REV(base) (BME_UBFX32(&LTC_VID1_REG(base), LTC_VID1_MIN_REV_SHIFT, LTC_VID…
13289 #define LTC_BRD_VID1_MAJ_REV(base) (BME_UBFX32(&LTC_VID1_REG(base), LTC_VID1_MAJ_REV_SHIFT, LTC_VID…
13298 #define LTC_BRD_VID1_IP_ID(base) (BME_UBFX32(&LTC_VID1_REG(base), LTC_VID1_IP_ID_SHIFT, LTC_VID1_IP…
13332 #define LTC_BRD_CHAVID_AESREV(base) (BME_UBFX32(&LTC_CHAVID_REG(base), LTC_CHAVID_AESREV_SHIFT, LTC…
13343 #define LTC_BRD_CHAVID_AESVID(base) (BME_UBFX32(&LTC_CHAVID_REG(base), LTC_CHAVID_AESVID_SHIFT, LTC…
16261 #define PIT_BRD_MCR_FRZ(base) (BME_UBFX32(&PIT_MCR_REG(base), PIT_MCR_FRZ_SHIFT, PIT_MCR_FRZ_WIDTH))
16281 #define PIT_BRD_MCR_MDIS(base) (BME_UBFX32(&PIT_MCR_REG(base), PIT_MCR_MDIS_SHIFT, PIT_MCR_MDIS_WID…
16413 #define PIT_BRD_TCTRL_TEN(base, index) (BME_UBFX32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_TEN_SHIFT…
16434 #define PIT_BRD_TCTRL_TIE(base, index) (BME_UBFX32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_TIE_SHIFT…
16455 #define PIT_BRD_TCTRL_CHN(base, index) (BME_UBFX32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_CHN_SHIFT…
16503 #define PIT_BRD_TFLG_TIF(base, index) (BME_UBFX32(&PIT_TFLG_REG(base, index), PIT_TFLG_TIF_SHIFT, P…
16933 #define PORT_BRD_PCR_PS(base, index) (BME_UBFX32(&PORT_PCR_REG(base, index), PORT_PCR_PS_SHIFT, POR…
16957 #define PORT_BRD_PCR_PE(base, index) (BME_UBFX32(&PORT_PCR_REG(base, index), PORT_PCR_PE_SHIFT, POR…
16979 #define PORT_BRD_PCR_SRE(base, index) (BME_UBFX32(&PORT_PCR_REG(base, index), PORT_PCR_SRE_SHIFT, P…
17002 #define PORT_BRD_PCR_PFE(base, index) (BME_UBFX32(&PORT_PCR_REG(base, index), PORT_PCR_PFE_SHIFT, P…
17024 #define PORT_BRD_PCR_DSE(base, index) (BME_UBFX32(&PORT_PCR_REG(base, index), PORT_PCR_DSE_SHIFT, P…
17052 #define PORT_BRD_PCR_MUX(base, index) (BME_UBFX32(&PORT_PCR_REG(base, index), PORT_PCR_MUX_SHIFT, P…
17087 #define PORT_BRD_PCR_IRQC(base, index) (BME_UBFX32(&PORT_PCR_REG(base, index), PORT_PCR_IRQC_SHIFT,…
17112 #define PORT_BRD_PCR_ISF(base, index) (BME_UBFX32(&PORT_PCR_REG(base, index), PORT_PCR_ISF_SHIFT, P…
17949 #define RSIM_BRD_CONTROL_BLE_RF_OSC_REQ_EN(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTROL_…
17965 #define RSIM_BRD_CONTROL_BLE_RF_OSC_REQ_STAT(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTRO…
17977 #define RSIM_BRD_CONTROL_BLE_RF_OSC_REQ_INT_EN(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONT…
17994 #define RSIM_BRD_CONTROL_BLE_RF_OSC_REQ_INT(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTROL…
18020 #define RSIM_BRD_CONTROL_RF_OSC_EN(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTROL_RF_OSC_E…
18037 #define RSIM_BRD_CONTROL_GASKET_BYPASS_OVRD_EN(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONT…
18069 #define RSIM_BRD_CONTROL_GASKET_BYPASS_OVRD(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTROL…
18087 #define RSIM_BRD_CONTROL_RF_OSC_BYPASS_EN(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTROL_R…
18103 #define RSIM_BRD_CONTROL_BLE_ACTIVE_PORT_1_SEL(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONT…
18119 #define RSIM_BRD_CONTROL_BLE_ACTIVE_PORT_2_SEL(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONT…
18134 #define RSIM_BRD_CONTROL_BLE_DEEP_SLEEP_EXIT(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTRO…
18154 #define RSIM_BRD_CONTROL_STOP_ACK_OVRD_EN(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTROL_S…
18170 #define RSIM_BRD_CONTROL_STOP_ACK_OVRD(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTROL_STOP…
18190 #define RSIM_BRD_CONTROL_RF_OSC_READY(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTROL_RF_OS…
18201 #define RSIM_BRD_CONTROL_RF_OSC_READY_OVRD_EN(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTR…
18218 #define RSIM_BRD_CONTROL_RF_OSC_READY_OVRD(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTROL_…
18236 #define RSIM_BRD_CONTROL_BLOCK_RADIO_RESETS(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTROL…
18254 #define RSIM_BRD_CONTROL_BLOCK_RADIO_OUTPUTS(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTRO…
18273 #define RSIM_BRD_CONTROL_RADIO_RESET(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTROL_RADIO_…
18322 #define RSIM_BRD_ACTIVE_DELAY_BLE_ACTIVE_FINE_DELAY(base) (BME_UBFX32(&RSIM_ACTIVE_DELAY_REG(base),…
18342 #define RSIM_BRD_ACTIVE_DELAY_BLE_ACTIVE_COARSE_DELAY(base) (BME_UBFX32(&RSIM_ACTIVE_DELAY_REG(base…
18382 #define RSIM_BRD_MAC_MSB_MAC_ADDR_MSB(base) (BME_UBFX32(&RSIM_MAC_MSB_REG(base), RSIM_MAC_MSB_MAC_A…
18442 #define RSIM_BRD_ANA_TEST_ATST_GATE_EN(base) (BME_UBFX32(&RSIM_ANA_TEST_REG(base), RSIM_ANA_TEST_AT…
18462 #define RSIM_BRD_ANA_TEST_RADIO_ID(base) (BME_UBFX32(&RSIM_ANA_TEST_REG(base), RSIM_ANA_TEST_RADIO_…
18542 #define RTC_BRD_TPR_TPR(base) (BME_UBFX32(&RTC_TPR_REG(base), RTC_TPR_TPR_SHIFT, RTC_TPR_TPR_WIDTH))
18612 #define RTC_BRD_TCR_TCR(base) (BME_UBFX32(&RTC_TCR_REG(base), RTC_TCR_TCR_SHIFT, RTC_TCR_TCR_WIDTH))
18632 #define RTC_BRD_TCR_CIR(base) (BME_UBFX32(&RTC_TCR_REG(base), RTC_TCR_CIR_SHIFT, RTC_TCR_CIR_WIDTH))
18650 #define RTC_BRD_TCR_TCV(base) (BME_UBFX32(&RTC_TCR_REG(base), RTC_TCR_TCV_SHIFT, RTC_TCR_TCV_WIDTH))
18663 #define RTC_BRD_TCR_CIC(base) (BME_UBFX32(&RTC_TCR_REG(base), RTC_TCR_CIC_SHIFT, RTC_TCR_CIC_WIDTH))
18702 #define RTC_BRD_CR_SWR(base) (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_SWR_SHIFT, RTC_CR_SWR_WIDTH))
18722 #define RTC_BRD_CR_WPE(base) (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_WPE_SHIFT, RTC_CR_WPE_WIDTH))
18740 #define RTC_BRD_CR_SUP(base) (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_SUP_SHIFT, RTC_CR_SUP_WIDTH))
18761 #define RTC_BRD_CR_UM(base)  (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_UM_SHIFT, RTC_CR_UM_WIDTH))
18782 #define RTC_BRD_CR_WPS(base) (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_WPS_SHIFT, RTC_CR_WPS_WIDTH))
18801 #define RTC_BRD_CR_OSCE(base) (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_OSCE_SHIFT, RTC_CR_OSCE_WIDTH))
18818 #define RTC_BRD_CR_CLKO(base) (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_CLKO_SHIFT, RTC_CR_CLKO_WIDTH))
18835 #define RTC_BRD_CR_SC16P(base) (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_SC16P_SHIFT, RTC_CR_SC16P_WIDT…
18852 #define RTC_BRD_CR_SC8P(base) (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_SC8P_SHIFT, RTC_CR_SC8P_WIDTH))
18869 #define RTC_BRD_CR_SC4P(base) (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_SC4P_SHIFT, RTC_CR_SC4P_WIDTH))
18886 #define RTC_BRD_CR_SC2P(base) (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_SC2P_SHIFT, RTC_CR_SC2P_WIDTH))
18932 #define RTC_BRD_SR_TIF(base) (BME_UBFX32(&RTC_SR_REG(base), RTC_SR_TIF_SHIFT, RTC_SR_TIF_WIDTH))
18949 #define RTC_BRD_SR_TOF(base) (BME_UBFX32(&RTC_SR_REG(base), RTC_SR_TOF_SHIFT, RTC_SR_TOF_WIDTH))
18965 #define RTC_BRD_SR_TAF(base) (BME_UBFX32(&RTC_SR_REG(base), RTC_SR_TAF_SHIFT, RTC_SR_TAF_WIDTH))
18982 #define RTC_BRD_SR_TCE(base) (BME_UBFX32(&RTC_SR_REG(base), RTC_SR_TCE_SHIFT, RTC_SR_TCE_WIDTH))
19027 #define RTC_BRD_LR_TCL(base) (BME_UBFX32(&RTC_LR_REG(base), RTC_LR_TCL_SHIFT, RTC_LR_TCL_WIDTH))
19046 #define RTC_BRD_LR_CRL(base) (BME_UBFX32(&RTC_LR_REG(base), RTC_LR_CRL_SHIFT, RTC_LR_CRL_WIDTH))
19065 #define RTC_BRD_LR_SRL(base) (BME_UBFX32(&RTC_LR_REG(base), RTC_LR_SRL_SHIFT, RTC_LR_SRL_WIDTH))
19084 #define RTC_BRD_LR_LRL(base) (BME_UBFX32(&RTC_LR_REG(base), RTC_LR_LRL_SHIFT, RTC_LR_LRL_WIDTH))
19126 #define RTC_BRD_IER_TIIE(base) (BME_UBFX32(&RTC_IER_REG(base), RTC_IER_TIIE_SHIFT, RTC_IER_TIIE_WID…
19143 #define RTC_BRD_IER_TOIE(base) (BME_UBFX32(&RTC_IER_REG(base), RTC_IER_TOIE_SHIFT, RTC_IER_TOIE_WID…
19160 #define RTC_BRD_IER_TAIE(base) (BME_UBFX32(&RTC_IER_REG(base), RTC_IER_TAIE_SHIFT, RTC_IER_TAIE_WID…
19181 #define RTC_BRD_IER_TSIE(base) (BME_UBFX32(&RTC_IER_REG(base), RTC_IER_TSIE_SHIFT, RTC_IER_TSIE_WID…
19201 #define RTC_BRD_IER_WPON(base) (BME_UBFX32(&RTC_IER_REG(base), RTC_IER_WPON_SHIFT, RTC_IER_WPON_WID…
19281 #define SIM_BRD_SOPT1_OSC32KOUT(base) (BME_UBFX32(&SIM_SOPT1_REG(base), SIM_SOPT1_OSC32KOUT_SHIFT, …
19303 #define SIM_BRD_SOPT1_OSC32KSEL(base) (BME_UBFX32(&SIM_SOPT1_REG(base), SIM_SOPT1_OSC32KSEL_SHIFT, …
19357 #define SIM_BRD_SOPT2_CLKOUTSEL(base) (BME_UBFX32(&SIM_SOPT2_REG(base), SIM_SOPT2_CLKOUTSEL_SHIFT, …
19378 #define SIM_BRD_SOPT2_TPMSRC(base) (BME_UBFX32(&SIM_SOPT2_REG(base), SIM_SOPT2_TPMSRC_SHIFT, SIM_SO…
19399 #define SIM_BRD_SOPT2_LPUART0SRC(base) (BME_UBFX32(&SIM_SOPT2_REG(base), SIM_SOPT2_LPUART0SRC_SHIFT…
19444 #define SIM_BRD_SOPT4_TPM1CH0SRC(base) (BME_UBFX32(&SIM_SOPT4_REG(base), SIM_SOPT4_TPM1CH0SRC_SHIFT…
19464 #define SIM_BRD_SOPT4_TPM2CH0SRC(base) (BME_UBFX32(&SIM_SOPT4_REG(base), SIM_SOPT4_TPM2CH0SRC_SHIFT…
19485 #define SIM_BRD_SOPT4_TPM0CLKSEL(base) (BME_UBFX32(&SIM_SOPT4_REG(base), SIM_SOPT4_TPM0CLKSEL_SHIFT…
19506 #define SIM_BRD_SOPT4_TPM1CLKSEL(base) (BME_UBFX32(&SIM_SOPT4_REG(base), SIM_SOPT4_TPM1CLKSEL_SHIFT…
19527 #define SIM_BRD_SOPT4_TPM2CLKSEL(base) (BME_UBFX32(&SIM_SOPT4_REG(base), SIM_SOPT4_TPM2CLKSEL_SHIFT…
19573 #define SIM_BRD_SOPT5_LPUART0TXSRC(base) (BME_UBFX32(&SIM_SOPT5_REG(base), SIM_SOPT5_LPUART0TXSRC_S…
19592 #define SIM_BRD_SOPT5_LPUART0RXSRC(base) (BME_UBFX32(&SIM_SOPT5_REG(base), SIM_SOPT5_LPUART0RXSRC_S…
19609 #define SIM_BRD_SOPT5_LPUART0ODE(base) (BME_UBFX32(&SIM_SOPT5_REG(base), SIM_SOPT5_LPUART0ODE_SHIFT…
19668 #define SIM_BRD_SOPT7_ADC0TRGSEL(base) (BME_UBFX32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC0TRGSEL_SHIFT…
19692 #define SIM_BRD_SOPT7_ADC0PRETRGSEL(base) (BME_UBFX32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC0PRETRGSEL…
19720 #define SIM_BRD_SOPT7_ADC0ALTTRGEN(base) (BME_UBFX32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC0ALTTRGEN_S…
19775 #define SIM_BRD_SDID_PINID(base) (BME_UBFX32(&SIM_SDID_REG(base), SIM_SDID_PINID_SHIFT, SIM_SDID_PI…
19786 #define SIM_BRD_SDID_DIEID(base) (BME_UBFX32(&SIM_SDID_REG(base), SIM_SDID_DIEID_SHIFT, SIM_SDID_DI…
19797 #define SIM_BRD_SDID_REVID(base) (BME_UBFX32(&SIM_SDID_REG(base), SIM_SDID_REVID_SHIFT, SIM_SDID_RE…
19808 #define SIM_BRD_SDID_SRAMSIZE(base) (BME_UBFX32(&SIM_SDID_REG(base), SIM_SDID_SRAMSIZE_SHIFT, SIM_S…
19822 #define SIM_BRD_SDID_SERIESID(base) (BME_UBFX32(&SIM_SDID_REG(base), SIM_SDID_SERIESID_SHIFT, SIM_S…
19839 #define SIM_BRD_SDID_SUBFAMID(base) (BME_UBFX32(&SIM_SDID_REG(base), SIM_SDID_SUBFAMID_SHIFT, SIM_S…
19856 #define SIM_BRD_SDID_FAMID(base) (BME_UBFX32(&SIM_SDID_REG(base), SIM_SDID_FAMID_SHIFT, SIM_SDID_FA…
19884 #define SIM_BRD_SCGC_BIT(base, index)        (BME_UBFX32(&SIM_SCGC_BIT_REG((base), (index)), SIM_SC…
19904 #define SIM_BRD_SCGC4_CMT(base) (BME_UBFX32(&SIM_SCGC4_REG(base), SIM_SCGC4_CMT_SHIFT, SIM_SCGC4_CM…
19923 #define SIM_BRD_SCGC4_I2C0(base) (BME_UBFX32(&SIM_SCGC4_REG(base), SIM_SCGC4_I2C0_SHIFT, SIM_SCGC4_…
19942 #define SIM_BRD_SCGC4_I2C1(base) (BME_UBFX32(&SIM_SCGC4_REG(base), SIM_SCGC4_I2C1_SHIFT, SIM_SCGC4_…
19961 #define SIM_BRD_SCGC4_CMP(base) (BME_UBFX32(&SIM_SCGC4_REG(base), SIM_SCGC4_CMP_SHIFT, SIM_SCGC4_CM…
20005 #define SIM_BRD_SCGC5_LPTMR(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_LPTMR_SHIFT, SIM_SCGC…
20024 #define SIM_BRD_SCGC5_TSI(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_TSI_SHIFT, SIM_SCGC5_TS…
20043 #define SIM_BRD_SCGC5_PORTA(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTA_SHIFT, SIM_SCGC…
20062 #define SIM_BRD_SCGC5_PORTB(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTB_SHIFT, SIM_SCGC…
20081 #define SIM_BRD_SCGC5_PORTC(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTC_SHIFT, SIM_SCGC…
20100 #define SIM_BRD_SCGC5_LPUART0(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_LPUART0_SHIFT, SIM_…
20119 #define SIM_BRD_SCGC5_LTC(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_LTC_SHIFT, SIM_SCGC5_LT…
20135 #define SIM_BRD_SCGC5_RSIM(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_RSIM_SHIFT, SIM_SCGC5_…
20150 #define SIM_BRD_SCGC5_DCDC(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_DCDC_SHIFT, SIM_SCGC5_…
20169 #define SIM_BRD_SCGC5_BTLL(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_BTLL_SHIFT, SIM_SCGC5_…
20188 #define SIM_BRD_SCGC5_PHYDIG(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_PHYDIG_SHIFT, SIM_SC…
20207 #define SIM_BRD_SCGC5_ZigBee(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_ZigBee_SHIFT, SIM_SC…
20253 #define SIM_BRD_SCGC6_FTF(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTF_SHIFT, SIM_SCGC6_FT…
20272 #define SIM_BRD_SCGC6_DMAMUX(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_DMAMUX_SHIFT, SIM_SC…
20291 #define SIM_BRD_SCGC6_TRNG(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_TRNG_SHIFT, SIM_SCGC6_…
20310 #define SIM_BRD_SCGC6_SPI0(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_SPI0_SHIFT, SIM_SCGC6_…
20329 #define SIM_BRD_SCGC6_SPI1(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_SPI1_SHIFT, SIM_SCGC6_…
20348 #define SIM_BRD_SCGC6_PIT(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_PIT_SHIFT, SIM_SCGC6_PI…
20367 #define SIM_BRD_SCGC6_TPM0(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_TPM0_SHIFT, SIM_SCGC6_…
20386 #define SIM_BRD_SCGC6_TPM1(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_TPM1_SHIFT, SIM_SCGC6_…
20405 #define SIM_BRD_SCGC6_TPM2(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_TPM2_SHIFT, SIM_SCGC6_…
20424 #define SIM_BRD_SCGC6_ADC0(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_ADC0_SHIFT, SIM_SCGC6_…
20443 #define SIM_BRD_SCGC6_RTC(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_RTC_SHIFT, SIM_SCGC6_RT…
20462 #define SIM_BRD_SCGC6_DAC0(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_DAC0_SHIFT, SIM_SCGC6_…
20506 #define SIM_BRD_SCGC7_DMA(base) (BME_UBFX32(&SIM_SCGC7_REG(base), SIM_SCGC7_DMA_SHIFT, SIM_SCGC7_DM…
20561 #define SIM_BRD_CLKDIV1_OUTDIV4(base) (BME_UBFX32(&SIM_CLKDIV1_REG(base), SIM_CLKDIV1_OUTDIV4_SHIFT…
20597 #define SIM_BRD_CLKDIV1_OUTDIV1(base) (BME_UBFX32(&SIM_CLKDIV1_REG(base), SIM_CLKDIV1_OUTDIV1_SHIFT…
20646 #define SIM_BRD_FCFG1_FLASHDIS(base) (BME_UBFX32(&SIM_FCFG1_REG(base), SIM_FCFG1_FLASHDIS_SHIFT, SI…
20670 #define SIM_BRD_FCFG1_FLASHDOZE(base) (BME_UBFX32(&SIM_FCFG1_REG(base), SIM_FCFG1_FLASHDOZE_SHIFT, …
20686 #define SIM_BRD_FCFG1_PFSIZE(base) (BME_UBFX32(&SIM_FCFG1_REG(base), SIM_FCFG1_PFSIZE_SHIFT, SIM_FC…
20725 #define SIM_BRD_FCFG2_MAXADDR1(base) (BME_UBFX32(&SIM_FCFG2_REG(base), SIM_FCFG2_MAXADDR1_SHIFT, SI…
20740 #define SIM_BRD_FCFG2_MAXADDR0(base) (BME_UBFX32(&SIM_FCFG2_REG(base), SIM_FCFG2_MAXADDR0_SHIFT, SI…
20773 #define SIM_BRD_UIDMH_UID(base) (BME_UBFX32(&SIM_UIDMH_REG(base), SIM_UIDMH_UID_SHIFT, SIM_UIDMH_UI…
20855 #define SIM_BRD_COPC_COPW(base) (BME_UBFX32(&SIM_COPC_REG(base), SIM_COPC_COPW_SHIFT, SIM_COPC_COPW…
20875 #define SIM_BRD_COPC_COPCLKS(base) (BME_UBFX32(&SIM_COPC_REG(base), SIM_COPC_COPCLKS_SHIFT, SIM_COP…
20900 #define SIM_BRD_COPC_COPT(base) (BME_UBFX32(&SIM_COPC_REG(base), SIM_COPC_COPT_SHIFT, SIM_COPC_COPT…
20917 #define SIM_BRD_COPC_COPSTPEN(base) (BME_UBFX32(&SIM_COPC_REG(base), SIM_COPC_COPSTPEN_SHIFT, SIM_C…
20934 #define SIM_BRD_COPC_COPDBGEN(base) (BME_UBFX32(&SIM_COPC_REG(base), SIM_COPC_COPDBGEN_SHIFT, SIM_C…
20955 #define SIM_BRD_COPC_COPCLKSEL(base) (BME_UBFX32(&SIM_COPC_REG(base), SIM_COPC_COPCLKSEL_SHIFT, SIM…
21411 #define SPI_BRD_MCR_HALT(base) (BME_UBFX32(&SPI_MCR_REG(base), SPI_MCR_HALT_SHIFT, SPI_MCR_HALT_WID…
21433 #define SPI_BRD_MCR_SMPL_PT(base) (BME_UBFX32(&SPI_MCR_REG(base), SPI_MCR_SMPL_PT_SHIFT, SPI_MCR_SM…
21486 #define SPI_BRD_MCR_DIS_RXF(base) (BME_UBFX32(&SPI_MCR_REG(base), SPI_MCR_DIS_RXF_SHIFT, SPI_MCR_DI…
21507 #define SPI_BRD_MCR_DIS_TXF(base) (BME_UBFX32(&SPI_MCR_REG(base), SPI_MCR_DIS_TXF_SHIFT, SPI_MCR_DI…
21530 #define SPI_BRD_MCR_MDIS(base) (BME_UBFX32(&SPI_MCR_REG(base), SPI_MCR_MDIS_SHIFT, SPI_MCR_MDIS_WID…
21550 #define SPI_BRD_MCR_DOZE(base) (BME_UBFX32(&SPI_MCR_REG(base), SPI_MCR_DOZE_SHIFT, SPI_MCR_DOZE_WID…
21570 #define SPI_BRD_MCR_PCSIS(base) (BME_UBFX32(&SPI_MCR_REG(base), SPI_MCR_PCSIS_SHIFT, SPI_MCR_PCSIS_…
21592 #define SPI_BRD_MCR_ROOE(base) (BME_UBFX32(&SPI_MCR_REG(base), SPI_MCR_ROOE_SHIFT, SPI_MCR_ROOE_WID…
21611 #define SPI_BRD_MCR_MTFE(base) (BME_UBFX32(&SPI_MCR_REG(base), SPI_MCR_MTFE_SHIFT, SPI_MCR_MTFE_WID…
21631 #define SPI_BRD_MCR_FRZ(base) (BME_UBFX32(&SPI_MCR_REG(base), SPI_MCR_FRZ_SHIFT, SPI_MCR_FRZ_WIDTH))
21652 #define SPI_BRD_MCR_DCONF(base) (BME_UBFX32(&SPI_MCR_REG(base), SPI_MCR_DCONF_SHIFT, SPI_MCR_DCONF_…
21667 #define SPI_BRD_MCR_CONT_SCKE(base) (BME_UBFX32(&SPI_MCR_REG(base), SPI_MCR_CONT_SCKE_SHIFT, SPI_MC…
21687 #define SPI_BRD_MCR_MSTR(base) (BME_UBFX32(&SPI_MCR_REG(base), SPI_MCR_MSTR_SHIFT, SPI_MCR_MSTR_WID…
21736 #define SPI_BRD_TCR_SPI_TCNT(base) (BME_UBFX32(&SPI_TCR_REG(base), SPI_TCR_SPI_TCNT_SHIFT, SPI_TCR_…
21788 #define SPI_BRD_CTAR_SLAVE_CPHA(base, index) (BME_UBFX32(&SPI_CTAR_SLAVE_REG(base, index), SPI_CTAR…
21809 #define SPI_BRD_CTAR_SLAVE_CPOL(base, index) (BME_UBFX32(&SPI_CTAR_SLAVE_REG(base, index), SPI_CTAR…
21825 #define SPI_BRD_CTAR_SLAVE_FMSZ(base, index) (BME_UBFX32(&SPI_CTAR_SLAVE_REG(base, index), SPI_CTAR…
21882 #define SPI_BRD_CTAR_BR(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_BR_SHIFT, SPI…
21904 #define SPI_BRD_CTAR_DT(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_DT_SHIFT, SPI…
21924 #define SPI_BRD_CTAR_ASC(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_ASC_SHIFT, S…
21947 #define SPI_BRD_CTAR_CSSCK(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_CSSCK_SHIF…
21971 #define SPI_BRD_CTAR_PBR(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_PBR_SHIFT, S…
21996 #define SPI_BRD_CTAR_PDT(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_PDT_SHIFT, S…
22019 #define SPI_BRD_CTAR_PASC(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_PASC_SHIFT,…
22042 #define SPI_BRD_CTAR_PCSSCK(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_PCSSCK_SH…
22061 #define SPI_BRD_CTAR_LSBFE(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_LSBFE_SHIF…
22086 #define SPI_BRD_CTAR_CPHA(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_CPHA_SHIFT,…
22112 #define SPI_BRD_CTAR_CPOL(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_CPOL_SHIFT,…
22128 #define SPI_BRD_CTAR_FMSZ(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_FMSZ_SHIFT,…
22156 #define SPI_BRD_CTAR_DBR(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_DBR_SHIFT, S…
22203 #define SPI_BRD_SR_POPNXTPTR(base) (BME_UBFX32(&SPI_SR_REG(base), SPI_SR_POPNXTPTR_SHIFT, SPI_SR_PO…
22216 #define SPI_BRD_SR_RXCTR(base) (BME_UBFX32(&SPI_SR_REG(base), SPI_SR_RXCTR_SHIFT, SPI_SR_RXCTR_WIDT…
22229 #define SPI_BRD_SR_TXNXTPTR(base) (BME_UBFX32(&SPI_SR_REG(base), SPI_SR_TXNXTPTR_SHIFT, SPI_SR_TXNX…
22242 #define SPI_BRD_SR_TXCTR(base) (BME_UBFX32(&SPI_SR_REG(base), SPI_SR_TXCTR_SHIFT, SPI_SR_TXCTR_WIDT…
22260 #define SPI_BRD_SR_RFDF(base) (BME_UBFX32(&SPI_SR_REG(base), SPI_SR_RFDF_SHIFT, SPI_SR_RFDF_WIDTH))
22281 #define SPI_BRD_SR_RFOF(base) (BME_UBFX32(&SPI_SR_REG(base), SPI_SR_RFOF_SHIFT, SPI_SR_RFOF_WIDTH))
22303 #define SPI_BRD_SR_TFFF(base) (BME_UBFX32(&SPI_SR_REG(base), SPI_SR_TFFF_SHIFT, SPI_SR_TFFF_WIDTH))
22326 #define SPI_BRD_SR_TFUF(base) (BME_UBFX32(&SPI_SR_REG(base), SPI_SR_TFUF_SHIFT, SPI_SR_TFUF_WIDTH))
22349 #define SPI_BRD_SR_EOQF(base) (BME_UBFX32(&SPI_SR_REG(base), SPI_SR_EOQF_SHIFT, SPI_SR_EOQF_WIDTH))
22370 #define SPI_BRD_SR_TXRXS(base) (BME_UBFX32(&SPI_SR_REG(base), SPI_SR_TXRXS_SHIFT, SPI_SR_TXRXS_WIDT…
22390 #define SPI_BRD_SR_TCF(base) (BME_UBFX32(&SPI_SR_REG(base), SPI_SR_TCF_SHIFT, SPI_SR_TCF_WIDTH))
22439 #define SPI_BRD_RSER_RFDF_DIRS(base) (BME_UBFX32(&SPI_RSER_REG(base), SPI_RSER_RFDF_DIRS_SHIFT, SPI…
22459 #define SPI_BRD_RSER_RFDF_RE(base) (BME_UBFX32(&SPI_RSER_REG(base), SPI_RSER_RFDF_RE_SHIFT, SPI_RSE…
22478 #define SPI_BRD_RSER_RFOF_RE(base) (BME_UBFX32(&SPI_RSER_REG(base), SPI_RSER_RFOF_RE_SHIFT, SPI_RSE…
22499 #define SPI_BRD_RSER_TFFF_DIRS(base) (BME_UBFX32(&SPI_RSER_REG(base), SPI_RSER_TFFF_DIRS_SHIFT, SPI…
22519 #define SPI_BRD_RSER_TFFF_RE(base) (BME_UBFX32(&SPI_RSER_REG(base), SPI_RSER_TFFF_RE_SHIFT, SPI_RSE…
22538 #define SPI_BRD_RSER_TFUF_RE(base) (BME_UBFX32(&SPI_RSER_REG(base), SPI_RSER_TFUF_RE_SHIFT, SPI_RSE…
22557 #define SPI_BRD_RSER_EOQF_RE(base) (BME_UBFX32(&SPI_RSER_REG(base), SPI_RSER_EOQF_RE_SHIFT, SPI_RSE…
22576 #define SPI_BRD_RSER_TCF_RE(base) (BME_UBFX32(&SPI_RSER_REG(base), SPI_RSER_TCF_RE_SHIFT, SPI_RSER_…
22625 #define SPI_BRD_PUSHR_TXDATA(base) (BME_UBFX32(&SPI_PUSHR_REG(base), SPI_PUSHR_TXDATA_SHIFT, SPI_PU…
22645 #define SPI_BRD_PUSHR_PCS(base) (BME_UBFX32(&SPI_PUSHR_REG(base), SPI_PUSHR_PCS_SHIFT, SPI_PUSHR_PC…
22665 #define SPI_BRD_PUSHR_CTCNT(base) (BME_UBFX32(&SPI_PUSHR_REG(base), SPI_PUSHR_CTCNT_SHIFT, SPI_PUSH…
22686 #define SPI_BRD_PUSHR_EOQ(base) (BME_UBFX32(&SPI_PUSHR_REG(base), SPI_PUSHR_EOQ_SHIFT, SPI_PUSHR_EO…
22714 #define SPI_BRD_PUSHR_CTAS(base) (BME_UBFX32(&SPI_PUSHR_REG(base), SPI_PUSHR_CTAS_SHIFT, SPI_PUSHR_…
22734 #define SPI_BRD_PUSHR_CONT(base) (BME_UBFX32(&SPI_PUSHR_REG(base), SPI_PUSHR_CONT_SHIFT, SPI_PUSHR_…
22822 #define SPI_BRD_TXFR0_TXDATA(base) (BME_UBFX32(&SPI_TXFR0_REG(base), SPI_TXFR0_TXDATA_SHIFT, SPI_TX…
22835 #define SPI_BRD_TXFR0_TXCMD_TXDATA(base) (BME_UBFX32(&SPI_TXFR0_REG(base), SPI_TXFR0_TXCMD_TXDATA_S…
22872 #define SPI_BRD_TXFR1_TXDATA(base) (BME_UBFX32(&SPI_TXFR1_REG(base), SPI_TXFR1_TXDATA_SHIFT, SPI_TX…
22885 #define SPI_BRD_TXFR1_TXCMD_TXDATA(base) (BME_UBFX32(&SPI_TXFR1_REG(base), SPI_TXFR1_TXCMD_TXDATA_S…
22922 #define SPI_BRD_TXFR2_TXDATA(base) (BME_UBFX32(&SPI_TXFR2_REG(base), SPI_TXFR2_TXDATA_SHIFT, SPI_TX…
22935 #define SPI_BRD_TXFR2_TXCMD_TXDATA(base) (BME_UBFX32(&SPI_TXFR2_REG(base), SPI_TXFR2_TXCMD_TXDATA_S…
22972 #define SPI_BRD_TXFR3_TXDATA(base) (BME_UBFX32(&SPI_TXFR3_REG(base), SPI_TXFR3_TXDATA_SHIFT, SPI_TX…
22985 #define SPI_BRD_TXFR3_TXCMD_TXDATA(base) (BME_UBFX32(&SPI_TXFR3_REG(base), SPI_TXFR3_TXCMD_TXDATA_S…
23147 #define TPM_BRD_SC_PS(base)  (BME_UBFX32(&TPM_SC_REG(base), TPM_SC_PS_SHIFT, TPM_SC_PS_WIDTH))
23170 #define TPM_BRD_SC_CMOD(base) (BME_UBFX32(&TPM_SC_REG(base), TPM_SC_CMOD_SHIFT, TPM_SC_CMOD_WIDTH))
23191 #define TPM_BRD_SC_CPWMS(base) (BME_UBFX32(&TPM_SC_REG(base), TPM_SC_CPWMS_SHIFT, TPM_SC_CPWMS_WIDT…
23210 #define TPM_BRD_SC_TOIE(base) (BME_UBFX32(&TPM_SC_REG(base), TPM_SC_TOIE_SHIFT, TPM_SC_TOIE_WIDTH))
23234 #define TPM_BRD_SC_TOF(base) (BME_UBFX32(&TPM_SC_REG(base), TPM_SC_TOF_SHIFT, TPM_SC_TOF_WIDTH))
23253 #define TPM_BRD_SC_DMA(base) (BME_UBFX32(&TPM_SC_REG(base), TPM_SC_DMA_SHIFT, TPM_SC_DMA_WIDTH))
23297 #define TPM_BRD_CNT_COUNT(base) (BME_UBFX32(&TPM_CNT_REG(base), TPM_CNT_COUNT_SHIFT, TPM_CNT_COUNT_…
23348 #define TPM_BRD_MOD_MOD(base) (BME_UBFX32(&TPM_MOD_REG(base), TPM_MOD_MOD_SHIFT, TPM_MOD_MOD_WIDTH))
23407 #define TPM_BRD_CnSC_DMA(base, index) (BME_UBFX32(&TPM_CnSC_REG(base, index), TPM_CnSC_DMA_SHIFT, T…
23424 #define TPM_BRD_CnSC_ELSA(base, index) (BME_UBFX32(&TPM_CnSC_REG(base, index), TPM_CnSC_ELSA_SHIFT,…
23441 #define TPM_BRD_CnSC_ELSB(base, index) (BME_UBFX32(&TPM_CnSC_REG(base, index), TPM_CnSC_ELSB_SHIFT,…
23458 #define TPM_BRD_CnSC_MSA(base, index) (BME_UBFX32(&TPM_CnSC_REG(base, index), TPM_CnSC_MSA_SHIFT, T…
23475 #define TPM_BRD_CnSC_MSB(base, index) (BME_UBFX32(&TPM_CnSC_REG(base, index), TPM_CnSC_MSB_SHIFT, T…
23494 #define TPM_BRD_CnSC_CHIE(base, index) (BME_UBFX32(&TPM_CnSC_REG(base, index), TPM_CnSC_CHIE_SHIFT,…
23518 #define TPM_BRD_CnSC_CHF(base, index) (BME_UBFX32(&TPM_CnSC_REG(base, index), TPM_CnSC_CHF_SHIFT, T…
23566 #define TPM_BRD_CnV_VAL(base, index) (BME_UBFX32(&TPM_CnV_REG(base, index), TPM_CnV_VAL_SHIFT, TPM_…
23621 #define TPM_BRD_STATUS_CH0F(base) (BME_UBFX32(&TPM_STATUS_REG(base), TPM_STATUS_CH0F_SHIFT, TPM_STA…
23640 #define TPM_BRD_STATUS_CH1F(base) (BME_UBFX32(&TPM_STATUS_REG(base), TPM_STATUS_CH1F_SHIFT, TPM_STA…
23659 #define TPM_BRD_STATUS_CH2F(base) (BME_UBFX32(&TPM_STATUS_REG(base), TPM_STATUS_CH2F_SHIFT, TPM_STA…
23678 #define TPM_BRD_STATUS_CH3F(base) (BME_UBFX32(&TPM_STATUS_REG(base), TPM_STATUS_CH3F_SHIFT, TPM_STA…
23697 #define TPM_BRD_STATUS_TOF(base) (BME_UBFX32(&TPM_STATUS_REG(base), TPM_STATUS_TOF_SHIFT, TPM_STATU…
23749 #define TPM_BRD_COMBINE_COMBINE0(base) (BME_UBFX32(&TPM_COMBINE_REG(base), TPM_COMBINE_COMBINE0_SHI…
23769 #define TPM_BRD_COMBINE_COMSWAP0(base) (BME_UBFX32(&TPM_COMBINE_REG(base), TPM_COMBINE_COMSWAP0_SHI…
23792 #define TPM_BRD_COMBINE_COMBINE1(base) (BME_UBFX32(&TPM_COMBINE_REG(base), TPM_COMBINE_COMBINE1_SHI…
23812 #define TPM_BRD_COMBINE_COMSWAP1(base) (BME_UBFX32(&TPM_COMBINE_REG(base), TPM_COMBINE_COMSWAP1_SHI…
23858 #define TPM_BRD_FILTER_CH0FVAL(base) (BME_UBFX32(&TPM_FILTER_REG(base), TPM_FILTER_CH0FVAL_SHIFT, T…
23875 #define TPM_BRD_FILTER_CH1FVAL(base) (BME_UBFX32(&TPM_FILTER_REG(base), TPM_FILTER_CH1FVAL_SHIFT, T…
23892 #define TPM_BRD_FILTER_CH2FVAL(base) (BME_UBFX32(&TPM_FILTER_REG(base), TPM_FILTER_CH2FVAL_SHIFT, T…
23909 #define TPM_BRD_FILTER_CH3FVAL(base) (BME_UBFX32(&TPM_FILTER_REG(base), TPM_FILTER_CH3FVAL_SHIFT, T…
23957 #define TPM_BRD_QDCTRL_QUADEN(base) (BME_UBFX32(&TPM_QDCTRL_REG(base), TPM_QDCTRL_QUADEN_SHIFT, TPM…
23980 #define TPM_BRD_QDCTRL_TOFDIR(base) (BME_UBFX32(&TPM_QDCTRL_REG(base), TPM_QDCTRL_TOFDIR_SHIFT, TPM…
23995 #define TPM_BRD_QDCTRL_QUADIR(base) (BME_UBFX32(&TPM_QDCTRL_REG(base), TPM_QDCTRL_QUADIR_SHIFT, TPM…
24010 #define TPM_BRD_QDCTRL_QUADMODE(base) (BME_UBFX32(&TPM_QDCTRL_REG(base), TPM_QDCTRL_QUADMODE_SHIFT,…
24058 #define TPM_BRD_CONF_DOZEEN(base) (BME_UBFX32(&TPM_CONF_REG(base), TPM_CONF_DOZEEN_SHIFT, TPM_CONF_…
24079 #define TPM_BRD_CONF_DBGMODE(base) (BME_UBFX32(&TPM_CONF_REG(base), TPM_CONF_DBGMODE_SHIFT, TPM_CON…
24103 #define TPM_BRD_CONF_GTBEEN(base) (BME_UBFX32(&TPM_CONF_REG(base), TPM_CONF_GTBEEN_SHIFT, TPM_CONF_…
24129 #define TPM_BRD_CONF_CSOT(base) (BME_UBFX32(&TPM_CONF_REG(base), TPM_CONF_CSOT_SHIFT, TPM_CONF_CSOT…
24154 #define TPM_BRD_CONF_CSOO(base) (BME_UBFX32(&TPM_CONF_REG(base), TPM_CONF_CSOO_SHIFT, TPM_CONF_CSOO…
24179 #define TPM_BRD_CONF_CROT(base) (BME_UBFX32(&TPM_CONF_REG(base), TPM_CONF_CROT_SHIFT, TPM_CONF_CROT…
24196 #define TPM_BRD_CONF_TRGSEL(base) (BME_UBFX32(&TPM_CONF_REG(base), TPM_CONF_TRGSEL_SHIFT, TPM_CONF_…
24309 #define TRNG_BRD_MCTL_SAMP_MODE(base) (BME_UBFX32(&TRNG_MCTL_REG(base), TRNG_MCTL_SAMP_MODE_SHIFT, …
24333 #define TRNG_BRD_MCTL_OSC_DIV(base) (BME_UBFX32(&TRNG_MCTL_REG(base), TRNG_MCTL_OSC_DIV_SHIFT, TRNG…
24348 #define TRNG_BRD_MCTL_UNUSED(base) (BME_UBFX32(&TRNG_MCTL_REG(base), TRNG_MCTL_UNUSED_SHIFT, TRNG_M…
24366 #define TRNG_BRD_MCTL_TRNG_ACC(base) (BME_UBFX32(&TRNG_MCTL_REG(base), TRNG_MCTL_TRNG_ACC_SHIFT, TR…
24399 #define TRNG_BRD_MCTL_FOR_SCLK(base) (BME_UBFX32(&TRNG_MCTL_REG(base), TRNG_MCTL_FOR_SCLK_SHIFT, TR…
24417 #define TRNG_BRD_MCTL_FCT_FAIL(base) (BME_UBFX32(&TRNG_MCTL_REG(base), TRNG_MCTL_FCT_FAIL_SHIFT, TR…
24429 #define TRNG_BRD_MCTL_FCT_VAL(base) (BME_UBFX32(&TRNG_MCTL_REG(base), TRNG_MCTL_FCT_VAL_SHIFT, TRNG…
24442 #define TRNG_BRD_MCTL_ENT_VAL(base) (BME_UBFX32(&TRNG_MCTL_REG(base), TRNG_MCTL_ENT_VAL_SHIFT, TRNG…
24453 #define TRNG_BRD_MCTL_TST_OUT(base) (BME_UBFX32(&TRNG_MCTL_REG(base), TRNG_MCTL_TST_OUT_SHIFT, TRNG…
24465 #define TRNG_BRD_MCTL_ERR(base) (BME_UBFX32(&TRNG_MCTL_REG(base), TRNG_MCTL_ERR_SHIFT, TRNG_MCTL_ER…
24486 #define TRNG_BRD_MCTL_TSTOP_OK(base) (BME_UBFX32(&TRNG_MCTL_REG(base), TRNG_MCTL_TSTOP_OK_SHIFT, TR…
24501 #define TRNG_BRD_MCTL_PRGM(base) (BME_UBFX32(&TRNG_MCTL_REG(base), TRNG_MCTL_PRGM_SHIFT, TRNG_MCTL_…
24550 #define TRNG_BRD_SCMISC_LRUN_MAX(base) (BME_UBFX32(&TRNG_SCMISC_REG(base), TRNG_SCMISC_LRUN_MAX_SHI…
24569 #define TRNG_BRD_SCMISC_RTY_CT(base) (BME_UBFX32(&TRNG_SCMISC_REG(base), TRNG_SCMISC_RTY_CT_SHIFT, …
24619 #define TRNG_BRD_PKRRNG_PKR_RNG(base) (BME_UBFX32(&TRNG_PKRRNG_REG(base), TRNG_PKRRNG_PKR_RNG_SHIFT…
24765 #define TRNG_BRD_SDCTL_SAMP_SIZE(base) (BME_UBFX32(&TRNG_SDCTL_REG(base), TRNG_SDCTL_SAMP_SIZE_SHIF…
24783 #define TRNG_BRD_SDCTL_ENT_DLY(base) (BME_UBFX32(&TRNG_SDCTL_REG(base), TRNG_SDCTL_ENT_DLY_SHIFT, T…
24837 #define TRNG_BRD_SBLIM_SB_LIM(base) (BME_UBFX32(&TRNG_SBLIM_REG(base), TRNG_SBLIM_SB_LIM_SHIFT, TRN…
25063 #define TRNG_BRD_SCMC_MONO_CT(base) (BME_UBFX32(&TRNG_SCMC_REG(base), TRNG_SCMC_MONO_CT_SHIFT, TRNG…
25112 #define TRNG_BRD_SCML_MONO_MAX(base) (BME_UBFX32(&TRNG_SCML_REG(base), TRNG_SCML_MONO_MAX_SHIFT, TR…
25130 #define TRNG_BRD_SCML_MONO_RNG(base) (BME_UBFX32(&TRNG_SCML_REG(base), TRNG_SCML_MONO_RNG_SHIFT, TR…
25185 #define TRNG_BRD_SCR1L_RUN1_MAX(base) (BME_UBFX32(&TRNG_SCR1L_REG(base), TRNG_SCR1L_RUN1_MAX_SHIFT,…
25203 #define TRNG_BRD_SCR1L_RUN1_RNG(base) (BME_UBFX32(&TRNG_SCR1L_REG(base), TRNG_SCR1L_RUN1_RNG_SHIFT,…
25248 #define TRNG_BRD_SCR1C_R1_0_CT(base) (BME_UBFX32(&TRNG_SCR1C_REG(base), TRNG_SCR1C_R1_0_CT_SHIFT, T…
25260 #define TRNG_BRD_SCR1C_R1_1_CT(base) (BME_UBFX32(&TRNG_SCR1C_REG(base), TRNG_SCR1C_R1_1_CT_SHIFT, T…
25311 #define TRNG_BRD_SCR2L_RUN2_MAX(base) (BME_UBFX32(&TRNG_SCR2L_REG(base), TRNG_SCR2L_RUN2_MAX_SHIFT,…
25329 #define TRNG_BRD_SCR2L_RUN2_RNG(base) (BME_UBFX32(&TRNG_SCR2L_REG(base), TRNG_SCR2L_RUN2_RNG_SHIFT,…
25374 #define TRNG_BRD_SCR2C_R2_0_CT(base) (BME_UBFX32(&TRNG_SCR2C_REG(base), TRNG_SCR2C_R2_0_CT_SHIFT, T…
25386 #define TRNG_BRD_SCR2C_R2_1_CT(base) (BME_UBFX32(&TRNG_SCR2C_REG(base), TRNG_SCR2C_R2_1_CT_SHIFT, T…
25427 #define TRNG_BRD_SCR3C_R3_0_CT(base) (BME_UBFX32(&TRNG_SCR3C_REG(base), TRNG_SCR3C_R3_0_CT_SHIFT, T…
25439 #define TRNG_BRD_SCR3C_R3_1_CT(base) (BME_UBFX32(&TRNG_SCR3C_REG(base), TRNG_SCR3C_R3_1_CT_SHIFT, T…
25490 #define TRNG_BRD_SCR3L_RUN3_MAX(base) (BME_UBFX32(&TRNG_SCR3L_REG(base), TRNG_SCR3L_RUN3_MAX_SHIFT,…
25508 #define TRNG_BRD_SCR3L_RUN3_RNG(base) (BME_UBFX32(&TRNG_SCR3L_REG(base), TRNG_SCR3L_RUN3_RNG_SHIFT,…
25553 #define TRNG_BRD_SCR4C_R4_0_CT(base) (BME_UBFX32(&TRNG_SCR4C_REG(base), TRNG_SCR4C_R4_0_CT_SHIFT, T…
25565 #define TRNG_BRD_SCR4C_R4_1_CT(base) (BME_UBFX32(&TRNG_SCR4C_REG(base), TRNG_SCR4C_R4_1_CT_SHIFT, T…
25616 #define TRNG_BRD_SCR4L_RUN4_MAX(base) (BME_UBFX32(&TRNG_SCR4L_REG(base), TRNG_SCR4L_RUN4_MAX_SHIFT,…
25634 #define TRNG_BRD_SCR4L_RUN4_RNG(base) (BME_UBFX32(&TRNG_SCR4L_REG(base), TRNG_SCR4L_RUN4_RNG_SHIFT,…
25689 #define TRNG_BRD_SCR5L_RUN5_MAX(base) (BME_UBFX32(&TRNG_SCR5L_REG(base), TRNG_SCR5L_RUN5_MAX_SHIFT,…
25707 #define TRNG_BRD_SCR5L_RUN5_RNG(base) (BME_UBFX32(&TRNG_SCR5L_REG(base), TRNG_SCR5L_RUN5_RNG_SHIFT,…
25752 #define TRNG_BRD_SCR5C_R5_0_CT(base) (BME_UBFX32(&TRNG_SCR5C_REG(base), TRNG_SCR5C_R5_0_CT_SHIFT, T…
25764 #define TRNG_BRD_SCR5C_R5_1_CT(base) (BME_UBFX32(&TRNG_SCR5C_REG(base), TRNG_SCR5C_R5_1_CT_SHIFT, T…
25815 #define TRNG_BRD_SCR6PL_RUN6P_MAX(base) (BME_UBFX32(&TRNG_SCR6PL_REG(base), TRNG_SCR6PL_RUN6P_MAX_S…
25833 #define TRNG_BRD_SCR6PL_RUN6P_RNG(base) (BME_UBFX32(&TRNG_SCR6PL_REG(base), TRNG_SCR6PL_RUN6P_RNG_S…
25878 #define TRNG_BRD_SCR6PC_R6P_0_CT(base) (BME_UBFX32(&TRNG_SCR6PC_REG(base), TRNG_SCR6PC_R6P_0_CT_SHI…
25890 #define TRNG_BRD_SCR6PC_R6P_1_CT(base) (BME_UBFX32(&TRNG_SCR6PC_REG(base), TRNG_SCR6PC_R6P_1_CT_SHI…
25940 #define TRNG_BRD_STATUS_TF1BR0(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TF1BR0_SHIFT, …
25952 #define TRNG_BRD_STATUS_TF1BR1(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TF1BR1_SHIFT, …
25964 #define TRNG_BRD_STATUS_TF2BR0(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TF2BR0_SHIFT, …
25976 #define TRNG_BRD_STATUS_TF2BR1(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TF2BR1_SHIFT, …
25988 #define TRNG_BRD_STATUS_TF3BR0(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TF3BR0_SHIFT, …
26000 #define TRNG_BRD_STATUS_TF3BR1(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TF3BR1_SHIFT, …
26012 #define TRNG_BRD_STATUS_TF4BR0(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TF4BR0_SHIFT, …
26024 #define TRNG_BRD_STATUS_TF4BR1(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TF4BR1_SHIFT, …
26036 #define TRNG_BRD_STATUS_TF5BR0(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TF5BR0_SHIFT, …
26048 #define TRNG_BRD_STATUS_TF5BR1(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TF5BR1_SHIFT, …
26060 #define TRNG_BRD_STATUS_TF6PBR0(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TF6PBR0_SHIFT…
26072 #define TRNG_BRD_STATUS_TF6PBR1(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TF6PBR1_SHIFT…
26083 #define TRNG_BRD_STATUS_TFSB(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TFSB_SHIFT, TRNG…
26094 #define TRNG_BRD_STATUS_TFLR(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TFLR_SHIFT, TRNG…
26105 #define TRNG_BRD_STATUS_TFP(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TFP_SHIFT, TRNG_S…
26116 #define TRNG_BRD_STATUS_TFMB(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TFMB_SHIFT, TRNG…
26129 #define TRNG_BRD_STATUS_RETRY_CT(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_RETRY_CT_SHI…
26193 #define TRNG_BRD_PKRCNT10_PKR_0_CT(base) (BME_UBFX32(&TRNG_PKRCNT10_REG(base), TRNG_PKRCNT10_PKR_0_…
26205 #define TRNG_BRD_PKRCNT10_PKR_1_CT(base) (BME_UBFX32(&TRNG_PKRCNT10_REG(base), TRNG_PKRCNT10_PKR_1_…
26244 #define TRNG_BRD_PKRCNT32_PKR_2_CT(base) (BME_UBFX32(&TRNG_PKRCNT32_REG(base), TRNG_PKRCNT32_PKR_2_…
26256 #define TRNG_BRD_PKRCNT32_PKR_3_CT(base) (BME_UBFX32(&TRNG_PKRCNT32_REG(base), TRNG_PKRCNT32_PKR_3_…
26295 #define TRNG_BRD_PKRCNT54_PKR_4_CT(base) (BME_UBFX32(&TRNG_PKRCNT54_REG(base), TRNG_PKRCNT54_PKR_4_…
26307 #define TRNG_BRD_PKRCNT54_PKR_5_CT(base) (BME_UBFX32(&TRNG_PKRCNT54_REG(base), TRNG_PKRCNT54_PKR_5_…
26346 #define TRNG_BRD_PKRCNT76_PKR_6_CT(base) (BME_UBFX32(&TRNG_PKRCNT76_REG(base), TRNG_PKRCNT76_PKR_6_…
26358 #define TRNG_BRD_PKRCNT76_PKR_7_CT(base) (BME_UBFX32(&TRNG_PKRCNT76_REG(base), TRNG_PKRCNT76_PKR_7_…
26397 #define TRNG_BRD_PKRCNT98_PKR_8_CT(base) (BME_UBFX32(&TRNG_PKRCNT98_REG(base), TRNG_PKRCNT98_PKR_8_…
26409 #define TRNG_BRD_PKRCNT98_PKR_9_CT(base) (BME_UBFX32(&TRNG_PKRCNT98_REG(base), TRNG_PKRCNT98_PKR_9_…
26448 #define TRNG_BRD_PKRCNTBA_PKR_A_CT(base) (BME_UBFX32(&TRNG_PKRCNTBA_REG(base), TRNG_PKRCNTBA_PKR_A_…
26460 #define TRNG_BRD_PKRCNTBA_PKR_B_CT(base) (BME_UBFX32(&TRNG_PKRCNTBA_REG(base), TRNG_PKRCNTBA_PKR_B_…
26499 #define TRNG_BRD_PKRCNTDC_PKR_C_CT(base) (BME_UBFX32(&TRNG_PKRCNTDC_REG(base), TRNG_PKRCNTDC_PKR_C_…
26511 #define TRNG_BRD_PKRCNTDC_PKR_D_CT(base) (BME_UBFX32(&TRNG_PKRCNTDC_REG(base), TRNG_PKRCNTDC_PKR_D_…
26550 #define TRNG_BRD_PKRCNTFE_PKR_E_CT(base) (BME_UBFX32(&TRNG_PKRCNTFE_REG(base), TRNG_PKRCNTFE_PKR_E_…
26562 #define TRNG_BRD_PKRCNTFE_PKR_F_CT(base) (BME_UBFX32(&TRNG_PKRCNTFE_REG(base), TRNG_PKRCNTFE_PKR_F_…
26609 #define TRNG_BRD_SEC_CFG_SH0(base) (BME_UBFX32(&TRNG_SEC_CFG_REG(base), TRNG_SEC_CFG_SH0_SHIFT, TRN…
26631 #define TRNG_BRD_SEC_CFG_NO_PRGM(base) (BME_UBFX32(&TRNG_SEC_CFG_REG(base), TRNG_SEC_CFG_NO_PRGM_SH…
26650 #define TRNG_BRD_SEC_CFG_SK_VAL(base) (BME_UBFX32(&TRNG_SEC_CFG_REG(base), TRNG_SEC_CFG_SK_VAL_SHIF…
26703 #define TRNG_BRD_INT_CTRL_HW_ERR(base) (BME_UBFX32(&TRNG_INT_CTRL_REG(base), TRNG_INT_CTRL_HW_ERR_S…
26722 #define TRNG_BRD_INT_CTRL_ENT_VAL(base) (BME_UBFX32(&TRNG_INT_CTRL_REG(base), TRNG_INT_CTRL_ENT_VAL…
26741 #define TRNG_BRD_INT_CTRL_FRQ_CT_FAIL(base) (BME_UBFX32(&TRNG_INT_CTRL_REG(base), TRNG_INT_CTRL_FRQ…
26809 #define TRNG_BRD_INT_MASK_HW_ERR(base) (BME_UBFX32(&TRNG_INT_MASK_REG(base), TRNG_INT_MASK_HW_ERR_S…
26828 #define TRNG_BRD_INT_MASK_ENT_VAL(base) (BME_UBFX32(&TRNG_INT_MASK_REG(base), TRNG_INT_MASK_ENT_VAL…
26847 #define TRNG_BRD_INT_MASK_FRQ_CT_FAIL(base) (BME_UBFX32(&TRNG_INT_MASK_REG(base), TRNG_INT_MASK_FRQ…
26904 #define TRNG_BRD_INT_STATUS_HW_ERR(base) (BME_UBFX32(&TRNG_INT_STATUS_REG(base), TRNG_INT_STATUS_HW…
26921 #define TRNG_BRD_INT_STATUS_ENT_VAL(base) (BME_UBFX32(&TRNG_INT_STATUS_REG(base), TRNG_INT_STATUS_E…
26938 #define TRNG_BRD_INT_STATUS_FRQ_CT_FAIL(base) (BME_UBFX32(&TRNG_INT_STATUS_REG(base), TRNG_INT_STAT…
26980 #define TRNG_BRD_VID1_RNG_MIN_REV(base) (BME_UBFX32(&TRNG_VID1_REG(base), TRNG_VID1_RNG_MIN_REV_SHI…
26994 #define TRNG_BRD_VID1_RNG_MAJ_REV(base) (BME_UBFX32(&TRNG_VID1_REG(base), TRNG_VID1_RNG_MAJ_REV_SHI…
27005 #define TRNG_BRD_VID1_RNG_IP_ID(base) (BME_UBFX32(&TRNG_VID1_REG(base), TRNG_VID1_RNG_IP_ID_SHIFT, …
27043 #define TRNG_BRD_VID2_RNG_CONFIG_OPT(base) (BME_UBFX32(&TRNG_VID2_REG(base), TRNG_VID2_RNG_CONFIG_O…
27057 #define TRNG_BRD_VID2_RNG_ECO_REV(base) (BME_UBFX32(&TRNG_VID2_REG(base), TRNG_VID2_RNG_ECO_REV_SHI…
27071 #define TRNG_BRD_VID2_RNG_INTG_OPT(base) (BME_UBFX32(&TRNG_VID2_REG(base), TRNG_VID2_RNG_INTG_OPT_S…
27085 #define TRNG_BRD_VID2_RNG_ERA(base) (BME_UBFX32(&TRNG_VID2_REG(base), TRNG_VID2_RNG_ERA_SHIFT, TRNG…
27145 #define TSI_BRD_GENCS_CURSW(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_CURSW_SHIFT, TSI_GENC…
27165 #define TSI_BRD_GENCS_EOSF(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_EOSF_SHIFT, TSI_GENCS_…
27186 #define TSI_BRD_GENCS_SCNIP(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_SCNIP_SHIFT, TSI_GENC…
27202 #define TSI_BRD_GENCS_STM(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_STM_SHIFT, TSI_GENCS_ST…
27222 #define TSI_BRD_GENCS_STPE(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_STPE_SHIFT, TSI_GENCS_…
27242 #define TSI_BRD_GENCS_TSIIEN(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_TSIIEN_SHIFT, TSI_GE…
27261 #define TSI_BRD_GENCS_TSIEN(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_TSIEN_SHIFT, TSI_GENC…
27313 #define TSI_BRD_GENCS_NSCN(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_NSCN_SHIFT, TSI_GENCS_…
27338 #define TSI_BRD_GENCS_PS(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_PS_SHIFT, TSI_GENCS_PS_W…
27364 #define TSI_BRD_GENCS_EXTCHRG(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_EXTCHRG_SHIFT, TSI_…
27385 #define TSI_BRD_GENCS_DVOLT(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_DVOLT_SHIFT, TSI_GENC…
27411 #define TSI_BRD_GENCS_REFCHRG(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_REFCHRG_SHIFT, TSI_…
27439 #define TSI_BRD_GENCS_MODE(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_MODE_SHIFT, TSI_GENCS_…
27459 #define TSI_BRD_GENCS_ESOR(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_ESOR_SHIFT, TSI_GENCS_…
27477 #define TSI_BRD_GENCS_OUTRGF(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_OUTRGF_SHIFT, TSI_GE…
27518 #define TSI_BRD_DATA_TSICNT(base) (BME_UBFX32(&TSI_DATA_REG(base), TSI_DATA_TSICNT_SHIFT, TSI_DATA_…
27554 #define TSI_BRD_DATA_DMAEN(base) (BME_UBFX32(&TSI_DATA_REG(base), TSI_DATA_DMAEN_SHIFT, TSI_DATA_DM…
27590 #define TSI_BRD_DATA_TSICH(base) (BME_UBFX32(&TSI_DATA_REG(base), TSI_DATA_TSICH_SHIFT, TSI_DATA_TS…
27630 #define TSI_BRD_TSHD_THRESL(base) (BME_UBFX32(&TSI_TSHD_REG(base), TSI_TSHD_THRESL_SHIFT, TSI_TSHD_…
27645 #define TSI_BRD_TSHD_THRESH(base) (BME_UBFX32(&TSI_TSHD_REG(base), TSI_TSHD_THRESH_SHIFT, TSI_TSHD_…
27864 #define XCVR_BRD_RX_DIG_CTRL_RX_ADC_NEGEDGE(base) (BME_UBFX32(&XCVR_RX_DIG_CTRL_REG(base), XCVR_RX_…
27883 #define XCVR_BRD_RX_DIG_CTRL_RX_CH_FILT_BYPASS(base) (BME_UBFX32(&XCVR_RX_DIG_CTRL_REG(base), XCVR_…
27902 #define XCVR_BRD_RX_DIG_CTRL_RX_ADC_RAW_EN(base) (BME_UBFX32(&XCVR_RX_DIG_CTRL_REG(base), XCVR_RX_D…
27921 #define XCVR_BRD_RX_DIG_CTRL_RX_DEC_FILT_OSR(base) (BME_UBFX32(&XCVR_RX_DIG_CTRL_REG(base), XCVR_RX…
27938 #define XCVR_BRD_RX_DIG_CTRL_RX_INTERP_EN(base) (BME_UBFX32(&XCVR_RX_DIG_CTRL_REG(base), XCVR_RX_DI…
27955 #define XCVR_BRD_RX_DIG_CTRL_RX_NORM_EN(base) (BME_UBFX32(&XCVR_RX_DIG_CTRL_REG(base), XCVR_RX_DIG_…
27972 #define XCVR_BRD_RX_DIG_CTRL_RX_RSSI_EN(base) (BME_UBFX32(&XCVR_RX_DIG_CTRL_REG(base), XCVR_RX_DIG_…
27991 #define XCVR_BRD_RX_DIG_CTRL_RX_AGC_EN(base) (BME_UBFX32(&XCVR_RX_DIG_CTRL_REG(base), XCVR_RX_DIG_C…
28010 #define XCVR_BRD_RX_DIG_CTRL_RX_DCOC_EN(base) (BME_UBFX32(&XCVR_RX_DIG_CTRL_REG(base), XCVR_RX_DIG_…
28029 #define XCVR_BRD_RX_DIG_CTRL_RX_DCOC_CAL_EN(base) (BME_UBFX32(&XCVR_RX_DIG_CTRL_REG(base), XCVR_RX_…
28048 #define XCVR_BRD_RX_DIG_CTRL_RX_IQ_SWAP(base) (BME_UBFX32(&XCVR_RX_DIG_CTRL_REG(base), XCVR_RX_DIG_…
28088 #define XCVR_BRD_AGC_CTRL_0_SLOW_AGC_EN(base) (BME_UBFX32(&XCVR_AGC_CTRL_0_REG(base), XCVR_AGC_CTRL…
28107 #define XCVR_BRD_AGC_CTRL_0_SLOW_AGC_SRC(base) (BME_UBFX32(&XCVR_AGC_CTRL_0_REG(base), XCVR_AGC_CTR…
28123 #define XCVR_BRD_AGC_CTRL_0_AGC_FREEZE_EN(base) (BME_UBFX32(&XCVR_AGC_CTRL_0_REG(base), XCVR_AGC_CT…
28142 #define XCVR_BRD_AGC_CTRL_0_FREEZE_AGC_SRC(base) (BME_UBFX32(&XCVR_AGC_CTRL_0_REG(base), XCVR_AGC_C…
28157 #define XCVR_BRD_AGC_CTRL_0_AGC_UP_EN(base) (BME_UBFX32(&XCVR_AGC_CTRL_0_REG(base), XCVR_AGC_CTRL_0…
28176 #define XCVR_BRD_AGC_CTRL_0_AGC_UP_SRC(base) (BME_UBFX32(&XCVR_AGC_CTRL_0_REG(base), XCVR_AGC_CTRL_…
28191 #define XCVR_BRD_AGC_CTRL_0_AGC_DOWN_BBF_STEP_SZ(base) (BME_UBFX32(&XCVR_AGC_CTRL_0_REG(base), XCVR…
28206 #define XCVR_BRD_AGC_CTRL_0_AGC_DOWN_TZA_STEP_SZ(base) (BME_UBFX32(&XCVR_AGC_CTRL_0_REG(base), XCVR…
28221 #define XCVR_BRD_AGC_CTRL_0_AGC_UP_RSSI_THRESH(base) (BME_UBFX32(&XCVR_AGC_CTRL_0_REG(base), XCVR_A…
28236 #define XCVR_BRD_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(base) (BME_UBFX32(&XCVR_AGC_CTRL_0_REG(base), XCVR…
28277 #define XCVR_BRD_AGC_CTRL_1_BBF_ALT_CODE(base) (BME_UBFX32(&XCVR_AGC_CTRL_1_REG(base), XCVR_AGC_CTR…
28293 #define XCVR_BRD_AGC_CTRL_1_LNM_ALT_CODE(base) (BME_UBFX32(&XCVR_AGC_CTRL_1_REG(base), XCVR_AGC_CTR…
28308 #define XCVR_BRD_AGC_CTRL_1_LNM_USER_GAIN(base) (BME_UBFX32(&XCVR_AGC_CTRL_1_REG(base), XCVR_AGC_CT…
28323 #define XCVR_BRD_AGC_CTRL_1_BBF_USER_GAIN(base) (BME_UBFX32(&XCVR_AGC_CTRL_1_REG(base), XCVR_AGC_CT…
28338 #define XCVR_BRD_AGC_CTRL_1_USER_LNM_GAIN_EN(base) (BME_UBFX32(&XCVR_AGC_CTRL_1_REG(base), XCVR_AGC…
28353 #define XCVR_BRD_AGC_CTRL_1_USER_BBF_GAIN_EN(base) (BME_UBFX32(&XCVR_AGC_CTRL_1_REG(base), XCVR_AGC…
28372 #define XCVR_BRD_AGC_CTRL_1_PRESLOW_EN(base) (BME_UBFX32(&XCVR_AGC_CTRL_1_REG(base), XCVR_AGC_CTRL_…
28387 #define XCVR_BRD_AGC_CTRL_1_TZA_GAIN_SETTLE_TIME(base) (BME_UBFX32(&XCVR_AGC_CTRL_1_REG(base), XCVR…
28427 #define XCVR_BRD_AGC_CTRL_2_BBF_PDET_RST(base) (BME_UBFX32(&XCVR_AGC_CTRL_2_REG(base), XCVR_AGC_CTR…
28442 #define XCVR_BRD_AGC_CTRL_2_TZA_PDET_RST(base) (BME_UBFX32(&XCVR_AGC_CTRL_2_REG(base), XCVR_AGC_CTR…
28457 #define XCVR_BRD_AGC_CTRL_2_BBF_GAIN_SETTLE_TIME(base) (BME_UBFX32(&XCVR_AGC_CTRL_2_REG(base), XCVR…
28482 #define XCVR_BRD_AGC_CTRL_2_BBF_PDET_THRESH_LO(base) (BME_UBFX32(&XCVR_AGC_CTRL_2_REG(base), XCVR_A…
28507 #define XCVR_BRD_AGC_CTRL_2_BBF_PDET_THRESH_HI(base) (BME_UBFX32(&XCVR_AGC_CTRL_2_REG(base), XCVR_A…
28532 #define XCVR_BRD_AGC_CTRL_2_TZA_PDET_THRESH_LO(base) (BME_UBFX32(&XCVR_AGC_CTRL_2_REG(base), XCVR_A…
28557 #define XCVR_BRD_AGC_CTRL_2_TZA_PDET_THRESH_HI(base) (BME_UBFX32(&XCVR_AGC_CTRL_2_REG(base), XCVR_A…
28572 #define XCVR_BRD_AGC_CTRL_2_AGC_FAST_EXPIRE(base) (BME_UBFX32(&XCVR_AGC_CTRL_2_REG(base), XCVR_AGC_…
28612 #define XCVR_BRD_AGC_CTRL_3_AGC_UNFREEZE_TIME(base) (BME_UBFX32(&XCVR_AGC_CTRL_3_REG(base), XCVR_AG…
28627 #define XCVR_BRD_AGC_CTRL_3_AGC_PDET_LO_DLY(base) (BME_UBFX32(&XCVR_AGC_CTRL_3_REG(base), XCVR_AGC_…
28642 #define XCVR_BRD_AGC_CTRL_3_AGC_RSSI_DELT_H2S(base) (BME_UBFX32(&XCVR_AGC_CTRL_3_REG(base), XCVR_AG…
28657 #define XCVR_BRD_AGC_CTRL_3_AGC_H2S_STEP_SZ(base) (BME_UBFX32(&XCVR_AGC_CTRL_3_REG(base), XCVR_AGC_…
28672 #define XCVR_BRD_AGC_CTRL_3_AGC_UP_STEP_SZ(base) (BME_UBFX32(&XCVR_AGC_CTRL_3_REG(base), XCVR_AGC_C…
28707 #define XCVR_BRD_AGC_STAT_BBF_PDET_LO_STAT(base) (BME_UBFX32(&XCVR_AGC_STAT_REG(base), XCVR_AGC_STA…
28718 #define XCVR_BRD_AGC_STAT_BBF_PDET_HI_STAT(base) (BME_UBFX32(&XCVR_AGC_STAT_REG(base), XCVR_AGC_STA…
28729 #define XCVR_BRD_AGC_STAT_TZA_PDET_LO_STAT(base) (BME_UBFX32(&XCVR_AGC_STAT_REG(base), XCVR_AGC_STA…
28740 #define XCVR_BRD_AGC_STAT_TZA_PDET_HI_STAT(base) (BME_UBFX32(&XCVR_AGC_STAT_REG(base), XCVR_AGC_STA…
28751 #define XCVR_BRD_AGC_STAT_CURR_AGC_IDX(base) (BME_UBFX32(&XCVR_AGC_STAT_REG(base), XCVR_AGC_STAT_CU…
28766 #define XCVR_BRD_AGC_STAT_AGC_FROZEN(base) (BME_UBFX32(&XCVR_AGC_STAT_REG(base), XCVR_AGC_STAT_AGC_…
28777 #define XCVR_BRD_AGC_STAT_RSSI_ADC_RAW(base) (BME_UBFX32(&XCVR_AGC_STAT_REG(base), XCVR_AGC_STAT_RS…
28813 #define XCVR_BRD_RSSI_CTRL_0_RSSI_USE_VALS(base) (BME_UBFX32(&XCVR_RSSI_CTRL_0_REG(base), XCVR_RSSI…
28832 #define XCVR_BRD_RSSI_CTRL_0_RSSI_HOLD_SRC(base) (BME_UBFX32(&XCVR_RSSI_CTRL_0_REG(base), XCVR_RSSI…
28848 #define XCVR_BRD_RSSI_CTRL_0_RSSI_HOLD_EN(base) (BME_UBFX32(&XCVR_RSSI_CTRL_0_REG(base), XCVR_RSSI_…
28863 #define XCVR_BRD_RSSI_CTRL_0_RSSI_DEC_EN(base) (BME_UBFX32(&XCVR_RSSI_CTRL_0_REG(base), XCVR_RSSI_C…
28882 #define XCVR_BRD_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT(base) (BME_UBFX32(&XCVR_RSSI_CTRL_0_REG(base), XCVR…
28901 #define XCVR_BRD_RSSI_CTRL_0_RSSI_IIR_WEIGHT(base) (BME_UBFX32(&XCVR_RSSI_CTRL_0_REG(base), XCVR_RS…
28916 #define XCVR_BRD_RSSI_CTRL_0_RSSI_ADJ(base) (BME_UBFX32(&XCVR_RSSI_CTRL_0_REG(base), XCVR_RSSI_CTRL…
28956 #define XCVR_BRD_RSSI_CTRL_1_RSSI_ED_THRESH0(base) (BME_UBFX32(&XCVR_RSSI_CTRL_1_REG(base), XCVR_RS…
28971 #define XCVR_BRD_RSSI_CTRL_1_RSSI_ED_THRESH1(base) (BME_UBFX32(&XCVR_RSSI_CTRL_1_REG(base), XCVR_RS…
28986 #define XCVR_BRD_RSSI_CTRL_1_RSSI_ED_THRESH0_H(base) (BME_UBFX32(&XCVR_RSSI_CTRL_1_REG(base), XCVR_…
29001 #define XCVR_BRD_RSSI_CTRL_1_RSSI_ED_THRESH1_H(base) (BME_UBFX32(&XCVR_RSSI_CTRL_1_REG(base), XCVR_…
29016 #define XCVR_BRD_RSSI_CTRL_1_RSSI_OUT(base) (BME_UBFX32(&XCVR_RSSI_CTRL_1_REG(base), XCVR_RSSI_CTRL…
29054 #define XCVR_BRD_DCOC_CTRL_0_DCOC_MAN(base) (BME_UBFX32(&XCVR_DCOC_CTRL_0_REG(base), XCVR_DCOC_CTRL…
29070 #define XCVR_BRD_DCOC_CTRL_0_DCOC_TRACK_EN(base) (BME_UBFX32(&XCVR_DCOC_CTRL_0_REG(base), XCVR_DCOC…
29085 #define XCVR_BRD_DCOC_CTRL_0_DCOC_CORRECT_EN(base) (BME_UBFX32(&XCVR_DCOC_CTRL_0_REG(base), XCVR_DC…
29107 #define XCVR_BRD_DCOC_CTRL_0_DCOC_SIGN_SCALE_IDX(base) (BME_UBFX32(&XCVR_DCOC_CTRL_0_REG(base), XCV…
29129 #define XCVR_BRD_DCOC_CTRL_0_DCOC_ALPHAC_SCALE_IDX(base) (BME_UBFX32(&XCVR_DCOC_CTRL_0_REG(base), X…
29155 #define XCVR_BRD_DCOC_CTRL_0_DCOC_ALPHA_RADIUS_IDX(base) (BME_UBFX32(&XCVR_DCOC_CTRL_0_REG(base), X…
29170 #define XCVR_BRD_DCOC_CTRL_0_DCOC_CAL_DURATION(base) (BME_UBFX32(&XCVR_DCOC_CTRL_0_REG(base), XCVR_…
29186 #define XCVR_BRD_DCOC_CTRL_0_DCOC_CORR_DLY(base) (BME_UBFX32(&XCVR_DCOC_CTRL_0_REG(base), XCVR_DCOC…
29202 #define XCVR_BRD_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(base) (BME_UBFX32(&XCVR_DCOC_CTRL_0_REG(base), XCV…
29246 #define XCVR_BRD_DCOC_CTRL_1_BBF_DCOC_STEP(base) (BME_UBFX32(&XCVR_DCOC_CTRL_1_REG(base), XCVR_DCOC…
29266 #define XCVR_BRD_DCOC_CTRL_1_TRACK_FROM_ZERO(base) (BME_UBFX32(&XCVR_DCOC_CTRL_1_REG(base), XCVR_DC…
29286 #define XCVR_BRD_DCOC_CTRL_1_BBA_CORR_POL(base) (BME_UBFX32(&XCVR_DCOC_CTRL_1_REG(base), XCVR_DCOC_…
29306 #define XCVR_BRD_DCOC_CTRL_1_TZA_CORR_POL(base) (BME_UBFX32(&XCVR_DCOC_CTRL_1_REG(base), XCVR_DCOC_…
29349 #define XCVR_BRD_DCOC_CTRL_2_BBF_DCOC_STEP_RECIP(base) (BME_UBFX32(&XCVR_DCOC_CTRL_2_REG(base), XCV…
29389 #define XCVR_BRD_DCOC_CTRL_3_BBF_DCOC_INIT_I(base) (BME_UBFX32(&XCVR_DCOC_CTRL_3_REG(base), XCVR_DC…
29404 #define XCVR_BRD_DCOC_CTRL_3_BBF_DCOC_INIT_Q(base) (BME_UBFX32(&XCVR_DCOC_CTRL_3_REG(base), XCVR_DC…
29419 #define XCVR_BRD_DCOC_CTRL_3_TZA_DCOC_INIT_I(base) (BME_UBFX32(&XCVR_DCOC_CTRL_3_REG(base), XCVR_DC…
29434 #define XCVR_BRD_DCOC_CTRL_3_TZA_DCOC_INIT_Q(base) (BME_UBFX32(&XCVR_DCOC_CTRL_3_REG(base), XCVR_DC…
29475 #define XCVR_BRD_DCOC_CTRL_4_DIG_DCOC_INIT_I(base) (BME_UBFX32(&XCVR_DCOC_CTRL_4_REG(base), XCVR_DC…
29491 #define XCVR_BRD_DCOC_CTRL_4_DIG_DCOC_INIT_Q(base) (BME_UBFX32(&XCVR_DCOC_CTRL_4_REG(base), XCVR_DC…
29532 #define XCVR_BRD_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN1(base) (BME_UBFX32(&XCVR_DCOC_CAL_GAIN_REG(base), …
29548 #define XCVR_BRD_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN1(base) (BME_UBFX32(&XCVR_DCOC_CAL_GAIN_REG(base), …
29564 #define XCVR_BRD_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN2(base) (BME_UBFX32(&XCVR_DCOC_CAL_GAIN_REG(base), …
29580 #define XCVR_BRD_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN2(base) (BME_UBFX32(&XCVR_DCOC_CAL_GAIN_REG(base), …
29596 #define XCVR_BRD_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN3(base) (BME_UBFX32(&XCVR_DCOC_CAL_GAIN_REG(base), …
29612 #define XCVR_BRD_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN3(base) (BME_UBFX32(&XCVR_DCOC_CAL_GAIN_REG(base), …
29650 #define XCVR_BRD_DCOC_STAT_BBF_DCOC_I(base) (BME_UBFX32(&XCVR_DCOC_STAT_REG(base), XCVR_DCOC_STAT_B…
29664 #define XCVR_BRD_DCOC_STAT_BBF_DCOC_Q(base) (BME_UBFX32(&XCVR_DCOC_STAT_REG(base), XCVR_DCOC_STAT_B…
29678 #define XCVR_BRD_DCOC_STAT_TZA_DCOC_I(base) (BME_UBFX32(&XCVR_DCOC_STAT_REG(base), XCVR_DCOC_STAT_T…
29692 #define XCVR_BRD_DCOC_STAT_TZA_DCOC_Q(base) (BME_UBFX32(&XCVR_DCOC_STAT_REG(base), XCVR_DCOC_STAT_T…
29724 #define XCVR_BRD_DCOC_DC_EST_DC_EST_I(base) (BME_UBFX32(&XCVR_DCOC_DC_EST_REG(base), XCVR_DCOC_DC_E…
29736 #define XCVR_BRD_DCOC_DC_EST_DC_EST_Q(base) (BME_UBFX32(&XCVR_DCOC_DC_EST_REG(base), XCVR_DCOC_DC_E…
29774 #define XCVR_BRD_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP(base) (BME_UBFX32(&XCVR_DCOC_CAL_RCP_REG(base), X…
29792 #define XCVR_BRD_DCOC_CAL_RCP_ALPHA_CALC_RECIP(base) (BME_UBFX32(&XCVR_DCOC_CAL_RCP_REG(base), XCVR…
29832 #define XCVR_BRD_IQMC_CTRL_IQMC_CAL_EN(base) (BME_UBFX32(&XCVR_IQMC_CTRL_REG(base), XCVR_IQMC_CTRL_…
29847 #define XCVR_BRD_IQMC_CTRL_IQMC_NUM_ITER(base) (BME_UBFX32(&XCVR_IQMC_CTRL_REG(base), XCVR_IQMC_CTR…
29887 #define XCVR_BRD_IQMC_CAL_IQMC_GAIN_ADJ(base) (BME_UBFX32(&XCVR_IQMC_CAL_REG(base), XCVR_IQMC_CAL_I…
29902 #define XCVR_BRD_IQMC_CAL_IQMC_PHASE_ADJ(base) (BME_UBFX32(&XCVR_IQMC_CAL_REG(base), XCVR_IQMC_CAL_…
29942 #define XCVR_BRD_TCA_AGC_VAL_3_0_TCA_AGC_VAL_0(base) (BME_UBFX32(&XCVR_TCA_AGC_VAL_3_0_REG(base), X…
29957 #define XCVR_BRD_TCA_AGC_VAL_3_0_TCA_AGC_VAL_1(base) (BME_UBFX32(&XCVR_TCA_AGC_VAL_3_0_REG(base), X…
29972 #define XCVR_BRD_TCA_AGC_VAL_3_0_TCA_AGC_VAL_2(base) (BME_UBFX32(&XCVR_TCA_AGC_VAL_3_0_REG(base), X…
29987 #define XCVR_BRD_TCA_AGC_VAL_3_0_TCA_AGC_VAL_3(base) (BME_UBFX32(&XCVR_TCA_AGC_VAL_3_0_REG(base), X…
30027 #define XCVR_BRD_TCA_AGC_VAL_7_4_TCA_AGC_VAL_4(base) (BME_UBFX32(&XCVR_TCA_AGC_VAL_7_4_REG(base), X…
30042 #define XCVR_BRD_TCA_AGC_VAL_7_4_TCA_AGC_VAL_5(base) (BME_UBFX32(&XCVR_TCA_AGC_VAL_7_4_REG(base), X…
30057 #define XCVR_BRD_TCA_AGC_VAL_7_4_TCA_AGC_VAL_6(base) (BME_UBFX32(&XCVR_TCA_AGC_VAL_7_4_REG(base), X…
30072 #define XCVR_BRD_TCA_AGC_VAL_7_4_TCA_AGC_VAL_7(base) (BME_UBFX32(&XCVR_TCA_AGC_VAL_7_4_REG(base), X…
30112 #define XCVR_BRD_TCA_AGC_VAL_8_TCA_AGC_VAL_8(base) (BME_UBFX32(&XCVR_TCA_AGC_VAL_8_REG(base), XCVR_…
30152 #define XCVR_BRD_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_0(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_VAL_7…
30167 #define XCVR_BRD_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_1(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_VAL_7…
30182 #define XCVR_BRD_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_2(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_VAL_7…
30197 #define XCVR_BRD_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_3(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_VAL_7…
30212 #define XCVR_BRD_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_4(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_VAL_7…
30227 #define XCVR_BRD_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_5(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_VAL_7…
30242 #define XCVR_BRD_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_6(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_VAL_7…
30257 #define XCVR_BRD_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_7(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_VAL_7…
30297 #define XCVR_BRD_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_8(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_VAL_…
30312 #define XCVR_BRD_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_9(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_VAL_…
30327 #define XCVR_BRD_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_10(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_VAL…
30367 #define XCVR_BRD_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_0(base) (BME_UBFX32(&XCVR_TCA_AGC_LIN_VAL_2_0_…
30383 #define XCVR_BRD_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_1(base) (BME_UBFX32(&XCVR_TCA_AGC_LIN_VAL_2_0_…
30399 #define XCVR_BRD_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_2(base) (BME_UBFX32(&XCVR_TCA_AGC_LIN_VAL_2_0_…
30440 #define XCVR_BRD_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_3(base) (BME_UBFX32(&XCVR_TCA_AGC_LIN_VAL_5_3_…
30456 #define XCVR_BRD_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_4(base) (BME_UBFX32(&XCVR_TCA_AGC_LIN_VAL_5_3_…
30472 #define XCVR_BRD_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_5(base) (BME_UBFX32(&XCVR_TCA_AGC_LIN_VAL_5_3_…
30513 #define XCVR_BRD_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_6(base) (BME_UBFX32(&XCVR_TCA_AGC_LIN_VAL_8_6_…
30529 #define XCVR_BRD_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_7(base) (BME_UBFX32(&XCVR_TCA_AGC_LIN_VAL_8_6_…
30545 #define XCVR_BRD_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_8(base) (BME_UBFX32(&XCVR_TCA_AGC_LIN_VAL_8_6_…
30586 #define XCVR_BRD_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_0(base) (BME_UBFX32(&XCVR_BBF_RES_TU…
30602 #define XCVR_BRD_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_1(base) (BME_UBFX32(&XCVR_BBF_RES_TU…
30618 #define XCVR_BRD_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_2(base) (BME_UBFX32(&XCVR_BBF_RES_TU…
30634 #define XCVR_BRD_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_3(base) (BME_UBFX32(&XCVR_BBF_RES_TU…
30675 #define XCVR_BRD_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_4(base) (BME_UBFX32(&XCVR_BBF_RES_TU…
30691 #define XCVR_BRD_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_5(base) (BME_UBFX32(&XCVR_BBF_RES_TU…
30707 #define XCVR_BRD_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_6(base) (BME_UBFX32(&XCVR_BBF_RES_TU…
30723 #define XCVR_BRD_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_7(base) (BME_UBFX32(&XCVR_BBF_RES_TU…
30764 #define XCVR_BRD_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_8(base) (BME_UBFX32(&XCVR_BBF_RES_T…
30780 #define XCVR_BRD_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_9(base) (BME_UBFX32(&XCVR_BBF_RES_T…
30796 #define XCVR_BRD_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_10(base) (BME_UBFX32(&XCVR_BBF_RES_…
30836 #define XCVR_BRD_AGC_GAIN_TBL_03_00_BBF_GAIN_00(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_03_00_REG(base…
30851 #define XCVR_BRD_AGC_GAIN_TBL_03_00_LNM_GAIN_00(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_03_00_REG(base…
30866 #define XCVR_BRD_AGC_GAIN_TBL_03_00_BBF_GAIN_01(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_03_00_REG(base…
30881 #define XCVR_BRD_AGC_GAIN_TBL_03_00_LNM_GAIN_01(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_03_00_REG(base…
30896 #define XCVR_BRD_AGC_GAIN_TBL_03_00_BBF_GAIN_02(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_03_00_REG(base…
30911 #define XCVR_BRD_AGC_GAIN_TBL_03_00_LNM_GAIN_02(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_03_00_REG(base…
30926 #define XCVR_BRD_AGC_GAIN_TBL_03_00_BBF_GAIN_03(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_03_00_REG(base…
30941 #define XCVR_BRD_AGC_GAIN_TBL_03_00_LNM_GAIN_03(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_03_00_REG(base…
30981 #define XCVR_BRD_AGC_GAIN_TBL_07_04_BBF_GAIN_04(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_07_04_REG(base…
30996 #define XCVR_BRD_AGC_GAIN_TBL_07_04_LNM_GAIN_04(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_07_04_REG(base…
31011 #define XCVR_BRD_AGC_GAIN_TBL_07_04_BBF_GAIN_05(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_07_04_REG(base…
31026 #define XCVR_BRD_AGC_GAIN_TBL_07_04_LNM_GAIN_05(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_07_04_REG(base…
31041 #define XCVR_BRD_AGC_GAIN_TBL_07_04_BBF_GAIN_06(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_07_04_REG(base…
31056 #define XCVR_BRD_AGC_GAIN_TBL_07_04_LNM_GAIN_06(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_07_04_REG(base…
31071 #define XCVR_BRD_AGC_GAIN_TBL_07_04_BBF_GAIN_07(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_07_04_REG(base…
31086 #define XCVR_BRD_AGC_GAIN_TBL_07_04_LNM_GAIN_07(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_07_04_REG(base…
31126 #define XCVR_BRD_AGC_GAIN_TBL_11_08_BBF_GAIN_08(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_11_08_REG(base…
31141 #define XCVR_BRD_AGC_GAIN_TBL_11_08_LNM_GAIN_08(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_11_08_REG(base…
31156 #define XCVR_BRD_AGC_GAIN_TBL_11_08_BBF_GAIN_09(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_11_08_REG(base…
31171 #define XCVR_BRD_AGC_GAIN_TBL_11_08_LNM_GAIN_09(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_11_08_REG(base…
31186 #define XCVR_BRD_AGC_GAIN_TBL_11_08_BBF_GAIN_10(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_11_08_REG(base…
31201 #define XCVR_BRD_AGC_GAIN_TBL_11_08_LNM_GAIN_10(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_11_08_REG(base…
31216 #define XCVR_BRD_AGC_GAIN_TBL_11_08_BBF_GAIN_11(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_11_08_REG(base…
31231 #define XCVR_BRD_AGC_GAIN_TBL_11_08_LNM_GAIN_11(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_11_08_REG(base…
31271 #define XCVR_BRD_AGC_GAIN_TBL_15_12_BBF_GAIN_12(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_15_12_REG(base…
31286 #define XCVR_BRD_AGC_GAIN_TBL_15_12_LNM_GAIN_12(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_15_12_REG(base…
31301 #define XCVR_BRD_AGC_GAIN_TBL_15_12_BBF_GAIN_13(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_15_12_REG(base…
31316 #define XCVR_BRD_AGC_GAIN_TBL_15_12_LNM_GAIN_13(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_15_12_REG(base…
31331 #define XCVR_BRD_AGC_GAIN_TBL_15_12_BBF_GAIN_14(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_15_12_REG(base…
31346 #define XCVR_BRD_AGC_GAIN_TBL_15_12_LNM_GAIN_14(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_15_12_REG(base…
31361 #define XCVR_BRD_AGC_GAIN_TBL_15_12_BBF_GAIN_15(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_15_12_REG(base…
31376 #define XCVR_BRD_AGC_GAIN_TBL_15_12_LNM_GAIN_15(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_15_12_REG(base…
31416 #define XCVR_BRD_AGC_GAIN_TBL_19_16_BBF_GAIN_16(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_19_16_REG(base…
31431 #define XCVR_BRD_AGC_GAIN_TBL_19_16_LNM_GAIN_16(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_19_16_REG(base…
31446 #define XCVR_BRD_AGC_GAIN_TBL_19_16_BBF_GAIN_17(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_19_16_REG(base…
31461 #define XCVR_BRD_AGC_GAIN_TBL_19_16_LNM_GAIN_17(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_19_16_REG(base…
31476 #define XCVR_BRD_AGC_GAIN_TBL_19_16_BBF_GAIN_18(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_19_16_REG(base…
31491 #define XCVR_BRD_AGC_GAIN_TBL_19_16_LNM_GAIN_18(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_19_16_REG(base…
31506 #define XCVR_BRD_AGC_GAIN_TBL_19_16_BBF_GAIN_19(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_19_16_REG(base…
31521 #define XCVR_BRD_AGC_GAIN_TBL_19_16_LNM_GAIN_19(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_19_16_REG(base…
31561 #define XCVR_BRD_AGC_GAIN_TBL_23_20_BBF_GAIN_20(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_23_20_REG(base…
31576 #define XCVR_BRD_AGC_GAIN_TBL_23_20_LNM_GAIN_20(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_23_20_REG(base…
31591 #define XCVR_BRD_AGC_GAIN_TBL_23_20_BBF_GAIN_21(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_23_20_REG(base…
31606 #define XCVR_BRD_AGC_GAIN_TBL_23_20_LNM_GAIN_21(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_23_20_REG(base…
31621 #define XCVR_BRD_AGC_GAIN_TBL_23_20_BBF_GAIN_22(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_23_20_REG(base…
31636 #define XCVR_BRD_AGC_GAIN_TBL_23_20_LNM_GAIN_22(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_23_20_REG(base…
31651 #define XCVR_BRD_AGC_GAIN_TBL_23_20_BBF_GAIN_23(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_23_20_REG(base…
31666 #define XCVR_BRD_AGC_GAIN_TBL_23_20_LNM_GAIN_23(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_23_20_REG(base…
31706 #define XCVR_BRD_AGC_GAIN_TBL_26_24_BBF_GAIN_24(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_26_24_REG(base…
31721 #define XCVR_BRD_AGC_GAIN_TBL_26_24_LNM_GAIN_24(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_26_24_REG(base…
31736 #define XCVR_BRD_AGC_GAIN_TBL_26_24_BBF_GAIN_25(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_26_24_REG(base…
31751 #define XCVR_BRD_AGC_GAIN_TBL_26_24_LNM_GAIN_25(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_26_24_REG(base…
31766 #define XCVR_BRD_AGC_GAIN_TBL_26_24_BBF_GAIN_26(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_26_24_REG(base…
31781 #define XCVR_BRD_AGC_GAIN_TBL_26_24_LNM_GAIN_26(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_26_24_REG(base…
31823 #define XCVR_BRD_DCOC_OFFSET__DCOC_BBF_OFFSET_I(base, index) (BME_UBFX32(&XCVR_DCOC_OFFSET__REG(bas…
31840 #define XCVR_BRD_DCOC_OFFSET__DCOC_BBF_OFFSET_Q(base, index) (BME_UBFX32(&XCVR_DCOC_OFFSET__REG(bas…
31857 #define XCVR_BRD_DCOC_OFFSET__DCOC_TZA_OFFSET_I(base, index) (BME_UBFX32(&XCVR_DCOC_OFFSET__REG(bas…
31874 #define XCVR_BRD_DCOC_OFFSET__DCOC_TZA_OFFSET_Q(base, index) (BME_UBFX32(&XCVR_DCOC_OFFSET__REG(bas…
31917 #define XCVR_BRD_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP(base, index) (BME_UBFX32(&XCVR_DCOC_TZA_STEP__REG…
31937 #define XCVR_BRD_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN(base, index) (BME_UBFX32(&XCVR_DCOC_TZA_STEP__RE…
31974 #define XCVR_BRD_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_I(base) (BME_UBFX32(&XCVR_DCOC_CAL_ALPHA_REG(base), …
31987 #define XCVR_BRD_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_Q(base) (BME_UBFX32(&XCVR_DCOC_CAL_ALPHA_REG(base), …
32020 #define XCVR_BRD_DCOC_CAL_BETA_DCOC_CAL_BETA_I(base) (BME_UBFX32(&XCVR_DCOC_CAL_BETA_REG(base), XCV…
32033 #define XCVR_BRD_DCOC_CAL_BETA_DCOC_CAL_BETA_Q(base) (BME_UBFX32(&XCVR_DCOC_CAL_BETA_REG(base), XCV…
32066 #define XCVR_BRD_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_I(base) (BME_UBFX32(&XCVR_DCOC_CAL_GAMMA_REG(base), …
32079 #define XCVR_BRD_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_Q(base) (BME_UBFX32(&XCVR_DCOC_CAL_GAMMA_REG(base), …
32120 #define XCVR_BRD_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(base) (BME_UBFX32(&XCVR_DCOC_CAL_IIR_REG(base), XC…
32140 #define XCVR_BRD_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(base) (BME_UBFX32(&XCVR_DCOC_CAL_IIR_REG(base), XC…
32160 #define XCVR_BRD_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(base) (BME_UBFX32(&XCVR_DCOC_CAL_IIR_REG(base), XC…
32199 #define XCVR_BRD_DCOC_CAL_DCOC_CAL_RES_I(base, index) (BME_UBFX32(&XCVR_DCOC_CAL_REG(base, index), …
32212 #define XCVR_BRD_DCOC_CAL_DCOC_CAL_RES_Q(base, index) (BME_UBFX32(&XCVR_DCOC_CAL_REG(base, index), …
32250 #define XCVR_BRD_RX_CHF_COEF_RX_CH_FILT_HX(base, index) (BME_UBFX32(&XCVR_RX_CHF_COEF_REG(base, ind…
32314 #define XCVR_BRD_TX_DIG_CTRL_DFT_MODE(base) (BME_UBFX32(&XCVR_TX_DIG_CTRL_REG(base), XCVR_TX_DIG_CT…
32330 #define XCVR_BRD_TX_DIG_CTRL_DFT_EN(base) (BME_UBFX32(&XCVR_TX_DIG_CTRL_REG(base), XCVR_TX_DIG_CTRL…
32356 #define XCVR_BRD_TX_DIG_CTRL_DFT_LFSR_LEN(base) (BME_UBFX32(&XCVR_TX_DIG_CTRL_REG(base), XCVR_TX_DI…
32375 #define XCVR_BRD_TX_DIG_CTRL_LFSR_EN(base) (BME_UBFX32(&XCVR_TX_DIG_CTRL_REG(base), XCVR_TX_DIG_CTR…
32401 #define XCVR_BRD_TX_DIG_CTRL_DFT_CLK_SEL(base) (BME_UBFX32(&XCVR_TX_DIG_CTRL_REG(base), XCVR_TX_DIG…
32427 #define XCVR_BRD_TX_DIG_CTRL_TONE_SEL(base) (BME_UBFX32(&XCVR_TX_DIG_CTRL_REG(base), XCVR_TX_DIG_CT…
32450 #define XCVR_BRD_TX_DIG_CTRL_POL(base) (BME_UBFX32(&XCVR_TX_DIG_CTRL_REG(base), XCVR_TX_DIG_CTRL_PO…
32476 #define XCVR_BRD_TX_DIG_CTRL_DP_SEL(base) (BME_UBFX32(&XCVR_TX_DIG_CTRL_REG(base), XCVR_TX_DIG_CTRL…
32493 #define XCVR_BRD_TX_DIG_CTRL_FREQ_WORD_ADJ(base) (BME_UBFX32(&XCVR_TX_DIG_CTRL_REG(base), XCVR_TX_D…
32534 #define XCVR_BRD_TX_DATA_PAD_PAT_DATA_PADDING_PAT_0(base) (BME_UBFX32(&XCVR_TX_DATA_PAD_PAT_REG(bas…
32550 #define XCVR_BRD_TX_DATA_PAD_PAT_DATA_PADDING_PAT_1(base) (BME_UBFX32(&XCVR_TX_DATA_PAD_PAT_REG(bas…
32566 #define XCVR_BRD_TX_DATA_PAD_PAT_DFT_LFSR_OUT(base) (BME_UBFX32(&XCVR_TX_DATA_PAD_PAT_REG(base), XC…
32580 #define XCVR_BRD_TX_DATA_PAD_PAT_LRM(base) (BME_UBFX32(&XCVR_TX_DATA_PAD_PAT_REG(base), XCVR_TX_DAT…
32626 #define XCVR_BRD_TX_GFSK_MOD_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(base) (BME_UBFX32(&XCVR_TX_GFSK_MOD_CT…
32649 #define XCVR_BRD_TX_GFSK_MOD_CTRL_GFSK_MI(base) (BME_UBFX32(&XCVR_TX_GFSK_MOD_CTRL_REG(base), XCVR_…
32665 #define XCVR_BRD_TX_GFSK_MOD_CTRL_GFSK_MLD(base) (BME_UBFX32(&XCVR_TX_GFSK_MOD_CTRL_REG(base), XCVR…
32692 #define XCVR_BRD_TX_GFSK_MOD_CTRL_GFSK_SYMBOL_RATE(base) (BME_UBFX32(&XCVR_TX_GFSK_MOD_CTRL_REG(bas…
32710 #define XCVR_BRD_TX_GFSK_MOD_CTRL_GFSK_FLD(base) (BME_UBFX32(&XCVR_TX_GFSK_MOD_CTRL_REG(base), XCVR…
32810 #define XCVR_BRD_TX_FSK_MOD_SCALE_FSK_MODULATION_SCALE_0(base) (BME_UBFX32(&XCVR_TX_FSK_MOD_SCALE_R…
32833 #define XCVR_BRD_TX_FSK_MOD_SCALE_FSK_MODULATION_SCALE_1(base) (BME_UBFX32(&XCVR_TX_FSK_MOD_SCALE_R…
32903 #define XCVR_BRD_TX_DFT_TONE_0_1_DFT_TONE_1(base) (BME_UBFX32(&XCVR_TX_DFT_TONE_0_1_REG(base), XCVR…
32922 #define XCVR_BRD_TX_DFT_TONE_0_1_DFT_TONE_0(base) (BME_UBFX32(&XCVR_TX_DFT_TONE_0_1_REG(base), XCVR…
32971 #define XCVR_BRD_TX_DFT_TONE_2_3_DFT_TONE_3(base) (BME_UBFX32(&XCVR_TX_DFT_TONE_2_3_REG(base), XCVR…
32990 #define XCVR_BRD_TX_DFT_TONE_2_3_DFT_TONE_2(base) (BME_UBFX32(&XCVR_TX_DFT_TONE_2_3_REG(base), XCVR…
33031 #define XCVR_BRD_PLL_MOD_OVRD_MODULATION_WORD_MANUAL(base) (BME_UBFX32(&XCVR_PLL_MOD_OVRD_REG(base)…
33047 #define XCVR_BRD_PLL_MOD_OVRD_MOD_DIS(base) (BME_UBFX32(&XCVR_PLL_MOD_OVRD_REG(base), XCVR_PLL_MOD_…
33063 #define XCVR_BRD_PLL_MOD_OVRD_HPM_BANK_MANUAL(base) (BME_UBFX32(&XCVR_PLL_MOD_OVRD_REG(base), XCVR_…
33079 #define XCVR_BRD_PLL_MOD_OVRD_HPM_BANK_DIS(base) (BME_UBFX32(&XCVR_PLL_MOD_OVRD_REG(base), XCVR_PLL…
33095 #define XCVR_BRD_PLL_MOD_OVRD_HPM_LSB_MANUAL(base) (BME_UBFX32(&XCVR_PLL_MOD_OVRD_REG(base), XCVR_P…
33112 #define XCVR_BRD_PLL_MOD_OVRD_HPM_LSB_DIS(base) (BME_UBFX32(&XCVR_PLL_MOD_OVRD_REG(base), XCVR_PLL_…
33181 #define XCVR_BRD_PLL_CHAN_MAP_CHANNEL_NUM(base) (BME_UBFX32(&XCVR_PLL_CHAN_MAP_REG(base), XCVR_PLL_…
33200 #define XCVR_BRD_PLL_CHAN_MAP_BOC(base) (BME_UBFX32(&XCVR_PLL_CHAN_MAP_REG(base), XCVR_PLL_CHAN_MAP…
33220 #define XCVR_BRD_PLL_CHAN_MAP_BMR(base) (BME_UBFX32(&XCVR_PLL_CHAN_MAP_REG(base), XCVR_PLL_CHAN_MAP…
33239 #define XCVR_BRD_PLL_CHAN_MAP_ZOC(base) (BME_UBFX32(&XCVR_PLL_CHAN_MAP_REG(base), XCVR_PLL_CHAN_MAP…
33280 #define XCVR_BRD_PLL_LOCK_DETECT_CT_FAIL(base) (BME_UBFX32(&XCVR_PLL_LOCK_DETECT_REG(base), XCVR_PL…
33292 #define XCVR_BRD_PLL_LOCK_DETECT_CTFF(base) (BME_UBFX32(&XCVR_PLL_LOCK_DETECT_REG(base), XCVR_PLL_L…
33309 #define XCVR_BRD_PLL_LOCK_DETECT_CS_FAIL(base) (BME_UBFX32(&XCVR_PLL_LOCK_DETECT_REG(base), XCVR_PL…
33321 #define XCVR_BRD_PLL_LOCK_DETECT_CSFF(base) (BME_UBFX32(&XCVR_PLL_LOCK_DETECT_REG(base), XCVR_PLL_L…
33337 #define XCVR_BRD_PLL_LOCK_DETECT_FT_FAIL(base) (BME_UBFX32(&XCVR_PLL_LOCK_DETECT_REG(base), XCVR_PL…
33349 #define XCVR_BRD_PLL_LOCK_DETECT_FTFF(base) (BME_UBFX32(&XCVR_PLL_LOCK_DETECT_REG(base), XCVR_PLL_L…
33365 #define XCVR_BRD_PLL_LOCK_DETECT_TAFF(base) (BME_UBFX32(&XCVR_PLL_LOCK_DETECT_REG(base), XCVR_PLL_L…
33382 #define XCVR_BRD_PLL_LOCK_DETECT_CTUNE_LDF_LEV(base) (BME_UBFX32(&XCVR_PLL_LOCK_DETECT_REG(base), X…
33399 #define XCVR_BRD_PLL_LOCK_DETECT_FTF_RX_THRSH(base) (BME_UBFX32(&XCVR_PLL_LOCK_DETECT_REG(base), XC…
33420 #define XCVR_BRD_PLL_LOCK_DETECT_FTW_RX(base) (BME_UBFX32(&XCVR_PLL_LOCK_DETECT_REG(base), XCVR_PLL…
33437 #define XCVR_BRD_PLL_LOCK_DETECT_FTF_TX_THRSH(base) (BME_UBFX32(&XCVR_PLL_LOCK_DETECT_REG(base), XC…
33458 #define XCVR_BRD_PLL_LOCK_DETECT_FTW_TX(base) (BME_UBFX32(&XCVR_PLL_LOCK_DETECT_REG(base), XCVR_PLL…
33499 #define XCVR_BRD_PLL_HP_MOD_CTRL_HPM_SDM_MANUAL(base) (BME_UBFX32(&XCVR_PLL_HP_MOD_CTRL_REG(base), …
33516 #define XCVR_BRD_PLL_HP_MOD_CTRL_HPFF(base) (BME_UBFX32(&XCVR_PLL_HP_MOD_CTRL_REG(base), XCVR_PLL_H…
33532 #define XCVR_BRD_PLL_HP_MOD_CTRL_HP_SDM_INV(base) (BME_UBFX32(&XCVR_PLL_HP_MOD_CTRL_REG(base), XCVR…
33548 #define XCVR_BRD_PLL_HP_MOD_CTRL_HP_SDM_DIS(base) (BME_UBFX32(&XCVR_PLL_HP_MOD_CTRL_REG(base), XCVR…
33574 #define XCVR_BRD_PLL_HP_MOD_CTRL_HPM_LFSR_LEN(base) (BME_UBFX32(&XCVR_PLL_HP_MOD_CTRL_REG(base), XC…
33590 #define XCVR_BRD_PLL_HP_MOD_CTRL_HP_DTH_SCL(base) (BME_UBFX32(&XCVR_PLL_HP_MOD_CTRL_REG(base), XCVR…
33606 #define XCVR_BRD_PLL_HP_MOD_CTRL_HPM_DTH_EN(base) (BME_UBFX32(&XCVR_PLL_HP_MOD_CTRL_REG(base), XCVR…
33628 #define XCVR_BRD_PLL_HP_MOD_CTRL_HPM_SCALE(base) (BME_UBFX32(&XCVR_PLL_HP_MOD_CTRL_REG(base), XCVR_…
33646 #define XCVR_BRD_PLL_HP_MOD_CTRL_HP_MOD_INV(base) (BME_UBFX32(&XCVR_PLL_HP_MOD_CTRL_REG(base), XCVR…
33686 #define XCVR_BRD_PLL_HPM_CAL_CTRL_HPM_CAL_FACTOR(base) (BME_UBFX32(&XCVR_PLL_HPM_CAL_CTRL_REG(base)…
33698 #define XCVR_BRD_PLL_HPM_CAL_CTRL_HP_CAL_DIS(base) (BME_UBFX32(&XCVR_PLL_HPM_CAL_CTRL_REG(base), XC…
33714 #define XCVR_BRD_PLL_HPM_CAL_CTRL_HPM_CAL_FACTOR_MANUAL(base) (BME_UBFX32(&XCVR_PLL_HPM_CAL_CTRL_RE…
33734 #define XCVR_BRD_PLL_HPM_CAL_CTRL_HP_CAL_ARY(base) (BME_UBFX32(&XCVR_PLL_HPM_CAL_CTRL_REG(base), XC…
33754 #define XCVR_BRD_PLL_HPM_CAL_CTRL_HP_CAL_TIME(base) (BME_UBFX32(&XCVR_PLL_HPM_CAL_CTRL_REG(base), X…
33816 #define XCVR_BRD_PLL_LD_HPM_CAL1_CS_WT(base) (BME_UBFX32(&XCVR_PLL_LD_HPM_CAL1_REG(base), XCVR_PLL_…
33842 #define XCVR_BRD_PLL_LD_HPM_CAL1_CS_FW(base) (BME_UBFX32(&XCVR_PLL_LD_HPM_CAL1_REG(base), XCVR_PLL_…
33858 #define XCVR_BRD_PLL_LD_HPM_CAL1_CS_FCNT(base) (BME_UBFX32(&XCVR_PLL_LD_HPM_CAL1_REG(base), XCVR_PL…
33910 #define XCVR_BRD_PLL_LD_HPM_CAL2_CS_RC(base) (BME_UBFX32(&XCVR_PLL_LD_HPM_CAL2_REG(base), XCVR_PLL_…
33927 #define XCVR_BRD_PLL_LD_HPM_CAL2_CS_FT(base) (BME_UBFX32(&XCVR_PLL_LD_HPM_CAL2_REG(base), XCVR_PLL_…
33969 #define XCVR_BRD_PLL_HPM_SDM_FRACTION_HPM_NUM_SELECTED(base) (BME_UBFX32(&XCVR_PLL_HPM_SDM_FRACTION…
33985 #define XCVR_BRD_PLL_HPM_SDM_FRACTION_HPM_DENOM(base) (BME_UBFX32(&XCVR_PLL_HPM_SDM_FRACTION_REG(ba…
34026 #define XCVR_BRD_PLL_LP_MOD_CTRL_PLL_LOOP_DIVIDER_MANUAL(base) (BME_UBFX32(&XCVR_PLL_LP_MOD_CTRL_RE…
34043 #define XCVR_BRD_PLL_LP_MOD_CTRL_PLL_LD_DIS(base) (BME_UBFX32(&XCVR_PLL_LP_MOD_CTRL_REG(base), XCVR…
34060 #define XCVR_BRD_PLL_LP_MOD_CTRL_LPFF(base) (BME_UBFX32(&XCVR_PLL_LP_MOD_CTRL_REG(base), XCVR_PLL_L…
34076 #define XCVR_BRD_PLL_LP_MOD_CTRL_LPM_SDM_INV(base) (BME_UBFX32(&XCVR_PLL_LP_MOD_CTRL_REG(base), XCV…
34094 #define XCVR_BRD_PLL_LP_MOD_CTRL_LPM_SDM_DIS(base) (BME_UBFX32(&XCVR_PLL_LP_MOD_CTRL_REG(base), XCV…
34130 #define XCVR_BRD_PLL_LP_MOD_CTRL_LPM_DTH_SCL(base) (BME_UBFX32(&XCVR_PLL_LP_MOD_CTRL_REG(base), XCV…
34145 #define XCVR_BRD_PLL_LP_MOD_CTRL_LPM_D_CTRL(base) (BME_UBFX32(&XCVR_PLL_LP_MOD_CTRL_REG(base), XCVR…
34165 #define XCVR_BRD_PLL_LP_MOD_CTRL_LPM_D_OVRD(base) (BME_UBFX32(&XCVR_PLL_LP_MOD_CTRL_REG(base), XCVR…
34200 #define XCVR_BRD_PLL_LP_MOD_CTRL_LPM_SCALE(base) (BME_UBFX32(&XCVR_PLL_LP_MOD_CTRL_REG(base), XCVR_…
34241 #define XCVR_BRD_PLL_LP_SDM_CTRL1_LPM_INTG_SELECTED(base) (BME_UBFX32(&XCVR_PLL_LP_SDM_CTRL1_REG(ba…
34254 #define XCVR_BRD_PLL_LP_SDM_CTRL1_LPM_INTG(base) (BME_UBFX32(&XCVR_PLL_LP_SDM_CTRL1_REG(base), XCVR…
34273 #define XCVR_BRD_PLL_LP_SDM_CTRL1_SDM_MAP_DIS(base) (BME_UBFX32(&XCVR_PLL_LP_SDM_CTRL1_REG(base), X…
34469 #define XCVR_BRD_PLL_DELAY_MATCH_LP_SDM_DELAY(base) (BME_UBFX32(&XCVR_PLL_DELAY_MATCH_REG(base), XC…
34487 #define XCVR_BRD_PLL_DELAY_MATCH_HPM_SDM_DELAY(base) (BME_UBFX32(&XCVR_PLL_DELAY_MATCH_REG(base), X…
34504 #define XCVR_BRD_PLL_DELAY_MATCH_HPM_BANK_DELAY(base) (BME_UBFX32(&XCVR_PLL_DELAY_MATCH_REG(base), …
34546 #define XCVR_BRD_PLL_CTUNE_CTRL_CTUNE_TARGET_MANUAL(base) (BME_UBFX32(&XCVR_PLL_CTUNE_CTRL_REG(base…
34562 #define XCVR_BRD_PLL_CTUNE_CTRL_CTUNE_TD(base) (BME_UBFX32(&XCVR_PLL_CTUNE_CTRL_REG(base), XCVR_PLL…
34579 #define XCVR_BRD_PLL_CTUNE_CTRL_CTUNE_ADJUST(base) (BME_UBFX32(&XCVR_PLL_CTUNE_CTRL_REG(base), XCVR…
34595 #define XCVR_BRD_PLL_CTUNE_CTRL_CTUNE_MANUAL(base) (BME_UBFX32(&XCVR_PLL_CTUNE_CTRL_REG(base), XCVR…
34611 #define XCVR_BRD_PLL_CTUNE_CTRL_CTUNE_DIS(base) (BME_UBFX32(&XCVR_PLL_CTUNE_CTRL_REG(base), XCVR_PL…
34646 #define XCVR_BRD_PLL_CTUNE_CNT6_CTUNE_COUNT_6(base) (BME_UBFX32(&XCVR_PLL_CTUNE_CNT6_REG(base), XCV…
34677 #define XCVR_BRD_PLL_CTUNE_CNT5_4_CTUNE_COUNT_4(base) (BME_UBFX32(&XCVR_PLL_CTUNE_CNT5_4_REG(base),…
34688 #define XCVR_BRD_PLL_CTUNE_CNT5_4_CTUNE_COUNT_5(base) (BME_UBFX32(&XCVR_PLL_CTUNE_CNT5_4_REG(base),…
34719 #define XCVR_BRD_PLL_CTUNE_CNT3_2_CTUNE_COUNT_2(base) (BME_UBFX32(&XCVR_PLL_CTUNE_CNT3_2_REG(base),…
34730 #define XCVR_BRD_PLL_CTUNE_CNT3_2_CTUNE_COUNT_3(base) (BME_UBFX32(&XCVR_PLL_CTUNE_CNT3_2_REG(base),…
34761 #define XCVR_BRD_PLL_CTUNE_CNT1_0_CTUNE_COUNT_0(base) (BME_UBFX32(&XCVR_PLL_CTUNE_CNT1_0_REG(base),…
34772 #define XCVR_BRD_PLL_CTUNE_CNT1_0_CTUNE_COUNT_1(base) (BME_UBFX32(&XCVR_PLL_CTUNE_CNT1_0_REG(base),…
34804 #define XCVR_BRD_PLL_CTUNE_RESULTS_CTUNE_SELECTED(base) (BME_UBFX32(&XCVR_PLL_CTUNE_RESULTS_REG(bas…
34816 #define XCVR_BRD_PLL_CTUNE_RESULTS_CTUNE_BEST_DIFF(base) (BME_UBFX32(&XCVR_PLL_CTUNE_RESULTS_REG(ba…
34828 #define XCVR_BRD_PLL_CTUNE_RESULTS_CTUNE_FREQ_TARGET(base) (BME_UBFX32(&XCVR_PLL_CTUNE_RESULTS_REG(…
34874 #define XCVR_BRD_CTRL_PROTOCOL(base) (BME_UBFX32(&XCVR_CTRL_REG(base), XCVR_CTRL_PROTOCOL_SHIFT, XC…
34893 #define XCVR_BRD_CTRL_TGT_PWR_SRC(base) (BME_UBFX32(&XCVR_CTRL_REG(base), XCVR_CTRL_TGT_PWR_SRC_SHI…
34914 #define XCVR_BRD_CTRL_REF_CLK_FREQ(base) (BME_UBFX32(&XCVR_CTRL_REG(base), XCVR_CTRL_REF_CLK_FREQ_S…
34949 #define XCVR_BRD_STATUS_TSM_COUNT(base) (BME_UBFX32(&XCVR_STATUS_REG(base), XCVR_STATUS_TSM_COUNT_S…
34964 #define XCVR_BRD_STATUS_PLL_SEQ_STATE(base) (BME_UBFX32(&XCVR_STATUS_REG(base), XCVR_STATUS_PLL_SEQ…
34975 #define XCVR_BRD_STATUS_RX_MODE(base) (BME_UBFX32(&XCVR_STATUS_REG(base), XCVR_STATUS_RX_MODE_SHIFT…
34986 #define XCVR_BRD_STATUS_TX_MODE(base) (BME_UBFX32(&XCVR_STATUS_REG(base), XCVR_STATUS_TX_MODE_SHIFT…
35002 #define XCVR_BRD_STATUS_BTLE_SYSCLK_REQ(base) (BME_UBFX32(&XCVR_STATUS_REG(base), XCVR_STATUS_BTLE_…
35016 #define XCVR_BRD_STATUS_RIF_LL_ACTIVE(base) (BME_UBFX32(&XCVR_STATUS_REG(base), XCVR_STATUS_RIF_LL_…
35033 #define XCVR_BRD_STATUS_XTAL_READY(base) (BME_UBFX32(&XCVR_STATUS_REG(base), XCVR_STATUS_XTAL_READY…
35045 #define XCVR_BRD_STATUS_SOC_USING_RF_OSC_CLK(base) (BME_UBFX32(&XCVR_STATUS_REG(base), XCVR_STATUS_…
35108 #define XCVR_BRD_OVERWRITE_VER_OVERWRITE_VER(base) (BME_UBFX32(&XCVR_OVERWRITE_VER_REG(base), XCVR_…
35158 #define XCVR_BRD_DMA_CTRL_DMA_I_EN(base) (BME_UBFX32(&XCVR_DMA_CTRL_REG(base), XCVR_DMA_CTRL_DMA_I_…
35178 #define XCVR_BRD_DMA_CTRL_DMA_Q_EN(base) (BME_UBFX32(&XCVR_DMA_CTRL_REG(base), XCVR_DMA_CTRL_DMA_Q_…
35225 #define XCVR_BRD_DMA_DATA_DMA_DATA_11_0(base) (BME_UBFX32(&XCVR_DMA_DATA_REG(base), XCVR_DMA_DATA_D…
35242 #define XCVR_BRD_DMA_DATA_DMA_DATA_27_16(base) (BME_UBFX32(&XCVR_DMA_DATA_REG(base), XCVR_DMA_DATA_…
35284 #define XCVR_BRD_DTEST_CTRL_DTEST_PAGE(base) (BME_UBFX32(&XCVR_DTEST_CTRL_REG(base), XCVR_DTEST_CTR…
35304 #define XCVR_BRD_DTEST_CTRL_DTEST_EN(base) (BME_UBFX32(&XCVR_DTEST_CTRL_REG(base), XCVR_DTEST_CTRL_…
35324 #define XCVR_BRD_DTEST_CTRL_GPIO0_OVLAY_PIN(base) (BME_UBFX32(&XCVR_DTEST_CTRL_REG(base), XCVR_DTES…
35344 #define XCVR_BRD_DTEST_CTRL_GPIO1_OVLAY_PIN(base) (BME_UBFX32(&XCVR_DTEST_CTRL_REG(base), XCVR_DTES…
35370 #define XCVR_BRD_DTEST_CTRL_TSM_GPIO_OVLAY_0(base) (BME_UBFX32(&XCVR_DTEST_CTRL_REG(base), XCVR_DTE…
35396 #define XCVR_BRD_DTEST_CTRL_TSM_GPIO_OVLAY_1(base) (BME_UBFX32(&XCVR_DTEST_CTRL_REG(base), XCVR_DTE…
35423 #define XCVR_BRD_DTEST_CTRL_DTEST_SHFT(base) (BME_UBFX32(&XCVR_DTEST_CTRL_REG(base), XCVR_DTEST_CTR…
35445 #define XCVR_BRD_DTEST_CTRL_RAW_MODE_I(base) (BME_UBFX32(&XCVR_DTEST_CTRL_REG(base), XCVR_DTEST_CTR…
35467 #define XCVR_BRD_DTEST_CTRL_RAW_MODE_Q(base) (BME_UBFX32(&XCVR_DTEST_CTRL_REG(base), XCVR_DTEST_CTR…
35512 #define XCVR_BRD_PB_CTRL_PB_PROTECT(base) (BME_UBFX32(&XCVR_PB_CTRL_REG(base), XCVR_PB_CTRL_PB_PROT…
35558 #define XCVR_BRD_TSM_CTRL_FORCE_TX_EN(base) (BME_UBFX32(&XCVR_TSM_CTRL_REG(base), XCVR_TSM_CTRL_FOR…
35578 #define XCVR_BRD_TSM_CTRL_FORCE_RX_EN(base) (BME_UBFX32(&XCVR_TSM_CTRL_REG(base), XCVR_TSM_CTRL_FOR…
35597 #define XCVR_BRD_TSM_CTRL_PA_RAMP_SEL(base) (BME_UBFX32(&XCVR_TSM_CTRL_REG(base), XCVR_TSM_CTRL_PA_…
35618 #define XCVR_BRD_TSM_CTRL_DATA_PADDING_EN(base) (BME_UBFX32(&XCVR_TSM_CTRL_REG(base), XCVR_TSM_CTRL…
35634 #define XCVR_BRD_TSM_CTRL_TX_ABORT_DIS(base) (BME_UBFX32(&XCVR_TSM_CTRL_REG(base), XCVR_TSM_CTRL_TX…
35650 #define XCVR_BRD_TSM_CTRL_RX_ABORT_DIS(base) (BME_UBFX32(&XCVR_TSM_CTRL_REG(base), XCVR_TSM_CTRL_RX…
35667 #define XCVR_BRD_TSM_CTRL_ABORT_ON_CTUNE(base) (BME_UBFX32(&XCVR_TSM_CTRL_REG(base), XCVR_TSM_CTRL_…
35684 #define XCVR_BRD_TSM_CTRL_ABORT_ON_CYCLE_SLIP(base) (BME_UBFX32(&XCVR_TSM_CTRL_REG(base), XCVR_TSM_…
35701 #define XCVR_BRD_TSM_CTRL_ABORT_ON_FREQ_TARG(base) (BME_UBFX32(&XCVR_TSM_CTRL_REG(base), XCVR_TSM_C…
35723 #define XCVR_BRD_TSM_CTRL_BKPT(base) (BME_UBFX32(&XCVR_TSM_CTRL_REG(base), XCVR_TSM_CTRL_BKPT_SHIFT…
35766 #define XCVR_BRD_END_OF_SEQ_END_OF_TX_WU(base) (BME_UBFX32(&XCVR_END_OF_SEQ_REG(base), XCVR_END_OF_…
35785 #define XCVR_BRD_END_OF_SEQ_END_OF_TX_WD(base) (BME_UBFX32(&XCVR_END_OF_SEQ_REG(base), XCVR_END_OF_…
35803 #define XCVR_BRD_END_OF_SEQ_END_OF_RX_WU(base) (BME_UBFX32(&XCVR_END_OF_SEQ_REG(base), XCVR_END_OF_…
35822 #define XCVR_BRD_END_OF_SEQ_END_OF_RX_WD(base) (BME_UBFX32(&XCVR_END_OF_SEQ_REG(base), XCVR_END_OF_…
35864 #define XCVR_BRD_TSM_OVRD0_PLL_REG_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM…
35880 #define XCVR_BRD_TSM_OVRD0_PLL_REG_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM_OV…
35898 #define XCVR_BRD_TSM_OVRD0_PLL_VCO_REG_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR…
35915 #define XCVR_BRD_TSM_OVRD0_PLL_VCO_REG_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TS…
35933 #define XCVR_BRD_TSM_OVRD0_QGEN_REG_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TS…
35949 #define XCVR_BRD_TSM_OVRD0_QGEN_REG_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM_O…
35967 #define XCVR_BRD_TSM_OVRD0_TCA_TX_REG_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_…
35983 #define XCVR_BRD_TSM_OVRD0_TCA_TX_REG_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM…
36001 #define XCVR_BRD_TSM_OVRD0_ADC_ANA_REG_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR…
36018 #define XCVR_BRD_TSM_OVRD0_ADC_ANA_REG_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TS…
36036 #define XCVR_BRD_TSM_OVRD0_ADC_DIG_REG_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR…
36053 #define XCVR_BRD_TSM_OVRD0_ADC_DIG_REG_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TS…
36071 #define XCVR_BRD_TSM_OVRD0_XTAL_PLL_REF_CLK_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base),…
36088 #define XCVR_BRD_TSM_OVRD0_XTAL_PLL_REF_CLK_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XC…
36106 #define XCVR_BRD_TSM_OVRD0_XTAL_ADC_REF_CLK_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base),…
36123 #define XCVR_BRD_TSM_OVRD0_XTAL_ADC_REF_CLK_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XC…
36141 #define XCVR_BRD_TSM_OVRD0_PLL_VCO_AUTOTUNE_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base),…
36158 #define XCVR_BRD_TSM_OVRD0_PLL_VCO_AUTOTUNE_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XC…
36176 #define XCVR_BRD_TSM_OVRD0_PLL_CYCLE_SLIP_LD_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base)…
36193 #define XCVR_BRD_TSM_OVRD0_PLL_CYCLE_SLIP_LD_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), X…
36210 #define XCVR_BRD_TSM_OVRD0_PLL_VCO_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM…
36226 #define XCVR_BRD_TSM_OVRD0_PLL_VCO_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM_OV…
36244 #define XCVR_BRD_TSM_OVRD0_PLL_VCO_BUF_RX_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), X…
36261 #define XCVR_BRD_TSM_OVRD0_PLL_VCO_BUF_RX_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR…
36279 #define XCVR_BRD_TSM_OVRD0_PLL_VCO_BUF_TX_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), X…
36296 #define XCVR_BRD_TSM_OVRD0_PLL_VCO_BUF_TX_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR…
36314 #define XCVR_BRD_TSM_OVRD0_PLL_PA_BUF_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_…
36330 #define XCVR_BRD_TSM_OVRD0_PLL_PA_BUF_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM…
36347 #define XCVR_BRD_TSM_OVRD0_PLL_LDV_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM…
36363 #define XCVR_BRD_TSM_OVRD0_PLL_LDV_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM_OV…
36381 #define XCVR_BRD_TSM_OVRD0_PLL_RX_LDV_RIPPLE_MUX_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(b…
36398 #define XCVR_BRD_TSM_OVRD0_PLL_RX_LDV_RIPPLE_MUX_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base…
36441 #define XCVR_BRD_TSM_OVRD1_PLL_TX_LDV_RIPPLE_MUX_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(b…
36458 #define XCVR_BRD_TSM_OVRD1_PLL_TX_LDV_RIPPLE_MUX_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base…
36476 #define XCVR_BRD_TSM_OVRD1_PLL_FILTER_CHARGE_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base)…
36493 #define XCVR_BRD_TSM_OVRD1_PLL_FILTER_CHARGE_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), X…
36511 #define XCVR_BRD_TSM_OVRD1_PLL_PHDET_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_T…
36527 #define XCVR_BRD_TSM_OVRD1_PLL_PHDET_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_…
36544 #define XCVR_BRD_TSM_OVRD1_QGEN25_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_…
36560 #define XCVR_BRD_TSM_OVRD1_QGEN25_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVR…
36577 #define XCVR_BRD_TSM_OVRD1_TX_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVRD…
36593 #define XCVR_BRD_TSM_OVRD1_TX_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVRD1_T…
36610 #define XCVR_BRD_TSM_OVRD1_ADC_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVR…
36626 #define XCVR_BRD_TSM_OVRD1_ADC_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVRD1_…
36644 #define XCVR_BRD_TSM_OVRD1_ADC_BIAS_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TS…
36660 #define XCVR_BRD_TSM_OVRD1_ADC_BIAS_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_O…
36677 #define XCVR_BRD_TSM_OVRD1_ADC_CLK_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM…
36693 #define XCVR_BRD_TSM_OVRD1_ADC_CLK_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OV…
36711 #define XCVR_BRD_TSM_OVRD1_ADC_I_ADC_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_T…
36727 #define XCVR_BRD_TSM_OVRD1_ADC_I_ADC_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_…
36745 #define XCVR_BRD_TSM_OVRD1_ADC_Q_ADC_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_T…
36761 #define XCVR_BRD_TSM_OVRD1_ADC_Q_ADC_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_…
36779 #define XCVR_BRD_TSM_OVRD1_ADC_DAC1_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TS…
36795 #define XCVR_BRD_TSM_OVRD1_ADC_DAC1_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_O…
36813 #define XCVR_BRD_TSM_OVRD1_ADC_DAC2_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TS…
36829 #define XCVR_BRD_TSM_OVRD1_ADC_DAC2_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_O…
36846 #define XCVR_BRD_TSM_OVRD1_ADC_RST_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM…
36862 #define XCVR_BRD_TSM_OVRD1_ADC_RST_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OV…
36879 #define XCVR_BRD_TSM_OVRD1_BBF_I_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_O…
36895 #define XCVR_BRD_TSM_OVRD1_BBF_I_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVRD…
36912 #define XCVR_BRD_TSM_OVRD1_BBF_Q_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_O…
36928 #define XCVR_BRD_TSM_OVRD1_BBF_Q_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVRD…
36946 #define XCVR_BRD_TSM_OVRD1_BBF_PDET_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TS…
36962 #define XCVR_BRD_TSM_OVRD1_BBF_PDET_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_O…
37005 #define XCVR_BRD_TSM_OVRD2_BBF_DCOC_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TS…
37021 #define XCVR_BRD_TSM_OVRD2_BBF_DCOC_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_O…
37038 #define XCVR_BRD_TSM_OVRD2_TCA_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVR…
37054 #define XCVR_BRD_TSM_OVRD2_TCA_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVRD2_…
37071 #define XCVR_BRD_TSM_OVRD2_TZA_I_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_O…
37087 #define XCVR_BRD_TSM_OVRD2_TZA_I_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVRD…
37104 #define XCVR_BRD_TSM_OVRD2_TZA_Q_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_O…
37120 #define XCVR_BRD_TSM_OVRD2_TZA_Q_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVRD…
37138 #define XCVR_BRD_TSM_OVRD2_TZA_PDET_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TS…
37154 #define XCVR_BRD_TSM_OVRD2_TZA_PDET_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_O…
37172 #define XCVR_BRD_TSM_OVRD2_TZA_DCOC_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TS…
37188 #define XCVR_BRD_TSM_OVRD2_TZA_DCOC_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_O…
37205 #define XCVR_BRD_TSM_OVRD2_PLL_DIG_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM…
37221 #define XCVR_BRD_TSM_OVRD2_PLL_DIG_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OV…
37238 #define XCVR_BRD_TSM_OVRD2_TX_DIG_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_…
37254 #define XCVR_BRD_TSM_OVRD2_TX_DIG_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVR…
37271 #define XCVR_BRD_TSM_OVRD2_RX_DIG_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_…
37287 #define XCVR_BRD_TSM_OVRD2_RX_DIG_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVR…
37304 #define XCVR_BRD_TSM_OVRD2_RX_INIT_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OV…
37320 #define XCVR_BRD_TSM_OVRD2_RX_INIT_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVRD2…
37338 #define XCVR_BRD_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR…
37355 #define XCVR_BRD_TSM_OVRD2_SIGMA_DELTA_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TS…
37373 #define XCVR_BRD_TSM_OVRD2_ZBDEM_RX_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TS…
37389 #define XCVR_BRD_TSM_OVRD2_ZBDEM_RX_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_O…
37406 #define XCVR_BRD_TSM_OVRD2_DCOC_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OV…
37422 #define XCVR_BRD_TSM_OVRD2_DCOC_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVRD2…
37439 #define XCVR_BRD_TSM_OVRD2_DCOC_INIT_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_…
37455 #define XCVR_BRD_TSM_OVRD2_DCOC_INIT_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVR…
37473 #define XCVR_BRD_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCV…
37490 #define XCVR_BRD_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_T…
37508 #define XCVR_BRD_TSM_OVRD2_SAR_ADC_TRIG_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCV…
37525 #define XCVR_BRD_TSM_OVRD2_SAR_ADC_TRIG_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_T…
37568 #define XCVR_BRD_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD3_REG(base), XCVR_…
37584 #define XCVR_BRD_TSM_OVRD3_TSM_SPARE0_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD3_REG(base), XCVR_TSM…
37602 #define XCVR_BRD_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD3_REG(base), XCVR_…
37618 #define XCVR_BRD_TSM_OVRD3_TSM_SPARE1_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD3_REG(base), XCVR_TSM…
37636 #define XCVR_BRD_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD3_REG(base), XCVR_…
37652 #define XCVR_BRD_TSM_OVRD3_TSM_SPARE2_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD3_REG(base), XCVR_TSM…
37670 #define XCVR_BRD_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD3_REG(base), XCVR_…
37686 #define XCVR_BRD_TSM_OVRD3_TSM_SPARE3_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD3_REG(base), XCVR_TSM…
37703 #define XCVR_BRD_TSM_OVRD3_TX_MODE_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD3_REG(base), XCVR_TSM_OV…
37719 #define XCVR_BRD_TSM_OVRD3_TX_MODE_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD3_REG(base), XCVR_TSM_OVRD3…
37736 #define XCVR_BRD_TSM_OVRD3_RX_MODE_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD3_REG(base), XCVR_TSM_OV…
37752 #define XCVR_BRD_TSM_OVRD3_RX_MODE_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD3_REG(base), XCVR_TSM_OVRD3…
37795 #define XCVR_BRD_PA_POWER_PA_POWER(base) (BME_UBFX32(&XCVR_PA_POWER_REG(base), XCVR_PA_POWER_PA_POW…
37841 #define XCVR_BRD_PA_BIAS_TBL0_PA_BIAS0(base) (BME_UBFX32(&XCVR_PA_BIAS_TBL0_REG(base), XCVR_PA_BIAS…
37860 #define XCVR_BRD_PA_BIAS_TBL0_PA_BIAS1(base) (BME_UBFX32(&XCVR_PA_BIAS_TBL0_REG(base), XCVR_PA_BIAS…
37879 #define XCVR_BRD_PA_BIAS_TBL0_PA_BIAS2(base) (BME_UBFX32(&XCVR_PA_BIAS_TBL0_REG(base), XCVR_PA_BIAS…
37898 #define XCVR_BRD_PA_BIAS_TBL0_PA_BIAS3(base) (BME_UBFX32(&XCVR_PA_BIAS_TBL0_REG(base), XCVR_PA_BIAS…
37942 #define XCVR_BRD_PA_BIAS_TBL1_PA_BIAS4(base) (BME_UBFX32(&XCVR_PA_BIAS_TBL1_REG(base), XCVR_PA_BIAS…
37961 #define XCVR_BRD_PA_BIAS_TBL1_PA_BIAS5(base) (BME_UBFX32(&XCVR_PA_BIAS_TBL1_REG(base), XCVR_PA_BIAS…
37980 #define XCVR_BRD_PA_BIAS_TBL1_PA_BIAS6(base) (BME_UBFX32(&XCVR_PA_BIAS_TBL1_REG(base), XCVR_PA_BIAS…
37999 #define XCVR_BRD_PA_BIAS_TBL1_PA_BIAS7(base) (BME_UBFX32(&XCVR_PA_BIAS_TBL1_REG(base), XCVR_PA_BIAS…
38050 #define XCVR_BRD_RECYCLE_COUNT_RECYCLE_COUNT0(base) (BME_UBFX32(&XCVR_RECYCLE_COUNT_REG(base), XCVR…
38076 #define XCVR_BRD_RECYCLE_COUNT_RECYCLE_COUNT1(base) (BME_UBFX32(&XCVR_RECYCLE_COUNT_REG(base), XCVR…
38121 #define XCVR_BRD_TSM_TIMING00_PLL_REG_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING00_REG(base), XCVR…
38137 #define XCVR_BRD_TSM_TIMING00_PLL_REG_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING00_REG(base), XCVR…
38153 #define XCVR_BRD_TSM_TIMING00_PLL_REG_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING00_REG(base), XCVR…
38169 #define XCVR_BRD_TSM_TIMING00_PLL_REG_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING00_REG(base), XCVR…
38214 #define XCVR_BRD_TSM_TIMING01_PLL_VCO_REG_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING01_REG(base), …
38230 #define XCVR_BRD_TSM_TIMING01_PLL_VCO_REG_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING01_REG(base), …
38246 #define XCVR_BRD_TSM_TIMING01_PLL_VCO_REG_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING01_REG(base), …
38262 #define XCVR_BRD_TSM_TIMING01_PLL_VCO_REG_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING01_REG(base), …
38307 #define XCVR_BRD_TSM_TIMING02_QGEN_REG_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING02_REG(base), XCV…
38323 #define XCVR_BRD_TSM_TIMING02_QGEN_REG_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING02_REG(base), XCV…
38339 #define XCVR_BRD_TSM_TIMING02_QGEN_REG_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING02_REG(base), XCV…
38355 #define XCVR_BRD_TSM_TIMING02_QGEN_REG_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING02_REG(base), XCV…
38400 #define XCVR_BRD_TSM_TIMING03_TCA_TX_REG_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING03_REG(base), X…
38416 #define XCVR_BRD_TSM_TIMING03_TCA_TX_REG_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING03_REG(base), X…
38432 #define XCVR_BRD_TSM_TIMING03_TCA_TX_REG_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING03_REG(base), X…
38448 #define XCVR_BRD_TSM_TIMING03_TCA_TX_REG_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING03_REG(base), X…
38493 #define XCVR_BRD_TSM_TIMING04_ADC_REG_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING04_REG(base), XCVR…
38509 #define XCVR_BRD_TSM_TIMING04_ADC_REG_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING04_REG(base), XCVR…
38554 #define XCVR_BRD_TSM_TIMING05_PLL_REF_CLK_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING05_REG(base), …
38570 #define XCVR_BRD_TSM_TIMING05_PLL_REF_CLK_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING05_REG(base), …
38586 #define XCVR_BRD_TSM_TIMING05_PLL_REF_CLK_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING05_REG(base), …
38602 #define XCVR_BRD_TSM_TIMING05_PLL_REF_CLK_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING05_REG(base), …
38647 #define XCVR_BRD_TSM_TIMING06_ADC_CLK_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING06_REG(base), XCVR…
38663 #define XCVR_BRD_TSM_TIMING06_ADC_CLK_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING06_REG(base), XCVR…
38709 #define XCVR_BRD_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING07_REG(ba…
38726 #define XCVR_BRD_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING07_REG(ba…
38743 #define XCVR_BRD_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING07_REG(ba…
38760 #define XCVR_BRD_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING07_REG(ba…
38806 #define XCVR_BRD_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING08_REG(b…
38823 #define XCVR_BRD_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING08_REG(b…
38840 #define XCVR_BRD_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING08_REG(b…
38857 #define XCVR_BRD_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING08_REG(b…
38902 #define XCVR_BRD_TSM_TIMING09_PLL_VCO_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING09_REG(base), XCVR…
38918 #define XCVR_BRD_TSM_TIMING09_PLL_VCO_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING09_REG(base), XCVR…
38934 #define XCVR_BRD_TSM_TIMING09_PLL_VCO_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING09_REG(base), XCVR…
38950 #define XCVR_BRD_TSM_TIMING09_PLL_VCO_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING09_REG(base), XCVR…
38995 #define XCVR_BRD_TSM_TIMING10_PLL_VCO_BUF_RX_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING10_REG(base…
39011 #define XCVR_BRD_TSM_TIMING10_PLL_VCO_BUF_RX_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING10_REG(base…
39056 #define XCVR_BRD_TSM_TIMING11_PLL_VCO_BUF_TX_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING11_REG(base…
39072 #define XCVR_BRD_TSM_TIMING11_PLL_VCO_BUF_TX_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING11_REG(base…
39117 #define XCVR_BRD_TSM_TIMING12_PLL_PA_BUF_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING12_REG(base), X…
39133 #define XCVR_BRD_TSM_TIMING12_PLL_PA_BUF_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING12_REG(base), X…
39178 #define XCVR_BRD_TSM_TIMING13_PLL_LDV_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING13_REG(base), XCVR…
39194 #define XCVR_BRD_TSM_TIMING13_PLL_LDV_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING13_REG(base), XCVR…
39210 #define XCVR_BRD_TSM_TIMING13_PLL_LDV_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING13_REG(base), XCVR…
39226 #define XCVR_BRD_TSM_TIMING13_PLL_LDV_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING13_REG(base), XCVR…
39272 #define XCVR_BRD_TSM_TIMING14_PLL_RX_LDV_RIPPLE_MUX_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING14_R…
39289 #define XCVR_BRD_TSM_TIMING14_PLL_RX_LDV_RIPPLE_MUX_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING14_R…
39335 #define XCVR_BRD_TSM_TIMING15_PLL_TX_LDV_RIPPLE_MUX_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING15_R…
39352 #define XCVR_BRD_TSM_TIMING15_PLL_TX_LDV_RIPPLE_MUX_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING15_R…
39398 #define XCVR_BRD_TSM_TIMING16_PLL_FILTER_CHARGE_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING16_REG(b…
39415 #define XCVR_BRD_TSM_TIMING16_PLL_FILTER_CHARGE_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING16_REG(b…
39432 #define XCVR_BRD_TSM_TIMING16_PLL_FILTER_CHARGE_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING16_REG(b…
39449 #define XCVR_BRD_TSM_TIMING16_PLL_FILTER_CHARGE_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING16_REG(b…
39494 #define XCVR_BRD_TSM_TIMING17_PLL_PHDET_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING17_REG(base), XC…
39510 #define XCVR_BRD_TSM_TIMING17_PLL_PHDET_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING17_REG(base), XC…
39526 #define XCVR_BRD_TSM_TIMING17_PLL_PHDET_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING17_REG(base), XC…
39542 #define XCVR_BRD_TSM_TIMING17_PLL_PHDET_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING17_REG(base), XC…
39587 #define XCVR_BRD_TSM_TIMING18_QGEN25_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING18_REG(base), XCVR_…
39603 #define XCVR_BRD_TSM_TIMING18_QGEN25_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING18_REG(base), XCVR_…
39648 #define XCVR_BRD_TSM_TIMING19_TX_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING19_REG(base), XCVR_TSM_…
39664 #define XCVR_BRD_TSM_TIMING19_TX_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING19_REG(base), XCVR_TSM_…
39709 #define XCVR_BRD_TSM_TIMING20_ADC_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING20_REG(base), XCVR_TSM…
39725 #define XCVR_BRD_TSM_TIMING20_ADC_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING20_REG(base), XCVR_TSM…
39770 #define XCVR_BRD_TSM_TIMING21_ADC_I_Q_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING21_REG(base), XCVR…
39786 #define XCVR_BRD_TSM_TIMING21_ADC_I_Q_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING21_REG(base), XCVR…
39831 #define XCVR_BRD_TSM_TIMING22_ADC_DAC_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING22_REG(base), XCVR…
39847 #define XCVR_BRD_TSM_TIMING22_ADC_DAC_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING22_REG(base), XCVR…
39892 #define XCVR_BRD_TSM_TIMING23_ADC_RST_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING23_REG(base), XCVR…
39908 #define XCVR_BRD_TSM_TIMING23_ADC_RST_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING23_REG(base), XCVR…
39953 #define XCVR_BRD_TSM_TIMING24_BBF_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING24_REG(base), XCVR_TSM…
39969 #define XCVR_BRD_TSM_TIMING24_BBF_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING24_REG(base), XCVR_TSM…
40014 #define XCVR_BRD_TSM_TIMING25_TCA_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING25_REG(base), XCVR_TSM…
40030 #define XCVR_BRD_TSM_TIMING25_TCA_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING25_REG(base), XCVR_TSM…
40075 #define XCVR_BRD_TSM_TIMING26_PLL_DIG_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING26_REG(base), XCVR…
40091 #define XCVR_BRD_TSM_TIMING26_PLL_DIG_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING26_REG(base), XCVR…
40107 #define XCVR_BRD_TSM_TIMING26_PLL_DIG_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING26_REG(base), XCVR…
40123 #define XCVR_BRD_TSM_TIMING26_PLL_DIG_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING26_REG(base), XCVR…
40168 #define XCVR_BRD_TSM_TIMING27_TX_DIG_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING27_REG(base), XCVR_…
40184 #define XCVR_BRD_TSM_TIMING27_TX_DIG_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING27_REG(base), XCVR_…
40229 #define XCVR_BRD_TSM_TIMING28_RX_DIG_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING28_REG(base), XCVR_…
40245 #define XCVR_BRD_TSM_TIMING28_RX_DIG_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING28_REG(base), XCVR_…
40290 #define XCVR_BRD_TSM_TIMING29_RX_INIT_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING29_REG(base), XCVR_TS…
40306 #define XCVR_BRD_TSM_TIMING29_RX_INIT_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING29_REG(base), XCVR_TS…
40351 #define XCVR_BRD_TSM_TIMING30_SIGMA_DELTA_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING30_REG(base), …
40367 #define XCVR_BRD_TSM_TIMING30_SIGMA_DELTA_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING30_REG(base), …
40383 #define XCVR_BRD_TSM_TIMING30_SIGMA_DELTA_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING30_REG(base), …
40399 #define XCVR_BRD_TSM_TIMING30_SIGMA_DELTA_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING30_REG(base), …
40444 #define XCVR_BRD_TSM_TIMING31_ZBDEM_RX_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING31_REG(base), XCV…
40460 #define XCVR_BRD_TSM_TIMING31_ZBDEM_RX_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING31_REG(base), XCV…
40505 #define XCVR_BRD_TSM_TIMING32_DCOC_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING32_REG(base), XCVR_TS…
40521 #define XCVR_BRD_TSM_TIMING32_DCOC_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING32_REG(base), XCVR_TS…
40566 #define XCVR_BRD_TSM_TIMING33_DCOC_INIT_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING33_REG(base), XCVR_…
40582 #define XCVR_BRD_TSM_TIMING33_DCOC_INIT_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING33_REG(base), XCVR_…
40627 #define XCVR_BRD_TSM_TIMING34_FREQ_TARG_LD_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING34_REG(base),…
40643 #define XCVR_BRD_TSM_TIMING34_FREQ_TARG_LD_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING34_REG(base),…
40659 #define XCVR_BRD_TSM_TIMING34_FREQ_TARG_LD_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING34_REG(base),…
40675 #define XCVR_BRD_TSM_TIMING34_FREQ_TARG_LD_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING34_REG(base),…
40720 #define XCVR_BRD_TSM_TIMING35_SAR_ADC_TRIG_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING35_REG(base),…
40736 #define XCVR_BRD_TSM_TIMING35_SAR_ADC_TRIG_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING35_REG(base),…
40752 #define XCVR_BRD_TSM_TIMING35_SAR_ADC_TRIG_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING35_REG(base),…
40768 #define XCVR_BRD_TSM_TIMING35_SAR_ADC_TRIG_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING35_REG(base),…
40813 #define XCVR_BRD_TSM_TIMING36_TSM_SPARE0_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING36_REG(base), X…
40829 #define XCVR_BRD_TSM_TIMING36_TSM_SPARE0_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING36_REG(base), X…
40845 #define XCVR_BRD_TSM_TIMING36_TSM_SPARE0_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING36_REG(base), X…
40861 #define XCVR_BRD_TSM_TIMING36_TSM_SPARE0_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING36_REG(base), X…
40906 #define XCVR_BRD_TSM_TIMING37_TSM_SPARE1_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING37_REG(base), X…
40922 #define XCVR_BRD_TSM_TIMING37_TSM_SPARE1_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING37_REG(base), X…
40938 #define XCVR_BRD_TSM_TIMING37_TSM_SPARE1_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING37_REG(base), X…
40954 #define XCVR_BRD_TSM_TIMING37_TSM_SPARE1_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING37_REG(base), X…
40999 #define XCVR_BRD_TSM_TIMING38_TSM_SPARE2_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING38_REG(base), X…
41015 #define XCVR_BRD_TSM_TIMING38_TSM_SPARE2_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING38_REG(base), X…
41031 #define XCVR_BRD_TSM_TIMING38_TSM_SPARE2_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING38_REG(base), X…
41047 #define XCVR_BRD_TSM_TIMING38_TSM_SPARE2_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING38_REG(base), X…
41092 #define XCVR_BRD_TSM_TIMING39_TSM_SPARE3_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING39_REG(base), X…
41108 #define XCVR_BRD_TSM_TIMING39_TSM_SPARE3_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING39_REG(base), X…
41124 #define XCVR_BRD_TSM_TIMING39_TSM_SPARE3_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING39_REG(base), X…
41140 #define XCVR_BRD_TSM_TIMING39_TSM_SPARE3_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING39_REG(base), X…
41185 #define XCVR_BRD_TSM_TIMING40_GPIO0_TRIG_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING40_REG(base), X…
41201 #define XCVR_BRD_TSM_TIMING40_GPIO0_TRIG_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING40_REG(base), X…
41217 #define XCVR_BRD_TSM_TIMING40_GPIO0_TRIG_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING40_REG(base), X…
41233 #define XCVR_BRD_TSM_TIMING40_GPIO0_TRIG_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING40_REG(base), X…
41278 #define XCVR_BRD_TSM_TIMING41_GPIO1_TRIG_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING41_REG(base), X…
41294 #define XCVR_BRD_TSM_TIMING41_GPIO1_TRIG_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING41_REG(base), X…
41310 #define XCVR_BRD_TSM_TIMING41_GPIO1_TRIG_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING41_REG(base), X…
41326 #define XCVR_BRD_TSM_TIMING41_GPIO1_TRIG_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING41_REG(base), X…
41371 #define XCVR_BRD_TSM_TIMING42_GPIO2_TRIG_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING42_REG(base), X…
41387 #define XCVR_BRD_TSM_TIMING42_GPIO2_TRIG_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING42_REG(base), X…
41403 #define XCVR_BRD_TSM_TIMING42_GPIO2_TRIG_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING42_REG(base), X…
41419 #define XCVR_BRD_TSM_TIMING42_GPIO2_TRIG_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING42_REG(base), X…
41464 #define XCVR_BRD_TSM_TIMING43_GPIO3_TRIG_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING43_REG(base), X…
41480 #define XCVR_BRD_TSM_TIMING43_GPIO3_TRIG_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING43_REG(base), X…
41496 #define XCVR_BRD_TSM_TIMING43_GPIO3_TRIG_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING43_REG(base), X…
41512 #define XCVR_BRD_TSM_TIMING43_GPIO3_TRIG_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING43_REG(base), X…
41553 #define XCVR_BRD_CORR_CTRL_CORR_VT(base) (BME_UBFX32(&XCVR_CORR_CTRL_REG(base), XCVR_CORR_CTRL_CORR…
41569 #define XCVR_BRD_CORR_CTRL_CORR_NVAL(base) (BME_UBFX32(&XCVR_CORR_CTRL_REG(base), XCVR_CORR_CTRL_CO…
41585 #define XCVR_BRD_CORR_CTRL_MAX_CORR_EN(base) (BME_UBFX32(&XCVR_CORR_CTRL_REG(base), XCVR_CORR_CTRL_…
41601 #define XCVR_BRD_CORR_CTRL_RX_MAX_CORR(base) (BME_UBFX32(&XCVR_CORR_CTRL_REG(base), XCVR_CORR_CTRL_…
41613 #define XCVR_BRD_CORR_CTRL_RX_MAX_PREAMBLE(base) (BME_UBFX32(&XCVR_CORR_CTRL_REG(base), XCVR_CORR_C…
41649 #define XCVR_BRD_PN_TYPE_PN_TYPE(base) (BME_UBFX32(&XCVR_PN_TYPE_REG(base), XCVR_PN_TYPE_PN_TYPE_SH…
41664 #define XCVR_BRD_PN_TYPE_TX_INV(base) (BME_UBFX32(&XCVR_PN_TYPE_REG(base), XCVR_PN_TYPE_TX_INV_SHIF…
41706 #define XCVR_BRD_PN_CODE_PN_LSB(base) (BME_UBFX32(&XCVR_PN_CODE_REG(base), XCVR_PN_CODE_PN_LSB_SHIF…
41721 #define XCVR_BRD_PN_CODE_PN_MSB(base) (BME_UBFX32(&XCVR_PN_CODE_REG(base), XCVR_PN_CODE_PN_MSB_SHIF…
41763 #define XCVR_BRD_SYNC_CTRL_SYNC_PER(base) (BME_UBFX32(&XCVR_SYNC_CTRL_REG(base), XCVR_SYNC_CTRL_SYN…
41781 #define XCVR_BRD_SYNC_CTRL_TRACK_ENABLE(base) (BME_UBFX32(&XCVR_SYNC_CTRL_REG(base), XCVR_SYNC_CTRL…
41823 #define XCVR_BRD_SNF_THR_SNF_THR(base) (BME_UBFX32(&XCVR_SNF_THR_REG(base), XCVR_SNF_THR_SNF_THR_SH…
41863 #define XCVR_BRD_FAD_THR_FAD_THR(base) (BME_UBFX32(&XCVR_FAD_THR_REG(base), XCVR_FAD_THR_FAD_THR_SH…
41903 #define XCVR_BRD_ZBDEM_AFC_AFC_EN(base) (BME_UBFX32(&XCVR_ZBDEM_AFC_REG(base), XCVR_ZBDEM_AFC_AFC_E…
41920 #define XCVR_BRD_ZBDEM_AFC_DCD_EN(base) (BME_UBFX32(&XCVR_ZBDEM_AFC_REG(base), XCVR_ZBDEM_AFC_DCD_E…
41935 #define XCVR_BRD_ZBDEM_AFC_AFC_OUT(base) (BME_UBFX32(&XCVR_ZBDEM_AFC_REG(base), XCVR_ZBDEM_AFC_AFC_…
41977 #define XCVR_BRD_LPPS_CTRL_LPPS_ENABLE(base) (BME_UBFX32(&XCVR_LPPS_CTRL_REG(base), XCVR_LPPS_CTRL_…
41994 #define XCVR_BRD_LPPS_CTRL_LPPS_QGEN25_ALLOW(base) (BME_UBFX32(&XCVR_LPPS_CTRL_REG(base), XCVR_LPPS…
42013 #define XCVR_BRD_LPPS_CTRL_LPPS_ADC_ALLOW(base) (BME_UBFX32(&XCVR_LPPS_CTRL_REG(base), XCVR_LPPS_CT…
42032 #define XCVR_BRD_LPPS_CTRL_LPPS_ADC_CLK_ALLOW(base) (BME_UBFX32(&XCVR_LPPS_CTRL_REG(base), XCVR_LPP…
42051 #define XCVR_BRD_LPPS_CTRL_LPPS_ADC_I_Q_ALLOW(base) (BME_UBFX32(&XCVR_LPPS_CTRL_REG(base), XCVR_LPP…
42070 #define XCVR_BRD_LPPS_CTRL_LPPS_ADC_DAC_ALLOW(base) (BME_UBFX32(&XCVR_LPPS_CTRL_REG(base), XCVR_LPP…
42089 #define XCVR_BRD_LPPS_CTRL_LPPS_BBF_ALLOW(base) (BME_UBFX32(&XCVR_LPPS_CTRL_REG(base), XCVR_LPPS_CT…
42108 #define XCVR_BRD_LPPS_CTRL_LPPS_TCA_ALLOW(base) (BME_UBFX32(&XCVR_LPPS_CTRL_REG(base), XCVR_LPPS_CT…
42150 #define XCVR_BRD_ADC_CTRL_ADC_32MHZ_SEL(base) (BME_UBFX32(&XCVR_ADC_CTRL_REG(base), XCVR_ADC_CTRL_A…
42167 #define XCVR_BRD_ADC_CTRL_ADC_2X_CLK_SEL(base) (BME_UBFX32(&XCVR_ADC_CTRL_REG(base), XCVR_ADC_CTRL_…
42183 #define XCVR_BRD_ADC_CTRL_ADC_DITHER_ON(base) (BME_UBFX32(&XCVR_ADC_CTRL_REG(base), XCVR_ADC_CTRL_A…
42199 #define XCVR_BRD_ADC_CTRL_ADC_TEST_ON(base) (BME_UBFX32(&XCVR_ADC_CTRL_REG(base), XCVR_ADC_CTRL_ADC…
42216 #define XCVR_BRD_ADC_CTRL_ADC_COMP_ON(base) (BME_UBFX32(&XCVR_ADC_CTRL_REG(base), XCVR_ADC_CTRL_ADC…
42257 #define XCVR_BRD_ADC_TUNE_ADC_R1_TUNE(base) (BME_UBFX32(&XCVR_ADC_TUNE_REG(base), XCVR_ADC_TUNE_ADC…
42273 #define XCVR_BRD_ADC_TUNE_ADC_R2_TUNE(base) (BME_UBFX32(&XCVR_ADC_TUNE_REG(base), XCVR_ADC_TUNE_ADC…
42289 #define XCVR_BRD_ADC_TUNE_ADC_C1_TUNE(base) (BME_UBFX32(&XCVR_ADC_TUNE_REG(base), XCVR_ADC_TUNE_ADC…
42305 #define XCVR_BRD_ADC_TUNE_ADC_C2_TUNE(base) (BME_UBFX32(&XCVR_ADC_TUNE_REG(base), XCVR_ADC_TUNE_ADC…
42346 #define XCVR_BRD_ADC_ADJ_ADC_IB_OPAMP1_ADJ(base) (BME_UBFX32(&XCVR_ADC_ADJ_REG(base), XCVR_ADC_ADJ_…
42362 #define XCVR_BRD_ADC_ADJ_ADC_IB_OPAMP2_ADJ(base) (BME_UBFX32(&XCVR_ADC_ADJ_REG(base), XCVR_ADC_ADJ_…
42377 #define XCVR_BRD_ADC_ADJ_ADC_IB_DAC1_ADJ(base) (BME_UBFX32(&XCVR_ADC_ADJ_REG(base), XCVR_ADC_ADJ_AD…
42392 #define XCVR_BRD_ADC_ADJ_ADC_IB_DAC2_ADJ(base) (BME_UBFX32(&XCVR_ADC_ADJ_REG(base), XCVR_ADC_ADJ_AD…
42408 #define XCVR_BRD_ADC_ADJ_ADC_IB_FLSH_ADJ(base) (BME_UBFX32(&XCVR_ADC_ADJ_REG(base), XCVR_ADC_ADJ_AD…
42424 #define XCVR_BRD_ADC_ADJ_ADC_FLSH_RES_ADJ(base) (BME_UBFX32(&XCVR_ADC_ADJ_REG(base), XCVR_ADC_ADJ_A…
42470 #define XCVR_BRD_ADC_REGS_ADC_ANA_REG_SUPPLY(base) (BME_UBFX32(&XCVR_ADC_REGS_REG(base), XCVR_ADC_R…
42491 #define XCVR_BRD_ADC_REGS_ADC_REG_DIG_SUPPLY(base) (BME_UBFX32(&XCVR_ADC_REGS_REG(base), XCVR_ADC_R…
42508 #define XCVR_BRD_ADC_REGS_ADC_ANA_REG_BYPASS_ON(base) (BME_UBFX32(&XCVR_ADC_REGS_REG(base), XCVR_AD…
42525 #define XCVR_BRD_ADC_REGS_ADC_DIG_REG_BYPASS_ON(base) (BME_UBFX32(&XCVR_ADC_REGS_REG(base), XCVR_AD…
42543 #define XCVR_BRD_ADC_REGS_ADC_VCMREF_BYPASS_ON(base) (BME_UBFX32(&XCVR_ADC_REGS_REG(base), XCVR_ADC…
42562 #define XCVR_BRD_ADC_REGS_ADC_INTERNAL_IREF_BYPASS_ON(base) (BME_UBFX32(&XCVR_ADC_REGS_REG(base), X…
42604 #define XCVR_BRD_ADC_TRIMS_ADC_IREF_OPAMPS_RES_TRIM(base) (BME_UBFX32(&XCVR_ADC_TRIMS_REG(base), XC…
42620 #define XCVR_BRD_ADC_TRIMS_ADC_IREF_FLSH_RES_TRIM(base) (BME_UBFX32(&XCVR_ADC_TRIMS_REG(base), XCVR…
42637 #define XCVR_BRD_ADC_TRIMS_ADC_VCM_TRIM(base) (BME_UBFX32(&XCVR_ADC_TRIMS_REG(base), XCVR_ADC_TRIMS…
42683 #define XCVR_BRD_ADC_TEST_CTRL_ADC_ATST_SEL(base) (BME_UBFX32(&XCVR_ADC_TEST_CTRL_REG(base), XCVR_A…
42699 #define XCVR_BRD_ADC_TEST_CTRL_ADC_DIG_REG_ATST_SEL(base) (BME_UBFX32(&XCVR_ADC_TEST_CTRL_REG(base)…
42715 #define XCVR_BRD_ADC_TEST_CTRL_ADC_ANA_REG_ATST_SEL(base) (BME_UBFX32(&XCVR_ADC_TEST_CTRL_REG(base)…
42742 #define XCVR_BRD_ADC_TEST_CTRL_DCOC_ALPHA_RADIUS_GS_IDX(base) (BME_UBFX32(&XCVR_ADC_TEST_CTRL_REG(b…
42757 #define XCVR_BRD_ADC_TEST_CTRL_ADC_SPARE3(base) (BME_UBFX32(&XCVR_ADC_TEST_CTRL_REG(base), XCVR_ADC…
42810 #define XCVR_BRD_BBF_CTRL_BBF_CAP_TUNE(base) (BME_UBFX32(&XCVR_BBF_CTRL_REG(base), XCVR_BBF_CTRL_BB…
42828 #define XCVR_BRD_BBF_CTRL_BBF_RES_TUNE2(base) (BME_UBFX32(&XCVR_BBF_CTRL_REG(base), XCVR_BBF_CTRL_B…
42848 #define XCVR_BRD_BBF_CTRL_BBF_CUR_CNTL(base) (BME_UBFX32(&XCVR_BBF_CTRL_REG(base), XCVR_BBF_CTRL_BB…
42863 #define XCVR_BRD_BBF_CTRL_BBF_DCOC_ON(base) (BME_UBFX32(&XCVR_BBF_CTRL_REG(base), XCVR_BBF_CTRL_BBF…
42880 #define XCVR_BRD_BBF_CTRL_BBF_TMUX_ON(base) (BME_UBFX32(&XCVR_BBF_CTRL_REG(base), XCVR_BBF_CTRL_BBF…
42903 #define XCVR_BRD_BBF_CTRL_DCOC_ALPHAC_SCALE_GS_IDX(base) (BME_UBFX32(&XCVR_BBF_CTRL_REG(base), XCVR…
42918 #define XCVR_BRD_BBF_CTRL_BBF_SPARE_3_2(base) (BME_UBFX32(&XCVR_BBF_CTRL_REG(base), XCVR_BBF_CTRL_B…
42967 #define XCVR_BRD_RX_ANA_CTRL_RX_ATST_SEL(base) (BME_UBFX32(&XCVR_RX_ANA_CTRL_REG(base), XCVR_RX_ANA…
42983 #define XCVR_BRD_RX_ANA_CTRL_IQMC_DC_GAIN_ADJ_EN(base) (BME_UBFX32(&XCVR_RX_ANA_CTRL_REG(base), XCV…
42998 #define XCVR_BRD_RX_ANA_CTRL_LNM_SPARE_3_2_1(base) (BME_UBFX32(&XCVR_RX_ANA_CTRL_REG(base), XCVR_RX…
43039 #define XCVR_BRD_XTAL_CTRL_XTAL_TRIM(base) (BME_UBFX32(&XCVR_XTAL_CTRL_REG(base), XCVR_XTAL_CTRL_XT…
43055 #define XCVR_BRD_XTAL_CTRL_XTAL_GM(base) (BME_UBFX32(&XCVR_XTAL_CTRL_REG(base), XCVR_XTAL_CTRL_XTAL…
43071 #define XCVR_BRD_XTAL_CTRL_XTAL_BYPASS(base) (BME_UBFX32(&XCVR_XTAL_CTRL_REG(base), XCVR_XTAL_CTRL_…
43092 #define XCVR_BRD_XTAL_CTRL_XTAL_READY_COUNT_SEL(base) (BME_UBFX32(&XCVR_XTAL_CTRL_REG(base), XCVR_X…
43108 #define XCVR_BRD_XTAL_CTRL_XTAL_COMP_BIAS_LO(base) (BME_UBFX32(&XCVR_XTAL_CTRL_REG(base), XCVR_XTAL…
43125 #define XCVR_BRD_XTAL_CTRL_XTAL_ALC_START_512U(base) (BME_UBFX32(&XCVR_XTAL_CTRL_REG(base), XCVR_XT…
43140 #define XCVR_BRD_XTAL_CTRL_XTAL_ALC_ON(base) (BME_UBFX32(&XCVR_XTAL_CTRL_REG(base), XCVR_XTAL_CTRL_…
43156 #define XCVR_BRD_XTAL_CTRL_XTAL_COMP_BIAS_HI(base) (BME_UBFX32(&XCVR_XTAL_CTRL_REG(base), XCVR_XTAL…
43172 #define XCVR_BRD_XTAL_CTRL_XTAL_READY(base) (BME_UBFX32(&XCVR_XTAL_CTRL_REG(base), XCVR_XTAL_CTRL_X…
43214 #define XCVR_BRD_XTAL_CTRL2_XTAL_REG_SUPPLY(base) (BME_UBFX32(&XCVR_XTAL_CTRL2_REG(base), XCVR_XTAL…
43231 #define XCVR_BRD_XTAL_CTRL2_XTAL_REG_BYPASS_ON(base) (BME_UBFX32(&XCVR_XTAL_CTRL2_REG(base), XCVR_X…
43247 #define XCVR_BRD_XTAL_CTRL2_XTAL_REG_ON_OVRD_ON(base) (BME_UBFX32(&XCVR_XTAL_CTRL2_REG(base), XCVR_…
43262 #define XCVR_BRD_XTAL_CTRL2_XTAL_REG_ON_OVRD(base) (BME_UBFX32(&XCVR_XTAL_CTRL2_REG(base), XCVR_XTA…
43278 #define XCVR_BRD_XTAL_CTRL2_XTAL_ON_OVRD_ON(base) (BME_UBFX32(&XCVR_XTAL_CTRL2_REG(base), XCVR_XTAL…
43293 #define XCVR_BRD_XTAL_CTRL2_XTAL_ON_OVRD(base) (BME_UBFX32(&XCVR_XTAL_CTRL2_REG(base), XCVR_XTAL_CT…
43308 #define XCVR_BRD_XTAL_CTRL2_XTAL_DIG_CLK_OUT_ON(base) (BME_UBFX32(&XCVR_XTAL_CTRL2_REG(base), XCVR_…
43324 #define XCVR_BRD_XTAL_CTRL2_XTAL_REG_ATST_SEL(base) (BME_UBFX32(&XCVR_XTAL_CTRL2_REG(base), XCVR_XT…
43341 #define XCVR_BRD_XTAL_CTRL2_XTAL_ATST_SEL(base) (BME_UBFX32(&XCVR_XTAL_CTRL2_REG(base), XCVR_XTAL_C…
43357 #define XCVR_BRD_XTAL_CTRL2_XTAL_ATST_ON(base) (BME_UBFX32(&XCVR_XTAL_CTRL2_REG(base), XCVR_XTAL_CT…
43372 #define XCVR_BRD_XTAL_CTRL2_XTAL_SPARE(base) (BME_UBFX32(&XCVR_XTAL_CTRL2_REG(base), XCVR_XTAL_CTRL…
43412 #define XCVR_BRD_BGAP_CTRL_BGAP_CURRENT_TRIM(base) (BME_UBFX32(&XCVR_BGAP_CTRL_REG(base), XCVR_BGAP…
43427 #define XCVR_BRD_BGAP_CTRL_BGAP_VOLTAGE_TRIM(base) (BME_UBFX32(&XCVR_BGAP_CTRL_REG(base), XCVR_BGAP…
43444 #define XCVR_BRD_BGAP_CTRL_BGAP_ATST_SEL(base) (BME_UBFX32(&XCVR_BGAP_CTRL_REG(base), XCVR_BGAP_CTR…
43460 #define XCVR_BRD_BGAP_CTRL_BGAP_ATST_ON(base) (BME_UBFX32(&XCVR_BGAP_CTRL_REG(base), XCVR_BGAP_CTRL…
43501 #define XCVR_BRD_PLL_CTRL_PLL_VCO_BIAS(base) (BME_UBFX32(&XCVR_PLL_CTRL_REG(base), XCVR_PLL_CTRL_PL…
43518 #define XCVR_BRD_PLL_CTRL_PLL_LFILT_CNTL(base) (BME_UBFX32(&XCVR_PLL_CTRL_REG(base), XCVR_PLL_CTRL_…
43539 #define XCVR_BRD_PLL_CTRL_PLL_REG_SUPPLY(base) (BME_UBFX32(&XCVR_PLL_CTRL_REG(base), XCVR_PLL_CTRL_…
43556 #define XCVR_BRD_PLL_CTRL_PLL_REG_BYPASS_ON(base) (BME_UBFX32(&XCVR_PLL_CTRL_REG(base), XCVR_PLL_CT…
43573 #define XCVR_BRD_PLL_CTRL_PLL_VCO_LDO_BYPASS(base) (BME_UBFX32(&XCVR_PLL_CTRL_REG(base), XCVR_PLL_C…
43589 #define XCVR_BRD_PLL_CTRL_HPM_BIAS(base) (BME_UBFX32(&XCVR_PLL_CTRL_REG(base), XCVR_PLL_CTRL_HPM_BI…
43604 #define XCVR_BRD_PLL_CTRL_PLL_VCO_SPARE7(base) (BME_UBFX32(&XCVR_PLL_CTRL_REG(base), XCVR_PLL_CTRL_…
43646 #define XCVR_BRD_PLL_CTRL2_PLL_VCO_KV(base) (BME_UBFX32(&XCVR_PLL_CTRL2_REG(base), XCVR_PLL_CTRL2_P…
43662 #define XCVR_BRD_PLL_CTRL2_PLL_KMOD_SLOPE(base) (BME_UBFX32(&XCVR_PLL_CTRL2_REG(base), XCVR_PLL_CTR…
43681 #define XCVR_BRD_PLL_CTRL2_PLL_VCO_REG_SUPPLY(base) (BME_UBFX32(&XCVR_PLL_CTRL2_REG(base), XCVR_PLL…
43697 #define XCVR_BRD_PLL_CTRL2_PLL_TMUX_ON(base) (BME_UBFX32(&XCVR_PLL_CTRL2_REG(base), XCVR_PLL_CTRL2_…
43742 #define XCVR_BRD_PLL_TEST_CTRL_PLL_TMUX_SEL(base) (BME_UBFX32(&XCVR_PLL_TEST_CTRL_REG(base), XCVR_P…
43758 #define XCVR_BRD_PLL_TEST_CTRL_PLL_VCO_REG_ATST(base) (BME_UBFX32(&XCVR_PLL_TEST_CTRL_REG(base), XC…
43774 #define XCVR_BRD_PLL_TEST_CTRL_PLL_REG_ATST_SEL(base) (BME_UBFX32(&XCVR_PLL_TEST_CTRL_REG(base), XC…
43789 #define XCVR_BRD_PLL_TEST_CTRL_PLL_VCO_TEST_CLK_MODE(base) (BME_UBFX32(&XCVR_PLL_TEST_CTRL_REG(base…
43804 #define XCVR_BRD_PLL_TEST_CTRL_PLL_FORCE_VTUNE_EXTERNALLY(base) (BME_UBFX32(&XCVR_PLL_TEST_CTRL_REG…
43819 #define XCVR_BRD_PLL_TEST_CTRL_PLL_RIPPLE_COUNTER_TEST_MODE(base) (BME_UBFX32(&XCVR_PLL_TEST_CTRL_R…
43865 #define XCVR_BRD_QGEN_CTRL_QGEN_REG_SUPPLY(base) (BME_UBFX32(&XCVR_QGEN_CTRL_REG(base), XCVR_QGEN_C…
43881 #define XCVR_BRD_QGEN_CTRL_QGEN_REG_ATST_SEL(base) (BME_UBFX32(&XCVR_QGEN_CTRL_REG(base), XCVR_QGEN…
43898 #define XCVR_BRD_QGEN_CTRL_QGEN_REG_BYPASS_ON(base) (BME_UBFX32(&XCVR_QGEN_CTRL_REG(base), XCVR_QGE…
43938 #define XCVR_BRD_TCA_CTRL_TCA_BIAS_CURR(base) (BME_UBFX32(&XCVR_TCA_CTRL_REG(base), XCVR_TCA_CTRL_T…
43953 #define XCVR_BRD_TCA_CTRL_TCA_LOW_PWR_ON(base) (BME_UBFX32(&XCVR_TCA_CTRL_REG(base), XCVR_TCA_CTRL_…
43970 #define XCVR_BRD_TCA_CTRL_TCA_TX_REG_BYPASS_ON(base) (BME_UBFX32(&XCVR_TCA_CTRL_REG(base), XCVR_TCA…
43991 #define XCVR_BRD_TCA_CTRL_TCA_TX_REG_SUPPLY(base) (BME_UBFX32(&XCVR_TCA_CTRL_REG(base), XCVR_TCA_CT…
44007 #define XCVR_BRD_TCA_CTRL_TCA_TX_REG_ATST_SEL(base) (BME_UBFX32(&XCVR_TCA_CTRL_REG(base), XCVR_TCA_…
44049 #define XCVR_BRD_TZA_CTRL_TZA_CAP_TUNE(base) (BME_UBFX32(&XCVR_TZA_CTRL_REG(base), XCVR_TZA_CTRL_TZ…
44064 #define XCVR_BRD_TZA_CTRL_TZA_GAIN(base) (BME_UBFX32(&XCVR_TZA_CTRL_REG(base), XCVR_TZA_CTRL_TZA_GA…
44080 #define XCVR_BRD_TZA_CTRL_TZA_DCOC_ON(base) (BME_UBFX32(&XCVR_TZA_CTRL_REG(base), XCVR_TZA_CTRL_TZA…
44095 #define XCVR_BRD_TZA_CTRL_TZA_CUR_CNTL(base) (BME_UBFX32(&XCVR_TZA_CTRL_REG(base), XCVR_TZA_CTRL_TZ…
44110 #define XCVR_BRD_TZA_CTRL_TZA_SPARE(base) (BME_UBFX32(&XCVR_TZA_CTRL_REG(base), XCVR_TZA_CTRL_TZA_S…
44151 #define XCVR_BRD_TX_ANA_CTRL_HPM_CAL_ADJUST(base) (BME_UBFX32(&XCVR_TX_ANA_CTRL_REG(base), XCVR_TX_…
44195 #define XCVR_BRD_ANA_SPARE_IQMC_DC_GAIN_ADJ(base) (BME_UBFX32(&XCVR_ANA_SPARE_REG(base), XCVR_ANA_S…
44221 #define XCVR_BRD_ANA_SPARE_DCOC_TRK_EST_GS_CNT(base) (BME_UBFX32(&XCVR_ANA_SPARE_REG(base), XCVR_AN…
44236 #define XCVR_BRD_ANA_SPARE_HPM_LSB_INVERT(base) (BME_UBFX32(&XCVR_ANA_SPARE_REG(base), XCVR_ANA_SPA…
44251 #define XCVR_BRD_ANA_SPARE_ANA_DTEST(base) (BME_UBFX32(&XCVR_ANA_SPARE_REG(base), XCVR_ANA_SPARE_AN…
44343 #define ZLL_BRD_IRQSTS_SEQIRQ(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_SEQIRQ_SHIFT, ZLL…
44360 #define ZLL_BRD_IRQSTS_TXIRQ(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_TXIRQ_SHIFT, ZLL_I…
44377 #define ZLL_BRD_IRQSTS_RXIRQ(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_RXIRQ_SHIFT, ZLL_I…
44394 #define ZLL_BRD_IRQSTS_CCAIRQ(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_CCAIRQ_SHIFT, ZLL…
44411 #define ZLL_BRD_IRQSTS_RXWTRMRKIRQ(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_RXWTRMRKIRQ_…
44428 #define ZLL_BRD_IRQSTS_FILTERFAIL_IRQ(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_FILTERFAI…
44445 #define ZLL_BRD_IRQSTS_PLL_UNLOCK_IRQ(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_PLL_UNLOC…
44458 #define ZLL_BRD_IRQSTS_RX_FRM_PEND(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_RX_FRM_PEND_…
44471 #define ZLL_BRD_IRQSTS_PB_ERR_IRQ(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_PB_ERR_IRQ_SH…
44489 #define ZLL_BRD_IRQSTS_TMRSTATUS(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_TMRSTATUS_SHIF…
44504 #define ZLL_BRD_IRQSTS_PI(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_PI_SHIFT, ZLL_IRQSTS_…
44523 #define ZLL_BRD_IRQSTS_SRCADDR(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_SRCADDR_SHIFT, Z…
44539 #define ZLL_BRD_IRQSTS_CCA(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_CCA_SHIFT, ZLL_IRQST…
44556 #define ZLL_BRD_IRQSTS_CRCVALID(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_CRCVALID_SHIFT,…
44568 #define ZLL_BRD_IRQSTS_TMR1IRQ(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_TMR1IRQ_SHIFT, Z…
44585 #define ZLL_BRD_IRQSTS_TMR2IRQ(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_TMR2IRQ_SHIFT, Z…
44601 #define ZLL_BRD_IRQSTS_TMR3IRQ(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_TMR3IRQ_SHIFT, Z…
44617 #define ZLL_BRD_IRQSTS_TMR4IRQ(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_TMR4IRQ_SHIFT, Z…
44634 #define ZLL_BRD_IRQSTS_TMR1MSK(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_TMR1MSK_SHIFT, Z…
44651 #define ZLL_BRD_IRQSTS_TMR2MSK(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_TMR2MSK_SHIFT, Z…
44668 #define ZLL_BRD_IRQSTS_TMR3MSK(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_TMR3MSK_SHIFT, Z…
44685 #define ZLL_BRD_IRQSTS_TMR4MSK(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_TMR4MSK_SHIFT, Z…
44701 #define ZLL_BRD_IRQSTS_RX_FRAME_LENGTH(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_RX_FRAME…
44749 #define ZLL_BRD_PHY_CTRL_XCVSEQ(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_XCVSEQ_SHIF…
44771 #define ZLL_BRD_PHY_CTRL_AUTOACK(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_AUTOACK_SH…
44792 #define ZLL_BRD_PHY_CTRL_RXACKRQD(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_RXACKRQD_…
44812 #define ZLL_BRD_PHY_CTRL_CCABFRTX(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_CCABFRTX_…
44831 #define ZLL_BRD_PHY_CTRL_SLOTTED(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_SLOTTED_SH…
44849 #define ZLL_BRD_PHY_CTRL_TMRTRIGEN(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_TMRTRIGE…
44867 #define ZLL_BRD_PHY_CTRL_SEQMSK(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_SEQMSK_SHIF…
44885 #define ZLL_BRD_PHY_CTRL_TXMSK(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_TXMSK_SHIFT,…
44903 #define ZLL_BRD_PHY_CTRL_RXMSK(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_RXMSK_SHIFT,…
44923 #define ZLL_BRD_PHY_CTRL_CCAMSK(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_CCAMSK_SHIF…
44944 #define ZLL_BRD_PHY_CTRL_RX_WMRK_MSK(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_RX_WMR…
44965 #define ZLL_BRD_PHY_CTRL_FILTERFAIL_MSK(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_FIL…
44983 #define ZLL_BRD_PHY_CTRL_PLL_UNLOCK_MSK(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_PLL…
45006 #define ZLL_BRD_PHY_CTRL_CRC_MSK(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_CRC_MSK_SH…
45023 #define ZLL_BRD_PHY_CTRL_PB_ERR_MSK(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_PB_ERR_…
45040 #define ZLL_BRD_PHY_CTRL_TMR1CMP_EN(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_TMR1CMP…
45057 #define ZLL_BRD_PHY_CTRL_TMR2CMP_EN(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_TMR2CMP…
45074 #define ZLL_BRD_PHY_CTRL_TMR3CMP_EN(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_TMR3CMP…
45091 #define ZLL_BRD_PHY_CTRL_TMR4CMP_EN(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_TMR4CMP…
45110 #define ZLL_BRD_PHY_CTRL_TC2PRIME_EN(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_TC2PRI…
45130 #define ZLL_BRD_PHY_CTRL_PROMISCUOUS(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_PROMIS…
45164 #define ZLL_BRD_PHY_CTRL_CCATYPE(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_CCATYPE_SH…
45180 #define ZLL_BRD_PHY_CTRL_PANCORDNTR0(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_PANCOR…
45199 #define ZLL_BRD_PHY_CTRL_TC3TMOUT(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_TC3TMOUT_…
45218 #define ZLL_BRD_PHY_CTRL_TRCV_MSK(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_TRCV_MSK_…
45405 #define ZLL_BRD_T2PRIMECMP_T2PRIMECMP(base) (BME_UBFX32(&ZLL_T2PRIMECMP_REG(base), ZLL_T2PRIMECMP_T…
45527 #define ZLL_BRD_PA_PWR_PA_PWR(base) (BME_UBFX32(&ZLL_PA_PWR_REG(base), ZLL_PA_PWR_PA_PWR_SHIFT, ZLL…
45569 #define ZLL_BRD_CHANNEL_NUM0_CHANNEL_NUM0(base) (BME_UBFX32(&ZLL_CHANNEL_NUM0_REG(base), ZLL_CHANNE…
45605 #define ZLL_BRD_LQI_AND_RSSI_LQI_VALUE(base) (BME_UBFX32(&ZLL_LQI_AND_RSSI_REG(base), ZLL_LQI_AND_R…
45616 #define ZLL_BRD_LQI_AND_RSSI_RSSI(base) (BME_UBFX32(&ZLL_LQI_AND_RSSI_REG(base), ZLL_LQI_AND_RSSI_R…
45628 #define ZLL_BRD_LQI_AND_RSSI_CCA1_ED_FNL(base) (BME_UBFX32(&ZLL_LQI_AND_RSSI_REG(base), ZLL_LQI_AND…
45670 #define ZLL_BRD_MACSHORTADDRS0_MACPANID0(base) (BME_UBFX32(&ZLL_MACSHORTADDRS0_REG(base), ZLL_MACSH…
45687 #define ZLL_BRD_MACSHORTADDRS0_MACSHORTADDRS0(base) (BME_UBFX32(&ZLL_MACSHORTADDRS0_REG(base), ZLL_…
45779 #define ZLL_BRD_RX_FRAME_FILTER_BEACON_FT(base) (BME_UBFX32(&ZLL_RX_FRAME_FILTER_REG(base), ZLL_RX_…
45796 #define ZLL_BRD_RX_FRAME_FILTER_DATA_FT(base) (BME_UBFX32(&ZLL_RX_FRAME_FILTER_REG(base), ZLL_RX_FR…
45813 #define ZLL_BRD_RX_FRAME_FILTER_ACK_FT(base) (BME_UBFX32(&ZLL_RX_FRAME_FILTER_REG(base), ZLL_RX_FRA…
45830 #define ZLL_BRD_RX_FRAME_FILTER_CMD_FT(base) (BME_UBFX32(&ZLL_RX_FRAME_FILTER_REG(base), ZLL_RX_FRA…
45849 #define ZLL_BRD_RX_FRAME_FILTER_NS_FT(base) (BME_UBFX32(&ZLL_RX_FRAME_FILTER_REG(base), ZLL_RX_FRAM…
45868 #define ZLL_BRD_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS(base) (BME_UBFX32(&ZLL_RX_FRAME_FILTER_REG(base)…
45891 #define ZLL_BRD_RX_FRAME_FILTER_FRM_VER(base) (BME_UBFX32(&ZLL_RX_FRAME_FILTER_REG(base), ZLL_RX_FR…
45931 #define ZLL_BRD_CCA_LQI_CTRL_CCA1_THRESH(base) (BME_UBFX32(&ZLL_CCA_LQI_CTRL_REG(base), ZLL_CCA_LQI…
45946 #define ZLL_BRD_CCA_LQI_CTRL_LQI_OFFSET_COMP(base) (BME_UBFX32(&ZLL_CCA_LQI_CTRL_REG(base), ZLL_CCA…
45965 #define ZLL_BRD_CCA_LQI_CTRL_CCA3_AND_NOT_OR(base) (BME_UBFX32(&ZLL_CCA_LQI_CTRL_REG(base), ZLL_CCA…
46008 #define ZLL_BRD_CCA2_CTRL_CCA2_NUM_CORR_PEAKS(base) (BME_UBFX32(&ZLL_CCA2_CTRL_REG(base), ZLL_CCA2_…
46023 #define ZLL_BRD_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH(base) (BME_UBFX32(&ZLL_CCA2_CTRL_REG(base), ZLL_CCA2…
46042 #define ZLL_BRD_CCA2_CTRL_CCA2_CORR_THRESH(base) (BME_UBFX32(&ZLL_CCA2_CTRL_REG(base), ZLL_CCA2_CTR…
46084 #define ZLL_BRD_FAD_CTRL_FAD_EN(base) (BME_UBFX32(&ZLL_FAD_CTRL_REG(base), ZLL_FAD_CTRL_FAD_EN_SHIF…
46103 #define ZLL_BRD_FAD_CTRL_ANTX(base) (BME_UBFX32(&ZLL_FAD_CTRL_REG(base), ZLL_FAD_CTRL_ANTX_SHIFT, Z…
46125 #define ZLL_BRD_FAD_CTRL_FAD_NOT_GPIO(base) (BME_UBFX32(&ZLL_FAD_CTRL_REG(base), ZLL_FAD_CTRL_FAD_N…
46147 #define ZLL_BRD_FAD_CTRL_ANTX_EN(base) (BME_UBFX32(&ZLL_FAD_CTRL_REG(base), ZLL_FAD_CTRL_ANTX_EN_SH…
46165 #define ZLL_BRD_FAD_CTRL_ANTX_HZ(base) (BME_UBFX32(&ZLL_FAD_CTRL_REG(base), ZLL_FAD_CTRL_ANTX_HZ_SH…
46188 #define ZLL_BRD_FAD_CTRL_ANTX_CTRLMODE(base) (BME_UBFX32(&ZLL_FAD_CTRL_REG(base), ZLL_FAD_CTRL_ANTX…
46208 #define ZLL_BRD_FAD_CTRL_ANTX_POL(base) (BME_UBFX32(&ZLL_FAD_CTRL_REG(base), ZLL_FAD_CTRL_ANTX_POL_…
46251 #define ZLL_BRD_SNF_CTRL_SNF_EN(base) (BME_UBFX32(&ZLL_SNF_CTRL_REG(base), ZLL_SNF_CTRL_SNF_EN_SHIF…
46295 #define ZLL_BRD_BSM_CTRL_BSM_EN(base) (BME_UBFX32(&ZLL_BSM_CTRL_REG(base), ZLL_BSM_CTRL_BSM_EN_SHIF…
46341 #define ZLL_BRD_MACSHORTADDRS1_MACPANID1(base) (BME_UBFX32(&ZLL_MACSHORTADDRS1_REG(base), ZLL_MACSH…
46358 #define ZLL_BRD_MACSHORTADDRS1_MACSHORTADDRS1(base) (BME_UBFX32(&ZLL_MACSHORTADDRS1_REG(base), ZLL_…
46457 #define ZLL_BRD_DUAL_PAN_CTRL_ACTIVE_NETWORK(base) (BME_UBFX32(&ZLL_DUAL_PAN_CTRL_REG(base), ZLL_DU…
46477 #define ZLL_BRD_DUAL_PAN_CTRL_DUAL_PAN_AUTO(base) (BME_UBFX32(&ZLL_DUAL_PAN_CTRL_REG(base), ZLL_DUA…
46493 #define ZLL_BRD_DUAL_PAN_CTRL_PANCORDNTR1(base) (BME_UBFX32(&ZLL_DUAL_PAN_CTRL_REG(base), ZLL_DUAL_…
46513 #define ZLL_BRD_DUAL_PAN_CTRL_CURRENT_NETWORK(base) (BME_UBFX32(&ZLL_DUAL_PAN_CTRL_REG(base), ZLL_D…
46541 #define ZLL_BRD_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN(base) (BME_UBFX32(&ZLL_DUAL_PAN_CTRL_REG(base), ZL…
46558 #define ZLL_BRD_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL(base) (BME_UBFX32(&ZLL_DUAL_PAN_CTRL_REG(base), Z…
46587 #define ZLL_BRD_DUAL_PAN_CTRL_DUAL_PAN_DWELL(base) (BME_UBFX32(&ZLL_DUAL_PAN_CTRL_REG(base), ZLL_DU…
46609 #define ZLL_BRD_DUAL_PAN_CTRL_DUAL_PAN_REMAIN(base) (BME_UBFX32(&ZLL_DUAL_PAN_CTRL_REG(base), ZLL_D…
46626 #define ZLL_BRD_DUAL_PAN_CTRL_RECD_ON_PAN0(base) (BME_UBFX32(&ZLL_DUAL_PAN_CTRL_REG(base), ZLL_DUAL…
46643 #define ZLL_BRD_DUAL_PAN_CTRL_RECD_ON_PAN1(base) (BME_UBFX32(&ZLL_DUAL_PAN_CTRL_REG(base), ZLL_DUAL…
46682 #define ZLL_BRD_CHANNEL_NUM1_CHANNEL_NUM1(base) (BME_UBFX32(&ZLL_CHANNEL_NUM1_REG(base), ZLL_CHANNE…
46726 #define ZLL_BRD_SAM_CTRL_SAP0_EN(base) (BME_UBFX32(&ZLL_SAM_CTRL_REG(base), ZLL_SAM_CTRL_SAP0_EN_SH…
46743 #define ZLL_BRD_SAM_CTRL_SAA0_EN(base) (BME_UBFX32(&ZLL_SAM_CTRL_REG(base), ZLL_SAM_CTRL_SAA0_EN_SH…
46760 #define ZLL_BRD_SAM_CTRL_SAP1_EN(base) (BME_UBFX32(&ZLL_SAM_CTRL_REG(base), ZLL_SAM_CTRL_SAP1_EN_SH…
46777 #define ZLL_BRD_SAM_CTRL_SAA1_EN(base) (BME_UBFX32(&ZLL_SAM_CTRL_REG(base), ZLL_SAM_CTRL_SAA1_EN_SH…
46790 #define ZLL_BRD_SAM_CTRL_SAA0_START(base) (BME_UBFX32(&ZLL_SAM_CTRL_REG(base), ZLL_SAM_CTRL_SAA0_ST…
46803 #define ZLL_BRD_SAM_CTRL_SAP1_START(base) (BME_UBFX32(&ZLL_SAM_CTRL_REG(base), ZLL_SAM_CTRL_SAP1_ST…
46816 #define ZLL_BRD_SAM_CTRL_SAA1_START(base) (BME_UBFX32(&ZLL_SAM_CTRL_REG(base), ZLL_SAM_CTRL_SAA1_ST…
46859 #define ZLL_BRD_SAM_TABLE_SAM_INDEX(base) (BME_UBFX32(&ZLL_SAM_TABLE_REG(base), ZLL_SAM_TABLE_SAM_I…
46896 #define ZLL_BRD_SAM_TABLE_SAM_CHECKSUM(base) (BME_UBFX32(&ZLL_SAM_TABLE_REG(base), ZLL_SAM_TABLE_SA…
46934 #define ZLL_BRD_SAM_TABLE_ACK_FRM_PND(base) (BME_UBFX32(&ZLL_SAM_TABLE_REG(base), ZLL_SAM_TABLE_ACK…
46953 #define ZLL_BRD_SAM_TABLE_ACK_FRM_PND_CTRL(base) (BME_UBFX32(&ZLL_SAM_TABLE_REG(base), ZLL_SAM_TABL…
46999 #define ZLL_BRD_SAM_TABLE_SAM_BUSY(base) (BME_UBFX32(&ZLL_SAM_TABLE_REG(base), ZLL_SAM_TABLE_SAM_BU…
47030 #define ZLL_BRD_SAM_MATCH_SAP0_MATCH(base) (BME_UBFX32(&ZLL_SAM_MATCH_REG(base), ZLL_SAM_MATCH_SAP0…
47039 #define ZLL_BRD_SAM_MATCH_SAP0_ADDR_PRESENT(base) (BME_UBFX32(&ZLL_SAM_MATCH_REG(base), ZLL_SAM_MAT…
47048 #define ZLL_BRD_SAM_MATCH_SAA0_MATCH(base) (BME_UBFX32(&ZLL_SAM_MATCH_REG(base), ZLL_SAM_MATCH_SAA0…
47057 #define ZLL_BRD_SAM_MATCH_SAA0_ADDR_ABSENT(base) (BME_UBFX32(&ZLL_SAM_MATCH_REG(base), ZLL_SAM_MATC…
47066 #define ZLL_BRD_SAM_MATCH_SAP1_MATCH(base) (BME_UBFX32(&ZLL_SAM_MATCH_REG(base), ZLL_SAM_MATCH_SAP1…
47075 #define ZLL_BRD_SAM_MATCH_SAP1_ADDR_PRESENT(base) (BME_UBFX32(&ZLL_SAM_MATCH_REG(base), ZLL_SAM_MAT…
47084 #define ZLL_BRD_SAM_MATCH_SAA1_MATCH(base) (BME_UBFX32(&ZLL_SAM_MATCH_REG(base), ZLL_SAM_MATCH_SAA1…
47093 #define ZLL_BRD_SAM_MATCH_SAA1_ADDR_ABSENT(base) (BME_UBFX32(&ZLL_SAM_MATCH_REG(base), ZLL_SAM_MATC…
47124 #define ZLL_BRD_SAM_FREE_IDX_SAP0_1ST_FREE_IDX(base) (BME_UBFX32(&ZLL_SAM_FREE_IDX_REG(base), ZLL_S…
47133 #define ZLL_BRD_SAM_FREE_IDX_SAA0_1ST_FREE_IDX(base) (BME_UBFX32(&ZLL_SAM_FREE_IDX_REG(base), ZLL_S…
47142 #define ZLL_BRD_SAM_FREE_IDX_SAP1_1ST_FREE_IDX(base) (BME_UBFX32(&ZLL_SAM_FREE_IDX_REG(base), ZLL_S…
47151 #define ZLL_BRD_SAM_FREE_IDX_SAA1_1ST_FREE_IDX(base) (BME_UBFX32(&ZLL_SAM_FREE_IDX_REG(base), ZLL_S…
47193 #define ZLL_BRD_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL…
47214 #define ZLL_BRD_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), …
47235 #define ZLL_BRD_SEQ_CTRL_STS_LATCH_PREAMBLE(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL_SEQ_…
47256 #define ZLL_BRD_SEQ_CTRL_STS_NO_RX_RECYCLE(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL_SEQ_C…
47273 #define ZLL_BRD_SEQ_CTRL_STS_FORCE_CRC_ERROR(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL_SEQ…
47293 #define ZLL_BRD_SEQ_CTRL_STS_CONTINUOUS_EN(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL_SEQ_C…
47311 #define ZLL_BRD_SEQ_CTRL_STS_XCVSEQ_ACTUAL(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL_SEQ_C…
47320 #define ZLL_BRD_SEQ_CTRL_STS_SEQ_IDLE(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL_SEQ_CTRL_S…
47337 #define ZLL_BRD_SEQ_CTRL_STS_NEW_SEQ_INHIBIT(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL_SEQ…
47353 #define ZLL_BRD_SEQ_CTRL_STS_RX_TIMEOUT_PENDING(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL_…
47367 #define ZLL_BRD_SEQ_CTRL_STS_RX_MODE(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL_SEQ_CTRL_ST…
47385 #define ZLL_BRD_SEQ_CTRL_STS_TMR2_SEQ_TRIG_ARMED(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL…
47402 #define ZLL_BRD_SEQ_CTRL_STS_SEQ_T_STATUS(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL_SEQ_CT…
47416 #define ZLL_BRD_SEQ_CTRL_STS_SW_ABORTED(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL_SEQ_CTRL…
47430 #define ZLL_BRD_SEQ_CTRL_STS_TC3_ABORTED(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL_SEQ_CTR…
47443 #define ZLL_BRD_SEQ_CTRL_STS_PLL_ABORTED(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL_SEQ_CTR…
47484 #define ZLL_BRD_ACKDELAY_ACKDELAY(base) (BME_UBFX32(&ZLL_ACKDELAY_REG(base), ZLL_ACKDELAY_ACKDELAY_…
47505 #define ZLL_BRD_ACKDELAY_TXDELAY(base) (BME_UBFX32(&ZLL_ACKDELAY_REG(base), ZLL_ACKDELAY_TXDELAY_SH…
47558 #define ZLL_BRD_FILTERFAIL_CODE_FILTERFAIL_CODE(base) (BME_UBFX32(&ZLL_FILTERFAIL_CODE_REG(base), Z…
47571 #define ZLL_BRD_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL(base) (BME_UBFX32(&ZLL_FILTERFAIL_CODE_REG(base)…
47614 #define ZLL_BRD_RX_WTR_MARK_RX_WTR_MARK(base) (BME_UBFX32(&ZLL_RX_WTR_MARK_REG(base), ZLL_RX_WTR_MA…
47661 #define ZLL_BRD_SLOT_PRELOAD_SLOT_PRELOAD(base) (BME_UBFX32(&ZLL_SLOT_PRELOAD_REG(base), ZLL_SLOT_P…
47699 #define ZLL_BRD_SEQ_STATE_SEQ_STATE(base) (BME_UBFX32(&ZLL_SEQ_STATE_REG(base), ZLL_SEQ_STATE_SEQ_S…
47718 #define ZLL_BRD_SEQ_STATE_PREAMBLE_DET(base) (BME_UBFX32(&ZLL_SEQ_STATE_REG(base), ZLL_SEQ_STATE_PR…
47738 #define ZLL_BRD_SEQ_STATE_SFD_DET(base) (BME_UBFX32(&ZLL_SEQ_STATE_REG(base), ZLL_SEQ_STATE_SFD_DET…
47757 #define ZLL_BRD_SEQ_STATE_FILTERFAIL_FLAG_SEL(base) (BME_UBFX32(&ZLL_SEQ_STATE_REG(base), ZLL_SEQ_S…
47774 #define ZLL_BRD_SEQ_STATE_CRCVALID(base) (BME_UBFX32(&ZLL_SEQ_STATE_REG(base), ZLL_SEQ_STATE_CRCVAL…
47787 #define ZLL_BRD_SEQ_STATE_PLL_ABORT(base) (BME_UBFX32(&ZLL_SEQ_STATE_REG(base), ZLL_SEQ_STATE_PLL_A…
47802 #define ZLL_BRD_SEQ_STATE_PLL_ABORTED(base) (BME_UBFX32(&ZLL_SEQ_STATE_REG(base), ZLL_SEQ_STATE_PLL…
47816 #define ZLL_BRD_SEQ_STATE_RX_BYTE_COUNT(base) (BME_UBFX32(&ZLL_SEQ_STATE_REG(base), ZLL_SEQ_STATE_R…
47833 #define ZLL_BRD_SEQ_STATE_CCCA_BUSY_CNT(base) (BME_UBFX32(&ZLL_SEQ_STATE_REG(base), ZLL_SEQ_STATE_C…
47882 #define ZLL_BRD_TMR_PRESCALE_TMR_PRESCALE(base) (BME_UBFX32(&ZLL_TMR_PRESCALE_REG(base), ZLL_TMR_PR…
47986 #define ZLL_BRD_LENIENCY_MSB_LENIENCY_REGISTER(base) (BME_UBFX32(&ZLL_LENIENCY_MSB_REG(base), ZLL_L…
48021 #define ZLL_BRD_PART_ID_PART_ID(base) (BME_UBFX32(&ZLL_PART_ID_REG(base), ZLL_PART_ID_PART_ID_SHIFT…