Lines Matching refs:BME_OR32

148 #define ADC_SET_SC1(base, index, value) (BME_OR32(&ADC_SC1_REG(base, index), (uint32_t)(value)))
329 #define ADC_SET_CFG1(base, value) (BME_OR32(&ADC_CFG1_REG(base), (uint32_t)(value)))
477 #define ADC_SET_CFG2(base, value) (BME_OR32(&ADC_CFG2_REG(base), (uint32_t)(value)))
666 #define ADC_SET_CV1(base, value) (BME_OR32(&ADC_CV1_REG(base), (uint32_t)(value)))
713 #define ADC_SET_CV2(base, value) (BME_OR32(&ADC_CV2_REG(base), (uint32_t)(value)))
755 #define ADC_SET_SC2(base, value) (BME_OR32(&ADC_SC2_REG(base), (uint32_t)(value)))
932 #define ADC_SET_SC3(base, value) (BME_OR32(&ADC_SC3_REG(base), (uint32_t)(value)))
1091 #define ADC_SET_OFS(base, value) (BME_OR32(&ADC_OFS_REG(base), (uint32_t)(value)))
1143 #define ADC_SET_PG(base, value)  (BME_OR32(&ADC_PG_REG(base), (uint32_t)(value)))
1193 #define ADC_SET_MG(base, value)  (BME_OR32(&ADC_MG_REG(base), (uint32_t)(value)))
1249 #define ADC_SET_CLPD(base, value) (BME_OR32(&ADC_CLPD_REG(base), (uint32_t)(value)))
1291 #define ADC_SET_CLPS(base, value) (BME_OR32(&ADC_CLPS_REG(base), (uint32_t)(value)))
1333 #define ADC_SET_CLP4(base, value) (BME_OR32(&ADC_CLP4_REG(base), (uint32_t)(value)))
1375 #define ADC_SET_CLP3(base, value) (BME_OR32(&ADC_CLP3_REG(base), (uint32_t)(value)))
1417 #define ADC_SET_CLP2(base, value) (BME_OR32(&ADC_CLP2_REG(base), (uint32_t)(value)))
1459 #define ADC_SET_CLP1(base, value) (BME_OR32(&ADC_CLP1_REG(base), (uint32_t)(value)))
1501 #define ADC_SET_CLP0(base, value) (BME_OR32(&ADC_CLP0_REG(base), (uint32_t)(value)))
1559 #define ADC_SET_CLMD(base, value) (BME_OR32(&ADC_CLMD_REG(base), (uint32_t)(value)))
1601 #define ADC_SET_CLMS(base, value) (BME_OR32(&ADC_CLMS_REG(base), (uint32_t)(value)))
1643 #define ADC_SET_CLM4(base, value) (BME_OR32(&ADC_CLM4_REG(base), (uint32_t)(value)))
1685 #define ADC_SET_CLM3(base, value) (BME_OR32(&ADC_CLM3_REG(base), (uint32_t)(value)))
1727 #define ADC_SET_CLM2(base, value) (BME_OR32(&ADC_CLM2_REG(base), (uint32_t)(value)))
1769 #define ADC_SET_CLM1(base, value) (BME_OR32(&ADC_CLM1_REG(base), (uint32_t)(value)))
1811 #define ADC_SET_CLM0(base, value) (BME_OR32(&ADC_CLM0_REG(base), (uint32_t)(value)))
3706 #define DCDC_SET_REG0(base, value) (BME_OR32(&DCDC_REG0_REG(base), (uint32_t)(value)))
4016 #define DCDC_SET_REG1(base, value) (BME_OR32(&DCDC_REG1_REG(base), (uint32_t)(value)))
4139 #define DCDC_SET_REG2(base, value) (BME_OR32(&DCDC_REG2_REG(base), (uint32_t)(value)))
4267 #define DCDC_SET_REG3(base, value) (BME_OR32(&DCDC_REG3_REG(base), (uint32_t)(value)))
4497 #define DCDC_SET_REG4(base, value) (BME_OR32(&DCDC_REG4_REG(base), (uint32_t)(value)))
4554 #define DCDC_SET_REG6(base, value) (BME_OR32(&DCDC_REG6_REG(base), (uint32_t)(value)))
4650 #define DCDC_SET_REG7(base, value) (BME_OR32(&DCDC_REG7_REG(base), (uint32_t)(value)))
4748 #define DMA_SET_SAR(base, index, value) (BME_OR32(&DMA_SAR_REG(base, index), (uint32_t)(value)))
4776 #define DMA_SET_DAR(base, index, value) (BME_OR32(&DMA_DAR_REG(base, index), (uint32_t)(value)))
4809 #define DMA_SET_DSR_BCR(base, index, value) (BME_OR32(&DMA_DSR_BCR_REG(base, index), (uint32_t)(val…
4982 #define DMA_SET_DCR(base, index, value) (BME_OR32(&DMA_DCR_REG(base, index), (uint32_t)(value)))
7089 #define GPIO_SET_PDOR(base, value) (BME_OR32(&GPIO_PDOR_REG(base), (uint32_t)(value)))
7190 #define GPIO_SET_PDDR(base, value) (BME_OR32(&GPIO_PDDR_REG(base), (uint32_t)(value)))
9890 #define LPTMR_SET_CSR(base, value) (BME_OR32(&LPTMR_CSR_REG(base), (uint32_t)(value)))
10062 #define LPTMR_SET_PSR(base, value) (BME_OR32(&LPTMR_PSR_REG(base), (uint32_t)(value)))
10184 #define LPTMR_SET_CMR(base, value) (BME_OR32(&LPTMR_CMR_REG(base), (uint32_t)(value)))
10228 #define LPTMR_SET_CNR(base, value) (BME_OR32(&LPTMR_CNR_REG(base), (uint32_t)(value)))
10283 #define LPUART_SET_BAUD(base, value) (BME_OR32(&LPUART_BAUD_REG(base), (uint32_t)(value)))
10569 #define LPUART_SET_STAT(base, value) (BME_OR32(&LPUART_STAT_REG(base), (uint32_t)(value)))
11012 #define LPUART_SET_CTRL(base, value) (BME_OR32(&LPUART_CTRL_REG(base), (uint32_t)(value)))
11604 #define LPUART_SET_DATA(base, value) (BME_OR32(&LPUART_DATA_REG(base), (uint32_t)(value)))
11869 #define LPUART_SET_MATCH(base, value) (BME_OR32(&LPUART_MATCH_REG(base), (uint32_t)(value)))
11934 #define LPUART_SET_MODIR(base, value) (BME_OR32(&LPUART_MODIR_REG(base), (uint32_t)(value)))
12159 #define LTC_SET_MD(base, value)  (BME_OR32(&LTC_MD_REG(base), (uint32_t)(value)))
12303 #define LTC_SET_KS(base, value)  (BME_OR32(&LTC_KS_REG(base), (uint32_t)(value)))
12335 #define LTC_SET_DS(base, value)  (BME_OR32(&LTC_DS_REG(base), (uint32_t)(value)))
12383 #define LTC_SET_ICVS(base, value) (BME_OR32(&LTC_ICVS_REG(base), (uint32_t)(value)))
12483 #define LTC_SET_CTL(base, value) (BME_OR32(&LTC_CTL_REG(base), (uint32_t)(value)))
12877 #define LTC_SET_STA(base, value) (BME_OR32(&LTC_STA_REG(base), (uint32_t)(value)))
13039 #define LTC_SET_AADSZ(base, value) (BME_OR32(&LTC_AADSZ_REG(base), (uint32_t)(value)))
13103 #define LTC_SET_CTX(base, index, value) (BME_OR32(&LTC_CTX_REG(base, index), (uint32_t)(value)))
13132 #define LTC_SET_KEY(base, index, value) (BME_OR32(&LTC_KEY_REG(base, index), (uint32_t)(value)))
16240 #define PIT_SET_MCR(base, value) (BME_OR32(&PIT_MCR_REG(base), (uint32_t)(value)))
16350 #define PIT_SET_LDVAL(base, index, value) (BME_OR32(&PIT_LDVAL_REG(base, index), (uint32_t)(value)))
16392 #define PIT_SET_TCTRL(base, index, value) (BME_OR32(&PIT_TCTRL_REG(base, index), (uint32_t)(value)))
16480 #define PIT_SET_TFLG(base, index, value) (BME_OR32(&PIT_TFLG_REG(base, index), (uint32_t)(value)))
16909 #define PORT_SET_PCR(base, index, value) (BME_OR32(&PORT_PCR_REG(base, index), (uint32_t)(value)))
17248 #define PORT_SET_ISFR(base, value) (BME_OR32(&PORT_ISFR_REG(base), (uint32_t)(value)))
17927 #define RSIM_SET_CONTROL(base, value) (BME_OR32(&RSIM_CONTROL_REG(base), (uint32_t)(value)))
18299 #define RSIM_SET_ACTIVE_DELAY(base, value) (BME_OR32(&RSIM_ACTIVE_DELAY_REG(base), (uint32_t)(value…
18423 #define RSIM_SET_ANA_TEST(base, value) (BME_OR32(&RSIM_ANA_TEST_REG(base), (uint32_t)(value)))
18500 #define RTC_SET_TSR(base, value) (BME_OR32(&RTC_TSR_REG(base), (uint32_t)(value)))
18521 #define RTC_SET_TPR(base, value) (BME_OR32(&RTC_TPR_REG(base), (uint32_t)(value)))
18565 #define RTC_SET_TAR(base, value) (BME_OR32(&RTC_TAR_REG(base), (uint32_t)(value)))
18586 #define RTC_SET_TCR(base, value) (BME_OR32(&RTC_TCR_REG(base), (uint32_t)(value)))
18682 #define RTC_SET_CR(base, value)  (BME_OR32(&RTC_CR_REG(base), (uint32_t)(value)))
18909 #define RTC_SET_SR(base, value)  (BME_OR32(&RTC_SR_REG(base), (uint32_t)(value)))
19005 #define RTC_SET_LR(base, value)  (BME_OR32(&RTC_LR_REG(base), (uint32_t)(value)))
19107 #define RTC_SET_IER(base, value) (BME_OR32(&RTC_IER_REG(base), (uint32_t)(value)))
19256 #define SIM_SET_SOPT1(base, value) (BME_OR32(&SIM_SOPT1_REG(base), (uint32_t)(value)))
19330 #define SIM_SET_SOPT2(base, value) (BME_OR32(&SIM_SOPT2_REG(base), (uint32_t)(value)))
19422 #define SIM_SET_SOPT4(base, value) (BME_OR32(&SIM_SOPT4_REG(base), (uint32_t)(value)))
19550 #define SIM_SET_SOPT5(base, value) (BME_OR32(&SIM_SOPT5_REG(base), (uint32_t)(value)))
19632 #define SIM_SET_SOPT7(base, value) (BME_OR32(&SIM_SOPT7_REG(base), (uint32_t)(value)))
19875 #define SIM_SET_SCGC4(base, value) (BME_OR32(&SIM_SCGC4_REG(base), (uint32_t)(value)))
19984 #define SIM_SET_SCGC5(base, value) (BME_OR32(&SIM_SCGC5_REG(base), (uint32_t)(value)))
20230 #define SIM_SET_SCGC6(base, value) (BME_OR32(&SIM_SCGC6_REG(base), (uint32_t)(value)))
20485 #define SIM_SET_SCGC7(base, value) (BME_OR32(&SIM_SCGC7_REG(base), (uint32_t)(value)))
20532 #define SIM_SET_CLKDIV1(base, value) (BME_OR32(&SIM_CLKDIV1_REG(base), (uint32_t)(value)))
20622 #define SIM_SET_FCFG1(base, value) (BME_OR32(&SIM_FCFG1_REG(base), (uint32_t)(value)))
20831 #define SIM_SET_COPC(base, value) (BME_OR32(&SIM_COPC_REG(base), (uint32_t)(value)))
21389 #define SPI_SET_MCR(base, value) (BME_OR32(&SPI_MCR_REG(base), (uint32_t)(value)))
21714 #define SPI_SET_TCR(base, value) (BME_OR32(&SPI_TCR_REG(base), (uint32_t)(value)))
21761 #define SPI_SET_CTAR_SLAVE(base, index, value) (BME_OR32(&SPI_CTAR_SLAVE_REG(base, index), (uint32_…
21859 #define SPI_SET_CTAR(base, index, value) (BME_OR32(&SPI_CTAR_REG(base, index), (uint32_t)(value)))
22185 #define SPI_SET_SR(base, value)  (BME_OR32(&SPI_SR_REG(base), (uint32_t)(value)))
22416 #define SPI_SET_RSER(base, value) (BME_OR32(&SPI_RSER_REG(base), (uint32_t)(value)))
22608 #define SPI_SET_PUSHR(base, value) (BME_OR32(&SPI_PUSHR_REG(base), (uint32_t)(value)))
22763 #define SPI_SET_PUSHR_SLAVE(base, value) (BME_OR32(&SPI_PUSHR_SLAVE_REG(base), (uint32_t)(value)))
23119 #define TPM_SET_SC(base, value)  (BME_OR32(&TPM_SC_REG(base), (uint32_t)(value)))
23282 #define TPM_SET_CNT(base, value) (BME_OR32(&TPM_CNT_REG(base), (uint32_t)(value)))
23331 #define TPM_SET_MOD(base, value) (BME_OR32(&TPM_MOD_REG(base), (uint32_t)(value)))
23386 #define TPM_SET_CnSC(base, index, value) (BME_OR32(&TPM_CnSC_REG(base, index), (uint32_t)(value)))
23548 #define TPM_SET_CnV(base, index, value) (BME_OR32(&TPM_CnV_REG(base, index), (uint32_t)(value)))
23600 #define TPM_SET_STATUS(base, value) (BME_OR32(&TPM_STATUS_REG(base), (uint32_t)(value)))
23724 #define TPM_SET_COMBINE(base, value) (BME_OR32(&TPM_COMBINE_REG(base), (uint32_t)(value)))
23839 #define TPM_SET_FILTER(base, value) (BME_OR32(&TPM_FILTER_REG(base), (uint32_t)(value)))
23934 #define TPM_SET_QDCTRL(base, value) (BME_OR32(&TPM_QDCTRL_REG(base), (uint32_t)(value)))
24036 #define TPM_SET_CONF(base, value) (BME_OR32(&TPM_CONF_REG(base), (uint32_t)(value)))
24281 #define TRNG_SET_MCTL(base, value) (BME_OR32(&TRNG_MCTL_REG(base), (uint32_t)(value)))
24529 #define TRNG_SET_SCMISC(base, value) (BME_OR32(&TRNG_SCMISC_REG(base), (uint32_t)(value)))
24596 #define TRNG_SET_PKRRNG(base, value) (BME_OR32(&TRNG_PKRRNG_REG(base), (uint32_t)(value)))
24647 #define TRNG_SET_PKRMAX(base, value) (BME_OR32(&TRNG_PKRMAX_REG(base), (uint32_t)(value)))
24745 #define TRNG_SET_SDCTL(base, value) (BME_OR32(&TRNG_SDCTL_REG(base), (uint32_t)(value)))
24812 #define TRNG_SET_SBLIM(base, value) (BME_OR32(&TRNG_SBLIM_REG(base), (uint32_t)(value)))
24907 #define TRNG_SET_FRQMIN(base, value) (BME_OR32(&TRNG_FRQMIN_REG(base), (uint32_t)(value)))
24957 #define TRNG_SET_FRQMAX(base, value) (BME_OR32(&TRNG_FRQMAX_REG(base), (uint32_t)(value)))
25092 #define TRNG_SET_SCML(base, value) (BME_OR32(&TRNG_SCML_REG(base), (uint32_t)(value)))
25164 #define TRNG_SET_SCR1L(base, value) (BME_OR32(&TRNG_SCR1L_REG(base), (uint32_t)(value)))
25290 #define TRNG_SET_SCR2L(base, value) (BME_OR32(&TRNG_SCR2L_REG(base), (uint32_t)(value)))
25469 #define TRNG_SET_SCR3L(base, value) (BME_OR32(&TRNG_SCR3L_REG(base), (uint32_t)(value)))
25595 #define TRNG_SET_SCR4L(base, value) (BME_OR32(&TRNG_SCR4L_REG(base), (uint32_t)(value)))
25668 #define TRNG_SET_SCR5L(base, value) (BME_OR32(&TRNG_SCR5L_REG(base), (uint32_t)(value)))
25794 #define TRNG_SET_SCR6PL(base, value) (BME_OR32(&TRNG_SCR6PL_REG(base), (uint32_t)(value)))
26588 #define TRNG_SET_SEC_CFG(base, value) (BME_OR32(&TRNG_SEC_CFG_REG(base), (uint32_t)(value)))
26681 #define TRNG_SET_INT_CTRL(base, value) (BME_OR32(&TRNG_INT_CTRL_REG(base), (uint32_t)(value)))
26787 #define TRNG_SET_INT_MASK(base, value) (BME_OR32(&TRNG_INT_MASK_REG(base), (uint32_t)(value)))
26882 #define TRNG_SET_INT_STATUS(base, value) (BME_OR32(&TRNG_INT_STATUS_REG(base), (uint32_t)(value)))
27123 #define TSI_SET_GENCS(base, value) (BME_OR32(&TSI_GENCS_REG(base), (uint32_t)(value)))
27500 #define TSI_SET_DATA(base, value) (BME_OR32(&TSI_DATA_REG(base), (uint32_t)(value)))
27613 #define TSI_SET_TSHD(base, value) (BME_OR32(&TSI_TSHD_REG(base), (uint32_t)(value)))
27843 #define XCVR_SET_RX_DIG_CTRL(base, value) (BME_OR32(&XCVR_RX_DIG_CTRL_REG(base), (uint32_t)(value)))
28071 #define XCVR_SET_AGC_CTRL_0(base, value) (BME_OR32(&XCVR_AGC_CTRL_0_REG(base), (uint32_t)(value)))
28259 #define XCVR_SET_AGC_CTRL_1(base, value) (BME_OR32(&XCVR_AGC_CTRL_1_REG(base), (uint32_t)(value)))
28410 #define XCVR_SET_AGC_CTRL_2(base, value) (BME_OR32(&XCVR_AGC_CTRL_2_REG(base), (uint32_t)(value)))
28595 #define XCVR_SET_AGC_CTRL_3(base, value) (BME_OR32(&XCVR_AGC_CTRL_3_REG(base), (uint32_t)(value)))
28796 #define XCVR_SET_RSSI_CTRL_0(base, value) (BME_OR32(&XCVR_RSSI_CTRL_0_REG(base), (uint32_t)(value)))
28939 #define XCVR_SET_RSSI_CTRL_1(base, value) (BME_OR32(&XCVR_RSSI_CTRL_1_REG(base), (uint32_t)(value)))
29035 #define XCVR_SET_DCOC_CTRL_0(base, value) (BME_OR32(&XCVR_DCOC_CTRL_0_REG(base), (uint32_t)(value)))
29225 #define XCVR_SET_DCOC_CTRL_1(base, value) (BME_OR32(&XCVR_DCOC_CTRL_1_REG(base), (uint32_t)(value)))
29329 #define XCVR_SET_DCOC_CTRL_2(base, value) (BME_OR32(&XCVR_DCOC_CTRL_2_REG(base), (uint32_t)(value)))
29372 #define XCVR_SET_DCOC_CTRL_3(base, value) (BME_OR32(&XCVR_DCOC_CTRL_3_REG(base), (uint32_t)(value)))
29457 #define XCVR_SET_DCOC_CTRL_4(base, value) (BME_OR32(&XCVR_DCOC_CTRL_4_REG(base), (uint32_t)(value)))
29514 #define XCVR_SET_DCOC_CAL_GAIN(base, value) (BME_OR32(&XCVR_DCOC_CAL_GAIN_REG(base), (uint32_t)(val…
29755 #define XCVR_SET_DCOC_CAL_RCP(base, value) (BME_OR32(&XCVR_DCOC_CAL_RCP_REG(base), (uint32_t)(value…
29815 #define XCVR_SET_IQMC_CTRL(base, value) (BME_OR32(&XCVR_IQMC_CTRL_REG(base), (uint32_t)(value)))
29870 #define XCVR_SET_IQMC_CAL(base, value) (BME_OR32(&XCVR_IQMC_CAL_REG(base), (uint32_t)(value)))
29925 #define XCVR_SET_TCA_AGC_VAL_3_0(base, value) (BME_OR32(&XCVR_TCA_AGC_VAL_3_0_REG(base), (uint32_t)…
30010 #define XCVR_SET_TCA_AGC_VAL_7_4(base, value) (BME_OR32(&XCVR_TCA_AGC_VAL_7_4_REG(base), (uint32_t)…
30095 #define XCVR_SET_TCA_AGC_VAL_8(base, value) (BME_OR32(&XCVR_TCA_AGC_VAL_8_REG(base), (uint32_t)(val…
30135 #define XCVR_SET_BBF_RES_TUNE_VAL_7_0(base, value) (BME_OR32(&XCVR_BBF_RES_TUNE_VAL_7_0_REG(base), …
30280 #define XCVR_SET_BBF_RES_TUNE_VAL_10_8(base, value) (BME_OR32(&XCVR_BBF_RES_TUNE_VAL_10_8_REG(base)…
30350 #define XCVR_SET_TCA_AGC_LIN_VAL_2_0(base, value) (BME_OR32(&XCVR_TCA_AGC_LIN_VAL_2_0_REG(base), (u…
30422 #define XCVR_SET_TCA_AGC_LIN_VAL_5_3(base, value) (BME_OR32(&XCVR_TCA_AGC_LIN_VAL_5_3_REG(base), (u…
30495 #define XCVR_SET_TCA_AGC_LIN_VAL_8_6(base, value) (BME_OR32(&XCVR_TCA_AGC_LIN_VAL_8_6_REG(base), (u…
30568 #define XCVR_SET_BBF_RES_TUNE_LIN_VAL_3_0(base, value) (BME_OR32(&XCVR_BBF_RES_TUNE_LIN_VAL_3_0_REG…
30657 #define XCVR_SET_BBF_RES_TUNE_LIN_VAL_7_4(base, value) (BME_OR32(&XCVR_BBF_RES_TUNE_LIN_VAL_7_4_REG…
30746 #define XCVR_SET_BBF_RES_TUNE_LIN_VAL_10_8(base, value) (BME_OR32(&XCVR_BBF_RES_TUNE_LIN_VAL_10_8_R…
30819 #define XCVR_SET_AGC_GAIN_TBL_03_00(base, value) (BME_OR32(&XCVR_AGC_GAIN_TBL_03_00_REG(base), (uin…
30964 #define XCVR_SET_AGC_GAIN_TBL_07_04(base, value) (BME_OR32(&XCVR_AGC_GAIN_TBL_07_04_REG(base), (uin…
31109 #define XCVR_SET_AGC_GAIN_TBL_11_08(base, value) (BME_OR32(&XCVR_AGC_GAIN_TBL_11_08_REG(base), (uin…
31254 #define XCVR_SET_AGC_GAIN_TBL_15_12(base, value) (BME_OR32(&XCVR_AGC_GAIN_TBL_15_12_REG(base), (uin…
31399 #define XCVR_SET_AGC_GAIN_TBL_19_16(base, value) (BME_OR32(&XCVR_AGC_GAIN_TBL_19_16_REG(base), (uin…
31544 #define XCVR_SET_AGC_GAIN_TBL_23_20(base, value) (BME_OR32(&XCVR_AGC_GAIN_TBL_23_20_REG(base), (uin…
31689 #define XCVR_SET_AGC_GAIN_TBL_26_24(base, value) (BME_OR32(&XCVR_AGC_GAIN_TBL_26_24_REG(base), (uin…
31804 #define XCVR_SET_DCOC_OFFSET_(base, index, value) (BME_OR32(&XCVR_DCOC_OFFSET__REG(base, index), (u…
31897 #define XCVR_SET_DCOC_TZA_STEP_(base, index, value) (BME_OR32(&XCVR_DCOC_TZA_STEP__REG(base, index)…
32098 #define XCVR_SET_DCOC_CAL_IIR(base, value) (BME_OR32(&XCVR_DCOC_CAL_IIR_REG(base), (uint32_t)(value…
32233 #define XCVR_SET_RX_CHF_COEF(base, index, value) (BME_OR32(&XCVR_RX_CHF_COEF_REG(base, index), (uin…
32273 #define XCVR_SET_TX_DIG_CTRL(base, value) (BME_OR32(&XCVR_TX_DIG_CTRL_REG(base), (uint32_t)(value)))
32516 #define XCVR_SET_TX_DATA_PAD_PAT(base, value) (BME_OR32(&XCVR_TX_DATA_PAD_PAT_REG(base), (uint32_t)…
32603 #define XCVR_SET_TX_GFSK_MOD_CTRL(base, value) (BME_OR32(&XCVR_TX_GFSK_MOD_CTRL_REG(base), (uint32_…
32738 #define XCVR_SET_TX_GFSK_COEFF2(base, value) (BME_OR32(&XCVR_TX_GFSK_COEFF2_REG(base), (uint32_t)(v…
32764 #define XCVR_SET_TX_GFSK_COEFF1(base, value) (BME_OR32(&XCVR_TX_GFSK_COEFF1_REG(base), (uint32_t)(v…
32785 #define XCVR_SET_TX_FSK_MOD_SCALE(base, value) (BME_OR32(&XCVR_TX_FSK_MOD_SCALE_REG(base), (uint32_…
32856 #define XCVR_SET_TX_DFT_MOD_PAT(base, value) (BME_OR32(&XCVR_TX_DFT_MOD_PAT_REG(base), (uint32_t)(v…
32882 #define XCVR_SET_TX_DFT_TONE_0_1(base, value) (BME_OR32(&XCVR_TX_DFT_TONE_0_1_REG(base), (uint32_t)…
32950 #define XCVR_SET_TX_DFT_TONE_2_3(base, value) (BME_OR32(&XCVR_TX_DFT_TONE_2_3_REG(base), (uint32_t)…
33013 #define XCVR_SET_PLL_MOD_OVRD(base, value) (BME_OR32(&XCVR_PLL_MOD_OVRD_REG(base), (uint32_t)(value…
33135 #define XCVR_SET_PLL_CHAN_MAP(base, value) (BME_OR32(&XCVR_PLL_CHAN_MAP_REG(base), (uint32_t)(value…
33262 #define XCVR_SET_PLL_LOCK_DETECT(base, value) (BME_OR32(&XCVR_PLL_LOCK_DETECT_REG(base), (uint32_t)…
33481 #define XCVR_SET_PLL_HP_MOD_CTRL(base, value) (BME_OR32(&XCVR_PLL_HP_MOD_CTRL_REG(base), (uint32_t)…
33669 #define XCVR_SET_PLL_HPM_CAL_CTRL(base, value) (BME_OR32(&XCVR_PLL_HPM_CAL_CTRL_REG(base), (uint32_…
33777 #define XCVR_SET_PLL_LD_HPM_CAL1(base, value) (BME_OR32(&XCVR_PLL_LD_HPM_CAL1_REG(base), (uint32_t)…
33881 #define XCVR_SET_PLL_LD_HPM_CAL2(base, value) (BME_OR32(&XCVR_PLL_LD_HPM_CAL2_REG(base), (uint32_t)…
33950 #define XCVR_SET_PLL_HPM_SDM_FRACTION(base, value) (BME_OR32(&XCVR_PLL_HPM_SDM_FRACTION_REG(base), …
34008 #define XCVR_SET_PLL_LP_MOD_CTRL(base, value) (BME_OR32(&XCVR_PLL_LP_MOD_CTRL_REG(base), (uint32_t)…
34223 #define XCVR_SET_PLL_LP_SDM_CTRL1(base, value) (BME_OR32(&XCVR_PLL_LP_SDM_CTRL1_REG(base), (uint32_…
34296 #define XCVR_SET_PLL_LP_SDM_CTRL2(base, value) (BME_OR32(&XCVR_PLL_LP_SDM_CTRL2_REG(base), (uint32_…
34339 #define XCVR_SET_PLL_LP_SDM_CTRL3(base, value) (BME_OR32(&XCVR_PLL_LP_SDM_CTRL3_REG(base), (uint32_…
34451 #define XCVR_SET_PLL_DELAY_MATCH(base, value) (BME_OR32(&XCVR_PLL_DELAY_MATCH_REG(base), (uint32_t)…
34527 #define XCVR_SET_PLL_CTUNE_CTRL(base, value) (BME_OR32(&XCVR_PLL_CTUNE_CTRL_REG(base), (uint32_t)(v…
34847 #define XCVR_SET_CTRL(base, value) (BME_OR32(&XCVR_CTRL_REG(base), (uint32_t)(value)))
35089 #define XCVR_SET_OVERWRITE_VER(base, value) (BME_OR32(&XCVR_OVERWRITE_VER_REG(base), (uint32_t)(val…
35136 #define XCVR_SET_DMA_CTRL(base, value) (BME_OR32(&XCVR_DMA_CTRL_REG(base), (uint32_t)(value)))
35266 #define XCVR_SET_DTEST_CTRL(base, value) (BME_OR32(&XCVR_DTEST_CTRL_REG(base), (uint32_t)(value)))
35490 #define XCVR_SET_PB_CTRL(base, value) (BME_OR32(&XCVR_PB_CTRL_REG(base), (uint32_t)(value)))
35535 #define XCVR_SET_TSM_CTRL(base, value) (BME_OR32(&XCVR_TSM_CTRL_REG(base), (uint32_t)(value)))
35746 #define XCVR_SET_END_OF_SEQ(base, value) (BME_OR32(&XCVR_END_OF_SEQ_REG(base), (uint32_t)(value)))
35845 #define XCVR_SET_TSM_OVRD0(base, value) (BME_OR32(&XCVR_TSM_OVRD0_REG(base), (uint32_t)(value)))
36421 #define XCVR_SET_TSM_OVRD1(base, value) (BME_OR32(&XCVR_TSM_OVRD1_REG(base), (uint32_t)(value)))
36985 #define XCVR_SET_TSM_OVRD2(base, value) (BME_OR32(&XCVR_TSM_OVRD2_REG(base), (uint32_t)(value)))
37548 #define XCVR_SET_TSM_OVRD3(base, value) (BME_OR32(&XCVR_TSM_OVRD3_REG(base), (uint32_t)(value)))
37778 #define XCVR_SET_PA_POWER(base, value) (BME_OR32(&XCVR_PA_POWER_REG(base), (uint32_t)(value)))
37818 #define XCVR_SET_PA_BIAS_TBL0(base, value) (BME_OR32(&XCVR_PA_BIAS_TBL0_REG(base), (uint32_t)(value…
37921 #define XCVR_SET_PA_BIAS_TBL1(base, value) (BME_OR32(&XCVR_PA_BIAS_TBL1_REG(base), (uint32_t)(value…
38022 #define XCVR_SET_RECYCLE_COUNT(base, value) (BME_OR32(&XCVR_RECYCLE_COUNT_REG(base), (uint32_t)(val…
38103 #define XCVR_SET_TSM_TIMING00(base, value) (BME_OR32(&XCVR_TSM_TIMING00_REG(base), (uint32_t)(value…
38196 #define XCVR_SET_TSM_TIMING01(base, value) (BME_OR32(&XCVR_TSM_TIMING01_REG(base), (uint32_t)(value…
38289 #define XCVR_SET_TSM_TIMING02(base, value) (BME_OR32(&XCVR_TSM_TIMING02_REG(base), (uint32_t)(value…
38382 #define XCVR_SET_TSM_TIMING03(base, value) (BME_OR32(&XCVR_TSM_TIMING03_REG(base), (uint32_t)(value…
38475 #define XCVR_SET_TSM_TIMING04(base, value) (BME_OR32(&XCVR_TSM_TIMING04_REG(base), (uint32_t)(value…
38536 #define XCVR_SET_TSM_TIMING05(base, value) (BME_OR32(&XCVR_TSM_TIMING05_REG(base), (uint32_t)(value…
38629 #define XCVR_SET_TSM_TIMING06(base, value) (BME_OR32(&XCVR_TSM_TIMING06_REG(base), (uint32_t)(value…
38690 #define XCVR_SET_TSM_TIMING07(base, value) (BME_OR32(&XCVR_TSM_TIMING07_REG(base), (uint32_t)(value…
38787 #define XCVR_SET_TSM_TIMING08(base, value) (BME_OR32(&XCVR_TSM_TIMING08_REG(base), (uint32_t)(value…
38884 #define XCVR_SET_TSM_TIMING09(base, value) (BME_OR32(&XCVR_TSM_TIMING09_REG(base), (uint32_t)(value…
38977 #define XCVR_SET_TSM_TIMING10(base, value) (BME_OR32(&XCVR_TSM_TIMING10_REG(base), (uint32_t)(value…
39038 #define XCVR_SET_TSM_TIMING11(base, value) (BME_OR32(&XCVR_TSM_TIMING11_REG(base), (uint32_t)(value…
39099 #define XCVR_SET_TSM_TIMING12(base, value) (BME_OR32(&XCVR_TSM_TIMING12_REG(base), (uint32_t)(value…
39160 #define XCVR_SET_TSM_TIMING13(base, value) (BME_OR32(&XCVR_TSM_TIMING13_REG(base), (uint32_t)(value…
39253 #define XCVR_SET_TSM_TIMING14(base, value) (BME_OR32(&XCVR_TSM_TIMING14_REG(base), (uint32_t)(value…
39316 #define XCVR_SET_TSM_TIMING15(base, value) (BME_OR32(&XCVR_TSM_TIMING15_REG(base), (uint32_t)(value…
39379 #define XCVR_SET_TSM_TIMING16(base, value) (BME_OR32(&XCVR_TSM_TIMING16_REG(base), (uint32_t)(value…
39476 #define XCVR_SET_TSM_TIMING17(base, value) (BME_OR32(&XCVR_TSM_TIMING17_REG(base), (uint32_t)(value…
39569 #define XCVR_SET_TSM_TIMING18(base, value) (BME_OR32(&XCVR_TSM_TIMING18_REG(base), (uint32_t)(value…
39630 #define XCVR_SET_TSM_TIMING19(base, value) (BME_OR32(&XCVR_TSM_TIMING19_REG(base), (uint32_t)(value…
39691 #define XCVR_SET_TSM_TIMING20(base, value) (BME_OR32(&XCVR_TSM_TIMING20_REG(base), (uint32_t)(value…
39752 #define XCVR_SET_TSM_TIMING21(base, value) (BME_OR32(&XCVR_TSM_TIMING21_REG(base), (uint32_t)(value…
39813 #define XCVR_SET_TSM_TIMING22(base, value) (BME_OR32(&XCVR_TSM_TIMING22_REG(base), (uint32_t)(value…
39874 #define XCVR_SET_TSM_TIMING23(base, value) (BME_OR32(&XCVR_TSM_TIMING23_REG(base), (uint32_t)(value…
39935 #define XCVR_SET_TSM_TIMING24(base, value) (BME_OR32(&XCVR_TSM_TIMING24_REG(base), (uint32_t)(value…
39996 #define XCVR_SET_TSM_TIMING25(base, value) (BME_OR32(&XCVR_TSM_TIMING25_REG(base), (uint32_t)(value…
40057 #define XCVR_SET_TSM_TIMING26(base, value) (BME_OR32(&XCVR_TSM_TIMING26_REG(base), (uint32_t)(value…
40150 #define XCVR_SET_TSM_TIMING27(base, value) (BME_OR32(&XCVR_TSM_TIMING27_REG(base), (uint32_t)(value…
40211 #define XCVR_SET_TSM_TIMING28(base, value) (BME_OR32(&XCVR_TSM_TIMING28_REG(base), (uint32_t)(value…
40272 #define XCVR_SET_TSM_TIMING29(base, value) (BME_OR32(&XCVR_TSM_TIMING29_REG(base), (uint32_t)(value…
40333 #define XCVR_SET_TSM_TIMING30(base, value) (BME_OR32(&XCVR_TSM_TIMING30_REG(base), (uint32_t)(value…
40426 #define XCVR_SET_TSM_TIMING31(base, value) (BME_OR32(&XCVR_TSM_TIMING31_REG(base), (uint32_t)(value…
40487 #define XCVR_SET_TSM_TIMING32(base, value) (BME_OR32(&XCVR_TSM_TIMING32_REG(base), (uint32_t)(value…
40548 #define XCVR_SET_TSM_TIMING33(base, value) (BME_OR32(&XCVR_TSM_TIMING33_REG(base), (uint32_t)(value…
40609 #define XCVR_SET_TSM_TIMING34(base, value) (BME_OR32(&XCVR_TSM_TIMING34_REG(base), (uint32_t)(value…
40702 #define XCVR_SET_TSM_TIMING35(base, value) (BME_OR32(&XCVR_TSM_TIMING35_REG(base), (uint32_t)(value…
40795 #define XCVR_SET_TSM_TIMING36(base, value) (BME_OR32(&XCVR_TSM_TIMING36_REG(base), (uint32_t)(value…
40888 #define XCVR_SET_TSM_TIMING37(base, value) (BME_OR32(&XCVR_TSM_TIMING37_REG(base), (uint32_t)(value…
40981 #define XCVR_SET_TSM_TIMING38(base, value) (BME_OR32(&XCVR_TSM_TIMING38_REG(base), (uint32_t)(value…
41074 #define XCVR_SET_TSM_TIMING39(base, value) (BME_OR32(&XCVR_TSM_TIMING39_REG(base), (uint32_t)(value…
41167 #define XCVR_SET_TSM_TIMING40(base, value) (BME_OR32(&XCVR_TSM_TIMING40_REG(base), (uint32_t)(value…
41260 #define XCVR_SET_TSM_TIMING41(base, value) (BME_OR32(&XCVR_TSM_TIMING41_REG(base), (uint32_t)(value…
41353 #define XCVR_SET_TSM_TIMING42(base, value) (BME_OR32(&XCVR_TSM_TIMING42_REG(base), (uint32_t)(value…
41446 #define XCVR_SET_TSM_TIMING43(base, value) (BME_OR32(&XCVR_TSM_TIMING43_REG(base), (uint32_t)(value…
41535 #define XCVR_SET_CORR_CTRL(base, value) (BME_OR32(&XCVR_CORR_CTRL_REG(base), (uint32_t)(value)))
41632 #define XCVR_SET_PN_TYPE(base, value) (BME_OR32(&XCVR_PN_TYPE_REG(base), (uint32_t)(value)))
41689 #define XCVR_SET_PN_CODE(base, value) (BME_OR32(&XCVR_PN_CODE_REG(base), (uint32_t)(value)))
41744 #define XCVR_SET_SYNC_CTRL(base, value) (BME_OR32(&XCVR_SYNC_CTRL_REG(base), (uint32_t)(value)))
41804 #define XCVR_SET_SNF_THR(base, value) (BME_OR32(&XCVR_SNF_THR_REG(base), (uint32_t)(value)))
41846 #define XCVR_SET_FAD_THR(base, value) (BME_OR32(&XCVR_FAD_THR_REG(base), (uint32_t)(value)))
41886 #define XCVR_SET_ZBDEM_AFC(base, value) (BME_OR32(&XCVR_ZBDEM_AFC_REG(base), (uint32_t)(value)))
41954 #define XCVR_SET_LPPS_CTRL(base, value) (BME_OR32(&XCVR_LPPS_CTRL_REG(base), (uint32_t)(value)))
42131 #define XCVR_SET_ADC_CTRL(base, value) (BME_OR32(&XCVR_ADC_CTRL_REG(base), (uint32_t)(value)))
42239 #define XCVR_SET_ADC_TUNE(base, value) (BME_OR32(&XCVR_ADC_TUNE_REG(base), (uint32_t)(value)))
42328 #define XCVR_SET_ADC_ADJ(base, value) (BME_OR32(&XCVR_ADC_ADJ_REG(base), (uint32_t)(value)))
42447 #define XCVR_SET_ADC_REGS(base, value) (BME_OR32(&XCVR_ADC_REGS_REG(base), (uint32_t)(value)))
42585 #define XCVR_SET_ADC_TRIMS(base, value) (BME_OR32(&XCVR_ADC_TRIMS_REG(base), (uint32_t)(value)))
42660 #define XCVR_SET_ADC_TEST_CTRL(base, value) (BME_OR32(&XCVR_ADC_TEST_CTRL_REG(base), (uint32_t)(val…
42780 #define XCVR_SET_BBF_CTRL(base, value) (BME_OR32(&XCVR_BBF_CTRL_REG(base), (uint32_t)(value)))
42941 #define XCVR_SET_RX_ANA_CTRL(base, value) (BME_OR32(&XCVR_RX_ANA_CTRL_REG(base), (uint32_t)(value)))
43021 #define XCVR_SET_XTAL_CTRL(base, value) (BME_OR32(&XCVR_XTAL_CTRL_REG(base), (uint32_t)(value)))
43191 #define XCVR_SET_XTAL_CTRL2(base, value) (BME_OR32(&XCVR_XTAL_CTRL2_REG(base), (uint32_t)(value)))
43395 #define XCVR_SET_BGAP_CTRL(base, value) (BME_OR32(&XCVR_BGAP_CTRL_REG(base), (uint32_t)(value)))
43483 #define XCVR_SET_PLL_CTRL(base, value) (BME_OR32(&XCVR_PLL_CTRL_REG(base), (uint32_t)(value)))
43627 #define XCVR_SET_PLL_CTRL2(base, value) (BME_OR32(&XCVR_PLL_CTRL2_REG(base), (uint32_t)(value)))
43720 #define XCVR_SET_PLL_TEST_CTRL(base, value) (BME_OR32(&XCVR_PLL_TEST_CTRL_REG(base), (uint32_t)(val…
43842 #define XCVR_SET_QGEN_CTRL(base, value) (BME_OR32(&XCVR_QGEN_CTRL_REG(base), (uint32_t)(value)))
43921 #define XCVR_SET_TCA_CTRL(base, value) (BME_OR32(&XCVR_TCA_CTRL_REG(base), (uint32_t)(value)))
44030 #define XCVR_SET_TZA_CTRL(base, value) (BME_OR32(&XCVR_TZA_CTRL_REG(base), (uint32_t)(value)))
44133 #define XCVR_SET_TX_ANA_CTRL(base, value) (BME_OR32(&XCVR_TX_ANA_CTRL_REG(base), (uint32_t)(value)))
44174 #define XCVR_SET_ANA_SPARE(base, value) (BME_OR32(&XCVR_ANA_SPARE_REG(base), (uint32_t)(value)))
44324 #define ZLL_SET_IRQSTS(base, value) (BME_OR32(&ZLL_IRQSTS_REG(base), (uint32_t)(value)))
44722 #define ZLL_SET_PHY_CTRL(base, value) (BME_OR32(&ZLL_PHY_CTRL_REG(base), (uint32_t)(value)))
45308 #define ZLL_SET_T1CMP(base, value) (BME_OR32(&ZLL_T1CMP_REG(base), (uint32_t)(value)))
45349 #define ZLL_SET_T2CMP(base, value) (BME_OR32(&ZLL_T2CMP_REG(base), (uint32_t)(value)))
45390 #define ZLL_SET_T2PRIMECMP(base, value) (BME_OR32(&ZLL_T2PRIMECMP_REG(base), (uint32_t)(value)))
45431 #define ZLL_SET_T3CMP(base, value) (BME_OR32(&ZLL_T3CMP_REG(base), (uint32_t)(value)))
45472 #define ZLL_SET_T4CMP(base, value) (BME_OR32(&ZLL_T4CMP_REG(base), (uint32_t)(value)))
45512 #define ZLL_SET_PA_PWR(base, value) (BME_OR32(&ZLL_PA_PWR_REG(base), (uint32_t)(value)))
45554 #define ZLL_SET_CHANNEL_NUM0(base, value) (BME_OR32(&ZLL_CHANNEL_NUM0_REG(base), (uint32_t)(value)))
45647 #define ZLL_SET_MACSHORTADDRS0(base, value) (BME_OR32(&ZLL_MACSHORTADDRS0_REG(base), (uint32_t)(val…
45714 #define ZLL_SET_MACLONGADDRS0_LSB(base, value) (BME_OR32(&ZLL_MACLONGADDRS0_LSB_REG(base), (uint32_…
45739 #define ZLL_SET_MACLONGADDRS0_MSB(base, value) (BME_OR32(&ZLL_MACLONGADDRS0_MSB_REG(base), (uint32_…
45760 #define ZLL_SET_RX_FRAME_FILTER(base, value) (BME_OR32(&ZLL_RX_FRAME_FILTER_REG(base), (uint32_t)(v…
45914 #define ZLL_SET_CCA_LQI_CTRL(base, value) (BME_OR32(&ZLL_CCA_LQI_CTRL_REG(base), (uint32_t)(value)))
45990 #define ZLL_SET_CCA2_CTRL(base, value) (BME_OR32(&ZLL_CCA2_CTRL_REG(base), (uint32_t)(value)))
46067 #define ZLL_SET_FAD_CTRL(base, value) (BME_OR32(&ZLL_FAD_CTRL_REG(base), (uint32_t)(value)))
46233 #define ZLL_SET_SNF_CTRL(base, value) (BME_OR32(&ZLL_SNF_CTRL_REG(base), (uint32_t)(value)))
46276 #define ZLL_SET_BSM_CTRL(base, value) (BME_OR32(&ZLL_BSM_CTRL_REG(base), (uint32_t)(value)))
46318 #define ZLL_SET_MACSHORTADDRS1(base, value) (BME_OR32(&ZLL_MACSHORTADDRS1_REG(base), (uint32_t)(val…
46385 #define ZLL_SET_MACLONGADDRS1_LSB(base, value) (BME_OR32(&ZLL_MACLONGADDRS1_LSB_REG(base), (uint32_…
46410 #define ZLL_SET_MACLONGADDRS1_MSB(base, value) (BME_OR32(&ZLL_MACLONGADDRS1_MSB_REG(base), (uint32_…
46431 #define ZLL_SET_DUAL_PAN_CTRL(base, value) (BME_OR32(&ZLL_DUAL_PAN_CTRL_REG(base), (uint32_t)(value…
46667 #define ZLL_SET_CHANNEL_NUM1(base, value) (BME_OR32(&ZLL_CHANNEL_NUM1_REG(base), (uint32_t)(value)))
46707 #define ZLL_SET_SAM_CTRL(base, value) (BME_OR32(&ZLL_SAM_CTRL_REG(base), (uint32_t)(value)))
46841 #define ZLL_SET_SAM_TABLE(base, value) (BME_OR32(&ZLL_SAM_TABLE_REG(base), (uint32_t)(value)))
47170 #define ZLL_SET_SEQ_CTRL_STS(base, value) (BME_OR32(&ZLL_SEQ_CTRL_STS_REG(base), (uint32_t)(value)))
47462 #define ZLL_SET_ACKDELAY(base, value) (BME_OR32(&ZLL_ACKDELAY_REG(base), (uint32_t)(value)))
47528 #define ZLL_SET_FILTERFAIL_CODE(base, value) (BME_OR32(&ZLL_FILTERFAIL_CODE_REG(base), (uint32_t)(v…
47599 #define ZLL_SET_RX_WTR_MARK(base, value) (BME_OR32(&ZLL_RX_WTR_MARK_REG(base), (uint32_t)(value)))
47646 #define ZLL_SET_SLOT_PRELOAD(base, value) (BME_OR32(&ZLL_SLOT_PRELOAD_REG(base), (uint32_t)(value)))
47854 #define ZLL_SET_TMR_PRESCALE(base, value) (BME_OR32(&ZLL_TMR_PRESCALE_REG(base), (uint32_t)(value)))
47919 #define ZLL_SET_LENIENCY_LSB(base, value) (BME_OR32(&ZLL_LENIENCY_LSB_REG(base), (uint32_t)(value)))
47954 #define ZLL_SET_LENIENCY_MSB(base, value) (BME_OR32(&ZLL_LENIENCY_MSB_REG(base), (uint32_t)(value)))
48042 #define ZLL_SET_PKT_BUFFER(base, index, value) (BME_OR32(&ZLL_PKT_BUFFER_REG(base, index), (uint32_…