Lines Matching refs:BME_BFI32

243 #define ADC_BWR_SC1_ADCH(base, index, value) (BME_BFI32(&ADC_SC1_REG(base, index), ((uint32_t)(valu…
264 #define ADC_BWR_SC1_DIFF(base, index, value) (BME_BFI32(&ADC_SC1_REG(base, index), ((uint32_t)(valu…
284 #define ADC_BWR_SC1_AIEN(base, index, value) (BME_BFI32(&ADC_SC1_REG(base, index), ((uint32_t)(valu…
362 #define ADC_BWR_CFG1_ADICLK(base, value) (BME_BFI32(&ADC_CFG1_REG(base), ((uint32_t)(value) << ADC_…
387 #define ADC_BWR_CFG1_MODE(base, value) (BME_BFI32(&ADC_CFG1_REG(base), ((uint32_t)(value) << ADC_CF…
412 #define ADC_BWR_CFG1_ADLSMP(base, value) (BME_BFI32(&ADC_CFG1_REG(base), ((uint32_t)(value) << ADC_…
433 #define ADC_BWR_CFG1_ADIV(base, value) (BME_BFI32(&ADC_CFG1_REG(base), ((uint32_t)(value) << ADC_CF…
454 #define ADC_BWR_CFG1_ADLPC(base, value) (BME_BFI32(&ADC_CFG1_REG(base), ((uint32_t)(value) << ADC_C…
509 #define ADC_BWR_CFG2_ADLSTS(base, value) (BME_BFI32(&ADC_CFG2_REG(base), ((uint32_t)(value) << ADC_…
531 #define ADC_BWR_CFG2_ADHSC(base, value) (BME_BFI32(&ADC_CFG2_REG(base), ((uint32_t)(value) << ADC_C…
558 #define ADC_BWR_CFG2_ADACKEN(base, value) (BME_BFI32(&ADC_CFG2_REG(base), ((uint32_t)(value) << ADC…
577 #define ADC_BWR_CFG2_MUXSEL(base, value) (BME_BFI32(&ADC_CFG2_REG(base), ((uint32_t)(value) << ADC_…
685 #define ADC_BWR_CV1_CV(base, value) (BME_BFI32(&ADC_CV1_REG(base), ((uint32_t)(value) << ADC_CV1_CV…
732 #define ADC_BWR_CV2_CV(base, value) (BME_BFI32(&ADC_CV2_REG(base), ((uint32_t)(value) << ADC_CV2_CV…
787 #define ADC_BWR_SC2_REFSEL(base, value) (BME_BFI32(&ADC_SC2_REG(base), ((uint32_t)(value) << ADC_SC…
805 #define ADC_BWR_SC2_DMAEN(base, value) (BME_BFI32(&ADC_SC2_REG(base), ((uint32_t)(value) << ADC_SC2…
827 #define ADC_BWR_SC2_ACREN(base, value) (BME_BFI32(&ADC_SC2_REG(base), ((uint32_t)(value) << ADC_SC2…
851 #define ADC_BWR_SC2_ACFGT(base, value) (BME_BFI32(&ADC_SC2_REG(base), ((uint32_t)(value) << ADC_SC2…
870 #define ADC_BWR_SC2_ACFE(base, value) (BME_BFI32(&ADC_SC2_REG(base), ((uint32_t)(value) << ADC_SC2_…
893 #define ADC_BWR_SC2_ADTRG(base, value) (BME_BFI32(&ADC_SC2_REG(base), ((uint32_t)(value) << ADC_SC2…
960 #define ADC_BWR_SC3_AVGS(base, value) (BME_BFI32(&ADC_SC3_REG(base), ((uint32_t)(value) << ADC_SC3_…
979 #define ADC_BWR_SC3_AVGE(base, value) (BME_BFI32(&ADC_SC3_REG(base), ((uint32_t)(value) << ADC_SC3_…
1000 #define ADC_BWR_SC3_ADCO(base, value) (BME_BFI32(&ADC_SC3_REG(base), ((uint32_t)(value) << ADC_SC3_…
1021 #define ADC_BWR_SC3_CALF(base, value) (BME_BFI32(&ADC_SC3_REG(base), ((uint32_t)(value) << ADC_SC3_…
1041 #define ADC_BWR_SC3_CAL(base, value) (BME_BFI32(&ADC_SC3_REG(base), ((uint32_t)(value) << ADC_SC3_C…
1110 #define ADC_BWR_OFS_OFS(base, value) (BME_BFI32(&ADC_OFS_REG(base), ((uint32_t)(value) << ADC_OFS_O…
1162 #define ADC_BWR_PG_PG(base, value) (BME_BFI32(&ADC_PG_REG(base), ((uint32_t)(value) << ADC_PG_PG_SH…
1212 #define ADC_BWR_MG_MG(base, value) (BME_BFI32(&ADC_MG_REG(base), ((uint32_t)(value) << ADC_MG_MG_SH…
1270 #define ADC_BWR_CLPD_CLPD(base, value) (BME_BFI32(&ADC_CLPD_REG(base), ((uint32_t)(value) << ADC_CL…
1312 #define ADC_BWR_CLPS_CLPS(base, value) (BME_BFI32(&ADC_CLPS_REG(base), ((uint32_t)(value) << ADC_CL…
1354 #define ADC_BWR_CLP4_CLP4(base, value) (BME_BFI32(&ADC_CLP4_REG(base), ((uint32_t)(value) << ADC_CL…
1396 #define ADC_BWR_CLP3_CLP3(base, value) (BME_BFI32(&ADC_CLP3_REG(base), ((uint32_t)(value) << ADC_CL…
1438 #define ADC_BWR_CLP2_CLP2(base, value) (BME_BFI32(&ADC_CLP2_REG(base), ((uint32_t)(value) << ADC_CL…
1480 #define ADC_BWR_CLP1_CLP1(base, value) (BME_BFI32(&ADC_CLP1_REG(base), ((uint32_t)(value) << ADC_CL…
1522 #define ADC_BWR_CLP0_CLP0(base, value) (BME_BFI32(&ADC_CLP0_REG(base), ((uint32_t)(value) << ADC_CL…
1580 #define ADC_BWR_CLMD_CLMD(base, value) (BME_BFI32(&ADC_CLMD_REG(base), ((uint32_t)(value) << ADC_CL…
1622 #define ADC_BWR_CLMS_CLMS(base, value) (BME_BFI32(&ADC_CLMS_REG(base), ((uint32_t)(value) << ADC_CL…
1664 #define ADC_BWR_CLM4_CLM4(base, value) (BME_BFI32(&ADC_CLM4_REG(base), ((uint32_t)(value) << ADC_CL…
1706 #define ADC_BWR_CLM3_CLM3(base, value) (BME_BFI32(&ADC_CLM3_REG(base), ((uint32_t)(value) << ADC_CL…
1748 #define ADC_BWR_CLM2_CLM2(base, value) (BME_BFI32(&ADC_CLM2_REG(base), ((uint32_t)(value) << ADC_CL…
1790 #define ADC_BWR_CLM1_CLM1(base, value) (BME_BFI32(&ADC_CLM1_REG(base), ((uint32_t)(value) << ADC_CL…
1832 #define ADC_BWR_CLM0_CLM0(base, value) (BME_BFI32(&ADC_CLM0_REG(base), ((uint32_t)(value) << ADC_CL…
3727 #define DCDC_BWR_REG0_DCDC_DISABLE_AUTO_CLK_SWITCH(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((…
3742 #define DCDC_BWR_REG0_DCDC_SEL_CLK(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32_t)(value)…
3758 #define DCDC_BWR_REG0_DCDC_PWD_OSC_INT(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32_t)(va…
3774 #define DCDC_BWR_REG0_DCDC_LP_DF_CMP_ENABLE(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32_…
3790 #define DCDC_BWR_REG0_DCDC_VBAT_DIV_CTRL(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32_t)(…
3812 #define DCDC_BWR_REG0_DCDC_LP_STATE_HYS_L(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32_t)…
3834 #define DCDC_BWR_REG0_DCDC_LP_STATE_HYS_H(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32_t)…
3849 #define DCDC_BWR_REG0_HYST_LP_COMP_ADJ(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32_t)(va…
3864 #define DCDC_BWR_REG0_HYST_LP_CMP_DISABLE(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32_t)…
3879 #define DCDC_BWR_REG0_OFFSET_RSNS_LP_ADJ(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32_t)(…
3894 #define DCDC_BWR_REG0_OFFSET_RSNS_LP_DISABLE(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32…
3909 #define DCDC_BWR_REG0_DCDC_LESS_I(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32_t)(value) …
3924 #define DCDC_BWR_REG0_PWD_CMP_OFFSET(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32_t)(valu…
3939 #define DCDC_BWR_REG0_DCDC_XTALOK_DISABLE(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32_t)…
3966 #define DCDC_BWR_REG0_VLPS_CONFIG_DCDC_HP(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32_t)…
3983 #define DCDC_BWR_REG0_VLPR_VLPW_CONFIG_DCDC_HP(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint…
4039 #define DCDC_BWR_REG1_POSLIMIT_BUCK_IN(base, value) (BME_BFI32(&DCDC_REG1_REG(base), ((uint32_t)(va…
4056 #define DCDC_BWR_REG1_POSLIMIT_BOOST_IN(base, value) (BME_BFI32(&DCDC_REG1_REG(base), ((uint32_t)(v…
4072 #define DCDC_BWR_REG1_DCDC_LOOPCTRL_CM_HST_THRESH(base, value) (BME_BFI32(&DCDC_REG1_REG(base), ((u…
4088 #define DCDC_BWR_REG1_DCDC_LOOPCTRL_DF_HST_THRESH(base, value) (BME_BFI32(&DCDC_REG1_REG(base), ((u…
4104 #define DCDC_BWR_REG1_DCDC_LOOPCTRL_EN_CM_HYST(base, value) (BME_BFI32(&DCDC_REG1_REG(base), ((uint…
4120 #define DCDC_BWR_REG1_DCDC_LOOPCTRL_EN_DF_HYST(base, value) (BME_BFI32(&DCDC_REG1_REG(base), ((uint…
4162 #define DCDC_BWR_REG2_DCDC_LOOPCTRL_DC_C(base, value) (BME_BFI32(&DCDC_REG2_REG(base), ((uint32_t)(…
4181 #define DCDC_BWR_REG2_DCDC_LOOPCTRL_DC_FF(base, value) (BME_BFI32(&DCDC_REG2_REG(base), ((uint32_t)…
4197 #define DCDC_BWR_REG2_DCDC_LOOPCTRL_HYST_SIGN(base, value) (BME_BFI32(&DCDC_REG2_REG(base), ((uint3…
4214 #define DCDC_BWR_REG2_DCDC_LOOPCTRL_TOGGLE_DIF(base, value) (BME_BFI32(&DCDC_REG2_REG(base), ((uint…
4231 #define DCDC_BWR_REG2_DCDC_BATTMONITOR_EN_BATADJ(base, value) (BME_BFI32(&DCDC_REG2_REG(base), ((ui…
4248 #define DCDC_BWR_REG2_DCDC_BATTMONITOR_BATT_VAL(base, value) (BME_BFI32(&DCDC_REG2_REG(base), ((uin…
4297 #define DCDC_BWR_REG3_DCDC_VDD1P8CTRL_TRG(base, value) (BME_BFI32(&DCDC_REG3_REG(base), ((uint32_t)…
4317 #define DCDC_BWR_REG3_DCDC_VDD1P45CTRL_TRG_BUCK(base, value) (BME_BFI32(&DCDC_REG3_REG(base), ((uin…
4342 #define DCDC_BWR_REG3_DCDC_VDD1P45CTRL_TRG_BOOST(base, value) (BME_BFI32(&DCDC_REG3_REG(base), ((ui…
4358 #define DCDC_BWR_REG3_DCDC_VDD1P45CTRL_ADJTN(base, value) (BME_BFI32(&DCDC_REG3_REG(base), ((uint32…
4373 #define DCDC_BWR_REG3_DCDC_MINPWR_DC_HALFCLK_LIMP(base, value) (BME_BFI32(&DCDC_REG3_REG(base), ((u…
4388 #define DCDC_BWR_REG3_DCDC_MINPWR_DOUBLE_FETS_LIMP(base, value) (BME_BFI32(&DCDC_REG3_REG(base), ((…
4403 #define DCDC_BWR_REG3_DCDC_MINPWR_HALF_FETS_LIMP(base, value) (BME_BFI32(&DCDC_REG3_REG(base), ((ui…
4418 #define DCDC_BWR_REG3_DCDC_MINPWR_DC_HALFCLK(base, value) (BME_BFI32(&DCDC_REG3_REG(base), ((uint32…
4433 #define DCDC_BWR_REG3_DCDC_MINPWR_DOUBLE_FETS(base, value) (BME_BFI32(&DCDC_REG3_REG(base), ((uint3…
4448 #define DCDC_BWR_REG3_DCDC_MINPWR_HALF_FETS(base, value) (BME_BFI32(&DCDC_REG3_REG(base), ((uint32_…
4463 #define DCDC_BWR_REG3_DCDC_VDD1P45CTRL_DISABLE_STEP(base, value) (BME_BFI32(&DCDC_REG3_REG(base), (…
4478 #define DCDC_BWR_REG3_DCDC_VDD1P8CTRL_DISABLE_STEP(base, value) (BME_BFI32(&DCDC_REG3_REG(base), ((…
4516 #define DCDC_BWR_REG4_DCDC_SW_SHUTDOWN(base, value) (BME_BFI32(&DCDC_REG4_REG(base), ((uint32_t)(va…
4535 #define DCDC_BWR_REG4_UNLOCK(base, value) (BME_BFI32(&DCDC_REG4_REG(base), ((uint32_t)(value) << DC…
4575 #define DCDC_BWR_REG6_PSWITCH_INT_RISE_EN(base, value) (BME_BFI32(&DCDC_REG6_REG(base), ((uint32_t)…
4590 #define DCDC_BWR_REG6_PSWITCH_INT_FALL_EN(base, value) (BME_BFI32(&DCDC_REG6_REG(base), ((uint32_t)…
4605 #define DCDC_BWR_REG6_PSWITCH_INT_CLEAR(base, value) (BME_BFI32(&DCDC_REG6_REG(base), ((uint32_t)(v…
4620 #define DCDC_BWR_REG6_PSWITCH_INT_MUTE(base, value) (BME_BFI32(&DCDC_REG6_REG(base), ((uint32_t)(va…
4690 #define DCDC_BWR_REG7_INTEGRATOR_VALUE_SEL(base, value) (BME_BFI32(&DCDC_REG7_REG(base), ((uint32_t…
4706 #define DCDC_BWR_REG7_PULSE_RUN_SPEEDUP(base, value) (BME_BFI32(&DCDC_REG7_REG(base), ((uint32_t)(v…
4860 #define DMA_BWR_DSR_BCR_DONE(base, index, value) (BME_BFI32(&DMA_DSR_BCR_REG(base, index), ((uint32…
5010 #define DMA_BWR_DCR_LCH2(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(valu…
5032 #define DMA_BWR_DCR_LCH1(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(valu…
5064 #define DMA_BWR_DCR_LINKCC(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(va…
5084 #define DMA_BWR_DCR_D_REQ(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(val…
5124 #define DMA_BWR_DCR_DMOD(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(valu…
5181 #define DMA_BWR_DCR_SMOD(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(valu…
5196 #define DMA_BWR_DCR_START(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(val…
5218 #define DMA_BWR_DCR_DSIZE(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(val…
5238 #define DMA_BWR_DCR_DINC(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(valu…
5260 #define DMA_BWR_DCR_SSIZE(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(val…
5279 #define DMA_BWR_DCR_SINC(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(valu…
5299 #define DMA_BWR_DCR_EADREQ(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(va…
5323 #define DMA_BWR_DCR_AA(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(value)…
5341 #define DMA_BWR_DCR_CS(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(value)…
5361 #define DMA_BWR_DCR_ERQ(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(value…
5381 #define DMA_BWR_DCR_EINT(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(valu…
9917 #define LPTMR_BWR_CSR_TEN(base, value) (BME_BFI32(&LPTMR_CSR_REG(base), ((uint32_t)(value) << LPTMR…
9937 #define LPTMR_BWR_CSR_TMS(base, value) (BME_BFI32(&LPTMR_CSR_REG(base), ((uint32_t)(value) << LPTMR…
9958 #define LPTMR_BWR_CSR_TFC(base, value) (BME_BFI32(&LPTMR_CSR_REG(base), ((uint32_t)(value) << LPTMR…
9980 #define LPTMR_BWR_CSR_TPP(base, value) (BME_BFI32(&LPTMR_CSR_REG(base), ((uint32_t)(value) << LPTMR…
10004 #define LPTMR_BWR_CSR_TPS(base, value) (BME_BFI32(&LPTMR_CSR_REG(base), ((uint32_t)(value) << LPTMR…
10023 #define LPTMR_BWR_CSR_TIE(base, value) (BME_BFI32(&LPTMR_CSR_REG(base), ((uint32_t)(value) << LPTMR…
10043 #define LPTMR_BWR_CSR_TCF(base, value) (BME_BFI32(&LPTMR_CSR_REG(base), ((uint32_t)(value) << LPTMR…
10092 #define LPTMR_BWR_PSR_PCS(base, value) (BME_BFI32(&LPTMR_PSR_REG(base), ((uint32_t)(value) << LPTMR…
10114 #define LPTMR_BWR_PSR_PBYP(base, value) (BME_BFI32(&LPTMR_PSR_REG(base), ((uint32_t)(value) << LPTM…
10165 #define LPTMR_BWR_PSR_PRESCALE(base, value) (BME_BFI32(&LPTMR_PSR_REG(base), ((uint32_t)(value) << …
10209 #define LPTMR_BWR_CMR_COMPARE(base, value) (BME_BFI32(&LPTMR_CMR_REG(base), ((uint32_t)(value) << L…
10247 #define LPTMR_BWR_CNR_COUNTER(base, value) (BME_BFI32(&LPTMR_CNR_REG(base), ((uint32_t)(value) << L…
10308 #define LPUART_BWR_BAUD_SBR(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) << L…
10328 #define LPUART_BWR_BAUD_SBNS(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) << …
10349 #define LPUART_BWR_BAUD_RXEDGIE(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) …
10369 #define LPUART_BWR_BAUD_LBKDIE(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) <…
10390 #define LPUART_BWR_BAUD_RESYNCDIS(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value…
10415 #define LPUART_BWR_BAUD_BOTHEDGE(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value)…
10436 #define LPUART_BWR_BAUD_MATCFG(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) <…
10456 #define LPUART_BWR_BAUD_RDMAE(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) <<…
10476 #define LPUART_BWR_BAUD_TDMAE(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) <<…
10494 #define LPUART_BWR_BAUD_OSR(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) << L…
10514 #define LPUART_BWR_BAUD_M10(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) << L…
10532 #define LPUART_BWR_BAUD_MAEN2(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) <<…
10550 #define LPUART_BWR_BAUD_MAEN1(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) <<…
10595 #define LPUART_BWR_STAT_MA2F(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << …
10615 #define LPUART_BWR_STAT_MA1F(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << …
10637 #define LPUART_BWR_STAT_PF(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << LP…
10659 #define LPUART_BWR_STAT_FE(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << LP…
10683 #define LPUART_BWR_STAT_NF(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << LP…
10710 #define LPUART_BWR_STAT_OR(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << LP…
10741 #define LPUART_BWR_STAT_IDLE(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << …
10849 #define LPUART_BWR_STAT_LBKDE(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) <<…
10874 #define LPUART_BWR_STAT_BRK13(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) <<…
10900 #define LPUART_BWR_STAT_RWUID(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) <<…
10921 #define LPUART_BWR_STAT_RXINV(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) <<…
10949 #define LPUART_BWR_STAT_MSBF(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << …
10969 #define LPUART_BWR_STAT_RXEDGIF(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) …
10989 #define LPUART_BWR_STAT_LBKDIF(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) <…
11040 #define LPUART_BWR_CTRL_PT(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LP…
11060 #define LPUART_BWR_CTRL_PE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LP…
11086 #define LPUART_BWR_CTRL_ILT(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << L…
11107 #define LPUART_BWR_CTRL_WAKE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << …
11124 #define LPUART_BWR_CTRL_M(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPU…
11147 #define LPUART_BWR_CTRL_RSRC(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << …
11164 #define LPUART_BWR_CTRL_DOZEEN(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) <…
11186 #define LPUART_BWR_CTRL_LOOPS(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) <<…
11212 #define LPUART_BWR_CTRL_IDLECFG(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) …
11229 #define LPUART_BWR_CTRL_MA2IE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) <<…
11246 #define LPUART_BWR_CTRL_MA1IE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) <<…
11270 #define LPUART_BWR_CTRL_SBK(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << L…
11297 #define LPUART_BWR_CTRL_RWU(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << L…
11317 #define LPUART_BWR_CTRL_RE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LP…
11339 #define LPUART_BWR_CTRL_TE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LP…
11358 #define LPUART_BWR_CTRL_ILIE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << …
11377 #define LPUART_BWR_CTRL_RIE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << L…
11397 #define LPUART_BWR_CTRL_TCIE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << …
11416 #define LPUART_BWR_CTRL_TIE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << L…
11436 #define LPUART_BWR_CTRL_PEIE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << …
11456 #define LPUART_BWR_CTRL_FEIE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << …
11475 #define LPUART_BWR_CTRL_NEIE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << …
11495 #define LPUART_BWR_CTRL_ORIE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << …
11516 #define LPUART_BWR_CTRL_TXINV(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) <<…
11538 #define LPUART_BWR_CTRL_TXDIR(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) <<…
11559 #define LPUART_BWR_CTRL_R9T8(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << …
11580 #define LPUART_BWR_CTRL_R8T9(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << …
11625 #define LPUART_BWR_DATA_R0T0(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) << …
11640 #define LPUART_BWR_DATA_R1T1(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) << …
11655 #define LPUART_BWR_DATA_R2T2(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) << …
11670 #define LPUART_BWR_DATA_R3T3(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) << …
11685 #define LPUART_BWR_DATA_R4T4(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) << …
11700 #define LPUART_BWR_DATA_R5T5(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) << …
11715 #define LPUART_BWR_DATA_R6T6(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) << …
11730 #define LPUART_BWR_DATA_R7T7(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) << …
11745 #define LPUART_BWR_DATA_R8T8(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) << …
11760 #define LPUART_BWR_DATA_R9T9(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) << …
11818 #define LPUART_BWR_DATA_FRETSC(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) <…
11894 #define LPUART_BWR_MATCH_MA1(base, value) (BME_BFI32(&LPUART_MATCH_REG(base), ((uint32_t)(value) <<…
11913 #define LPUART_BWR_MATCH_MA2(base, value) (BME_BFI32(&LPUART_MATCH_REG(base), ((uint32_t)(value) <<…
11964 #define LPUART_BWR_MODIR_TXCTSE(base, value) (BME_BFI32(&LPUART_MODIR_REG(base), ((uint32_t)(value)…
11986 #define LPUART_BWR_MODIR_TXRTSE(base, value) (BME_BFI32(&LPUART_MODIR_REG(base), ((uint32_t)(value)…
12007 #define LPUART_BWR_MODIR_TXRTSPOL(base, value) (BME_BFI32(&LPUART_MODIR_REG(base), ((uint32_t)(valu…
12027 #define LPUART_BWR_MODIR_RXRTSE(base, value) (BME_BFI32(&LPUART_MODIR_REG(base), ((uint32_t)(value)…
12047 #define LPUART_BWR_MODIR_TXCTSC(base, value) (BME_BFI32(&LPUART_MODIR_REG(base), ((uint32_t)(value)…
12066 #define LPUART_BWR_MODIR_TXCTSSRC(base, value) (BME_BFI32(&LPUART_MODIR_REG(base), ((uint32_t)(valu…
12088 #define LPUART_BWR_MODIR_TNP(base, value) (BME_BFI32(&LPUART_MODIR_REG(base), ((uint32_t)(value) <<…
12107 #define LPUART_BWR_MODIR_IREN(base, value) (BME_BFI32(&LPUART_MODIR_REG(base), ((uint32_t)(value) <…
12186 #define LTC_BWR_MD_ENC(base, value) (BME_BFI32(&LTC_MD_REG(base), ((uint32_t)(value) << LTC_MD_ENC_…
12207 #define LTC_BWR_MD_ICV_TEST(base, value) (BME_BFI32(&LTC_MD_REG(base), ((uint32_t)(value) << LTC_MD…
12233 #define LTC_BWR_MD_AS(base, value) (BME_BFI32(&LTC_MD_REG(base), ((uint32_t)(value) << LTC_MD_AS_SH…
12257 #define LTC_BWR_MD_AAI(base, value) (BME_BFI32(&LTC_MD_REG(base), ((uint32_t)(value) << LTC_MD_AAI_…
12276 #define LTC_BWR_MD_ALG(base, value) (BME_BFI32(&LTC_MD_REG(base), ((uint32_t)(value) << LTC_MD_ALG_…
12358 #define LTC_BWR_DS_DS(base, value) (BME_BFI32(&LTC_DS_REG(base), ((uint32_t)(value) << LTC_DS_DS_SH…
12404 #define LTC_BWR_ICVS_ICVS(base, value) (BME_BFI32(&LTC_ICVS_REG(base), ((uint32_t)(value) << LTC_IC…
12510 #define LTC_BWR_CTL_IM(base, value) (BME_BFI32(&LTC_CTL_REG(base), ((uint32_t)(value) << LTC_CTL_IM…
12531 #define LTC_BWR_CTL_IFE(base, value) (BME_BFI32(&LTC_CTL_REG(base), ((uint32_t)(value) << LTC_CTL_I…
12553 #define LTC_BWR_CTL_IFR(base, value) (BME_BFI32(&LTC_CTL_REG(base), ((uint32_t)(value) << LTC_CTL_I…
12574 #define LTC_BWR_CTL_OFE(base, value) (BME_BFI32(&LTC_CTL_REG(base), ((uint32_t)(value) << LTC_CTL_O…
12596 #define LTC_BWR_CTL_OFR(base, value) (BME_BFI32(&LTC_CTL_REG(base), ((uint32_t)(value) << LTC_CTL_O…
12617 #define LTC_BWR_CTL_IFS(base, value) (BME_BFI32(&LTC_CTL_REG(base), ((uint32_t)(value) << LTC_CTL_I…
12638 #define LTC_BWR_CTL_OFS(base, value) (BME_BFI32(&LTC_CTL_REG(base), ((uint32_t)(value) << LTC_CTL_O…
12660 #define LTC_BWR_CTL_KIS(base, value) (BME_BFI32(&LTC_CTL_REG(base), ((uint32_t)(value) << LTC_CTL_K…
12682 #define LTC_BWR_CTL_KOS(base, value) (BME_BFI32(&LTC_CTL_REG(base), ((uint32_t)(value) << LTC_CTL_K…
12704 #define LTC_BWR_CTL_CIS(base, value) (BME_BFI32(&LTC_CTL_REG(base), ((uint32_t)(value) << LTC_CTL_C…
12726 #define LTC_BWR_CTL_COS(base, value) (BME_BFI32(&LTC_CTL_REG(base), ((uint32_t)(value) << LTC_CTL_C…
12749 #define LTC_BWR_CTL_KAL(base, value) (BME_BFI32(&LTC_CTL_REG(base), ((uint32_t)(value) << LTC_CTL_K…
12917 #define LTC_BWR_STA_DI(base, value) (BME_BFI32(&LTC_STA_REG(base), ((uint32_t)(value) << LTC_STA_DI…
13060 #define LTC_BWR_AADSZ_AADSZ(base, value) (BME_BFI32(&LTC_AADSZ_REG(base), ((uint32_t)(value) << LTC…
13075 #define LTC_BWR_AADSZ_AL(base, value) (BME_BFI32(&LTC_AADSZ_REG(base), ((uint32_t)(value) << LTC_AA…
16265 #define PIT_BWR_MCR_FRZ(base, value) (BME_BFI32(&PIT_MCR_REG(base), ((uint32_t)(value) << PIT_MCR_F…
16285 #define PIT_BWR_MCR_MDIS(base, value) (BME_BFI32(&PIT_MCR_REG(base), ((uint32_t)(value) << PIT_MCR_…
16417 #define PIT_BWR_TCTRL_TEN(base, index, value) (BME_BFI32(&PIT_TCTRL_REG(base, index), ((uint32_t)(v…
16438 #define PIT_BWR_TCTRL_TIE(base, index, value) (BME_BFI32(&PIT_TCTRL_REG(base, index), ((uint32_t)(v…
16459 #define PIT_BWR_TCTRL_CHN(base, index, value) (BME_BFI32(&PIT_TCTRL_REG(base, index), ((uint32_t)(v…
16507 #define PIT_BWR_TFLG_TIF(base, index, value) (BME_BFI32(&PIT_TFLG_REG(base, index), ((uint32_t)(val…
16937 #define PORT_BWR_PCR_PS(base, index, value) (BME_BFI32(&PORT_PCR_REG(base, index), ((uint32_t)(valu…
16961 #define PORT_BWR_PCR_PE(base, index, value) (BME_BFI32(&PORT_PCR_REG(base, index), ((uint32_t)(valu…
16983 #define PORT_BWR_PCR_SRE(base, index, value) (BME_BFI32(&PORT_PCR_REG(base, index), ((uint32_t)(val…
17006 #define PORT_BWR_PCR_PFE(base, index, value) (BME_BFI32(&PORT_PCR_REG(base, index), ((uint32_t)(val…
17028 #define PORT_BWR_PCR_DSE(base, index, value) (BME_BFI32(&PORT_PCR_REG(base, index), ((uint32_t)(val…
17056 #define PORT_BWR_PCR_MUX(base, index, value) (BME_BFI32(&PORT_PCR_REG(base, index), ((uint32_t)(val…
17091 #define PORT_BWR_PCR_IRQC(base, index, value) (BME_BFI32(&PORT_PCR_REG(base, index), ((uint32_t)(va…
17116 #define PORT_BWR_PCR_ISF(base, index, value) (BME_BFI32(&PORT_PCR_REG(base, index), ((uint32_t)(val…
17152 #define PORT_BWR_GPCLR_GPWD(base, value) (BME_BFI32(&PORT_GPCLR_REG(base), ((uint32_t)(value) << PO…
17170 #define PORT_BWR_GPCLR_GPWE(base, value) (BME_BFI32(&PORT_GPCLR_REG(base), ((uint32_t)(value) << PO…
17206 #define PORT_BWR_GPCHR_GPWD(base, value) (BME_BFI32(&PORT_GPCHR_REG(base), ((uint32_t)(value) << PO…
17224 #define PORT_BWR_GPCHR_GPWE(base, value) (BME_BFI32(&PORT_GPCHR_REG(base), ((uint32_t)(value) << PO…
17953 #define RSIM_BWR_CONTROL_BLE_RF_OSC_REQ_EN(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((uint3…
17981 #define RSIM_BWR_CONTROL_BLE_RF_OSC_REQ_INT_EN(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((u…
17998 #define RSIM_BWR_CONTROL_BLE_RF_OSC_REQ_INT(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((uint…
18024 #define RSIM_BWR_CONTROL_RF_OSC_EN(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((uint32_t)(val…
18041 #define RSIM_BWR_CONTROL_GASKET_BYPASS_OVRD_EN(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((u…
18073 #define RSIM_BWR_CONTROL_GASKET_BYPASS_OVRD(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((uint…
18091 #define RSIM_BWR_CONTROL_RF_OSC_BYPASS_EN(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((uint32…
18107 #define RSIM_BWR_CONTROL_BLE_ACTIVE_PORT_1_SEL(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((u…
18123 #define RSIM_BWR_CONTROL_BLE_ACTIVE_PORT_2_SEL(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((u…
18138 #define RSIM_BWR_CONTROL_BLE_DEEP_SLEEP_EXIT(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((uin…
18158 #define RSIM_BWR_CONTROL_STOP_ACK_OVRD_EN(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((uint32…
18174 #define RSIM_BWR_CONTROL_STOP_ACK_OVRD(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((uint32_t)…
18205 #define RSIM_BWR_CONTROL_RF_OSC_READY_OVRD_EN(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((ui…
18222 #define RSIM_BWR_CONTROL_RF_OSC_READY_OVRD(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((uint3…
18240 #define RSIM_BWR_CONTROL_BLOCK_RADIO_RESETS(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((uint…
18258 #define RSIM_BWR_CONTROL_BLOCK_RADIO_OUTPUTS(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((uin…
18277 #define RSIM_BWR_CONTROL_RADIO_RESET(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((uint32_t)(v…
18326 #define RSIM_BWR_ACTIVE_DELAY_BLE_ACTIVE_FINE_DELAY(base, value) (BME_BFI32(&RSIM_ACTIVE_DELAY_REG(…
18346 #define RSIM_BWR_ACTIVE_DELAY_BLE_ACTIVE_COARSE_DELAY(base, value) (BME_BFI32(&RSIM_ACTIVE_DELAY_RE…
18446 #define RSIM_BWR_ANA_TEST_ATST_GATE_EN(base, value) (BME_BFI32(&RSIM_ANA_TEST_REG(base), ((uint32_t…
18546 #define RTC_BWR_TPR_TPR(base, value) (BME_BFI32(&RTC_TPR_REG(base), ((uint32_t)(value) << RTC_TPR_T…
18616 #define RTC_BWR_TCR_TCR(base, value) (BME_BFI32(&RTC_TCR_REG(base), ((uint32_t)(value) << RTC_TCR_T…
18636 #define RTC_BWR_TCR_CIR(base, value) (BME_BFI32(&RTC_TCR_REG(base), ((uint32_t)(value) << RTC_TCR_C…
18706 #define RTC_BWR_CR_SWR(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_SWR_…
18726 #define RTC_BWR_CR_WPE(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_WPE_…
18744 #define RTC_BWR_CR_SUP(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_SUP_…
18765 #define RTC_BWR_CR_UM(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_UM_SH…
18786 #define RTC_BWR_CR_WPS(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_WPS_…
18805 #define RTC_BWR_CR_OSCE(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_OSC…
18822 #define RTC_BWR_CR_CLKO(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_CLK…
18839 #define RTC_BWR_CR_SC16P(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_SC…
18856 #define RTC_BWR_CR_SC8P(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_SC8…
18873 #define RTC_BWR_CR_SC4P(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_SC4…
18890 #define RTC_BWR_CR_SC2P(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_SC2…
18986 #define RTC_BWR_SR_TCE(base, value) (BME_BFI32(&RTC_SR_REG(base), ((uint32_t)(value) << RTC_SR_TCE_…
19031 #define RTC_BWR_LR_TCL(base, value) (BME_BFI32(&RTC_LR_REG(base), ((uint32_t)(value) << RTC_LR_TCL_…
19050 #define RTC_BWR_LR_CRL(base, value) (BME_BFI32(&RTC_LR_REG(base), ((uint32_t)(value) << RTC_LR_CRL_…
19069 #define RTC_BWR_LR_SRL(base, value) (BME_BFI32(&RTC_LR_REG(base), ((uint32_t)(value) << RTC_LR_SRL_…
19088 #define RTC_BWR_LR_LRL(base, value) (BME_BFI32(&RTC_LR_REG(base), ((uint32_t)(value) << RTC_LR_LRL_…
19130 #define RTC_BWR_IER_TIIE(base, value) (BME_BFI32(&RTC_IER_REG(base), ((uint32_t)(value) << RTC_IER_…
19147 #define RTC_BWR_IER_TOIE(base, value) (BME_BFI32(&RTC_IER_REG(base), ((uint32_t)(value) << RTC_IER_…
19164 #define RTC_BWR_IER_TAIE(base, value) (BME_BFI32(&RTC_IER_REG(base), ((uint32_t)(value) << RTC_IER_…
19185 #define RTC_BWR_IER_TSIE(base, value) (BME_BFI32(&RTC_IER_REG(base), ((uint32_t)(value) << RTC_IER_…
19205 #define RTC_BWR_IER_WPON(base, value) (BME_BFI32(&RTC_IER_REG(base), ((uint32_t)(value) << RTC_IER_…
19285 #define SIM_BWR_SOPT1_OSC32KOUT(base, value) (BME_BFI32(&SIM_SOPT1_REG(base), ((uint32_t)(value) <<…
19307 #define SIM_BWR_SOPT1_OSC32KSEL(base, value) (BME_BFI32(&SIM_SOPT1_REG(base), ((uint32_t)(value) <<…
19361 #define SIM_BWR_SOPT2_CLKOUTSEL(base, value) (BME_BFI32(&SIM_SOPT2_REG(base), ((uint32_t)(value) <<…
19382 #define SIM_BWR_SOPT2_TPMSRC(base, value) (BME_BFI32(&SIM_SOPT2_REG(base), ((uint32_t)(value) << SI…
19403 #define SIM_BWR_SOPT2_LPUART0SRC(base, value) (BME_BFI32(&SIM_SOPT2_REG(base), ((uint32_t)(value) <…
19448 #define SIM_BWR_SOPT4_TPM1CH0SRC(base, value) (BME_BFI32(&SIM_SOPT4_REG(base), ((uint32_t)(value) <…
19468 #define SIM_BWR_SOPT4_TPM2CH0SRC(base, value) (BME_BFI32(&SIM_SOPT4_REG(base), ((uint32_t)(value) <…
19489 #define SIM_BWR_SOPT4_TPM0CLKSEL(base, value) (BME_BFI32(&SIM_SOPT4_REG(base), ((uint32_t)(value) <…
19510 #define SIM_BWR_SOPT4_TPM1CLKSEL(base, value) (BME_BFI32(&SIM_SOPT4_REG(base), ((uint32_t)(value) <…
19531 #define SIM_BWR_SOPT4_TPM2CLKSEL(base, value) (BME_BFI32(&SIM_SOPT4_REG(base), ((uint32_t)(value) <…
19577 #define SIM_BWR_SOPT5_LPUART0TXSRC(base, value) (BME_BFI32(&SIM_SOPT5_REG(base), ((uint32_t)(value)…
19596 #define SIM_BWR_SOPT5_LPUART0RXSRC(base, value) (BME_BFI32(&SIM_SOPT5_REG(base), ((uint32_t)(value)…
19613 #define SIM_BWR_SOPT5_LPUART0ODE(base, value) (BME_BFI32(&SIM_SOPT5_REG(base), ((uint32_t)(value) <…
19672 #define SIM_BWR_SOPT7_ADC0TRGSEL(base, value) (BME_BFI32(&SIM_SOPT7_REG(base), ((uint32_t)(value) <…
19696 #define SIM_BWR_SOPT7_ADC0PRETRGSEL(base, value) (BME_BFI32(&SIM_SOPT7_REG(base), ((uint32_t)(value…
19724 #define SIM_BWR_SOPT7_ADC0ALTTRGEN(base, value) (BME_BFI32(&SIM_SOPT7_REG(base), ((uint32_t)(value)…
19886 #define SIM_BWR_SCGC_BIT(base, index, value) (BME_BFI32(&SIM_SCGC_BIT_REG((base), (index)), ((uint3…
19908 #define SIM_BWR_SCGC4_CMT(base, value) (BME_BFI32(&SIM_SCGC4_REG(base), ((uint32_t)(value) << SIM_S…
19927 #define SIM_BWR_SCGC4_I2C0(base, value) (BME_BFI32(&SIM_SCGC4_REG(base), ((uint32_t)(value) << SIM_…
19946 #define SIM_BWR_SCGC4_I2C1(base, value) (BME_BFI32(&SIM_SCGC4_REG(base), ((uint32_t)(value) << SIM_…
19965 #define SIM_BWR_SCGC4_CMP(base, value) (BME_BFI32(&SIM_SCGC4_REG(base), ((uint32_t)(value) << SIM_S…
20009 #define SIM_BWR_SCGC5_LPTMR(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << SIM…
20028 #define SIM_BWR_SCGC5_TSI(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << SIM_S…
20047 #define SIM_BWR_SCGC5_PORTA(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << SIM…
20066 #define SIM_BWR_SCGC5_PORTB(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << SIM…
20085 #define SIM_BWR_SCGC5_PORTC(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << SIM…
20104 #define SIM_BWR_SCGC5_LPUART0(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << S…
20123 #define SIM_BWR_SCGC5_LTC(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << SIM_S…
20154 #define SIM_BWR_SCGC5_DCDC(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << SIM_…
20173 #define SIM_BWR_SCGC5_BTLL(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << SIM_…
20192 #define SIM_BWR_SCGC5_PHYDIG(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << SI…
20211 #define SIM_BWR_SCGC5_ZigBee(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << SI…
20257 #define SIM_BWR_SCGC6_FTF(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_S…
20276 #define SIM_BWR_SCGC6_DMAMUX(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SI…
20295 #define SIM_BWR_SCGC6_TRNG(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_…
20314 #define SIM_BWR_SCGC6_SPI0(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_…
20333 #define SIM_BWR_SCGC6_SPI1(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_…
20352 #define SIM_BWR_SCGC6_PIT(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_S…
20371 #define SIM_BWR_SCGC6_TPM0(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_…
20390 #define SIM_BWR_SCGC6_TPM1(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_…
20409 #define SIM_BWR_SCGC6_TPM2(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_…
20428 #define SIM_BWR_SCGC6_ADC0(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_…
20447 #define SIM_BWR_SCGC6_RTC(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_S…
20466 #define SIM_BWR_SCGC6_DAC0(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_…
20510 #define SIM_BWR_SCGC7_DMA(base, value) (BME_BFI32(&SIM_SCGC7_REG(base), ((uint32_t)(value) << SIM_S…
20565 #define SIM_BWR_CLKDIV1_OUTDIV4(base, value) (BME_BFI32(&SIM_CLKDIV1_REG(base), ((uint32_t)(value) …
20601 #define SIM_BWR_CLKDIV1_OUTDIV1(base, value) (BME_BFI32(&SIM_CLKDIV1_REG(base), ((uint32_t)(value) …
20650 #define SIM_BWR_FCFG1_FLASHDIS(base, value) (BME_BFI32(&SIM_FCFG1_REG(base), ((uint32_t)(value) << …
20674 #define SIM_BWR_FCFG1_FLASHDOZE(base, value) (BME_BFI32(&SIM_FCFG1_REG(base), ((uint32_t)(value) <<…
20859 #define SIM_BWR_COPC_COPW(base, value) (BME_BFI32(&SIM_COPC_REG(base), ((uint32_t)(value) << SIM_CO…
20879 #define SIM_BWR_COPC_COPCLKS(base, value) (BME_BFI32(&SIM_COPC_REG(base), ((uint32_t)(value) << SIM…
20904 #define SIM_BWR_COPC_COPT(base, value) (BME_BFI32(&SIM_COPC_REG(base), ((uint32_t)(value) << SIM_CO…
20921 #define SIM_BWR_COPC_COPSTPEN(base, value) (BME_BFI32(&SIM_COPC_REG(base), ((uint32_t)(value) << SI…
20938 #define SIM_BWR_COPC_COPDBGEN(base, value) (BME_BFI32(&SIM_COPC_REG(base), ((uint32_t)(value) << SI…
20959 #define SIM_BWR_COPC_COPCLKSEL(base, value) (BME_BFI32(&SIM_COPC_REG(base), ((uint32_t)(value) << S…
21415 #define SPI_BWR_MCR_HALT(base, value) (BME_BFI32(&SPI_MCR_REG(base), ((uint32_t)(value) << SPI_MCR_…
21437 #define SPI_BWR_MCR_SMPL_PT(base, value) (BME_BFI32(&SPI_MCR_REG(base), ((uint32_t)(value) << SPI_M…
21453 #define SPI_BWR_MCR_CLR_RXF(base, value) (BME_BFI32(&SPI_MCR_REG(base), ((uint32_t)(value) << SPI_M…
21469 #define SPI_BWR_MCR_CLR_TXF(base, value) (BME_BFI32(&SPI_MCR_REG(base), ((uint32_t)(value) << SPI_M…
21490 #define SPI_BWR_MCR_DIS_RXF(base, value) (BME_BFI32(&SPI_MCR_REG(base), ((uint32_t)(value) << SPI_M…
21511 #define SPI_BWR_MCR_DIS_TXF(base, value) (BME_BFI32(&SPI_MCR_REG(base), ((uint32_t)(value) << SPI_M…
21534 #define SPI_BWR_MCR_MDIS(base, value) (BME_BFI32(&SPI_MCR_REG(base), ((uint32_t)(value) << SPI_MCR_…
21554 #define SPI_BWR_MCR_DOZE(base, value) (BME_BFI32(&SPI_MCR_REG(base), ((uint32_t)(value) << SPI_MCR_…
21574 #define SPI_BWR_MCR_PCSIS(base, value) (BME_BFI32(&SPI_MCR_REG(base), ((uint32_t)(value) << SPI_MCR…
21596 #define SPI_BWR_MCR_ROOE(base, value) (BME_BFI32(&SPI_MCR_REG(base), ((uint32_t)(value) << SPI_MCR_…
21615 #define SPI_BWR_MCR_MTFE(base, value) (BME_BFI32(&SPI_MCR_REG(base), ((uint32_t)(value) << SPI_MCR_…
21635 #define SPI_BWR_MCR_FRZ(base, value) (BME_BFI32(&SPI_MCR_REG(base), ((uint32_t)(value) << SPI_MCR_F…
21671 #define SPI_BWR_MCR_CONT_SCKE(base, value) (BME_BFI32(&SPI_MCR_REG(base), ((uint32_t)(value) << SPI…
21691 #define SPI_BWR_MCR_MSTR(base, value) (BME_BFI32(&SPI_MCR_REG(base), ((uint32_t)(value) << SPI_MCR_…
21740 #define SPI_BWR_TCR_SPI_TCNT(base, value) (BME_BFI32(&SPI_TCR_REG(base), ((uint32_t)(value) << SPI_…
21792 #define SPI_BWR_CTAR_SLAVE_CPHA(base, index, value) (BME_BFI32(&SPI_CTAR_SLAVE_REG(base, index), ((…
21813 #define SPI_BWR_CTAR_SLAVE_CPOL(base, index, value) (BME_BFI32(&SPI_CTAR_SLAVE_REG(base, index), ((…
21829 #define SPI_BWR_CTAR_SLAVE_FMSZ(base, index, value) (BME_BFI32(&SPI_CTAR_SLAVE_REG(base, index), ((…
21886 #define SPI_BWR_CTAR_BR(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(valu…
21908 #define SPI_BWR_CTAR_DT(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(valu…
21928 #define SPI_BWR_CTAR_ASC(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(val…
21951 #define SPI_BWR_CTAR_CSSCK(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(v…
21975 #define SPI_BWR_CTAR_PBR(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(val…
22000 #define SPI_BWR_CTAR_PDT(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(val…
22023 #define SPI_BWR_CTAR_PASC(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(va…
22046 #define SPI_BWR_CTAR_PCSSCK(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(…
22065 #define SPI_BWR_CTAR_LSBFE(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(v…
22090 #define SPI_BWR_CTAR_CPHA(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(va…
22116 #define SPI_BWR_CTAR_CPOL(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(va…
22132 #define SPI_BWR_CTAR_FMSZ(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(va…
22160 #define SPI_BWR_CTAR_DBR(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(val…
22264 #define SPI_BWR_SR_RFDF(base, value) (BME_BFI32(&SPI_SR_REG(base), ((uint32_t)(value) << SPI_SR_RFD…
22285 #define SPI_BWR_SR_RFOF(base, value) (BME_BFI32(&SPI_SR_REG(base), ((uint32_t)(value) << SPI_SR_RFO…
22307 #define SPI_BWR_SR_TFFF(base, value) (BME_BFI32(&SPI_SR_REG(base), ((uint32_t)(value) << SPI_SR_TFF…
22330 #define SPI_BWR_SR_TFUF(base, value) (BME_BFI32(&SPI_SR_REG(base), ((uint32_t)(value) << SPI_SR_TFU…
22353 #define SPI_BWR_SR_EOQF(base, value) (BME_BFI32(&SPI_SR_REG(base), ((uint32_t)(value) << SPI_SR_EOQ…
22374 #define SPI_BWR_SR_TXRXS(base, value) (BME_BFI32(&SPI_SR_REG(base), ((uint32_t)(value) << SPI_SR_TX…
22394 #define SPI_BWR_SR_TCF(base, value) (BME_BFI32(&SPI_SR_REG(base), ((uint32_t)(value) << SPI_SR_TCF_…
22443 #define SPI_BWR_RSER_RFDF_DIRS(base, value) (BME_BFI32(&SPI_RSER_REG(base), ((uint32_t)(value) << S…
22463 #define SPI_BWR_RSER_RFDF_RE(base, value) (BME_BFI32(&SPI_RSER_REG(base), ((uint32_t)(value) << SPI…
22482 #define SPI_BWR_RSER_RFOF_RE(base, value) (BME_BFI32(&SPI_RSER_REG(base), ((uint32_t)(value) << SPI…
22503 #define SPI_BWR_RSER_TFFF_DIRS(base, value) (BME_BFI32(&SPI_RSER_REG(base), ((uint32_t)(value) << S…
22523 #define SPI_BWR_RSER_TFFF_RE(base, value) (BME_BFI32(&SPI_RSER_REG(base), ((uint32_t)(value) << SPI…
22542 #define SPI_BWR_RSER_TFUF_RE(base, value) (BME_BFI32(&SPI_RSER_REG(base), ((uint32_t)(value) << SPI…
22561 #define SPI_BWR_RSER_EOQF_RE(base, value) (BME_BFI32(&SPI_RSER_REG(base), ((uint32_t)(value) << SPI…
22580 #define SPI_BWR_RSER_TCF_RE(base, value) (BME_BFI32(&SPI_RSER_REG(base), ((uint32_t)(value) << SPI_…
22629 #define SPI_BWR_PUSHR_TXDATA(base, value) (BME_BFI32(&SPI_PUSHR_REG(base), ((uint32_t)(value) << SP…
22649 #define SPI_BWR_PUSHR_PCS(base, value) (BME_BFI32(&SPI_PUSHR_REG(base), ((uint32_t)(value) << SPI_P…
22669 #define SPI_BWR_PUSHR_CTCNT(base, value) (BME_BFI32(&SPI_PUSHR_REG(base), ((uint32_t)(value) << SPI…
22690 #define SPI_BWR_PUSHR_EOQ(base, value) (BME_BFI32(&SPI_PUSHR_REG(base), ((uint32_t)(value) << SPI_P…
22718 #define SPI_BWR_PUSHR_CTAS(base, value) (BME_BFI32(&SPI_PUSHR_REG(base), ((uint32_t)(value) << SPI_…
22738 #define SPI_BWR_PUSHR_CONT(base, value) (BME_BFI32(&SPI_PUSHR_REG(base), ((uint32_t)(value) << SPI_…
23151 #define TPM_BWR_SC_PS(base, value) (BME_BFI32(&TPM_SC_REG(base), ((uint32_t)(value) << TPM_SC_PS_SH…
23174 #define TPM_BWR_SC_CMOD(base, value) (BME_BFI32(&TPM_SC_REG(base), ((uint32_t)(value) << TPM_SC_CMO…
23195 #define TPM_BWR_SC_CPWMS(base, value) (BME_BFI32(&TPM_SC_REG(base), ((uint32_t)(value) << TPM_SC_CP…
23214 #define TPM_BWR_SC_TOIE(base, value) (BME_BFI32(&TPM_SC_REG(base), ((uint32_t)(value) << TPM_SC_TOI…
23238 #define TPM_BWR_SC_TOF(base, value) (BME_BFI32(&TPM_SC_REG(base), ((uint32_t)(value) << TPM_SC_TOF_…
23257 #define TPM_BWR_SC_DMA(base, value) (BME_BFI32(&TPM_SC_REG(base), ((uint32_t)(value) << TPM_SC_DMA_…
23301 #define TPM_BWR_CNT_COUNT(base, value) (BME_BFI32(&TPM_CNT_REG(base), ((uint32_t)(value) << TPM_CNT…
23352 #define TPM_BWR_MOD_MOD(base, value) (BME_BFI32(&TPM_MOD_REG(base), ((uint32_t)(value) << TPM_MOD_M…
23411 #define TPM_BWR_CnSC_DMA(base, index, value) (BME_BFI32(&TPM_CnSC_REG(base, index), ((uint32_t)(val…
23428 #define TPM_BWR_CnSC_ELSA(base, index, value) (BME_BFI32(&TPM_CnSC_REG(base, index), ((uint32_t)(va…
23445 #define TPM_BWR_CnSC_ELSB(base, index, value) (BME_BFI32(&TPM_CnSC_REG(base, index), ((uint32_t)(va…
23462 #define TPM_BWR_CnSC_MSA(base, index, value) (BME_BFI32(&TPM_CnSC_REG(base, index), ((uint32_t)(val…
23479 #define TPM_BWR_CnSC_MSB(base, index, value) (BME_BFI32(&TPM_CnSC_REG(base, index), ((uint32_t)(val…
23498 #define TPM_BWR_CnSC_CHIE(base, index, value) (BME_BFI32(&TPM_CnSC_REG(base, index), ((uint32_t)(va…
23522 #define TPM_BWR_CnSC_CHF(base, index, value) (BME_BFI32(&TPM_CnSC_REG(base, index), ((uint32_t)(val…
23570 #define TPM_BWR_CnV_VAL(base, index, value) (BME_BFI32(&TPM_CnV_REG(base, index), ((uint32_t)(value…
23625 #define TPM_BWR_STATUS_CH0F(base, value) (BME_BFI32(&TPM_STATUS_REG(base), ((uint32_t)(value) << TP…
23644 #define TPM_BWR_STATUS_CH1F(base, value) (BME_BFI32(&TPM_STATUS_REG(base), ((uint32_t)(value) << TP…
23663 #define TPM_BWR_STATUS_CH2F(base, value) (BME_BFI32(&TPM_STATUS_REG(base), ((uint32_t)(value) << TP…
23682 #define TPM_BWR_STATUS_CH3F(base, value) (BME_BFI32(&TPM_STATUS_REG(base), ((uint32_t)(value) << TP…
23701 #define TPM_BWR_STATUS_TOF(base, value) (BME_BFI32(&TPM_STATUS_REG(base), ((uint32_t)(value) << TPM…
23753 #define TPM_BWR_COMBINE_COMBINE0(base, value) (BME_BFI32(&TPM_COMBINE_REG(base), ((uint32_t)(value)…
23773 #define TPM_BWR_COMBINE_COMSWAP0(base, value) (BME_BFI32(&TPM_COMBINE_REG(base), ((uint32_t)(value)…
23796 #define TPM_BWR_COMBINE_COMBINE1(base, value) (BME_BFI32(&TPM_COMBINE_REG(base), ((uint32_t)(value)…
23816 #define TPM_BWR_COMBINE_COMSWAP1(base, value) (BME_BFI32(&TPM_COMBINE_REG(base), ((uint32_t)(value)…
23862 #define TPM_BWR_FILTER_CH0FVAL(base, value) (BME_BFI32(&TPM_FILTER_REG(base), ((uint32_t)(value) <<…
23879 #define TPM_BWR_FILTER_CH1FVAL(base, value) (BME_BFI32(&TPM_FILTER_REG(base), ((uint32_t)(value) <<…
23896 #define TPM_BWR_FILTER_CH2FVAL(base, value) (BME_BFI32(&TPM_FILTER_REG(base), ((uint32_t)(value) <<…
23913 #define TPM_BWR_FILTER_CH3FVAL(base, value) (BME_BFI32(&TPM_FILTER_REG(base), ((uint32_t)(value) <<…
23961 #define TPM_BWR_QDCTRL_QUADEN(base, value) (BME_BFI32(&TPM_QDCTRL_REG(base), ((uint32_t)(value) << …
24014 #define TPM_BWR_QDCTRL_QUADMODE(base, value) (BME_BFI32(&TPM_QDCTRL_REG(base), ((uint32_t)(value) <…
24062 #define TPM_BWR_CONF_DOZEEN(base, value) (BME_BFI32(&TPM_CONF_REG(base), ((uint32_t)(value) << TPM_…
24083 #define TPM_BWR_CONF_DBGMODE(base, value) (BME_BFI32(&TPM_CONF_REG(base), ((uint32_t)(value) << TPM…
24107 #define TPM_BWR_CONF_GTBEEN(base, value) (BME_BFI32(&TPM_CONF_REG(base), ((uint32_t)(value) << TPM_…
24133 #define TPM_BWR_CONF_CSOT(base, value) (BME_BFI32(&TPM_CONF_REG(base), ((uint32_t)(value) << TPM_CO…
24158 #define TPM_BWR_CONF_CSOO(base, value) (BME_BFI32(&TPM_CONF_REG(base), ((uint32_t)(value) << TPM_CO…
24183 #define TPM_BWR_CONF_CROT(base, value) (BME_BFI32(&TPM_CONF_REG(base), ((uint32_t)(value) << TPM_CO…
24200 #define TPM_BWR_CONF_TRGSEL(base, value) (BME_BFI32(&TPM_CONF_REG(base), ((uint32_t)(value) << TPM_…
24313 #define TRNG_BWR_MCTL_SAMP_MODE(base, value) (BME_BFI32(&TRNG_MCTL_REG(base), ((uint32_t)(value) <<…
24337 #define TRNG_BWR_MCTL_OSC_DIV(base, value) (BME_BFI32(&TRNG_MCTL_REG(base), ((uint32_t)(value) << T…
24352 #define TRNG_BWR_MCTL_UNUSED(base, value) (BME_BFI32(&TRNG_MCTL_REG(base), ((uint32_t)(value) << TR…
24370 #define TRNG_BWR_MCTL_TRNG_ACC(base, value) (BME_BFI32(&TRNG_MCTL_REG(base), ((uint32_t)(value) << …
24403 #define TRNG_BWR_MCTL_FOR_SCLK(base, value) (BME_BFI32(&TRNG_MCTL_REG(base), ((uint32_t)(value) << …
24469 #define TRNG_BWR_MCTL_ERR(base, value) (BME_BFI32(&TRNG_MCTL_REG(base), ((uint32_t)(value) << TRNG_…
24505 #define TRNG_BWR_MCTL_PRGM(base, value) (BME_BFI32(&TRNG_MCTL_REG(base), ((uint32_t)(value) << TRNG…
24554 #define TRNG_BWR_SCMISC_LRUN_MAX(base, value) (BME_BFI32(&TRNG_SCMISC_REG(base), ((uint32_t)(value)…
24573 #define TRNG_BWR_SCMISC_RTY_CT(base, value) (BME_BFI32(&TRNG_SCMISC_REG(base), ((uint32_t)(value) <…
24623 #define TRNG_BWR_PKRRNG_PKR_RNG(base, value) (BME_BFI32(&TRNG_PKRRNG_REG(base), ((uint32_t)(value) …
24769 #define TRNG_BWR_SDCTL_SAMP_SIZE(base, value) (BME_BFI32(&TRNG_SDCTL_REG(base), ((uint32_t)(value) …
24787 #define TRNG_BWR_SDCTL_ENT_DLY(base, value) (BME_BFI32(&TRNG_SDCTL_REG(base), ((uint32_t)(value) <<…
24841 #define TRNG_BWR_SBLIM_SB_LIM(base, value) (BME_BFI32(&TRNG_SBLIM_REG(base), ((uint32_t)(value) << …
25116 #define TRNG_BWR_SCML_MONO_MAX(base, value) (BME_BFI32(&TRNG_SCML_REG(base), ((uint32_t)(value) << …
25134 #define TRNG_BWR_SCML_MONO_RNG(base, value) (BME_BFI32(&TRNG_SCML_REG(base), ((uint32_t)(value) << …
25189 #define TRNG_BWR_SCR1L_RUN1_MAX(base, value) (BME_BFI32(&TRNG_SCR1L_REG(base), ((uint32_t)(value) <…
25207 #define TRNG_BWR_SCR1L_RUN1_RNG(base, value) (BME_BFI32(&TRNG_SCR1L_REG(base), ((uint32_t)(value) <…
25315 #define TRNG_BWR_SCR2L_RUN2_MAX(base, value) (BME_BFI32(&TRNG_SCR2L_REG(base), ((uint32_t)(value) <…
25333 #define TRNG_BWR_SCR2L_RUN2_RNG(base, value) (BME_BFI32(&TRNG_SCR2L_REG(base), ((uint32_t)(value) <…
25494 #define TRNG_BWR_SCR3L_RUN3_MAX(base, value) (BME_BFI32(&TRNG_SCR3L_REG(base), ((uint32_t)(value) <…
25512 #define TRNG_BWR_SCR3L_RUN3_RNG(base, value) (BME_BFI32(&TRNG_SCR3L_REG(base), ((uint32_t)(value) <…
25620 #define TRNG_BWR_SCR4L_RUN4_MAX(base, value) (BME_BFI32(&TRNG_SCR4L_REG(base), ((uint32_t)(value) <…
25638 #define TRNG_BWR_SCR4L_RUN4_RNG(base, value) (BME_BFI32(&TRNG_SCR4L_REG(base), ((uint32_t)(value) <…
25693 #define TRNG_BWR_SCR5L_RUN5_MAX(base, value) (BME_BFI32(&TRNG_SCR5L_REG(base), ((uint32_t)(value) <…
25711 #define TRNG_BWR_SCR5L_RUN5_RNG(base, value) (BME_BFI32(&TRNG_SCR5L_REG(base), ((uint32_t)(value) <…
25819 #define TRNG_BWR_SCR6PL_RUN6P_MAX(base, value) (BME_BFI32(&TRNG_SCR6PL_REG(base), ((uint32_t)(value…
25837 #define TRNG_BWR_SCR6PL_RUN6P_RNG(base, value) (BME_BFI32(&TRNG_SCR6PL_REG(base), ((uint32_t)(value…
26613 #define TRNG_BWR_SEC_CFG_SH0(base, value) (BME_BFI32(&TRNG_SEC_CFG_REG(base), ((uint32_t)(value) <<…
26635 #define TRNG_BWR_SEC_CFG_NO_PRGM(base, value) (BME_BFI32(&TRNG_SEC_CFG_REG(base), ((uint32_t)(value…
26654 #define TRNG_BWR_SEC_CFG_SK_VAL(base, value) (BME_BFI32(&TRNG_SEC_CFG_REG(base), ((uint32_t)(value)…
26707 #define TRNG_BWR_INT_CTRL_HW_ERR(base, value) (BME_BFI32(&TRNG_INT_CTRL_REG(base), ((uint32_t)(valu…
26726 #define TRNG_BWR_INT_CTRL_ENT_VAL(base, value) (BME_BFI32(&TRNG_INT_CTRL_REG(base), ((uint32_t)(val…
26745 #define TRNG_BWR_INT_CTRL_FRQ_CT_FAIL(base, value) (BME_BFI32(&TRNG_INT_CTRL_REG(base), ((uint32_t)…
26813 #define TRNG_BWR_INT_MASK_HW_ERR(base, value) (BME_BFI32(&TRNG_INT_MASK_REG(base), ((uint32_t)(valu…
26832 #define TRNG_BWR_INT_MASK_ENT_VAL(base, value) (BME_BFI32(&TRNG_INT_MASK_REG(base), ((uint32_t)(val…
26851 #define TRNG_BWR_INT_MASK_FRQ_CT_FAIL(base, value) (BME_BFI32(&TRNG_INT_MASK_REG(base), ((uint32_t)…
26942 #define TRNG_BWR_INT_STATUS_FRQ_CT_FAIL(base, value) (BME_BFI32(&TRNG_INT_STATUS_REG(base), ((uint3…
27149 #define TSI_BWR_GENCS_CURSW(base, value) (BME_BFI32(&TSI_GENCS_REG(base), ((uint32_t)(value) << TSI…
27169 #define TSI_BWR_GENCS_EOSF(base, value) (BME_BFI32(&TSI_GENCS_REG(base), ((uint32_t)(value) << TSI_…
27206 #define TSI_BWR_GENCS_STM(base, value) (BME_BFI32(&TSI_GENCS_REG(base), ((uint32_t)(value) << TSI_G…
27226 #define TSI_BWR_GENCS_STPE(base, value) (BME_BFI32(&TSI_GENCS_REG(base), ((uint32_t)(value) << TSI_…
27246 #define TSI_BWR_GENCS_TSIIEN(base, value) (BME_BFI32(&TSI_GENCS_REG(base), ((uint32_t)(value) << TS…
27265 #define TSI_BWR_GENCS_TSIEN(base, value) (BME_BFI32(&TSI_GENCS_REG(base), ((uint32_t)(value) << TSI…
27317 #define TSI_BWR_GENCS_NSCN(base, value) (BME_BFI32(&TSI_GENCS_REG(base), ((uint32_t)(value) << TSI_…
27342 #define TSI_BWR_GENCS_PS(base, value) (BME_BFI32(&TSI_GENCS_REG(base), ((uint32_t)(value) << TSI_GE…
27368 #define TSI_BWR_GENCS_EXTCHRG(base, value) (BME_BFI32(&TSI_GENCS_REG(base), ((uint32_t)(value) << T…
27389 #define TSI_BWR_GENCS_DVOLT(base, value) (BME_BFI32(&TSI_GENCS_REG(base), ((uint32_t)(value) << TSI…
27415 #define TSI_BWR_GENCS_REFCHRG(base, value) (BME_BFI32(&TSI_GENCS_REG(base), ((uint32_t)(value) << T…
27443 #define TSI_BWR_GENCS_MODE(base, value) (BME_BFI32(&TSI_GENCS_REG(base), ((uint32_t)(value) << TSI_…
27463 #define TSI_BWR_GENCS_ESOR(base, value) (BME_BFI32(&TSI_GENCS_REG(base), ((uint32_t)(value) << TSI_…
27481 #define TSI_BWR_GENCS_OUTRGF(base, value) (BME_BFI32(&TSI_GENCS_REG(base), ((uint32_t)(value) << TS…
27536 #define TSI_BWR_DATA_SWTS(base, value) (BME_BFI32(&TSI_DATA_REG(base), ((uint32_t)(value) << TSI_DA…
27558 #define TSI_BWR_DATA_DMAEN(base, value) (BME_BFI32(&TSI_DATA_REG(base), ((uint32_t)(value) << TSI_D…
27594 #define TSI_BWR_DATA_TSICH(base, value) (BME_BFI32(&TSI_DATA_REG(base), ((uint32_t)(value) << TSI_D…
27634 #define TSI_BWR_TSHD_THRESL(base, value) (BME_BFI32(&TSI_TSHD_REG(base), ((uint32_t)(value) << TSI_…
27649 #define TSI_BWR_TSHD_THRESH(base, value) (BME_BFI32(&TSI_TSHD_REG(base), ((uint32_t)(value) << TSI_…
27868 #define XCVR_BWR_RX_DIG_CTRL_RX_ADC_NEGEDGE(base, value) (BME_BFI32(&XCVR_RX_DIG_CTRL_REG(base), ((…
27887 #define XCVR_BWR_RX_DIG_CTRL_RX_CH_FILT_BYPASS(base, value) (BME_BFI32(&XCVR_RX_DIG_CTRL_REG(base),…
27906 #define XCVR_BWR_RX_DIG_CTRL_RX_ADC_RAW_EN(base, value) (BME_BFI32(&XCVR_RX_DIG_CTRL_REG(base), ((u…
27925 #define XCVR_BWR_RX_DIG_CTRL_RX_DEC_FILT_OSR(base, value) (BME_BFI32(&XCVR_RX_DIG_CTRL_REG(base), (…
27942 #define XCVR_BWR_RX_DIG_CTRL_RX_INTERP_EN(base, value) (BME_BFI32(&XCVR_RX_DIG_CTRL_REG(base), ((ui…
27959 #define XCVR_BWR_RX_DIG_CTRL_RX_NORM_EN(base, value) (BME_BFI32(&XCVR_RX_DIG_CTRL_REG(base), ((uint…
27976 #define XCVR_BWR_RX_DIG_CTRL_RX_RSSI_EN(base, value) (BME_BFI32(&XCVR_RX_DIG_CTRL_REG(base), ((uint…
27995 #define XCVR_BWR_RX_DIG_CTRL_RX_AGC_EN(base, value) (BME_BFI32(&XCVR_RX_DIG_CTRL_REG(base), ((uint3…
28014 #define XCVR_BWR_RX_DIG_CTRL_RX_DCOC_EN(base, value) (BME_BFI32(&XCVR_RX_DIG_CTRL_REG(base), ((uint…
28033 #define XCVR_BWR_RX_DIG_CTRL_RX_DCOC_CAL_EN(base, value) (BME_BFI32(&XCVR_RX_DIG_CTRL_REG(base), ((…
28052 #define XCVR_BWR_RX_DIG_CTRL_RX_IQ_SWAP(base, value) (BME_BFI32(&XCVR_RX_DIG_CTRL_REG(base), ((uint…
28092 #define XCVR_BWR_AGC_CTRL_0_SLOW_AGC_EN(base, value) (BME_BFI32(&XCVR_AGC_CTRL_0_REG(base), ((uint3…
28111 #define XCVR_BWR_AGC_CTRL_0_SLOW_AGC_SRC(base, value) (BME_BFI32(&XCVR_AGC_CTRL_0_REG(base), ((uint…
28127 #define XCVR_BWR_AGC_CTRL_0_AGC_FREEZE_EN(base, value) (BME_BFI32(&XCVR_AGC_CTRL_0_REG(base), ((uin…
28146 #define XCVR_BWR_AGC_CTRL_0_FREEZE_AGC_SRC(base, value) (BME_BFI32(&XCVR_AGC_CTRL_0_REG(base), ((ui…
28161 #define XCVR_BWR_AGC_CTRL_0_AGC_UP_EN(base, value) (BME_BFI32(&XCVR_AGC_CTRL_0_REG(base), ((uint32_…
28180 #define XCVR_BWR_AGC_CTRL_0_AGC_UP_SRC(base, value) (BME_BFI32(&XCVR_AGC_CTRL_0_REG(base), ((uint32…
28195 #define XCVR_BWR_AGC_CTRL_0_AGC_DOWN_BBF_STEP_SZ(base, value) (BME_BFI32(&XCVR_AGC_CTRL_0_REG(base)…
28210 #define XCVR_BWR_AGC_CTRL_0_AGC_DOWN_TZA_STEP_SZ(base, value) (BME_BFI32(&XCVR_AGC_CTRL_0_REG(base)…
28225 #define XCVR_BWR_AGC_CTRL_0_AGC_UP_RSSI_THRESH(base, value) (BME_BFI32(&XCVR_AGC_CTRL_0_REG(base), …
28240 #define XCVR_BWR_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(base, value) (BME_BFI32(&XCVR_AGC_CTRL_0_REG(base)…
28281 #define XCVR_BWR_AGC_CTRL_1_BBF_ALT_CODE(base, value) (BME_BFI32(&XCVR_AGC_CTRL_1_REG(base), ((uint…
28297 #define XCVR_BWR_AGC_CTRL_1_LNM_ALT_CODE(base, value) (BME_BFI32(&XCVR_AGC_CTRL_1_REG(base), ((uint…
28312 #define XCVR_BWR_AGC_CTRL_1_LNM_USER_GAIN(base, value) (BME_BFI32(&XCVR_AGC_CTRL_1_REG(base), ((uin…
28327 #define XCVR_BWR_AGC_CTRL_1_BBF_USER_GAIN(base, value) (BME_BFI32(&XCVR_AGC_CTRL_1_REG(base), ((uin…
28342 #define XCVR_BWR_AGC_CTRL_1_USER_LNM_GAIN_EN(base, value) (BME_BFI32(&XCVR_AGC_CTRL_1_REG(base), ((…
28357 #define XCVR_BWR_AGC_CTRL_1_USER_BBF_GAIN_EN(base, value) (BME_BFI32(&XCVR_AGC_CTRL_1_REG(base), ((…
28376 #define XCVR_BWR_AGC_CTRL_1_PRESLOW_EN(base, value) (BME_BFI32(&XCVR_AGC_CTRL_1_REG(base), ((uint32…
28391 #define XCVR_BWR_AGC_CTRL_1_TZA_GAIN_SETTLE_TIME(base, value) (BME_BFI32(&XCVR_AGC_CTRL_1_REG(base)…
28431 #define XCVR_BWR_AGC_CTRL_2_BBF_PDET_RST(base, value) (BME_BFI32(&XCVR_AGC_CTRL_2_REG(base), ((uint…
28446 #define XCVR_BWR_AGC_CTRL_2_TZA_PDET_RST(base, value) (BME_BFI32(&XCVR_AGC_CTRL_2_REG(base), ((uint…
28461 #define XCVR_BWR_AGC_CTRL_2_BBF_GAIN_SETTLE_TIME(base, value) (BME_BFI32(&XCVR_AGC_CTRL_2_REG(base)…
28486 #define XCVR_BWR_AGC_CTRL_2_BBF_PDET_THRESH_LO(base, value) (BME_BFI32(&XCVR_AGC_CTRL_2_REG(base), …
28511 #define XCVR_BWR_AGC_CTRL_2_BBF_PDET_THRESH_HI(base, value) (BME_BFI32(&XCVR_AGC_CTRL_2_REG(base), …
28536 #define XCVR_BWR_AGC_CTRL_2_TZA_PDET_THRESH_LO(base, value) (BME_BFI32(&XCVR_AGC_CTRL_2_REG(base), …
28561 #define XCVR_BWR_AGC_CTRL_2_TZA_PDET_THRESH_HI(base, value) (BME_BFI32(&XCVR_AGC_CTRL_2_REG(base), …
28576 #define XCVR_BWR_AGC_CTRL_2_AGC_FAST_EXPIRE(base, value) (BME_BFI32(&XCVR_AGC_CTRL_2_REG(base), ((u…
28616 #define XCVR_BWR_AGC_CTRL_3_AGC_UNFREEZE_TIME(base, value) (BME_BFI32(&XCVR_AGC_CTRL_3_REG(base), (…
28631 #define XCVR_BWR_AGC_CTRL_3_AGC_PDET_LO_DLY(base, value) (BME_BFI32(&XCVR_AGC_CTRL_3_REG(base), ((u…
28646 #define XCVR_BWR_AGC_CTRL_3_AGC_RSSI_DELT_H2S(base, value) (BME_BFI32(&XCVR_AGC_CTRL_3_REG(base), (…
28661 #define XCVR_BWR_AGC_CTRL_3_AGC_H2S_STEP_SZ(base, value) (BME_BFI32(&XCVR_AGC_CTRL_3_REG(base), ((u…
28676 #define XCVR_BWR_AGC_CTRL_3_AGC_UP_STEP_SZ(base, value) (BME_BFI32(&XCVR_AGC_CTRL_3_REG(base), ((ui…
28817 #define XCVR_BWR_RSSI_CTRL_0_RSSI_USE_VALS(base, value) (BME_BFI32(&XCVR_RSSI_CTRL_0_REG(base), ((u…
28836 #define XCVR_BWR_RSSI_CTRL_0_RSSI_HOLD_SRC(base, value) (BME_BFI32(&XCVR_RSSI_CTRL_0_REG(base), ((u…
28852 #define XCVR_BWR_RSSI_CTRL_0_RSSI_HOLD_EN(base, value) (BME_BFI32(&XCVR_RSSI_CTRL_0_REG(base), ((ui…
28867 #define XCVR_BWR_RSSI_CTRL_0_RSSI_DEC_EN(base, value) (BME_BFI32(&XCVR_RSSI_CTRL_0_REG(base), ((uin…
28886 #define XCVR_BWR_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT(base, value) (BME_BFI32(&XCVR_RSSI_CTRL_0_REG(base)…
28905 #define XCVR_BWR_RSSI_CTRL_0_RSSI_IIR_WEIGHT(base, value) (BME_BFI32(&XCVR_RSSI_CTRL_0_REG(base), (…
28920 #define XCVR_BWR_RSSI_CTRL_0_RSSI_ADJ(base, value) (BME_BFI32(&XCVR_RSSI_CTRL_0_REG(base), ((uint32…
28960 #define XCVR_BWR_RSSI_CTRL_1_RSSI_ED_THRESH0(base, value) (BME_BFI32(&XCVR_RSSI_CTRL_1_REG(base), (…
28975 #define XCVR_BWR_RSSI_CTRL_1_RSSI_ED_THRESH1(base, value) (BME_BFI32(&XCVR_RSSI_CTRL_1_REG(base), (…
28990 #define XCVR_BWR_RSSI_CTRL_1_RSSI_ED_THRESH0_H(base, value) (BME_BFI32(&XCVR_RSSI_CTRL_1_REG(base),…
29005 #define XCVR_BWR_RSSI_CTRL_1_RSSI_ED_THRESH1_H(base, value) (BME_BFI32(&XCVR_RSSI_CTRL_1_REG(base),…
29058 #define XCVR_BWR_DCOC_CTRL_0_DCOC_MAN(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_0_REG(base), ((uint32…
29074 #define XCVR_BWR_DCOC_CTRL_0_DCOC_TRACK_EN(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_0_REG(base), ((u…
29089 #define XCVR_BWR_DCOC_CTRL_0_DCOC_CORRECT_EN(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_0_REG(base), (…
29111 #define XCVR_BWR_DCOC_CTRL_0_DCOC_SIGN_SCALE_IDX(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_0_REG(base…
29133 #define XCVR_BWR_DCOC_CTRL_0_DCOC_ALPHAC_SCALE_IDX(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_0_REG(ba…
29159 #define XCVR_BWR_DCOC_CTRL_0_DCOC_ALPHA_RADIUS_IDX(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_0_REG(ba…
29174 #define XCVR_BWR_DCOC_CTRL_0_DCOC_CAL_DURATION(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_0_REG(base),…
29190 #define XCVR_BWR_DCOC_CTRL_0_DCOC_CORR_DLY(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_0_REG(base), ((u…
29206 #define XCVR_BWR_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_0_REG(base…
29250 #define XCVR_BWR_DCOC_CTRL_1_BBF_DCOC_STEP(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_1_REG(base), ((u…
29270 #define XCVR_BWR_DCOC_CTRL_1_TRACK_FROM_ZERO(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_1_REG(base), (…
29290 #define XCVR_BWR_DCOC_CTRL_1_BBA_CORR_POL(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_1_REG(base), ((ui…
29310 #define XCVR_BWR_DCOC_CTRL_1_TZA_CORR_POL(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_1_REG(base), ((ui…
29353 #define XCVR_BWR_DCOC_CTRL_2_BBF_DCOC_STEP_RECIP(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_2_REG(base…
29393 #define XCVR_BWR_DCOC_CTRL_3_BBF_DCOC_INIT_I(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_3_REG(base), (…
29408 #define XCVR_BWR_DCOC_CTRL_3_BBF_DCOC_INIT_Q(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_3_REG(base), (…
29423 #define XCVR_BWR_DCOC_CTRL_3_TZA_DCOC_INIT_I(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_3_REG(base), (…
29438 #define XCVR_BWR_DCOC_CTRL_3_TZA_DCOC_INIT_Q(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_3_REG(base), (…
29479 #define XCVR_BWR_DCOC_CTRL_4_DIG_DCOC_INIT_I(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_4_REG(base), (…
29495 #define XCVR_BWR_DCOC_CTRL_4_DIG_DCOC_INIT_Q(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_4_REG(base), (…
29536 #define XCVR_BWR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN1(base, value) (BME_BFI32(&XCVR_DCOC_CAL_GAIN_REG(b…
29552 #define XCVR_BWR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN1(base, value) (BME_BFI32(&XCVR_DCOC_CAL_GAIN_REG(b…
29568 #define XCVR_BWR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN2(base, value) (BME_BFI32(&XCVR_DCOC_CAL_GAIN_REG(b…
29584 #define XCVR_BWR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN2(base, value) (BME_BFI32(&XCVR_DCOC_CAL_GAIN_REG(b…
29600 #define XCVR_BWR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN3(base, value) (BME_BFI32(&XCVR_DCOC_CAL_GAIN_REG(b…
29616 #define XCVR_BWR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN3(base, value) (BME_BFI32(&XCVR_DCOC_CAL_GAIN_REG(b…
29778 #define XCVR_BWR_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP(base, value) (BME_BFI32(&XCVR_DCOC_CAL_RCP_REG(ba…
29796 #define XCVR_BWR_DCOC_CAL_RCP_ALPHA_CALC_RECIP(base, value) (BME_BFI32(&XCVR_DCOC_CAL_RCP_REG(base)…
29836 #define XCVR_BWR_IQMC_CTRL_IQMC_CAL_EN(base, value) (BME_BFI32(&XCVR_IQMC_CTRL_REG(base), ((uint32_…
29851 #define XCVR_BWR_IQMC_CTRL_IQMC_NUM_ITER(base, value) (BME_BFI32(&XCVR_IQMC_CTRL_REG(base), ((uint3…
29891 #define XCVR_BWR_IQMC_CAL_IQMC_GAIN_ADJ(base, value) (BME_BFI32(&XCVR_IQMC_CAL_REG(base), ((uint32_…
29906 #define XCVR_BWR_IQMC_CAL_IQMC_PHASE_ADJ(base, value) (BME_BFI32(&XCVR_IQMC_CAL_REG(base), ((uint32…
29946 #define XCVR_BWR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_0(base, value) (BME_BFI32(&XCVR_TCA_AGC_VAL_3_0_REG(ba…
29961 #define XCVR_BWR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_1(base, value) (BME_BFI32(&XCVR_TCA_AGC_VAL_3_0_REG(ba…
29976 #define XCVR_BWR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_2(base, value) (BME_BFI32(&XCVR_TCA_AGC_VAL_3_0_REG(ba…
29991 #define XCVR_BWR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_3(base, value) (BME_BFI32(&XCVR_TCA_AGC_VAL_3_0_REG(ba…
30031 #define XCVR_BWR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_4(base, value) (BME_BFI32(&XCVR_TCA_AGC_VAL_7_4_REG(ba…
30046 #define XCVR_BWR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_5(base, value) (BME_BFI32(&XCVR_TCA_AGC_VAL_7_4_REG(ba…
30061 #define XCVR_BWR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_6(base, value) (BME_BFI32(&XCVR_TCA_AGC_VAL_7_4_REG(ba…
30076 #define XCVR_BWR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_7(base, value) (BME_BFI32(&XCVR_TCA_AGC_VAL_7_4_REG(ba…
30116 #define XCVR_BWR_TCA_AGC_VAL_8_TCA_AGC_VAL_8(base, value) (BME_BFI32(&XCVR_TCA_AGC_VAL_8_REG(base),…
30156 #define XCVR_BWR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_0(base, value) (BME_BFI32(&XCVR_BBF_RES_TUNE…
30171 #define XCVR_BWR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_1(base, value) (BME_BFI32(&XCVR_BBF_RES_TUNE…
30186 #define XCVR_BWR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_2(base, value) (BME_BFI32(&XCVR_BBF_RES_TUNE…
30201 #define XCVR_BWR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_3(base, value) (BME_BFI32(&XCVR_BBF_RES_TUNE…
30216 #define XCVR_BWR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_4(base, value) (BME_BFI32(&XCVR_BBF_RES_TUNE…
30231 #define XCVR_BWR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_5(base, value) (BME_BFI32(&XCVR_BBF_RES_TUNE…
30246 #define XCVR_BWR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_6(base, value) (BME_BFI32(&XCVR_BBF_RES_TUNE…
30261 #define XCVR_BWR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_7(base, value) (BME_BFI32(&XCVR_BBF_RES_TUNE…
30301 #define XCVR_BWR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_8(base, value) (BME_BFI32(&XCVR_BBF_RES_TUN…
30316 #define XCVR_BWR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_9(base, value) (BME_BFI32(&XCVR_BBF_RES_TUN…
30331 #define XCVR_BWR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_10(base, value) (BME_BFI32(&XCVR_BBF_RES_TU…
30371 #define XCVR_BWR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_0(base, value) (BME_BFI32(&XCVR_TCA_AGC_LIN_VA…
30387 #define XCVR_BWR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_1(base, value) (BME_BFI32(&XCVR_TCA_AGC_LIN_VA…
30403 #define XCVR_BWR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_2(base, value) (BME_BFI32(&XCVR_TCA_AGC_LIN_VA…
30444 #define XCVR_BWR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_3(base, value) (BME_BFI32(&XCVR_TCA_AGC_LIN_VA…
30460 #define XCVR_BWR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_4(base, value) (BME_BFI32(&XCVR_TCA_AGC_LIN_VA…
30476 #define XCVR_BWR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_5(base, value) (BME_BFI32(&XCVR_TCA_AGC_LIN_VA…
30517 #define XCVR_BWR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_6(base, value) (BME_BFI32(&XCVR_TCA_AGC_LIN_VA…
30533 #define XCVR_BWR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_7(base, value) (BME_BFI32(&XCVR_TCA_AGC_LIN_VA…
30549 #define XCVR_BWR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_8(base, value) (BME_BFI32(&XCVR_TCA_AGC_LIN_VA…
30590 #define XCVR_BWR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_0(base, value) (BME_BFI32(&XCVR_BBF_…
30606 #define XCVR_BWR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_1(base, value) (BME_BFI32(&XCVR_BBF_…
30622 #define XCVR_BWR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_2(base, value) (BME_BFI32(&XCVR_BBF_…
30638 #define XCVR_BWR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_3(base, value) (BME_BFI32(&XCVR_BBF_…
30679 #define XCVR_BWR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_4(base, value) (BME_BFI32(&XCVR_BBF_…
30695 #define XCVR_BWR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_5(base, value) (BME_BFI32(&XCVR_BBF_…
30711 #define XCVR_BWR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_6(base, value) (BME_BFI32(&XCVR_BBF_…
30727 #define XCVR_BWR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_7(base, value) (BME_BFI32(&XCVR_BBF_…
30768 #define XCVR_BWR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_8(base, value) (BME_BFI32(&XCVR_BBF…
30784 #define XCVR_BWR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_9(base, value) (BME_BFI32(&XCVR_BBF…
30800 #define XCVR_BWR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_10(base, value) (BME_BFI32(&XCVR_BB…
30840 #define XCVR_BWR_AGC_GAIN_TBL_03_00_BBF_GAIN_00(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_03_00_RE…
30855 #define XCVR_BWR_AGC_GAIN_TBL_03_00_LNM_GAIN_00(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_03_00_RE…
30870 #define XCVR_BWR_AGC_GAIN_TBL_03_00_BBF_GAIN_01(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_03_00_RE…
30885 #define XCVR_BWR_AGC_GAIN_TBL_03_00_LNM_GAIN_01(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_03_00_RE…
30900 #define XCVR_BWR_AGC_GAIN_TBL_03_00_BBF_GAIN_02(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_03_00_RE…
30915 #define XCVR_BWR_AGC_GAIN_TBL_03_00_LNM_GAIN_02(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_03_00_RE…
30930 #define XCVR_BWR_AGC_GAIN_TBL_03_00_BBF_GAIN_03(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_03_00_RE…
30945 #define XCVR_BWR_AGC_GAIN_TBL_03_00_LNM_GAIN_03(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_03_00_RE…
30985 #define XCVR_BWR_AGC_GAIN_TBL_07_04_BBF_GAIN_04(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_07_04_RE…
31000 #define XCVR_BWR_AGC_GAIN_TBL_07_04_LNM_GAIN_04(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_07_04_RE…
31015 #define XCVR_BWR_AGC_GAIN_TBL_07_04_BBF_GAIN_05(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_07_04_RE…
31030 #define XCVR_BWR_AGC_GAIN_TBL_07_04_LNM_GAIN_05(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_07_04_RE…
31045 #define XCVR_BWR_AGC_GAIN_TBL_07_04_BBF_GAIN_06(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_07_04_RE…
31060 #define XCVR_BWR_AGC_GAIN_TBL_07_04_LNM_GAIN_06(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_07_04_RE…
31075 #define XCVR_BWR_AGC_GAIN_TBL_07_04_BBF_GAIN_07(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_07_04_RE…
31090 #define XCVR_BWR_AGC_GAIN_TBL_07_04_LNM_GAIN_07(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_07_04_RE…
31130 #define XCVR_BWR_AGC_GAIN_TBL_11_08_BBF_GAIN_08(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_11_08_RE…
31145 #define XCVR_BWR_AGC_GAIN_TBL_11_08_LNM_GAIN_08(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_11_08_RE…
31160 #define XCVR_BWR_AGC_GAIN_TBL_11_08_BBF_GAIN_09(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_11_08_RE…
31175 #define XCVR_BWR_AGC_GAIN_TBL_11_08_LNM_GAIN_09(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_11_08_RE…
31190 #define XCVR_BWR_AGC_GAIN_TBL_11_08_BBF_GAIN_10(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_11_08_RE…
31205 #define XCVR_BWR_AGC_GAIN_TBL_11_08_LNM_GAIN_10(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_11_08_RE…
31220 #define XCVR_BWR_AGC_GAIN_TBL_11_08_BBF_GAIN_11(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_11_08_RE…
31235 #define XCVR_BWR_AGC_GAIN_TBL_11_08_LNM_GAIN_11(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_11_08_RE…
31275 #define XCVR_BWR_AGC_GAIN_TBL_15_12_BBF_GAIN_12(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_15_12_RE…
31290 #define XCVR_BWR_AGC_GAIN_TBL_15_12_LNM_GAIN_12(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_15_12_RE…
31305 #define XCVR_BWR_AGC_GAIN_TBL_15_12_BBF_GAIN_13(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_15_12_RE…
31320 #define XCVR_BWR_AGC_GAIN_TBL_15_12_LNM_GAIN_13(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_15_12_RE…
31335 #define XCVR_BWR_AGC_GAIN_TBL_15_12_BBF_GAIN_14(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_15_12_RE…
31350 #define XCVR_BWR_AGC_GAIN_TBL_15_12_LNM_GAIN_14(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_15_12_RE…
31365 #define XCVR_BWR_AGC_GAIN_TBL_15_12_BBF_GAIN_15(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_15_12_RE…
31380 #define XCVR_BWR_AGC_GAIN_TBL_15_12_LNM_GAIN_15(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_15_12_RE…
31420 #define XCVR_BWR_AGC_GAIN_TBL_19_16_BBF_GAIN_16(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_19_16_RE…
31435 #define XCVR_BWR_AGC_GAIN_TBL_19_16_LNM_GAIN_16(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_19_16_RE…
31450 #define XCVR_BWR_AGC_GAIN_TBL_19_16_BBF_GAIN_17(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_19_16_RE…
31465 #define XCVR_BWR_AGC_GAIN_TBL_19_16_LNM_GAIN_17(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_19_16_RE…
31480 #define XCVR_BWR_AGC_GAIN_TBL_19_16_BBF_GAIN_18(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_19_16_RE…
31495 #define XCVR_BWR_AGC_GAIN_TBL_19_16_LNM_GAIN_18(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_19_16_RE…
31510 #define XCVR_BWR_AGC_GAIN_TBL_19_16_BBF_GAIN_19(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_19_16_RE…
31525 #define XCVR_BWR_AGC_GAIN_TBL_19_16_LNM_GAIN_19(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_19_16_RE…
31565 #define XCVR_BWR_AGC_GAIN_TBL_23_20_BBF_GAIN_20(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_23_20_RE…
31580 #define XCVR_BWR_AGC_GAIN_TBL_23_20_LNM_GAIN_20(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_23_20_RE…
31595 #define XCVR_BWR_AGC_GAIN_TBL_23_20_BBF_GAIN_21(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_23_20_RE…
31610 #define XCVR_BWR_AGC_GAIN_TBL_23_20_LNM_GAIN_21(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_23_20_RE…
31625 #define XCVR_BWR_AGC_GAIN_TBL_23_20_BBF_GAIN_22(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_23_20_RE…
31640 #define XCVR_BWR_AGC_GAIN_TBL_23_20_LNM_GAIN_22(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_23_20_RE…
31655 #define XCVR_BWR_AGC_GAIN_TBL_23_20_BBF_GAIN_23(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_23_20_RE…
31670 #define XCVR_BWR_AGC_GAIN_TBL_23_20_LNM_GAIN_23(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_23_20_RE…
31710 #define XCVR_BWR_AGC_GAIN_TBL_26_24_BBF_GAIN_24(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_26_24_RE…
31725 #define XCVR_BWR_AGC_GAIN_TBL_26_24_LNM_GAIN_24(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_26_24_RE…
31740 #define XCVR_BWR_AGC_GAIN_TBL_26_24_BBF_GAIN_25(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_26_24_RE…
31755 #define XCVR_BWR_AGC_GAIN_TBL_26_24_LNM_GAIN_25(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_26_24_RE…
31770 #define XCVR_BWR_AGC_GAIN_TBL_26_24_BBF_GAIN_26(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_26_24_RE…
31785 #define XCVR_BWR_AGC_GAIN_TBL_26_24_LNM_GAIN_26(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_26_24_RE…
31827 #define XCVR_BWR_DCOC_OFFSET__DCOC_BBF_OFFSET_I(base, index, value) (BME_BFI32(&XCVR_DCOC_OFFSET__R…
31844 #define XCVR_BWR_DCOC_OFFSET__DCOC_BBF_OFFSET_Q(base, index, value) (BME_BFI32(&XCVR_DCOC_OFFSET__R…
31861 #define XCVR_BWR_DCOC_OFFSET__DCOC_TZA_OFFSET_I(base, index, value) (BME_BFI32(&XCVR_DCOC_OFFSET__R…
31878 #define XCVR_BWR_DCOC_OFFSET__DCOC_TZA_OFFSET_Q(base, index, value) (BME_BFI32(&XCVR_DCOC_OFFSET__R…
31921 #define XCVR_BWR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP(base, index, value) (BME_BFI32(&XCVR_DCOC_TZA_STE…
31941 #define XCVR_BWR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN(base, index, value) (BME_BFI32(&XCVR_DCOC_TZA_ST…
32124 #define XCVR_BWR_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(base, value) (BME_BFI32(&XCVR_DCOC_CAL_IIR_REG(bas…
32144 #define XCVR_BWR_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(base, value) (BME_BFI32(&XCVR_DCOC_CAL_IIR_REG(bas…
32164 #define XCVR_BWR_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(base, value) (BME_BFI32(&XCVR_DCOC_CAL_IIR_REG(bas…
32254 #define XCVR_BWR_RX_CHF_COEF_RX_CH_FILT_HX(base, index, value) (BME_BFI32(&XCVR_RX_CHF_COEF_REG(bas…
32318 #define XCVR_BWR_TX_DIG_CTRL_DFT_MODE(base, value) (BME_BFI32(&XCVR_TX_DIG_CTRL_REG(base), ((uint32…
32334 #define XCVR_BWR_TX_DIG_CTRL_DFT_EN(base, value) (BME_BFI32(&XCVR_TX_DIG_CTRL_REG(base), ((uint32_t…
32360 #define XCVR_BWR_TX_DIG_CTRL_DFT_LFSR_LEN(base, value) (BME_BFI32(&XCVR_TX_DIG_CTRL_REG(base), ((ui…
32379 #define XCVR_BWR_TX_DIG_CTRL_LFSR_EN(base, value) (BME_BFI32(&XCVR_TX_DIG_CTRL_REG(base), ((uint32_…
32405 #define XCVR_BWR_TX_DIG_CTRL_DFT_CLK_SEL(base, value) (BME_BFI32(&XCVR_TX_DIG_CTRL_REG(base), ((uin…
32431 #define XCVR_BWR_TX_DIG_CTRL_TONE_SEL(base, value) (BME_BFI32(&XCVR_TX_DIG_CTRL_REG(base), ((uint32…
32454 #define XCVR_BWR_TX_DIG_CTRL_POL(base, value) (BME_BFI32(&XCVR_TX_DIG_CTRL_REG(base), ((uint32_t)(v…
32480 #define XCVR_BWR_TX_DIG_CTRL_DP_SEL(base, value) (BME_BFI32(&XCVR_TX_DIG_CTRL_REG(base), ((uint32_t…
32497 #define XCVR_BWR_TX_DIG_CTRL_FREQ_WORD_ADJ(base, value) (BME_BFI32(&XCVR_TX_DIG_CTRL_REG(base), ((u…
32538 #define XCVR_BWR_TX_DATA_PAD_PAT_DATA_PADDING_PAT_0(base, value) (BME_BFI32(&XCVR_TX_DATA_PAD_PAT_R…
32554 #define XCVR_BWR_TX_DATA_PAD_PAT_DATA_PADDING_PAT_1(base, value) (BME_BFI32(&XCVR_TX_DATA_PAD_PAT_R…
32584 #define XCVR_BWR_TX_DATA_PAD_PAT_LRM(base, value) (BME_BFI32(&XCVR_TX_DATA_PAD_PAT_REG(base), ((uin…
32630 #define XCVR_BWR_TX_GFSK_MOD_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(base, value) (BME_BFI32(&XCVR_TX_GFSK_…
32653 #define XCVR_BWR_TX_GFSK_MOD_CTRL_GFSK_MI(base, value) (BME_BFI32(&XCVR_TX_GFSK_MOD_CTRL_REG(base),…
32669 #define XCVR_BWR_TX_GFSK_MOD_CTRL_GFSK_MLD(base, value) (BME_BFI32(&XCVR_TX_GFSK_MOD_CTRL_REG(base)…
32696 #define XCVR_BWR_TX_GFSK_MOD_CTRL_GFSK_SYMBOL_RATE(base, value) (BME_BFI32(&XCVR_TX_GFSK_MOD_CTRL_R…
32714 #define XCVR_BWR_TX_GFSK_MOD_CTRL_GFSK_FLD(base, value) (BME_BFI32(&XCVR_TX_GFSK_MOD_CTRL_REG(base)…
32814 #define XCVR_BWR_TX_FSK_MOD_SCALE_FSK_MODULATION_SCALE_0(base, value) (BME_BFI32(&XCVR_TX_FSK_MOD_S…
32837 #define XCVR_BWR_TX_FSK_MOD_SCALE_FSK_MODULATION_SCALE_1(base, value) (BME_BFI32(&XCVR_TX_FSK_MOD_S…
32907 #define XCVR_BWR_TX_DFT_TONE_0_1_DFT_TONE_1(base, value) (BME_BFI32(&XCVR_TX_DFT_TONE_0_1_REG(base)…
32926 #define XCVR_BWR_TX_DFT_TONE_0_1_DFT_TONE_0(base, value) (BME_BFI32(&XCVR_TX_DFT_TONE_0_1_REG(base)…
32975 #define XCVR_BWR_TX_DFT_TONE_2_3_DFT_TONE_3(base, value) (BME_BFI32(&XCVR_TX_DFT_TONE_2_3_REG(base)…
32994 #define XCVR_BWR_TX_DFT_TONE_2_3_DFT_TONE_2(base, value) (BME_BFI32(&XCVR_TX_DFT_TONE_2_3_REG(base)…
33035 #define XCVR_BWR_PLL_MOD_OVRD_MODULATION_WORD_MANUAL(base, value) (BME_BFI32(&XCVR_PLL_MOD_OVRD_REG…
33051 #define XCVR_BWR_PLL_MOD_OVRD_MOD_DIS(base, value) (BME_BFI32(&XCVR_PLL_MOD_OVRD_REG(base), ((uint3…
33067 #define XCVR_BWR_PLL_MOD_OVRD_HPM_BANK_MANUAL(base, value) (BME_BFI32(&XCVR_PLL_MOD_OVRD_REG(base),…
33083 #define XCVR_BWR_PLL_MOD_OVRD_HPM_BANK_DIS(base, value) (BME_BFI32(&XCVR_PLL_MOD_OVRD_REG(base), ((…
33099 #define XCVR_BWR_PLL_MOD_OVRD_HPM_LSB_MANUAL(base, value) (BME_BFI32(&XCVR_PLL_MOD_OVRD_REG(base), …
33116 #define XCVR_BWR_PLL_MOD_OVRD_HPM_LSB_DIS(base, value) (BME_BFI32(&XCVR_PLL_MOD_OVRD_REG(base), ((u…
33185 #define XCVR_BWR_PLL_CHAN_MAP_CHANNEL_NUM(base, value) (BME_BFI32(&XCVR_PLL_CHAN_MAP_REG(base), ((u…
33204 #define XCVR_BWR_PLL_CHAN_MAP_BOC(base, value) (BME_BFI32(&XCVR_PLL_CHAN_MAP_REG(base), ((uint32_t)…
33224 #define XCVR_BWR_PLL_CHAN_MAP_BMR(base, value) (BME_BFI32(&XCVR_PLL_CHAN_MAP_REG(base), ((uint32_t)…
33243 #define XCVR_BWR_PLL_CHAN_MAP_ZOC(base, value) (BME_BFI32(&XCVR_PLL_CHAN_MAP_REG(base), ((uint32_t)…
33296 #define XCVR_BWR_PLL_LOCK_DETECT_CTFF(base, value) (BME_BFI32(&XCVR_PLL_LOCK_DETECT_REG(base), ((ui…
33325 #define XCVR_BWR_PLL_LOCK_DETECT_CSFF(base, value) (BME_BFI32(&XCVR_PLL_LOCK_DETECT_REG(base), ((ui…
33353 #define XCVR_BWR_PLL_LOCK_DETECT_FTFF(base, value) (BME_BFI32(&XCVR_PLL_LOCK_DETECT_REG(base), ((ui…
33369 #define XCVR_BWR_PLL_LOCK_DETECT_TAFF(base, value) (BME_BFI32(&XCVR_PLL_LOCK_DETECT_REG(base), ((ui…
33386 #define XCVR_BWR_PLL_LOCK_DETECT_CTUNE_LDF_LEV(base, value) (BME_BFI32(&XCVR_PLL_LOCK_DETECT_REG(ba…
33403 #define XCVR_BWR_PLL_LOCK_DETECT_FTF_RX_THRSH(base, value) (BME_BFI32(&XCVR_PLL_LOCK_DETECT_REG(bas…
33424 #define XCVR_BWR_PLL_LOCK_DETECT_FTW_RX(base, value) (BME_BFI32(&XCVR_PLL_LOCK_DETECT_REG(base), ((…
33441 #define XCVR_BWR_PLL_LOCK_DETECT_FTF_TX_THRSH(base, value) (BME_BFI32(&XCVR_PLL_LOCK_DETECT_REG(bas…
33462 #define XCVR_BWR_PLL_LOCK_DETECT_FTW_TX(base, value) (BME_BFI32(&XCVR_PLL_LOCK_DETECT_REG(base), ((…
33503 #define XCVR_BWR_PLL_HP_MOD_CTRL_HPM_SDM_MANUAL(base, value) (BME_BFI32(&XCVR_PLL_HP_MOD_CTRL_REG(b…
33520 #define XCVR_BWR_PLL_HP_MOD_CTRL_HPFF(base, value) (BME_BFI32(&XCVR_PLL_HP_MOD_CTRL_REG(base), ((ui…
33536 #define XCVR_BWR_PLL_HP_MOD_CTRL_HP_SDM_INV(base, value) (BME_BFI32(&XCVR_PLL_HP_MOD_CTRL_REG(base)…
33552 #define XCVR_BWR_PLL_HP_MOD_CTRL_HP_SDM_DIS(base, value) (BME_BFI32(&XCVR_PLL_HP_MOD_CTRL_REG(base)…
33578 #define XCVR_BWR_PLL_HP_MOD_CTRL_HPM_LFSR_LEN(base, value) (BME_BFI32(&XCVR_PLL_HP_MOD_CTRL_REG(bas…
33594 #define XCVR_BWR_PLL_HP_MOD_CTRL_HP_DTH_SCL(base, value) (BME_BFI32(&XCVR_PLL_HP_MOD_CTRL_REG(base)…
33610 #define XCVR_BWR_PLL_HP_MOD_CTRL_HPM_DTH_EN(base, value) (BME_BFI32(&XCVR_PLL_HP_MOD_CTRL_REG(base)…
33632 #define XCVR_BWR_PLL_HP_MOD_CTRL_HPM_SCALE(base, value) (BME_BFI32(&XCVR_PLL_HP_MOD_CTRL_REG(base),…
33650 #define XCVR_BWR_PLL_HP_MOD_CTRL_HP_MOD_INV(base, value) (BME_BFI32(&XCVR_PLL_HP_MOD_CTRL_REG(base)…
33702 #define XCVR_BWR_PLL_HPM_CAL_CTRL_HP_CAL_DIS(base, value) (BME_BFI32(&XCVR_PLL_HPM_CAL_CTRL_REG(bas…
33718 #define XCVR_BWR_PLL_HPM_CAL_CTRL_HPM_CAL_FACTOR_MANUAL(base, value) (BME_BFI32(&XCVR_PLL_HPM_CAL_C…
33738 #define XCVR_BWR_PLL_HPM_CAL_CTRL_HP_CAL_ARY(base, value) (BME_BFI32(&XCVR_PLL_HPM_CAL_CTRL_REG(bas…
33758 #define XCVR_BWR_PLL_HPM_CAL_CTRL_HP_CAL_TIME(base, value) (BME_BFI32(&XCVR_PLL_HPM_CAL_CTRL_REG(ba…
33820 #define XCVR_BWR_PLL_LD_HPM_CAL1_CS_WT(base, value) (BME_BFI32(&XCVR_PLL_LD_HPM_CAL1_REG(base), ((u…
33846 #define XCVR_BWR_PLL_LD_HPM_CAL1_CS_FW(base, value) (BME_BFI32(&XCVR_PLL_LD_HPM_CAL1_REG(base), ((u…
33862 #define XCVR_BWR_PLL_LD_HPM_CAL1_CS_FCNT(base, value) (BME_BFI32(&XCVR_PLL_LD_HPM_CAL1_REG(base), (…
33914 #define XCVR_BWR_PLL_LD_HPM_CAL2_CS_RC(base, value) (BME_BFI32(&XCVR_PLL_LD_HPM_CAL2_REG(base), ((u…
33931 #define XCVR_BWR_PLL_LD_HPM_CAL2_CS_FT(base, value) (BME_BFI32(&XCVR_PLL_LD_HPM_CAL2_REG(base), ((u…
33989 #define XCVR_BWR_PLL_HPM_SDM_FRACTION_HPM_DENOM(base, value) (BME_BFI32(&XCVR_PLL_HPM_SDM_FRACTION_…
34030 #define XCVR_BWR_PLL_LP_MOD_CTRL_PLL_LOOP_DIVIDER_MANUAL(base, value) (BME_BFI32(&XCVR_PLL_LP_MOD_C…
34047 #define XCVR_BWR_PLL_LP_MOD_CTRL_PLL_LD_DIS(base, value) (BME_BFI32(&XCVR_PLL_LP_MOD_CTRL_REG(base)…
34064 #define XCVR_BWR_PLL_LP_MOD_CTRL_LPFF(base, value) (BME_BFI32(&XCVR_PLL_LP_MOD_CTRL_REG(base), ((ui…
34080 #define XCVR_BWR_PLL_LP_MOD_CTRL_LPM_SDM_INV(base, value) (BME_BFI32(&XCVR_PLL_LP_MOD_CTRL_REG(base…
34098 #define XCVR_BWR_PLL_LP_MOD_CTRL_LPM_SDM_DIS(base, value) (BME_BFI32(&XCVR_PLL_LP_MOD_CTRL_REG(base…
34134 #define XCVR_BWR_PLL_LP_MOD_CTRL_LPM_DTH_SCL(base, value) (BME_BFI32(&XCVR_PLL_LP_MOD_CTRL_REG(base…
34149 #define XCVR_BWR_PLL_LP_MOD_CTRL_LPM_D_CTRL(base, value) (BME_BFI32(&XCVR_PLL_LP_MOD_CTRL_REG(base)…
34169 #define XCVR_BWR_PLL_LP_MOD_CTRL_LPM_D_OVRD(base, value) (BME_BFI32(&XCVR_PLL_LP_MOD_CTRL_REG(base)…
34204 #define XCVR_BWR_PLL_LP_MOD_CTRL_LPM_SCALE(base, value) (BME_BFI32(&XCVR_PLL_LP_MOD_CTRL_REG(base),…
34258 #define XCVR_BWR_PLL_LP_SDM_CTRL1_LPM_INTG(base, value) (BME_BFI32(&XCVR_PLL_LP_SDM_CTRL1_REG(base)…
34277 #define XCVR_BWR_PLL_LP_SDM_CTRL1_SDM_MAP_DIS(base, value) (BME_BFI32(&XCVR_PLL_LP_SDM_CTRL1_REG(ba…
34473 #define XCVR_BWR_PLL_DELAY_MATCH_LP_SDM_DELAY(base, value) (BME_BFI32(&XCVR_PLL_DELAY_MATCH_REG(bas…
34491 #define XCVR_BWR_PLL_DELAY_MATCH_HPM_SDM_DELAY(base, value) (BME_BFI32(&XCVR_PLL_DELAY_MATCH_REG(ba…
34508 #define XCVR_BWR_PLL_DELAY_MATCH_HPM_BANK_DELAY(base, value) (BME_BFI32(&XCVR_PLL_DELAY_MATCH_REG(b…
34550 #define XCVR_BWR_PLL_CTUNE_CTRL_CTUNE_TARGET_MANUAL(base, value) (BME_BFI32(&XCVR_PLL_CTUNE_CTRL_RE…
34566 #define XCVR_BWR_PLL_CTUNE_CTRL_CTUNE_TD(base, value) (BME_BFI32(&XCVR_PLL_CTUNE_CTRL_REG(base), ((…
34583 #define XCVR_BWR_PLL_CTUNE_CTRL_CTUNE_ADJUST(base, value) (BME_BFI32(&XCVR_PLL_CTUNE_CTRL_REG(base)…
34599 #define XCVR_BWR_PLL_CTUNE_CTRL_CTUNE_MANUAL(base, value) (BME_BFI32(&XCVR_PLL_CTUNE_CTRL_REG(base)…
34615 #define XCVR_BWR_PLL_CTUNE_CTRL_CTUNE_DIS(base, value) (BME_BFI32(&XCVR_PLL_CTUNE_CTRL_REG(base), (…
34878 #define XCVR_BWR_CTRL_PROTOCOL(base, value) (BME_BFI32(&XCVR_CTRL_REG(base), ((uint32_t)(value) << …
34897 #define XCVR_BWR_CTRL_TGT_PWR_SRC(base, value) (BME_BFI32(&XCVR_CTRL_REG(base), ((uint32_t)(value) …
34918 #define XCVR_BWR_CTRL_REF_CLK_FREQ(base, value) (BME_BFI32(&XCVR_CTRL_REG(base), ((uint32_t)(value)…
35112 #define XCVR_BWR_OVERWRITE_VER_OVERWRITE_VER(base, value) (BME_BFI32(&XCVR_OVERWRITE_VER_REG(base),…
35162 #define XCVR_BWR_DMA_CTRL_DMA_I_EN(base, value) (BME_BFI32(&XCVR_DMA_CTRL_REG(base), ((uint32_t)(va…
35182 #define XCVR_BWR_DMA_CTRL_DMA_Q_EN(base, value) (BME_BFI32(&XCVR_DMA_CTRL_REG(base), ((uint32_t)(va…
35288 #define XCVR_BWR_DTEST_CTRL_DTEST_PAGE(base, value) (BME_BFI32(&XCVR_DTEST_CTRL_REG(base), ((uint32…
35308 #define XCVR_BWR_DTEST_CTRL_DTEST_EN(base, value) (BME_BFI32(&XCVR_DTEST_CTRL_REG(base), ((uint32_t…
35328 #define XCVR_BWR_DTEST_CTRL_GPIO0_OVLAY_PIN(base, value) (BME_BFI32(&XCVR_DTEST_CTRL_REG(base), ((u…
35348 #define XCVR_BWR_DTEST_CTRL_GPIO1_OVLAY_PIN(base, value) (BME_BFI32(&XCVR_DTEST_CTRL_REG(base), ((u…
35374 #define XCVR_BWR_DTEST_CTRL_TSM_GPIO_OVLAY_0(base, value) (BME_BFI32(&XCVR_DTEST_CTRL_REG(base), ((…
35400 #define XCVR_BWR_DTEST_CTRL_TSM_GPIO_OVLAY_1(base, value) (BME_BFI32(&XCVR_DTEST_CTRL_REG(base), ((…
35427 #define XCVR_BWR_DTEST_CTRL_DTEST_SHFT(base, value) (BME_BFI32(&XCVR_DTEST_CTRL_REG(base), ((uint32…
35449 #define XCVR_BWR_DTEST_CTRL_RAW_MODE_I(base, value) (BME_BFI32(&XCVR_DTEST_CTRL_REG(base), ((uint32…
35471 #define XCVR_BWR_DTEST_CTRL_RAW_MODE_Q(base, value) (BME_BFI32(&XCVR_DTEST_CTRL_REG(base), ((uint32…
35516 #define XCVR_BWR_PB_CTRL_PB_PROTECT(base, value) (BME_BFI32(&XCVR_PB_CTRL_REG(base), ((uint32_t)(va…
35562 #define XCVR_BWR_TSM_CTRL_FORCE_TX_EN(base, value) (BME_BFI32(&XCVR_TSM_CTRL_REG(base), ((uint32_t)…
35582 #define XCVR_BWR_TSM_CTRL_FORCE_RX_EN(base, value) (BME_BFI32(&XCVR_TSM_CTRL_REG(base), ((uint32_t)…
35601 #define XCVR_BWR_TSM_CTRL_PA_RAMP_SEL(base, value) (BME_BFI32(&XCVR_TSM_CTRL_REG(base), ((uint32_t)…
35622 #define XCVR_BWR_TSM_CTRL_DATA_PADDING_EN(base, value) (BME_BFI32(&XCVR_TSM_CTRL_REG(base), ((uint3…
35638 #define XCVR_BWR_TSM_CTRL_TX_ABORT_DIS(base, value) (BME_BFI32(&XCVR_TSM_CTRL_REG(base), ((uint32_t…
35654 #define XCVR_BWR_TSM_CTRL_RX_ABORT_DIS(base, value) (BME_BFI32(&XCVR_TSM_CTRL_REG(base), ((uint32_t…
35671 #define XCVR_BWR_TSM_CTRL_ABORT_ON_CTUNE(base, value) (BME_BFI32(&XCVR_TSM_CTRL_REG(base), ((uint32…
35688 #define XCVR_BWR_TSM_CTRL_ABORT_ON_CYCLE_SLIP(base, value) (BME_BFI32(&XCVR_TSM_CTRL_REG(base), ((u…
35705 #define XCVR_BWR_TSM_CTRL_ABORT_ON_FREQ_TARG(base, value) (BME_BFI32(&XCVR_TSM_CTRL_REG(base), ((ui…
35727 #define XCVR_BWR_TSM_CTRL_BKPT(base, value) (BME_BFI32(&XCVR_TSM_CTRL_REG(base), ((uint32_t)(value)…
35770 #define XCVR_BWR_END_OF_SEQ_END_OF_TX_WU(base, value) (BME_BFI32(&XCVR_END_OF_SEQ_REG(base), ((uint…
35789 #define XCVR_BWR_END_OF_SEQ_END_OF_TX_WD(base, value) (BME_BFI32(&XCVR_END_OF_SEQ_REG(base), ((uint…
35807 #define XCVR_BWR_END_OF_SEQ_END_OF_RX_WU(base, value) (BME_BFI32(&XCVR_END_OF_SEQ_REG(base), ((uint…
35826 #define XCVR_BWR_END_OF_SEQ_END_OF_RX_WD(base, value) (BME_BFI32(&XCVR_END_OF_SEQ_REG(base), ((uint…
35868 #define XCVR_BWR_TSM_OVRD0_PLL_REG_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((…
35884 #define XCVR_BWR_TSM_OVRD0_PLL_REG_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((uin…
35902 #define XCVR_BWR_TSM_OVRD0_PLL_VCO_REG_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base)…
35919 #define XCVR_BWR_TSM_OVRD0_PLL_VCO_REG_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), (…
35937 #define XCVR_BWR_TSM_OVRD0_QGEN_REG_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), (…
35953 #define XCVR_BWR_TSM_OVRD0_QGEN_REG_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((ui…
35971 #define XCVR_BWR_TSM_OVRD0_TCA_TX_REG_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base),…
35987 #define XCVR_BWR_TSM_OVRD0_TCA_TX_REG_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((…
36005 #define XCVR_BWR_TSM_OVRD0_ADC_ANA_REG_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base)…
36022 #define XCVR_BWR_TSM_OVRD0_ADC_ANA_REG_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), (…
36040 #define XCVR_BWR_TSM_OVRD0_ADC_DIG_REG_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base)…
36057 #define XCVR_BWR_TSM_OVRD0_ADC_DIG_REG_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), (…
36075 #define XCVR_BWR_TSM_OVRD0_XTAL_PLL_REF_CLK_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(…
36092 #define XCVR_BWR_TSM_OVRD0_XTAL_PLL_REF_CLK_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(bas…
36110 #define XCVR_BWR_TSM_OVRD0_XTAL_ADC_REF_CLK_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(…
36127 #define XCVR_BWR_TSM_OVRD0_XTAL_ADC_REF_CLK_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(bas…
36145 #define XCVR_BWR_TSM_OVRD0_PLL_VCO_AUTOTUNE_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(…
36162 #define XCVR_BWR_TSM_OVRD0_PLL_VCO_AUTOTUNE_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(bas…
36180 #define XCVR_BWR_TSM_OVRD0_PLL_CYCLE_SLIP_LD_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG…
36197 #define XCVR_BWR_TSM_OVRD0_PLL_CYCLE_SLIP_LD_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(ba…
36214 #define XCVR_BWR_TSM_OVRD0_PLL_VCO_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((…
36230 #define XCVR_BWR_TSM_OVRD0_PLL_VCO_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((uin…
36248 #define XCVR_BWR_TSM_OVRD0_PLL_VCO_BUF_RX_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(ba…
36265 #define XCVR_BWR_TSM_OVRD0_PLL_VCO_BUF_RX_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base)…
36283 #define XCVR_BWR_TSM_OVRD0_PLL_VCO_BUF_TX_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(ba…
36300 #define XCVR_BWR_TSM_OVRD0_PLL_VCO_BUF_TX_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base)…
36318 #define XCVR_BWR_TSM_OVRD0_PLL_PA_BUF_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base),…
36334 #define XCVR_BWR_TSM_OVRD0_PLL_PA_BUF_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((…
36351 #define XCVR_BWR_TSM_OVRD0_PLL_LDV_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((…
36367 #define XCVR_BWR_TSM_OVRD0_PLL_LDV_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((uin…
36385 #define XCVR_BWR_TSM_OVRD0_PLL_RX_LDV_RIPPLE_MUX_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0…
36402 #define XCVR_BWR_TSM_OVRD0_PLL_RX_LDV_RIPPLE_MUX_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_RE…
36445 #define XCVR_BWR_TSM_OVRD1_PLL_TX_LDV_RIPPLE_MUX_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1…
36462 #define XCVR_BWR_TSM_OVRD1_PLL_TX_LDV_RIPPLE_MUX_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_RE…
36480 #define XCVR_BWR_TSM_OVRD1_PLL_FILTER_CHARGE_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG…
36497 #define XCVR_BWR_TSM_OVRD1_PLL_FILTER_CHARGE_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(ba…
36515 #define XCVR_BWR_TSM_OVRD1_PLL_PHDET_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), …
36531 #define XCVR_BWR_TSM_OVRD1_PLL_PHDET_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((u…
36548 #define XCVR_BWR_TSM_OVRD1_QGEN25_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((u…
36564 #define XCVR_BWR_TSM_OVRD1_QGEN25_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint…
36581 #define XCVR_BWR_TSM_OVRD1_TX_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint3…
36597 #define XCVR_BWR_TSM_OVRD1_TX_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint32_t…
36614 #define XCVR_BWR_TSM_OVRD1_ADC_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint…
36630 #define XCVR_BWR_TSM_OVRD1_ADC_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint32_…
36648 #define XCVR_BWR_TSM_OVRD1_ADC_BIAS_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), (…
36664 #define XCVR_BWR_TSM_OVRD1_ADC_BIAS_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((ui…
36681 #define XCVR_BWR_TSM_OVRD1_ADC_CLK_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((…
36697 #define XCVR_BWR_TSM_OVRD1_ADC_CLK_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uin…
36715 #define XCVR_BWR_TSM_OVRD1_ADC_I_ADC_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), …
36731 #define XCVR_BWR_TSM_OVRD1_ADC_I_ADC_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((u…
36749 #define XCVR_BWR_TSM_OVRD1_ADC_Q_ADC_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), …
36765 #define XCVR_BWR_TSM_OVRD1_ADC_Q_ADC_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((u…
36783 #define XCVR_BWR_TSM_OVRD1_ADC_DAC1_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), (…
36799 #define XCVR_BWR_TSM_OVRD1_ADC_DAC1_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((ui…
36817 #define XCVR_BWR_TSM_OVRD1_ADC_DAC2_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), (…
36833 #define XCVR_BWR_TSM_OVRD1_ADC_DAC2_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((ui…
36850 #define XCVR_BWR_TSM_OVRD1_ADC_RST_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((…
36866 #define XCVR_BWR_TSM_OVRD1_ADC_RST_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uin…
36883 #define XCVR_BWR_TSM_OVRD1_BBF_I_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((ui…
36899 #define XCVR_BWR_TSM_OVRD1_BBF_I_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint3…
36916 #define XCVR_BWR_TSM_OVRD1_BBF_Q_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((ui…
36932 #define XCVR_BWR_TSM_OVRD1_BBF_Q_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint3…
36950 #define XCVR_BWR_TSM_OVRD1_BBF_PDET_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), (…
36966 #define XCVR_BWR_TSM_OVRD1_BBF_PDET_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((ui…
37009 #define XCVR_BWR_TSM_OVRD2_BBF_DCOC_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), (…
37025 #define XCVR_BWR_TSM_OVRD2_BBF_DCOC_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((ui…
37042 #define XCVR_BWR_TSM_OVRD2_TCA_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint…
37058 #define XCVR_BWR_TSM_OVRD2_TCA_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint32_…
37075 #define XCVR_BWR_TSM_OVRD2_TZA_I_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((ui…
37091 #define XCVR_BWR_TSM_OVRD2_TZA_I_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint3…
37108 #define XCVR_BWR_TSM_OVRD2_TZA_Q_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((ui…
37124 #define XCVR_BWR_TSM_OVRD2_TZA_Q_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint3…
37142 #define XCVR_BWR_TSM_OVRD2_TZA_PDET_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), (…
37158 #define XCVR_BWR_TSM_OVRD2_TZA_PDET_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((ui…
37176 #define XCVR_BWR_TSM_OVRD2_TZA_DCOC_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), (…
37192 #define XCVR_BWR_TSM_OVRD2_TZA_DCOC_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((ui…
37209 #define XCVR_BWR_TSM_OVRD2_PLL_DIG_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((…
37225 #define XCVR_BWR_TSM_OVRD2_PLL_DIG_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uin…
37242 #define XCVR_BWR_TSM_OVRD2_TX_DIG_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((u…
37258 #define XCVR_BWR_TSM_OVRD2_TX_DIG_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint…
37275 #define XCVR_BWR_TSM_OVRD2_RX_DIG_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((u…
37291 #define XCVR_BWR_TSM_OVRD2_RX_DIG_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint…
37308 #define XCVR_BWR_TSM_OVRD2_RX_INIT_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uin…
37324 #define XCVR_BWR_TSM_OVRD2_RX_INIT_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint32…
37342 #define XCVR_BWR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base)…
37359 #define XCVR_BWR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), (…
37377 #define XCVR_BWR_TSM_OVRD2_ZBDEM_RX_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), (…
37393 #define XCVR_BWR_TSM_OVRD2_ZBDEM_RX_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((ui…
37410 #define XCVR_BWR_TSM_OVRD2_DCOC_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uin…
37426 #define XCVR_BWR_TSM_OVRD2_DCOC_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint32…
37443 #define XCVR_BWR_TSM_OVRD2_DCOC_INIT_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((u…
37459 #define XCVR_BWR_TSM_OVRD2_DCOC_INIT_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint…
37477 #define XCVR_BWR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base…
37494 #define XCVR_BWR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), …
37512 #define XCVR_BWR_TSM_OVRD2_SAR_ADC_TRIG_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base…
37529 #define XCVR_BWR_TSM_OVRD2_SAR_ADC_TRIG_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), …
37572 #define XCVR_BWR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD3_REG(base),…
37588 #define XCVR_BWR_TSM_OVRD3_TSM_SPARE0_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD3_REG(base), ((…
37606 #define XCVR_BWR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD3_REG(base),…
37622 #define XCVR_BWR_TSM_OVRD3_TSM_SPARE1_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD3_REG(base), ((…
37640 #define XCVR_BWR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD3_REG(base),…
37656 #define XCVR_BWR_TSM_OVRD3_TSM_SPARE2_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD3_REG(base), ((…
37674 #define XCVR_BWR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD3_REG(base),…
37690 #define XCVR_BWR_TSM_OVRD3_TSM_SPARE3_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD3_REG(base), ((…
37707 #define XCVR_BWR_TSM_OVRD3_TX_MODE_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD3_REG(base), ((uin…
37723 #define XCVR_BWR_TSM_OVRD3_TX_MODE_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD3_REG(base), ((uint32…
37740 #define XCVR_BWR_TSM_OVRD3_RX_MODE_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD3_REG(base), ((uin…
37756 #define XCVR_BWR_TSM_OVRD3_RX_MODE_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD3_REG(base), ((uint32…
37799 #define XCVR_BWR_PA_POWER_PA_POWER(base, value) (BME_BFI32(&XCVR_PA_POWER_REG(base), ((uint32_t)(va…
37845 #define XCVR_BWR_PA_BIAS_TBL0_PA_BIAS0(base, value) (BME_BFI32(&XCVR_PA_BIAS_TBL0_REG(base), ((uint…
37864 #define XCVR_BWR_PA_BIAS_TBL0_PA_BIAS1(base, value) (BME_BFI32(&XCVR_PA_BIAS_TBL0_REG(base), ((uint…
37883 #define XCVR_BWR_PA_BIAS_TBL0_PA_BIAS2(base, value) (BME_BFI32(&XCVR_PA_BIAS_TBL0_REG(base), ((uint…
37902 #define XCVR_BWR_PA_BIAS_TBL0_PA_BIAS3(base, value) (BME_BFI32(&XCVR_PA_BIAS_TBL0_REG(base), ((uint…
37946 #define XCVR_BWR_PA_BIAS_TBL1_PA_BIAS4(base, value) (BME_BFI32(&XCVR_PA_BIAS_TBL1_REG(base), ((uint…
37965 #define XCVR_BWR_PA_BIAS_TBL1_PA_BIAS5(base, value) (BME_BFI32(&XCVR_PA_BIAS_TBL1_REG(base), ((uint…
37984 #define XCVR_BWR_PA_BIAS_TBL1_PA_BIAS6(base, value) (BME_BFI32(&XCVR_PA_BIAS_TBL1_REG(base), ((uint…
38003 #define XCVR_BWR_PA_BIAS_TBL1_PA_BIAS7(base, value) (BME_BFI32(&XCVR_PA_BIAS_TBL1_REG(base), ((uint…
38054 #define XCVR_BWR_RECYCLE_COUNT_RECYCLE_COUNT0(base, value) (BME_BFI32(&XCVR_RECYCLE_COUNT_REG(base)…
38080 #define XCVR_BWR_RECYCLE_COUNT_RECYCLE_COUNT1(base, value) (BME_BFI32(&XCVR_RECYCLE_COUNT_REG(base)…
38125 #define XCVR_BWR_TSM_TIMING00_PLL_REG_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING00_REG(base)…
38141 #define XCVR_BWR_TSM_TIMING00_PLL_REG_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING00_REG(base)…
38157 #define XCVR_BWR_TSM_TIMING00_PLL_REG_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING00_REG(base)…
38173 #define XCVR_BWR_TSM_TIMING00_PLL_REG_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING00_REG(base)…
38218 #define XCVR_BWR_TSM_TIMING01_PLL_VCO_REG_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING01_REG(b…
38234 #define XCVR_BWR_TSM_TIMING01_PLL_VCO_REG_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING01_REG(b…
38250 #define XCVR_BWR_TSM_TIMING01_PLL_VCO_REG_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING01_REG(b…
38266 #define XCVR_BWR_TSM_TIMING01_PLL_VCO_REG_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING01_REG(b…
38311 #define XCVR_BWR_TSM_TIMING02_QGEN_REG_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING02_REG(base…
38327 #define XCVR_BWR_TSM_TIMING02_QGEN_REG_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING02_REG(base…
38343 #define XCVR_BWR_TSM_TIMING02_QGEN_REG_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING02_REG(base…
38359 #define XCVR_BWR_TSM_TIMING02_QGEN_REG_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING02_REG(base…
38404 #define XCVR_BWR_TSM_TIMING03_TCA_TX_REG_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING03_REG(ba…
38420 #define XCVR_BWR_TSM_TIMING03_TCA_TX_REG_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING03_REG(ba…
38436 #define XCVR_BWR_TSM_TIMING03_TCA_TX_REG_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING03_REG(ba…
38452 #define XCVR_BWR_TSM_TIMING03_TCA_TX_REG_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING03_REG(ba…
38497 #define XCVR_BWR_TSM_TIMING04_ADC_REG_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING04_REG(base)…
38513 #define XCVR_BWR_TSM_TIMING04_ADC_REG_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING04_REG(base)…
38558 #define XCVR_BWR_TSM_TIMING05_PLL_REF_CLK_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING05_REG(b…
38574 #define XCVR_BWR_TSM_TIMING05_PLL_REF_CLK_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING05_REG(b…
38590 #define XCVR_BWR_TSM_TIMING05_PLL_REF_CLK_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING05_REG(b…
38606 #define XCVR_BWR_TSM_TIMING05_PLL_REF_CLK_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING05_REG(b…
38651 #define XCVR_BWR_TSM_TIMING06_ADC_CLK_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING06_REG(base)…
38667 #define XCVR_BWR_TSM_TIMING06_ADC_CLK_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING06_REG(base)…
38713 #define XCVR_BWR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING07_…
38730 #define XCVR_BWR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING07_…
38747 #define XCVR_BWR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING07_…
38764 #define XCVR_BWR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING07_…
38810 #define XCVR_BWR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING08…
38827 #define XCVR_BWR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING08…
38844 #define XCVR_BWR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING08…
38861 #define XCVR_BWR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING08…
38906 #define XCVR_BWR_TSM_TIMING09_PLL_VCO_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING09_REG(base)…
38922 #define XCVR_BWR_TSM_TIMING09_PLL_VCO_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING09_REG(base)…
38938 #define XCVR_BWR_TSM_TIMING09_PLL_VCO_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING09_REG(base)…
38954 #define XCVR_BWR_TSM_TIMING09_PLL_VCO_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING09_REG(base)…
38999 #define XCVR_BWR_TSM_TIMING10_PLL_VCO_BUF_RX_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING10_RE…
39015 #define XCVR_BWR_TSM_TIMING10_PLL_VCO_BUF_RX_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING10_RE…
39060 #define XCVR_BWR_TSM_TIMING11_PLL_VCO_BUF_TX_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING11_RE…
39076 #define XCVR_BWR_TSM_TIMING11_PLL_VCO_BUF_TX_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING11_RE…
39121 #define XCVR_BWR_TSM_TIMING12_PLL_PA_BUF_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING12_REG(ba…
39137 #define XCVR_BWR_TSM_TIMING12_PLL_PA_BUF_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING12_REG(ba…
39182 #define XCVR_BWR_TSM_TIMING13_PLL_LDV_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING13_REG(base)…
39198 #define XCVR_BWR_TSM_TIMING13_PLL_LDV_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING13_REG(base)…
39214 #define XCVR_BWR_TSM_TIMING13_PLL_LDV_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING13_REG(base)…
39230 #define XCVR_BWR_TSM_TIMING13_PLL_LDV_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING13_REG(base)…
39276 #define XCVR_BWR_TSM_TIMING14_PLL_RX_LDV_RIPPLE_MUX_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMI…
39293 #define XCVR_BWR_TSM_TIMING14_PLL_RX_LDV_RIPPLE_MUX_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMI…
39339 #define XCVR_BWR_TSM_TIMING15_PLL_TX_LDV_RIPPLE_MUX_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMI…
39356 #define XCVR_BWR_TSM_TIMING15_PLL_TX_LDV_RIPPLE_MUX_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMI…
39402 #define XCVR_BWR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING16…
39419 #define XCVR_BWR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING16…
39436 #define XCVR_BWR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING16…
39453 #define XCVR_BWR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING16…
39498 #define XCVR_BWR_TSM_TIMING17_PLL_PHDET_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING17_REG(bas…
39514 #define XCVR_BWR_TSM_TIMING17_PLL_PHDET_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING17_REG(bas…
39530 #define XCVR_BWR_TSM_TIMING17_PLL_PHDET_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING17_REG(bas…
39546 #define XCVR_BWR_TSM_TIMING17_PLL_PHDET_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING17_REG(bas…
39591 #define XCVR_BWR_TSM_TIMING18_QGEN25_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING18_REG(base),…
39607 #define XCVR_BWR_TSM_TIMING18_QGEN25_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING18_REG(base),…
39652 #define XCVR_BWR_TSM_TIMING19_TX_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING19_REG(base), ((u…
39668 #define XCVR_BWR_TSM_TIMING19_TX_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING19_REG(base), ((u…
39713 #define XCVR_BWR_TSM_TIMING20_ADC_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING20_REG(base), ((…
39729 #define XCVR_BWR_TSM_TIMING20_ADC_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING20_REG(base), ((…
39774 #define XCVR_BWR_TSM_TIMING21_ADC_I_Q_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING21_REG(base)…
39790 #define XCVR_BWR_TSM_TIMING21_ADC_I_Q_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING21_REG(base)…
39835 #define XCVR_BWR_TSM_TIMING22_ADC_DAC_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING22_REG(base)…
39851 #define XCVR_BWR_TSM_TIMING22_ADC_DAC_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING22_REG(base)…
39896 #define XCVR_BWR_TSM_TIMING23_ADC_RST_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING23_REG(base)…
39912 #define XCVR_BWR_TSM_TIMING23_ADC_RST_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING23_REG(base)…
39957 #define XCVR_BWR_TSM_TIMING24_BBF_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING24_REG(base), ((…
39973 #define XCVR_BWR_TSM_TIMING24_BBF_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING24_REG(base), ((…
40018 #define XCVR_BWR_TSM_TIMING25_TCA_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING25_REG(base), ((…
40034 #define XCVR_BWR_TSM_TIMING25_TCA_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING25_REG(base), ((…
40079 #define XCVR_BWR_TSM_TIMING26_PLL_DIG_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING26_REG(base)…
40095 #define XCVR_BWR_TSM_TIMING26_PLL_DIG_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING26_REG(base)…
40111 #define XCVR_BWR_TSM_TIMING26_PLL_DIG_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING26_REG(base)…
40127 #define XCVR_BWR_TSM_TIMING26_PLL_DIG_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING26_REG(base)…
40172 #define XCVR_BWR_TSM_TIMING27_TX_DIG_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING27_REG(base),…
40188 #define XCVR_BWR_TSM_TIMING27_TX_DIG_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING27_REG(base),…
40233 #define XCVR_BWR_TSM_TIMING28_RX_DIG_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING28_REG(base),…
40249 #define XCVR_BWR_TSM_TIMING28_RX_DIG_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING28_REG(base),…
40294 #define XCVR_BWR_TSM_TIMING29_RX_INIT_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING29_REG(base), (…
40310 #define XCVR_BWR_TSM_TIMING29_RX_INIT_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING29_REG(base), (…
40355 #define XCVR_BWR_TSM_TIMING30_SIGMA_DELTA_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING30_REG(b…
40371 #define XCVR_BWR_TSM_TIMING30_SIGMA_DELTA_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING30_REG(b…
40387 #define XCVR_BWR_TSM_TIMING30_SIGMA_DELTA_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING30_REG(b…
40403 #define XCVR_BWR_TSM_TIMING30_SIGMA_DELTA_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING30_REG(b…
40448 #define XCVR_BWR_TSM_TIMING31_ZBDEM_RX_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING31_REG(base…
40464 #define XCVR_BWR_TSM_TIMING31_ZBDEM_RX_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING31_REG(base…
40509 #define XCVR_BWR_TSM_TIMING32_DCOC_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING32_REG(base), (…
40525 #define XCVR_BWR_TSM_TIMING32_DCOC_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING32_REG(base), (…
40570 #define XCVR_BWR_TSM_TIMING33_DCOC_INIT_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING33_REG(base),…
40586 #define XCVR_BWR_TSM_TIMING33_DCOC_INIT_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING33_REG(base),…
40631 #define XCVR_BWR_TSM_TIMING34_FREQ_TARG_LD_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING34_REG(…
40647 #define XCVR_BWR_TSM_TIMING34_FREQ_TARG_LD_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING34_REG(…
40663 #define XCVR_BWR_TSM_TIMING34_FREQ_TARG_LD_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING34_REG(…
40679 #define XCVR_BWR_TSM_TIMING34_FREQ_TARG_LD_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING34_REG(…
40724 #define XCVR_BWR_TSM_TIMING35_SAR_ADC_TRIG_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING35_REG(…
40740 #define XCVR_BWR_TSM_TIMING35_SAR_ADC_TRIG_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING35_REG(…
40756 #define XCVR_BWR_TSM_TIMING35_SAR_ADC_TRIG_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING35_REG(…
40772 #define XCVR_BWR_TSM_TIMING35_SAR_ADC_TRIG_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING35_REG(…
40817 #define XCVR_BWR_TSM_TIMING36_TSM_SPARE0_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING36_REG(ba…
40833 #define XCVR_BWR_TSM_TIMING36_TSM_SPARE0_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING36_REG(ba…
40849 #define XCVR_BWR_TSM_TIMING36_TSM_SPARE0_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING36_REG(ba…
40865 #define XCVR_BWR_TSM_TIMING36_TSM_SPARE0_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING36_REG(ba…
40910 #define XCVR_BWR_TSM_TIMING37_TSM_SPARE1_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING37_REG(ba…
40926 #define XCVR_BWR_TSM_TIMING37_TSM_SPARE1_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING37_REG(ba…
40942 #define XCVR_BWR_TSM_TIMING37_TSM_SPARE1_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING37_REG(ba…
40958 #define XCVR_BWR_TSM_TIMING37_TSM_SPARE1_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING37_REG(ba…
41003 #define XCVR_BWR_TSM_TIMING38_TSM_SPARE2_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING38_REG(ba…
41019 #define XCVR_BWR_TSM_TIMING38_TSM_SPARE2_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING38_REG(ba…
41035 #define XCVR_BWR_TSM_TIMING38_TSM_SPARE2_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING38_REG(ba…
41051 #define XCVR_BWR_TSM_TIMING38_TSM_SPARE2_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING38_REG(ba…
41096 #define XCVR_BWR_TSM_TIMING39_TSM_SPARE3_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING39_REG(ba…
41112 #define XCVR_BWR_TSM_TIMING39_TSM_SPARE3_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING39_REG(ba…
41128 #define XCVR_BWR_TSM_TIMING39_TSM_SPARE3_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING39_REG(ba…
41144 #define XCVR_BWR_TSM_TIMING39_TSM_SPARE3_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING39_REG(ba…
41189 #define XCVR_BWR_TSM_TIMING40_GPIO0_TRIG_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING40_REG(ba…
41205 #define XCVR_BWR_TSM_TIMING40_GPIO0_TRIG_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING40_REG(ba…
41221 #define XCVR_BWR_TSM_TIMING40_GPIO0_TRIG_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING40_REG(ba…
41237 #define XCVR_BWR_TSM_TIMING40_GPIO0_TRIG_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING40_REG(ba…
41282 #define XCVR_BWR_TSM_TIMING41_GPIO1_TRIG_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING41_REG(ba…
41298 #define XCVR_BWR_TSM_TIMING41_GPIO1_TRIG_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING41_REG(ba…
41314 #define XCVR_BWR_TSM_TIMING41_GPIO1_TRIG_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING41_REG(ba…
41330 #define XCVR_BWR_TSM_TIMING41_GPIO1_TRIG_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING41_REG(ba…
41375 #define XCVR_BWR_TSM_TIMING42_GPIO2_TRIG_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING42_REG(ba…
41391 #define XCVR_BWR_TSM_TIMING42_GPIO2_TRIG_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING42_REG(ba…
41407 #define XCVR_BWR_TSM_TIMING42_GPIO2_TRIG_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING42_REG(ba…
41423 #define XCVR_BWR_TSM_TIMING42_GPIO2_TRIG_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING42_REG(ba…
41468 #define XCVR_BWR_TSM_TIMING43_GPIO3_TRIG_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING43_REG(ba…
41484 #define XCVR_BWR_TSM_TIMING43_GPIO3_TRIG_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING43_REG(ba…
41500 #define XCVR_BWR_TSM_TIMING43_GPIO3_TRIG_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING43_REG(ba…
41516 #define XCVR_BWR_TSM_TIMING43_GPIO3_TRIG_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING43_REG(ba…
41557 #define XCVR_BWR_CORR_CTRL_CORR_VT(base, value) (BME_BFI32(&XCVR_CORR_CTRL_REG(base), ((uint32_t)(v…
41573 #define XCVR_BWR_CORR_CTRL_CORR_NVAL(base, value) (BME_BFI32(&XCVR_CORR_CTRL_REG(base), ((uint32_t)…
41589 #define XCVR_BWR_CORR_CTRL_MAX_CORR_EN(base, value) (BME_BFI32(&XCVR_CORR_CTRL_REG(base), ((uint32_…
41653 #define XCVR_BWR_PN_TYPE_PN_TYPE(base, value) (BME_BFI32(&XCVR_PN_TYPE_REG(base), ((uint32_t)(value…
41668 #define XCVR_BWR_PN_TYPE_TX_INV(base, value) (BME_BFI32(&XCVR_PN_TYPE_REG(base), ((uint32_t)(value)…
41710 #define XCVR_BWR_PN_CODE_PN_LSB(base, value) (BME_BFI32(&XCVR_PN_CODE_REG(base), ((uint32_t)(value)…
41725 #define XCVR_BWR_PN_CODE_PN_MSB(base, value) (BME_BFI32(&XCVR_PN_CODE_REG(base), ((uint32_t)(value)…
41767 #define XCVR_BWR_SYNC_CTRL_SYNC_PER(base, value) (BME_BFI32(&XCVR_SYNC_CTRL_REG(base), ((uint32_t)(…
41785 #define XCVR_BWR_SYNC_CTRL_TRACK_ENABLE(base, value) (BME_BFI32(&XCVR_SYNC_CTRL_REG(base), ((uint32…
41827 #define XCVR_BWR_SNF_THR_SNF_THR(base, value) (BME_BFI32(&XCVR_SNF_THR_REG(base), ((uint32_t)(value…
41867 #define XCVR_BWR_FAD_THR_FAD_THR(base, value) (BME_BFI32(&XCVR_FAD_THR_REG(base), ((uint32_t)(value…
41907 #define XCVR_BWR_ZBDEM_AFC_AFC_EN(base, value) (BME_BFI32(&XCVR_ZBDEM_AFC_REG(base), ((uint32_t)(va…
41924 #define XCVR_BWR_ZBDEM_AFC_DCD_EN(base, value) (BME_BFI32(&XCVR_ZBDEM_AFC_REG(base), ((uint32_t)(va…
41981 #define XCVR_BWR_LPPS_CTRL_LPPS_ENABLE(base, value) (BME_BFI32(&XCVR_LPPS_CTRL_REG(base), ((uint32_…
41998 #define XCVR_BWR_LPPS_CTRL_LPPS_QGEN25_ALLOW(base, value) (BME_BFI32(&XCVR_LPPS_CTRL_REG(base), ((u…
42017 #define XCVR_BWR_LPPS_CTRL_LPPS_ADC_ALLOW(base, value) (BME_BFI32(&XCVR_LPPS_CTRL_REG(base), ((uint…
42036 #define XCVR_BWR_LPPS_CTRL_LPPS_ADC_CLK_ALLOW(base, value) (BME_BFI32(&XCVR_LPPS_CTRL_REG(base), ((…
42055 #define XCVR_BWR_LPPS_CTRL_LPPS_ADC_I_Q_ALLOW(base, value) (BME_BFI32(&XCVR_LPPS_CTRL_REG(base), ((…
42074 #define XCVR_BWR_LPPS_CTRL_LPPS_ADC_DAC_ALLOW(base, value) (BME_BFI32(&XCVR_LPPS_CTRL_REG(base), ((…
42093 #define XCVR_BWR_LPPS_CTRL_LPPS_BBF_ALLOW(base, value) (BME_BFI32(&XCVR_LPPS_CTRL_REG(base), ((uint…
42112 #define XCVR_BWR_LPPS_CTRL_LPPS_TCA_ALLOW(base, value) (BME_BFI32(&XCVR_LPPS_CTRL_REG(base), ((uint…
42154 #define XCVR_BWR_ADC_CTRL_ADC_32MHZ_SEL(base, value) (BME_BFI32(&XCVR_ADC_CTRL_REG(base), ((uint32_…
42171 #define XCVR_BWR_ADC_CTRL_ADC_2X_CLK_SEL(base, value) (BME_BFI32(&XCVR_ADC_CTRL_REG(base), ((uint32…
42187 #define XCVR_BWR_ADC_CTRL_ADC_DITHER_ON(base, value) (BME_BFI32(&XCVR_ADC_CTRL_REG(base), ((uint32_…
42203 #define XCVR_BWR_ADC_CTRL_ADC_TEST_ON(base, value) (BME_BFI32(&XCVR_ADC_CTRL_REG(base), ((uint32_t)…
42220 #define XCVR_BWR_ADC_CTRL_ADC_COMP_ON(base, value) (BME_BFI32(&XCVR_ADC_CTRL_REG(base), ((uint32_t)…
42261 #define XCVR_BWR_ADC_TUNE_ADC_R1_TUNE(base, value) (BME_BFI32(&XCVR_ADC_TUNE_REG(base), ((uint32_t)…
42277 #define XCVR_BWR_ADC_TUNE_ADC_R2_TUNE(base, value) (BME_BFI32(&XCVR_ADC_TUNE_REG(base), ((uint32_t)…
42293 #define XCVR_BWR_ADC_TUNE_ADC_C1_TUNE(base, value) (BME_BFI32(&XCVR_ADC_TUNE_REG(base), ((uint32_t)…
42309 #define XCVR_BWR_ADC_TUNE_ADC_C2_TUNE(base, value) (BME_BFI32(&XCVR_ADC_TUNE_REG(base), ((uint32_t)…
42350 #define XCVR_BWR_ADC_ADJ_ADC_IB_OPAMP1_ADJ(base, value) (BME_BFI32(&XCVR_ADC_ADJ_REG(base), ((uint3…
42366 #define XCVR_BWR_ADC_ADJ_ADC_IB_OPAMP2_ADJ(base, value) (BME_BFI32(&XCVR_ADC_ADJ_REG(base), ((uint3…
42381 #define XCVR_BWR_ADC_ADJ_ADC_IB_DAC1_ADJ(base, value) (BME_BFI32(&XCVR_ADC_ADJ_REG(base), ((uint32_…
42396 #define XCVR_BWR_ADC_ADJ_ADC_IB_DAC2_ADJ(base, value) (BME_BFI32(&XCVR_ADC_ADJ_REG(base), ((uint32_…
42412 #define XCVR_BWR_ADC_ADJ_ADC_IB_FLSH_ADJ(base, value) (BME_BFI32(&XCVR_ADC_ADJ_REG(base), ((uint32_…
42428 #define XCVR_BWR_ADC_ADJ_ADC_FLSH_RES_ADJ(base, value) (BME_BFI32(&XCVR_ADC_ADJ_REG(base), ((uint32…
42474 #define XCVR_BWR_ADC_REGS_ADC_ANA_REG_SUPPLY(base, value) (BME_BFI32(&XCVR_ADC_REGS_REG(base), ((ui…
42495 #define XCVR_BWR_ADC_REGS_ADC_REG_DIG_SUPPLY(base, value) (BME_BFI32(&XCVR_ADC_REGS_REG(base), ((ui…
42512 #define XCVR_BWR_ADC_REGS_ADC_ANA_REG_BYPASS_ON(base, value) (BME_BFI32(&XCVR_ADC_REGS_REG(base), (…
42529 #define XCVR_BWR_ADC_REGS_ADC_DIG_REG_BYPASS_ON(base, value) (BME_BFI32(&XCVR_ADC_REGS_REG(base), (…
42547 #define XCVR_BWR_ADC_REGS_ADC_VCMREF_BYPASS_ON(base, value) (BME_BFI32(&XCVR_ADC_REGS_REG(base), ((…
42566 #define XCVR_BWR_ADC_REGS_ADC_INTERNAL_IREF_BYPASS_ON(base, value) (BME_BFI32(&XCVR_ADC_REGS_REG(ba…
42608 #define XCVR_BWR_ADC_TRIMS_ADC_IREF_OPAMPS_RES_TRIM(base, value) (BME_BFI32(&XCVR_ADC_TRIMS_REG(bas…
42624 #define XCVR_BWR_ADC_TRIMS_ADC_IREF_FLSH_RES_TRIM(base, value) (BME_BFI32(&XCVR_ADC_TRIMS_REG(base)…
42641 #define XCVR_BWR_ADC_TRIMS_ADC_VCM_TRIM(base, value) (BME_BFI32(&XCVR_ADC_TRIMS_REG(base), ((uint32…
42687 #define XCVR_BWR_ADC_TEST_CTRL_ADC_ATST_SEL(base, value) (BME_BFI32(&XCVR_ADC_TEST_CTRL_REG(base), …
42703 #define XCVR_BWR_ADC_TEST_CTRL_ADC_DIG_REG_ATST_SEL(base, value) (BME_BFI32(&XCVR_ADC_TEST_CTRL_REG…
42719 #define XCVR_BWR_ADC_TEST_CTRL_ADC_ANA_REG_ATST_SEL(base, value) (BME_BFI32(&XCVR_ADC_TEST_CTRL_REG…
42746 #define XCVR_BWR_ADC_TEST_CTRL_DCOC_ALPHA_RADIUS_GS_IDX(base, value) (BME_BFI32(&XCVR_ADC_TEST_CTRL…
42761 #define XCVR_BWR_ADC_TEST_CTRL_ADC_SPARE3(base, value) (BME_BFI32(&XCVR_ADC_TEST_CTRL_REG(base), ((…
42814 #define XCVR_BWR_BBF_CTRL_BBF_CAP_TUNE(base, value) (BME_BFI32(&XCVR_BBF_CTRL_REG(base), ((uint32_t…
42832 #define XCVR_BWR_BBF_CTRL_BBF_RES_TUNE2(base, value) (BME_BFI32(&XCVR_BBF_CTRL_REG(base), ((uint32_…
42852 #define XCVR_BWR_BBF_CTRL_BBF_CUR_CNTL(base, value) (BME_BFI32(&XCVR_BBF_CTRL_REG(base), ((uint32_t…
42867 #define XCVR_BWR_BBF_CTRL_BBF_DCOC_ON(base, value) (BME_BFI32(&XCVR_BBF_CTRL_REG(base), ((uint32_t)…
42884 #define XCVR_BWR_BBF_CTRL_BBF_TMUX_ON(base, value) (BME_BFI32(&XCVR_BBF_CTRL_REG(base), ((uint32_t)…
42907 #define XCVR_BWR_BBF_CTRL_DCOC_ALPHAC_SCALE_GS_IDX(base, value) (BME_BFI32(&XCVR_BBF_CTRL_REG(base)…
42922 #define XCVR_BWR_BBF_CTRL_BBF_SPARE_3_2(base, value) (BME_BFI32(&XCVR_BBF_CTRL_REG(base), ((uint32_…
42971 #define XCVR_BWR_RX_ANA_CTRL_RX_ATST_SEL(base, value) (BME_BFI32(&XCVR_RX_ANA_CTRL_REG(base), ((uin…
42987 #define XCVR_BWR_RX_ANA_CTRL_IQMC_DC_GAIN_ADJ_EN(base, value) (BME_BFI32(&XCVR_RX_ANA_CTRL_REG(base…
43002 #define XCVR_BWR_RX_ANA_CTRL_LNM_SPARE_3_2_1(base, value) (BME_BFI32(&XCVR_RX_ANA_CTRL_REG(base), (…
43043 #define XCVR_BWR_XTAL_CTRL_XTAL_TRIM(base, value) (BME_BFI32(&XCVR_XTAL_CTRL_REG(base), ((uint32_t)…
43059 #define XCVR_BWR_XTAL_CTRL_XTAL_GM(base, value) (BME_BFI32(&XCVR_XTAL_CTRL_REG(base), ((uint32_t)(v…
43075 #define XCVR_BWR_XTAL_CTRL_XTAL_BYPASS(base, value) (BME_BFI32(&XCVR_XTAL_CTRL_REG(base), ((uint32_…
43096 #define XCVR_BWR_XTAL_CTRL_XTAL_READY_COUNT_SEL(base, value) (BME_BFI32(&XCVR_XTAL_CTRL_REG(base), …
43112 #define XCVR_BWR_XTAL_CTRL_XTAL_COMP_BIAS_LO(base, value) (BME_BFI32(&XCVR_XTAL_CTRL_REG(base), ((u…
43129 #define XCVR_BWR_XTAL_CTRL_XTAL_ALC_START_512U(base, value) (BME_BFI32(&XCVR_XTAL_CTRL_REG(base), (…
43144 #define XCVR_BWR_XTAL_CTRL_XTAL_ALC_ON(base, value) (BME_BFI32(&XCVR_XTAL_CTRL_REG(base), ((uint32_…
43160 #define XCVR_BWR_XTAL_CTRL_XTAL_COMP_BIAS_HI(base, value) (BME_BFI32(&XCVR_XTAL_CTRL_REG(base), ((u…
43218 #define XCVR_BWR_XTAL_CTRL2_XTAL_REG_SUPPLY(base, value) (BME_BFI32(&XCVR_XTAL_CTRL2_REG(base), ((u…
43235 #define XCVR_BWR_XTAL_CTRL2_XTAL_REG_BYPASS_ON(base, value) (BME_BFI32(&XCVR_XTAL_CTRL2_REG(base), …
43251 #define XCVR_BWR_XTAL_CTRL2_XTAL_REG_ON_OVRD_ON(base, value) (BME_BFI32(&XCVR_XTAL_CTRL2_REG(base),…
43266 #define XCVR_BWR_XTAL_CTRL2_XTAL_REG_ON_OVRD(base, value) (BME_BFI32(&XCVR_XTAL_CTRL2_REG(base), ((…
43282 #define XCVR_BWR_XTAL_CTRL2_XTAL_ON_OVRD_ON(base, value) (BME_BFI32(&XCVR_XTAL_CTRL2_REG(base), ((u…
43297 #define XCVR_BWR_XTAL_CTRL2_XTAL_ON_OVRD(base, value) (BME_BFI32(&XCVR_XTAL_CTRL2_REG(base), ((uint…
43312 #define XCVR_BWR_XTAL_CTRL2_XTAL_DIG_CLK_OUT_ON(base, value) (BME_BFI32(&XCVR_XTAL_CTRL2_REG(base),…
43328 #define XCVR_BWR_XTAL_CTRL2_XTAL_REG_ATST_SEL(base, value) (BME_BFI32(&XCVR_XTAL_CTRL2_REG(base), (…
43345 #define XCVR_BWR_XTAL_CTRL2_XTAL_ATST_SEL(base, value) (BME_BFI32(&XCVR_XTAL_CTRL2_REG(base), ((uin…
43361 #define XCVR_BWR_XTAL_CTRL2_XTAL_ATST_ON(base, value) (BME_BFI32(&XCVR_XTAL_CTRL2_REG(base), ((uint…
43376 #define XCVR_BWR_XTAL_CTRL2_XTAL_SPARE(base, value) (BME_BFI32(&XCVR_XTAL_CTRL2_REG(base), ((uint32…
43416 #define XCVR_BWR_BGAP_CTRL_BGAP_CURRENT_TRIM(base, value) (BME_BFI32(&XCVR_BGAP_CTRL_REG(base), ((u…
43431 #define XCVR_BWR_BGAP_CTRL_BGAP_VOLTAGE_TRIM(base, value) (BME_BFI32(&XCVR_BGAP_CTRL_REG(base), ((u…
43448 #define XCVR_BWR_BGAP_CTRL_BGAP_ATST_SEL(base, value) (BME_BFI32(&XCVR_BGAP_CTRL_REG(base), ((uint3…
43464 #define XCVR_BWR_BGAP_CTRL_BGAP_ATST_ON(base, value) (BME_BFI32(&XCVR_BGAP_CTRL_REG(base), ((uint32…
43505 #define XCVR_BWR_PLL_CTRL_PLL_VCO_BIAS(base, value) (BME_BFI32(&XCVR_PLL_CTRL_REG(base), ((uint32_t…
43522 #define XCVR_BWR_PLL_CTRL_PLL_LFILT_CNTL(base, value) (BME_BFI32(&XCVR_PLL_CTRL_REG(base), ((uint32…
43543 #define XCVR_BWR_PLL_CTRL_PLL_REG_SUPPLY(base, value) (BME_BFI32(&XCVR_PLL_CTRL_REG(base), ((uint32…
43560 #define XCVR_BWR_PLL_CTRL_PLL_REG_BYPASS_ON(base, value) (BME_BFI32(&XCVR_PLL_CTRL_REG(base), ((uin…
43577 #define XCVR_BWR_PLL_CTRL_PLL_VCO_LDO_BYPASS(base, value) (BME_BFI32(&XCVR_PLL_CTRL_REG(base), ((ui…
43593 #define XCVR_BWR_PLL_CTRL_HPM_BIAS(base, value) (BME_BFI32(&XCVR_PLL_CTRL_REG(base), ((uint32_t)(va…
43608 #define XCVR_BWR_PLL_CTRL_PLL_VCO_SPARE7(base, value) (BME_BFI32(&XCVR_PLL_CTRL_REG(base), ((uint32…
43650 #define XCVR_BWR_PLL_CTRL2_PLL_VCO_KV(base, value) (BME_BFI32(&XCVR_PLL_CTRL2_REG(base), ((uint32_t…
43666 #define XCVR_BWR_PLL_CTRL2_PLL_KMOD_SLOPE(base, value) (BME_BFI32(&XCVR_PLL_CTRL2_REG(base), ((uint…
43685 #define XCVR_BWR_PLL_CTRL2_PLL_VCO_REG_SUPPLY(base, value) (BME_BFI32(&XCVR_PLL_CTRL2_REG(base), ((…
43701 #define XCVR_BWR_PLL_CTRL2_PLL_TMUX_ON(base, value) (BME_BFI32(&XCVR_PLL_CTRL2_REG(base), ((uint32_…
43746 #define XCVR_BWR_PLL_TEST_CTRL_PLL_TMUX_SEL(base, value) (BME_BFI32(&XCVR_PLL_TEST_CTRL_REG(base), …
43762 #define XCVR_BWR_PLL_TEST_CTRL_PLL_VCO_REG_ATST(base, value) (BME_BFI32(&XCVR_PLL_TEST_CTRL_REG(bas…
43778 #define XCVR_BWR_PLL_TEST_CTRL_PLL_REG_ATST_SEL(base, value) (BME_BFI32(&XCVR_PLL_TEST_CTRL_REG(bas…
43793 #define XCVR_BWR_PLL_TEST_CTRL_PLL_VCO_TEST_CLK_MODE(base, value) (BME_BFI32(&XCVR_PLL_TEST_CTRL_RE…
43808 #define XCVR_BWR_PLL_TEST_CTRL_PLL_FORCE_VTUNE_EXTERNALLY(base, value) (BME_BFI32(&XCVR_PLL_TEST_CT…
43823 #define XCVR_BWR_PLL_TEST_CTRL_PLL_RIPPLE_COUNTER_TEST_MODE(base, value) (BME_BFI32(&XCVR_PLL_TEST_…
43869 #define XCVR_BWR_QGEN_CTRL_QGEN_REG_SUPPLY(base, value) (BME_BFI32(&XCVR_QGEN_CTRL_REG(base), ((uin…
43885 #define XCVR_BWR_QGEN_CTRL_QGEN_REG_ATST_SEL(base, value) (BME_BFI32(&XCVR_QGEN_CTRL_REG(base), ((u…
43902 #define XCVR_BWR_QGEN_CTRL_QGEN_REG_BYPASS_ON(base, value) (BME_BFI32(&XCVR_QGEN_CTRL_REG(base), ((…
43942 #define XCVR_BWR_TCA_CTRL_TCA_BIAS_CURR(base, value) (BME_BFI32(&XCVR_TCA_CTRL_REG(base), ((uint32_…
43957 #define XCVR_BWR_TCA_CTRL_TCA_LOW_PWR_ON(base, value) (BME_BFI32(&XCVR_TCA_CTRL_REG(base), ((uint32…
43974 #define XCVR_BWR_TCA_CTRL_TCA_TX_REG_BYPASS_ON(base, value) (BME_BFI32(&XCVR_TCA_CTRL_REG(base), ((…
43995 #define XCVR_BWR_TCA_CTRL_TCA_TX_REG_SUPPLY(base, value) (BME_BFI32(&XCVR_TCA_CTRL_REG(base), ((uin…
44011 #define XCVR_BWR_TCA_CTRL_TCA_TX_REG_ATST_SEL(base, value) (BME_BFI32(&XCVR_TCA_CTRL_REG(base), ((u…
44053 #define XCVR_BWR_TZA_CTRL_TZA_CAP_TUNE(base, value) (BME_BFI32(&XCVR_TZA_CTRL_REG(base), ((uint32_t…
44068 #define XCVR_BWR_TZA_CTRL_TZA_GAIN(base, value) (BME_BFI32(&XCVR_TZA_CTRL_REG(base), ((uint32_t)(va…
44084 #define XCVR_BWR_TZA_CTRL_TZA_DCOC_ON(base, value) (BME_BFI32(&XCVR_TZA_CTRL_REG(base), ((uint32_t)…
44099 #define XCVR_BWR_TZA_CTRL_TZA_CUR_CNTL(base, value) (BME_BFI32(&XCVR_TZA_CTRL_REG(base), ((uint32_t…
44114 #define XCVR_BWR_TZA_CTRL_TZA_SPARE(base, value) (BME_BFI32(&XCVR_TZA_CTRL_REG(base), ((uint32_t)(v…
44155 #define XCVR_BWR_TX_ANA_CTRL_HPM_CAL_ADJUST(base, value) (BME_BFI32(&XCVR_TX_ANA_CTRL_REG(base), ((…
44199 #define XCVR_BWR_ANA_SPARE_IQMC_DC_GAIN_ADJ(base, value) (BME_BFI32(&XCVR_ANA_SPARE_REG(base), ((ui…
44225 #define XCVR_BWR_ANA_SPARE_DCOC_TRK_EST_GS_CNT(base, value) (BME_BFI32(&XCVR_ANA_SPARE_REG(base), (…
44240 #define XCVR_BWR_ANA_SPARE_HPM_LSB_INVERT(base, value) (BME_BFI32(&XCVR_ANA_SPARE_REG(base), ((uint…
44347 #define ZLL_BWR_IRQSTS_SEQIRQ(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value) << …
44364 #define ZLL_BWR_IRQSTS_TXIRQ(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value) << Z…
44381 #define ZLL_BWR_IRQSTS_RXIRQ(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value) << Z…
44398 #define ZLL_BWR_IRQSTS_CCAIRQ(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value) << …
44415 #define ZLL_BWR_IRQSTS_RXWTRMRKIRQ(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value…
44432 #define ZLL_BWR_IRQSTS_FILTERFAIL_IRQ(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(va…
44449 #define ZLL_BWR_IRQSTS_PLL_UNLOCK_IRQ(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(va…
44475 #define ZLL_BWR_IRQSTS_PB_ERR_IRQ(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value)…
44572 #define ZLL_BWR_IRQSTS_TMR1IRQ(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value) <<…
44589 #define ZLL_BWR_IRQSTS_TMR2IRQ(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value) <<…
44605 #define ZLL_BWR_IRQSTS_TMR3IRQ(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value) <<…
44621 #define ZLL_BWR_IRQSTS_TMR4IRQ(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value) <<…
44638 #define ZLL_BWR_IRQSTS_TMR1MSK(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value) <<…
44655 #define ZLL_BWR_IRQSTS_TMR2MSK(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value) <<…
44672 #define ZLL_BWR_IRQSTS_TMR3MSK(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value) <<…
44689 #define ZLL_BWR_IRQSTS_TMR4MSK(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value) <<…
44753 #define ZLL_BWR_PHY_CTRL_XCVSEQ(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value)…
44775 #define ZLL_BWR_PHY_CTRL_AUTOACK(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value…
44796 #define ZLL_BWR_PHY_CTRL_RXACKRQD(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(valu…
44816 #define ZLL_BWR_PHY_CTRL_CCABFRTX(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(valu…
44835 #define ZLL_BWR_PHY_CTRL_SLOTTED(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value…
44853 #define ZLL_BWR_PHY_CTRL_TMRTRIGEN(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(val…
44871 #define ZLL_BWR_PHY_CTRL_SEQMSK(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value)…
44889 #define ZLL_BWR_PHY_CTRL_TXMSK(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value) …
44907 #define ZLL_BWR_PHY_CTRL_RXMSK(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value) …
44927 #define ZLL_BWR_PHY_CTRL_CCAMSK(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value)…
44948 #define ZLL_BWR_PHY_CTRL_RX_WMRK_MSK(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(v…
44969 #define ZLL_BWR_PHY_CTRL_FILTERFAIL_MSK(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t…
44987 #define ZLL_BWR_PHY_CTRL_PLL_UNLOCK_MSK(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t…
45010 #define ZLL_BWR_PHY_CTRL_CRC_MSK(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value…
45027 #define ZLL_BWR_PHY_CTRL_PB_ERR_MSK(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(va…
45044 #define ZLL_BWR_PHY_CTRL_TMR1CMP_EN(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(va…
45061 #define ZLL_BWR_PHY_CTRL_TMR2CMP_EN(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(va…
45078 #define ZLL_BWR_PHY_CTRL_TMR3CMP_EN(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(va…
45095 #define ZLL_BWR_PHY_CTRL_TMR4CMP_EN(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(va…
45114 #define ZLL_BWR_PHY_CTRL_TC2PRIME_EN(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(v…
45134 #define ZLL_BWR_PHY_CTRL_PROMISCUOUS(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(v…
45168 #define ZLL_BWR_PHY_CTRL_CCATYPE(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value…
45184 #define ZLL_BWR_PHY_CTRL_PANCORDNTR0(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(v…
45203 #define ZLL_BWR_PHY_CTRL_TC3TMOUT(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(valu…
45222 #define ZLL_BWR_PHY_CTRL_TRCV_MSK(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(valu…
45409 #define ZLL_BWR_T2PRIMECMP_T2PRIMECMP(base, value) (BME_BFI32(&ZLL_T2PRIMECMP_REG(base), ((uint32_t…
45531 #define ZLL_BWR_PA_PWR_PA_PWR(base, value) (BME_BFI32(&ZLL_PA_PWR_REG(base), ((uint32_t)(value) << …
45573 #define ZLL_BWR_CHANNEL_NUM0_CHANNEL_NUM0(base, value) (BME_BFI32(&ZLL_CHANNEL_NUM0_REG(base), ((ui…
45674 #define ZLL_BWR_MACSHORTADDRS0_MACPANID0(base, value) (BME_BFI32(&ZLL_MACSHORTADDRS0_REG(base), ((u…
45691 #define ZLL_BWR_MACSHORTADDRS0_MACSHORTADDRS0(base, value) (BME_BFI32(&ZLL_MACSHORTADDRS0_REG(base)…
45783 #define ZLL_BWR_RX_FRAME_FILTER_BEACON_FT(base, value) (BME_BFI32(&ZLL_RX_FRAME_FILTER_REG(base), (…
45800 #define ZLL_BWR_RX_FRAME_FILTER_DATA_FT(base, value) (BME_BFI32(&ZLL_RX_FRAME_FILTER_REG(base), ((u…
45817 #define ZLL_BWR_RX_FRAME_FILTER_ACK_FT(base, value) (BME_BFI32(&ZLL_RX_FRAME_FILTER_REG(base), ((ui…
45834 #define ZLL_BWR_RX_FRAME_FILTER_CMD_FT(base, value) (BME_BFI32(&ZLL_RX_FRAME_FILTER_REG(base), ((ui…
45853 #define ZLL_BWR_RX_FRAME_FILTER_NS_FT(base, value) (BME_BFI32(&ZLL_RX_FRAME_FILTER_REG(base), ((uin…
45872 #define ZLL_BWR_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS(base, value) (BME_BFI32(&ZLL_RX_FRAME_FILTER_REG…
45895 #define ZLL_BWR_RX_FRAME_FILTER_FRM_VER(base, value) (BME_BFI32(&ZLL_RX_FRAME_FILTER_REG(base), ((u…
45935 #define ZLL_BWR_CCA_LQI_CTRL_CCA1_THRESH(base, value) (BME_BFI32(&ZLL_CCA_LQI_CTRL_REG(base), ((uin…
45950 #define ZLL_BWR_CCA_LQI_CTRL_LQI_OFFSET_COMP(base, value) (BME_BFI32(&ZLL_CCA_LQI_CTRL_REG(base), (…
45969 #define ZLL_BWR_CCA_LQI_CTRL_CCA3_AND_NOT_OR(base, value) (BME_BFI32(&ZLL_CCA_LQI_CTRL_REG(base), (…
46027 #define ZLL_BWR_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH(base, value) (BME_BFI32(&ZLL_CCA2_CTRL_REG(base), ((…
46046 #define ZLL_BWR_CCA2_CTRL_CCA2_CORR_THRESH(base, value) (BME_BFI32(&ZLL_CCA2_CTRL_REG(base), ((uint…
46088 #define ZLL_BWR_FAD_CTRL_FAD_EN(base, value) (BME_BFI32(&ZLL_FAD_CTRL_REG(base), ((uint32_t)(value)…
46107 #define ZLL_BWR_FAD_CTRL_ANTX(base, value) (BME_BFI32(&ZLL_FAD_CTRL_REG(base), ((uint32_t)(value) <…
46129 #define ZLL_BWR_FAD_CTRL_FAD_NOT_GPIO(base, value) (BME_BFI32(&ZLL_FAD_CTRL_REG(base), ((uint32_t)(…
46151 #define ZLL_BWR_FAD_CTRL_ANTX_EN(base, value) (BME_BFI32(&ZLL_FAD_CTRL_REG(base), ((uint32_t)(value…
46169 #define ZLL_BWR_FAD_CTRL_ANTX_HZ(base, value) (BME_BFI32(&ZLL_FAD_CTRL_REG(base), ((uint32_t)(value…
46192 #define ZLL_BWR_FAD_CTRL_ANTX_CTRLMODE(base, value) (BME_BFI32(&ZLL_FAD_CTRL_REG(base), ((uint32_t)…
46212 #define ZLL_BWR_FAD_CTRL_ANTX_POL(base, value) (BME_BFI32(&ZLL_FAD_CTRL_REG(base), ((uint32_t)(valu…
46255 #define ZLL_BWR_SNF_CTRL_SNF_EN(base, value) (BME_BFI32(&ZLL_SNF_CTRL_REG(base), ((uint32_t)(value)…
46299 #define ZLL_BWR_BSM_CTRL_BSM_EN(base, value) (BME_BFI32(&ZLL_BSM_CTRL_REG(base), ((uint32_t)(value)…
46345 #define ZLL_BWR_MACSHORTADDRS1_MACPANID1(base, value) (BME_BFI32(&ZLL_MACSHORTADDRS1_REG(base), ((u…
46362 #define ZLL_BWR_MACSHORTADDRS1_MACSHORTADDRS1(base, value) (BME_BFI32(&ZLL_MACSHORTADDRS1_REG(base)…
46461 #define ZLL_BWR_DUAL_PAN_CTRL_ACTIVE_NETWORK(base, value) (BME_BFI32(&ZLL_DUAL_PAN_CTRL_REG(base), …
46481 #define ZLL_BWR_DUAL_PAN_CTRL_DUAL_PAN_AUTO(base, value) (BME_BFI32(&ZLL_DUAL_PAN_CTRL_REG(base), (…
46497 #define ZLL_BWR_DUAL_PAN_CTRL_PANCORDNTR1(base, value) (BME_BFI32(&ZLL_DUAL_PAN_CTRL_REG(base), ((u…
46545 #define ZLL_BWR_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN(base, value) (BME_BFI32(&ZLL_DUAL_PAN_CTRL_REG(bas…
46562 #define ZLL_BWR_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL(base, value) (BME_BFI32(&ZLL_DUAL_PAN_CTRL_REG(ba…
46591 #define ZLL_BWR_DUAL_PAN_CTRL_DUAL_PAN_DWELL(base, value) (BME_BFI32(&ZLL_DUAL_PAN_CTRL_REG(base), …
46686 #define ZLL_BWR_CHANNEL_NUM1_CHANNEL_NUM1(base, value) (BME_BFI32(&ZLL_CHANNEL_NUM1_REG(base), ((ui…
46730 #define ZLL_BWR_SAM_CTRL_SAP0_EN(base, value) (BME_BFI32(&ZLL_SAM_CTRL_REG(base), ((uint32_t)(value…
46747 #define ZLL_BWR_SAM_CTRL_SAA0_EN(base, value) (BME_BFI32(&ZLL_SAM_CTRL_REG(base), ((uint32_t)(value…
46764 #define ZLL_BWR_SAM_CTRL_SAP1_EN(base, value) (BME_BFI32(&ZLL_SAM_CTRL_REG(base), ((uint32_t)(value…
46781 #define ZLL_BWR_SAM_CTRL_SAA1_EN(base, value) (BME_BFI32(&ZLL_SAM_CTRL_REG(base), ((uint32_t)(value…
46794 #define ZLL_BWR_SAM_CTRL_SAA0_START(base, value) (BME_BFI32(&ZLL_SAM_CTRL_REG(base), ((uint32_t)(va…
46807 #define ZLL_BWR_SAM_CTRL_SAP1_START(base, value) (BME_BFI32(&ZLL_SAM_CTRL_REG(base), ((uint32_t)(va…
46820 #define ZLL_BWR_SAM_CTRL_SAA1_START(base, value) (BME_BFI32(&ZLL_SAM_CTRL_REG(base), ((uint32_t)(va…
46863 #define ZLL_BWR_SAM_TABLE_SAM_INDEX(base, value) (BME_BFI32(&ZLL_SAM_TABLE_REG(base), ((uint32_t)(v…
46900 #define ZLL_BWR_SAM_TABLE_SAM_CHECKSUM(base, value) (BME_BFI32(&ZLL_SAM_TABLE_REG(base), ((uint32_t…
46938 #define ZLL_BWR_SAM_TABLE_ACK_FRM_PND(base, value) (BME_BFI32(&ZLL_SAM_TABLE_REG(base), ((uint32_t)…
46957 #define ZLL_BWR_SAM_TABLE_ACK_FRM_PND_CTRL(base, value) (BME_BFI32(&ZLL_SAM_TABLE_REG(base), ((uint…
47197 #define ZLL_BWR_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT(base, value) (BME_BFI32(&ZLL_SEQ_CTRL_STS_REG(base…
47218 #define ZLL_BWR_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH(base, value) (BME_BFI32(&ZLL_SEQ_CTRL_STS_REG(b…
47239 #define ZLL_BWR_SEQ_CTRL_STS_LATCH_PREAMBLE(base, value) (BME_BFI32(&ZLL_SEQ_CTRL_STS_REG(base), ((…
47260 #define ZLL_BWR_SEQ_CTRL_STS_NO_RX_RECYCLE(base, value) (BME_BFI32(&ZLL_SEQ_CTRL_STS_REG(base), ((u…
47277 #define ZLL_BWR_SEQ_CTRL_STS_FORCE_CRC_ERROR(base, value) (BME_BFI32(&ZLL_SEQ_CTRL_STS_REG(base), (…
47297 #define ZLL_BWR_SEQ_CTRL_STS_CONTINUOUS_EN(base, value) (BME_BFI32(&ZLL_SEQ_CTRL_STS_REG(base), ((u…
47488 #define ZLL_BWR_ACKDELAY_ACKDELAY(base, value) (BME_BFI32(&ZLL_ACKDELAY_REG(base), ((uint32_t)(valu…
47509 #define ZLL_BWR_ACKDELAY_TXDELAY(base, value) (BME_BFI32(&ZLL_ACKDELAY_REG(base), ((uint32_t)(value…
47575 #define ZLL_BWR_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL(base, value) (BME_BFI32(&ZLL_FILTERFAIL_CODE_REG…
47618 #define ZLL_BWR_RX_WTR_MARK_RX_WTR_MARK(base, value) (BME_BFI32(&ZLL_RX_WTR_MARK_REG(base), ((uint3…
47665 #define ZLL_BWR_SLOT_PRELOAD_SLOT_PRELOAD(base, value) (BME_BFI32(&ZLL_SLOT_PRELOAD_REG(base), ((ui…
47886 #define ZLL_BWR_TMR_PRESCALE_TMR_PRESCALE(base, value) (BME_BFI32(&ZLL_TMR_PRESCALE_REG(base), ((ui…
47990 #define ZLL_BWR_LENIENCY_MSB_LENIENCY_REGISTER(base, value) (BME_BFI32(&ZLL_LENIENCY_MSB_REG(base),…