Lines Matching refs:BME_AND32

149 #define ADC_CLR_SC1(base, index, value) (BME_AND32(&ADC_SC1_REG(base, index), (uint32_t)(~(value))))
330 #define ADC_CLR_CFG1(base, value) (BME_AND32(&ADC_CFG1_REG(base), (uint32_t)(~(value))))
478 #define ADC_CLR_CFG2(base, value) (BME_AND32(&ADC_CFG2_REG(base), (uint32_t)(~(value))))
667 #define ADC_CLR_CV1(base, value) (BME_AND32(&ADC_CV1_REG(base), (uint32_t)(~(value))))
714 #define ADC_CLR_CV2(base, value) (BME_AND32(&ADC_CV2_REG(base), (uint32_t)(~(value))))
756 #define ADC_CLR_SC2(base, value) (BME_AND32(&ADC_SC2_REG(base), (uint32_t)(~(value))))
933 #define ADC_CLR_SC3(base, value) (BME_AND32(&ADC_SC3_REG(base), (uint32_t)(~(value))))
1092 #define ADC_CLR_OFS(base, value) (BME_AND32(&ADC_OFS_REG(base), (uint32_t)(~(value))))
1144 #define ADC_CLR_PG(base, value)  (BME_AND32(&ADC_PG_REG(base), (uint32_t)(~(value))))
1194 #define ADC_CLR_MG(base, value)  (BME_AND32(&ADC_MG_REG(base), (uint32_t)(~(value))))
1250 #define ADC_CLR_CLPD(base, value) (BME_AND32(&ADC_CLPD_REG(base), (uint32_t)(~(value))))
1292 #define ADC_CLR_CLPS(base, value) (BME_AND32(&ADC_CLPS_REG(base), (uint32_t)(~(value))))
1334 #define ADC_CLR_CLP4(base, value) (BME_AND32(&ADC_CLP4_REG(base), (uint32_t)(~(value))))
1376 #define ADC_CLR_CLP3(base, value) (BME_AND32(&ADC_CLP3_REG(base), (uint32_t)(~(value))))
1418 #define ADC_CLR_CLP2(base, value) (BME_AND32(&ADC_CLP2_REG(base), (uint32_t)(~(value))))
1460 #define ADC_CLR_CLP1(base, value) (BME_AND32(&ADC_CLP1_REG(base), (uint32_t)(~(value))))
1502 #define ADC_CLR_CLP0(base, value) (BME_AND32(&ADC_CLP0_REG(base), (uint32_t)(~(value))))
1560 #define ADC_CLR_CLMD(base, value) (BME_AND32(&ADC_CLMD_REG(base), (uint32_t)(~(value))))
1602 #define ADC_CLR_CLMS(base, value) (BME_AND32(&ADC_CLMS_REG(base), (uint32_t)(~(value))))
1644 #define ADC_CLR_CLM4(base, value) (BME_AND32(&ADC_CLM4_REG(base), (uint32_t)(~(value))))
1686 #define ADC_CLR_CLM3(base, value) (BME_AND32(&ADC_CLM3_REG(base), (uint32_t)(~(value))))
1728 #define ADC_CLR_CLM2(base, value) (BME_AND32(&ADC_CLM2_REG(base), (uint32_t)(~(value))))
1770 #define ADC_CLR_CLM1(base, value) (BME_AND32(&ADC_CLM1_REG(base), (uint32_t)(~(value))))
1812 #define ADC_CLR_CLM0(base, value) (BME_AND32(&ADC_CLM0_REG(base), (uint32_t)(~(value))))
3707 #define DCDC_CLR_REG0(base, value) (BME_AND32(&DCDC_REG0_REG(base), (uint32_t)(~(value))))
4017 #define DCDC_CLR_REG1(base, value) (BME_AND32(&DCDC_REG1_REG(base), (uint32_t)(~(value))))
4140 #define DCDC_CLR_REG2(base, value) (BME_AND32(&DCDC_REG2_REG(base), (uint32_t)(~(value))))
4268 #define DCDC_CLR_REG3(base, value) (BME_AND32(&DCDC_REG3_REG(base), (uint32_t)(~(value))))
4498 #define DCDC_CLR_REG4(base, value) (BME_AND32(&DCDC_REG4_REG(base), (uint32_t)(~(value))))
4555 #define DCDC_CLR_REG6(base, value) (BME_AND32(&DCDC_REG6_REG(base), (uint32_t)(~(value))))
4651 #define DCDC_CLR_REG7(base, value) (BME_AND32(&DCDC_REG7_REG(base), (uint32_t)(~(value))))
4749 #define DMA_CLR_SAR(base, index, value) (BME_AND32(&DMA_SAR_REG(base, index), (uint32_t)(~(value))))
4777 #define DMA_CLR_DAR(base, index, value) (BME_AND32(&DMA_DAR_REG(base, index), (uint32_t)(~(value))))
4810 #define DMA_CLR_DSR_BCR(base, index, value) (BME_AND32(&DMA_DSR_BCR_REG(base, index), (uint32_t)(~(…
4983 #define DMA_CLR_DCR(base, index, value) (BME_AND32(&DMA_DCR_REG(base, index), (uint32_t)(~(value))))
7090 #define GPIO_CLR_PDOR(base, value) (BME_AND32(&GPIO_PDOR_REG(base), (uint32_t)(~(value))))
7191 #define GPIO_CLR_PDDR(base, value) (BME_AND32(&GPIO_PDDR_REG(base), (uint32_t)(~(value))))
9891 #define LPTMR_CLR_CSR(base, value) (BME_AND32(&LPTMR_CSR_REG(base), (uint32_t)(~(value))))
10063 #define LPTMR_CLR_PSR(base, value) (BME_AND32(&LPTMR_PSR_REG(base), (uint32_t)(~(value))))
10185 #define LPTMR_CLR_CMR(base, value) (BME_AND32(&LPTMR_CMR_REG(base), (uint32_t)(~(value))))
10229 #define LPTMR_CLR_CNR(base, value) (BME_AND32(&LPTMR_CNR_REG(base), (uint32_t)(~(value))))
10284 #define LPUART_CLR_BAUD(base, value) (BME_AND32(&LPUART_BAUD_REG(base), (uint32_t)(~(value))))
10570 #define LPUART_CLR_STAT(base, value) (BME_AND32(&LPUART_STAT_REG(base), (uint32_t)(~(value))))
11013 #define LPUART_CLR_CTRL(base, value) (BME_AND32(&LPUART_CTRL_REG(base), (uint32_t)(~(value))))
11605 #define LPUART_CLR_DATA(base, value) (BME_AND32(&LPUART_DATA_REG(base), (uint32_t)(~(value))))
11870 #define LPUART_CLR_MATCH(base, value) (BME_AND32(&LPUART_MATCH_REG(base), (uint32_t)(~(value))))
11935 #define LPUART_CLR_MODIR(base, value) (BME_AND32(&LPUART_MODIR_REG(base), (uint32_t)(~(value))))
12160 #define LTC_CLR_MD(base, value)  (BME_AND32(&LTC_MD_REG(base), (uint32_t)(~(value))))
12304 #define LTC_CLR_KS(base, value)  (BME_AND32(&LTC_KS_REG(base), (uint32_t)(~(value))))
12336 #define LTC_CLR_DS(base, value)  (BME_AND32(&LTC_DS_REG(base), (uint32_t)(~(value))))
12384 #define LTC_CLR_ICVS(base, value) (BME_AND32(&LTC_ICVS_REG(base), (uint32_t)(~(value))))
12484 #define LTC_CLR_CTL(base, value) (BME_AND32(&LTC_CTL_REG(base), (uint32_t)(~(value))))
12878 #define LTC_CLR_STA(base, value) (BME_AND32(&LTC_STA_REG(base), (uint32_t)(~(value))))
13040 #define LTC_CLR_AADSZ(base, value) (BME_AND32(&LTC_AADSZ_REG(base), (uint32_t)(~(value))))
13104 #define LTC_CLR_CTX(base, index, value) (BME_AND32(&LTC_CTX_REG(base, index), (uint32_t)(~(value))))
13133 #define LTC_CLR_KEY(base, index, value) (BME_AND32(&LTC_KEY_REG(base, index), (uint32_t)(~(value))))
16241 #define PIT_CLR_MCR(base, value) (BME_AND32(&PIT_MCR_REG(base), (uint32_t)(~(value))))
16351 #define PIT_CLR_LDVAL(base, index, value) (BME_AND32(&PIT_LDVAL_REG(base, index), (uint32_t)(~(valu…
16393 #define PIT_CLR_TCTRL(base, index, value) (BME_AND32(&PIT_TCTRL_REG(base, index), (uint32_t)(~(valu…
16481 #define PIT_CLR_TFLG(base, index, value) (BME_AND32(&PIT_TFLG_REG(base, index), (uint32_t)(~(value)…
16910 #define PORT_CLR_PCR(base, index, value) (BME_AND32(&PORT_PCR_REG(base, index), (uint32_t)(~(value)…
17249 #define PORT_CLR_ISFR(base, value) (BME_AND32(&PORT_ISFR_REG(base), (uint32_t)(~(value))))
17928 #define RSIM_CLR_CONTROL(base, value) (BME_AND32(&RSIM_CONTROL_REG(base), (uint32_t)(~(value))))
18300 #define RSIM_CLR_ACTIVE_DELAY(base, value) (BME_AND32(&RSIM_ACTIVE_DELAY_REG(base), (uint32_t)(~(va…
18424 #define RSIM_CLR_ANA_TEST(base, value) (BME_AND32(&RSIM_ANA_TEST_REG(base), (uint32_t)(~(value))))
18501 #define RTC_CLR_TSR(base, value) (BME_AND32(&RTC_TSR_REG(base), (uint32_t)(~(value))))
18522 #define RTC_CLR_TPR(base, value) (BME_AND32(&RTC_TPR_REG(base), (uint32_t)(~(value))))
18566 #define RTC_CLR_TAR(base, value) (BME_AND32(&RTC_TAR_REG(base), (uint32_t)(~(value))))
18587 #define RTC_CLR_TCR(base, value) (BME_AND32(&RTC_TCR_REG(base), (uint32_t)(~(value))))
18683 #define RTC_CLR_CR(base, value)  (BME_AND32(&RTC_CR_REG(base), (uint32_t)(~(value))))
18910 #define RTC_CLR_SR(base, value)  (BME_AND32(&RTC_SR_REG(base), (uint32_t)(~(value))))
19006 #define RTC_CLR_LR(base, value)  (BME_AND32(&RTC_LR_REG(base), (uint32_t)(~(value))))
19108 #define RTC_CLR_IER(base, value) (BME_AND32(&RTC_IER_REG(base), (uint32_t)(~(value))))
19257 #define SIM_CLR_SOPT1(base, value) (BME_AND32(&SIM_SOPT1_REG(base), (uint32_t)(~(value))))
19331 #define SIM_CLR_SOPT2(base, value) (BME_AND32(&SIM_SOPT2_REG(base), (uint32_t)(~(value))))
19423 #define SIM_CLR_SOPT4(base, value) (BME_AND32(&SIM_SOPT4_REG(base), (uint32_t)(~(value))))
19551 #define SIM_CLR_SOPT5(base, value) (BME_AND32(&SIM_SOPT5_REG(base), (uint32_t)(~(value))))
19633 #define SIM_CLR_SOPT7(base, value) (BME_AND32(&SIM_SOPT7_REG(base), (uint32_t)(~(value))))
19876 #define SIM_CLR_SCGC4(base, value) (BME_AND32(&SIM_SCGC4_REG(base), (uint32_t)(~(value))))
19985 #define SIM_CLR_SCGC5(base, value) (BME_AND32(&SIM_SCGC5_REG(base), (uint32_t)(~(value))))
20231 #define SIM_CLR_SCGC6(base, value) (BME_AND32(&SIM_SCGC6_REG(base), (uint32_t)(~(value))))
20486 #define SIM_CLR_SCGC7(base, value) (BME_AND32(&SIM_SCGC7_REG(base), (uint32_t)(~(value))))
20533 #define SIM_CLR_CLKDIV1(base, value) (BME_AND32(&SIM_CLKDIV1_REG(base), (uint32_t)(~(value))))
20623 #define SIM_CLR_FCFG1(base, value) (BME_AND32(&SIM_FCFG1_REG(base), (uint32_t)(~(value))))
20832 #define SIM_CLR_COPC(base, value) (BME_AND32(&SIM_COPC_REG(base), (uint32_t)(~(value))))
21390 #define SPI_CLR_MCR(base, value) (BME_AND32(&SPI_MCR_REG(base), (uint32_t)(~(value))))
21715 #define SPI_CLR_TCR(base, value) (BME_AND32(&SPI_TCR_REG(base), (uint32_t)(~(value))))
21762 #define SPI_CLR_CTAR_SLAVE(base, index, value) (BME_AND32(&SPI_CTAR_SLAVE_REG(base, index), (uint32…
21860 #define SPI_CLR_CTAR(base, index, value) (BME_AND32(&SPI_CTAR_REG(base, index), (uint32_t)(~(value)…
22186 #define SPI_CLR_SR(base, value)  (BME_AND32(&SPI_SR_REG(base), (uint32_t)(~(value))))
22417 #define SPI_CLR_RSER(base, value) (BME_AND32(&SPI_RSER_REG(base), (uint32_t)(~(value))))
22609 #define SPI_CLR_PUSHR(base, value) (BME_AND32(&SPI_PUSHR_REG(base), (uint32_t)(~(value))))
22764 #define SPI_CLR_PUSHR_SLAVE(base, value) (BME_AND32(&SPI_PUSHR_SLAVE_REG(base), (uint32_t)(~(value)…
23120 #define TPM_CLR_SC(base, value)  (BME_AND32(&TPM_SC_REG(base), (uint32_t)(~(value))))
23283 #define TPM_CLR_CNT(base, value) (BME_AND32(&TPM_CNT_REG(base), (uint32_t)(~(value))))
23332 #define TPM_CLR_MOD(base, value) (BME_AND32(&TPM_MOD_REG(base), (uint32_t)(~(value))))
23387 #define TPM_CLR_CnSC(base, index, value) (BME_AND32(&TPM_CnSC_REG(base, index), (uint32_t)(~(value)…
23549 #define TPM_CLR_CnV(base, index, value) (BME_AND32(&TPM_CnV_REG(base, index), (uint32_t)(~(value))))
23601 #define TPM_CLR_STATUS(base, value) (BME_AND32(&TPM_STATUS_REG(base), (uint32_t)(~(value))))
23725 #define TPM_CLR_COMBINE(base, value) (BME_AND32(&TPM_COMBINE_REG(base), (uint32_t)(~(value))))
23840 #define TPM_CLR_FILTER(base, value) (BME_AND32(&TPM_FILTER_REG(base), (uint32_t)(~(value))))
23935 #define TPM_CLR_QDCTRL(base, value) (BME_AND32(&TPM_QDCTRL_REG(base), (uint32_t)(~(value))))
24037 #define TPM_CLR_CONF(base, value) (BME_AND32(&TPM_CONF_REG(base), (uint32_t)(~(value))))
24282 #define TRNG_CLR_MCTL(base, value) (BME_AND32(&TRNG_MCTL_REG(base), (uint32_t)(~(value))))
24530 #define TRNG_CLR_SCMISC(base, value) (BME_AND32(&TRNG_SCMISC_REG(base), (uint32_t)(~(value))))
24597 #define TRNG_CLR_PKRRNG(base, value) (BME_AND32(&TRNG_PKRRNG_REG(base), (uint32_t)(~(value))))
24648 #define TRNG_CLR_PKRMAX(base, value) (BME_AND32(&TRNG_PKRMAX_REG(base), (uint32_t)(~(value))))
24746 #define TRNG_CLR_SDCTL(base, value) (BME_AND32(&TRNG_SDCTL_REG(base), (uint32_t)(~(value))))
24813 #define TRNG_CLR_SBLIM(base, value) (BME_AND32(&TRNG_SBLIM_REG(base), (uint32_t)(~(value))))
24908 #define TRNG_CLR_FRQMIN(base, value) (BME_AND32(&TRNG_FRQMIN_REG(base), (uint32_t)(~(value))))
24958 #define TRNG_CLR_FRQMAX(base, value) (BME_AND32(&TRNG_FRQMAX_REG(base), (uint32_t)(~(value))))
25093 #define TRNG_CLR_SCML(base, value) (BME_AND32(&TRNG_SCML_REG(base), (uint32_t)(~(value))))
25165 #define TRNG_CLR_SCR1L(base, value) (BME_AND32(&TRNG_SCR1L_REG(base), (uint32_t)(~(value))))
25291 #define TRNG_CLR_SCR2L(base, value) (BME_AND32(&TRNG_SCR2L_REG(base), (uint32_t)(~(value))))
25470 #define TRNG_CLR_SCR3L(base, value) (BME_AND32(&TRNG_SCR3L_REG(base), (uint32_t)(~(value))))
25596 #define TRNG_CLR_SCR4L(base, value) (BME_AND32(&TRNG_SCR4L_REG(base), (uint32_t)(~(value))))
25669 #define TRNG_CLR_SCR5L(base, value) (BME_AND32(&TRNG_SCR5L_REG(base), (uint32_t)(~(value))))
25795 #define TRNG_CLR_SCR6PL(base, value) (BME_AND32(&TRNG_SCR6PL_REG(base), (uint32_t)(~(value))))
26589 #define TRNG_CLR_SEC_CFG(base, value) (BME_AND32(&TRNG_SEC_CFG_REG(base), (uint32_t)(~(value))))
26682 #define TRNG_CLR_INT_CTRL(base, value) (BME_AND32(&TRNG_INT_CTRL_REG(base), (uint32_t)(~(value))))
26788 #define TRNG_CLR_INT_MASK(base, value) (BME_AND32(&TRNG_INT_MASK_REG(base), (uint32_t)(~(value))))
26883 #define TRNG_CLR_INT_STATUS(base, value) (BME_AND32(&TRNG_INT_STATUS_REG(base), (uint32_t)(~(value)…
27124 #define TSI_CLR_GENCS(base, value) (BME_AND32(&TSI_GENCS_REG(base), (uint32_t)(~(value))))
27501 #define TSI_CLR_DATA(base, value) (BME_AND32(&TSI_DATA_REG(base), (uint32_t)(~(value))))
27614 #define TSI_CLR_TSHD(base, value) (BME_AND32(&TSI_TSHD_REG(base), (uint32_t)(~(value))))
27844 #define XCVR_CLR_RX_DIG_CTRL(base, value) (BME_AND32(&XCVR_RX_DIG_CTRL_REG(base), (uint32_t)(~(valu…
28072 #define XCVR_CLR_AGC_CTRL_0(base, value) (BME_AND32(&XCVR_AGC_CTRL_0_REG(base), (uint32_t)(~(value)…
28260 #define XCVR_CLR_AGC_CTRL_1(base, value) (BME_AND32(&XCVR_AGC_CTRL_1_REG(base), (uint32_t)(~(value)…
28411 #define XCVR_CLR_AGC_CTRL_2(base, value) (BME_AND32(&XCVR_AGC_CTRL_2_REG(base), (uint32_t)(~(value)…
28596 #define XCVR_CLR_AGC_CTRL_3(base, value) (BME_AND32(&XCVR_AGC_CTRL_3_REG(base), (uint32_t)(~(value)…
28797 #define XCVR_CLR_RSSI_CTRL_0(base, value) (BME_AND32(&XCVR_RSSI_CTRL_0_REG(base), (uint32_t)(~(valu…
28940 #define XCVR_CLR_RSSI_CTRL_1(base, value) (BME_AND32(&XCVR_RSSI_CTRL_1_REG(base), (uint32_t)(~(valu…
29036 #define XCVR_CLR_DCOC_CTRL_0(base, value) (BME_AND32(&XCVR_DCOC_CTRL_0_REG(base), (uint32_t)(~(valu…
29226 #define XCVR_CLR_DCOC_CTRL_1(base, value) (BME_AND32(&XCVR_DCOC_CTRL_1_REG(base), (uint32_t)(~(valu…
29330 #define XCVR_CLR_DCOC_CTRL_2(base, value) (BME_AND32(&XCVR_DCOC_CTRL_2_REG(base), (uint32_t)(~(valu…
29373 #define XCVR_CLR_DCOC_CTRL_3(base, value) (BME_AND32(&XCVR_DCOC_CTRL_3_REG(base), (uint32_t)(~(valu…
29458 #define XCVR_CLR_DCOC_CTRL_4(base, value) (BME_AND32(&XCVR_DCOC_CTRL_4_REG(base), (uint32_t)(~(valu…
29515 #define XCVR_CLR_DCOC_CAL_GAIN(base, value) (BME_AND32(&XCVR_DCOC_CAL_GAIN_REG(base), (uint32_t)(~(…
29756 #define XCVR_CLR_DCOC_CAL_RCP(base, value) (BME_AND32(&XCVR_DCOC_CAL_RCP_REG(base), (uint32_t)(~(va…
29816 #define XCVR_CLR_IQMC_CTRL(base, value) (BME_AND32(&XCVR_IQMC_CTRL_REG(base), (uint32_t)(~(value))))
29871 #define XCVR_CLR_IQMC_CAL(base, value) (BME_AND32(&XCVR_IQMC_CAL_REG(base), (uint32_t)(~(value))))
29926 #define XCVR_CLR_TCA_AGC_VAL_3_0(base, value) (BME_AND32(&XCVR_TCA_AGC_VAL_3_0_REG(base), (uint32_t…
30011 #define XCVR_CLR_TCA_AGC_VAL_7_4(base, value) (BME_AND32(&XCVR_TCA_AGC_VAL_7_4_REG(base), (uint32_t…
30096 #define XCVR_CLR_TCA_AGC_VAL_8(base, value) (BME_AND32(&XCVR_TCA_AGC_VAL_8_REG(base), (uint32_t)(~(…
30136 #define XCVR_CLR_BBF_RES_TUNE_VAL_7_0(base, value) (BME_AND32(&XCVR_BBF_RES_TUNE_VAL_7_0_REG(base),…
30281 #define XCVR_CLR_BBF_RES_TUNE_VAL_10_8(base, value) (BME_AND32(&XCVR_BBF_RES_TUNE_VAL_10_8_REG(base…
30351 #define XCVR_CLR_TCA_AGC_LIN_VAL_2_0(base, value) (BME_AND32(&XCVR_TCA_AGC_LIN_VAL_2_0_REG(base), (…
30423 #define XCVR_CLR_TCA_AGC_LIN_VAL_5_3(base, value) (BME_AND32(&XCVR_TCA_AGC_LIN_VAL_5_3_REG(base), (…
30496 #define XCVR_CLR_TCA_AGC_LIN_VAL_8_6(base, value) (BME_AND32(&XCVR_TCA_AGC_LIN_VAL_8_6_REG(base), (…
30569 #define XCVR_CLR_BBF_RES_TUNE_LIN_VAL_3_0(base, value) (BME_AND32(&XCVR_BBF_RES_TUNE_LIN_VAL_3_0_RE…
30658 #define XCVR_CLR_BBF_RES_TUNE_LIN_VAL_7_4(base, value) (BME_AND32(&XCVR_BBF_RES_TUNE_LIN_VAL_7_4_RE…
30747 #define XCVR_CLR_BBF_RES_TUNE_LIN_VAL_10_8(base, value) (BME_AND32(&XCVR_BBF_RES_TUNE_LIN_VAL_10_8_…
30820 #define XCVR_CLR_AGC_GAIN_TBL_03_00(base, value) (BME_AND32(&XCVR_AGC_GAIN_TBL_03_00_REG(base), (ui…
30965 #define XCVR_CLR_AGC_GAIN_TBL_07_04(base, value) (BME_AND32(&XCVR_AGC_GAIN_TBL_07_04_REG(base), (ui…
31110 #define XCVR_CLR_AGC_GAIN_TBL_11_08(base, value) (BME_AND32(&XCVR_AGC_GAIN_TBL_11_08_REG(base), (ui…
31255 #define XCVR_CLR_AGC_GAIN_TBL_15_12(base, value) (BME_AND32(&XCVR_AGC_GAIN_TBL_15_12_REG(base), (ui…
31400 #define XCVR_CLR_AGC_GAIN_TBL_19_16(base, value) (BME_AND32(&XCVR_AGC_GAIN_TBL_19_16_REG(base), (ui…
31545 #define XCVR_CLR_AGC_GAIN_TBL_23_20(base, value) (BME_AND32(&XCVR_AGC_GAIN_TBL_23_20_REG(base), (ui…
31690 #define XCVR_CLR_AGC_GAIN_TBL_26_24(base, value) (BME_AND32(&XCVR_AGC_GAIN_TBL_26_24_REG(base), (ui…
31805 #define XCVR_CLR_DCOC_OFFSET_(base, index, value) (BME_AND32(&XCVR_DCOC_OFFSET__REG(base, index), (…
31898 #define XCVR_CLR_DCOC_TZA_STEP_(base, index, value) (BME_AND32(&XCVR_DCOC_TZA_STEP__REG(base, index…
32099 #define XCVR_CLR_DCOC_CAL_IIR(base, value) (BME_AND32(&XCVR_DCOC_CAL_IIR_REG(base), (uint32_t)(~(va…
32234 #define XCVR_CLR_RX_CHF_COEF(base, index, value) (BME_AND32(&XCVR_RX_CHF_COEF_REG(base, index), (ui…
32274 #define XCVR_CLR_TX_DIG_CTRL(base, value) (BME_AND32(&XCVR_TX_DIG_CTRL_REG(base), (uint32_t)(~(valu…
32517 #define XCVR_CLR_TX_DATA_PAD_PAT(base, value) (BME_AND32(&XCVR_TX_DATA_PAD_PAT_REG(base), (uint32_t…
32604 #define XCVR_CLR_TX_GFSK_MOD_CTRL(base, value) (BME_AND32(&XCVR_TX_GFSK_MOD_CTRL_REG(base), (uint32…
32739 #define XCVR_CLR_TX_GFSK_COEFF2(base, value) (BME_AND32(&XCVR_TX_GFSK_COEFF2_REG(base), (uint32_t)(…
32765 #define XCVR_CLR_TX_GFSK_COEFF1(base, value) (BME_AND32(&XCVR_TX_GFSK_COEFF1_REG(base), (uint32_t)(…
32786 #define XCVR_CLR_TX_FSK_MOD_SCALE(base, value) (BME_AND32(&XCVR_TX_FSK_MOD_SCALE_REG(base), (uint32…
32857 #define XCVR_CLR_TX_DFT_MOD_PAT(base, value) (BME_AND32(&XCVR_TX_DFT_MOD_PAT_REG(base), (uint32_t)(…
32883 #define XCVR_CLR_TX_DFT_TONE_0_1(base, value) (BME_AND32(&XCVR_TX_DFT_TONE_0_1_REG(base), (uint32_t…
32951 #define XCVR_CLR_TX_DFT_TONE_2_3(base, value) (BME_AND32(&XCVR_TX_DFT_TONE_2_3_REG(base), (uint32_t…
33014 #define XCVR_CLR_PLL_MOD_OVRD(base, value) (BME_AND32(&XCVR_PLL_MOD_OVRD_REG(base), (uint32_t)(~(va…
33136 #define XCVR_CLR_PLL_CHAN_MAP(base, value) (BME_AND32(&XCVR_PLL_CHAN_MAP_REG(base), (uint32_t)(~(va…
33263 #define XCVR_CLR_PLL_LOCK_DETECT(base, value) (BME_AND32(&XCVR_PLL_LOCK_DETECT_REG(base), (uint32_t…
33482 #define XCVR_CLR_PLL_HP_MOD_CTRL(base, value) (BME_AND32(&XCVR_PLL_HP_MOD_CTRL_REG(base), (uint32_t…
33670 #define XCVR_CLR_PLL_HPM_CAL_CTRL(base, value) (BME_AND32(&XCVR_PLL_HPM_CAL_CTRL_REG(base), (uint32…
33778 #define XCVR_CLR_PLL_LD_HPM_CAL1(base, value) (BME_AND32(&XCVR_PLL_LD_HPM_CAL1_REG(base), (uint32_t…
33882 #define XCVR_CLR_PLL_LD_HPM_CAL2(base, value) (BME_AND32(&XCVR_PLL_LD_HPM_CAL2_REG(base), (uint32_t…
33951 #define XCVR_CLR_PLL_HPM_SDM_FRACTION(base, value) (BME_AND32(&XCVR_PLL_HPM_SDM_FRACTION_REG(base),…
34009 #define XCVR_CLR_PLL_LP_MOD_CTRL(base, value) (BME_AND32(&XCVR_PLL_LP_MOD_CTRL_REG(base), (uint32_t…
34224 #define XCVR_CLR_PLL_LP_SDM_CTRL1(base, value) (BME_AND32(&XCVR_PLL_LP_SDM_CTRL1_REG(base), (uint32…
34297 #define XCVR_CLR_PLL_LP_SDM_CTRL2(base, value) (BME_AND32(&XCVR_PLL_LP_SDM_CTRL2_REG(base), (uint32…
34340 #define XCVR_CLR_PLL_LP_SDM_CTRL3(base, value) (BME_AND32(&XCVR_PLL_LP_SDM_CTRL3_REG(base), (uint32…
34452 #define XCVR_CLR_PLL_DELAY_MATCH(base, value) (BME_AND32(&XCVR_PLL_DELAY_MATCH_REG(base), (uint32_t…
34528 #define XCVR_CLR_PLL_CTUNE_CTRL(base, value) (BME_AND32(&XCVR_PLL_CTUNE_CTRL_REG(base), (uint32_t)(…
34848 #define XCVR_CLR_CTRL(base, value) (BME_AND32(&XCVR_CTRL_REG(base), (uint32_t)(~(value))))
35090 #define XCVR_CLR_OVERWRITE_VER(base, value) (BME_AND32(&XCVR_OVERWRITE_VER_REG(base), (uint32_t)(~(…
35137 #define XCVR_CLR_DMA_CTRL(base, value) (BME_AND32(&XCVR_DMA_CTRL_REG(base), (uint32_t)(~(value))))
35267 #define XCVR_CLR_DTEST_CTRL(base, value) (BME_AND32(&XCVR_DTEST_CTRL_REG(base), (uint32_t)(~(value)…
35491 #define XCVR_CLR_PB_CTRL(base, value) (BME_AND32(&XCVR_PB_CTRL_REG(base), (uint32_t)(~(value))))
35536 #define XCVR_CLR_TSM_CTRL(base, value) (BME_AND32(&XCVR_TSM_CTRL_REG(base), (uint32_t)(~(value))))
35747 #define XCVR_CLR_END_OF_SEQ(base, value) (BME_AND32(&XCVR_END_OF_SEQ_REG(base), (uint32_t)(~(value)…
35846 #define XCVR_CLR_TSM_OVRD0(base, value) (BME_AND32(&XCVR_TSM_OVRD0_REG(base), (uint32_t)(~(value))))
36422 #define XCVR_CLR_TSM_OVRD1(base, value) (BME_AND32(&XCVR_TSM_OVRD1_REG(base), (uint32_t)(~(value))))
36986 #define XCVR_CLR_TSM_OVRD2(base, value) (BME_AND32(&XCVR_TSM_OVRD2_REG(base), (uint32_t)(~(value))))
37549 #define XCVR_CLR_TSM_OVRD3(base, value) (BME_AND32(&XCVR_TSM_OVRD3_REG(base), (uint32_t)(~(value))))
37779 #define XCVR_CLR_PA_POWER(base, value) (BME_AND32(&XCVR_PA_POWER_REG(base), (uint32_t)(~(value))))
37819 #define XCVR_CLR_PA_BIAS_TBL0(base, value) (BME_AND32(&XCVR_PA_BIAS_TBL0_REG(base), (uint32_t)(~(va…
37922 #define XCVR_CLR_PA_BIAS_TBL1(base, value) (BME_AND32(&XCVR_PA_BIAS_TBL1_REG(base), (uint32_t)(~(va…
38023 #define XCVR_CLR_RECYCLE_COUNT(base, value) (BME_AND32(&XCVR_RECYCLE_COUNT_REG(base), (uint32_t)(~(…
38104 #define XCVR_CLR_TSM_TIMING00(base, value) (BME_AND32(&XCVR_TSM_TIMING00_REG(base), (uint32_t)(~(va…
38197 #define XCVR_CLR_TSM_TIMING01(base, value) (BME_AND32(&XCVR_TSM_TIMING01_REG(base), (uint32_t)(~(va…
38290 #define XCVR_CLR_TSM_TIMING02(base, value) (BME_AND32(&XCVR_TSM_TIMING02_REG(base), (uint32_t)(~(va…
38383 #define XCVR_CLR_TSM_TIMING03(base, value) (BME_AND32(&XCVR_TSM_TIMING03_REG(base), (uint32_t)(~(va…
38476 #define XCVR_CLR_TSM_TIMING04(base, value) (BME_AND32(&XCVR_TSM_TIMING04_REG(base), (uint32_t)(~(va…
38537 #define XCVR_CLR_TSM_TIMING05(base, value) (BME_AND32(&XCVR_TSM_TIMING05_REG(base), (uint32_t)(~(va…
38630 #define XCVR_CLR_TSM_TIMING06(base, value) (BME_AND32(&XCVR_TSM_TIMING06_REG(base), (uint32_t)(~(va…
38691 #define XCVR_CLR_TSM_TIMING07(base, value) (BME_AND32(&XCVR_TSM_TIMING07_REG(base), (uint32_t)(~(va…
38788 #define XCVR_CLR_TSM_TIMING08(base, value) (BME_AND32(&XCVR_TSM_TIMING08_REG(base), (uint32_t)(~(va…
38885 #define XCVR_CLR_TSM_TIMING09(base, value) (BME_AND32(&XCVR_TSM_TIMING09_REG(base), (uint32_t)(~(va…
38978 #define XCVR_CLR_TSM_TIMING10(base, value) (BME_AND32(&XCVR_TSM_TIMING10_REG(base), (uint32_t)(~(va…
39039 #define XCVR_CLR_TSM_TIMING11(base, value) (BME_AND32(&XCVR_TSM_TIMING11_REG(base), (uint32_t)(~(va…
39100 #define XCVR_CLR_TSM_TIMING12(base, value) (BME_AND32(&XCVR_TSM_TIMING12_REG(base), (uint32_t)(~(va…
39161 #define XCVR_CLR_TSM_TIMING13(base, value) (BME_AND32(&XCVR_TSM_TIMING13_REG(base), (uint32_t)(~(va…
39254 #define XCVR_CLR_TSM_TIMING14(base, value) (BME_AND32(&XCVR_TSM_TIMING14_REG(base), (uint32_t)(~(va…
39317 #define XCVR_CLR_TSM_TIMING15(base, value) (BME_AND32(&XCVR_TSM_TIMING15_REG(base), (uint32_t)(~(va…
39380 #define XCVR_CLR_TSM_TIMING16(base, value) (BME_AND32(&XCVR_TSM_TIMING16_REG(base), (uint32_t)(~(va…
39477 #define XCVR_CLR_TSM_TIMING17(base, value) (BME_AND32(&XCVR_TSM_TIMING17_REG(base), (uint32_t)(~(va…
39570 #define XCVR_CLR_TSM_TIMING18(base, value) (BME_AND32(&XCVR_TSM_TIMING18_REG(base), (uint32_t)(~(va…
39631 #define XCVR_CLR_TSM_TIMING19(base, value) (BME_AND32(&XCVR_TSM_TIMING19_REG(base), (uint32_t)(~(va…
39692 #define XCVR_CLR_TSM_TIMING20(base, value) (BME_AND32(&XCVR_TSM_TIMING20_REG(base), (uint32_t)(~(va…
39753 #define XCVR_CLR_TSM_TIMING21(base, value) (BME_AND32(&XCVR_TSM_TIMING21_REG(base), (uint32_t)(~(va…
39814 #define XCVR_CLR_TSM_TIMING22(base, value) (BME_AND32(&XCVR_TSM_TIMING22_REG(base), (uint32_t)(~(va…
39875 #define XCVR_CLR_TSM_TIMING23(base, value) (BME_AND32(&XCVR_TSM_TIMING23_REG(base), (uint32_t)(~(va…
39936 #define XCVR_CLR_TSM_TIMING24(base, value) (BME_AND32(&XCVR_TSM_TIMING24_REG(base), (uint32_t)(~(va…
39997 #define XCVR_CLR_TSM_TIMING25(base, value) (BME_AND32(&XCVR_TSM_TIMING25_REG(base), (uint32_t)(~(va…
40058 #define XCVR_CLR_TSM_TIMING26(base, value) (BME_AND32(&XCVR_TSM_TIMING26_REG(base), (uint32_t)(~(va…
40151 #define XCVR_CLR_TSM_TIMING27(base, value) (BME_AND32(&XCVR_TSM_TIMING27_REG(base), (uint32_t)(~(va…
40212 #define XCVR_CLR_TSM_TIMING28(base, value) (BME_AND32(&XCVR_TSM_TIMING28_REG(base), (uint32_t)(~(va…
40273 #define XCVR_CLR_TSM_TIMING29(base, value) (BME_AND32(&XCVR_TSM_TIMING29_REG(base), (uint32_t)(~(va…
40334 #define XCVR_CLR_TSM_TIMING30(base, value) (BME_AND32(&XCVR_TSM_TIMING30_REG(base), (uint32_t)(~(va…
40427 #define XCVR_CLR_TSM_TIMING31(base, value) (BME_AND32(&XCVR_TSM_TIMING31_REG(base), (uint32_t)(~(va…
40488 #define XCVR_CLR_TSM_TIMING32(base, value) (BME_AND32(&XCVR_TSM_TIMING32_REG(base), (uint32_t)(~(va…
40549 #define XCVR_CLR_TSM_TIMING33(base, value) (BME_AND32(&XCVR_TSM_TIMING33_REG(base), (uint32_t)(~(va…
40610 #define XCVR_CLR_TSM_TIMING34(base, value) (BME_AND32(&XCVR_TSM_TIMING34_REG(base), (uint32_t)(~(va…
40703 #define XCVR_CLR_TSM_TIMING35(base, value) (BME_AND32(&XCVR_TSM_TIMING35_REG(base), (uint32_t)(~(va…
40796 #define XCVR_CLR_TSM_TIMING36(base, value) (BME_AND32(&XCVR_TSM_TIMING36_REG(base), (uint32_t)(~(va…
40889 #define XCVR_CLR_TSM_TIMING37(base, value) (BME_AND32(&XCVR_TSM_TIMING37_REG(base), (uint32_t)(~(va…
40982 #define XCVR_CLR_TSM_TIMING38(base, value) (BME_AND32(&XCVR_TSM_TIMING38_REG(base), (uint32_t)(~(va…
41075 #define XCVR_CLR_TSM_TIMING39(base, value) (BME_AND32(&XCVR_TSM_TIMING39_REG(base), (uint32_t)(~(va…
41168 #define XCVR_CLR_TSM_TIMING40(base, value) (BME_AND32(&XCVR_TSM_TIMING40_REG(base), (uint32_t)(~(va…
41261 #define XCVR_CLR_TSM_TIMING41(base, value) (BME_AND32(&XCVR_TSM_TIMING41_REG(base), (uint32_t)(~(va…
41354 #define XCVR_CLR_TSM_TIMING42(base, value) (BME_AND32(&XCVR_TSM_TIMING42_REG(base), (uint32_t)(~(va…
41447 #define XCVR_CLR_TSM_TIMING43(base, value) (BME_AND32(&XCVR_TSM_TIMING43_REG(base), (uint32_t)(~(va…
41536 #define XCVR_CLR_CORR_CTRL(base, value) (BME_AND32(&XCVR_CORR_CTRL_REG(base), (uint32_t)(~(value))))
41633 #define XCVR_CLR_PN_TYPE(base, value) (BME_AND32(&XCVR_PN_TYPE_REG(base), (uint32_t)(~(value))))
41690 #define XCVR_CLR_PN_CODE(base, value) (BME_AND32(&XCVR_PN_CODE_REG(base), (uint32_t)(~(value))))
41745 #define XCVR_CLR_SYNC_CTRL(base, value) (BME_AND32(&XCVR_SYNC_CTRL_REG(base), (uint32_t)(~(value))))
41805 #define XCVR_CLR_SNF_THR(base, value) (BME_AND32(&XCVR_SNF_THR_REG(base), (uint32_t)(~(value))))
41847 #define XCVR_CLR_FAD_THR(base, value) (BME_AND32(&XCVR_FAD_THR_REG(base), (uint32_t)(~(value))))
41887 #define XCVR_CLR_ZBDEM_AFC(base, value) (BME_AND32(&XCVR_ZBDEM_AFC_REG(base), (uint32_t)(~(value))))
41955 #define XCVR_CLR_LPPS_CTRL(base, value) (BME_AND32(&XCVR_LPPS_CTRL_REG(base), (uint32_t)(~(value))))
42132 #define XCVR_CLR_ADC_CTRL(base, value) (BME_AND32(&XCVR_ADC_CTRL_REG(base), (uint32_t)(~(value))))
42240 #define XCVR_CLR_ADC_TUNE(base, value) (BME_AND32(&XCVR_ADC_TUNE_REG(base), (uint32_t)(~(value))))
42329 #define XCVR_CLR_ADC_ADJ(base, value) (BME_AND32(&XCVR_ADC_ADJ_REG(base), (uint32_t)(~(value))))
42448 #define XCVR_CLR_ADC_REGS(base, value) (BME_AND32(&XCVR_ADC_REGS_REG(base), (uint32_t)(~(value))))
42586 #define XCVR_CLR_ADC_TRIMS(base, value) (BME_AND32(&XCVR_ADC_TRIMS_REG(base), (uint32_t)(~(value))))
42661 #define XCVR_CLR_ADC_TEST_CTRL(base, value) (BME_AND32(&XCVR_ADC_TEST_CTRL_REG(base), (uint32_t)(~(…
42781 #define XCVR_CLR_BBF_CTRL(base, value) (BME_AND32(&XCVR_BBF_CTRL_REG(base), (uint32_t)(~(value))))
42942 #define XCVR_CLR_RX_ANA_CTRL(base, value) (BME_AND32(&XCVR_RX_ANA_CTRL_REG(base), (uint32_t)(~(valu…
43022 #define XCVR_CLR_XTAL_CTRL(base, value) (BME_AND32(&XCVR_XTAL_CTRL_REG(base), (uint32_t)(~(value))))
43192 #define XCVR_CLR_XTAL_CTRL2(base, value) (BME_AND32(&XCVR_XTAL_CTRL2_REG(base), (uint32_t)(~(value)…
43396 #define XCVR_CLR_BGAP_CTRL(base, value) (BME_AND32(&XCVR_BGAP_CTRL_REG(base), (uint32_t)(~(value))))
43484 #define XCVR_CLR_PLL_CTRL(base, value) (BME_AND32(&XCVR_PLL_CTRL_REG(base), (uint32_t)(~(value))))
43628 #define XCVR_CLR_PLL_CTRL2(base, value) (BME_AND32(&XCVR_PLL_CTRL2_REG(base), (uint32_t)(~(value))))
43721 #define XCVR_CLR_PLL_TEST_CTRL(base, value) (BME_AND32(&XCVR_PLL_TEST_CTRL_REG(base), (uint32_t)(~(…
43843 #define XCVR_CLR_QGEN_CTRL(base, value) (BME_AND32(&XCVR_QGEN_CTRL_REG(base), (uint32_t)(~(value))))
43922 #define XCVR_CLR_TCA_CTRL(base, value) (BME_AND32(&XCVR_TCA_CTRL_REG(base), (uint32_t)(~(value))))
44031 #define XCVR_CLR_TZA_CTRL(base, value) (BME_AND32(&XCVR_TZA_CTRL_REG(base), (uint32_t)(~(value))))
44134 #define XCVR_CLR_TX_ANA_CTRL(base, value) (BME_AND32(&XCVR_TX_ANA_CTRL_REG(base), (uint32_t)(~(valu…
44175 #define XCVR_CLR_ANA_SPARE(base, value) (BME_AND32(&XCVR_ANA_SPARE_REG(base), (uint32_t)(~(value))))
44325 #define ZLL_CLR_IRQSTS(base, value) (BME_AND32(&ZLL_IRQSTS_REG(base), (uint32_t)(~(value))))
44723 #define ZLL_CLR_PHY_CTRL(base, value) (BME_AND32(&ZLL_PHY_CTRL_REG(base), (uint32_t)(~(value))))
45309 #define ZLL_CLR_T1CMP(base, value) (BME_AND32(&ZLL_T1CMP_REG(base), (uint32_t)(~(value))))
45350 #define ZLL_CLR_T2CMP(base, value) (BME_AND32(&ZLL_T2CMP_REG(base), (uint32_t)(~(value))))
45391 #define ZLL_CLR_T2PRIMECMP(base, value) (BME_AND32(&ZLL_T2PRIMECMP_REG(base), (uint32_t)(~(value))))
45432 #define ZLL_CLR_T3CMP(base, value) (BME_AND32(&ZLL_T3CMP_REG(base), (uint32_t)(~(value))))
45473 #define ZLL_CLR_T4CMP(base, value) (BME_AND32(&ZLL_T4CMP_REG(base), (uint32_t)(~(value))))
45513 #define ZLL_CLR_PA_PWR(base, value) (BME_AND32(&ZLL_PA_PWR_REG(base), (uint32_t)(~(value))))
45555 #define ZLL_CLR_CHANNEL_NUM0(base, value) (BME_AND32(&ZLL_CHANNEL_NUM0_REG(base), (uint32_t)(~(valu…
45648 #define ZLL_CLR_MACSHORTADDRS0(base, value) (BME_AND32(&ZLL_MACSHORTADDRS0_REG(base), (uint32_t)(~(…
45715 #define ZLL_CLR_MACLONGADDRS0_LSB(base, value) (BME_AND32(&ZLL_MACLONGADDRS0_LSB_REG(base), (uint32…
45740 #define ZLL_CLR_MACLONGADDRS0_MSB(base, value) (BME_AND32(&ZLL_MACLONGADDRS0_MSB_REG(base), (uint32…
45761 #define ZLL_CLR_RX_FRAME_FILTER(base, value) (BME_AND32(&ZLL_RX_FRAME_FILTER_REG(base), (uint32_t)(…
45915 #define ZLL_CLR_CCA_LQI_CTRL(base, value) (BME_AND32(&ZLL_CCA_LQI_CTRL_REG(base), (uint32_t)(~(valu…
45991 #define ZLL_CLR_CCA2_CTRL(base, value) (BME_AND32(&ZLL_CCA2_CTRL_REG(base), (uint32_t)(~(value))))
46068 #define ZLL_CLR_FAD_CTRL(base, value) (BME_AND32(&ZLL_FAD_CTRL_REG(base), (uint32_t)(~(value))))
46234 #define ZLL_CLR_SNF_CTRL(base, value) (BME_AND32(&ZLL_SNF_CTRL_REG(base), (uint32_t)(~(value))))
46277 #define ZLL_CLR_BSM_CTRL(base, value) (BME_AND32(&ZLL_BSM_CTRL_REG(base), (uint32_t)(~(value))))
46319 #define ZLL_CLR_MACSHORTADDRS1(base, value) (BME_AND32(&ZLL_MACSHORTADDRS1_REG(base), (uint32_t)(~(…
46386 #define ZLL_CLR_MACLONGADDRS1_LSB(base, value) (BME_AND32(&ZLL_MACLONGADDRS1_LSB_REG(base), (uint32…
46411 #define ZLL_CLR_MACLONGADDRS1_MSB(base, value) (BME_AND32(&ZLL_MACLONGADDRS1_MSB_REG(base), (uint32…
46432 #define ZLL_CLR_DUAL_PAN_CTRL(base, value) (BME_AND32(&ZLL_DUAL_PAN_CTRL_REG(base), (uint32_t)(~(va…
46668 #define ZLL_CLR_CHANNEL_NUM1(base, value) (BME_AND32(&ZLL_CHANNEL_NUM1_REG(base), (uint32_t)(~(valu…
46708 #define ZLL_CLR_SAM_CTRL(base, value) (BME_AND32(&ZLL_SAM_CTRL_REG(base), (uint32_t)(~(value))))
46842 #define ZLL_CLR_SAM_TABLE(base, value) (BME_AND32(&ZLL_SAM_TABLE_REG(base), (uint32_t)(~(value))))
47171 #define ZLL_CLR_SEQ_CTRL_STS(base, value) (BME_AND32(&ZLL_SEQ_CTRL_STS_REG(base), (uint32_t)(~(valu…
47463 #define ZLL_CLR_ACKDELAY(base, value) (BME_AND32(&ZLL_ACKDELAY_REG(base), (uint32_t)(~(value))))
47529 #define ZLL_CLR_FILTERFAIL_CODE(base, value) (BME_AND32(&ZLL_FILTERFAIL_CODE_REG(base), (uint32_t)(…
47600 #define ZLL_CLR_RX_WTR_MARK(base, value) (BME_AND32(&ZLL_RX_WTR_MARK_REG(base), (uint32_t)(~(value)…
47647 #define ZLL_CLR_SLOT_PRELOAD(base, value) (BME_AND32(&ZLL_SLOT_PRELOAD_REG(base), (uint32_t)(~(valu…
47855 #define ZLL_CLR_TMR_PRESCALE(base, value) (BME_AND32(&ZLL_TMR_PRESCALE_REG(base), (uint32_t)(~(valu…
47920 #define ZLL_CLR_LENIENCY_LSB(base, value) (BME_AND32(&ZLL_LENIENCY_LSB_REG(base), (uint32_t)(~(valu…
47955 #define ZLL_CLR_LENIENCY_MSB(base, value) (BME_AND32(&ZLL_LENIENCY_MSB_REG(base), (uint32_t)(~(valu…
48043 #define ZLL_CLR_PKT_BUFFER(base, index, value) (BME_AND32(&ZLL_PKT_BUFFER_REG(base, index), (uint32…