Lines Matching refs:u32NBit
49 static void SwitchNBitOutput(uint32_t u32NBit);
50 static void SwitchNBitInput(uint32_t u32NBit);
53 static void SPIM_WriteStatusRegister(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit);
54 static void SPIM_ReadStatusRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit);
55 static void SPIM_ReadStatusRegister2(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit);
56 static void SPIM_WriteStatusRegister2(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit);
57 static void SPIM_ReadStatusRegister3(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit);
58 static void SPIM_ReadSecurityRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit);
59 static int spim_is_write_done(uint32_t u32NBit);
60 static int spim_wait_write_done(uint32_t u32NBit);
61 static void spim_set_write_enable(int isEn, uint32_t u32NBit);
64 static void SPIM_SPANSION_4Bytes_Enable(int isEn, uint32_t u32NBit);
79 static void SwitchNBitOutput(uint32_t u32NBit) in SwitchNBitOutput() argument
81 switch (u32NBit) in SwitchNBitOutput()
100 static void SwitchNBitInput(uint32_t u32NBit) in SwitchNBitInput() argument
102 switch (u32NBit) in SwitchNBitInput()
271 static void SPIM_ReadStatusRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit) in SPIM_ReadStatusRegister() argument
276 SwitchNBitOutput(u32NBit); in SPIM_ReadStatusRegister()
278 SwitchNBitInput(u32NBit); in SPIM_ReadStatusRegister()
290 static void SPIM_WriteStatusRegister(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit) in SPIM_WriteStatusRegister() argument
296 SwitchNBitOutput(u32NBit); in SPIM_WriteStatusRegister()
308 static void SPIM_ReadStatusRegister2(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit) in SPIM_ReadStatusRegister2() argument
313 SwitchNBitOutput(u32NBit); in SPIM_ReadStatusRegister2()
315 SwitchNBitInput(u32NBit); in SPIM_ReadStatusRegister2()
328 static void SPIM_WriteStatusRegister2(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit) in SPIM_WriteStatusRegister2() argument
336 SwitchNBitOutput(u32NBit); in SPIM_WriteStatusRegister2()
349 static void SPIM_WriteStatusRegister3(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit)
355 SwitchNBitOutput(u32NBit);
368 static void SPIM_ReadStatusRegister3(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit) in SPIM_ReadStatusRegister3() argument
373 SwitchNBitOutput(u32NBit); in SPIM_ReadStatusRegister3()
375 SwitchNBitInput(u32NBit); in SPIM_ReadStatusRegister3()
388 static void SPIM_WriteSecurityRegister(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit)
394 SwitchNBitOutput(u32NBit);
407 static void SPIM_ReadSecurityRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit) in SPIM_ReadSecurityRegister() argument
412 SwitchNBitOutput(u32NBit); in SPIM_ReadSecurityRegister()
414 SwitchNBitInput(u32NBit); in SPIM_ReadSecurityRegister()
423 static int spim_is_write_done(uint32_t u32NBit) in spim_is_write_done() argument
426 SPIM_ReadStatusRegister(status, sizeof (status), u32NBit); in spim_is_write_done()
435 static int spim_wait_write_done(uint32_t u32NBit) in spim_wait_write_done() argument
442 if (spim_is_write_done(u32NBit)) in spim_wait_write_done()
461 static void spim_set_write_enable(int isEn, uint32_t u32NBit) in spim_set_write_enable() argument
467 SwitchNBitOutput(u32NBit); in spim_set_write_enable()
566 void SPIM_ReadJedecId(uint8_t idBuf[], uint32_t u32NRx, uint32_t u32NBit) in SPIM_ReadJedecId() argument
571 SwitchNBitOutput(u32NBit); in SPIM_ReadJedecId()
573 SwitchNBitInput(u32NBit); in SPIM_ReadJedecId()
650 void SPIM_SetQuadEnable(int isEn, uint32_t u32NBit) in SPIM_SetQuadEnable() argument
655 SPIM_ReadJedecId(idBuf, sizeof (idBuf), u32NBit); in SPIM_SetQuadEnable()
662 SPIM_ReadStatusRegister(&dataBuf[0], 1UL, u32NBit); in SPIM_SetQuadEnable()
663 SPIM_ReadStatusRegister2(&dataBuf[1], 1UL, u32NBit); in SPIM_SetQuadEnable()
674 spim_set_write_enable(1, u32NBit); /* Write Enable. */ in SPIM_SetQuadEnable()
675 SPIM_WriteStatusRegister2(dataBuf, sizeof (dataBuf), u32NBit); in SPIM_SetQuadEnable()
676 spim_wait_write_done(u32NBit); in SPIM_SetQuadEnable()
678 SPIM_ReadStatusRegister(&dataBuf[0], 1UL, u32NBit); in SPIM_SetQuadEnable()
679 SPIM_ReadStatusRegister2(&dataBuf[1], 1UL, u32NBit); in SPIM_SetQuadEnable()
686 spim_set_write_enable(1, u32NBit); /* Write Enable. */ in SPIM_SetQuadEnable()
688 SPIM_WriteStatusRegister(dataBuf, sizeof (dataBuf), u32NBit); in SPIM_SetQuadEnable()
689 spim_wait_write_done(u32NBit); in SPIM_SetQuadEnable()
738 static void SPIM_SPANSION_4Bytes_Enable(int isEn, uint32_t u32NBit) in SPIM_SPANSION_4Bytes_Enable() argument
745 SwitchNBitOutput(u32NBit); in SPIM_SPANSION_4Bytes_Enable()
777 int SPIM_Is4ByteModeEnable(uint32_t u32NBit) in SPIM_Is4ByteModeEnable() argument
784 SPIM_ReadJedecId(idBuf, sizeof (idBuf), u32NBit); in SPIM_Is4ByteModeEnable()
808 SPIM_ReadStatusRegister3(dataBuf, sizeof (dataBuf), u32NBit); in SPIM_Is4ByteModeEnable()
814 SPIM_ReadSecurityRegister(dataBuf, sizeof (dataBuf), u32NBit); in SPIM_Is4ByteModeEnable()
832 int SPIM_Enable_4Bytes_Mode(int isEn, uint32_t u32NBit) in SPIM_Enable_4Bytes_Mode() argument
838 SPIM_ReadJedecId(idBuf, sizeof (idBuf), u32NBit); in SPIM_Enable_4Bytes_Mode()
854 SPIM_SPANSION_4Bytes_Enable(isEn, u32NBit); in SPIM_Enable_4Bytes_Mode()
868 SwitchNBitOutput(u32NBit); in SPIM_Enable_4Bytes_Mode()
880 while (! SPIM_Is4ByteModeEnable(u32NBit)) { } in SPIM_Enable_4Bytes_Mode()
884 while (SPIM_Is4ByteModeEnable(u32NBit)) { } in SPIM_Enable_4Bytes_Mode()
893 void SPIM_WinbondUnlock(uint32_t u32NBit) in SPIM_WinbondUnlock() argument
898 SPIM_ReadJedecId(idBuf, sizeof (idBuf), u32NBit); in SPIM_WinbondUnlock()
906 SPIM_ReadStatusRegister(&dataBuf[0], 1UL, u32NBit); in SPIM_WinbondUnlock()
907 SPIM_ReadStatusRegister2(&dataBuf[1], 1UL, u32NBit); in SPIM_WinbondUnlock()
911 spim_set_write_enable(1, u32NBit); /* Write Enable. */ in SPIM_WinbondUnlock()
912 SPIM_WriteStatusRegister2(dataBuf, sizeof (dataBuf), u32NBit); in SPIM_WinbondUnlock()
913 spim_wait_write_done(u32NBit); in SPIM_WinbondUnlock()
915 SPIM_ReadStatusRegister(&dataBuf[0], 1UL, u32NBit); in SPIM_WinbondUnlock()
916 SPIM_ReadStatusRegister2(&dataBuf[1], 1UL, u32NBit); in SPIM_WinbondUnlock()
926 void SPIM_ChipErase(uint32_t u32NBit, int isSync) in SPIM_ChipErase() argument
930 spim_set_write_enable(1, u32NBit); /* Write Enable. */ in SPIM_ChipErase()
933 SwitchNBitOutput(u32NBit); in SPIM_ChipErase()
939 spim_wait_write_done(u32NBit); in SPIM_ChipErase()
953 void SPIM_EraseBlock(uint32_t u32Addr, int is4ByteAddr, uint8_t u8ErsCmd, uint32_t u32NBit, int isS… in SPIM_EraseBlock() argument
958 spim_set_write_enable(1, u32NBit); /* Write Enable. */ in SPIM_EraseBlock()
977 SwitchNBitOutput(u32NBit); in SPIM_EraseBlock()
983 spim_wait_write_done(u32NBit); in SPIM_EraseBlock()