Lines Matching refs:dataBuf
53 static void SPIM_WriteStatusRegister(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit);
54 static void SPIM_ReadStatusRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit);
55 static void SPIM_ReadStatusRegister2(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit);
56 static void SPIM_WriteStatusRegister2(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit);
57 static void SPIM_ReadStatusRegister3(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit);
58 static void SPIM_ReadSecurityRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit);
271 static void SPIM_ReadStatusRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit) in SPIM_ReadStatusRegister() argument
279 spim_read(dataBuf, u32NRx); in SPIM_ReadStatusRegister()
290 static void SPIM_WriteStatusRegister(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit) in SPIM_WriteStatusRegister() argument
294 cmdBuf[1] = dataBuf[0]; in SPIM_WriteStatusRegister()
308 static void SPIM_ReadStatusRegister2(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit) in SPIM_ReadStatusRegister2() argument
316 spim_read(dataBuf, u32NRx); in SPIM_ReadStatusRegister2()
328 static void SPIM_WriteStatusRegister2(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit) in SPIM_WriteStatusRegister2() argument
332 cmdBuf[1] = dataBuf[0]; in SPIM_WriteStatusRegister2()
333 cmdBuf[2] = dataBuf[1]; in SPIM_WriteStatusRegister2()
349 static void SPIM_WriteStatusRegister3(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit)
352 cmdBuf[1] = dataBuf[0];
368 static void SPIM_ReadStatusRegister3(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit) in SPIM_ReadStatusRegister3() argument
376 spim_read(dataBuf, u32NRx); in SPIM_ReadStatusRegister3()
388 static void SPIM_WriteSecurityRegister(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit)
391 cmdBuf[1] = dataBuf[0];
407 static void SPIM_ReadSecurityRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit) in SPIM_ReadSecurityRegister() argument
415 spim_read(dataBuf, u32NRx); in SPIM_ReadSecurityRegister()
534 uint8_t dataBuf[] = {0x00U}; in SPIM_InitFlash() local
537 SPIM_WriteStatusRegister(dataBuf, sizeof (dataBuf), 1U); in SPIM_InitFlash()
583 uint8_t dataBuf[1], status1; in spim_enable_spansion_quad_mode() local
591 spim_read(dataBuf, sizeof (dataBuf)); in spim_enable_spansion_quad_mode()
595 status1 = dataBuf[0]; in spim_enable_spansion_quad_mode()
603 spim_read(dataBuf, sizeof (dataBuf)); in spim_enable_spansion_quad_mode()
614 cmdBuf[2] = dataBuf[0] | 0x2U; /* set QUAD */ in spim_enable_spansion_quad_mode()
618 cmdBuf[2] = dataBuf[0] & ~0x2U; /* clear QUAD */ in spim_enable_spansion_quad_mode()
635 spim_read(dataBuf, sizeof (dataBuf)); in spim_enable_spansion_quad_mode()
653 uint8_t dataBuf[2]; in SPIM_SetQuadEnable() local
662 SPIM_ReadStatusRegister(&dataBuf[0], 1UL, u32NBit); in SPIM_SetQuadEnable()
663 SPIM_ReadStatusRegister2(&dataBuf[1], 1UL, u32NBit); in SPIM_SetQuadEnable()
664 SPIM_DBGMSG("Status Register: 0x%x - 0x%x\n", dataBuf[0], dataBuf[1]); in SPIM_SetQuadEnable()
667 dataBuf[1] |= SR2_QE; in SPIM_SetQuadEnable()
671 dataBuf[1] &= ~SR2_QE; in SPIM_SetQuadEnable()
675 SPIM_WriteStatusRegister2(dataBuf, sizeof (dataBuf), u32NBit); in SPIM_SetQuadEnable()
678 SPIM_ReadStatusRegister(&dataBuf[0], 1UL, u32NBit); in SPIM_SetQuadEnable()
679 SPIM_ReadStatusRegister2(&dataBuf[1], 1UL, u32NBit); in SPIM_SetQuadEnable()
680 SPIM_DBGMSG("Status Register: 0x%x - 0x%x\n", dataBuf[0], dataBuf[1]); in SPIM_SetQuadEnable()
687 dataBuf[0] = isEn ? SR_QE : 0U; in SPIM_SetQuadEnable()
688 SPIM_WriteStatusRegister(dataBuf, sizeof (dataBuf), u32NBit); in SPIM_SetQuadEnable()
741 uint8_t dataBuf[1]; in SPIM_SPANSION_4Bytes_Enable() local
748 spim_read(dataBuf, 1UL); in SPIM_SPANSION_4Bytes_Enable()
751 SPIM_DBGMSG("Bank Address register= 0x%x\n", dataBuf[0]); in SPIM_SPANSION_4Bytes_Enable()
757 cmdBuf[1] = dataBuf[0] | 0x80U; /* set EXTADD */ in SPIM_SPANSION_4Bytes_Enable()
761 cmdBuf[1] = dataBuf[0] & ~0x80U; /* clear EXTADD */ in SPIM_SPANSION_4Bytes_Enable()
782 uint8_t dataBuf[1]; in SPIM_Is4ByteModeEnable() local
808 SPIM_ReadStatusRegister3(dataBuf, sizeof (dataBuf), u32NBit); in SPIM_Is4ByteModeEnable()
809 isEn = !! (dataBuf[0] & SR3_ADR); in SPIM_Is4ByteModeEnable()
814 SPIM_ReadSecurityRegister(dataBuf, sizeof (dataBuf), u32NBit); in SPIM_Is4ByteModeEnable()
815 isEn = !! (dataBuf[0] & SCUR_4BYTE); in SPIM_Is4ByteModeEnable()
896 uint8_t dataBuf[4]; in SPIM_WinbondUnlock() local
906 SPIM_ReadStatusRegister(&dataBuf[0], 1UL, u32NBit); in SPIM_WinbondUnlock()
907 SPIM_ReadStatusRegister2(&dataBuf[1], 1UL, u32NBit); in SPIM_WinbondUnlock()
908 SPIM_DBGMSG("Status Register: 0x%x - 0x%x\n", dataBuf[0], dataBuf[1]); in SPIM_WinbondUnlock()
909 dataBuf[1] &= ~0x40; /* clear Status Register-1 SEC bit */ in SPIM_WinbondUnlock()
912 SPIM_WriteStatusRegister2(dataBuf, sizeof (dataBuf), u32NBit); in SPIM_WinbondUnlock()
915 SPIM_ReadStatusRegister(&dataBuf[0], 1UL, u32NBit); in SPIM_WinbondUnlock()
916 SPIM_ReadStatusRegister2(&dataBuf[1], 1UL, u32NBit); in SPIM_WinbondUnlock()
917 SPIM_DBGMSG("Status Register (after unlock): 0x%x - 0x%x\n", dataBuf[0], dataBuf[1]); in SPIM_WinbondUnlock()