440 …leFaultBrake(EPWM_T *epwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource)  in EPWM_EnableFaultBrake()  argument
448 …       if((u32BrakeSource == EPWM_FB_EDGE_SYS_CSS) || (u32BrakeSource == EPWM_FB_EDGE_SYS_BOD) || \  in EPWM_EnableFaultBrake()
449 …          (u32BrakeSource == EPWM_FB_EDGE_SYS_RAM) || (u32BrakeSource == EPWM_FB_EDGE_SYS_COR) || \  in EPWM_EnableFaultBrake()
450 …        (u32BrakeSource == EPWM_FB_LEVEL_SYS_CSS) || (u32BrakeSource == EPWM_FB_LEVEL_SYS_BOD) || \  in EPWM_EnableFaultBrake()
451 …            (u32BrakeSource == EPWM_FB_LEVEL_SYS_RAM) || (u32BrakeSource == EPWM_FB_LEVEL_SYS_COR))  in EPWM_EnableFaultBrake()
453 …(epwm)->BRKCTL[i >> 1U] |= (u32BrakeSource & (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_BRKCTL0_1_SYSLBEN_…  in EPWM_EnableFaultBrake()
454                 (epwm)->FAILBRK |= (u32BrakeSource & 0xFU);  in EPWM_EnableFaultBrake()
458                 (epwm)->BRKCTL[i >> 1U] |= u32BrakeSource;  in EPWM_EnableFaultBrake()
770 void EPWM_EnableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource)  in EPWM_EnableFaultBrakeInt()  argument
772     (epwm)->INTEN1 |= (0x7UL << u32BrakeSource);  in EPWM_EnableFaultBrakeInt()
786 void EPWM_DisableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource)  in EPWM_DisableFaultBrakeInt()  argument
788     (epwm)->INTEN1 &= ~(0x7UL << u32BrakeSource);  in EPWM_DisableFaultBrakeInt()
801 void EPWM_ClearFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource)  in EPWM_ClearFaultBrakeIntFlag()  argument
803     (epwm)->INTSTS1 = (0x3fUL << u32BrakeSource);  in EPWM_ClearFaultBrakeIntFlag()
817 uint32_t EPWM_GetFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource)  in EPWM_GetFaultBrakeIntFlag()  argument
819     return (((epwm)->INTSTS1 & (0x3fUL << u32BrakeSource)) ? 1UL : 0UL);  in EPWM_GetFaultBrakeIntFlag()