139     uint32_t i;  in EPWM_ConfigOutputChannel()  local
172         i = (u32EPWMClockSrc / u32Frequency) / u32Prescale;  in EPWM_ConfigOutputChannel()
174         if(i < (0x10000U))  in EPWM_ConfigOutputChannel()
176             u32CNR = i;  in EPWM_ConfigOutputChannel()
181     i = u32EPWMClockSrc / (u32Prescale * u32CNR);  in EPWM_ConfigOutputChannel()
199     return(i);  in EPWM_ConfigOutputChannel()
229     uint32_t i;  in EPWM_Stop()  local
230     for(i = 0U; i < EPWM_CHANNEL_NUM; i ++)  in EPWM_Stop()
232         if(u32ChannelMask & (1UL << i))  in EPWM_Stop()
234             (epwm)->PERIOD[i] = 0U;  in EPWM_Stop()
442     uint32_t i;  in EPWM_EnableFaultBrake()  local
444     for(i = 0U; i < EPWM_CHANNEL_NUM; i ++)  in EPWM_EnableFaultBrake()
446         if(u32ChannelMask & (1UL << i))  in EPWM_EnableFaultBrake()
453 …(epwm)->BRKCTL[i >> 1U] |= (u32BrakeSource & (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_BRKCTL0_1_SYSLBEN_…  in EPWM_EnableFaultBrake()
458                 (epwm)->BRKCTL[i >> 1U] |= u32BrakeSource;  in EPWM_EnableFaultBrake()
462         if(u32LevelMask & (1UL << i))  in EPWM_EnableFaultBrake()
464             if((i & 0x1U) == 0U)  in EPWM_EnableFaultBrake()
467                 (epwm)->BRKCTL[i >> 1] &= ~EPWM_BRKCTL0_1_BRKAEVEN_Msk;  in EPWM_EnableFaultBrake()
468                 (epwm)->BRKCTL[i >> 1] |= ((3U) << EPWM_BRKCTL0_1_BRKAEVEN_Pos);  in EPWM_EnableFaultBrake()
473                 (epwm)->BRKCTL[i >> 1] &= ~EPWM_BRKCTL0_1_BRKAODD_Msk;  in EPWM_EnableFaultBrake()
474                 (epwm)->BRKCTL[i >> 1] |= ((3U) << EPWM_BRKCTL0_1_BRKAODD_Pos);  in EPWM_EnableFaultBrake()
479             if((i & 0x1U) == 0U)  in EPWM_EnableFaultBrake()
482                 (epwm)->BRKCTL[i >> 1U] &= ~EPWM_BRKCTL0_1_BRKAEVEN_Msk;  in EPWM_EnableFaultBrake()
483                 (epwm)->BRKCTL[i >> 1U] |= ((2U) << EPWM_BRKCTL0_1_BRKAEVEN_Pos);  in EPWM_EnableFaultBrake()
488                 (epwm)->BRKCTL[i >> 1U] &= ~EPWM_BRKCTL0_1_BRKAODD_Msk;  in EPWM_EnableFaultBrake()
489                 (epwm)->BRKCTL[i >> 1U] |= ((2U) << EPWM_BRKCTL0_1_BRKAODD_Pos);  in EPWM_EnableFaultBrake()
1195     uint32_t i;  in EPWM_EnableSyncPhase()  local
1196     for(i = 0U; i < EPWM_CHANNEL_NUM; i ++)  in EPWM_EnableSyncPhase()
1198         if(u32ChannelMask & (1UL << i))  in EPWM_EnableSyncPhase()
1200             (epwm)->SYNC |= ((1UL << EPWM_SYNC_PHSEN0_Pos) << (i >> 1U));  in EPWM_EnableSyncPhase()
1218     uint32_t i;  in EPWM_DisableSyncPhase()  local
1219     for(i = 0U; i < EPWM_CHANNEL_NUM; i ++)  in EPWM_DisableSyncPhase()
1221         if(u32ChannelMask & (1UL << i))  in EPWM_DisableSyncPhase()
1223             (epwm)->SYNC &= ~((1UL << EPWM_SYNC_PHSEN0_Pos) << (i >> 1U));  in EPWM_DisableSyncPhase()