193     uint32_t reg;  in EMAC_PhyInit()  local
202         reg = EMAC_MdioRead(PHY_CNTL_REG, EMAC_PHY_ADDR) ;  in EMAC_PhyInit()
204         if ((reg & PHY_CNTL_RESET_PHY) == 0UL)  in EMAC_PhyInit()
244         reg = EMAC_MdioRead(PHY_ANLPA_REG, EMAC_PHY_ADDR) ;  in EMAC_PhyInit()
246         if (reg & PHY_ANLPA_DR100_TX_FULL)  in EMAC_PhyInit()
251         else if (reg & PHY_ANLPA_DR100_TX_HALF)  in EMAC_PhyInit()
256         else if (reg & PHY_ANLPA_DR10_TX_FULL)  in EMAC_PhyInit()
447     uint32_t reg;  in EMAC_EnableCamEntry()  local
455     reg = (uint32_t)&EMAC->CAM0M + u32Entry * 2UL * 4UL;  in EMAC_EnableCamEntry()
456     *(uint32_t volatile *)reg = u32Msw;  in EMAC_EnableCamEntry()
457     reg = (uint32_t)&EMAC->CAM0L + u32Entry * 2UL * 4UL;  in EMAC_EnableCamEntry()
458     *(uint32_t volatile *)reg = u32Lsw;  in EMAC_EnableCamEntry()
486     uint32_t status, reg;  in EMAC_RecvPkt()  local
490     reg = EMAC->INTSTS;  in EMAC_RecvPkt()
491     EMAC->INTSTS = reg & 0xFFFFUL;  /* Clear all RX related interrupt status */  in EMAC_RecvPkt()
493     if (reg & EMAC_INTSTS_RXBEIF_Msk)  in EMAC_RecvPkt()
551     uint32_t status, reg;  in EMAC_RecvPktTS()  local
555     reg = EMAC->INTSTS;  in EMAC_RecvPktTS()
556     EMAC->INTSTS = reg & 0xFFFFUL; /* Clear all Rx related interrupt status */  in EMAC_RecvPktTS()
558     if (reg & EMAC_INTSTS_RXBEIF_Msk)  in EMAC_RecvPktTS()
689     uint32_t status, reg;  in EMAC_SendPktDone()  local
693     reg = EMAC->INTSTS;  in EMAC_SendPktDone()
695     EMAC->INTSTS = reg & (0xFFFF0000UL & ~EMAC_INTSTS_TSALMIF_Msk);  in EMAC_SendPktDone()
698     if (reg & EMAC_INTSTS_TXBEIF_Msk)  in EMAC_SendPktDone()
773     uint32_t status, reg;  in EMAC_SendPktDoneTS()  local
776     reg = EMAC->INTSTS;  in EMAC_SendPktDoneTS()
778     EMAC->INTSTS = reg & (0xFFFF0000UL & ~EMAC_INTSTS_TSALMIF_Msk);  in EMAC_SendPktDoneTS()
781     if (reg & EMAC_INTSTS_TXBEIF_Msk)  in EMAC_SendPktDoneTS()
847     uint32_t reg;  in EMAC_EnableTS()  local
861     EMAC->TSINC = (reg = (uint32_t)f);  in EMAC_EnableTS()
862     f = (double)9223372036854775808.0 / ((double)(CLK_GetHCLKFreq()) * (double)reg);  in EMAC_EnableTS()
967     uint32_t reg, ret = EMAC_LINK_DOWN;  in EMAC_CheckLinkStatus()  local
973         reg = EMAC_MdioRead(PHY_ANLPA_REG, EMAC_PHY_ADDR) ;  in EMAC_CheckLinkStatus()
975         if (reg & PHY_ANLPA_DR100_TX_FULL)  in EMAC_CheckLinkStatus()
981         else if (reg & PHY_ANLPA_DR100_TX_HALF)  in EMAC_CheckLinkStatus()
987         else if (reg & PHY_ANLPA_DR10_TX_FULL)  in EMAC_CheckLinkStatus()