Lines Matching refs:u32NBit
49 static void SwitchNBitOutput(uint32_t u32NBit);
50 static void SwitchNBitInput(uint32_t u32NBit);
53 static void SPIM_WriteStatusRegister(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit);
54 static void SPIM_ReadStatusRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit);
55 static void SPIM_ReadStatusRegister2(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit);
56 static void SPIM_WriteStatusRegister2(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit);
57 static void SPIM_ReadStatusRegister3(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit);
58 static void SPIM_ReadSecurityRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit);
59 static int spim_is_write_done(uint32_t u32NBit);
60 static int spim_wait_write_done(uint32_t u32NBit);
61 static void spim_set_write_enable(int isEn, uint32_t u32NBit);
64 static void SPIM_SPANSION_4Bytes_Enable(int isEn, uint32_t u32NBit);
79 static void SwitchNBitOutput(uint32_t u32NBit) in SwitchNBitOutput() argument
81 switch (u32NBit) in SwitchNBitOutput()
100 static void SwitchNBitInput(uint32_t u32NBit) in SwitchNBitInput() argument
102 switch (u32NBit) in SwitchNBitInput()
297 static void SPIM_ReadStatusRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit) in SPIM_ReadStatusRegister() argument
302 SwitchNBitOutput(u32NBit); in SPIM_ReadStatusRegister()
304 SwitchNBitInput(u32NBit); in SPIM_ReadStatusRegister()
316 static void SPIM_WriteStatusRegister(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit) in SPIM_WriteStatusRegister() argument
322 SwitchNBitOutput(u32NBit); in SPIM_WriteStatusRegister()
334 static void SPIM_ReadStatusRegister2(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit) in SPIM_ReadStatusRegister2() argument
339 SwitchNBitOutput(u32NBit); in SPIM_ReadStatusRegister2()
341 SwitchNBitInput(u32NBit); in SPIM_ReadStatusRegister2()
354 static void SPIM_WriteStatusRegister2(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit) in SPIM_WriteStatusRegister2() argument
362 SwitchNBitOutput(u32NBit); in SPIM_WriteStatusRegister2()
375 static void SPIM_WriteStatusRegister3(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit)
381 SwitchNBitOutput(u32NBit);
394 static void SPIM_ReadStatusRegister3(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit) in SPIM_ReadStatusRegister3() argument
399 SwitchNBitOutput(u32NBit); in SPIM_ReadStatusRegister3()
401 SwitchNBitInput(u32NBit); in SPIM_ReadStatusRegister3()
414 static void SPIM_WriteSecurityRegister(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit)
420 SwitchNBitOutput(u32NBit);
433 static void SPIM_ReadSecurityRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit) in SPIM_ReadSecurityRegister() argument
438 SwitchNBitOutput(u32NBit); in SPIM_ReadSecurityRegister()
440 SwitchNBitInput(u32NBit); in SPIM_ReadSecurityRegister()
449 static int spim_is_write_done(uint32_t u32NBit) in spim_is_write_done() argument
452 SPIM_ReadStatusRegister(status, sizeof (status), u32NBit); in spim_is_write_done()
461 static int spim_wait_write_done(uint32_t u32NBit) in spim_wait_write_done() argument
468 if (spim_is_write_done(u32NBit)) in spim_wait_write_done()
487 static void spim_set_write_enable(int isEn, uint32_t u32NBit) in spim_set_write_enable() argument
493 SwitchNBitOutput(u32NBit); in spim_set_write_enable()
592 void SPIM_ReadJedecId(uint8_t idBuf[], uint32_t u32NRx, uint32_t u32NBit) in SPIM_ReadJedecId() argument
597 SwitchNBitOutput(u32NBit); in SPIM_ReadJedecId()
599 SwitchNBitInput(u32NBit); in SPIM_ReadJedecId()
676 void SPIM_SetQuadEnable(int isEn, uint32_t u32NBit) in SPIM_SetQuadEnable() argument
681 SPIM_ReadJedecId(idBuf, sizeof (idBuf), u32NBit); in SPIM_SetQuadEnable()
688 SPIM_ReadStatusRegister(&dataBuf[0], 1UL, u32NBit); in SPIM_SetQuadEnable()
689 SPIM_ReadStatusRegister2(&dataBuf[1], 1UL, u32NBit); in SPIM_SetQuadEnable()
700 spim_set_write_enable(1, u32NBit); /* Write Enable. */ in SPIM_SetQuadEnable()
701 SPIM_WriteStatusRegister2(dataBuf, sizeof (dataBuf), u32NBit); in SPIM_SetQuadEnable()
702 spim_wait_write_done(u32NBit); in SPIM_SetQuadEnable()
704 SPIM_ReadStatusRegister(&dataBuf[0], 1UL, u32NBit); in SPIM_SetQuadEnable()
705 SPIM_ReadStatusRegister2(&dataBuf[1], 1UL, u32NBit); in SPIM_SetQuadEnable()
712 spim_set_write_enable(1, u32NBit); /* Write Enable. */ in SPIM_SetQuadEnable()
714 SPIM_WriteStatusRegister(dataBuf, sizeof (dataBuf), u32NBit); in SPIM_SetQuadEnable()
715 spim_wait_write_done(u32NBit); in SPIM_SetQuadEnable()
764 static void SPIM_SPANSION_4Bytes_Enable(int isEn, uint32_t u32NBit) in SPIM_SPANSION_4Bytes_Enable() argument
771 SwitchNBitOutput(u32NBit); in SPIM_SPANSION_4Bytes_Enable()
803 int SPIM_Is4ByteModeEnable(uint32_t u32NBit) in SPIM_Is4ByteModeEnable() argument
810 SPIM_ReadJedecId(idBuf, sizeof (idBuf), u32NBit); in SPIM_Is4ByteModeEnable()
834 SPIM_ReadStatusRegister3(dataBuf, sizeof (dataBuf), u32NBit); in SPIM_Is4ByteModeEnable()
840 SPIM_ReadSecurityRegister(dataBuf, sizeof (dataBuf), u32NBit); in SPIM_Is4ByteModeEnable()
858 int SPIM_Enable_4Bytes_Mode(int isEn, uint32_t u32NBit) in SPIM_Enable_4Bytes_Mode() argument
865 SPIM_ReadJedecId(idBuf, sizeof (idBuf), u32NBit); in SPIM_Enable_4Bytes_Mode()
883 SPIM_SPANSION_4Bytes_Enable(isEn, u32NBit); in SPIM_Enable_4Bytes_Mode()
897 SwitchNBitOutput(u32NBit); in SPIM_Enable_4Bytes_Mode()
916 while ((i32TimeOutCount-- > 0) && !SPIM_Is4ByteModeEnable(u32NBit)) { } in SPIM_Enable_4Bytes_Mode()
920 while ((i32TimeOutCount-- > 0) && SPIM_Is4ByteModeEnable(u32NBit)) { } in SPIM_Enable_4Bytes_Mode()
930 void SPIM_WinbondUnlock(uint32_t u32NBit) in SPIM_WinbondUnlock() argument
935 SPIM_ReadJedecId(idBuf, sizeof (idBuf), u32NBit); in SPIM_WinbondUnlock()
943 SPIM_ReadStatusRegister(&dataBuf[0], 1UL, u32NBit); in SPIM_WinbondUnlock()
944 SPIM_ReadStatusRegister2(&dataBuf[1], 1UL, u32NBit); in SPIM_WinbondUnlock()
948 spim_set_write_enable(1, u32NBit); /* Write Enable. */ in SPIM_WinbondUnlock()
949 SPIM_WriteStatusRegister2(dataBuf, sizeof (dataBuf), u32NBit); in SPIM_WinbondUnlock()
950 spim_wait_write_done(u32NBit); in SPIM_WinbondUnlock()
952 SPIM_ReadStatusRegister(&dataBuf[0], 1UL, u32NBit); in SPIM_WinbondUnlock()
953 SPIM_ReadStatusRegister2(&dataBuf[1], 1UL, u32NBit); in SPIM_WinbondUnlock()
963 void SPIM_ChipErase(uint32_t u32NBit, int isSync) in SPIM_ChipErase() argument
967 spim_set_write_enable(1, u32NBit); /* Write Enable. */ in SPIM_ChipErase()
970 SwitchNBitOutput(u32NBit); in SPIM_ChipErase()
976 spim_wait_write_done(u32NBit); in SPIM_ChipErase()
990 void SPIM_EraseBlock(uint32_t u32Addr, int is4ByteAddr, uint8_t u8ErsCmd, uint32_t u32NBit, int isS… in SPIM_EraseBlock() argument
995 spim_set_write_enable(1, u32NBit); /* Write Enable. */ in SPIM_EraseBlock()
1014 SwitchNBitOutput(u32NBit); in SPIM_EraseBlock()
1020 spim_wait_write_done(u32NBit); in SPIM_EraseBlock()