Lines Matching refs:dataBuf
53 static void SPIM_WriteStatusRegister(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit);
54 static void SPIM_ReadStatusRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit);
55 static void SPIM_ReadStatusRegister2(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit);
56 static void SPIM_WriteStatusRegister2(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit);
57 static void SPIM_ReadStatusRegister3(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit);
58 static void SPIM_ReadSecurityRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit);
297 static void SPIM_ReadStatusRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit) in SPIM_ReadStatusRegister() argument
305 spim_read(dataBuf, u32NRx); in SPIM_ReadStatusRegister()
316 static void SPIM_WriteStatusRegister(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit) in SPIM_WriteStatusRegister() argument
320 cmdBuf[1] = dataBuf[0]; in SPIM_WriteStatusRegister()
334 static void SPIM_ReadStatusRegister2(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit) in SPIM_ReadStatusRegister2() argument
342 spim_read(dataBuf, u32NRx); in SPIM_ReadStatusRegister2()
354 static void SPIM_WriteStatusRegister2(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit) in SPIM_WriteStatusRegister2() argument
358 cmdBuf[1] = dataBuf[0]; in SPIM_WriteStatusRegister2()
359 cmdBuf[2] = dataBuf[1]; in SPIM_WriteStatusRegister2()
375 static void SPIM_WriteStatusRegister3(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit)
378 cmdBuf[1] = dataBuf[0];
394 static void SPIM_ReadStatusRegister3(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit) in SPIM_ReadStatusRegister3() argument
402 spim_read(dataBuf, u32NRx); in SPIM_ReadStatusRegister3()
414 static void SPIM_WriteSecurityRegister(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit)
417 cmdBuf[1] = dataBuf[0];
433 static void SPIM_ReadSecurityRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit) in SPIM_ReadSecurityRegister() argument
441 spim_read(dataBuf, u32NRx); in SPIM_ReadSecurityRegister()
560 uint8_t dataBuf[] = {0x00U}; in SPIM_InitFlash() local
563 SPIM_WriteStatusRegister(dataBuf, sizeof (dataBuf), 1U); in SPIM_InitFlash()
609 uint8_t dataBuf[1], status1; in spim_enable_spansion_quad_mode() local
617 spim_read(dataBuf, sizeof (dataBuf)); in spim_enable_spansion_quad_mode()
621 status1 = dataBuf[0]; in spim_enable_spansion_quad_mode()
629 spim_read(dataBuf, sizeof (dataBuf)); in spim_enable_spansion_quad_mode()
640 cmdBuf[2] = dataBuf[0] | 0x2U; /* set QUAD */ in spim_enable_spansion_quad_mode()
644 cmdBuf[2] = dataBuf[0] & ~0x2U; /* clear QUAD */ in spim_enable_spansion_quad_mode()
661 spim_read(dataBuf, sizeof (dataBuf)); in spim_enable_spansion_quad_mode()
679 uint8_t dataBuf[2]; in SPIM_SetQuadEnable() local
688 SPIM_ReadStatusRegister(&dataBuf[0], 1UL, u32NBit); in SPIM_SetQuadEnable()
689 SPIM_ReadStatusRegister2(&dataBuf[1], 1UL, u32NBit); in SPIM_SetQuadEnable()
690 SPIM_DBGMSG("Status Register: 0x%x - 0x%x\n", dataBuf[0], dataBuf[1]); in SPIM_SetQuadEnable()
693 dataBuf[1] |= SR2_QE; in SPIM_SetQuadEnable()
697 dataBuf[1] &= ~SR2_QE; in SPIM_SetQuadEnable()
701 SPIM_WriteStatusRegister2(dataBuf, sizeof (dataBuf), u32NBit); in SPIM_SetQuadEnable()
704 SPIM_ReadStatusRegister(&dataBuf[0], 1UL, u32NBit); in SPIM_SetQuadEnable()
705 SPIM_ReadStatusRegister2(&dataBuf[1], 1UL, u32NBit); in SPIM_SetQuadEnable()
706 SPIM_DBGMSG("Status Register: 0x%x - 0x%x\n", dataBuf[0], dataBuf[1]); in SPIM_SetQuadEnable()
713 dataBuf[0] = isEn ? SR_QE : 0U; in SPIM_SetQuadEnable()
714 SPIM_WriteStatusRegister(dataBuf, sizeof (dataBuf), u32NBit); in SPIM_SetQuadEnable()
767 uint8_t dataBuf[1]; in SPIM_SPANSION_4Bytes_Enable() local
774 spim_read(dataBuf, 1UL); in SPIM_SPANSION_4Bytes_Enable()
777 SPIM_DBGMSG("Bank Address register= 0x%x\n", dataBuf[0]); in SPIM_SPANSION_4Bytes_Enable()
783 cmdBuf[1] = dataBuf[0] | 0x80U; /* set EXTADD */ in SPIM_SPANSION_4Bytes_Enable()
787 cmdBuf[1] = dataBuf[0] & ~0x80U; /* clear EXTADD */ in SPIM_SPANSION_4Bytes_Enable()
808 uint8_t dataBuf[1]; in SPIM_Is4ByteModeEnable() local
834 SPIM_ReadStatusRegister3(dataBuf, sizeof (dataBuf), u32NBit); in SPIM_Is4ByteModeEnable()
835 isEn = !! (dataBuf[0] & SR3_ADR); in SPIM_Is4ByteModeEnable()
840 SPIM_ReadSecurityRegister(dataBuf, sizeof (dataBuf), u32NBit); in SPIM_Is4ByteModeEnable()
841 isEn = !! (dataBuf[0] & SCUR_4BYTE); in SPIM_Is4ByteModeEnable()
933 uint8_t dataBuf[4]; in SPIM_WinbondUnlock() local
943 SPIM_ReadStatusRegister(&dataBuf[0], 1UL, u32NBit); in SPIM_WinbondUnlock()
944 SPIM_ReadStatusRegister2(&dataBuf[1], 1UL, u32NBit); in SPIM_WinbondUnlock()
945 SPIM_DBGMSG("Status Register: 0x%x - 0x%x\n", dataBuf[0], dataBuf[1]); in SPIM_WinbondUnlock()
946 dataBuf[1] &= ~0x40; /* clear Status Register-1 SEC bit */ in SPIM_WinbondUnlock()
949 SPIM_WriteStatusRegister2(dataBuf, sizeof (dataBuf), u32NBit); in SPIM_WinbondUnlock()
952 SPIM_ReadStatusRegister(&dataBuf[0], 1UL, u32NBit); in SPIM_WinbondUnlock()
953 SPIM_ReadStatusRegister2(&dataBuf[1], 1UL, u32NBit); in SPIM_WinbondUnlock()
954 SPIM_DBGMSG("Status Register (after unlock): 0x%x - 0x%x\n", dataBuf[0], dataBuf[1]); in SPIM_WinbondUnlock()