135     uint32_t i;  in EPWM_ConfigOutputChannel()  local
168         i = (u32EPWMClockSrc / u32Frequency) / u32Prescale;  in EPWM_ConfigOutputChannel()
170         if(i < (0x10000U))  in EPWM_ConfigOutputChannel()
172             u32CNR = i;  in EPWM_ConfigOutputChannel()
177     i = u32EPWMClockSrc / (u32Prescale * u32CNR);  in EPWM_ConfigOutputChannel()
194     return(i);  in EPWM_ConfigOutputChannel()
224     uint32_t i;  in EPWM_Stop()  local
225     for(i = 0U; i < EPWM_CHANNEL_NUM; i ++)  in EPWM_Stop()
227         if(u32ChannelMask & (1UL << i))  in EPWM_Stop()
229             (epwm)->PERIOD[i] = 0U;  in EPWM_Stop()
491     uint32_t i;  in EPWM_EnableFaultBrake()  local
493     for(i = 0U; i < EPWM_CHANNEL_NUM; i ++)  in EPWM_EnableFaultBrake()
495         if(u32ChannelMask & (1UL << i))  in EPWM_EnableFaultBrake()
502 …(epwm)->BRKCTL[i >> 1U] |= (u32BrakeSource & (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_BRKCTL0_1_SYSLBEN_…  in EPWM_EnableFaultBrake()
507                 (epwm)->BRKCTL[i >> 1U] |= u32BrakeSource;  in EPWM_EnableFaultBrake()
511         if(u32LevelMask & (1UL << i))  in EPWM_EnableFaultBrake()
513             if((i & 0x1U) == 0U)  in EPWM_EnableFaultBrake()
516                 (epwm)->BRKCTL[i >> 1] &= ~EPWM_BRKCTL0_1_BRKAEVEN_Msk;  in EPWM_EnableFaultBrake()
517                 (epwm)->BRKCTL[i >> 1] |= ((3U) << EPWM_BRKCTL0_1_BRKAEVEN_Pos);  in EPWM_EnableFaultBrake()
522                 (epwm)->BRKCTL[i >> 1] &= ~EPWM_BRKCTL0_1_BRKAODD_Msk;  in EPWM_EnableFaultBrake()
523                 (epwm)->BRKCTL[i >> 1] |= ((3U) << EPWM_BRKCTL0_1_BRKAODD_Pos);  in EPWM_EnableFaultBrake()
528             if((i & 0x1U) == 0U)  in EPWM_EnableFaultBrake()
531                 (epwm)->BRKCTL[i >> 1U] &= ~EPWM_BRKCTL0_1_BRKAEVEN_Msk;  in EPWM_EnableFaultBrake()
532                 (epwm)->BRKCTL[i >> 1U] |= ((2U) << EPWM_BRKCTL0_1_BRKAEVEN_Pos);  in EPWM_EnableFaultBrake()
537                 (epwm)->BRKCTL[i >> 1U] &= ~EPWM_BRKCTL0_1_BRKAODD_Msk;  in EPWM_EnableFaultBrake()
538                 (epwm)->BRKCTL[i >> 1U] |= ((2U) << EPWM_BRKCTL0_1_BRKAODD_Pos);  in EPWM_EnableFaultBrake()
1245     uint32_t i;  in EPWM_EnableSyncPhase()  local
1246     for(i = 0U; i < EPWM_CHANNEL_NUM; i ++)  in EPWM_EnableSyncPhase()
1248         if(u32ChannelMask & (1UL << i))  in EPWM_EnableSyncPhase()
1250             (epwm)->SYNC |= ((1UL << EPWM_SYNC_PHSEN0_Pos) << (i >> 1U));  in EPWM_EnableSyncPhase()
1268     uint32_t i;  in EPWM_DisableSyncPhase()  local
1269     for(i = 0U; i < EPWM_CHANNEL_NUM; i ++)  in EPWM_DisableSyncPhase()
1271         if(u32ChannelMask & (1UL << i))  in EPWM_DisableSyncPhase()
1273             (epwm)->SYNC &= ~((1UL << EPWM_SYNC_PHSEN0_Pos) << (i >> 1U));  in EPWM_DisableSyncPhase()