Lines Matching refs:u32NF
1043 uint32_t u32PllSrcClk, u32NR, u32NF, u32NO, u32PllClk; in CLK_EnablePLL() local
1117 …for(u32NF = 2UL; u32NF <= 513UL; u32NF++) /* NF = 2~513 since NF = FBDIV+2 and FBDIV = 0~511… in CLK_EnablePLL()
1119 … u32Tmp2 = (u32Tmp * u32NF) << 1; /* FVCO = FREF*2*NF */ in CLK_EnablePLL()
1127 u32MinNF = u32NF; in CLK_EnablePLL()
1404 uint32_t u32FIN, u32NF, u32NR, u32NO; in CLK_GetPLLClockFreq() local
1434 u32NF = ((u32PllReg & CLK_PLLCTL_FBDIV_Msk) >> CLK_PLLCTL_FBDIV_Pos) + 2UL; in CLK_GetPLLClockFreq()
1438 u32PllFreq = (((u32FIN >> 2) * (u32NF << 1)) / (u32NR * u32NO) << 2); in CLK_GetPLLClockFreq()
1639 uint32_t u32NR = 0UL, u32NF = 0UL, u32NO, u32X = 0UL; in CLK_EnablePLLFN() local
1702 u32NF = (uint32_t)fNX_X; in CLK_EnablePLLFN()
1704 if((u32NF >= 12) && (u32NF <= 255)) /* Constraint 4: 12<= NF <= 255. */ in CLK_EnablePLLFN()
1706 fX = fNX_X - u32NF; in CLK_EnablePLLFN()
1719 ((u32NF - 2UL) << CLK_PLLFNCTL0_FBDIV_Pos); in CLK_EnablePLLFN()
1723 … u32PllClk = (uint32_t)((float)u32FIN / (((u32NO + 1UL) * u32NR)<<11) * ((u32NF<<12)+u32X)); in CLK_EnablePLLFN()
1754 uint32_t u32FIN, u32NF, u32NR, u32NO, u32X; in CLK_GetPLLFNClockFreq() local
1786 u32NF = ((u32PllReg0 & CLK_PLLFNCTL0_FBDIV_Msk) >> CLK_PLLFNCTL0_FBDIV_Pos) + 2UL; in CLK_GetPLLFNClockFreq()
1790 u32PllFreq = (uint32_t)((float)u32FIN / ((u32NO * u32NR)<<11) * ( ((u32NF<<12)+u32X))); in CLK_GetPLLFNClockFreq()