492 …leFaultBrake(EPWM_T *epwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource)  in EPWM_EnableFaultBrake()  argument
500 …       if((u32BrakeSource == EPWM_FB_EDGE_SYS_CSS) || (u32BrakeSource == EPWM_FB_EDGE_SYS_BOD) || \  in EPWM_EnableFaultBrake()
501 …          (u32BrakeSource == EPWM_FB_EDGE_SYS_RAM) || (u32BrakeSource == EPWM_FB_EDGE_SYS_COR) || \  in EPWM_EnableFaultBrake()
502 …        (u32BrakeSource == EPWM_FB_LEVEL_SYS_CSS) || (u32BrakeSource == EPWM_FB_LEVEL_SYS_BOD) || \  in EPWM_EnableFaultBrake()
503 …            (u32BrakeSource == EPWM_FB_LEVEL_SYS_RAM) || (u32BrakeSource == EPWM_FB_LEVEL_SYS_COR))  in EPWM_EnableFaultBrake()
505 …(epwm)->BRKCTL[i >> 1U] |= (u32BrakeSource & (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_BRKCTL0_1_SYSLBEN_…  in EPWM_EnableFaultBrake()
506                 (epwm)->FAILBRK |= (u32BrakeSource & 0xFU);  in EPWM_EnableFaultBrake()
510                 (epwm)->BRKCTL[i >> 1U] |= u32BrakeSource;  in EPWM_EnableFaultBrake()
822 void EPWM_EnableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource)  in EPWM_EnableFaultBrakeInt()  argument
824     (epwm)->INTEN1 |= (0x7UL << u32BrakeSource);  in EPWM_EnableFaultBrakeInt()
838 void EPWM_DisableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource)  in EPWM_DisableFaultBrakeInt()  argument
840     (epwm)->INTEN1 &= ~(0x7UL << u32BrakeSource);  in EPWM_DisableFaultBrakeInt()
853 void EPWM_ClearFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource)  in EPWM_ClearFaultBrakeIntFlag()  argument
855     (epwm)->INTSTS1 = (0x3fUL << u32BrakeSource);  in EPWM_ClearFaultBrakeIntFlag()
869 uint32_t EPWM_GetFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource)  in EPWM_GetFaultBrakeIntFlag()  argument
871     return (((epwm)->INTSTS1 & (0x3fUL << u32BrakeSource)) ? 1UL : 0UL);  in EPWM_GetFaultBrakeIntFlag()