137     uint32_t i;  in EPWM_ConfigOutputChannel()  local
170         i = (u32EPWMClockSrc / u32Frequency) / u32Prescale;  in EPWM_ConfigOutputChannel()
172         if(i < (0x10000U))  in EPWM_ConfigOutputChannel()
174             u32CNR = i;  in EPWM_ConfigOutputChannel()
179     i = u32EPWMClockSrc / (u32Prescale * u32CNR);  in EPWM_ConfigOutputChannel()
197     return(i);  in EPWM_ConfigOutputChannel()
227     uint32_t i;  in EPWM_Stop()  local
228     for(i = 0U; i < EPWM_CHANNEL_NUM; i ++)  in EPWM_Stop()
230         if(u32ChannelMask & (1UL << i))  in EPWM_Stop()
232             (epwm)->PERIOD[i] = 0U;  in EPWM_Stop()
494     uint32_t i;  in EPWM_EnableFaultBrake()  local
496     for(i = 0U; i < EPWM_CHANNEL_NUM; i ++)  in EPWM_EnableFaultBrake()
498         if(u32ChannelMask & (1UL << i))  in EPWM_EnableFaultBrake()
505 …(epwm)->BRKCTL[i >> 1U] |= (u32BrakeSource & (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_BRKCTL0_1_SYSLBEN_…  in EPWM_EnableFaultBrake()
510                 (epwm)->BRKCTL[i >> 1U] |= u32BrakeSource;  in EPWM_EnableFaultBrake()
514         if(u32LevelMask & (1UL << i))  in EPWM_EnableFaultBrake()
516             if((i & 0x1U) == 0U)  in EPWM_EnableFaultBrake()
519                 (epwm)->BRKCTL[i >> 1] &= ~EPWM_BRKCTL0_1_BRKAEVEN_Msk;  in EPWM_EnableFaultBrake()
520                 (epwm)->BRKCTL[i >> 1] |= ((3U) << EPWM_BRKCTL0_1_BRKAEVEN_Pos);  in EPWM_EnableFaultBrake()
525                 (epwm)->BRKCTL[i >> 1] &= ~EPWM_BRKCTL0_1_BRKAODD_Msk;  in EPWM_EnableFaultBrake()
526                 (epwm)->BRKCTL[i >> 1] |= ((3U) << EPWM_BRKCTL0_1_BRKAODD_Pos);  in EPWM_EnableFaultBrake()
531             if((i & 0x1U) == 0U)  in EPWM_EnableFaultBrake()
534                 (epwm)->BRKCTL[i >> 1U] &= ~EPWM_BRKCTL0_1_BRKAEVEN_Msk;  in EPWM_EnableFaultBrake()
535                 (epwm)->BRKCTL[i >> 1U] |= ((2U) << EPWM_BRKCTL0_1_BRKAEVEN_Pos);  in EPWM_EnableFaultBrake()
540                 (epwm)->BRKCTL[i >> 1U] &= ~EPWM_BRKCTL0_1_BRKAODD_Msk;  in EPWM_EnableFaultBrake()
541                 (epwm)->BRKCTL[i >> 1U] |= ((2U) << EPWM_BRKCTL0_1_BRKAODD_Pos);  in EPWM_EnableFaultBrake()
1247     uint32_t i;  in EPWM_EnableSyncPhase()  local
1248     for(i = 0U; i < EPWM_CHANNEL_NUM; i ++)  in EPWM_EnableSyncPhase()
1250         if(u32ChannelMask & (1UL << i))  in EPWM_EnableSyncPhase()
1252             (epwm)->SYNC |= ((1UL << EPWM_SYNC_PHSEN0_Pos) << (i >> 1U));  in EPWM_EnableSyncPhase()
1270     uint32_t i;  in EPWM_DisableSyncPhase()  local
1271     for(i = 0U; i < EPWM_CHANNEL_NUM; i ++)  in EPWM_DisableSyncPhase()
1273         if(u32ChannelMask & (1UL << i))  in EPWM_DisableSyncPhase()
1275             (epwm)->SYNC &= ~((1UL << EPWM_SYNC_PHSEN0_Pos) << (i >> 1U));  in EPWM_DisableSyncPhase()