Lines Matching full:description
9 …<description>nRF9230_engb reference description for system-on-chip with many ARM 32-bit Cortex-M33…
54 <description>Factory Information Configuration Registers</description>
68 <description>Unspecified</description>
74 <description>Device address type.</description>
82 <description>Device address type.</description>
88 <description>Public address.</description>
93 <description>Random address.</description>
104 <description>Description collection: 48 bit device address.</description>
112 <description>Device address [n].</description>
122 <description>Description collection: Encryption Root.</description>
130 <description>Encryption root word [n].</description>
140 <description>Description collection: Identity Root.</description>
148 <description>Identity root word [n].</description>
157 <description>Device info</description>
163 <description>Configuration identifier</description>
171 <description>Identification number for the HW</description>
179 <description>Part code</description>
187 <description>Part code</description>
193 <description>Unspecified</description>
202 <description>Part Variant, Hardware version and Production configuration</description>
210 …<description>Part Variant, Hardware version and Production configuration, encoded as ASCII</descri…
216 <description>Unspecified</description>
225 <description>Package option</description>
233 <description>Package option</description>
239 <description>Unspecified</description>
248 <description>RAM variant</description>
256 <description>RAM variant</description>
262 <description>Unspecified</description>
271 <description>MRAM variant</description>
279 <description>MRAM variant</description>
285 <description>Unspecified</description>
294 <description>Code memory page size in bytes</description>
302 <description>Code memory page size in bytes</description>
308 <description>Unspecified</description>
317 <description>Code memory size</description>
325 <description>Code memory size in number of pages</description>
331 <description>Unspecified</description>
340 <description>Device type</description>
348 <description>Device type</description>
354 <description>Device is an physical DIE</description>
359 <description>Device is an FPGA</description>
369 <description>SIP-specific device info</description>
375 <description>SIP part number</description>
392 …<description>Description collection: SIP hardware revision, encoded in ASCII, ex B0A or B1A</descr…
410 …<description>Description collection: SIP VARIANT, encoded in ASCII, ex SIAA, SIBA or SICA</descrip…
426 <description>PMIC version</description>
434 <description>PMIC version, incremental code</description>
444 <description>Description collection: Test site, in ascii</description>
453 <description>Lot number + test index in hex format (number digits 0-9).</description>
461 <description>Lot number in hex format</description>
467 <description>Test ID in hex format</description>
477 <description>Description collection: Test program id, in ascii</description>
486 <description>OSAT part number</description>
503 <description>Description collection: OSAT production build version</description>
512 <description>Unspecified</description>
518 <description>Unspecified</description>
524 …<description>LF oscillator configuration. Note. This configuration overrides corresponding LF osci…
532 <description>LF oscillator source.</description>
538 … <description>LF oscillator source is unconfigured. Default will be used.</description>
543 <description>Use LFXO as source for the LF oscillator.</description>
548 <description>Use LFRC as source for the LF oscillator.</description>
553 <description>Use LFLPRC as source for the LF oscillator.</description>
558 <description>Use LF Synth as source for the LF oscillator.</description>
567 …<description>LFXO configuration. Note. This configuration overrides corresponding LFXO configurati…
575 <description>LFXO crystal or external signal accuracy.</description>
581 <description>The accuracy is unconfigured.</description>
586 … <description>LFXO crystal or external signal has an accuracy of 500 ppm.</description>
591 … <description>LFXO crystal or external signal has an accuracy of 250 ppm.</description>
596 … <description>LFXO crystal or external signal has an accuracy of 150 ppm.</description>
601 … <description>LFXO crystal or external signal has an accuracy of 100 ppm.</description>
606 … <description>LFXO crystal or external signal has an accuracy of 75 ppm.</description>
611 … <description>LFXO crystal or external signal has an accuracy of 50 ppm.</description>
616 … <description>LFXO crystal or external signal has an accuracy of 30 ppm.</description>
621 … <description>LFXO crystal or external signal has an accuracy of 20 ppm.</description>
628 … <description>LFXO mode. LFXO will not start unless MODE is configured.</description>
634 <description>The mode is unconfigured.</description>
639 <description>LFXO Pierce mode.</description>
644 <description>LFXO PIXO mode.</description>
649 <description>LFXO in external sine wave mode.</description>
654 <description>LFXO in external square wave mode.</description>
661 … <description>Built-in load capacitors selection in 1 pF steps. Max. value 25 pF.</description>
667 …<description>The built-in load capacitors is unconfigured. LFXO will not start unless LOADCAP is c…
672 …<description>Do not use the built-in load capacitors, only external capacitors will be used.</desc…
679 <description>LFXO startup time in ms.</description>
685 <description>Startup time has not been configured.</description>
694 …description>LFXO calibration needed. Must be written to 0xFFFFFFFF after any modification of the L…
702 …description>LFXO calibration needed. Must be written to 0xFFFFFFFF after any modification of the L…
708 <description>Calibrate the LFXO at startup.</description>
717 …description>LFRC autocalibration configuration. Note. This configuration overrides corresponding L…
725 <description>Temperature measurement interval in 0.25 s steps.</description>
731 …<description>Temperature delta that should trigger a calibration in 0.25 degrees steps.</descripti…
737 …<description>Maximum number of TEMPINTERVAL periods in between calibrations, independent of temper…
743 <description>LFRC.AUTOCALCONFIG register enable.</description>
749 … <description>LFRC.AUTOCALCONFIG register has been configured and can be used.</description>
754 … <description>LFRC.AUTOCALCONFIG register has not been configured and cannot be used.</description>
764 <description>Unspecified</description>
770 …<description>HFXO64M configuration. Note. This configuration overrides corresponding XO configurat…
778 <description>HFXO64M mode.</description>
784 <description>The mode is unconfigured.</description>
789 <description>Normal operating mode.</description>
794 <description>TCXO/bypass mode</description>
799 <description>Reserved value</description>
804 <description>Reserved value</description>
809 <description>Reserved value</description>
814 <description>Reserved value</description>
819 <description>Reserved value</description>
831 <description>Unspecified</description>
837 <description>Unspecified</description>
843 <description>Unspecified</description>
849 <description>Trim value for GLOBAL.SAADC.CALVREF</description>
857 <description>Trim value</description>
867 … <description>Description collection: Trim value for GLOBAL.SAADC.CALGAIN</description>
875 <description>Trim value</description>
883 <description>Trim value for GLOBAL.SAADC.CALOFFSET</description>
891 <description>Trim value</description>
901 … <description>Description collection: Trim value for GLOBAL.SAADC.LINCALCOEFF</description>
909 <description>Trim value</description>
917 <description>Trim value for GLOBAL.SAADC.CALIREF</description>
925 <description>Trim value</description>
933 <description>Trim value for GLOBAL.SAADC.CALVREFTC</description>
941 <description>Trim value</description>
950 <description>Unspecified</description>
956 <description>Unspecified</description>
962 <description>Trim value for GLOBAL.CANPLL.TRIM.CTUNE</description>
970 <description>Trim value</description>
980 <description>Unspecified</description>
986 <description>Trim value for GLOBAL.COMP.REFTRIM</description>
994 <description>Trim value</description>
1004 <description>Unspecified</description>
1010 <description>Unspecified</description>
1016 <description>Unspecified</description>
1022 <description>Trim value for APPLICATION.HSFLL.TRIM.VSUP</description>
1030 <description>Trim value</description>
1040 … <description>Description collection: Trim value for APPLICATION.HSFLL.TRIM.COARSE</description>
1048 <description>Trim value</description>
1058 … <description>Description collection: Trim value for APPLICATION.HSFLL.TRIM.FINE</description>
1066 <description>Trim value</description>
1076 <description>Unspecified</description>
1084 <description>Unspecified</description>
1090 …<description>Description cluster: Trim value for APPLICATION.MEMCONF.BLOCKTYPE[n].TRIM</descriptio…
1098 <description>Trim value</description>
1109 <description>Unspecified</description>
1115 <description>Unspecified</description>
1121 <description>Unspecified</description>
1127 <description>Trim value for RADIOCORE.HSFLL.TRIM.VSUP</description>
1135 <description>Trim value</description>
1145 … <description>Description collection: Trim value for RADIOCORE.HSFLL.TRIM.COARSE</description>
1153 <description>Trim value</description>
1163 … <description>Description collection: Trim value for RADIOCORE.HSFLL.TRIM.FINE</description>
1171 <description>Trim value</description>
1181 <description>Unspecified</description>
1189 <description>Unspecified</description>
1195 … <description>Description cluster: Trim value for RADIOCORE.MEMCONF.BLOCKTYPE[n].TRIM</description>
1203 <description>Trim value</description>
1217 <description>USBHSCORE</description>
1232 <description>Control and Status Register</description>
1240 <description>Mode: Host only. VBUS Valid Override Enable (VbvalidOvEn)</description>
1246 …<description>Override is disabled and bvalid signal from the respective PHY selected is used inter…
1251 …<description>The vbus-valid signal received from the PHY is overridden with GOTGCTL.VbvalidOvVal</…
1258 <description>Mode: Host only. VBUS Valid OverrideValue (VbvalidOvVal)</description>
1264 <description>vbusvalid value when GOTGCTL.VbvalidOvEn = 1</description>
1269 <description>vbusvalid value when GOTGCTL.VbvalidOvEn is 1</description>
1276 …<description>Mode: Host only. A-Peripheral Session Valid Override Enable (AvalidOvEn)</description>
1282 <description>Derive AValid from PHY</description>
1287 <description>Derive Avalid from GOTGCTL.AvalidOvVal</description>
1294 … <description>Mode: Host only. A-Peripheral Session Valid OverrideValue (AvalidOvVal)</description>
1300 <description>Avalid value is 1'b0 when GOTGCTL.AvalidOvEn =1</description>
1305 <description>Avalid value is 1'b1 when GOTGCTL.AvalidOvEn =1</description>
1312 …<description>Mode: Device only. B-Peripheral Session Valid Override Value (BvalidOvEn)</descriptio…
1318 …<description>Override is disabled and bvalid signal from the respective PHY selected is used inter…
1323 …<description>Internally Bvalid received from the PHY is overridden with GOTGCTL.BvalidOvVal</descr…
1330 …<description>Mode: Device only. B-Peripheral Session Valid OverrideValue (BvalidOvVal)</descriptio…
1336 <description>Bvalid value when GOTGCTL.BvalidOvEn =1</description>
1341 <description>Bvalid value when GOTGCTL.BvalidOvEn =1</description>
1348 <description>Mode: Host and Device. Debounce Filter Bypass</description>
1354 <description>Debounce Filter Bypass is disabled.</description>
1359 <description>Debounce Filter Bypass is enabled.</description>
1366 <description>Mode: Host and Device. Connector ID Status (ConIDSts)</description>
1373 <description>The core is in A-Device mode.</description>
1378 <description>The core is in B-Device mode.</description>
1385 <description>Mode: Host only. Long/Short Debounce Time (DbncTime)</description>
1392 …<description>Long debounce time, used for physical connections (100 ms + 2.5 micro-sec)</descripti…
1397 … <description>Short debounce time, used for soft connections (2.5 micro-sec)</description>
1404 <description>Mode: Host only. A-Session Valid (ASesVld)</description>
1411 <description>A-session is not valid.</description>
1416 <description>A-session is valid.</description>
1423 <description>Mode: Device only. B-Session Valid (BSesVld)</description>
1430 <description>B-session is not valid.</description>
1435 <description>B-session is valid.</description>
1442 <description>OTG Version (OTGVer)</description>
1448 <description>Supports OTG Version 1.3</description>
1453 <description>Supports OTG Version 2.0</description>
1460 <description>Current Mode of Operation (CurMod)</description>
1467 <description>Current mode is device mode.</description>
1472 <description>Current mode is host mode.</description>
1479 <description>Mode: Host and Device. Multi Valued ID pin (MultValIdBC)</description>
1486 <description>B-Device connected to ACA. VBUS is on.</description>
1491 <description>B-Device connected to ACA. VBUS is off.</description>
1496 <description>A-Device connected to ACA</description>
1501 <description>A-Device not connected to ACA</description>
1506 <description>B-Device not connected to ACA</description>
1513 …description>Mode: Device Only. This bit when programmed to 1'b1 results in the core asserting chir…
1519 …<description>The controller does not assert chirp_on before sending an actual Chirp 'K' signal on …
1524 …<description>The controller asserts chirp_on before sending an actual Chirp 'K' signal on USB.</de…
1533 <description>Interrupt Register</description>
1541 <description>Mode: Host and Device. Session End Detected (SesEndDet)</description>
1547 <description>Session is Active</description>
1552 <description>SessionEnd utmiotg_bvalid signal is deasserted</description>
1559 …<description>Mode: Host and Device. Session Request Success Status Change (SesReqSucStsChng)</desc…
1565 <description>No Change in Session Request Status</description>
1570 <description>Session Request Status has changed</description>
1577 …<description>Mode: Host and Device. Host Negotiation Success Status Change (HstNegSucStsChng)</des…
1583 <description>No Change</description>
1588 <description>Host Negotiation Status Change</description>
1595 <description>Mode:Host and Device. Host Negotiation Detected (HstNegDet)</description>
1601 <description>No Active HNP Request</description>
1606 <description>Active HNP request detected</description>
1613 … <description>Mode: Host and Device. A-Device Timeout Change (ADevTOUTChg)</description>
1619 <description>No A-Device Timeout</description>
1624 <description>A-Device Timeout</description>
1631 <description>Mode: Host only. Debounce Done (DbnceDone)</description>
1637 <description>After Connect waiting for Debounce to complete</description>
1642 <description>Debounce completed</description>
1649 …<description>This bit when set indicates that there is a change in the value of at least one ACA p…
1655 <description>Indicates there is no change in ACA pin value</description>
1660 <description>Indicates there is a change in ACA pin value</description>
1669 <description>AHB Configuration Register</description>
1677 <description>Mode: Host and device. Global Interrupt Mask (GlblIntrMsk)</description>
1683 <description>Mask the interrupt assertion to the application</description>
1688 <description>Unmask the interrupt assertion to the application.</description>
1695 <description>Mode: Host and device. Burst Length/Type (HBstLen)</description>
1701 <description>1 word or single</description>
1706 <description>4 words or INCR</description>
1711 <description>8 words</description>
1716 <description>16 words or INCR4</description>
1721 <description>32 words</description>
1726 <description>64 words or INCR8</description>
1731 <description>128 words</description>
1736 <description>256 words or INCR16</description>
1741 <description>Others reserved</description>
1748 <description>Mode: Host and device. DMA Enable (DMAEn)</description>
1754 <description>Core operates in Slave mode</description>
1759 <description>Core operates in a DMA mode</description>
1766 … <description>Mode: Host and device. Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)</description>
1772 …<description>DIEPINTn.TxFEmp interrupt indicates that the Non-Periodic TxFIFO is half empty or tha…
1777 …description>GINTSTS.NPTxFEmp interrupt indicates that the Non-Periodic TxFIFO is completely empty …
1784 <description>Mode: Host and Device. Remote Memory Support (RemMemSupp)</description>
1790 <description>Remote Memory Support Feature disabled</description>
1795 <description>Remote Memory Support Feature enabled</description>
1802 …<description>Mode: Host and Device. Notify All DMA Write Transactions (NotiAllDmaWrit)</descriptio…
1808 <description>Unspecified</description>
1813 …description>The core asserts int_dma_req for all the DMA write transactions on the AHB interface a…
1820 <description>Mode: Host and Device. AHB Single Support (AHBSingle)</description>
1826 … <description>The remaining data in the transfer is sent using INCR burst size</description>
1831 … <description>The remaining data in the transfer is sent using Single burst size</description>
1840 <description>USB Configuration Register</description>
1848 <description>Mode: Host and Device. HS/FS Timeout Calibration (TOutCal)</description>
1854 <description>Add 0 PHY clocks</description>
1859 <description>Add 1 PHY clocks</description>
1864 <description>Add 2 PHY clocks</description>
1869 <description>Add 3 PHY clocks</description>
1874 <description>Add 4 PHY clocks</description>
1879 <description>Add 5 PHY clocks</description>
1884 <description>Add 6 PHY clocks</description>
1889 <description>Add 7 PHY clocks</description>
1896 <description>Mode: Host and Device. PHY Interface (PHYIf)</description>
1902 <description>PHY 8bit Mode</description>
1907 <description>PHY 16bit Mode</description>
1914 <description>Mode: Host and Device. ULPI or UTMI+ Select (ULPI_UTMI_Sel)</description>
1921 <description>UTMI+ Interface</description>
1926 <description>ULPI Interface</description>
1933 … <description>Mode: Host and Device. Full-Speed Serial Interface Select (FSIntf)</description>
1940 <description>6-pin unidirectional full-speed serial interface</description>
1945 <description>3-pin bidirectional full-speed serial interface</description>
1952 <description>PHYSel</description>
1959 <description>USB 2.0 high-speed UTMI+ or ULPI PHY is selected</description>
1964 <description>USB 1.1 full-speed serial transceiver is selected</description>
1971 <description>Mode: Device only. USB Turnaround Time (USBTrdTim)</description>
1977 <description>MAC interface is 16-bit UTMI+.</description>
1982 <description>MAC interface is 8-bit UTMI+.</description>
1989 <description>PHY Low-Power Clock Select (PhyLPwrClkSel)</description>
1995 <description>480-MHz Internal PLL clock</description>
2000 <description>48-MHz External Clock</description>
2007 … <description>Mode: Device only. TermSel DLine Pulsing Selection (TermSelDLPulse)</description>
2013 <description>Data line pulsing using utmi_txvalid</description>
2018 <description>Data line pulsing using utmi_termsel</description>
2025 <description>Mode: Host and Device. IC_USB-Capable (IC_USBCap)</description>
2032 <description>IC_USB PHY Interface is not selected</description>
2037 <description>IC_USB PHY Interface is selected</description>
2044 <description>Mode: Device only. Tx End Delay (TxEndDelay)</description>
2050 <description>Normal Mode</description>
2055 <description>Tx End delay</description>
2062 <description>Mode: Host and device. Force Host Mode (ForceHstMode)</description>
2068 <description>Normal Mode</description>
2073 <description>Force Host Mode</description>
2080 <description>Mode:Host and device. Force Device Mode (ForceDevMode)</description>
2086 <description>Normal Mode</description>
2091 <description>Force Device Mode</description>
2098 <description>Mode: Host and device. Corrupt Tx packet (CorruptTxPkt)</description>
2105 <description>Normal Mode</description>
2110 <description>Debug Mode</description>
2119 <description>Reset Register</description>
2127 <description>Mode: Host and Device. Core Soft Reset (CSftRst)</description>
2133 <description>No reset</description>
2138 <description>Resets hclk and phy_clock domains</description>
2145 …<description>Mode: Host and Device. PIU FS Dedicated Controller Soft Reset (PIUFSSftRst)</descript…
2151 <description>No Reset</description>
2156 <description>PIU FS Dedicated Controller Soft Reset</description>
2163 <description>Mode: Host only. Host Frame Counter Reset (FrmCntrRst)</description>
2169 <description>No reset</description>
2174 <description>Host Frame Counter Reset</description>
2181 <description>Mode: Host and Device. RxFIFO Flush (RxFFlsh)</description>
2187 <description>Does not flush the entire RxFIFO</description>
2192 <description>Flushes the entire RxFIFO</description>
2199 <description>Mode: Host and Device. TxFIFO Flush (TxFFlsh)</description>
2205 <description>No Flush</description>
2210 <description>Selectively flushes a single or all transmit FIFOs</description>
2217 <description>Mode: Host and Device. TxFIFO Number (TxFNum)</description>
2223 …description>-Periodic TxFIFO flush in host mode -Periodic TxFIFO 0 flush in device mode when in sh…
2228 …description>-Periodic TxFIFO flush in host mode -Periodic TxFIFO 1 flush in device mode when in sh…
2233 …description>-Periodic TxFIFO 2 flush in device mode when in shared FIFO operation -TXFIFO 2 flush …
2238 …description>-Periodic TxFIFO 3 flush in device mode when in shared FIFO operation -TXFIFO 3 flush …
2243 …description>-Periodic TxFIFO 4 flush in device mode when in shared FIFO operation -TXFIFO 4 flush …
2248 …description>-Periodic TxFIFO 5 flush in device mode when in shared FIFO operation -TXFIFO 5 flush …
2253 …description>-Periodic TxFIFO 6 flush in device mode when in shared FIFO operation -TXFIFO 6 flush …
2258 …description>-Periodic TxFIFO 7 flush in device mode when in shared FIFO operation -TXFIFO 7 flush …
2263 …description>-Periodic TxFIFO 8 flush in device mode when in shared FIFO operation -TXFIFO 8 flush …
2268 …description>-Periodic TxFIFO 9 flush in device mode when in shared FIFO operation -TXFIFO 9 flush …
2273 …description>-Periodic TxFIFO 10 flush in device mode when in shared FIFO operation -TXFIFO 10 flus…
2278 …description>-Periodic TxFIFO 11 flush in device mode when in shared FIFO operation -TXFIFO 11 flus…
2283 …description>-Periodic TxFIFO 12 flush in device mode when in shared FIFO operation -TXFIFO 12 flus…
2288 …description>-Periodic TxFIFO 13 flush in Device mode when in shared FIFO operation -TXFIFO 13 flus…
2293 …description>-Periodic TxFIFO 14 flush in Device mode when in shared FIFO operation -TXFIFO 14 flus…
2298 …description>-Periodic TxFIFO 15 flush in Device mode when in shared FIFO operation - TXFIFO 15 flu…
2303 <description>Flush all the transmit FIFOs in device or host mode</description>
2310 <description>Mode: Host and Device. Core Soft Reset Done (CSftRstDone)</description>
2316 <description>No reset</description>
2321 <description>Core Soft Reset is done</description>
2328 <description>Mode: Host and Device. DMA Request Signal (DMAReq)</description>
2335 <description>No DMA request</description>
2340 <description>DMA request is in progress</description>
2347 <description>Mode: Host and Device. AHB Master Idle (AHBIdle)</description>
2354 <description>Not Idle</description>
2359 <description>AHB Master Idle</description>
2368 <description>Interrupt Register</description>
2376 <description>Mode: Host and Device. Current Mode of Operation (CurMod)</description>
2383 <description>Device mode</description>
2388 <description>Host mode</description>
2395 <description>Mode: Host and Device. Mode Mismatch Interrupt (ModeMis)</description>
2401 <description>No Mode Mismatch Interrupt</description>
2406 <description>Mode Mismatch Interrupt</description>
2413 <description>Mode: Host and Device. OTG Interrupt (OTGInt)</description>
2420 <description>No Interrupt</description>
2425 <description>OTG Interrupt</description>
2432 <description>Mode: Host and Device. Start of (micro)Frame (Sof)</description>
2438 <description>No Start of Frame</description>
2443 <description>Start of Frame</description>
2450 <description>Mode: Host and Device. RxFIFO Non-Empty (RxFLvl)</description>
2457 <description>Rx Fifo is empty</description>
2462 <description>Rx Fifo is not empty</description>
2469 <description>Mode: Host and Device. Non-periodic TxFIFO Empty (NPTxFEmp)</description>
2476 <description>Non-periodic TxFIFO is not empty</description>
2481 <description>Non-periodic TxFIFO is empty</description>
2488 … <description>Mode: Device only. Global IN Non-periodic NAK Effective (GINNakEff)</description>
2495 <description>Global Non-periodic IN NAK not active</description>
2500 <description>Set Global Non-periodic IN NAK bit</description>
2507 <description>Mode: Device only. Global OUT NAK Effective (GOUTNakEff)</description>
2514 <description>Not Active</description>
2519 <description>Global OUT NAK Effective</description>
2526 <description>Mode: Device only. Early Suspend (ErlySusp)</description>
2532 <description>No Idle state detected</description>
2537 <description>3ms of Idle state detected</description>
2544 <description>Mode: Device only. USB Suspend (USBSusp)</description>
2550 <description>Not Active</description>
2555 <description>USB Suspend</description>
2562 <description>Mode: Device only. USB Reset (USBRst)</description>
2568 <description>Not active</description>
2573 <description>USB Reset</description>
2580 <description>Mode: Device only. Enumeration Done (EnumDone)</description>
2586 <description>Not active</description>
2591 <description>Enumeration Done</description>
2598 …<description>Mode: Device only. Isochronous OUT Packet Dropped Interrupt (ISOOutDrop)</description>
2604 <description>Not active</description>
2609 <description>Isochronous OUT Packet Dropped Interrupt</description>
2616 <description>Mode: Device only. End of Periodic Frame Interrupt (EOPF)</description>
2622 <description>Not active</description>
2627 <description>End of Periodic Frame Interrupt</description>
2634 <description>Mode: Device only. Restore Done Interrupt (RstrDoneInt)</description>
2640 <description>Not active</description>
2645 <description>Restore Done Interrupt</description>
2652 <description>Mode: Device only. Endpoint Mismatch Interrupt (EPMis)</description>
2658 <description>Not active</description>
2663 <description>Endpoint Mismatch Interrupt</description>
2670 <description>Mode: Device only. IN Endpoints Interrupt (IEPInt)</description>
2677 <description>Not active</description>
2682 <description>IN Endpoints Interrupt</description>
2689 <description>Mode: Device only. OUT Endpoints Interrupt (OEPInt)</description>
2696 <description>Not active</description>
2701 <description>OUT Endpoints Interrupt</description>
2708 … <description>Mode: Device only. Incomplete Isochronous IN Transfer (incompISOIN)</description>
2714 <description>Not active</description>
2719 <description>Incomplete Isochronous IN Transfer</description>
2726 <description>Incomplete Periodic Transfer (incomplP)</description>
2732 <description>Not active</description>
2737 <description>Incomplete Periodic Transfer</description>
2744 <description>Mode: Device only. Data Fetch Suspended (FetSusp)</description>
2750 <description>Not active</description>
2755 <description>Data Fetch Suspended</description>
2762 <description>Mode: Device only. Reset detected Interrupt (ResetDet)</description>
2768 <description>Not active</description>
2773 <description>Reset detected Interrupt</description>
2780 <description>Mode: Host only. Host Port Interrupt (PrtInt)</description>
2787 <description>Not active</description>
2792 <description>Host Port Interrupt</description>
2799 <description>Mode: Host only. Host Channels Interrupt (HChInt)</description>
2806 <description>Not active</description>
2811 <description>Host Channels Interrupt</description>
2818 … <description>Mode: Host and Device. LPM Transaction Received Interrupt (LPM_Int).</description>
2824 <description>Not Active</description>
2829 <description>LPM Transaction Received Interrupt</description>
2836 … <description>Mode: Host and Device. Connector ID Status Change (ConIDStsChng)</description>
2842 <description>Not Active</description>
2847 <description>Connector ID Status Change</description>
2854 <description>Mode: Host only. Disconnect Detected Interrupt (DisconnInt)</description>
2860 <description>Not active</description>
2865 <description>Disconnect Detected Interrupt</description>
2872 …<description>Mode: Host and Device. Session Request/New Session Detected Interrupt (SessReqInt)</d…
2878 <description>Not active</description>
2883 <description>Session Request New Session Detected Interrupt</description>
2890 …<description>Mode: Host and Device. Resume/Remote Wakeup Detected Interrupt (WkUpInt)</description>
2896 <description>Not active</description>
2901 <description>Resume or Remote Wakeup Detected Interrupt</description>
2910 <description>Interrupt Mask Register</description>
2918 … <description>Mode: Host and Device. Mode Mismatch Interrupt Mask (ModeMisMsk)</description>
2924 <description>Mode Mismatch Interrupt Mask</description>
2929 <description>No Mode Mismatch Interrupt Mask</description>
2936 <description>Mode: Host and Device. OTG Interrupt Mask (OTGIntMsk)</description>
2942 <description>OTG Interrupt Mask</description>
2947 <description>No OTG Interrupt Mask</description>
2954 <description>Mode: Host and Device. Start of (micro)Frame Mask (SofMsk)</description>
2960 <description>Start of Frame Mask</description>
2965 <description>No Start of Frame Mask</description>
2972 … <description>Mode: Host and Device. Receive FIFO Non-Empty Mask (RxFLvlMsk)</description>
2978 <description>Receive FIFO Non-Empty Mask</description>
2983 <description>No Receive FIFO Non-Empty Mask</description>
2990 … <description>Mode: Host and Device. Non-periodic TxFIFO Empty Mask (NPTxFEmpMsk)</description>
2996 <description>Non-periodic TxFIFO Empty Mask</description>
3001 <description>No Non-periodic TxFIFO Empty Mask</description>
3008 …<description>Mode: Device only,. Global Non-periodic IN NAK Effective Mask (GINNakEffMsk)</descrip…
3014 <description>Global Non-periodic IN NAK Effective Mask</description>
3019 <description>No Global Non-periodic IN NAK Effective Mask</description>
3026 … <description>Mode: Device only. Global OUT NAK Effective Mask (GOUTNakEffMsk)</description>
3032 <description>Global OUT NAK Effective Mask</description>
3037 <description>No Global OUT NAK Effective Mask</description>
3044 <description>Mode: Device only. Early Suspend Mask (ErlySuspMsk)</description>
3050 <description>Early Suspend Mask</description>
3055 <description>No Early Suspend Mask</description>
3062 <description>Mode: Device only. USB Suspend Mask (USBSuspMsk)</description>
3068 <description>USB Suspend Mask</description>
3073 <description>No USB Suspend Mask</description>
3080 <description>Mode: Device only. USB Reset Mask (USBRstMsk)</description>
3086 <description>USB Reset Mask</description>
3091 <description>No USB Reset Mask</description>
3098 <description>Mode: Device only. Enumeration Done Mask (EnumDoneMsk)</description>
3104 <description>Enumeration Done Mask</description>
3109 <description>No Enumeration Done Mask</description>
3116 …<description>Mode: Device only. Isochronous OUT Packet Dropped Interrupt Mask (ISOOutDropMsk)</des…
3122 <description>Isochronous OUT Packet Dropped Interrupt Mask</description>
3127 <description>No Isochronous OUT Packet Dropped Interrupt Mask</description>
3134 … <description>Mode: Device only. End of Periodic Frame Interrupt Mask (EOPFMsk)</description>
3140 <description>End of Periodic Frame Interrupt Mask</description>
3145 <description>No End of Periodic Frame Interrupt Mask</description>
3152 … <description>Mode: Host and Device. Restore Done Interrupt Mask (RstrDoneIntMsk)</description>
3158 <description>Restore Done Interrupt Mask</description>
3163 <description>No Restore Done Interrupt Mask</description>
3170 … <description>Mode: Device only. Endpoint Mismatch Interrupt Mask (EPMisMsk)</description>
3176 <description>Endpoint Mismatch Interrupt Mask</description>
3181 <description>No Endpoint Mismatch Interrupt Mask</description>
3188 <description>Mode: Device only. IN Endpoints Interrupt Mask (IEPIntMsk)</description>
3194 <description>IN Endpoints Interrupt Mask</description>
3199 <description>No IN Endpoints Interrupt Mask</description>
3206 <description>Mode: Device only. OUT Endpoints Interrupt Mask (OEPIntMsk)</description>
3212 <description>OUT Endpoints Interrupt Mask</description>
3217 <description>No OUT Endpoints Interrupt Mask</description>
3224 <description>Incomplete Periodic Transfer Mask (incomplPMsk)</description>
3230 …<description>Host mode: Incomplete Periodic Transfer MaskDevice mode: Incomplete Isochronous OUT T…
3235 …<description>Host mode: No Incomplete Periodic Transfer MaskDevice mode: No Incomplete Isochronous…
3242 <description>Mode: Device only. Data Fetch Suspended Mask (FetSuspMsk)</description>
3248 <description>Data Fetch Suspended Mask</description>
3253 <description>No Data Fetch Suspended Mask</description>
3260 … <description>Mode: Device only. Reset detected Interrupt Mask (ResetDetMsk)</description>
3266 <description>Reset detected Interrupt Mask</description>
3271 <description>No Reset detected Interrupt Mask</description>
3278 <description>Mode: Host only. Host Port Interrupt Mask (PrtIntMsk)</description>
3284 <description>Host Port Interrupt Mask</description>
3289 <description>No Host Port Interrupt Mask</description>
3296 <description>Mode: Host only. Host Channels Interrupt Mask (HChIntMsk)</description>
3302 <description>Host Channels Interrupt Mask</description>
3307 <description>No Host Channels Interrupt Mask</description>
3314 … <description>Mode: Host and Device. LPM Transaction Received Interrupt (LPM_Int)</description>
3320 <description>LPM Transaction received interrupt Mask</description>
3325 <description>No LPM Transaction received interrupt Mask</description>
3332 …<description>Mode: Host and Device. Connector ID Status Change Mask (ConIDStsChngMsk)</description>
3338 <description>Connector ID Status Change Mask</description>
3343 <description>No Connector ID Status Change Mask</description>
3350 …<description>Mode: Host and Device. Disconnect Detected Interrupt Mask (DisconnIntMsk)</descriptio…
3356 <description>Disconnect Detected Interrupt Mask</description>
3361 <description>No Disconnect Detected Interrupt Mask</description>
3368 …<description>Mode: Host and Device. Session Request/New Session Detected Interrupt Mask (SessReqIn…
3374 <description>Session Request or New Session Detected Interrupt Mask</description>
3379 … <description>No Session Request or New Session Detected Interrupt Mask</description>
3386 …<description>Mode: Host and Device. Resume/Remote Wakeup Detected Interrupt Mask (WkUpIntMsk)</des…
3392 <description>Resume or Remote Wakeup Detected Interrupt Mask</description>
3397 <description>Unmask Resume Remote Wakeup Detected Interrupt</description>
3406 <description>Receive Status Debug Read Register</description>
3414 <description>Channel Number (ChNum)</description>
3421 <description>Channel or EndPoint 0</description>
3426 <description>Channel or EndPoint 1</description>
3431 <description>Channel or EndPoint 2</description>
3436 <description>Channel or EndPoint 3</description>
3441 <description>Channel or EndPoint 4</description>
3446 <description>Channel or EndPoint 5</description>
3451 <description>Channel or EndPoint 6</description>
3456 <description>Channel or EndPoint 7</description>
3461 <description>Channel or EndPoint 8</description>
3466 <description>Channel or EndPoint 9</description>
3471 <description>Channel or EndPoint 10</description>
3476 <description>Channel or EndPoint 11</description>
3481 <description>Channel or EndPoint 12</description>
3486 <description>Channel or EndPoint 13</description>
3491 <description>Channel or EndPoint 14</description>
3496 <description>Channel or EndPoint 15</description>
3503 <description>Byte Count (BCnt)</description>
3510 <description>Data PID (DPID)</description>
3517 <description>DATA0</description>
3522 <description>DATA2</description>
3527 <description>DATA1</description>
3532 <description>MDATA</description>
3539 … <description>Packet Status (PktSts) indicates the status of the received packet.</description>
3546 <description>Global OUT NAK in device mode (triggers an interrupt)</description>
3551 …<description>IN data packet received in host mode and OUT data packet received in device mode</des…
3556 …<description>IN or OUT transfer completed in both host and device mode (triggers an interrupt)</de…
3561 … <description>SETUP transaction completed in device mode (triggers an interrupt)</description>
3566 <description>Data toggle error (triggers an interrupt) in host mode</description>
3571 <description>SETUP data packet received in device mode</description>
3576 <description>Channel halted in host mode (triggers an interrupt)</description>
3583 <description>Mode: Device only. Frame Number (FN)</description>
3592 <description>Receive Status Read/Pop Register</description>
3600 <description>Channel Number (ChNum)</description>
3607 <description>Channel or EndPoint 0</description>
3612 <description>Channel or EndPoint 1</description>
3617 <description>Channel or EndPoint 2</description>
3622 <description>Channel or EndPoint 3</description>
3627 <description>Channel or EndPoint 4</description>
3632 <description>Channel or EndPoint 5</description>
3637 <description>Channel or EndPoint 6</description>
3642 <description>Channel or EndPoint 7</description>
3647 <description>Channel or EndPoint 8</description>
3652 <description>Channel or EndPoint 9</description>
3657 <description>Channel or EndPoint 10</description>
3662 <description>Channel or EndPoint 11</description>
3667 <description>Channel or EndPoint 12</description>
3672 <description>Channel or EndPoint 13</description>
3677 <description>Channel or EndPoint 14</description>
3682 <description>Channel or EndPoint 15</description>
3689 <description>Byte Count (BCnt)</description>
3696 <description>Data PID (DPID)</description>
3703 <description>DATA0</description>
3708 <description>DATA2</description>
3713 <description>DATA1</description>
3718 <description>MDATA</description>
3725 … <description>Packet Status (PktSts) indicates the status of the received packet.</description>
3732 <description>Global OUT NAK in device mode (triggers an interrupt)</description>
3737 …<description>IN data packet received in host mode and OUT data packet received in device mode</des…
3742 …<description>IN or OUT transfer completed in both host and device mode (triggers an interrupt)</de…
3747 … <description>SETUP transaction completed in device mode (triggers an interrupt)</description>
3752 <description>Data toggle error (triggers an interrupt) in host mode</description>
3759 <description>Mode: Device only. Frame Number (FN)</description>
3768 <description>Receive FIFO Size Register</description>
3776 <description>Mode: Host and Device. RxFIFO Depth (RxFDep)</description>
3784 <description>Non-periodic Transmit FIFO Size Register</description>
3792 <description>Non-periodic Transmit RAM Start Address (NPTxFStAddr)</description>
3798 <description>Mode: Host only. Non-periodic TxFIFO Depth (NPTxFDep)</description>
3806 <description>Non-periodic Transmit FIFO/Queue Status Register</description>
3814 <description>Non-periodic TxFIFO Space Avail (NPTxFSpcAvail)</description>
3821 … <description>Non-periodic Transmit Request Queue Space Available (NPTxQSpcAvail)</description>
3828 <description>Non-periodic Transmit Request Queue is full</description>
3833 <description>1 location available</description>
3838 <description>2 locations available</description>
3843 <description>3 locations available</description>
3848 <description>4 locations available</description>
3853 <description>5 locations available</description>
3858 <description>6 locations available</description>
3863 <description>7 locations available</description>
3868 <description>8 locations available</description>
3875 <description>Top of the Non-periodic Transmit Request Queue (NPTxQTop)</description>
3882 <description>IN/OUT token</description>
3887 <description>Zero-length transmit packet (device IN/host OUT)</description>
3892 <description>PING/CSPLIT token</description>
3897 <description>Channel halt command</description>
3906 <description>General Purpose Input/Output Register</description>
3927 <description>User ID Register</description>
3935 <description>User ID (UserID) Application-programmable ID field.</description>
3943 <description>Synopsys ID Register</description>
3951 <description>Release number of the controller being used currently.</description>
3960 <description>User Hardware Configuration 1 Register</description>
3968 <description>This 32-bit field uses two bits per</description>
3977 <description>User Hardware Configuration 2 Register</description>
3985 <description>Mode of Operation (OtgMode)</description>
3992 <description>HNP- and SRP-Capable OTG (Host and Device)</description>
3997 <description>SRP-Capable OTG (Host and Device)</description>
4002 <description>Non-HNP and Non-SRP Capable OTG (Host and Device)</description>
4007 <description>SRP-Capable Device</description>
4012 <description>Non-OTG Device</description>
4017 <description>SRP-Capable Host</description>
4022 <description>Non-OTG Host</description>
4029 <description>Architecture (OtgArch)</description>
4036 <description>Slave Mode</description>
4041 <description>External DMA Mode</description>
4046 <description>Internal DMA Mode</description>
4053 <description>Point-to-Point (SingPnt)</description>
4060 <description>Multi-point application (hub and split support)</description>
4065 <description>Single-point application (no hub and split support)</description>
4072 <description>High-Speed PHY Interface Type (HSPhyType)</description>
4079 <description>High-Speed interface not supported</description>
4084 <description>High Speed Interface UTMI+ is supported</description>
4089 <description>High Speed Interface ULPI is supported</description>
4094 <description>High Speed Interfaces UTMI+ and ULPI is supported</description>
4101 <description>Full-Speed PHY Interface Type (FSPhyType)</description>
4108 <description>Full-speed interface not supported</description>
4113 <description>Dedicated full-speed interface is supported</description>
4118 <description>FS pins shared with UTMI+ pins is supported</description>
4123 <description>FS pins shared with ULPI pins is supported</description>
4130 <description>Number of Device Endpoints (NumDevEps)</description>
4137 <description>End point 0</description>
4142 <description>End point 1</description>
4147 <description>End point 2</description>
4152 <description>End point 3</description>
4157 <description>End point 4</description>
4162 <description>End point 5</description>
4167 <description>End point 6</description>
4172 <description>End point 7</description>
4177 <description>End point 8</description>
4182 <description>End point 9</description>
4187 <description>End point 10</description>
4192 <description>End point 11</description>
4197 <description>End point 12</description>
4202 <description>End point 13</description>
4207 <description>End point 14</description>
4212 <description>End point 15</description>
4219 <description>Number of Host Channels (NumHstChnl)</description>
4226 <description>Host Channel 1</description>
4231 <description>Host Channel 2</description>
4236 <description>Host Channel 3</description>
4241 <description>Host Channel 4</description>
4246 <description>Host Channel 5</description>
4251 <description>Host Channel 6</description>
4256 <description>Host Channel 7</description>
4261 <description>Host Channel 8</description>
4266 <description>Host Channel 9</description>
4271 <description>Host Channel 10</description>
4276 <description>Host Channel 11</description>
4281 <description>Host Channel 12</description>
4286 <description>Host Channel 13</description>
4291 <description>Host Channel 14</description>
4296 <description>Host Channel 15</description>
4301 <description>Host Channel 16</description>
4308 <description>Periodic OUT Channels Supported in Host Mode (PerioSupport)</description>
4315 <description>Periodic OUT Channels is not supported in Host Mode</description>
4320 <description>Periodic OUT Channels Supported in Host Mode Supported</description>
4327 <description>Dynamic FIFO Sizing Enabled (DynFifoSizing)</description>
4334 <description>Dynamic FIFO Sizing Disabled</description>
4339 <description>Dynamic FIFO Sizing Enabled</description>
4346 <description>Multi Processor Interrupt Enabled (MultiProcIntrpt)</description>
4353 <description>No Multi Processor Interrupt Enabled</description>
4358 <description>Multi Processor Interrupt Enabled</description>
4365 <description>Non-periodic Request Queue Depth (NPTxQDepth)</description>
4372 <description>Queue size 2</description>
4377 <description>Queue size 4</description>
4382 <description>Queue size 8</description>
4389 <description>Host Mode Periodic Request Queue Depth (PTxQDepth)</description>
4396 <description>Queue Depth 2</description>
4401 <description>Queue Depth 4</description>
4406 <description>Queue Depth 8</description>
4411 <description>Queue Depth 16</description>
4418 … <description>Device Mode IN Token Sequence Learning Queue Depth (TknQDepth)</description>
4427 <description>User Hardware Configuration 3 Register</description>
4435 <description>Width of Transfer Size Counters (XferSizeWidth)</description>
4442 <description>Width of Transfer Size Counter 11 bits</description>
4447 <description>Width of Transfer Size Counter 12 bits</description>
4452 <description>Width of Transfer Size Counter 13 bits</description>
4457 <description>Width of Transfer Size Counter 14 bits</description>
4462 <description>Width of Transfer Size Counter 15 bits</description>
4467 <description>Width of Transfer Size Counter 16 bits</description>
4472 <description>Width of Transfer Size Counter 17 bits</description>
4477 <description>Width of Transfer Size Counter 18 bits</description>
4482 <description>Width of Transfer Size Counter 19 bits</description>
4489 <description>Width of Packet Size Counters (PktSizeWidth)</description>
4496 <description>Width of Packet Size Counter 4</description>
4501 <description>Width of Packet Size Counter 5</description>
4506 <description>Width of Packet Size Counter 6</description>
4511 <description>Width of Packet Size Counter 7</description>
4516 <description>Width of Packet Size Counter 8</description>
4521 <description>Width of Packet Size Counter 9</description>
4526 <description>Width of Packet Size Counter 10</description>
4533 <description>OTG Function Enabled (OtgEn)</description>
4540 <description>Not OTG Capable</description>
4545 <description>OTG Capable</description>
4552 <description>I2C Selection (I2CIntSel)</description>
4559 <description>I2C Interface is not available</description>
4564 <description>I2C Interface is available</description>
4571 <description>Vendor Control Interface Support (VndctlSupt)</description>
4578 <description>Vendor Control Interface is not available.</description>
4583 <description>Vendor Control Interface is available.</description>
4590 <description>Optional Features Removed (OptFeature)</description>
4597 <description>Optional features were not Removed</description>
4602 <description>Optional Features have been Removed</description>
4609 <description>Reset Style for Clocked always Blocks in RTL (RstType)</description>
4616 <description>Asynchronous reset is used in the core</description>
4621 <description>Synchronous reset is used in the core</description>
4628 …<description>This bit indicates whether ADP logic is present within or external to the controller<…
4635 <description>ADP logic is not present along with the controller</description>
4640 <description>ADP logic is present along with the controller</description>
4647 <description>HSIC mode specified for Mode of Operation</description>
4654 <description>No HSIC capability</description>
4659 <description>HSIC-capable with shared UTMI PHY interface</description>
4666 … <description>This bit indicates the controller support for Battery Charger.</description>
4673 <description>No Battery Charger Support</description>
4678 <description>Battery Charger Support present</description>
4685 <description>LPM mode specified for Mode of Operation.</description>
4692 <description>LPM disabled</description>
4697 <description>LPM enabled</description>
4704 <description>DFIFO Depth (DfifoDepth - EP_LOC_CNT)</description>
4713 <description>User Hardware Configuration 4 Register</description>
4721 … <description>Number of Device Mode Periodic IN Endpoints (NumDevPerioEps)</description>
4728 <description>Number of Periodic IN EPs is 0</description>
4733 <description>Number of Periodic IN EPs is 1</description>
4738 <description>Number of Periodic IN EPs is 2</description>
4743 <description>Number of Periodic IN EPs is 3</description>
4748 <description>Number of Periodic IN EPs is 4</description>
4753 <description>Number of Periodic IN EPs is 5</description>
4758 <description>Number of Periodic IN EPs is 6</description>
4763 <description>Number of Periodic IN EPs is 7</description>
4768 <description>Number of Periodic IN EPs is 8</description>
4773 <description>Number of Periodic IN EPs is 9</description>
4778 <description>Number of Periodic IN EPs is 10</description>
4783 <description>Number of Periodic IN EPs is 11</description>
4788 <description>Number of Periodic IN EPs is 12</description>
4793 <description>Number of Periodic IN EPs is 13</description>
4798 <description>Number of Periodic IN EPs is 14</description>
4803 <description>Number of Periodic IN EPs is 15</description>
4810 <description>Enable Partial Power Down (PartialPwrDn)</description>
4817 <description>Partial Power Down disabled</description>
4822 <description>Partial Power Down enabled</description>
4829 <description>Minimum AHB Frequency Less Than 60 MHz (AhbFreq)</description>
4836 <description>Minimum AHB Frequency More Than 60 MHz</description>
4841 <description>Minimum AHB Frequency Less Than 60 MHz</description>
4848 <description>Enable Hibernation (Hibernation)</description>
4855 <description>Hibernation feature disabled</description>
4860 <description>Hibernation feature enabled</description>
4867 <description>Enable Hibernation</description>
4874 <description>Extended Hibernation feature not enabled</description>
4879 <description>Extended Hibernation feature enabled</description>
4886 <description>Enhanced LPM Support1 (EnhancedLPMSupt1)</description>
4893 …<description>Reject L1 Request even if Non-Periodic (Bulk/Interrupt) TxFIFO is not empty.</descrip…
4898 …<description>Accept L1 Request even if Non-Periodic (Bulk/Interrupt) TxFIFO is not empty</descript…
4905 <description>Service Interval Flow</description>
4912 <description>Service Interval Flow not supported</description>
4917 <description>Service Interval Flow supported</description>
4924 <description>Interpacket Gap ISOC OUT Worst-case Support (ipgisocSupt)</description>
4931 <description>Interpacket Gap ISOC OUT Worst-case Support is Disabled</description>
4936 … <description>Interpacket Gap ISOC OUT Worst-case Support is Enabled (Default)</description>
4943 <description>Active Clock Gating Support</description>
4950 <description>Unspecified</description>
4955 <description>Active Clock Gating Support</description>
4962 <description>Enhanced LPM Support (EnhancedLPMSupt)</description>
4969 <description>Enhanced LPM Support is enabled</description>
4976 <description>UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width</description>
4983 <description>8 bits</description>
4988 <description>16 bits</description>
4993 <description>8/16 bits, software selectable</description>
5000 <description>Number of Device Mode Control Endpoints in Addition to</description>
5007 <description>End point 0</description>
5012 <description>End point 1</description>
5017 <description>End point 2</description>
5022 <description>End point 3</description>
5027 <description>End point 4</description>
5032 <description>End point 5</description>
5037 <description>End point 6</description>
5042 <description>End point 7</description>
5047 <description>End point 8</description>
5052 <description>End point 9</description>
5057 <description>End point 10</description>
5062 <description>End point 11</description>
5067 <description>End point 12</description>
5072 <description>End point 13</description>
5077 <description>End point 14</description>
5082 <description>End point 15</description>
5089 <description>IDDIG Filter Enable (IddgFltr)</description>
5096 <description>Iddig Filter Disabled</description>
5101 <description>Iddig Filter Enabled</description>
5108 <description>VBUS Valid Filter Enabled (VBusValidFltr)</description>
5115 <description>Vbus Valid Filter Disabled</description>
5120 <description>Vbus Valid Filter Enabled</description>
5127 <description>a_valid Filter Enabled (AValidFltr)</description>
5134 <description>No filter</description>
5139 <description>Filter</description>
5146 <description>b_valid Filter Enabled (BValidFltr)</description>
5153 <description>No Filter</description>
5158 <description>Filter</description>
5165 <description>session_end Filter Enabled (SessEndFltr)</description>
5172 <description>No filter</description>
5177 <description>Filter</description>
5184 <description>Enable Dedicated Transmit FIFO for device IN Endpoints</description>
5191 <description>Dedicated Transmit FIFO Operation not enabled</description>
5196 <description>Dedicated Transmit FIFO Operation enabled</description>
5203 … <description>Number of Device Mode IN Endpoints Including Control Endpoints (INEps)</description>
5210 <description>1 IN Endpoint</description>
5215 <description>2 IN Endpoints</description>
5220 <description>3 IN Endpoints</description>
5225 <description>4 IN Endpoints</description>
5230 <description>5 IN Endpoints</description>
5235 <description>6 IN Endpoints</description>
5240 <description>7 IN Endpoints</description>
5245 <description>8 IN Endpoints</description>
5250 <description>9 IN Endpoints</description>
5255 <description>10 IN Endpoints</description>
5260 <description>11 IN Endpoints</description>
5265 <description>12 IN Endpoints</description>
5270 <description>13 IN Endpoints</description>
5275 <description>14 IN Endpoints</description>
5280 <description>15 IN Endpoints</description>
5285 <description>16 IN Endpoints</description>
5292 <description>Scatter/Gather DMA configuration</description>
5299 <description>Non-Scatter/Gather DMA configuration</description>
5304 <description>Scatter/Gather DMA configuration</description>
5311 <description>Scatter/Gather DMA configuration</description>
5318 <description>Non Dynamic configuration</description>
5323 <description>Dynamic configuration</description>
5332 <description>LPM Config Register</description>
5340 <description>LPM-Capable (LPMCap)</description>
5346 <description>LPM capability is not enabled</description>
5351 <description>LPM capability is enabled</description>
5358 … <description>Mode: Device only. LPM response programmed by application (AppL1Res)</description>
5364 …<description>The core responds with a NYET when an error is detected in either of the LPM token pa…
5369 … <description>The core responds with an ACK only on a successful LPM transaction</description>
5376 <description>Host-Initiated Resume Duration (HIRD)</description>
5382 <description>RemoteWakeEnable (bRemoteWake)</description>
5388 <description>Remote Wakeup is disabled</description>
5393 … <description>In Host or device mode, this field takes the value of remote wake up</description>
5400 <description>Enable utmi_sleep_n (EnblSlpM)</description>
5406 …<description>utmi_sleep_n assertion from the core is not transferred to the external PHY</descript…
5411 …<description>utmi_sleep_n assertion from the core is transferred to the external PHY when utmi_l1_…
5418 <description>BESL/HIRD Threshold (HIRD_Thres)</description>
5424 <description>LPM Response (CoreL1Res)</description>
5431 <description>ERROR : No handshake response</description>
5436 <description>STALL response</description>
5441 <description>NYET response</description>
5446 <description>ACK response</description>
5453 <description>Port Sleep Status (SlpSts)</description>
5460 … <description>In Host or Device mode, this bit indicates core is not in L1</description>
5465 …description>In Host mode, this bit indicates the core transitions to Sleep state as a successful L…
5472 <description>Sleep State Resume OK (L1ResumeOK)</description>
5479 … <description>The application/core cannot start Resume from Sleep state</description>
5484 <description>The application/core can start Resume from Sleep state</description>
5491 <description>LPM Channel Index</description>
5497 <description>Channel 0</description>
5502 <description>Channel 1</description>
5507 <description>Channel 2</description>
5512 <description>Channel 3</description>
5517 <description>Channel 4</description>
5522 <description>Channel 5</description>
5527 <description>Channel 6</description>
5532 <description>Channel 7</description>
5537 <description>Channel 8</description>
5542 <description>Channel 9</description>
5547 <description>Channel 10</description>
5552 <description>Channel 11</description>
5557 <description>Channel 12</description>
5562 <description>Channel 13</description>
5567 <description>Channel 14</description>
5572 <description>Channel15</description>
5579 <description>LPM Retry Count (LPM_Retry_Cnt)</description>
5585 <description>Zero LPM retries</description>
5590 <description>One LPM retry</description>
5595 <description>Two LPM retries</description>
5600 <description>Three LPM retries</description>
5605 <description>Four LPM retries</description>
5610 <description>Five LPM retries</description>
5615 <description>Six LPM retries</description>
5620 <description>Seven LPM retries</description>
5627 <description>Send LPM Transaction (SndLPM)</description>
5633 …<description>In host-only mode: Received the response from the device for the LPM transaction</des…
5638 …<description>In host-only mode: Sending LPM transaction containing EXT and LPM tokens</description>
5645 <description>LPM Retry Count Status (LPM_RetryCnt_Sts)</description>
5652 <description>Zero LPM retries remaining</description>
5657 <description>One LPM retry remaining</description>
5662 <description>Two LPM retries remaining</description>
5667 <description>Three LPM retries remaining</description>
5672 <description>Four LPM retries remaining</description>
5677 <description>Five LPM retries remaining</description>
5682 <description>Six LPM retries remaining</description>
5687 <description>Seven LPM retries remaining</description>
5694 <description>LPM Enable BESL (LPM_EnBESL)</description>
5700 <description>BESL is disabled</description>
5705 <description>BESL is enabled as defined in LPM Errata</description>
5712 <description>LPM Restore Sleep Status (LPM_RestoreSlpSts)</description>
5718 …<description>Puts the core in Shallow Sleep mode based on the BESL value from the Host</descriptio…
5723 … <description>Puts the core in Deep Sleep mode based on the BESL value from the Host</description>
5732 <description>Global Power Down Register</description>
5740 <description>PMU Interrupt Select (PMUIntSel)</description>
5746 <description>Internal DWC_otg_core interrupt is selected</description>
5751 <description>External DWC_otg_pmu interrupt is selected</description>
5758 <description>PMU Active (PMUActv)</description>
5764 <description>Disable PMU module</description>
5769 <description>Enable PMU module</description>
5776 <description>Restore</description>
5782 <description>The controller in normal mode of operation</description>
5787 <description>The controller in Restore mode</description>
5794 <description>Power Down Clamp (PwrDnClmp)</description>
5800 <description>Disable PMU power clamp</description>
5805 <description>Enable PMU power clamp</description>
5812 <description>Power Down ResetN (PwrDnRst_n)</description>
5818 <description>Reset the controller</description>
5823 <description>The controller is in normal operation</description>
5830 <description>Power Down Switch (PwrDnSwtch)</description>
5836 <description>The controller is in ON state</description>
5841 <description>The controller is in OFF state</description>
5848 <description>DisableVBUS</description>
5854 …<description>Host mode:HPRT0.PrtPwr was not programmed to 0, and in Device mode:Session Valid</des…
5859 …<description>Host mode:HPRT0.PrtPwr was programmed to 0 and in Device mode:Session End</descriptio…
5866 <description>Line State Change (LnStsChng)</description>
5872 <description>No LineState change on USB</description>
5877 <description>LineState change on USB</description>
5884 <description>LineStageChangeMsk</description>
5890 <description>No LineStateChange Interrupt Mask</description>
5895 <description>Mask for LineStateChange Interrupt</description>
5902 <description>ResetDetected</description>
5908 <description>Reset not detected</description>
5913 <description>Reset detected</description>
5920 <description>ResetDetMsk</description>
5926 <description>No ResetDetect Interrupt Mask</description>
5931 <description>Mask for ResetDetect Interrupt</description>
5938 <description>DisconnectDetect</description>
5944 <description>Disconnect not detected</description>
5949 <description>Disconnect detected</description>
5956 <description>DisconnectDetectMsk</description>
5962 <description>No DisconnectDetect Interrupt Mask</description>
5967 <description>Mask for DisconnectDetect Interrupt</description>
5974 <description>ConnectDet</description>
5980 <description>Connect not detected</description>
5985 <description>Connect detected</description>
5992 <description>ConnDetMsk</description>
5998 <description>No ConnectDet Interrupt Mask</description>
6003 <description>Mask for ConnectDet Interrupt</description>
6010 <description>SRPDetect</description>
6016 <description>SRP not detected</description>
6021 <description>SRP detected</description>
6028 <description>SRPDetectMsk</description>
6034 <description>No SRPDetect Interrupt Mask</description>
6039 <description>Mask for SRPDetect Interrupt</description>
6046 <description>Status Change Interrupt (StsChngInt)</description>
6052 <description>No Status change</description>
6057 <description>Status change detected</description>
6064 <description>StsChngIntMsk</description>
6070 <description>No Status Change Interrupt Mask</description>
6075 <description>Mask for Status Change Interrupt</description>
6082 <description>LineState</description>
6089 <description>Linestate on USB: DM = 0, DP = 0</description>
6094 <description>Linestate on USB: DM = 0, DP = 1</description>
6099 <description>Linestate on USB: DM = 1, DP = 0</description>
6104 <description>Linestate on USB: Not-defined</description>
6111 …description>This bit indicates the status of the signal IDDIG. The application must read this bit …
6118 <description>Host Mode</description>
6123 <description>Device Mode</description>
6130 <description>B Session Valid (BSessVld)</description>
6137 <description>B_Valid is 0</description>
6142 <description>B_Valid is 1</description>
6149 <description>MultValIdBC</description>
6156 <description>OTG device as B-device</description>
6161 <description>OTG device as B-device, can connect</description>
6166 <description>OTG device as B-device, cannot connect</description>
6171 <description>OTG device as A-device</description>
6176 <description>ID_OTG pin is grounded</description>
6181 <description>OTG device as A-device, RID_A=1 and RID_GND=1</description>
6186 <description>ID pull down when ID_OTG is floating</description>
6191 … <description>OTG device as B-device, can connect, RID_C=1 and RID_FLOAT=1</description>
6196 … <description>OTG device as B-device, cannot connect, RID_B=1 and RID_FLOAT=1</description>
6201 <description>OTG device as A-device</description>
6210 <description>Global DFIFO Configuration Register</description>
6218 <description>GDFIFOCfg</description>
6224 … <description>This field provides the start address of the EP info controller.</description>
6232 <description>Interrupt Mask Register 2</description>
6247 <description>Interrupt Register 2</description>
6262 <description>Host Periodic Transmit FIFO Size Register</description>
6270 <description>Host Periodic TxFIFO Start Address (PTxFStAddr)</description>
6276 <description>Host Periodic TxFIFO Depth (PTxFSize)</description>
6286 … <description>Description collection: Device IN Endpoint Transmit FIFO Size Register</description>
6294 … <description>IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr)</description>
6300 <description>IN Endpoint TxFIFO Depth (INEPnTxFDep)</description>
6308 <description>Host Configuration Register</description>
6316 <description>FS/LS PHY Clock Select (FSLSPclkSel)</description>
6322 <description>PHY clock is running at 30/60 MHz</description>
6327 <description>PHY clock is running at 48 MHz</description>
6332 <description>PHY clock is running at 6 MHz</description>
6339 <description>FS- and LS-Only Support (FSLSSupp)</description>
6345 … <description>HS/FS/LS, based on the maximum speed supported by the connected device</description>
6350 <description>FS/LS-only, even if the connected device can support HS</description>
6357 <description>Enable 32 KHz Suspend mode (Ena32KHzS)</description>
6363 <description>32 KHz Suspend mode disabled</description>
6368 <description>32 KHz Suspend mode enabled</description>
6375 <description>Resume Validation Period (ResValid)</description>
6381 <description>Mode Change Ready Timer Enable (ModeChTimEn)</description>
6387 …description>The Host core waits for either 200 PHY clock cycles or a linestate of SE0 at the end o…
6392 …<description>The Host core waits only for a linestate of SE0 at the end of resume to change the op…
6401 <description>Host Frame Interval Register</description>
6409 <description>Frame Interval (FrInt)</description>
6415 <description>Reload Control (HFIRRldCtrl)</description>
6421 <description>The HFIR cannot be reloaded dynamically</description>
6426 <description>The HFIR can be dynamically reloaded during runtime</description>
6435 <description>Host Frame Number/Frame Time Remaining Register</description>
6443 <description>Frame Number (FrNum)</description>
6450 <description>No SOF is transmitted</description>
6455 <description>SOF is transmitted</description>
6462 <description>Frame Time Remaining (FrRem)</description>
6471 <description>Host All Channels Interrupt Register</description>
6485 <description>Not active</description>
6490 <description>Host Channel Interrupt</description>
6499 <description>Host All Channels Interrupt Mask Register</description>
6507 <description>Channel Interrupt Mask (HAINTMsk)</description>
6513 <description>Unmask Channel interrupt</description>
6518 <description>Mask Channel interrupt</description>
6527 <description>Host Port Control and Status Register</description>
6535 <description>Port Connect Status (PrtConnSts)</description>
6542 <description>No device is attached to the port</description>
6547 <description>A device is attached to the port</description>
6554 <description>Port Connect Detected (PrtConnDet)</description>
6560 <description>No device connection detected</description>
6565 <description>Device connection detected</description>
6572 <description>Port Enable (PrtEna)</description>
6578 <description>Port disabled</description>
6583 <description>Port enabled</description>
6590 <description>Port Enable/Disable Change (PrtEnChng)</description>
6596 <description>Port Enable bit 2 has not changed</description>
6601 <description>Port Enable bit 2 changed</description>
6608 <description>Port Overcurrent Active (PrtOvrCurrAct)</description>
6615 <description>No overcurrent condition</description>
6620 <description>Overcurrent condition</description>
6627 <description>Port Overcurrent Change (PrtOvrCurrChng)</description>
6633 <description>Status of port overcurrent status is not changed</description>
6638 <description>Status of port overcurrent changed</description>
6645 <description>Port Resume (PrtRes)</description>
6651 <description>No resume driven</description>
6656 <description>Resume driven</description>
6663 <description>Port Suspend (PrtSusp)</description>
6669 <description>Port not in Suspend mode</description>
6674 <description>Port in Suspend mode</description>
6681 <description>Port Reset (PrtRst)</description>
6687 <description>Port not in reset</description>
6692 <description>Port in reset</description>
6699 <description>Port Line Status (PrtLnSts)</description>
6706 <description>Logic level of D+</description>
6711 <description>Logic level of D-</description>
6718 <description>Port Power (PrtPwr)</description>
6724 <description>Power off</description>
6729 <description>Power on</description>
6736 <description>Port Test Control (PrtTstCtl)</description>
6742 <description>Test mode disabled</description>
6747 <description>Test_J mode</description>
6752 <description>Test_K mode</description>
6757 <description>Test_SE0_NAK mode</description>
6762 <description>Test_Packet mode</description>
6767 <description>Test_force_Enable</description>
6774 <description>Port Speed (PrtSpd)</description>
6781 <description>High speed</description>
6786 <description>Full speed</description>
6791 <description>Low speed</description>
6802 <description>Unspecified</description>
6808 <description>Description cluster: Host Channel Characteristics Register</description>
6816 <description>Maximum Packet Size (MPS)</description>
6822 <description>Endpoint Number (EPNum)</description>
6828 <description>End point 0</description>
6833 <description>End point 1</description>
6838 <description>End point 2</description>
6843 <description>End point 3</description>
6848 <description>End point 4</description>
6853 <description>End point 5</description>
6858 <description>End point 6</description>
6863 <description>End point 7</description>
6868 <description>End point 8</description>
6873 <description>End point 9</description>
6878 <description>End point 10</description>
6883 <description>End point 11</description>
6888 <description>End point 12</description>
6893 <description>End point 13</description>
6898 <description>End point 14</description>
6903 <description>End point 15</description>
6910 <description>Endpoint Direction (EPDir)</description>
6916 <description>OUT Direction</description>
6921 <description>IN Direction</description>
6928 <description>Low-Speed Device (LSpdDev)</description>
6934 <description>Not Communicating with low speed device</description>
6939 <description>Communicating with low speed device</description>
6946 <description>Endpoint Type (EPType)</description>
6952 <description>Control</description>
6957 <description>Isochronous</description>
6962 <description>Bulk</description>
6967 <description>Interrupt</description>
6974 <description>Multi Count (MC) / Error Count (EC)</description>
6980 <description>1 transaction</description>
6985 … <description>2 transactions to be issued for this endpoint per microframe</description>
6990 … <description>3 transactions to be issued for this endpoint per microframe</description>
6997 <description>Device Address (DevAddr)</description>
7003 <description>Odd Frame (OddFrm)</description>
7009 <description>Even Frame Transfer</description>
7014 <description>Odd Frame Transfer</description>
7021 <description>Channel Disable (ChDis)</description>
7027 <description>Transmit/Recieve normal</description>
7032 <description>Stop transmitting/receiving data on channel</description>
7039 <description>Channel Enable (ChEna)</description>
7045 …description>If Scatter/Gather mode is enabled, indicates that the descriptor structure is not yet …
7050 …description>If Scatter/Gather mode is enabled, indicates that the descriptor structure and data bu…
7059 <description>Description cluster: Host Channel Interrupt Register</description>
7067 <description>Transfer Completed (XferCompl)</description>
7073 <description>Transfer in progress or No Active Transfer</description>
7078 <description>Transfer completed normally without any errors</description>
7085 <description>Channel Halted (ChHltd)</description>
7091 <description>Channel not halted</description>
7096 <description>Channel Halted</description>
7103 <description>AHB Error (AHBErr)</description>
7109 <description>No AHB error</description>
7114 <description>AHB error during AHB read/write</description>
7121 <description>STALL Response Received Interrupt (STALL)</description>
7127 <description>No Stall Response Received Interrupt</description>
7132 <description>Stall Response Received Interrupt</description>
7139 <description>NAK Response Received Interrupt (NAK)</description>
7145 <description>No NAK Response Received Interrupt</description>
7150 <description>NAK Response Received Interrupt</description>
7157 <description>ACK Response Received/Transmitted Interrupt (ACK)</description>
7163 <description>No ACK Response Received or Transmitted Interrupt</description>
7168 <description>ACK Response Received or Transmitted Interrup</description>
7175 <description>NYET Response Received Interrupt (NYET)</description>
7181 <description>No NYET Response Received Interrupt</description>
7186 <description>NYET Response Received Interrupt</description>
7193 <description>Transaction Error (XactErr)</description>
7199 <description>No Transaction Error</description>
7204 <description>Transaction Error</description>
7211 <description>Babble Error (BblErr)</description>
7217 <description>No Babble Error</description>
7222 <description>Babble Error</description>
7229 <description>Frame Overrun (FrmOvrun).</description>
7235 <description>No Frame Overrun</description>
7240 <description>Frame Overrun</description>
7252 <description>No Data Toggle Error</description>
7257 <description>Data Toggle Error</description>
7266 <description>Description cluster: Host Channel Interrupt Mask Register</description>
7279 <description>Transfer Completed Mask</description>
7284 <description>No Transfer Completed Mask</description>
7296 <description>Channel Halted Mask</description>
7301 <description>No Channel Halted Mask</description>
7313 <description>AHB Error Mask</description>
7318 <description>No AHB Error Mask</description>
7330 <description>Mask STALL Response Received Interrupt</description>
7335 <description>No STALL Response Received Interrupt Mask</description>
7347 <description>Mask NAK Response Received Interrupt</description>
7352 <description>No NAK Response Received Interrupt Mask</description>
7364 <description>Mask ACK Response Received/Transmitted Interrupt</description>
7369 <description>No ACK Response Received/Transmitted Interrupt Mask</description>
7381 <description>Mask NYET Response Received Interrupt</description>
7386 <description>No NYET Response Received Interrupt Mask</description>
7398 <description>Mask Transaction Error</description>
7403 <description>No Transaction Error Mask</description>
7415 <description>Mask Babble Error</description>
7420 <description>No Babble Error Mask</description>
7432 <description>Mask Overrun Mask</description>
7437 <description>No Frame Overrun Mask</description>
7449 <description>Mask Data Toggle Error</description>
7454 <description>No Data Toggle Error Mask</description>
7463 <description>Description cluster: Host Channel Transfer Size Register</description>
7471 <description>Non-Scatter/Gather DMA Mode:</description>
7477 <description>Non-Scatter/Gather DMA Mode:</description>
7483 <description>PID (Pid)</description>
7489 <description>DATA0</description>
7494 <description>DATA2</description>
7499 <description>DATA1</description>
7504 <description>MDATA (non-control)/SETUP (control)</description>
7511 <description>Do Ping (DoPng)</description>
7517 <description>No ping protocol</description>
7522 <description>Ping protocol</description>
7531 <description>Description cluster: Host Channel DMA Address Register</description>
7539 <description>In Buffer DMA Mode:</description>
7548 <description>Device Configuration Register</description>
7556 <description>Device Speed (DevSpd)</description>
7562 <description>High speed USB 2.0 PHY clock is 30 MHz or 60 MHz</description>
7567 <description>Full speed USB 2.0 PHY clock is 30 MHz or 60 MHz</description>
7572 <description>Low speed USB 1.1 transceiver clock is 6 MHz</description>
7577 <description>Full speed USB 1.1 transceiver clock is 48 MHz</description>
7584 <description>Non-Zero-Length Status OUT Handshake (NZStsOUTHShk)</description>
7590 …description>Send the received OUT packet to the application (zero-length or non-zero length) and s…
7595 …<description>Send a STALL handshake on a nonzero-length status OUT transaction and do not send the…
7602 <description>Enable 32 KHz Suspend mode (Ena32KHzSusp)</description>
7608 <description>USB 1.1 Full-Speed Serial Transceiver not selected</description>
7613 … <description>USB 1.1 Full-Speed Serial Transceiver Interface selected</description>
7620 <description>Device Address (DevAddr)</description>
7626 <description>Periodic Frame Interval (PerFrInt)</description>
7632 <description>80 percent of the (micro)Frame interval</description>
7637 <description>85 percent of the (micro)Frame interval</description>
7642 <description>90 percent of the (micro)Frame interval</description>
7647 <description>95 percent of the (micro)Frame interval</description>
7654 <description>XCVRDLY</description>
7660 … <description>No delay between xcvr_sel and txvalid during Device chirp</description>
7665 … <description>Enable delay between xcvr_sel and txvalid during Device chirp</description>
7672 <description>Erratic Error Interrupt Mask</description>
7678 <description>Early suspend interrupt is generated on erratic error</description>
7683 <description>Mask early suspend interrupt on erratic error</description>
7690 <description>Worst-Case Inter-Packet Gap ISOC OUT Support (ipgisocSupt)</description>
7696 … <description>Worst-Case Inter-Packet Gap ISOC OUT Support is disabled</description>
7701 <description>Worst-Case Inter-Packet Gap ISOC OUT Support is enabled</description>
7708 <description>Periodic Scheduling Interval (PerSchIntvl)</description>
7714 <description>25 percent of (micro)Frame</description>
7719 <description>50 percent of (micro)Frame</description>
7724 <description>75 percent of (micro)Frame</description>
7731 <description>Resume Validation Period (ResValid)</description>
7739 <description>Device Control Register</description>
7747 <description>Remote Wakeup Signaling (RmtWkUpSig)</description>
7753 <description>Core does not send Remote Wakeup Signaling</description>
7758 <description>Core sends Remote Wakeup Signaling</description>
7765 <description>Soft Disconnect (SftDiscon)</description>
7771 …<description>The core drives the phy_opmode_o signal on the UTMI+ to 2'b00, which generates a devi…
7776 …<description>The core drives the phy_opmode_o signal on the UTMI+ to 2'b01, which generates a devi…
7783 <description>Global Non-periodic IN NAK Status (GNPINNakSts)</description>
7790 …<description>A handshake is sent out based on the data availability in the transmit FIFO</descript…
7795 …<description>A NAK handshake is sent out on all non-periodic IN endpoints, irrespective of the dat…
7802 <description>Global OUT NAK Status (GOUTNakSts)</description>
7809 …<description>A handshake is sent based on the FIFO Status and the NAK and STALL bit settings.</des…
7814 …description>No data is written to the RxFIFO, irrespective of space availability. Sends a NAK hand…
7821 <description>Test Control (TstCtl)</description>
7827 <description>Test mode disabled</description>
7832 <description>Test_J mode</description>
7837 <description>Test_K mode</description>
7842 <description>Test_SE0_NAK mode</description>
7847 <description>Test_Packet mode</description>
7852 <description>Test_force_Enable</description>
7859 <description>Set Global Non-periodic IN NAK (SGNPInNak)</description>
7866 <description>Disable Global Non-periodic IN NAK</description>
7871 <description>Set Global Non-periodic IN NAK</description>
7878 <description>Clear Global Non-periodic IN NAK (CGNPInNak)</description>
7885 <description>Disable Global Non-periodic IN NAK</description>
7890 <description>Clear Global Non-periodic IN NAK</description>
7897 <description>Set Global OUT NAK (SGOUTNak)</description>
7904 <description>Disable Global OUT NAK</description>
7909 <description>Set Global OUT NAK</description>
7916 <description>Clear Global OUT NAK (CGOUTNak)</description>
7923 <description>Disable Clear Global OUT NAK</description>
7928 <description>Clear Global OUT NAK</description>
7935 <description>Power-On Programming Done (PWROnPrgDone)</description>
7941 <description>Power-On Programming not done</description>
7946 <description>Power-On Programming Done</description>
7953 … <description>Ignore Frame Number Feature for Isochronous Endpoints (IgnrFrmNum)</description>
7959 …description>Scatter/Gather DMA Mode: The core transmits the packets only in the frame number in wh…
7964 …description>Scatter/Gather DMA Mode: The core ignores the frame number, sending packets immediatel…
7971 <description>NAK on Babble Error (NakOnBble)</description>
7977 <description>Disable NAK on Babble Error</description>
7982 <description>NAK on Babble Error</description>
7989 <description>DeepSleepBESLReject</description>
7995 <description>Deep Sleep BESL Reject feature is disabled</description>
8000 <description>Deep Sleep BESL Reject feature is enabled</description>
8007 … <description>Service Interval based scheduling for Isochronous IN Endpoints</description>
8013 … <description>The controller behavior depends on DCTL.IgnrFrmNum field.</description>
8018 …<description>Scatter/Gather DMA Mode: The controller can transmit the packets in any frame of the …
8025 … <description>Disable the correction to OpMode/XcvrSel/TermSel on UTMI Interface.</description>
8031 …<description>Opmode, XcvrSel, TermSel are changed by the Device Controller after TxValid goes LOW …
8036 …<description>Opmode, XcvrSel, TermSel are changed by the Device Controller immediately on soft dis…
8043 <description>Disable the correction of TermSel on UTMI Interface.</description>
8049 …<description>Valid Combination of XcvrSel and TermSel is driven by the Device Controller.</descrip…
8054 …<description>Invalid Combination of XcvrSel and TermSel is driven by the Device Controller.</descr…
8063 <description>Device Status Register</description>
8071 <description>Suspend Status (SuspSts)</description>
8078 <description>No suspend state</description>
8083 <description>Suspend state</description>
8090 <description>Enumerated Speed (EnumSpd)</description>
8097 <description>High speed (PHY clock is running at 30 or 60 MHz)</description>
8102 <description>Full speed (PHY clock is running at 30 or 60 MHz)</description>
8107 <description>Low speed (PHY clock is running at 6 MHz)</description>
8112 <description>Full speed (PHY clock is running at 48 MHz)</description>
8119 <description>Erratic Error (ErrticErr)</description>
8126 <description>No Erratic Error</description>
8131 <description>Erratic Error</description>
8138 <description>Frame or Microframe Number of the Received SOF (SOFFN)</description>
8145 <description>Device Line Status (DevLnSts)</description>
8154 <description>Device IN Endpoint Common Interrupt Mask Register</description>
8162 <description>Transfer Completed Interrupt Mask (XferComplMsk)</description>
8168 <description>Mask Transfer Completed Interrupt</description>
8173 <description>No Transfer Completed Interrupt Mask</description>
8180 <description>Endpoint Disabled Interrupt Mask (EPDisbldMsk)</description>
8186 <description>Mask Endpoint Disabled Interrupt</description>
8191 <description>No Endpoint Disabled Interrupt Mask</description>
8198 <description>AHB Error Mask (AHBErrMsk)</description>
8204 <description>Mask AHB Error Interrupt</description>
8209 <description>No AHB Error Interrupt Mask</description>
8216 … <description>Timeout Condition Mask (TimeOUTMsk) (Non-isochronous endpoints)</description>
8222 <description>Mask Timeout Condition Interrupt</description>
8227 <description>No Timeout Condition Interrupt Mask</description>
8234 <description>IN Token Received When TxFIFO Empty Mask (INTknTXFEmpMsk)</description>
8240 <description>Mask IN Token Received When TxFIFO Empty Interrupt</description>
8245 <description>No IN Token Received When TxFIFO Empty Interrupt</description>
8252 <description>IN Token received with EP Mismatch Mask (INTknEPMisMsk)</description>
8258 <description>Mask IN Token received with EP Mismatch Interrupt</description>
8263 <description>No Mask IN Token received with EP Mismatch Interrupt</description>
8270 <description>IN Endpoint NAK Effective Mask (INEPNakEffMsk)</description>
8276 <description>Mask IN Endpoint NAK Effective Interrupt</description>
8281 <description>No IN Endpoint NAK Effective Interrupt Mask</description>
8288 <description>Fifo Underrun Mask (TxfifoUndrnMsk)</description>
8294 <description>Mask Fifo Underrun Interrupt</description>
8299 <description>No Fifo Underrun Interrupt Mask</description>
8306 <description>NAK interrupt Mask (NAKMsk)</description>
8312 <description>Mask NAK Interrupt</description>
8317 <description>No Mask NAK Interrupt</description>
8326 <description>Device OUT Endpoint Common Interrupt Mask Register</description>
8334 <description>Transfer Completed Interrupt Mask (XferComplMsk)</description>
8340 <description>Mask Transfer Completed Interrupt</description>
8345 <description>No Transfer Completed Interrupt Mask</description>
8352 <description>Endpoint Disabled Interrupt Mask (EPDisbldMsk)</description>
8358 <description>Mask Endpoint Disabled Interrupt</description>
8363 <description>No Endpoint Disabled Interrupt Mask</description>
8370 <description>AHB Error (AHBErrMsk)</description>
8376 <description>Mask AHB Error Interrupt</description>
8381 <description>No AHB Error Interrupt Mask</description>
8388 <description>SETUP Phase Done Mask (SetUPMsk)</description>
8394 <description>Mask SETUP Phase Done Interrupt</description>
8399 <description>No SETUP Phase Done Interrupt Mask</description>
8406 … <description>OUT Token Received when Endpoint Disabled Mask (OUTTknEPdisMsk)</description>
8412 … <description>Mask OUT Token Received when Endpoint Disabled Interrupt</description>
8417 … <description>No OUT Token Received when Endpoint Disabled Interrupt Mask</description>
8424 <description>Status Phase Received Mask (StsPhseRcvdMsk)</description>
8430 <description>Status Phase Received Mask</description>
8435 <description>No Status Phase Received Mask</description>
8442 <description>Back-to-Back SETUP Packets Received Mask (Back2BackSETup)</description>
8448 <description>Mask Back-to-Back SETUP Packets Received Interrupt</description>
8453 <description>No Back-to-Back SETUP Packets Received Interrupt Mask</description>
8460 <description>OUT Packet Error Mask (OutPktErrMsk)</description>
8466 <description>Mask OUT Packet Error Interrupt</description>
8471 <description>No OUT Packet Error Interrupt Mask</description>
8478 <description>Babble Error interrupt Mask (BbleErrMsk)</description>
8484 <description>Mask Babble Error Interrupt</description>
8489 <description>No Babble Error Interrupt Mask</description>
8496 <description>NAK interrupt Mask (NAKMsk)</description>
8502 <description>Mask NAK Interrupt</description>
8507 <description>No NAK Interrupt Mask</description>
8514 <description>NYET interrupt Mask (NYETMsk)</description>
8520 <description>Mask NYET Interrupt</description>
8525 <description>No NYET Interrupt Mask</description>
8534 <description>Device All Endpoints Interrupt Register</description>
8542 <description>IN Endpoint 0 Interrupt Bit</description>
8549 <description>No Interrupt</description>
8554 <description>Interrupt is active for IN EP0</description>
8561 <description>IN Endpoint 1 Interrupt Bit</description>
8568 <description>No Interrupt</description>
8573 <description>Interrupt is active for the IN EP</description>
8580 <description>IN Endpoint 2 Interrupt Bit</description>
8587 <description>No Interrupt</description>
8592 <description>Interrupt is active for the IN EP</description>
8599 <description>IN Endpoint 3 Interrupt Bit</description>
8606 <description>No Interrupt</description>
8611 <description>Interrupt is active for the IN EP</description>
8618 <description>IN Endpoint 4 Interrupt Bit</description>
8625 <description>No Interrupt</description>
8630 <description>Interrupt is active for the IN EP</description>
8637 <description>IN Endpoint 5 Interrupt Bit</description>
8644 <description>No Interrupt</description>
8649 <description>Interrupt is active for the IN EP</description>
8656 <description>IN Endpoint 6 Interrupt Bit</description>
8663 <description>No Interrupt</description>
8668 <description>Interrupt is active for the IN EP</description>
8675 <description>IN Endpoint 7 Interrupt Bit</description>
8682 <description>No Interrupt</description>
8687 <description>Interrupt is active for the IN EP</description>
8694 <description>IN Endpoint 8 Interrupt Bit</description>
8701 <description>No Interrupt</description>
8706 <description>Interrupt is active for the IN EP</description>
8713 <description>IN Endpoint 9 Interrupt Bit</description>
8720 <description>No Interrupt</description>
8725 <description>Interrupt is active for the IN EP</description>
8732 <description>IN Endpoint 10 Interrupt Bit</description>
8739 <description>No Interrupt</description>
8744 <description>Interrupt is active for the IN EP</description>
8751 <description>IN Endpoint 11 Interrupt Bit</description>
8758 <description>No Interrupt</description>
8763 <description>Interrupt is active for the IN EP</description>
8770 <description>OUT Endpoint 0 Interrupt Bit</description>
8777 <description>No Interrupt</description>
8782 <description>Interrupt is active for OUT EP0</description>
8789 <description>OUT Endpoint 1 Interrupt Bit</description>
8796 <description>No Interrupt</description>
8801 <description>Interrupt is active for the OUT EP</description>
8808 <description>OUT Endpoint 2 Interrupt Bit</description>
8815 <description>No Interrupt</description>
8820 <description>Interrupt is active for the OUT EP</description>
8827 <description>OUT Endpoint 3 Interrupt Bit</description>
8834 <description>No Interrupt</description>
8839 <description>Interrupt is active for the OUT EP</description>
8846 <description>OUT Endpoint 4 Interrupt Bit</description>
8853 <description>No Interrupt</description>
8858 <description>Interrupt is active for the OUT EP</description>
8865 <description>OUT Endpoint 5 Interrupt Bit</description>
8872 <description>No Interrupt</description>
8877 <description>Interrupt is active for the OUT EP</description>
8884 <description>OUT Endpoint 12 Interrupt Bit</description>
8891 <description>No Interrupt</description>
8896 <description>Interrupt is active for the OUT EP</description>
8903 <description>OUT Endpoint 13 Interrupt Bit</description>
8910 <description>No Interrupt</description>
8915 <description>Interrupt is active for the OUT EP</description>
8922 <description>OUT Endpoint 14 Interrupt Bit</description>
8929 <description>No Interrupt</description>
8934 <description>Interrupt is active for the OUT EP</description>
8941 <description>OUT Endpoint 15 Interrupt Bit</description>
8948 <description>No Interrupt</description>
8953 <description>Interrupt is active for the OUT EP</description>
8962 <description>Device All Endpoints Interrupt Mask Register</description>
8970 <description>IN Endpoint 0 Interrupt mask Bit</description>
8976 <description>Mask IN Endpoint 0 Interrupt</description>
8981 <description>No Interrupt mask</description>
8988 <description>IN Endpoint 1 Interrupt mask Bit</description>
8994 <description>Mask IN Endpoint Interrupt</description>
8999 <description>No Interrupt mask</description>
9006 <description>IN Endpoint 2 Interrupt mask Bit</description>
9012 <description>Mask IN Endpoint Interrupt</description>
9017 <description>No Interrupt mask</description>
9024 <description>IN Endpoint 3 Interrupt mask Bit</description>
9030 <description>Mask IN Endpoint Interrupt</description>
9035 <description>No Interrupt mask</description>
9042 <description>IN Endpoint 4 Interrupt mask Bit</description>
9048 <description>Mask IN Endpoint Interrupt</description>
9053 <description>No Interrupt mask</description>
9060 <description>IN Endpoint 5 Interrupt mask Bit</description>
9066 <description>Mask IN Endpoint Interrupt</description>
9071 <description>No Interrupt mask</description>
9078 <description>IN Endpoint 6 Interrupt mask Bit</description>
9084 <description>Mask IN Endpoint Interrupt</description>
9089 <description>No Interrupt mask</description>
9096 <description>IN Endpoint 7 Interrupt mask Bit</description>
9102 <description>Mask IN Endpoint Interrupt</description>
9107 <description>No Interrupt mask</description>
9114 <description>IN Endpoint 8 Interrupt mask Bit</description>
9120 <description>Mask IN Endpoint Interrupt</description>
9125 <description>No Interrupt mask</description>
9132 <description>IN Endpoint 9 Interrupt mask Bit</description>
9138 <description>Mask IN Endpoint Interrupt</description>
9143 <description>No Interrupt mask</description>
9150 <description>IN Endpoint 10 Interrupt mask Bit</description>
9156 <description>Mask IN Endpoint Interrupt</description>
9161 <description>No Interrupt mask</description>
9168 <description>IN Endpoint 11 Interrupt mask Bit</description>
9174 <description>Mask IN Endpoint Interrupt</description>
9179 <description>No Interrupt mask</description>
9186 <description>OUT Endpoint 0 Interrupt mask Bit</description>
9192 <description>Mask OUT Endpoint 0 Interrupt</description>
9197 <description>No Interrupt mask</description>
9204 <description>OUT Endpoint 1 Interrupt mask Bit</description>
9210 <description>Mask OUT Endpoint Interrupt</description>
9215 <description>No Interrupt mask</description>
9222 <description>OUT Endpoint 2 Interrupt mask Bit</description>
9228 <description>Mask OUT Endpoint Interrupt</description>
9233 <description>No Interrupt mask</description>
9240 <description>OUT Endpoint 3 Interrupt mask Bit</description>
9246 <description>Mask OUT Endpoint Interrupt</description>
9251 <description>No Interrupt mask</description>
9258 <description>OUT Endpoint 4 Interrupt mask Bit</description>
9264 <description>Mask OUT Endpoint Interrupt</description>
9269 <description>No Interrupt mask</description>
9276 <description>OUT Endpoint 5 Interrupt mask Bit</description>
9282 <description>Mask OUT Endpoint Interrupt</description>
9287 <description>No Interrupt mask</description>
9294 <description>OUT Endpoint 12 Interrupt mask Bit</description>
9300 <description>Mask OUT Endpoint Interrupt</description>
9305 <description>No Interrupt mask</description>
9312 <description>OUT Endpoint 13 Interrupt mask Bit</description>
9318 <description>Mask OUT Endpoint Interrupt</description>
9323 <description>No Interrupt mask</description>
9330 <description>OUT Endpoint 14 Interrupt mask Bit</description>
9336 <description>Mask OUT Endpoint Interrupt</description>
9341 <description>No Interrupt mask</description>
9348 <description>OUT Endpoint 15 Interrupt mask Bit</description>
9354 <description>Mask OUT Endpoint Interrupt</description>
9359 <description>No Interrupt mask</description>
9368 <description>Device VBUS Discharge Time Register</description>
9376 <description>Device VBUS Discharge Time (DVBUSDis)</description>
9384 <description>Device VBUS Pulsing Time Register</description>
9392 <description>Device VBUS Pulsing Time (DVBUSPulse)</description>
9400 <description>Device Threshold Control Register</description>
9408 <description>Non-ISO IN Endpoints Threshold Enable. (NonISOThrEn)</description>
9414 <description>No thresholding</description>
9419 <description>Enable thresholding for non-isochronous IN endpoints</description>
9431 <description>No thresholding</description>
9436 <description>Enables thresholding for isochronous IN endpoints</description>
9443 <description>Transmit Threshold Length (TxThrLen)</description>
9449 <description>AHB Threshold Ratio (AHBThrRatio)</description>
9455 <description>AHB threshold = MAC threshold</description>
9460 <description>AHB threshold = MAC threshold /2</description>
9465 <description>AHB threshold = MAC threshold /4</description>
9470 <description>AHB threshold = MAC threshold /8</description>
9477 <description>Receive Threshold Enable (RxThrEn)</description>
9483 <description>Disable thresholding</description>
9488 <description>Enable thresholding in the receive direction</description>
9495 <description>Receive Threshold Length (RxThrLen)</description>
9501 <description>Arbiter Parking Enable (ArbPrkEn)</description>
9507 <description>Disable DMA arbiter parking</description>
9512 <description>Enable DMA arbiter parking for IN endpoints</description>
9521 <description>Device IN Endpoint FIFO Empty Interrupt Mask Register</description>
9529 <description>IN EP Tx FIFO Empty Interrupt Mask Bits (InEpTxfEmpMsk)</description>
9535 <description>Mask IN EP0 Tx FIFO Empty Interrupt</description>
9540 <description>Mask IN EP1 Tx FIFO Empty Interrupt</description>
9545 <description>Mask IN EP2 Tx FIFO Empty Interrupt</description>
9550 <description>Mask IN EP3 Tx FIFO Empty Interrupt</description>
9555 <description>Mask IN EP4 Tx FIFO Empty Interrupt</description>
9560 <description>Mask IN EP5 Tx FIFO Empty Interrupt</description>
9565 <description>Mask IN EP6 Tx FIFO Empty Interrupt</description>
9570 <description>Mask IN EP7 Tx FIFO Empty Interrupt</description>
9575 <description>Mask IN EP8 Tx FIFO Empty Interrupt</description>
9580 <description>Mask IN EP9 Tx FIFO Empty Interrupt</description>
9585 <description>Mask IN EP10 Tx FIFO Empty Interrupt</description>
9590 <description>Mask IN EP11 Tx FIFO Empty Interrupt</description>
9595 <description>Mask IN EP12 Tx FIFO Empty Interrupt</description>
9600 <description>Mask IN EP13 Tx FIFO Empty Interrupt</description>
9605 <description>Mask IN EP14 Tx FIFO Empty Interrupt</description>
9610 <description>Mask IN EP15 Tx FIFO Empty Interrupt</description>
9619 <description>Device Control IN Endpoint 0 Control Register</description>
9627 <description>Maximum Packet Size (MPS)</description>
9633 <description>64 bytes</description>
9638 <description>32 bytes</description>
9643 <description>16 bytes</description>
9648 <description>8 bytes</description>
9655 <description>USB Active Endpoint (USBActEP)</description>
9662 <description>Control endpoint is always active</description>
9669 <description>NAK Status (NAKSts)</description>
9676 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
9681 … <description>The core is transmitting NAK handshakes on this endpoint</description>
9688 <description>Endpoint Type (EPType)</description>
9695 <description>Endpoint Control 0</description>
9702 <description>STALL Handshake (Stall)</description>
9708 <description>No Stall</description>
9713 <description>Stall Handshake</description>
9720 <description>TxFIFO Number (TxFNum)</description>
9726 <description>Tx FIFO 0</description>
9731 <description>Tx FIFO 1</description>
9736 <description>Tx FIFO 2</description>
9741 <description>Tx FIFO 3</description>
9746 <description>Tx FIFO 4</description>
9751 <description>Tx FIFO 5</description>
9756 <description>Tx FIFO 6</description>
9761 <description>Tx FIFO 7</description>
9766 <description>Tx FIFO 8</description>
9771 <description>Tx FIFO 9</description>
9776 <description>Tx FIFO 10</description>
9781 <description>Tx FIFO 11</description>
9786 <description>Tx FIFO 12</description>
9791 <description>Tx FIFO 13</description>
9796 <description>Tx FIFO 14</description>
9801 <description>Tx FIFO 15</description>
9814 <description>No action</description>
9819 <description>Clear NAK</description>
9832 <description>No action</description>
9837 <description>Set NAK</description>
9844 <description>Endpoint Disable (EPDis)</description>
9850 <description>No action</description>
9855 <description>Disabled Endpoint</description>
9862 <description>Endpoint Enable (EPEna)</description>
9868 <description>No action</description>
9873 <description>Enable Endpoint</description>
9882 <description>Device IN Endpoint 0 Interrupt Register</description>
9890 <description>Transfer Completed Interrupt (XferCompl)</description>
9896 <description>No Transfer Complete Interrupt</description>
9901 <description>Transfer Completed Interrupt</description>
9908 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
9914 <description>No Endpoint Disabled Interrupt</description>
9919 <description>Endpoint Disabled Interrupt</description>
9926 <description>AHB Error (AHBErr)</description>
9932 <description>No AHB Error Interrupt</description>
9937 <description>AHB Error interrupt</description>
9944 <description>Timeout Condition (TimeOUT)</description>
9950 <description>No Timeout interrupt</description>
9955 <description>Timeout interrupt</description>
9962 <description>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</description>
9968 <description>No IN Token Received when TxFIFO Empty interrupt</description>
9973 <description>IN Token Received when TxFIFO Empty Interrupt</description>
9980 <description>IN Token Received with EP Mismatch (INTknEPMis)</description>
9986 <description>No IN Token Received with EP Mismatch interrupt</description>
9991 <description>IN Token Received with EP Mismatch interrupt</description>
9998 <description>IN Endpoint NAK Effective (INEPNakEff)</description>
10004 <description>No IN Endpoint NAK Effective interrupt</description>
10009 <description>IN Endpoint NAK Effective interrupt</description>
10016 <description>Transmit FIFO Empty (TxFEmp)</description>
10023 <description>No Transmit FIFO Empty interrupt</description>
10028 <description>Transmit FIFO Empty interrupt</description>
10035 <description>Fifo Underrun (TxfifoUndrn)</description>
10041 <description>No Fifo Underrun interrupt</description>
10046 <description>Fifo Underrun interrupt</description>
10053 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
10059 <description>No BNA interrupt</description>
10064 <description>BNA interrupt</description>
10071 <description>Packet Drop Status (PktDrpSts)</description>
10077 <description>No interrupt</description>
10082 <description>Packet Drop Status</description>
10089 <description>NAK Interrupt (BbleErr)</description>
10095 <description>No interrupt</description>
10100 <description>BbleErr interrupt</description>
10107 <description>NAK Interrupt (NAKInterrupt)</description>
10113 <description>No interrupt</description>
10118 <description>NAK Interrupt</description>
10125 <description>NYET Interrupt (NYETIntrpt)</description>
10131 <description>No interrupt</description>
10136 <description>NYET Interrupt</description>
10145 <description>Device IN Endpoint 0 Transfer Size Register</description>
10153 <description>Transfer Size (XferSize)</description>
10159 <description>Packet Count (PktCnt)</description>
10167 <description>Device IN Endpoint 0 DMA Address Register</description>
10175 <description>DMAAddr</description>
10183 <description>Device IN Endpoint Transmit FIFO Status Register 0</description>
10191 <description>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</description>
10200 <description>Device Control IN Endpoint Control Register</description>
10208 <description>Maximum Packet Size (MPS)</description>
10214 <description>USB Active Endpoint (USBActEP)</description>
10220 <description>Not Active</description>
10225 <description>USB Active Endpoint</description>
10238 <description>DATA0 or Even Frame</description>
10243 <description>DATA1 or Odd Frame</description>
10250 <description>NAK Status (NAKSts)</description>
10257 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
10262 … <description>The core is transmitting NAK handshakes on this endpoint</description>
10269 <description>Endpoint Type (EPType)</description>
10275 <description>Control</description>
10280 <description>Isochronous</description>
10285 <description>Bulk</description>
10290 <description>Interrupt</description>
10297 <description>STALL Handshake (Stall)</description>
10303 <description>STALL All non-active tokens</description>
10308 <description>STALL All Active Tokens</description>
10315 <description>TxFIFO Number (TxFNum)</description>
10321 <description>Tx FIFO 0</description>
10326 <description>Tx FIFO 1</description>
10331 <description>Tx FIFO 2</description>
10336 <description>Tx FIFO 3</description>
10341 <description>Tx FIFO 4</description>
10346 <description>Tx FIFO 5</description>
10351 <description>Tx FIFO 6</description>
10356 <description>Tx FIFO 7</description>
10361 <description>Tx FIFO 8</description>
10366 <description>Tx FIFO 9</description>
10371 <description>Tx FIFO 10</description>
10376 <description>Tx FIFO 11</description>
10381 <description>Tx FIFO 12</description>
10386 <description>Tx FIFO 13</description>
10391 <description>Tx FIFO 14</description>
10396 <description>Tx FIFO 15</description>
10403 <description>Clear NAK (CNAK)</description>
10410 <description>No Clear NAK</description>
10415 <description>Clear NAK</description>
10422 <description>Set NAK (SNAK)</description>
10429 <description>No Set NAK</description>
10434 <description>Set NAK</description>
10441 <description>Set DATA0 PID (SetD0PID)</description>
10448 … <description>Disables Set DATA0 PID or Do not force Even (micro)Frame</description>
10453 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame</descript…
10460 <description>Set DATA1 PID (SetD1PID)</description>
10467 … <description>Disables Set DATA1 PID or Do not force Odd (micro)Frame</description>
10472 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame</descripti…
10479 <description>Endpoint Disable (EPDis)</description>
10485 <description>No Action</description>
10490 <description>Disable Endpoint</description>
10497 <description>Endpoint Enable (EPEna)</description>
10503 <description>No Action</description>
10508 <description>Enable Endpoint</description>
10517 <description>Device IN Endpoint Interrupt Register</description>
10525 <description>Transfer Completed Interrupt (XferCompl)</description>
10531 <description>No Transfer Complete Interrupt</description>
10536 <description>Transfer Complete Interrupt</description>
10543 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
10549 <description>No Endpoint Disabled Interrupt</description>
10554 <description>Endpoint Disabled Interrupt</description>
10561 <description>AHB Error (AHBErr)</description>
10567 <description>No AHB Error Interrupt</description>
10572 <description>AHB Error interrupt</description>
10579 <description>Timeout Condition (TimeOUT)</description>
10585 <description>No Timeout interrupt</description>
10590 <description>Timeout interrupt</description>
10597 <description>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</description>
10603 <description>No IN Token Received interrupt</description>
10608 <description>IN Token Received Interrupt</description>
10615 <description>IN Token Received with EP Mismatch (INTknEPMis)</description>
10621 <description>No IN Token Received with EP Mismatch interrupt</description>
10626 <description>IN Token Received with EP Mismatch interrupt</description>
10633 <description>IN Endpoint NAK Effective (INEPNakEff)</description>
10639 <description>No Endpoint NAK Effective interrupt</description>
10644 <description>IN Endpoint NAK Effective interrupt</description>
10651 <description>Transmit FIFO Empty (TxFEmp)</description>
10658 <description>No Transmit FIFO Empty interrupt</description>
10663 <description>Transmit FIFO Empty interrupt</description>
10670 <description>Fifo Underrun (TxfifoUndrn)</description>
10676 <description>No Tx FIFO Underrun interrupt</description>
10681 <description>TxFIFO Underrun interrupt</description>
10688 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
10694 <description>No BNA interrupt</description>
10699 <description>BNA interrupt</description>
10706 <description>Packet Drop Status (PktDrpSts)</description>
10712 <description>No interrupt</description>
10717 <description>Packet Drop Status interrupt</description>
10724 <description>NAK Interrupt (BbleErr)</description>
10730 <description>No interrupt</description>
10735 <description>BbleErr interrupt</description>
10742 <description>NAK Interrupt (NAKInterrupt)</description>
10748 <description>No NAK interrupt</description>
10753 <description>NAK Interrupt</description>
10760 <description>NYET Interrupt (NYETIntrpt)</description>
10766 <description>No NYET interrupt</description>
10771 <description>NYET Interrupt</description>
10780 <description>Device IN Endpoint Transfer Size Register</description>
10788 <description>Transfer Size (XferSize)</description>
10794 <description>Packet Count (PktCnt)</description>
10800 <description>MC</description>
10806 <description>1 packet</description>
10811 <description>2 packets</description>
10816 <description>3 packets</description>
10825 <description>Device IN Endpoint DMA Address Register</description>
10833 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
10841 <description>Device IN Endpoint Transmit FIFO Status Register</description>
10849 <description>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</description>
10858 <description>Device Control IN Endpoint Control Register</description>
10866 <description>Maximum Packet Size (MPS)</description>
10872 <description>USB Active Endpoint (USBActEP)</description>
10878 <description>Not Active</description>
10883 <description>USB Active Endpoint</description>
10896 <description>DATA0 or Even Frame</description>
10901 <description>DATA1 or Odd Frame</description>
10908 <description>NAK Status (NAKSts)</description>
10915 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
10920 … <description>The core is transmitting NAK handshakes on this endpoint</description>
10927 <description>Endpoint Type (EPType)</description>
10933 <description>Control</description>
10938 <description>Isochronous</description>
10943 <description>Bulk</description>
10948 <description>Interrupt</description>
10955 <description>STALL Handshake (Stall)</description>
10961 <description>STALL All non-active tokens</description>
10966 <description>STALL All Active Tokens</description>
10973 <description>TxFIFO Number (TxFNum)</description>
10979 <description>Tx FIFO 0</description>
10984 <description>Tx FIFO 1</description>
10989 <description>Tx FIFO 2</description>
10994 <description>Tx FIFO 3</description>
10999 <description>Tx FIFO 4</description>
11004 <description>Tx FIFO 5</description>
11009 <description>Tx FIFO 6</description>
11014 <description>Tx FIFO 7</description>
11019 <description>Tx FIFO 8</description>
11024 <description>Tx FIFO 9</description>
11029 <description>Tx FIFO 10</description>
11034 <description>Tx FIFO 11</description>
11039 <description>Tx FIFO 12</description>
11044 <description>Tx FIFO 13</description>
11049 <description>Tx FIFO 14</description>
11054 <description>Tx FIFO 15</description>
11061 <description>Clear NAK (CNAK)</description>
11068 <description>No Clear NAK</description>
11073 <description>Clear NAK</description>
11080 <description>Set NAK (SNAK)</description>
11087 <description>No Set NAK</description>
11092 <description>Set NAK</description>
11099 <description>Set DATA0 PID (SetD0PID)</description>
11106 … <description>Disables Set DATA0 PID or Do not force Even (micro)Frame</description>
11111 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame</descript…
11118 <description>Set DATA1 PID (SetD1PID)</description>
11125 … <description>Disables Set DATA1 PID or Do not force Odd (micro)Frame</description>
11130 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame</descripti…
11137 <description>Endpoint Disable (EPDis)</description>
11143 <description>No Action</description>
11148 <description>Disable Endpoint</description>
11155 <description>Endpoint Enable (EPEna)</description>
11161 <description>No Action</description>
11166 <description>Enable Endpoint</description>
11175 <description>Device IN Endpoint Interrupt Register</description>
11183 <description>Transfer Completed Interrupt (XferCompl)</description>
11189 <description>No Transfer Complete Interrupt</description>
11194 <description>Transfer Complete Interrupt</description>
11201 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
11207 <description>No Endpoint Disabled Interrupt</description>
11212 <description>Endpoint Disabled Interrupt</description>
11219 <description>AHB Error (AHBErr)</description>
11225 <description>No AHB Error Interrupt</description>
11230 <description>AHB Error interrupt</description>
11237 <description>Timeout Condition (TimeOUT)</description>
11243 <description>No Timeout interrupt</description>
11248 <description>Timeout interrupt</description>
11255 <description>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</description>
11261 <description>No IN Token Received interrupt</description>
11266 <description>IN Token Received Interrupt</description>
11273 <description>IN Token Received with EP Mismatch (INTknEPMis)</description>
11279 <description>No IN Token Received with EP Mismatch interrupt</description>
11284 <description>IN Token Received with EP Mismatch interrupt</description>
11291 <description>IN Endpoint NAK Effective (INEPNakEff)</description>
11297 <description>No Endpoint NAK Effective interrupt</description>
11302 <description>IN Endpoint NAK Effective interrupt</description>
11309 <description>Transmit FIFO Empty (TxFEmp)</description>
11316 <description>No Transmit FIFO Empty interrupt</description>
11321 <description>Transmit FIFO Empty interrupt</description>
11328 <description>Fifo Underrun (TxfifoUndrn)</description>
11334 <description>No Tx FIFO Underrun interrupt</description>
11339 <description>TxFIFO Underrun interrupt</description>
11346 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
11352 <description>No BNA interrupt</description>
11357 <description>BNA interrupt</description>
11364 <description>Packet Drop Status (PktDrpSts)</description>
11370 <description>No interrupt</description>
11375 <description>Packet Drop Status interrupt</description>
11382 <description>NAK Interrupt (BbleErr)</description>
11388 <description>No interrupt</description>
11393 <description>BbleErr interrupt</description>
11400 <description>NAK Interrupt (NAKInterrupt)</description>
11406 <description>No NAK interrupt</description>
11411 <description>NAK Interrupt</description>
11418 <description>NYET Interrupt (NYETIntrpt)</description>
11424 <description>No NYET interrupt</description>
11429 <description>NYET Interrupt</description>
11438 <description>Device IN Endpoint Transfer Size Register</description>
11446 <description>Transfer Size (XferSize)</description>
11452 <description>Packet Count (PktCnt)</description>
11458 <description>MC</description>
11464 <description>1 packet</description>
11469 <description>2 packets</description>
11474 <description>3 packets</description>
11483 <description>Device IN Endpoint DMA Address Register</description>
11491 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
11499 <description>Device IN Endpoint Transmit FIFO Status Register</description>
11507 <description>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</description>
11516 <description>Device Control IN Endpoint Control Register</description>
11524 <description>Maximum Packet Size (MPS)</description>
11530 <description>USB Active Endpoint (USBActEP)</description>
11536 <description>Not Active</description>
11541 <description>USB Active Endpoint</description>
11554 <description>DATA0 or Even Frame</description>
11559 <description>DATA1 or Odd Frame</description>
11566 <description>NAK Status (NAKSts)</description>
11573 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
11578 … <description>The core is transmitting NAK handshakes on this endpoint</description>
11585 <description>Endpoint Type (EPType)</description>
11591 <description>Control</description>
11596 <description>Isochronous</description>
11601 <description>Bulk</description>
11606 <description>Interrupt</description>
11613 <description>STALL Handshake (Stall)</description>
11619 <description>STALL All non-active tokens</description>
11624 <description>STALL All Active Tokens</description>
11631 <description>TxFIFO Number (TxFNum)</description>
11637 <description>Tx FIFO 0</description>
11642 <description>Tx FIFO 1</description>
11647 <description>Tx FIFO 2</description>
11652 <description>Tx FIFO 3</description>
11657 <description>Tx FIFO 4</description>
11662 <description>Tx FIFO 5</description>
11667 <description>Tx FIFO 6</description>
11672 <description>Tx FIFO 7</description>
11677 <description>Tx FIFO 8</description>
11682 <description>Tx FIFO 9</description>
11687 <description>Tx FIFO 10</description>
11692 <description>Tx FIFO 11</description>
11697 <description>Tx FIFO 12</description>
11702 <description>Tx FIFO 13</description>
11707 <description>Tx FIFO 14</description>
11712 <description>Tx FIFO 15</description>
11719 <description>Clear NAK (CNAK)</description>
11726 <description>No Clear NAK</description>
11731 <description>Clear NAK</description>
11738 <description>Set NAK (SNAK)</description>
11745 <description>No Set NAK</description>
11750 <description>Set NAK</description>
11757 <description>Set DATA0 PID (SetD0PID)</description>
11764 … <description>Disables Set DATA0 PID or Do not force Even (micro)Frame</description>
11769 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame</descript…
11776 <description>Set DATA1 PID (SetD1PID)</description>
11783 … <description>Disables Set DATA1 PID or Do not force Odd (micro)Frame</description>
11788 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame</descripti…
11795 <description>Endpoint Disable (EPDis)</description>
11801 <description>No Action</description>
11806 <description>Disable Endpoint</description>
11813 <description>Endpoint Enable (EPEna)</description>
11819 <description>No Action</description>
11824 <description>Enable Endpoint</description>
11833 <description>Device IN Endpoint Interrupt Register</description>
11841 <description>Transfer Completed Interrupt (XferCompl)</description>
11847 <description>No Transfer Complete Interrupt</description>
11852 <description>Transfer Complete Interrupt</description>
11859 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
11865 <description>No Endpoint Disabled Interrupt</description>
11870 <description>Endpoint Disabled Interrupt</description>
11877 <description>AHB Error (AHBErr)</description>
11883 <description>No AHB Error Interrupt</description>
11888 <description>AHB Error interrupt</description>
11895 <description>Timeout Condition (TimeOUT)</description>
11901 <description>No Timeout interrupt</description>
11906 <description>Timeout interrupt</description>
11913 <description>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</description>
11919 <description>No IN Token Received interrupt</description>
11924 <description>IN Token Received Interrupt</description>
11931 <description>IN Token Received with EP Mismatch (INTknEPMis)</description>
11937 <description>No IN Token Received with EP Mismatch interrupt</description>
11942 <description>IN Token Received with EP Mismatch interrupt</description>
11949 <description>IN Endpoint NAK Effective (INEPNakEff)</description>
11955 <description>No Endpoint NAK Effective interrupt</description>
11960 <description>IN Endpoint NAK Effective interrupt</description>
11967 <description>Transmit FIFO Empty (TxFEmp)</description>
11974 <description>No Transmit FIFO Empty interrupt</description>
11979 <description>Transmit FIFO Empty interrupt</description>
11986 <description>Fifo Underrun (TxfifoUndrn)</description>
11992 <description>No Tx FIFO Underrun interrupt</description>
11997 <description>TxFIFO Underrun interrupt</description>
12004 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
12010 <description>No BNA interrupt</description>
12015 <description>BNA interrupt</description>
12022 <description>Packet Drop Status (PktDrpSts)</description>
12028 <description>No interrupt</description>
12033 <description>Packet Drop Status interrupt</description>
12040 <description>NAK Interrupt (BbleErr)</description>
12046 <description>No interrupt</description>
12051 <description>BbleErr interrupt</description>
12058 <description>NAK Interrupt (NAKInterrupt)</description>
12064 <description>No NAK interrupt</description>
12069 <description>NAK Interrupt</description>
12076 <description>NYET Interrupt (NYETIntrpt)</description>
12082 <description>No NYET interrupt</description>
12087 <description>NYET Interrupt</description>
12096 <description>Device IN Endpoint Transfer Size Register</description>
12104 <description>Transfer Size (XferSize)</description>
12110 <description>Packet Count (PktCnt)</description>
12116 <description>MC</description>
12122 <description>1 packet</description>
12127 <description>2 packets</description>
12132 <description>3 packets</description>
12141 <description>Device IN Endpoint DMA Address Register</description>
12149 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
12157 <description>Device IN Endpoint Transmit FIFO Status Register</description>
12165 <description>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</description>
12174 <description>Device Control IN Endpoint Control Register</description>
12182 <description>Maximum Packet Size (MPS)</description>
12188 <description>USB Active Endpoint (USBActEP)</description>
12194 <description>Not Active</description>
12199 <description>USB Active Endpoint</description>
12212 <description>DATA0 or Even Frame</description>
12217 <description>DATA1 or Odd Frame</description>
12224 <description>NAK Status (NAKSts)</description>
12231 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
12236 … <description>The core is transmitting NAK handshakes on this endpoint</description>
12243 <description>Endpoint Type (EPType)</description>
12249 <description>Control</description>
12254 <description>Isochronous</description>
12259 <description>Bulk</description>
12264 <description>Interrupt</description>
12271 <description>STALL Handshake (Stall)</description>
12277 <description>STALL All non-active tokens</description>
12282 <description>STALL All Active Tokens</description>
12289 <description>TxFIFO Number (TxFNum)</description>
12295 <description>Tx FIFO 0</description>
12300 <description>Tx FIFO 1</description>
12305 <description>Tx FIFO 2</description>
12310 <description>Tx FIFO 3</description>
12315 <description>Tx FIFO 4</description>
12320 <description>Tx FIFO 5</description>
12325 <description>Tx FIFO 6</description>
12330 <description>Tx FIFO 7</description>
12335 <description>Tx FIFO 8</description>
12340 <description>Tx FIFO 9</description>
12345 <description>Tx FIFO 10</description>
12350 <description>Tx FIFO 11</description>
12355 <description>Tx FIFO 12</description>
12360 <description>Tx FIFO 13</description>
12365 <description>Tx FIFO 14</description>
12370 <description>Tx FIFO 15</description>
12377 <description>Clear NAK (CNAK)</description>
12384 <description>No Clear NAK</description>
12389 <description>Clear NAK</description>
12396 <description>Set NAK (SNAK)</description>
12403 <description>No Set NAK</description>
12408 <description>Set NAK</description>
12415 <description>Set DATA0 PID (SetD0PID)</description>
12422 … <description>Disables Set DATA0 PID or Do not force Even (micro)Frame</description>
12427 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame</descript…
12434 <description>Set DATA1 PID (SetD1PID)</description>
12441 … <description>Disables Set DATA1 PID or Do not force Odd (micro)Frame</description>
12446 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame</descripti…
12453 <description>Endpoint Disable (EPDis)</description>
12459 <description>No Action</description>
12464 <description>Disable Endpoint</description>
12471 <description>Endpoint Enable (EPEna)</description>
12477 <description>No Action</description>
12482 <description>Enable Endpoint</description>
12491 <description>Device IN Endpoint Interrupt Register</description>
12499 <description>Transfer Completed Interrupt (XferCompl)</description>
12505 <description>No Transfer Complete Interrupt</description>
12510 <description>Transfer Complete Interrupt</description>
12517 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
12523 <description>No Endpoint Disabled Interrupt</description>
12528 <description>Endpoint Disabled Interrupt</description>
12535 <description>AHB Error (AHBErr)</description>
12541 <description>No AHB Error Interrupt</description>
12546 <description>AHB Error interrupt</description>
12553 <description>Timeout Condition (TimeOUT)</description>
12559 <description>No Timeout interrupt</description>
12564 <description>Timeout interrupt</description>
12571 <description>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</description>
12577 <description>No IN Token Received interrupt</description>
12582 <description>IN Token Received Interrupt</description>
12589 <description>IN Token Received with EP Mismatch (INTknEPMis)</description>
12595 <description>No IN Token Received with EP Mismatch interrupt</description>
12600 <description>IN Token Received with EP Mismatch interrupt</description>
12607 <description>IN Endpoint NAK Effective (INEPNakEff)</description>
12613 <description>No Endpoint NAK Effective interrupt</description>
12618 <description>IN Endpoint NAK Effective interrupt</description>
12625 <description>Transmit FIFO Empty (TxFEmp)</description>
12632 <description>No Transmit FIFO Empty interrupt</description>
12637 <description>Transmit FIFO Empty interrupt</description>
12644 <description>Fifo Underrun (TxfifoUndrn)</description>
12650 <description>No Tx FIFO Underrun interrupt</description>
12655 <description>TxFIFO Underrun interrupt</description>
12662 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
12668 <description>No BNA interrupt</description>
12673 <description>BNA interrupt</description>
12680 <description>Packet Drop Status (PktDrpSts)</description>
12686 <description>No interrupt</description>
12691 <description>Packet Drop Status interrupt</description>
12698 <description>NAK Interrupt (BbleErr)</description>
12704 <description>No interrupt</description>
12709 <description>BbleErr interrupt</description>
12716 <description>NAK Interrupt (NAKInterrupt)</description>
12722 <description>No NAK interrupt</description>
12727 <description>NAK Interrupt</description>
12734 <description>NYET Interrupt (NYETIntrpt)</description>
12740 <description>No NYET interrupt</description>
12745 <description>NYET Interrupt</description>
12754 <description>Device IN Endpoint Transfer Size Register</description>
12762 <description>Transfer Size (XferSize)</description>
12768 <description>Packet Count (PktCnt)</description>
12774 <description>MC</description>
12780 <description>1 packet</description>
12785 <description>2 packets</description>
12790 <description>3 packets</description>
12799 <description>Device IN Endpoint DMA Address Register</description>
12807 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
12815 <description>Device IN Endpoint Transmit FIFO Status Register</description>
12823 <description>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</description>
12832 <description>Device Control IN Endpoint Control Register</description>
12840 <description>Maximum Packet Size (MPS)</description>
12846 <description>USB Active Endpoint (USBActEP)</description>
12852 <description>Not Active</description>
12857 <description>USB Active Endpoint</description>
12870 <description>DATA0 or Even Frame</description>
12875 <description>DATA1 or Odd Frame</description>
12882 <description>NAK Status (NAKSts)</description>
12889 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
12894 … <description>The core is transmitting NAK handshakes on this endpoint</description>
12901 <description>Endpoint Type (EPType)</description>
12907 <description>Control</description>
12912 <description>Isochronous</description>
12917 <description>Bulk</description>
12922 <description>Interrupt</description>
12929 <description>STALL Handshake (Stall)</description>
12935 <description>STALL All non-active tokens</description>
12940 <description>STALL All Active Tokens</description>
12947 <description>TxFIFO Number (TxFNum)</description>
12953 <description>Tx FIFO 0</description>
12958 <description>Tx FIFO 1</description>
12963 <description>Tx FIFO 2</description>
12968 <description>Tx FIFO 3</description>
12973 <description>Tx FIFO 4</description>
12978 <description>Tx FIFO 5</description>
12983 <description>Tx FIFO 6</description>
12988 <description>Tx FIFO 7</description>
12993 <description>Tx FIFO 8</description>
12998 <description>Tx FIFO 9</description>
13003 <description>Tx FIFO 10</description>
13008 <description>Tx FIFO 11</description>
13013 <description>Tx FIFO 12</description>
13018 <description>Tx FIFO 13</description>
13023 <description>Tx FIFO 14</description>
13028 <description>Tx FIFO 15</description>
13035 <description>Clear NAK (CNAK)</description>
13042 <description>No Clear NAK</description>
13047 <description>Clear NAK</description>
13054 <description>Set NAK (SNAK)</description>
13061 <description>No Set NAK</description>
13066 <description>Set NAK</description>
13073 <description>Set DATA0 PID (SetD0PID)</description>
13080 … <description>Disables Set DATA0 PID or Do not force Even (micro)Frame</description>
13085 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame</descript…
13092 <description>Set DATA1 PID (SetD1PID)</description>
13099 … <description>Disables Set DATA1 PID or Do not force Odd (micro)Frame</description>
13104 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame</descripti…
13111 <description>Endpoint Disable (EPDis)</description>
13117 <description>No Action</description>
13122 <description>Disable Endpoint</description>
13129 <description>Endpoint Enable (EPEna)</description>
13135 <description>No Action</description>
13140 <description>Enable Endpoint</description>
13149 <description>Device IN Endpoint Interrupt Register</description>
13157 <description>Transfer Completed Interrupt (XferCompl)</description>
13163 <description>No Transfer Complete Interrupt</description>
13168 <description>Transfer Complete Interrupt</description>
13175 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
13181 <description>No Endpoint Disabled Interrupt</description>
13186 <description>Endpoint Disabled Interrupt</description>
13193 <description>AHB Error (AHBErr)</description>
13199 <description>No AHB Error Interrupt</description>
13204 <description>AHB Error interrupt</description>
13211 <description>Timeout Condition (TimeOUT)</description>
13217 <description>No Timeout interrupt</description>
13222 <description>Timeout interrupt</description>
13229 <description>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</description>
13235 <description>No IN Token Received interrupt</description>
13240 <description>IN Token Received Interrupt</description>
13247 <description>IN Token Received with EP Mismatch (INTknEPMis)</description>
13253 <description>No IN Token Received with EP Mismatch interrupt</description>
13258 <description>IN Token Received with EP Mismatch interrupt</description>
13265 <description>IN Endpoint NAK Effective (INEPNakEff)</description>
13271 <description>No Endpoint NAK Effective interrupt</description>
13276 <description>IN Endpoint NAK Effective interrupt</description>
13283 <description>Transmit FIFO Empty (TxFEmp)</description>
13290 <description>No Transmit FIFO Empty interrupt</description>
13295 <description>Transmit FIFO Empty interrupt</description>
13302 <description>Fifo Underrun (TxfifoUndrn)</description>
13308 <description>No Tx FIFO Underrun interrupt</description>
13313 <description>TxFIFO Underrun interrupt</description>
13320 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
13326 <description>No BNA interrupt</description>
13331 <description>BNA interrupt</description>
13338 <description>Packet Drop Status (PktDrpSts)</description>
13344 <description>No interrupt</description>
13349 <description>Packet Drop Status interrupt</description>
13356 <description>NAK Interrupt (BbleErr)</description>
13362 <description>No interrupt</description>
13367 <description>BbleErr interrupt</description>
13374 <description>NAK Interrupt (NAKInterrupt)</description>
13380 <description>No NAK interrupt</description>
13385 <description>NAK Interrupt</description>
13392 <description>NYET Interrupt (NYETIntrpt)</description>
13398 <description>No NYET interrupt</description>
13403 <description>NYET Interrupt</description>
13412 <description>Device IN Endpoint Transfer Size Register</description>
13420 <description>Transfer Size (XferSize)</description>
13426 <description>Packet Count (PktCnt)</description>
13432 <description>MC</description>
13438 <description>1 packet</description>
13443 <description>2 packets</description>
13448 <description>3 packets</description>
13457 <description>Device IN Endpoint DMA Address Register</description>
13465 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
13473 <description>Device IN Endpoint Transmit FIFO Status Register</description>
13481 <description>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</description>
13490 <description>Device Control IN Endpoint Control Register</description>
13498 <description>Maximum Packet Size (MPS)</description>
13504 <description>USB Active Endpoint (USBActEP)</description>
13510 <description>Not Active</description>
13515 <description>USB Active Endpoint</description>
13528 <description>DATA0 or Even Frame</description>
13533 <description>DATA1 or Odd Frame</description>
13540 <description>NAK Status (NAKSts)</description>
13547 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
13552 … <description>The core is transmitting NAK handshakes on this endpoint</description>
13559 <description>Endpoint Type (EPType)</description>
13565 <description>Control</description>
13570 <description>Isochronous</description>
13575 <description>Bulk</description>
13580 <description>Interrupt</description>
13587 <description>STALL Handshake (Stall)</description>
13593 <description>STALL All non-active tokens</description>
13598 <description>STALL All Active Tokens</description>
13605 <description>TxFIFO Number (TxFNum)</description>
13611 <description>Tx FIFO 0</description>
13616 <description>Tx FIFO 1</description>
13621 <description>Tx FIFO 2</description>
13626 <description>Tx FIFO 3</description>
13631 <description>Tx FIFO 4</description>
13636 <description>Tx FIFO 5</description>
13641 <description>Tx FIFO 6</description>
13646 <description>Tx FIFO 7</description>
13651 <description>Tx FIFO 8</description>
13656 <description>Tx FIFO 9</description>
13661 <description>Tx FIFO 10</description>
13666 <description>Tx FIFO 11</description>
13671 <description>Tx FIFO 12</description>
13676 <description>Tx FIFO 13</description>
13681 <description>Tx FIFO 14</description>
13686 <description>Tx FIFO 15</description>
13693 <description>Clear NAK (CNAK)</description>
13700 <description>No Clear NAK</description>
13705 <description>Clear NAK</description>
13712 <description>Set NAK (SNAK)</description>
13719 <description>No Set NAK</description>
13724 <description>Set NAK</description>
13731 <description>Set DATA0 PID (SetD0PID)</description>
13738 … <description>Disables Set DATA0 PID or Do not force Even (micro)Frame</description>
13743 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame</descript…
13750 <description>Set DATA1 PID (SetD1PID)</description>
13757 … <description>Disables Set DATA1 PID or Do not force Odd (micro)Frame</description>
13762 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame</descripti…
13769 <description>Endpoint Disable (EPDis)</description>
13775 <description>No Action</description>
13780 <description>Disable Endpoint</description>
13787 <description>Endpoint Enable (EPEna)</description>
13793 <description>No Action</description>
13798 <description>Enable Endpoint</description>
13807 <description>Device IN Endpoint Interrupt Register</description>
13815 <description>Transfer Completed Interrupt (XferCompl)</description>
13821 <description>No Transfer Complete Interrupt</description>
13826 <description>Transfer Complete Interrupt</description>
13833 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
13839 <description>No Endpoint Disabled Interrupt</description>
13844 <description>Endpoint Disabled Interrupt</description>
13851 <description>AHB Error (AHBErr)</description>
13857 <description>No AHB Error Interrupt</description>
13862 <description>AHB Error interrupt</description>
13869 <description>Timeout Condition (TimeOUT)</description>
13875 <description>No Timeout interrupt</description>
13880 <description>Timeout interrupt</description>
13887 <description>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</description>
13893 <description>No IN Token Received interrupt</description>
13898 <description>IN Token Received Interrupt</description>
13905 <description>IN Token Received with EP Mismatch (INTknEPMis)</description>
13911 <description>No IN Token Received with EP Mismatch interrupt</description>
13916 <description>IN Token Received with EP Mismatch interrupt</description>
13923 <description>IN Endpoint NAK Effective (INEPNakEff)</description>
13929 <description>No Endpoint NAK Effective interrupt</description>
13934 <description>IN Endpoint NAK Effective interrupt</description>
13941 <description>Transmit FIFO Empty (TxFEmp)</description>
13948 <description>No Transmit FIFO Empty interrupt</description>
13953 <description>Transmit FIFO Empty interrupt</description>
13960 <description>Fifo Underrun (TxfifoUndrn)</description>
13966 <description>No Tx FIFO Underrun interrupt</description>
13971 <description>TxFIFO Underrun interrupt</description>
13978 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
13984 <description>No BNA interrupt</description>
13989 <description>BNA interrupt</description>
13996 <description>Packet Drop Status (PktDrpSts)</description>
14002 <description>No interrupt</description>
14007 <description>Packet Drop Status interrupt</description>
14014 <description>NAK Interrupt (BbleErr)</description>
14020 <description>No interrupt</description>
14025 <description>BbleErr interrupt</description>
14032 <description>NAK Interrupt (NAKInterrupt)</description>
14038 <description>No NAK interrupt</description>
14043 <description>NAK Interrupt</description>
14050 <description>NYET Interrupt (NYETIntrpt)</description>
14056 <description>No NYET interrupt</description>
14061 <description>NYET Interrupt</description>
14070 <description>Device IN Endpoint Transfer Size Register</description>
14078 <description>Transfer Size (XferSize)</description>
14084 <description>Packet Count (PktCnt)</description>
14090 <description>MC</description>
14096 <description>1 packet</description>
14101 <description>2 packets</description>
14106 <description>3 packets</description>
14115 <description>Device IN Endpoint DMA Address Register</description>
14123 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
14131 <description>Device IN Endpoint Transmit FIFO Status Register</description>
14139 <description>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</description>
14148 <description>Device Control IN Endpoint Control Register</description>
14156 <description>Maximum Packet Size (MPS)</description>
14162 <description>USB Active Endpoint (USBActEP)</description>
14168 <description>Not Active</description>
14173 <description>USB Active Endpoint</description>
14186 <description>DATA0 or Even Frame</description>
14191 <description>DATA1 or Odd Frame</description>
14198 <description>NAK Status (NAKSts)</description>
14205 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
14210 … <description>The core is transmitting NAK handshakes on this endpoint</description>
14217 <description>Endpoint Type (EPType)</description>
14223 <description>Control</description>
14228 <description>Isochronous</description>
14233 <description>Bulk</description>
14238 <description>Interrupt</description>
14245 <description>STALL Handshake (Stall)</description>
14251 <description>STALL All non-active tokens</description>
14256 <description>STALL All Active Tokens</description>
14263 <description>TxFIFO Number (TxFNum)</description>
14269 <description>Tx FIFO 0</description>
14274 <description>Tx FIFO 1</description>
14279 <description>Tx FIFO 2</description>
14284 <description>Tx FIFO 3</description>
14289 <description>Tx FIFO 4</description>
14294 <description>Tx FIFO 5</description>
14299 <description>Tx FIFO 6</description>
14304 <description>Tx FIFO 7</description>
14309 <description>Tx FIFO 8</description>
14314 <description>Tx FIFO 9</description>
14319 <description>Tx FIFO 10</description>
14324 <description>Tx FIFO 11</description>
14329 <description>Tx FIFO 12</description>
14334 <description>Tx FIFO 13</description>
14339 <description>Tx FIFO 14</description>
14344 <description>Tx FIFO 15</description>
14351 <description>Clear NAK (CNAK)</description>
14358 <description>No Clear NAK</description>
14363 <description>Clear NAK</description>
14370 <description>Set NAK (SNAK)</description>
14377 <description>No Set NAK</description>
14382 <description>Set NAK</description>
14389 <description>Set DATA0 PID (SetD0PID)</description>
14396 … <description>Disables Set DATA0 PID or Do not force Even (micro)Frame</description>
14401 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame</descript…
14408 <description>Set DATA1 PID (SetD1PID)</description>
14415 … <description>Disables Set DATA1 PID or Do not force Odd (micro)Frame</description>
14420 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame</descripti…
14427 <description>Endpoint Disable (EPDis)</description>
14433 <description>No Action</description>
14438 <description>Disable Endpoint</description>
14445 <description>Endpoint Enable (EPEna)</description>
14451 <description>No Action</description>
14456 <description>Enable Endpoint</description>
14465 <description>Device IN Endpoint Interrupt Register</description>
14473 <description>Transfer Completed Interrupt (XferCompl)</description>
14479 <description>No Transfer Complete Interrupt</description>
14484 <description>Transfer Complete Interrupt</description>
14491 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
14497 <description>No Endpoint Disabled Interrupt</description>
14502 <description>Endpoint Disabled Interrupt</description>
14509 <description>AHB Error (AHBErr)</description>
14515 <description>No AHB Error Interrupt</description>
14520 <description>AHB Error interrupt</description>
14527 <description>Timeout Condition (TimeOUT)</description>
14533 <description>No Timeout interrupt</description>
14538 <description>Timeout interrupt</description>
14545 <description>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</description>
14551 <description>No IN Token Received interrupt</description>
14556 <description>IN Token Received Interrupt</description>
14563 <description>IN Token Received with EP Mismatch (INTknEPMis)</description>
14569 <description>No IN Token Received with EP Mismatch interrupt</description>
14574 <description>IN Token Received with EP Mismatch interrupt</description>
14581 <description>IN Endpoint NAK Effective (INEPNakEff)</description>
14587 <description>No Endpoint NAK Effective interrupt</description>
14592 <description>IN Endpoint NAK Effective interrupt</description>
14599 <description>Transmit FIFO Empty (TxFEmp)</description>
14606 <description>No Transmit FIFO Empty interrupt</description>
14611 <description>Transmit FIFO Empty interrupt</description>
14618 <description>Fifo Underrun (TxfifoUndrn)</description>
14624 <description>No Tx FIFO Underrun interrupt</description>
14629 <description>TxFIFO Underrun interrupt</description>
14636 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
14642 <description>No BNA interrupt</description>
14647 <description>BNA interrupt</description>
14654 <description>Packet Drop Status (PktDrpSts)</description>
14660 <description>No interrupt</description>
14665 <description>Packet Drop Status interrupt</description>
14672 <description>NAK Interrupt (BbleErr)</description>
14678 <description>No interrupt</description>
14683 <description>BbleErr interrupt</description>
14690 <description>NAK Interrupt (NAKInterrupt)</description>
14696 <description>No NAK interrupt</description>
14701 <description>NAK Interrupt</description>
14708 <description>NYET Interrupt (NYETIntrpt)</description>
14714 <description>No NYET interrupt</description>
14719 <description>NYET Interrupt</description>
14728 <description>Device IN Endpoint Transfer Size Register</description>
14736 <description>Transfer Size (XferSize)</description>
14742 <description>Packet Count (PktCnt)</description>
14748 <description>MC</description>
14754 <description>1 packet</description>
14759 <description>2 packets</description>
14764 <description>3 packets</description>
14773 <description>Device IN Endpoint DMA Address Register</description>
14781 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
14789 <description>Device IN Endpoint Transmit FIFO Status Register</description>
14797 <description>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</description>
14806 <description>Device Control IN Endpoint Control Register</description>
14814 <description>Maximum Packet Size (MPS)</description>
14820 <description>USB Active Endpoint (USBActEP)</description>
14826 <description>Not Active</description>
14831 <description>USB Active Endpoint</description>
14844 <description>DATA0 or Even Frame</description>
14849 <description>DATA1 or Odd Frame</description>
14856 <description>NAK Status (NAKSts)</description>
14863 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
14868 … <description>The core is transmitting NAK handshakes on this endpoint</description>
14875 <description>Endpoint Type (EPType)</description>
14881 <description>Control</description>
14886 <description>Isochronous</description>
14891 <description>Bulk</description>
14896 <description>Interrupt</description>
14903 <description>STALL Handshake (Stall)</description>
14909 <description>STALL All non-active tokens</description>
14914 <description>STALL All Active Tokens</description>
14921 <description>TxFIFO Number (TxFNum)</description>
14927 <description>Tx FIFO 0</description>
14932 <description>Tx FIFO 1</description>
14937 <description>Tx FIFO 2</description>
14942 <description>Tx FIFO 3</description>
14947 <description>Tx FIFO 4</description>
14952 <description>Tx FIFO 5</description>
14957 <description>Tx FIFO 6</description>
14962 <description>Tx FIFO 7</description>
14967 <description>Tx FIFO 8</description>
14972 <description>Tx FIFO 9</description>
14977 <description>Tx FIFO 10</description>
14982 <description>Tx FIFO 11</description>
14987 <description>Tx FIFO 12</description>
14992 <description>Tx FIFO 13</description>
14997 <description>Tx FIFO 14</description>
15002 <description>Tx FIFO 15</description>
15009 <description>Clear NAK (CNAK)</description>
15016 <description>No Clear NAK</description>
15021 <description>Clear NAK</description>
15028 <description>Set NAK (SNAK)</description>
15035 <description>No Set NAK</description>
15040 <description>Set NAK</description>
15047 <description>Set DATA0 PID (SetD0PID)</description>
15054 … <description>Disables Set DATA0 PID or Do not force Even (micro)Frame</description>
15059 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame</descript…
15066 <description>Set DATA1 PID (SetD1PID)</description>
15073 … <description>Disables Set DATA1 PID or Do not force Odd (micro)Frame</description>
15078 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame</descripti…
15085 <description>Endpoint Disable (EPDis)</description>
15091 <description>No Action</description>
15096 <description>Disable Endpoint</description>
15103 <description>Endpoint Enable (EPEna)</description>
15109 <description>No Action</description>
15114 <description>Enable Endpoint</description>
15123 <description>Device IN Endpoint Interrupt Register</description>
15131 <description>Transfer Completed Interrupt (XferCompl)</description>
15137 <description>No Transfer Complete Interrupt</description>
15142 <description>Transfer Complete Interrupt</description>
15149 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
15155 <description>No Endpoint Disabled Interrupt</description>
15160 <description>Endpoint Disabled Interrupt</description>
15167 <description>AHB Error (AHBErr)</description>
15173 <description>No AHB Error Interrupt</description>
15178 <description>AHB Error interrupt</description>
15185 <description>Timeout Condition (TimeOUT)</description>
15191 <description>No Timeout interrupt</description>
15196 <description>Timeout interrupt</description>
15203 <description>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</description>
15209 <description>No IN Token Received interrupt</description>
15214 <description>IN Token Received Interrupt</description>
15221 <description>IN Token Received with EP Mismatch (INTknEPMis)</description>
15227 <description>No IN Token Received with EP Mismatch interrupt</description>
15232 <description>IN Token Received with EP Mismatch interrupt</description>
15239 <description>IN Endpoint NAK Effective (INEPNakEff)</description>
15245 <description>No Endpoint NAK Effective interrupt</description>
15250 <description>IN Endpoint NAK Effective interrupt</description>
15257 <description>Transmit FIFO Empty (TxFEmp)</description>
15264 <description>No Transmit FIFO Empty interrupt</description>
15269 <description>Transmit FIFO Empty interrupt</description>
15276 <description>Fifo Underrun (TxfifoUndrn)</description>
15282 <description>No Tx FIFO Underrun interrupt</description>
15287 <description>TxFIFO Underrun interrupt</description>
15294 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
15300 <description>No BNA interrupt</description>
15305 <description>BNA interrupt</description>
15312 <description>Packet Drop Status (PktDrpSts)</description>
15318 <description>No interrupt</description>
15323 <description>Packet Drop Status interrupt</description>
15330 <description>NAK Interrupt (BbleErr)</description>
15336 <description>No interrupt</description>
15341 <description>BbleErr interrupt</description>
15348 <description>NAK Interrupt (NAKInterrupt)</description>
15354 <description>No NAK interrupt</description>
15359 <description>NAK Interrupt</description>
15366 <description>NYET Interrupt (NYETIntrpt)</description>
15372 <description>No NYET interrupt</description>
15377 <description>NYET Interrupt</description>
15386 <description>Device IN Endpoint Transfer Size Register</description>
15394 <description>Transfer Size (XferSize)</description>
15400 <description>Packet Count (PktCnt)</description>
15406 <description>MC</description>
15412 <description>1 packet</description>
15417 <description>2 packets</description>
15422 <description>3 packets</description>
15431 <description>Device IN Endpoint DMA Address Register</description>
15439 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
15447 <description>Device IN Endpoint Transmit FIFO Status Register</description>
15455 <description>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</description>
15464 <description>Device Control IN Endpoint Control Register</description>
15472 <description>Maximum Packet Size (MPS)</description>
15478 <description>USB Active Endpoint (USBActEP)</description>
15484 <description>Not Active</description>
15489 <description>USB Active Endpoint</description>
15502 <description>DATA0 or Even Frame</description>
15507 <description>DATA1 or Odd Frame</description>
15514 <description>NAK Status (NAKSts)</description>
15521 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
15526 … <description>The core is transmitting NAK handshakes on this endpoint</description>
15533 <description>Endpoint Type (EPType)</description>
15539 <description>Control</description>
15544 <description>Isochronous</description>
15549 <description>Bulk</description>
15554 <description>Interrupt</description>
15561 <description>STALL Handshake (Stall)</description>
15567 <description>STALL All non-active tokens</description>
15572 <description>STALL All Active Tokens</description>
15579 <description>TxFIFO Number (TxFNum)</description>
15585 <description>Tx FIFO 0</description>
15590 <description>Tx FIFO 1</description>
15595 <description>Tx FIFO 2</description>
15600 <description>Tx FIFO 3</description>
15605 <description>Tx FIFO 4</description>
15610 <description>Tx FIFO 5</description>
15615 <description>Tx FIFO 6</description>
15620 <description>Tx FIFO 7</description>
15625 <description>Tx FIFO 8</description>
15630 <description>Tx FIFO 9</description>
15635 <description>Tx FIFO 10</description>
15640 <description>Tx FIFO 11</description>
15645 <description>Tx FIFO 12</description>
15650 <description>Tx FIFO 13</description>
15655 <description>Tx FIFO 14</description>
15660 <description>Tx FIFO 15</description>
15667 <description>Clear NAK (CNAK)</description>
15674 <description>No Clear NAK</description>
15679 <description>Clear NAK</description>
15686 <description>Set NAK (SNAK)</description>
15693 <description>No Set NAK</description>
15698 <description>Set NAK</description>
15705 <description>Set DATA0 PID (SetD0PID)</description>
15712 … <description>Disables Set DATA0 PID or Do not force Even (micro)Frame</description>
15717 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame</descript…
15724 <description>Set DATA1 PID (SetD1PID)</description>
15731 … <description>Disables Set DATA1 PID or Do not force Odd (micro)Frame</description>
15736 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame</descripti…
15743 <description>Endpoint Disable (EPDis)</description>
15749 <description>No Action</description>
15754 <description>Disable Endpoint</description>
15761 <description>Endpoint Enable (EPEna)</description>
15767 <description>No Action</description>
15772 <description>Enable Endpoint</description>
15781 <description>Device IN Endpoint Interrupt Register</description>
15789 <description>Transfer Completed Interrupt (XferCompl)</description>
15795 <description>No Transfer Complete Interrupt</description>
15800 <description>Transfer Complete Interrupt</description>
15807 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
15813 <description>No Endpoint Disabled Interrupt</description>
15818 <description>Endpoint Disabled Interrupt</description>
15825 <description>AHB Error (AHBErr)</description>
15831 <description>No AHB Error Interrupt</description>
15836 <description>AHB Error interrupt</description>
15843 <description>Timeout Condition (TimeOUT)</description>
15849 <description>No Timeout interrupt</description>
15854 <description>Timeout interrupt</description>
15861 <description>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</description>
15867 <description>No IN Token Received interrupt</description>
15872 <description>IN Token Received Interrupt</description>
15879 <description>IN Token Received with EP Mismatch (INTknEPMis)</description>
15885 <description>No IN Token Received with EP Mismatch interrupt</description>
15890 <description>IN Token Received with EP Mismatch interrupt</description>
15897 <description>IN Endpoint NAK Effective (INEPNakEff)</description>
15903 <description>No Endpoint NAK Effective interrupt</description>
15908 <description>IN Endpoint NAK Effective interrupt</description>
15915 <description>Transmit FIFO Empty (TxFEmp)</description>
15922 <description>No Transmit FIFO Empty interrupt</description>
15927 <description>Transmit FIFO Empty interrupt</description>
15934 <description>Fifo Underrun (TxfifoUndrn)</description>
15940 <description>No Tx FIFO Underrun interrupt</description>
15945 <description>TxFIFO Underrun interrupt</description>
15952 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
15958 <description>No BNA interrupt</description>
15963 <description>BNA interrupt</description>
15970 <description>Packet Drop Status (PktDrpSts)</description>
15976 <description>No interrupt</description>
15981 <description>Packet Drop Status interrupt</description>
15988 <description>NAK Interrupt (BbleErr)</description>
15994 <description>No interrupt</description>
15999 <description>BbleErr interrupt</description>
16006 <description>NAK Interrupt (NAKInterrupt)</description>
16012 <description>No NAK interrupt</description>
16017 <description>NAK Interrupt</description>
16024 <description>NYET Interrupt (NYETIntrpt)</description>
16030 <description>No NYET interrupt</description>
16035 <description>NYET Interrupt</description>
16044 <description>Device IN Endpoint Transfer Size Register</description>
16052 <description>Transfer Size (XferSize)</description>
16058 <description>Packet Count (PktCnt)</description>
16064 <description>MC</description>
16070 <description>1 packet</description>
16075 <description>2 packets</description>
16080 <description>3 packets</description>
16089 <description>Device IN Endpoint DMA Address Register</description>
16097 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
16105 <description>Device IN Endpoint Transmit FIFO Status Register</description>
16113 <description>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</description>
16122 <description>Device Control IN Endpoint Control Register</description>
16130 <description>Maximum Packet Size (MPS)</description>
16136 <description>USB Active Endpoint (USBActEP)</description>
16142 <description>Not Active</description>
16147 <description>USB Active Endpoint</description>
16160 <description>DATA0 or Even Frame</description>
16165 <description>DATA1 or Odd Frame</description>
16172 <description>NAK Status (NAKSts)</description>
16179 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
16184 … <description>The core is transmitting NAK handshakes on this endpoint</description>
16191 <description>Endpoint Type (EPType)</description>
16197 <description>Control</description>
16202 <description>Isochronous</description>
16207 <description>Bulk</description>
16212 <description>Interrupt</description>
16219 <description>STALL Handshake (Stall)</description>
16225 <description>STALL All non-active tokens</description>
16230 <description>STALL All Active Tokens</description>
16237 <description>TxFIFO Number (TxFNum)</description>
16243 <description>Tx FIFO 0</description>
16248 <description>Tx FIFO 1</description>
16253 <description>Tx FIFO 2</description>
16258 <description>Tx FIFO 3</description>
16263 <description>Tx FIFO 4</description>
16268 <description>Tx FIFO 5</description>
16273 <description>Tx FIFO 6</description>
16278 <description>Tx FIFO 7</description>
16283 <description>Tx FIFO 8</description>
16288 <description>Tx FIFO 9</description>
16293 <description>Tx FIFO 10</description>
16298 <description>Tx FIFO 11</description>
16303 <description>Tx FIFO 12</description>
16308 <description>Tx FIFO 13</description>
16313 <description>Tx FIFO 14</description>
16318 <description>Tx FIFO 15</description>
16325 <description>Clear NAK (CNAK)</description>
16332 <description>No Clear NAK</description>
16337 <description>Clear NAK</description>
16344 <description>Set NAK (SNAK)</description>
16351 <description>No Set NAK</description>
16356 <description>Set NAK</description>
16363 <description>Set DATA0 PID (SetD0PID)</description>
16370 … <description>Disables Set DATA0 PID or Do not force Even (micro)Frame</description>
16375 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame</descript…
16382 <description>Set DATA1 PID (SetD1PID)</description>
16389 … <description>Disables Set DATA1 PID or Do not force Odd (micro)Frame</description>
16394 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame</descripti…
16401 <description>Endpoint Disable (EPDis)</description>
16407 <description>No Action</description>
16412 <description>Disable Endpoint</description>
16419 <description>Endpoint Enable (EPEna)</description>
16425 <description>No Action</description>
16430 <description>Enable Endpoint</description>
16439 <description>Device IN Endpoint Interrupt Register</description>
16447 <description>Transfer Completed Interrupt (XferCompl)</description>
16453 <description>No Transfer Complete Interrupt</description>
16458 <description>Transfer Complete Interrupt</description>
16465 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
16471 <description>No Endpoint Disabled Interrupt</description>
16476 <description>Endpoint Disabled Interrupt</description>
16483 <description>AHB Error (AHBErr)</description>
16489 <description>No AHB Error Interrupt</description>
16494 <description>AHB Error interrupt</description>
16501 <description>Timeout Condition (TimeOUT)</description>
16507 <description>No Timeout interrupt</description>
16512 <description>Timeout interrupt</description>
16519 <description>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</description>
16525 <description>No IN Token Received interrupt</description>
16530 <description>IN Token Received Interrupt</description>
16537 <description>IN Token Received with EP Mismatch (INTknEPMis)</description>
16543 <description>No IN Token Received with EP Mismatch interrupt</description>
16548 <description>IN Token Received with EP Mismatch interrupt</description>
16555 <description>IN Endpoint NAK Effective (INEPNakEff)</description>
16561 <description>No Endpoint NAK Effective interrupt</description>
16566 <description>IN Endpoint NAK Effective interrupt</description>
16573 <description>Transmit FIFO Empty (TxFEmp)</description>
16580 <description>No Transmit FIFO Empty interrupt</description>
16585 <description>Transmit FIFO Empty interrupt</description>
16592 <description>Fifo Underrun (TxfifoUndrn)</description>
16598 <description>No Tx FIFO Underrun interrupt</description>
16603 <description>TxFIFO Underrun interrupt</description>
16610 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
16616 <description>No BNA interrupt</description>
16621 <description>BNA interrupt</description>
16628 <description>Packet Drop Status (PktDrpSts)</description>
16634 <description>No interrupt</description>
16639 <description>Packet Drop Status interrupt</description>
16646 <description>NAK Interrupt (BbleErr)</description>
16652 <description>No interrupt</description>
16657 <description>BbleErr interrupt</description>
16664 <description>NAK Interrupt (NAKInterrupt)</description>
16670 <description>No NAK interrupt</description>
16675 <description>NAK Interrupt</description>
16682 <description>NYET Interrupt (NYETIntrpt)</description>
16688 <description>No NYET interrupt</description>
16693 <description>NYET Interrupt</description>
16702 <description>Device IN Endpoint Transfer Size Register</description>
16710 <description>Transfer Size (XferSize)</description>
16716 <description>Packet Count (PktCnt)</description>
16722 <description>MC</description>
16728 <description>1 packet</description>
16733 <description>2 packets</description>
16738 <description>3 packets</description>
16747 <description>Device IN Endpoint DMA Address Register</description>
16755 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
16763 <description>Device IN Endpoint Transmit FIFO Status Register</description>
16771 <description>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</description>
16780 <description>Device Control IN Endpoint Control Register</description>
16788 <description>Maximum Packet Size (MPS)</description>
16794 <description>USB Active Endpoint (USBActEP)</description>
16800 <description>Not Active</description>
16805 <description>USB Active Endpoint</description>
16818 <description>DATA0 or Even Frame</description>
16823 <description>DATA1 or Odd Frame</description>
16830 <description>NAK Status (NAKSts)</description>
16837 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
16842 … <description>The core is transmitting NAK handshakes on this endpoint</description>
16849 <description>Endpoint Type (EPType)</description>
16855 <description>Control</description>
16860 <description>Isochronous</description>
16865 <description>Bulk</description>
16870 <description>Interrupt</description>
16877 <description>STALL Handshake (Stall)</description>
16883 <description>STALL All non-active tokens</description>
16888 <description>STALL All Active Tokens</description>
16895 <description>TxFIFO Number (TxFNum)</description>
16901 <description>Tx FIFO 0</description>
16906 <description>Tx FIFO 1</description>
16911 <description>Tx FIFO 2</description>
16916 <description>Tx FIFO 3</description>
16921 <description>Tx FIFO 4</description>
16926 <description>Tx FIFO 5</description>
16931 <description>Tx FIFO 6</description>
16936 <description>Tx FIFO 7</description>
16941 <description>Tx FIFO 8</description>
16946 <description>Tx FIFO 9</description>
16951 <description>Tx FIFO 10</description>
16956 <description>Tx FIFO 11</description>
16961 <description>Tx FIFO 12</description>
16966 <description>Tx FIFO 13</description>
16971 <description>Tx FIFO 14</description>
16976 <description>Tx FIFO 15</description>
16983 <description>Clear NAK (CNAK)</description>
16990 <description>No Clear NAK</description>
16995 <description>Clear NAK</description>
17002 <description>Set NAK (SNAK)</description>
17009 <description>No Set NAK</description>
17014 <description>Set NAK</description>
17021 <description>Set DATA0 PID (SetD0PID)</description>
17028 … <description>Disables Set DATA0 PID or Do not force Even (micro)Frame</description>
17033 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame</descript…
17040 <description>Set DATA1 PID (SetD1PID)</description>
17047 … <description>Disables Set DATA1 PID or Do not force Odd (micro)Frame</description>
17052 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame</descripti…
17059 <description>Endpoint Disable (EPDis)</description>
17065 <description>No Action</description>
17070 <description>Disable Endpoint</description>
17077 <description>Endpoint Enable (EPEna)</description>
17083 <description>No Action</description>
17088 <description>Enable Endpoint</description>
17097 <description>Device IN Endpoint Interrupt Register</description>
17105 <description>Transfer Completed Interrupt (XferCompl)</description>
17111 <description>No Transfer Complete Interrupt</description>
17116 <description>Transfer Complete Interrupt</description>
17123 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
17129 <description>No Endpoint Disabled Interrupt</description>
17134 <description>Endpoint Disabled Interrupt</description>
17141 <description>AHB Error (AHBErr)</description>
17147 <description>No AHB Error Interrupt</description>
17152 <description>AHB Error interrupt</description>
17159 <description>Timeout Condition (TimeOUT)</description>
17165 <description>No Timeout interrupt</description>
17170 <description>Timeout interrupt</description>
17177 <description>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</description>
17183 <description>No IN Token Received interrupt</description>
17188 <description>IN Token Received Interrupt</description>
17195 <description>IN Token Received with EP Mismatch (INTknEPMis)</description>
17201 <description>No IN Token Received with EP Mismatch interrupt</description>
17206 <description>IN Token Received with EP Mismatch interrupt</description>
17213 <description>IN Endpoint NAK Effective (INEPNakEff)</description>
17219 <description>No Endpoint NAK Effective interrupt</description>
17224 <description>IN Endpoint NAK Effective interrupt</description>
17231 <description>Transmit FIFO Empty (TxFEmp)</description>
17238 <description>No Transmit FIFO Empty interrupt</description>
17243 <description>Transmit FIFO Empty interrupt</description>
17250 <description>Fifo Underrun (TxfifoUndrn)</description>
17256 <description>No Tx FIFO Underrun interrupt</description>
17261 <description>TxFIFO Underrun interrupt</description>
17268 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
17274 <description>No BNA interrupt</description>
17279 <description>BNA interrupt</description>
17286 <description>Packet Drop Status (PktDrpSts)</description>
17292 <description>No interrupt</description>
17297 <description>Packet Drop Status interrupt</description>
17304 <description>NAK Interrupt (BbleErr)</description>
17310 <description>No interrupt</description>
17315 <description>BbleErr interrupt</description>
17322 <description>NAK Interrupt (NAKInterrupt)</description>
17328 <description>No NAK interrupt</description>
17333 <description>NAK Interrupt</description>
17340 <description>NYET Interrupt (NYETIntrpt)</description>
17346 <description>No NYET interrupt</description>
17351 <description>NYET Interrupt</description>
17360 <description>Device IN Endpoint Transfer Size Register</description>
17368 <description>Transfer Size (XferSize)</description>
17374 <description>Packet Count (PktCnt)</description>
17380 <description>MC</description>
17386 <description>1 packet</description>
17391 <description>2 packets</description>
17396 <description>3 packets</description>
17405 <description>Device IN Endpoint DMA Address Register</description>
17413 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
17421 <description>Device IN Endpoint Transmit FIFO Status Register</description>
17429 <description>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</description>
17438 <description>Device Control OUT Endpoint 0 Control Register</description>
17446 <description>Maximum Packet Size (MPS)</description>
17453 <description>64 bytes</description>
17458 <description>32 bytes</description>
17463 <description>16 bytes</description>
17468 <description>8 bytes</description>
17475 <description>USB Active Endpoint (USBActEP)</description>
17482 <description>USB Active Endpoint 0</description>
17489 <description>NAK Status (NAKSts)</description>
17496 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
17501 … <description>The core is transmitting NAK handshakes on this endpoint</description>
17508 <description>Endpoint Type (EPType)</description>
17515 <description>Endpoint Control 0</description>
17522 <description>STALL Handshake (Stall)</description>
17528 <description>No Stall</description>
17533 <description>Stall Handshake</description>
17540 <description>Clear NAK (CNAK)</description>
17547 <description>No action</description>
17552 <description>Clear NAK</description>
17559 <description>Set NAK (SNAK)</description>
17566 <description>No action</description>
17571 <description>Set NAK</description>
17578 <description>Endpoint Disable (EPDis)</description>
17585 <description>No Endpoint disable</description>
17592 <description>Endpoint Enable (EPEna)</description>
17598 <description>No action</description>
17603 <description>Enable Endpoint</description>
17612 <description>Device OUT Endpoint 0 Interrupt Register</description>
17620 <description>Transfer Completed Interrupt (XferCompl)</description>
17626 <description>No Transfer Complete Interrupt</description>
17631 <description>Transfer Complete Interrupt</description>
17638 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
17644 <description>No Endpoint Disabled Interrupt</description>
17649 <description>Endpoint Disabled Interrupt</description>
17656 <description>AHB Error (AHBErr)</description>
17662 <description>No AHB Error Interrupt</description>
17667 <description>AHB Error interrupt</description>
17674 <description>SETUP Phase Done (SetUp)</description>
17680 <description>No SETUP Phase Done</description>
17685 <description>SETUP Phase Done</description>
17692 <description>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</description>
17698 <description>No OUT Token Received When Endpoint Disabled</description>
17703 <description>OUT Token Received When Endpoint Disabled</description>
17710 <description>Status Phase Received for Control Write (StsPhseRcvd)</description>
17716 <description>No Status Phase Received for Control Write</description>
17721 <description>Status Phase Received for Control Write</description>
17728 <description>Back-to-Back SETUP Packets Received (Back2BackSETup)</description>
17734 <description>No Back-to-Back SETUP Packets Received</description>
17739 <description>Back-to-Back SETUP Packets Received</description>
17746 <description>OUT Packet Error (OutPktErr)</description>
17752 <description>No OUT Packet Error</description>
17757 <description>OUT Packet Error</description>
17764 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
17770 <description>No BNA interrupt</description>
17775 <description>BNA interrupt</description>
17782 <description>Packet Drop Status (PktDrpSts)</description>
17788 <description>No interrupt</description>
17793 <description>Packet Drop Status interrupt</description>
17800 <description>NAK Interrupt (BbleErr)</description>
17806 <description>No BbleErr interrupt</description>
17811 <description>BbleErr interrupt</description>
17818 <description>NAK Interrupt (NAKInterrupt)</description>
17824 <description>No NAK interrupt</description>
17829 <description>NAK Interrupt</description>
17836 <description>NYET Interrupt (NYETIntrpt)</description>
17842 <description>No NYET interrupt</description>
17847 <description>NYET Interrupt</description>
17854 <description>Setup Packet Received</description>
17860 <description>No Setup packet received</description>
17865 <description>Setup packet received</description>
17874 <description>Device OUT Endpoint 0 Transfer Size Register</description>
17882 <description>Transfer Size (XferSize)</description>
17888 <description>Packet Count (PktCnt)</description>
17894 <description>SETUP Packet Count (SUPCnt)</description>
17900 <description>1 packet</description>
17905 <description>2 packets</description>
17910 <description>3 packets</description>
17919 <description>Device OUT Endpoint 0 DMA Address Register</description>
17927 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
17935 <description>Device Control OUT Endpoint Control Register</description>
17943 <description>Maximum Packet Size (MPS)</description>
17949 <description>USB Active Endpoint (USBActEP)</description>
17955 <description>Not Active</description>
17960 <description>USB Active Endpoint</description>
17967 <description>Endpoint Data PID (DPID)</description>
17974 <description>Endpoint Data PID not active</description>
17979 <description>Endpoint Data PID active</description>
17986 <description>NAK Status (NAKSts)</description>
17993 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
17998 … <description>The core is transmitting NAK handshakes on this endpoint</description>
18005 <description>Endpoint Type (EPType)</description>
18011 <description>Control</description>
18016 <description>Isochronous</description>
18021 <description>Bulk</description>
18026 <description>Interrupt</description>
18033 <description>STALL Handshake (Stall)</description>
18039 <description>STALL All non-active tokens</description>
18044 <description>STALL All Active Tokens</description>
18057 <description>No Clear NAK</description>
18062 <description>Clear NAK</description>
18069 <description>Set NAK (SNAK)</description>
18076 <description>No Set NAK</description>
18081 <description>Set NAK</description>
18088 <description>Set DATA0 PID (SetD0PID)</description>
18095 <description>Disables Set DATA0 PID or Do not force Even Frame</description>
18100 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
18107 <description>Set DATA1 PID (SetD1PID)</description>
18114 <description>Disables Set DATA1 PID or Do not force Odd Frame</description>
18119 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
18126 <description>Endpoint Disable (EPDis)</description>
18132 <description>No Action</description>
18137 <description>Disable Endpoint</description>
18144 <description>Endpoint Enable (EPEna)</description>
18150 <description>No Action</description>
18155 <description>Enable Endpoint</description>
18164 <description>Device OUT Endpoint Interrupt Register</description>
18172 <description>Transfer Completed Interrupt (XferCompl)</description>
18178 <description>No Transfer Complete Interrupt</description>
18183 <description>Transfer Complete Interrupt</description>
18190 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
18196 <description>No Endpoint Disabled Interrupt</description>
18201 <description>Endpoint Disabled Interrupt</description>
18208 <description>AHB Error (AHBErr)</description>
18214 <description>No AHB Error Interrupt</description>
18219 <description>AHB Error interrupt</description>
18226 <description>SETUP Phase Done (SetUp)</description>
18232 <description>No SETUP Phase Done</description>
18237 <description>SETUP Phase Done</description>
18244 <description>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</description>
18250 <description>No OUT Token Received When Endpoint Disabled</description>
18255 <description>OUT Token Received When Endpoint Disabled</description>
18262 <description>Status Phase Received for Control Write (StsPhseRcvd)</description>
18268 <description>No Status Phase Received for Control Write</description>
18273 <description>Status Phase Received for Control Write</description>
18280 <description>Back-to-Back SETUP Packets Received (Back2BackSETup)</description>
18286 <description>No Back-to-Back SETUP Packets Received</description>
18291 <description>Back-to-Back SETUP Packets Received</description>
18298 <description>OUT Packet Error (OutPktErr)</description>
18304 <description>No OUT Packet Error</description>
18309 <description>OUT Packet Error</description>
18316 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
18322 <description>No BNA interrupt</description>
18327 <description>BNA interrupt</description>
18334 <description>Packet Drop Status (PktDrpSts)</description>
18340 <description>No interrupt</description>
18345 <description>Packet Drop Status interrupt</description>
18352 <description>NAK Interrupt (BbleErr)</description>
18358 <description>No BbleErr interrupt</description>
18363 <description>BbleErr interrupt</description>
18370 <description>NAK Interrupt (NAKInterrupt)</description>
18376 <description>No NAK interrupt</description>
18381 <description>NAK Interrupt</description>
18388 <description>NYET Interrupt (NYETIntrpt)</description>
18394 <description>No NYET interrupt</description>
18399 <description>NYET Interrupt</description>
18406 <description>Setup Packet Received</description>
18412 <description>No Setup packet received</description>
18417 <description>Setup packet received</description>
18426 <description>Device OUT Endpoint Transfer Size Register</description>
18434 <description>Transfer Size (XferSize)</description>
18440 <description>Packet Count (PktCnt)</description>
18446 <description>RxDPID</description>
18453 <description>DATA0</description>
18458 <description>DATA2 or 1 packet</description>
18463 <description>DATA1 or 2 packets</description>
18468 <description>MDATA or 3 packets</description>
18477 <description>Device OUT Endpoint DMA Address Register</description>
18485 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
18493 <description>Device Control OUT Endpoint Control Register</description>
18501 <description>Maximum Packet Size (MPS)</description>
18507 <description>USB Active Endpoint (USBActEP)</description>
18513 <description>Not Active</description>
18518 <description>USB Active Endpoint</description>
18525 <description>Endpoint Data PID (DPID)</description>
18532 <description>Endpoint Data PID not active</description>
18537 <description>Endpoint Data PID active</description>
18544 <description>NAK Status (NAKSts)</description>
18551 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
18556 … <description>The core is transmitting NAK handshakes on this endpoint</description>
18563 <description>Endpoint Type (EPType)</description>
18569 <description>Control</description>
18574 <description>Isochronous</description>
18579 <description>Bulk</description>
18584 <description>Interrupt</description>
18591 <description>STALL Handshake (Stall)</description>
18597 <description>STALL All non-active tokens</description>
18602 <description>STALL All Active Tokens</description>
18615 <description>No Clear NAK</description>
18620 <description>Clear NAK</description>
18627 <description>Set NAK (SNAK)</description>
18634 <description>No Set NAK</description>
18639 <description>Set NAK</description>
18646 <description>Set DATA0 PID (SetD0PID)</description>
18653 <description>Disables Set DATA0 PID or Do not force Even Frame</description>
18658 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
18665 <description>Set DATA1 PID (SetD1PID)</description>
18672 <description>Disables Set DATA1 PID or Do not force Odd Frame</description>
18677 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
18684 <description>Endpoint Disable (EPDis)</description>
18690 <description>No Action</description>
18695 <description>Disable Endpoint</description>
18702 <description>Endpoint Enable (EPEna)</description>
18708 <description>No Action</description>
18713 <description>Enable Endpoint</description>
18722 <description>Device OUT Endpoint Interrupt Register</description>
18730 <description>Transfer Completed Interrupt (XferCompl)</description>
18736 <description>No Transfer Complete Interrupt</description>
18741 <description>Transfer Complete Interrupt</description>
18748 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
18754 <description>No Endpoint Disabled Interrupt</description>
18759 <description>Endpoint Disabled Interrupt</description>
18766 <description>AHB Error (AHBErr)</description>
18772 <description>No AHB Error Interrupt</description>
18777 <description>AHB Error interrupt</description>
18784 <description>SETUP Phase Done (SetUp)</description>
18790 <description>No SETUP Phase Done</description>
18795 <description>SETUP Phase Done</description>
18802 <description>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</description>
18808 <description>No OUT Token Received When Endpoint Disabled</description>
18813 <description>OUT Token Received When Endpoint Disabled</description>
18820 <description>Status Phase Received for Control Write (StsPhseRcvd)</description>
18826 <description>No Status Phase Received for Control Write</description>
18831 <description>Status Phase Received for Control Write</description>
18838 <description>Back-to-Back SETUP Packets Received (Back2BackSETup)</description>
18844 <description>No Back-to-Back SETUP Packets Received</description>
18849 <description>Back-to-Back SETUP Packets Received</description>
18856 <description>OUT Packet Error (OutPktErr)</description>
18862 <description>No OUT Packet Error</description>
18867 <description>OUT Packet Error</description>
18874 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
18880 <description>No BNA interrupt</description>
18885 <description>BNA interrupt</description>
18892 <description>Packet Drop Status (PktDrpSts)</description>
18898 <description>No interrupt</description>
18903 <description>Packet Drop Status interrupt</description>
18910 <description>NAK Interrupt (BbleErr)</description>
18916 <description>No BbleErr interrupt</description>
18921 <description>BbleErr interrupt</description>
18928 <description>NAK Interrupt (NAKInterrupt)</description>
18934 <description>No NAK interrupt</description>
18939 <description>NAK Interrupt</description>
18946 <description>NYET Interrupt (NYETIntrpt)</description>
18952 <description>No NYET interrupt</description>
18957 <description>NYET Interrupt</description>
18964 <description>Setup Packet Received</description>
18970 <description>No Setup packet received</description>
18975 <description>Setup packet received</description>
18984 <description>Device OUT Endpoint Transfer Size Register</description>
18992 <description>Transfer Size (XferSize)</description>
18998 <description>Packet Count (PktCnt)</description>
19004 <description>RxDPID</description>
19011 <description>DATA0</description>
19016 <description>DATA2 or 1 packet</description>
19021 <description>DATA1 or 2 packets</description>
19026 <description>MDATA or 3 packets</description>
19035 <description>Device OUT Endpoint DMA Address Register</description>
19043 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
19051 <description>Device Control OUT Endpoint Control Register</description>
19059 <description>Maximum Packet Size (MPS)</description>
19065 <description>USB Active Endpoint (USBActEP)</description>
19071 <description>Not Active</description>
19076 <description>USB Active Endpoint</description>
19083 <description>Endpoint Data PID (DPID)</description>
19090 <description>Endpoint Data PID not active</description>
19095 <description>Endpoint Data PID active</description>
19102 <description>NAK Status (NAKSts)</description>
19109 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
19114 … <description>The core is transmitting NAK handshakes on this endpoint</description>
19121 <description>Endpoint Type (EPType)</description>
19127 <description>Control</description>
19132 <description>Isochronous</description>
19137 <description>Bulk</description>
19142 <description>Interrupt</description>
19149 <description>STALL Handshake (Stall)</description>
19155 <description>STALL All non-active tokens</description>
19160 <description>STALL All Active Tokens</description>
19173 <description>No Clear NAK</description>
19178 <description>Clear NAK</description>
19185 <description>Set NAK (SNAK)</description>
19192 <description>No Set NAK</description>
19197 <description>Set NAK</description>
19204 <description>Set DATA0 PID (SetD0PID)</description>
19211 <description>Disables Set DATA0 PID or Do not force Even Frame</description>
19216 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
19223 <description>Set DATA1 PID (SetD1PID)</description>
19230 <description>Disables Set DATA1 PID or Do not force Odd Frame</description>
19235 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
19242 <description>Endpoint Disable (EPDis)</description>
19248 <description>No Action</description>
19253 <description>Disable Endpoint</description>
19260 <description>Endpoint Enable (EPEna)</description>
19266 <description>No Action</description>
19271 <description>Enable Endpoint</description>
19280 <description>Device OUT Endpoint Interrupt Register</description>
19288 <description>Transfer Completed Interrupt (XferCompl)</description>
19294 <description>No Transfer Complete Interrupt</description>
19299 <description>Transfer Complete Interrupt</description>
19306 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
19312 <description>No Endpoint Disabled Interrupt</description>
19317 <description>Endpoint Disabled Interrupt</description>
19324 <description>AHB Error (AHBErr)</description>
19330 <description>No AHB Error Interrupt</description>
19335 <description>AHB Error interrupt</description>
19342 <description>SETUP Phase Done (SetUp)</description>
19348 <description>No SETUP Phase Done</description>
19353 <description>SETUP Phase Done</description>
19360 <description>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</description>
19366 <description>No OUT Token Received When Endpoint Disabled</description>
19371 <description>OUT Token Received When Endpoint Disabled</description>
19378 <description>Status Phase Received for Control Write (StsPhseRcvd)</description>
19384 <description>No Status Phase Received for Control Write</description>
19389 <description>Status Phase Received for Control Write</description>
19396 <description>Back-to-Back SETUP Packets Received (Back2BackSETup)</description>
19402 <description>No Back-to-Back SETUP Packets Received</description>
19407 <description>Back-to-Back SETUP Packets Received</description>
19414 <description>OUT Packet Error (OutPktErr)</description>
19420 <description>No OUT Packet Error</description>
19425 <description>OUT Packet Error</description>
19432 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
19438 <description>No BNA interrupt</description>
19443 <description>BNA interrupt</description>
19450 <description>Packet Drop Status (PktDrpSts)</description>
19456 <description>No interrupt</description>
19461 <description>Packet Drop Status interrupt</description>
19468 <description>NAK Interrupt (BbleErr)</description>
19474 <description>No BbleErr interrupt</description>
19479 <description>BbleErr interrupt</description>
19486 <description>NAK Interrupt (NAKInterrupt)</description>
19492 <description>No NAK interrupt</description>
19497 <description>NAK Interrupt</description>
19504 <description>NYET Interrupt (NYETIntrpt)</description>
19510 <description>No NYET interrupt</description>
19515 <description>NYET Interrupt</description>
19522 <description>Setup Packet Received</description>
19528 <description>No Setup packet received</description>
19533 <description>Setup packet received</description>
19542 <description>Device OUT Endpoint Transfer Size Register</description>
19550 <description>Transfer Size (XferSize)</description>
19556 <description>Packet Count (PktCnt)</description>
19562 <description>RxDPID</description>
19569 <description>DATA0</description>
19574 <description>DATA2 or 1 packet</description>
19579 <description>DATA1 or 2 packets</description>
19584 <description>MDATA or 3 packets</description>
19593 <description>Device OUT Endpoint DMA Address Register</description>
19601 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
19609 <description>Device Control OUT Endpoint Control Register</description>
19617 <description>Maximum Packet Size (MPS)</description>
19623 <description>USB Active Endpoint (USBActEP)</description>
19629 <description>Not Active</description>
19634 <description>USB Active Endpoint</description>
19641 <description>Endpoint Data PID (DPID)</description>
19648 <description>Endpoint Data PID not active</description>
19653 <description>Endpoint Data PID active</description>
19660 <description>NAK Status (NAKSts)</description>
19667 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
19672 … <description>The core is transmitting NAK handshakes on this endpoint</description>
19679 <description>Endpoint Type (EPType)</description>
19685 <description>Control</description>
19690 <description>Isochronous</description>
19695 <description>Bulk</description>
19700 <description>Interrupt</description>
19707 <description>STALL Handshake (Stall)</description>
19713 <description>STALL All non-active tokens</description>
19718 <description>STALL All Active Tokens</description>
19731 <description>No Clear NAK</description>
19736 <description>Clear NAK</description>
19743 <description>Set NAK (SNAK)</description>
19750 <description>No Set NAK</description>
19755 <description>Set NAK</description>
19762 <description>Set DATA0 PID (SetD0PID)</description>
19769 <description>Disables Set DATA0 PID or Do not force Even Frame</description>
19774 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
19781 <description>Set DATA1 PID (SetD1PID)</description>
19788 <description>Disables Set DATA1 PID or Do not force Odd Frame</description>
19793 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
19800 <description>Endpoint Disable (EPDis)</description>
19806 <description>No Action</description>
19811 <description>Disable Endpoint</description>
19818 <description>Endpoint Enable (EPEna)</description>
19824 <description>No Action</description>
19829 <description>Enable Endpoint</description>
19838 <description>Device OUT Endpoint Interrupt Register</description>
19846 <description>Transfer Completed Interrupt (XferCompl)</description>
19852 <description>No Transfer Complete Interrupt</description>
19857 <description>Transfer Complete Interrupt</description>
19864 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
19870 <description>No Endpoint Disabled Interrupt</description>
19875 <description>Endpoint Disabled Interrupt</description>
19882 <description>AHB Error (AHBErr)</description>
19888 <description>No AHB Error Interrupt</description>
19893 <description>AHB Error interrupt</description>
19900 <description>SETUP Phase Done (SetUp)</description>
19906 <description>No SETUP Phase Done</description>
19911 <description>SETUP Phase Done</description>
19918 <description>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</description>
19924 <description>No OUT Token Received When Endpoint Disabled</description>
19929 <description>OUT Token Received When Endpoint Disabled</description>
19936 <description>Status Phase Received for Control Write (StsPhseRcvd)</description>
19942 <description>No Status Phase Received for Control Write</description>
19947 <description>Status Phase Received for Control Write</description>
19954 <description>Back-to-Back SETUP Packets Received (Back2BackSETup)</description>
19960 <description>No Back-to-Back SETUP Packets Received</description>
19965 <description>Back-to-Back SETUP Packets Received</description>
19972 <description>OUT Packet Error (OutPktErr)</description>
19978 <description>No OUT Packet Error</description>
19983 <description>OUT Packet Error</description>
19990 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
19996 <description>No BNA interrupt</description>
20001 <description>BNA interrupt</description>
20008 <description>Packet Drop Status (PktDrpSts)</description>
20014 <description>No interrupt</description>
20019 <description>Packet Drop Status interrupt</description>
20026 <description>NAK Interrupt (BbleErr)</description>
20032 <description>No BbleErr interrupt</description>
20037 <description>BbleErr interrupt</description>
20044 <description>NAK Interrupt (NAKInterrupt)</description>
20050 <description>No NAK interrupt</description>
20055 <description>NAK Interrupt</description>
20062 <description>NYET Interrupt (NYETIntrpt)</description>
20068 <description>No NYET interrupt</description>
20073 <description>NYET Interrupt</description>
20080 <description>Setup Packet Received</description>
20086 <description>No Setup packet received</description>
20091 <description>Setup packet received</description>
20100 <description>Device OUT Endpoint Transfer Size Register</description>
20108 <description>Transfer Size (XferSize)</description>
20114 <description>Packet Count (PktCnt)</description>
20120 <description>RxDPID</description>
20127 <description>DATA0</description>
20132 <description>DATA2 or 1 packet</description>
20137 <description>DATA1 or 2 packets</description>
20142 <description>MDATA or 3 packets</description>
20151 <description>Device OUT Endpoint DMA Address Register</description>
20159 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
20167 <description>Device Control OUT Endpoint Control Register</description>
20175 <description>Maximum Packet Size (MPS)</description>
20181 <description>USB Active Endpoint (USBActEP)</description>
20187 <description>Not Active</description>
20192 <description>USB Active Endpoint</description>
20199 <description>Endpoint Data PID (DPID)</description>
20206 <description>Endpoint Data PID not active</description>
20211 <description>Endpoint Data PID active</description>
20218 <description>NAK Status (NAKSts)</description>
20225 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
20230 … <description>The core is transmitting NAK handshakes on this endpoint</description>
20237 <description>Endpoint Type (EPType)</description>
20243 <description>Control</description>
20248 <description>Isochronous</description>
20253 <description>Bulk</description>
20258 <description>Interrupt</description>
20265 <description>STALL Handshake (Stall)</description>
20271 <description>STALL All non-active tokens</description>
20276 <description>STALL All Active Tokens</description>
20289 <description>No Clear NAK</description>
20294 <description>Clear NAK</description>
20301 <description>Set NAK (SNAK)</description>
20308 <description>No Set NAK</description>
20313 <description>Set NAK</description>
20320 <description>Set DATA0 PID (SetD0PID)</description>
20327 <description>Disables Set DATA0 PID or Do not force Even Frame</description>
20332 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
20339 <description>Set DATA1 PID (SetD1PID)</description>
20346 <description>Disables Set DATA1 PID or Do not force Odd Frame</description>
20351 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
20358 <description>Endpoint Disable (EPDis)</description>
20364 <description>No Action</description>
20369 <description>Disable Endpoint</description>
20376 <description>Endpoint Enable (EPEna)</description>
20382 <description>No Action</description>
20387 <description>Enable Endpoint</description>
20396 <description>Device OUT Endpoint Interrupt Register</description>
20404 <description>Transfer Completed Interrupt (XferCompl)</description>
20410 <description>No Transfer Complete Interrupt</description>
20415 <description>Transfer Complete Interrupt</description>
20422 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
20428 <description>No Endpoint Disabled Interrupt</description>
20433 <description>Endpoint Disabled Interrupt</description>
20440 <description>AHB Error (AHBErr)</description>
20446 <description>No AHB Error Interrupt</description>
20451 <description>AHB Error interrupt</description>
20458 <description>SETUP Phase Done (SetUp)</description>
20464 <description>No SETUP Phase Done</description>
20469 <description>SETUP Phase Done</description>
20476 <description>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</description>
20482 <description>No OUT Token Received When Endpoint Disabled</description>
20487 <description>OUT Token Received When Endpoint Disabled</description>
20494 <description>Status Phase Received for Control Write (StsPhseRcvd)</description>
20500 <description>No Status Phase Received for Control Write</description>
20505 <description>Status Phase Received for Control Write</description>
20512 <description>Back-to-Back SETUP Packets Received (Back2BackSETup)</description>
20518 <description>No Back-to-Back SETUP Packets Received</description>
20523 <description>Back-to-Back SETUP Packets Received</description>
20530 <description>OUT Packet Error (OutPktErr)</description>
20536 <description>No OUT Packet Error</description>
20541 <description>OUT Packet Error</description>
20548 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
20554 <description>No BNA interrupt</description>
20559 <description>BNA interrupt</description>
20566 <description>Packet Drop Status (PktDrpSts)</description>
20572 <description>No interrupt</description>
20577 <description>Packet Drop Status interrupt</description>
20584 <description>NAK Interrupt (BbleErr)</description>
20590 <description>No BbleErr interrupt</description>
20595 <description>BbleErr interrupt</description>
20602 <description>NAK Interrupt (NAKInterrupt)</description>
20608 <description>No NAK interrupt</description>
20613 <description>NAK Interrupt</description>
20620 <description>NYET Interrupt (NYETIntrpt)</description>
20626 <description>No NYET interrupt</description>
20631 <description>NYET Interrupt</description>
20638 <description>Setup Packet Received</description>
20644 <description>No Setup packet received</description>
20649 <description>Setup packet received</description>
20658 <description>Device OUT Endpoint Transfer Size Register</description>
20666 <description>Transfer Size (XferSize)</description>
20672 <description>Packet Count (PktCnt)</description>
20678 <description>RxDPID</description>
20685 <description>DATA0</description>
20690 <description>DATA2 or 1 packet</description>
20695 <description>DATA1 or 2 packets</description>
20700 <description>MDATA or 3 packets</description>
20709 <description>Device OUT Endpoint DMA Address Register</description>
20717 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
20725 <description>Device Control OUT Endpoint Control Register</description>
20733 <description>Maximum Packet Size (MPS)</description>
20739 <description>USB Active Endpoint (USBActEP)</description>
20745 <description>Not Active</description>
20750 <description>USB Active Endpoint</description>
20757 <description>Endpoint Data PID (DPID)</description>
20764 <description>Endpoint Data PID not active</description>
20769 <description>Endpoint Data PID active</description>
20776 <description>NAK Status (NAKSts)</description>
20783 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
20788 … <description>The core is transmitting NAK handshakes on this endpoint</description>
20795 <description>Endpoint Type (EPType)</description>
20801 <description>Control</description>
20806 <description>Isochronous</description>
20811 <description>Bulk</description>
20816 <description>Interrupt</description>
20823 <description>STALL Handshake (Stall)</description>
20829 <description>STALL All non-active tokens</description>
20834 <description>STALL All Active Tokens</description>
20847 <description>No Clear NAK</description>
20852 <description>Clear NAK</description>
20859 <description>Set NAK (SNAK)</description>
20866 <description>No Set NAK</description>
20871 <description>Set NAK</description>
20878 <description>Set DATA0 PID (SetD0PID)</description>
20885 <description>Disables Set DATA0 PID or Do not force Even Frame</description>
20890 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
20897 <description>Set DATA1 PID (SetD1PID)</description>
20904 <description>Disables Set DATA1 PID or Do not force Odd Frame</description>
20909 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
20916 <description>Endpoint Disable (EPDis)</description>
20922 <description>No Action</description>
20927 <description>Disable Endpoint</description>
20934 <description>Endpoint Enable (EPEna)</description>
20940 <description>No Action</description>
20945 <description>Enable Endpoint</description>
20954 <description>Device OUT Endpoint Interrupt Register</description>
20962 <description>Transfer Completed Interrupt (XferCompl)</description>
20968 <description>No Transfer Complete Interrupt</description>
20973 <description>Transfer Complete Interrupt</description>
20980 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
20986 <description>No Endpoint Disabled Interrupt</description>
20991 <description>Endpoint Disabled Interrupt</description>
20998 <description>AHB Error (AHBErr)</description>
21004 <description>No AHB Error Interrupt</description>
21009 <description>AHB Error interrupt</description>
21016 <description>SETUP Phase Done (SetUp)</description>
21022 <description>No SETUP Phase Done</description>
21027 <description>SETUP Phase Done</description>
21034 <description>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</description>
21040 <description>No OUT Token Received When Endpoint Disabled</description>
21045 <description>OUT Token Received When Endpoint Disabled</description>
21052 <description>Status Phase Received for Control Write (StsPhseRcvd)</description>
21058 <description>No Status Phase Received for Control Write</description>
21063 <description>Status Phase Received for Control Write</description>
21070 <description>Back-to-Back SETUP Packets Received (Back2BackSETup)</description>
21076 <description>No Back-to-Back SETUP Packets Received</description>
21081 <description>Back-to-Back SETUP Packets Received</description>
21088 <description>OUT Packet Error (OutPktErr)</description>
21094 <description>No OUT Packet Error</description>
21099 <description>OUT Packet Error</description>
21106 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
21112 <description>No BNA interrupt</description>
21117 <description>BNA interrupt</description>
21124 <description>Packet Drop Status (PktDrpSts)</description>
21130 <description>No interrupt</description>
21135 <description>Packet Drop Status interrupt</description>
21142 <description>NAK Interrupt (BbleErr)</description>
21148 <description>No BbleErr interrupt</description>
21153 <description>BbleErr interrupt</description>
21160 <description>NAK Interrupt (NAKInterrupt)</description>
21166 <description>No NAK interrupt</description>
21171 <description>NAK Interrupt</description>
21178 <description>NYET Interrupt (NYETIntrpt)</description>
21184 <description>No NYET interrupt</description>
21189 <description>NYET Interrupt</description>
21196 <description>Setup Packet Received</description>
21202 <description>No Setup packet received</description>
21207 <description>Setup packet received</description>
21216 <description>Device OUT Endpoint Transfer Size Register</description>
21224 <description>Transfer Size (XferSize)</description>
21230 <description>Packet Count (PktCnt)</description>
21236 <description>RxDPID</description>
21243 <description>DATA0</description>
21248 <description>DATA2 or 1 packet</description>
21253 <description>DATA1 or 2 packets</description>
21258 <description>MDATA or 3 packets</description>
21267 <description>Device OUT Endpoint DMA Address Register</description>
21275 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
21283 <description>Device Control OUT Endpoint Control Register</description>
21291 <description>Maximum Packet Size (MPS)</description>
21297 <description>USB Active Endpoint (USBActEP)</description>
21303 <description>Not Active</description>
21308 <description>USB Active Endpoint</description>
21315 <description>Endpoint Data PID (DPID)</description>
21322 <description>Endpoint Data PID not active</description>
21327 <description>Endpoint Data PID active</description>
21334 <description>NAK Status (NAKSts)</description>
21341 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
21346 … <description>The core is transmitting NAK handshakes on this endpoint</description>
21353 <description>Endpoint Type (EPType)</description>
21359 <description>Control</description>
21364 <description>Isochronous</description>
21369 <description>Bulk</description>
21374 <description>Interrupt</description>
21381 <description>STALL Handshake (Stall)</description>
21387 <description>STALL All non-active tokens</description>
21392 <description>STALL All Active Tokens</description>
21405 <description>No Clear NAK</description>
21410 <description>Clear NAK</description>
21417 <description>Set NAK (SNAK)</description>
21424 <description>No Set NAK</description>
21429 <description>Set NAK</description>
21436 <description>Set DATA0 PID (SetD0PID)</description>
21443 <description>Disables Set DATA0 PID or Do not force Even Frame</description>
21448 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
21455 <description>Set DATA1 PID (SetD1PID)</description>
21462 <description>Disables Set DATA1 PID or Do not force Odd Frame</description>
21467 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
21474 <description>Endpoint Disable (EPDis)</description>
21480 <description>No Action</description>
21485 <description>Disable Endpoint</description>
21492 <description>Endpoint Enable (EPEna)</description>
21498 <description>No Action</description>
21503 <description>Enable Endpoint</description>
21512 <description>Device OUT Endpoint Interrupt Register</description>
21520 <description>Transfer Completed Interrupt (XferCompl)</description>
21526 <description>No Transfer Complete Interrupt</description>
21531 <description>Transfer Complete Interrupt</description>
21538 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
21544 <description>No Endpoint Disabled Interrupt</description>
21549 <description>Endpoint Disabled Interrupt</description>
21556 <description>AHB Error (AHBErr)</description>
21562 <description>No AHB Error Interrupt</description>
21567 <description>AHB Error interrupt</description>
21574 <description>SETUP Phase Done (SetUp)</description>
21580 <description>No SETUP Phase Done</description>
21585 <description>SETUP Phase Done</description>
21592 <description>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</description>
21598 <description>No OUT Token Received When Endpoint Disabled</description>
21603 <description>OUT Token Received When Endpoint Disabled</description>
21610 <description>Status Phase Received for Control Write (StsPhseRcvd)</description>
21616 <description>No Status Phase Received for Control Write</description>
21621 <description>Status Phase Received for Control Write</description>
21628 <description>Back-to-Back SETUP Packets Received (Back2BackSETup)</description>
21634 <description>No Back-to-Back SETUP Packets Received</description>
21639 <description>Back-to-Back SETUP Packets Received</description>
21646 <description>OUT Packet Error (OutPktErr)</description>
21652 <description>No OUT Packet Error</description>
21657 <description>OUT Packet Error</description>
21664 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
21670 <description>No BNA interrupt</description>
21675 <description>BNA interrupt</description>
21682 <description>Packet Drop Status (PktDrpSts)</description>
21688 <description>No interrupt</description>
21693 <description>Packet Drop Status interrupt</description>
21700 <description>NAK Interrupt (BbleErr)</description>
21706 <description>No BbleErr interrupt</description>
21711 <description>BbleErr interrupt</description>
21718 <description>NAK Interrupt (NAKInterrupt)</description>
21724 <description>No NAK interrupt</description>
21729 <description>NAK Interrupt</description>
21736 <description>NYET Interrupt (NYETIntrpt)</description>
21742 <description>No NYET interrupt</description>
21747 <description>NYET Interrupt</description>
21754 <description>Setup Packet Received</description>
21760 <description>No Setup packet received</description>
21765 <description>Setup packet received</description>
21774 <description>Device OUT Endpoint Transfer Size Register</description>
21782 <description>Transfer Size (XferSize)</description>
21788 <description>Packet Count (PktCnt)</description>
21794 <description>RxDPID</description>
21801 <description>DATA0</description>
21806 <description>DATA2 or 1 packet</description>
21811 <description>DATA1 or 2 packets</description>
21816 <description>MDATA or 3 packets</description>
21825 <description>Device OUT Endpoint DMA Address Register</description>
21833 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
21841 <description>Device Control OUT Endpoint Control Register</description>
21849 <description>Maximum Packet Size (MPS)</description>
21855 <description>USB Active Endpoint (USBActEP)</description>
21861 <description>Not Active</description>
21866 <description>USB Active Endpoint</description>
21873 <description>Endpoint Data PID (DPID)</description>
21880 <description>Endpoint Data PID not active</description>
21885 <description>Endpoint Data PID active</description>
21892 <description>NAK Status (NAKSts)</description>
21899 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
21904 … <description>The core is transmitting NAK handshakes on this endpoint</description>
21911 <description>Endpoint Type (EPType)</description>
21917 <description>Control</description>
21922 <description>Isochronous</description>
21927 <description>Bulk</description>
21932 <description>Interrupt</description>
21939 <description>STALL Handshake (Stall)</description>
21945 <description>STALL All non-active tokens</description>
21950 <description>STALL All Active Tokens</description>
21963 <description>No Clear NAK</description>
21968 <description>Clear NAK</description>
21975 <description>Set NAK (SNAK)</description>
21982 <description>No Set NAK</description>
21987 <description>Set NAK</description>
21994 <description>Set DATA0 PID (SetD0PID)</description>
22001 <description>Disables Set DATA0 PID or Do not force Even Frame</description>
22006 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
22013 <description>Set DATA1 PID (SetD1PID)</description>
22020 <description>Disables Set DATA1 PID or Do not force Odd Frame</description>
22025 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
22032 <description>Endpoint Disable (EPDis)</description>
22038 <description>No Action</description>
22043 <description>Disable Endpoint</description>
22050 <description>Endpoint Enable (EPEna)</description>
22056 <description>No Action</description>
22061 <description>Enable Endpoint</description>
22070 <description>Device OUT Endpoint Interrupt Register</description>
22078 <description>Transfer Completed Interrupt (XferCompl)</description>
22084 <description>No Transfer Complete Interrupt</description>
22089 <description>Transfer Complete Interrupt</description>
22096 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
22102 <description>No Endpoint Disabled Interrupt</description>
22107 <description>Endpoint Disabled Interrupt</description>
22114 <description>AHB Error (AHBErr)</description>
22120 <description>No AHB Error Interrupt</description>
22125 <description>AHB Error interrupt</description>
22132 <description>SETUP Phase Done (SetUp)</description>
22138 <description>No SETUP Phase Done</description>
22143 <description>SETUP Phase Done</description>
22150 <description>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</description>
22156 <description>No OUT Token Received When Endpoint Disabled</description>
22161 <description>OUT Token Received When Endpoint Disabled</description>
22168 <description>Status Phase Received for Control Write (StsPhseRcvd)</description>
22174 <description>No Status Phase Received for Control Write</description>
22179 <description>Status Phase Received for Control Write</description>
22186 <description>Back-to-Back SETUP Packets Received (Back2BackSETup)</description>
22192 <description>No Back-to-Back SETUP Packets Received</description>
22197 <description>Back-to-Back SETUP Packets Received</description>
22204 <description>OUT Packet Error (OutPktErr)</description>
22210 <description>No OUT Packet Error</description>
22215 <description>OUT Packet Error</description>
22222 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
22228 <description>No BNA interrupt</description>
22233 <description>BNA interrupt</description>
22240 <description>Packet Drop Status (PktDrpSts)</description>
22246 <description>No interrupt</description>
22251 <description>Packet Drop Status interrupt</description>
22258 <description>NAK Interrupt (BbleErr)</description>
22264 <description>No BbleErr interrupt</description>
22269 <description>BbleErr interrupt</description>
22276 <description>NAK Interrupt (NAKInterrupt)</description>
22282 <description>No NAK interrupt</description>
22287 <description>NAK Interrupt</description>
22294 <description>NYET Interrupt (NYETIntrpt)</description>
22300 <description>No NYET interrupt</description>
22305 <description>NYET Interrupt</description>
22312 <description>Setup Packet Received</description>
22318 <description>No Setup packet received</description>
22323 <description>Setup packet received</description>
22332 <description>Device OUT Endpoint Transfer Size Register</description>
22340 <description>Transfer Size (XferSize)</description>
22346 <description>Packet Count (PktCnt)</description>
22352 <description>RxDPID</description>
22359 <description>DATA0</description>
22364 <description>DATA2 or 1 packet</description>
22369 <description>DATA1 or 2 packets</description>
22374 <description>MDATA or 3 packets</description>
22383 <description>Device OUT Endpoint DMA Address Register</description>
22391 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
22399 <description>Device Control OUT Endpoint Control Register</description>
22407 <description>Maximum Packet Size (MPS)</description>
22413 <description>USB Active Endpoint (USBActEP)</description>
22419 <description>Not Active</description>
22424 <description>USB Active Endpoint</description>
22431 <description>Endpoint Data PID (DPID)</description>
22438 <description>Endpoint Data PID not active</description>
22443 <description>Endpoint Data PID active</description>
22450 <description>NAK Status (NAKSts)</description>
22457 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
22462 … <description>The core is transmitting NAK handshakes on this endpoint</description>
22469 <description>Endpoint Type (EPType)</description>
22475 <description>Control</description>
22480 <description>Isochronous</description>
22485 <description>Bulk</description>
22490 <description>Interrupt</description>
22497 <description>STALL Handshake (Stall)</description>
22503 <description>STALL All non-active tokens</description>
22508 <description>STALL All Active Tokens</description>
22521 <description>No Clear NAK</description>
22526 <description>Clear NAK</description>
22533 <description>Set NAK (SNAK)</description>
22540 <description>No Set NAK</description>
22545 <description>Set NAK</description>
22552 <description>Set DATA0 PID (SetD0PID)</description>
22559 <description>Disables Set DATA0 PID or Do not force Even Frame</description>
22564 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
22571 <description>Set DATA1 PID (SetD1PID)</description>
22578 <description>Disables Set DATA1 PID or Do not force Odd Frame</description>
22583 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
22590 <description>Endpoint Disable (EPDis)</description>
22596 <description>No Action</description>
22601 <description>Disable Endpoint</description>
22608 <description>Endpoint Enable (EPEna)</description>
22614 <description>No Action</description>
22619 <description>Enable Endpoint</description>
22628 <description>Device OUT Endpoint Interrupt Register</description>
22636 <description>Transfer Completed Interrupt (XferCompl)</description>
22642 <description>No Transfer Complete Interrupt</description>
22647 <description>Transfer Complete Interrupt</description>
22654 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
22660 <description>No Endpoint Disabled Interrupt</description>
22665 <description>Endpoint Disabled Interrupt</description>
22672 <description>AHB Error (AHBErr)</description>
22678 <description>No AHB Error Interrupt</description>
22683 <description>AHB Error interrupt</description>
22690 <description>SETUP Phase Done (SetUp)</description>
22696 <description>No SETUP Phase Done</description>
22701 <description>SETUP Phase Done</description>
22708 <description>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</description>
22714 <description>No OUT Token Received When Endpoint Disabled</description>
22719 <description>OUT Token Received When Endpoint Disabled</description>
22726 <description>Status Phase Received for Control Write (StsPhseRcvd)</description>
22732 <description>No Status Phase Received for Control Write</description>
22737 <description>Status Phase Received for Control Write</description>
22744 <description>Back-to-Back SETUP Packets Received (Back2BackSETup)</description>
22750 <description>No Back-to-Back SETUP Packets Received</description>
22755 <description>Back-to-Back SETUP Packets Received</description>
22762 <description>OUT Packet Error (OutPktErr)</description>
22768 <description>No OUT Packet Error</description>
22773 <description>OUT Packet Error</description>
22780 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
22786 <description>No BNA interrupt</description>
22791 <description>BNA interrupt</description>
22798 <description>Packet Drop Status (PktDrpSts)</description>
22804 <description>No interrupt</description>
22809 <description>Packet Drop Status interrupt</description>
22816 <description>NAK Interrupt (BbleErr)</description>
22822 <description>No BbleErr interrupt</description>
22827 <description>BbleErr interrupt</description>
22834 <description>NAK Interrupt (NAKInterrupt)</description>
22840 <description>No NAK interrupt</description>
22845 <description>NAK Interrupt</description>
22852 <description>NYET Interrupt (NYETIntrpt)</description>
22858 <description>No NYET interrupt</description>
22863 <description>NYET Interrupt</description>
22870 <description>Setup Packet Received</description>
22876 <description>No Setup packet received</description>
22881 <description>Setup packet received</description>
22890 <description>Device OUT Endpoint Transfer Size Register</description>
22898 <description>Transfer Size (XferSize)</description>
22904 <description>Packet Count (PktCnt)</description>
22910 <description>RxDPID</description>
22917 <description>DATA0</description>
22922 <description>DATA2 or 1 packet</description>
22927 <description>DATA1 or 2 packets</description>
22932 <description>MDATA or 3 packets</description>
22941 <description>Device OUT Endpoint DMA Address Register</description>
22949 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
22957 <description>Power and Clock Gating Control Register</description>
22965 <description>Stop Pclk (StopPclk)</description>
22971 <description>Disable Stop Pclk</description>
22976 <description>Enable Stop Pclk</description>
22983 <description>Gate Hclk (GateHclk)</description>
22989 … <description>Clears this bit when the USB is resumed or a new session starts</description>
22994 …<description>Sets this bit to gate hclk to modules when the USB is suspended or the session is not…
23001 <description>Reset Power-Down Modules (RstPdwnModule)</description>
23007 <description>Power is turned on</description>
23012 <description>Power is turned off</description>
23019 <description>Enable Sleep Clock Gating</description>
23025 <description>The PHY clock is not gated in Sleep state</description>
23030 … <description>The Core internal clock gating is enabled in Sleep state</description>
23037 <description>PHY In Sleep</description>
23044 <description>Phy not in Sleep state</description>
23049 <description>Phy in Sleep state</description>
23056 <description>L1 Deep Sleep</description>
23063 <description>Non Deep Sleep</description>
23068 <description>Deep Sleep</description>
23075 <description>Restore Mode (RestoreMode)</description>
23081 …description>In Host mode,this bit indicates Host-initiated Resume and Reset. In Device mode, this …
23086 …description>In Host mode,this bit indicates Device-initiated Remote Wakeup. In Device mode, this b…
23093 <description>Essential Register Values Restored (EssRegRestored)</description>
23100 <description>Register values of essential registers are not restored</description>
23105 … <description>Register values of essential registers have been restored</description>
23112 <description>Restore Value (RestoreValue)</description>
23120 <description>Global STAR Fix Disable Register</description>
23128 …<description>Disable the STAR fix added for Device controller to go back to low power mode when Ho…
23134 …<description>Device controller goes back into SUSPENDED state when host ignores Remote Wakeup</des…
23139 …<description>Device controller waits indefinitely without entering SUSPENDED state when host ignor…
23146 …<description>Disable the STAR fix added for Device controller to detect lineK and move to RESUMING…
23152 <description>Device controller detects line K and resumes</description>
23157 <description>Device controller does not detect line K and resume</description>
23164 …description>Disable the STAR fix added for Device controller to reject DATA0 for the first Control…
23170 <description>Transaction Error reported when host sends DATA0 PID</description>
23175 … <description>Transaction Error not reported when host sends DATA0 PID</description>
23182 …<description>Disable the STAR fix added for Host controller to flag error for SSPLIT STALL/NYET</d…
23188 … <description>Transaction Error reported when device sends STALL/NYET for SSPLIT</description>
23193 … <description>Transaction Error not reported when device sends STALL/NYET for SSPLIT</description>
23200 …<description>Disable the STAR fix added for Host controller to accept DATA1 PID from device for IS…
23206 …<description>Transaction Error not reported when device sends DATA1 PID for ISOC Split</descriptio…
23211 … <description>Transaction Error reported when device sends DATA1 PID for ISOC Split</description>
23218 …<description>Disable the STAR fix added for Host controller to handle Faulty cable scenarios</desc…
23224 <description>Fix for handling faulty cable enabled</description>
23229 <description>Fix for handling faulty cable disabled</description>
23236 …<description>Disable the STAR fix added for Host controller LS mode IPG increment from 2 LS bit ti…
23242 <description>Host LS mode IPG is 3 LS bit times</description>
23247 <description>Host LS mode IPG is 2 LS bit times</description>
23254 …<description>Disable the STAR fix added for Device controller to transition to IDLE state during F…
23260 … <description>Device controller transitions to IDLE state during FS device disconnect</description>
23265 …<description>Device controller does not transition to IDLE state during FS device disconnect</desc…
23272 …<description>Disable the STAR fix added for Device controller to not start Remote Wakeup signallin…
23278 …<description>Device controller does not start remote wakeup signalling when host resume has alread…
23283 …<description>Device controller is allowed to start remote wakeup signalling when host resume has a…
23290 …<description>Disable the STAR fix added for Device controller to not hang when Remote Wakeup signa…
23296 …<description>Device controller does not hang when remote wakeup signalling clashes with host resum…
23301 …<description>Device controller hangs when remote wakeup signalling clashes with host resume during…
23308 …description>Disable the STAR fix added for Host controller to wait for IPG duration to send next t…
23314 <description>Host controller checks IPG after NAK/STALL for IN token</description>
23319 … <description>Host controller does not check IPG after NAK/STALL for IN token</description>
23326 …description>Disable the STAR fix added for Host controller to increase the gap between utmi_xcvrse…
23332 …<description>Host controller asserts utmi_txvalid at least 2 utmi_clk cycles after utmi_xcvrselect…
23337 …<description>Host controller can assert utmi_txvalid after 1 utmi_clk cycle of utmi_xcvrselect swi…
23344 …description>Disable the STAR fix added for Host controller to increase the preamble transceiver se…
23350 …description>Host controller waits for previous functional register update to complete before switc…
23355 …description>Host controller does not wait for the previous functional register update to complete …
23362 …description>Disable the STAR fix added for Host controller to report transaction error when DATA0 …
23368 …<description>Host controller reports transaction error when DATA0 PID is received for CTRL STATUS …
23373 …<description>Host controller retries the transfer when DATA0 PID is received for CTRL STATUS IN tr…
23380 …<description>Disable the correction to OpMode/XcvrSel/TermSel on UTMI Interface in Host mode.</des…
23386 …<description>Opmode, XcvrSel, TermSel are changed by the Host Controller after TxValid goes LOW (1…
23391 …description>Opmode, XcvrSel, TermSel are changed by the Host Controller without waiting for TxVali…
23398 …<description>Disable the STAR fix added for correcting Opmode and XcvrSel on UTMI Interface when r…
23404 …<description>Valid Combination of Opmode and XcvrSel is driven when reset is detected in suspend s…
23409 …<description>Invalid Combination of Opmode and XcvrSel is driven when reset is detected in suspend…
23416 …<description>Disable the STAR fix added for correcting Txvalid deassertion on UTMI Interface when …
23422 …<description>Txvalid is deasserted during soft disconnect after receiving Txready from the PHY</de…
23427 …<description>Txvalid is deasserted during soft disconnect without waiting for Txready from the PHY…
23434 …<description>Disable the STAR fix added for correcting Host behavior when port is disabled.</descr…
23440 <description>Txvalid is not asserted when port is disabled</description>
23445 <description>Txvalid can be asserted when port is disabled</description>
23456 <description>Unspecified</description>
23464 <description>Description collection: Data FIFO Access Register Map 0</description>
23473 <description>Unspecified</description>
23481 <description>Description collection: Data FIFO Direct Access Register Map</description>
23492 <description>I3CCORE 0</description>
23507 <description>Unspecified</description>
23513 <description>DWC_mipi_i3c control Register</description>
23521 <description>I3C Broadcast Address include</description>
23527 <description>Unspecified</description>
23532 <description>Unspecified</description>
23539 <description>I2C Slave Present</description>
23545 <description>Unspecified</description>
23550 <description>Unspecified</description>
23557 <description>Hot-Join ACK/NACK Control</description>
23563 <description>Unspecified</description>
23568 <description>Unspecified</description>
23575 <description>Idle Count Multiplier</description>
23581 <description>Unspecified</description>
23586 <description>Unspecified</description>
23591 <description>Unspecified</description>
23596 <description>Unspecified</description>
23603 <description>This field is used in Slave mode of operation.</description>
23609 <description>DMA Handshake Interface Enable</description>
23615 <description>The DMA handshake control has no significance.</description>
23620 … <description>Enables the DMA handshake control to interact with external DMA.</description>
23627 <description>DWC_mipi_i3c Abort</description>
23633 <description>DWC_mipi_i3c Resume</description>
23639 <description>Controls whether or not DWC_mipi_i3c is enabled.</description>
23645 <description>Disables the DWC_mipi_i3c controller</description>
23650 <description>Enables the DWC_mipi_i3c controller.</description>
23659 …<description>In the master mode of operation this Register is used to program the Device Dynamic A…
23667 <description>Device Static Address.</description>
23673 <description>Static Address Valid.</description>
23679 <description>Unspecified</description>
23684 <description>Unspecified</description>
23691 <description>Device Dynamic Address.</description>
23697 <description>Dynamic Address Valid</description>
23703 <description>Unspecified</description>
23708 <description>Unspecified</description>
23717 <description>Hardware Capability register</description>
23725 <description>Reflects the IC_DEVICE_ROLE Configurable Parameter.</description>
23732 <description>Master Only</description>
23737 <description>Programmable Master-Slave</description>
23742 <description>Secondary Master</description>
23747 <description>Slave Only</description>
23754 <description>Reflects the IC_SPEED_HDR_DDR Configurable Parameter.</description>
23761 <description>HDR-DDR not supported</description>
23766 <description>HDR-DDR supported</description>
23773 <description>Reflects the IC_SPEED_HDR_TS Configurable Parameter.</description>
23780 <description>HDR-TS not supported</description>
23785 <description>HDR-TS supported</description>
23792 <description>Reflects the IC_CLK_PERIOD Configurable Parameter</description>
23799 <description>Reflects the IC_HDR_TX_CLK_PERIOD Configurable Parameter.</description>
23806 <description>Reflects the IC_HAS_DMA Configurable Parameter.</description>
23813 <description>Reflects the IC_SLV_HJ Configurable Parameter.</description>
23820 <description>Reflects the IC_SLV_IBI Configurable Parameter.</description>
23829 <description>Command Queue Port.</description>
23837 <description>32 bit command</description>
23846 <description>Response Queue Port</description>
23854 <description>32 bit Response</description>
23863 <description>Receive Data Port Register</description>
23871 <description>Receive Data Port.</description>
23880 <description>Transmit Data Port Register</description>
23889 <description>Transmit Data Port</description>
23898 <description>In-Band Interrupt Queue Data Register</description>
23906 <description>In-Band Interrupt Data</description>
23915 <description>In-Band Interrupt Queue Status Register</description>
23924 <description>In-Band Interrupt data length.</description>
23931 <description>IBI Identifier.</description>
23938 … <description>The acknowledge bit of the IBI Received Status (IBISTS) bitfield.</description>
23945 <description>Responded with ACK</description>
23950 <description>Responded with NACK</description>
23959 <description>Queue Threshold Control Register</description>
23967 <description>Command Buffer Empty Threshold Value.</description>
23973 <description>Response Buffer Threshold Value.</description>
23979 <description>In-Band Interrupt Status Threshold Value.</description>
23987 <description>Data Buffer Threshold Control Register</description>
23995 <description>Transmit Buffer Threshold Value</description>
24001 <description>Unspecified</description>
24006 <description>Unspecified</description>
24011 <description>Unspecified</description>
24016 <description>Unspecified</description>
24021 <description>Unspecified</description>
24026 <description>Unspecified</description>
24033 <description>Receive Buffer Threshold Value</description>
24039 <description>Unspecified</description>
24044 <description>Unspecified</description>
24049 <description>Unspecified</description>
24054 <description>Unspecified</description>
24059 <description>Unspecified</description>
24064 <description>Unspecified</description>
24071 <description>Transfer Start Threshold Value</description>
24077 <description>Unspecified</description>
24082 <description>Unspecified</description>
24087 <description>Unspecified</description>
24092 <description>Unspecified</description>
24097 <description>Unspecified</description>
24102 <description>Unspecified</description>
24109 <description>Receive Start Threshold Value</description>
24115 <description>Unspecified</description>
24120 <description>Unspecified</description>
24125 <description>Unspecified</description>
24130 <description>Unspecified</description>
24135 <description>Unspecified</description>
24140 <description>Unspecified</description>
24149 …<description>This Register is used to control whether or not to intimate the application if an IBI…
24157 <description>Notify Rejected Hot-Join Control.</description>
24163 <description>Unspecified</description>
24168 <description>Unspecified</description>
24175 <description>Notify Rejected Master Request Control.</description>
24181 …description>Suppress passing the IBI Status to the IBI FIFO (hence not notifying the application) …
24186 …description>Writes IBI Status to the IBI FIFO (hence notifying the application) when a MR Request …
24193 <description>Notify Rejected Slave Interrupt Request Control.</description>
24199 …description>Suppress passing the IBI Status to the IBI FIFO (hence not notifying the application) …
24204 …description>Writes IBI Status to the IBI FIFO (hence notifying the application) when a Slave Inter…
24213 <description>IBI Master Request Rejection Control Register.</description>
24221 <description>In-band Master Request Reject.</description>
24227 <description>ACK Master Request.</description>
24232 … <description>NACK and send Directed DISEC CCC to disable the interrupting slave.</description>
24241 <description>IBI SIR Request Rejection Control</description>
24249 <description>In-band Slave Interrupt Request Reject</description>
24255 <description>ACK the SIR Request.</description>
24260 <description>NACK and send directed auto disable CCC.</description>
24269 …<description>This Register is used for general software reset and for individual buffer reset.</de…
24277 <description>Core Software Reset.</description>
24283 <description>Command Queue Software Reset</description>
24289 <description>Response Queue Software Reset</description>
24295 <description>Transmit Buffer Software Reset</description>
24301 <description>Receive Buffer Software Reset.</description>
24307 <description>IBI Queue Software Reset.</description>
24313 <description>Bus Reset type</description>
24319 <description>Exit Pattern.</description>
24324 <description>SCL_LOW_RESET Pattern.</description>
24331 <description>Bus Reset.</description>
24339 …<description>This register indicates the status/values of some events/controls that are relavant t…
24347 <description>Slave Interrupt Request Enable.</description>
24354 <description>Master Request Enable.</description>
24361 <description>Hot-Join Interrupt Enable</description>
24367 <description>Activity State Status.</description>
24374 <description>Unspecified</description>
24379 <description>Unspecified</description>
24384 <description>Unspecified</description>
24389 <description>Unspecified</description>
24396 <description>MRL Updated Status.</description>
24402 <description>MWL Updated Status.</description>
24410 <description>Interrupt Status Register</description>
24418 <description>Transmit Buffer Threshold Status</description>
24425 <description>Receive Buffer Threshold Status.</description>
24432 <description>IBI Buffer Threshold Status.</description>
24439 <description>Command Queue Ready.</description>
24446 <description>Response Queue Ready Status.</description>
24453 <description>Transfer Abort Status.</description>
24459 <description>CCC Table Updated Status.</description>
24465 <description>Dynamic Address Assigned Status.</description>
24471 <description>Transfer Error Status.</description>
24477 <description>Define Slave CCC Received Status.</description>
24483 <description>Read Request Received.</description>
24489 <description>IBI status is updated.</description>
24495 …<description>This interrupt is set when the role of the controller changes from being a Master to …
24501 <description>Bus Reset Pattern Generation Done Status.</description>
24509 <description>Interrupt Status Enable Register.</description>
24517 <description>Transmit Buffer Threshold Status Enable.</description>
24523 <description>Receive Buffer Threshold Status Enable</description>
24529 <description>IBI Buffer Threshold Status Enable.</description>
24535 <description>Command Queue Ready Status Enable</description>
24541 <description>Response Queue Ready Status Enable</description>
24547 <description>Transfer Abort Status Enable.</description>
24553 <description>CCC Table Updated Status Enable.</description>
24559 <description>Dynamic Address Assigned Status Enable</description>
24565 <description>Transfer Error Status Enable</description>
24571 <description>Define Slave CCC Received Status Enable</description>
24577 <description>Read Request Received Status Enable</description>
24583 <description>IBI Updated Status Enable</description>
24589 <description>Bus owner Updated Status Enable</description>
24595 <description>Bus Reset Pattern Generation Done Status Enable.</description>
24603 <description>Interrupt Signal Enable Register</description>
24611 <description>Transmit Buffer Threshold Signal Enable</description>
24617 <description>Receive Buffer Threshold Signal Enable</description>
24623 <description>IBI Buffer Threshold Signal Enable</description>
24629 <description>Command Queue Ready Signal Enable</description>
24635 <description>Response Queue Ready Signal Enable</description>
24641 <description>Transfer Abort Signal Enable</description>
24647 <description>CCC Table Updated Signal Enable</description>
24653 <description>Dynamic Address Assigned Signal Enable</description>
24659 <description>Transfer Error Signal Enable</description>
24665 <description>Define Slave CCC Received Signal Enable</description>
24671 <description>Read Request Received Signal Enable</description>
24677 <description>IBI Updated Signal Enable</description>
24683 <description>Bus owner Updated Signal Enable</description>
24689 <description>Bus Reset Pattern Generation Done Signal Enable.</description>
24697 <description>Interrupt Force Enable Register</description>
24705 <description>Transmit Buffer Threshold Force Enable</description>
24712 <description>Receive Buffer Threshold Force Enable</description>
24719 <description>IBI Buffer Threshold Force Enable</description>
24726 <description>Command Queue Ready Force Enable</description>
24733 <description>Response Queue Ready Force Enable</description>
24740 <description>Transfer Abort Force Enable</description>
24747 <description>CCC Table Updated Force Enable</description>
24754 <description>Dynamic Address Assigned Force Enable</description>
24761 <description>Transfer Error Force Enable</description>
24768 <description>Define Slave CCC Received Force Enable</description>
24775 <description>Read Request Received Force Enable</description>
24782 <description>IBI Updated Force Enable</description>
24789 <description>Bus owner Updated Force Enable</description>
24796 <description>Bus Reset Pattern Generation Done Force Enable.</description>
24805 <description>Queue Status Level Register.</description>
24813 <description>Command Queue Empty Locations.</description>
24820 <description>Response Buffer Level Value.</description>
24827 <description>IBI Buffer Level Value.</description>
24834 <description>IBI Buffer Status Count.</description>
24843 <description>Data Buffer Status Level Register.</description>
24851 <description>Transmit Buffer Empty Level Value.</description>
24858 <description>Receive Buffer Level Value.</description>
24867 …<description>The user can get status of the DWC_mipi_i3c Controller from this 32-bit read only reg…
24875 …<description>This bit is used to check the SCL line level to recover from errors and for debugging…
24882 …<description>This bit is used to check the SDA line level to recover from errors and for debugging…
24889 … <description>This Bit is used to check whether the Master is Current Master or not.</description>
24896 <description>Master is not Current Master</description>
24901 <description>Master is Current Master</description>
24908 <description>Transfer Type Status</description>
24915 …<description>Controller is in Idle state, waiting for commands from application or Slave initated …
24920 <description>Broadcast CCC Write Transfer.</description>
24925 <description>Directed CCC Write Transfer.</description>
24930 <description>Directed CCC Read Transfer.</description>
24935 <description>ENTDAA Address Assignment Transfer.</description>
24940 <description>SETDASA Address Assignment Transfer.</description>
24945 <description>Private I3C SDR Write Transfer.</description>
24950 <description>Private I3C SDR Read Transfer.</description>
24955 <description>Private I2C SDR Write Transfer.</description>
24960 <description>Private I2C SDR Read Transfer.</description>
24965 <description>Private HDR Ternary Symbol(TS) Write Transfer.</description>
24970 <description>Private HDR Ternary Symbol(TS) Read Transfer.</description>
24975 <description>Private HDR Double-Data Rate(DDR) Write Transfer.</description>
24980 <description>Private HDR Double-Data Rate(DDR) Read Transfer.</description>
24985 <description>Servicing In-Band Interrupt Transfer.</description>
24990 …<description>Halt state. Controller is in Halt State, waiting for the application to resume throug…
24997 <description>Current Master Transfer State Status.</description>
25004 …<description>Controller is Idle state, waiting for commands from application or Slave initated In-…
25009 <description>START Generation State.</description>
25014 <description>RESTART Generation State.</description>
25019 <description>STOP Genration State.</description>
25024 … <description>START Hold Generation for the Slave Initiated START State.</description>
25029 … <description>Broadcast Write Address Header(7h7E,W) Generation State.</description>
25034 … <description>Broadcast Read Address Header(7h7E,R) Generation State.</description>
25039 <description>Dynamic Address Assignment State.</description>
25044 <description>Slave Address Generation State.</description>
25049 <description>CCC Byte Generation State.</description>
25054 <description>HDR Command Generation State.</description>
25059 <description>Write Data Transfer State.</description>
25064 <description>Read Data Transfer State.</description>
25069 <description>In-Band Interrupt(SIR) Read Data State.</description>
25074 <description>In-Band Interrupt Auto-Disable State</description>
25079 <description>HDR-DDR CRC Data Generation/Receive State.</description>
25084 <description>Clock Extension State.</description>
25089 <description>Halt State.</description>
25096 …<description>This field reflects the Transaction-ID of the current executing command.</description>
25103 …<description>This field reflects whether the Master Controller is in Idle state or not.</descripti…
25110 <description>Unspecified</description>
25115 <description>Unspecified</description>
25124 …<description>The user can get status of the DWC_mipi_i3c Controller from this 32-bit read only reg…
25133 …<description>This bit is used to check the SCL line level to recover from errors and for debugging…
25140 …<description>This bit is used to check the SDA line level to recover from errors and for debugging…
25147 … <description>This Bit is used to check whether the Master is Current Master or not.</description>
25154 <description>Master is not Current Master</description>
25159 <description>Master is Current Master</description>
25166 <description>Transfer Type Status</description>
25173 <description>Controller is in Idle state.</description>
25178 <description>Hot-Join transfer state.</description>
25183 <description>IBI transfer state.</description>
25188 <description>Master write transfer ongoing.</description>
25193 <description>Read data prefetch state.</description>
25198 <description>Master read transfer ongoing.</description>
25203 … <description>Slave controller in Halt State waiting for resume from application.</description>
25210 <description>Current Master Transfer State Status.</description>
25217 …<description>This field reflects the Transaction-ID of the current executing command.</description>
25224 …<description>This field reflects whether the Master Controller is in Idle state or not.</descripti…
25231 <description>Unspecified</description>
25236 <description>Unspecified</description>
25245 <description>Device Operating Status Register.</description>
25253 <description>Pending Interrupt</description>
25260 <description>Protocol Error</description>
25267 <description>Activity Mode</description>
25274 <description>Underflow error</description>
25281 <description>Slave Busy</description>
25288 <description>Overflow Error</description>
25295 <description>Data not ready</description>
25302 <description>Buffer not available</description>
25309 <description>Frame Error</description>
25318 <description>Pointer for Device Address Table</description>
25326 <description>Start Address of Device Address Table.</description>
25333 <description>Depth of Device Address Table</description>
25342 <description>Pointer for Device Characteristics Table</description>
25350 <description>Start Address of Device Characteristics Table.</description>
25357 <description>Depth of Device Characteristics Table</description>
25364 <description>Current index of Device Characteristics Table.</description>
25372 <description>Pointer for Vendor Specific Registers.</description>
25380 <description>Start Address of Vendor specific registers.</description>
25389 <description>I3C MIPI Manufacturer ID Register.</description>
25397 <description>Specifies the Provisional ID Type Selector (PID[32]).</description>
25403 <description>Specifies the MIPI Manufacturer ID.</description>
25411 <description>I3C Normal Provisional ID Register.</description>
25419 … <description>Specifies the additional 12-bit ID of DWC_mipi_i3c device (PID[11:0]).</description>
25425 … <description>This field is used to program the instance ID of the Slave.</description>
25431 <description>Specifies the Part ID of DWC_mipi_i3c device (PID[31:16])</description>
25439 <description>I3C Slave Characteristic Register.</description>
25447 …<description>Max Data Speed Limitation field in Bus Characteristic Register (BCR[0]).</description>
25453 … <description>IBI Request Capable field in Bus Characteristic Register (BCR[1]).</description>
25460 … <description>IBI Payload field in Bus Characteristic Register (BCR[2]).</description>
25467 … <description>Offline Capable field in Bus Characteristic Register (BCR[3]).</description>
25474 … <description>Bridge Identifier field in Bus Characteristic Register (BCR[4]).</description>
25481 …<description>SDR Only or SDR and HDR Capable field in Bus Characteristic Register (BCR[5]).</descr…
25487 … <description>Device Role field in Bus Characteristic Register (BCR[7:6]).</description>
25493 <description>I3C Device Characteristic Value.</description>
25499 <description>I3C Device HDR Capability Register Value.</description>
25508 <description>I3C Max Write/Read Length Register.</description>
25516 <description>I3C Device Max Write Length</description>
25523 <description>I3C Device Max Read Length.</description>
25532 <description>MXDS Maximum Read Turnaround Time.</description>
25540 …<description>Specifies the maximum read turnaround time (in microseconds (us)) of DWC_mipi_i3c Sla…
25549 …<description>The values in this register are returned by the slave as GETACCMST CCC data.</descrip…
25557 …<description>Specifies the Maximum Sustained Data Rate for non-CCC messages sent by Master Device …
25563 <description>12.5MHz</description>
25568 <description>8MHZ</description>
25573 <description>6MHz</description>
25578 <description>4MHz</description>
25583 <description>2MHz</description>
25590 …<description>Specifies the Maximum Sustained Data Rate for non-CCC messages sent by DWC_mipi_i3c S…
25596 <description>12.5MHz</description>
25601 <description>8MHZ</description>
25606 <description>6MHz</description>
25611 <description>4MHz</description>
25616 <description>2MHz</description>
25623 …<description>Specifies the clock to data turnaround time (Tsco parameter) of DWC_mipi_i3c Slave de…
25629 <description>8ns</description>
25634 <description>9ns</description>
25639 <description>10ns</description>
25644 <description>11ns</description>
25649 <description>12ns</description>
25658 <description>This register is used in slave mode of operation.</description>
25666 <description>Slave Interrupt Request</description>
25672 <description>Slave Interrupt Request Control</description>
25678 <description>Send the Assigned Dynamic Address</description>
25685 <description>Master Request</description>
25691 <description>IBI Completion Status</description>
25698 <description>IBI accepted by the Master (ACK response received)</description>
25703 <description>IBI Not Attempted</description>
25712 <description>TSP/TSL Symbol Timing Register</description>
25720 <description>TSP/TSL Symbol Count Value.</description>
25728 <description>Device Control Extended register.</description>
25736 …<description>This bit is used to select the Device Operation Mode before the controller is enabled…
25742 <description>Unspecified</description>
25747 <description>Unspecified</description>
25754 …<description>In Slave mode of operation, this bit serves as a control to ACK/NACK GETACCMST CCC fr…
25760 <description>ACK GETACCMST CCC</description>
25765 <description>NACK GETACCMST CCC</description>
25774 <description>SCL I3C Open Drain Timing Register</description>
25782 <description>I3C Open Drain Low Count.</description>
25788 <description>I3C Open Drain High Count.</description>
25796 <description>SCL I3C Push Pull Timing Register</description>
25804 <description>I3C Push Pull Low Count.</description>
25810 <description>I3C Push Pull High Count.</description>
25818 <description>SCL I2C Fast Mode Timing Register</description>
25826 <description>I2C Fast Mode Low Count</description>
25832 <description>I2C Fast Mode High Count</description>
25840 <description>SCL I2C Fast Mode Plus Timing Register</description>
25848 <description>I2C Fast Mode Plus Low Count</description>
25854 <description>I2C Fast Mode Plus High Count</description>
25862 <description>SCL Extended Low Count Timing Register.</description>
25870 <description>I3C Extended Low Count Register 1</description>
25876 <description>I3C Extended Low Count Register 2</description>
25882 <description>I3C Extended Low Count Register 3</description>
25888 <description>I3C Extended Low Count Register 4</description>
25896 <description>SCL Termination Bit Low Count Timing Register</description>
25904 <description>I3C Read Termination Bit Low count.</description>
25910 <description>I3C HDR Ternary Skew Count.</description>
25918 <description>SDA Hold and Mode Switch Delay Timing Register</description>
25926 …<description>This field controls the hold time (in term of the core clock period) of the transmit …
25934 <description>Bus Free and Available Timing Register</description>
25942 … <description>This register field is used only in Master mode of operation</description>
25948 … <description>This register field is used only in Slave mode of operation</description>
25956 <description>Bus Idle Timing Register</description>
25964 <description>Bus Idle Count Value.</description>
25972 …<description>The SCL Low Master Extended Timeout register is used to define the duration of the SC…
25980 …<description>This count defines the number of core clock periods to count for generation of the SC…
25988 … <description>This register reflects the current release number of DWC_mipi_i3c</description>
25996 <description>Current release number</description>
26005 … <description>This register reflects the current release type of DWC_mipi_i3c.</description>
26013 <description>Current release type</description>
26022 …<description>This register reflects the configured size of the Data Buffer and Queues in DWC_mipi_…
26030 <description>Transmit Data Buffer Size</description>
26037 <description>2 DWORDS</description>
26042 <description>4 DWORDS</description>
26047 <description>8 DWORDS</description>
26052 <description>16 DWORDS</description>
26057 <description>32 DWORDS</description>
26062 <description>64 DWORDS</description>
26069 <description>Receive Data Buffer Size</description>
26076 <description>2 DWORDS</description>
26081 <description>4 DWORDS</description>
26086 <description>8 DWORDS</description>
26091 <description>16 DWORDS</description>
26096 <description>32 DWORDS</description>
26101 <description>64 DWORDS</description>
26108 <description>Command Queue Size</description>
26115 <description>2 DWORDS</description>
26120 <description>4 DWORDS</description>
26125 <description>8 DWORDS</description>
26130 <description>16 DWORDS</description>
26137 <description>Response Queue Size</description>
26144 <description>2 DWORDS</description>
26149 <description>4 DWORDS</description>
26154 <description>8 DWORDS</description>
26159 <description>16 DWORDS</description>
26166 <description>IBI Queue Size</description>
26173 <description>2 DWORDS</description>
26178 <description>4 DWORDS</description>
26183 <description>8 DWORDS</description>
26188 <description>16 DWORDS</description>
26199 <description>Unspecified</description>
26205 …<description>Description cluster: Device Characteristic Table Location-1 of Device [n]</descriptio…
26213 <description>The LSB 32-bit value of Provisional-ID</description>
26222 …<description>Description cluster: Device Characteristic Table Location-2 of Device [n]</descriptio…
26230 <description>The MSB 16-bit value of Provisional-ID</description>
26239 …<description>Description cluster: Device Characteristic Table Location-3 of Device [n]</descriptio…
26247 <description>Device Characteristic Value</description>
26254 <description>Bus Characteristic Value</description>
26263 …<description>Description cluster: Device Characteristic Table Location-4 of Device [n]</descriptio…
26271 <description>Device Dynamic Address assigned.</description>
26283 …<description>Description collection: Secondary Master Device Characteristic Table Location of Devi…
26291 <description>The Dynamic Addr of Device [n]</description>
26298 <description>The DCR TYPE of Device [n]</description>
26305 <description>The BCR TYPE of Device [n]</description>
26312 <description>The Static Addr of Device [n]</description>
26323 <description>Description collection: Device Address Table of Device [n]</description>
26331 <description>Device Static Address.</description>
26337 <description>Device Dynamic Address with parity.</description>
26343 …<description>This field is used to set the Device NACK Retry count for the particular device.</des…
26349 <description>Legacy I2C device or not.</description>
26358 <description>Unspecified</description>
26364 <description>Unspecified</description>
26370 … <description>This register contains the source address of the DMA transfer.</description>
26378 <description>Current Source Address of DMA transfer.</description>
26386 … <description>This register contains the destination address of the DMA transfer.</description>
26394 <description>Current Destination address of DMA transfer.</description>
26402 … <description>This register contains fields that control the DMA transfer.</description>
26410 <description>Interrupt Enable Bit.</description>
26416 <description>Unspecified</description>
26421 <description>Unspecified</description>
26428 <description>Destination Transfer Width.</description>
26434 <description>Unspecified</description>
26439 <description>Unspecified</description>
26444 <description>Unspecified</description>
26449 <description>Unspecified</description>
26454 <description>Unspecified</description>
26459 <description>Unspecified</description>
26464 <description>Unspecified</description>
26469 <description>Unspecified</description>
26476 <description>Reserved field - read-only</description>
26483 <description>Destination Address Increment.</description>
26489 <description>Unspecified</description>
26494 <description>Unspecified</description>
26499 <description>Unspecified</description>
26504 <description>Unspecified</description>
26511 <description>Source Address Increment.</description>
26517 <description>Unspecified</description>
26522 <description>Unspecified</description>
26527 <description>Unspecified</description>
26532 <description>Unspecified</description>
26539 <description>Destination Burst Transaction Length.</description>
26545 <description>Unspecified</description>
26550 <description>Unspecified</description>
26555 <description>Unspecified</description>
26560 <description>Unspecified</description>
26565 <description>Unspecified</description>
26570 <description>Unspecified</description>
26575 <description>Unspecified</description>
26580 <description>Unspecified</description>
26587 <description>Source Burst Transaction Length.</description>
26593 <description>Unspecified</description>
26598 <description>Unspecified</description>
26603 <description>Unspecified</description>
26608 <description>Unspecified</description>
26613 <description>Unspecified</description>
26618 <description>Unspecified</description>
26623 <description>Unspecified</description>
26628 <description>Unspecified</description>
26635 <description>Reserved field - read-only</description>
26642 <description>Destination scatter enable.</description>
26648 <description>Unspecified</description>
26653 <description>Unspecified</description>
26660 <description>Reserved field - read-only</description>
26667 <description>Transfer Type and Flow Control.</description>
26673 <description>Unspecified</description>
26678 <description>Unspecified</description>
26683 <description>Unspecified</description>
26688 <description>Unspecified</description>
26693 <description>Unspecified</description>
26698 <description>Unspecified</description>
26703 <description>Unspecified</description>
26708 <description>Unspecified</description>
26715 <description>Reserved field - read-only</description>
26722 <description>Reserved field - read-only</description>
26729 <description>Reserved field - read-only</description>
26736 <description>Reserved field - read-only</description>
26743 <description>Reserved field - read-only</description>
26752 … <description>This register contains fields that control the DMA transfer.</description>
26760 <description>Block Transfer Size.</description>
26766 <description>Reserved field - read-only</description>
26773 <description>Done bit.</description>
26779 <description>Unspecified</description>
26784 <description>Unspecified</description>
26793 … <description>This register contains fields that configure the DMA transfer.</description>
26801 <description>Reserved field - read-only</description>
26808 <description>Channel Priority.</description>
26814 <description>Unspecified</description>
26819 <description>Unspecified</description>
26824 <description>Unspecified</description>
26829 <description>Unspecified</description>
26834 <description>Unspecified</description>
26839 <description>Unspecified</description>
26844 <description>Unspecified</description>
26849 <description>Unspecified</description>
26856 <description>Channel Suspend.</description>
26862 <description>Unspecified</description>
26867 <description>Unspecified</description>
26874 <description>Channel FIFO status.</description>
26881 <description>Unspecified</description>
26886 <description>Unspecified</description>
26893 <description>Destination Software or Hardware Handshaking Select.</description>
26899 <description>Unspecified</description>
26904 <description>Unspecified</description>
26911 <description>Source Software or Hardware Handshaking Select.</description>
26917 <description>Unspecified</description>
26922 <description>Unspecified</description>
26929 <description>Reserved field - read-only</description>
26936 <description>Reserved field - read-only</description>
26943 <description>Reserved field - read-only</description>
26950 <description>Reserved field - read-only</description>
26957 <description>Destination Handshaking Interface Polarity.</description>
26963 <description>Unspecified</description>
26968 <description>Unspecified</description>
26975 <description>Source Handshaking Interface Polarity.</description>
26981 <description>Unspecified</description>
26986 <description>Unspecified</description>
26993 <description>Maximum AMBA Burst Length.</description>
26999 <description>Reserved field - read-only</description>
27006 <description>Reserved field- read-only</description>
27015 … <description>This register contains fields that configure the DMA transfer.</description>
27023 <description>Flow Control Mode.</description>
27029 <description>Unspecified</description>
27034 <description>Unspecified</description>
27041 <description>FIFO Mode Select.</description>
27047 <description>Unspecified</description>
27052 <description>Unspecified</description>
27059 … <description>Protection Control bits used to drive the AHB HPROT[3:1] bus.</description>
27065 <description>Reserved field- read-only</description>
27072 <description>Reserved field- read-only</description>
27079 <description>Source Hardware Interface.</description>
27085 <description>Reserved field - read-only</description>
27092 <description>Destination hardware interface.</description>
27098 <description>Reserved field - read-only</description>
27105 <description>Reserved field - read-only</description>
27114 <description>Destination Scatter register.</description>
27122 <description>Destination Scatter Interval.</description>
27128 <description>Destination Scatter Count.</description>
27137 <description>Unspecified</description>
27143 … <description>This register contains the source address of the DMA transfer.</description>
27151 <description>Current Source Address of DMA transfer.</description>
27159 … <description>This register contains the destination address of the DMA transfer.</description>
27167 <description>Current Destination address of DMA transfer.</description>
27175 … <description>This register contains fields that control the DMA transfer.</description>
27183 <description>Interrupt Enable Bit.</description>
27189 <description>Unspecified</description>
27194 <description>Unspecified</description>
27201 <description>Reserved field - read-only</description>
27208 <description>Source Transfer Width.</description>
27214 <description>Unspecified</description>
27219 <description>Unspecified</description>
27224 <description>Unspecified</description>
27229 <description>Unspecified</description>
27234 <description>Unspecified</description>
27239 <description>Unspecified</description>
27244 <description>Unspecified</description>
27249 <description>Unspecified</description>
27256 <description>Destination Address Increment.</description>
27262 <description>Unspecified</description>
27267 <description>Unspecified</description>
27272 <description>Unspecified</description>
27277 <description>Unspecified</description>
27284 <description>Source Address Increment.</description>
27290 <description>Unspecified</description>
27295 <description>Unspecified</description>
27300 <description>Unspecified</description>
27305 <description>Unspecified</description>
27312 <description>Destination Burst Transaction Length.</description>
27318 <description>Unspecified</description>
27323 <description>Unspecified</description>
27328 <description>Unspecified</description>
27333 <description>Unspecified</description>
27338 <description>Unspecified</description>
27343 <description>Unspecified</description>
27348 <description>Unspecified</description>
27353 <description>Unspecified</description>
27360 <description>Source Burst Transaction Length.</description>
27366 <description>Unspecified</description>
27371 <description>Unspecified</description>
27376 <description>Unspecified</description>
27381 <description>Unspecified</description>
27386 <description>Unspecified</description>
27391 <description>Unspecified</description>
27396 <description>Unspecified</description>
27401 <description>Unspecified</description>
27408 <description>Source gather enable.</description>
27414 <description>Unspecified</description>
27419 <description>Unspecified</description>
27426 <description>Reserved field - read-only</description>
27433 <description>Reserved field - read-only</description>
27440 <description>Transfer Type and Flow Control.</description>
27446 <description>Unspecified</description>
27451 <description>Unspecified</description>
27456 <description>Unspecified</description>
27461 <description>Unspecified</description>
27466 <description>Unspecified</description>
27471 <description>Unspecified</description>
27476 <description>Unspecified</description>
27481 <description>Unspecified</description>
27488 <description>Reserved field - read-only</description>
27495 <description>Reserved field - read-only</description>
27502 <description>Reserved field - read-only</description>
27509 <description>Reserved field - read-only</description>
27516 <description>Reserved field - read-only</description>
27525 … <description>This register contains fields that control the DMA transfer.</description>
27533 <description>Block Transfer Size.</description>
27539 <description>Reserved field - read-only</description>
27546 <description>Done bit.</description>
27552 <description>Unspecified</description>
27557 <description>Unspecified</description>
27566 … <description>This register contains fields that configure the DMA transfer.</description>
27574 <description>Reserved field - read-only</description>
27581 <description>Channel Priority.</description>
27587 <description>Unspecified</description>
27592 <description>Unspecified</description>
27597 <description>Unspecified</description>
27602 <description>Unspecified</description>
27607 <description>Unspecified</description>
27612 <description>Unspecified</description>
27617 <description>Unspecified</description>
27622 <description>Unspecified</description>
27629 <description>Channel Suspend.</description>
27635 <description>Unspecified</description>
27640 <description>Unspecified</description>
27647 <description>Channel FIFO status.</description>
27654 <description>Unspecified</description>
27659 <description>Unspecified</description>
27666 <description>Destination Software or Hardware Handshaking Select.</description>
27672 <description>Unspecified</description>
27677 <description>Unspecified</description>
27684 <description>Source Software or Hardware Handshaking Select.</description>
27690 <description>Unspecified</description>
27695 <description>Unspecified</description>
27702 <description>Reserved field - read-only</description>
27709 <description>Reserved field - read-only</description>
27716 <description>Reserved field - read-only</description>
27723 <description>Reserved field - read-only</description>
27730 <description>Destination Handshaking Interface Polarity.</description>
27736 <description>Unspecified</description>
27741 <description>Unspecified</description>
27748 <description>Source Handshaking Interface Polarity.</description>
27754 <description>Unspecified</description>
27759 <description>Unspecified</description>
27766 <description>Maximum AMBA Burst Length.</description>
27772 <description>Reserved field - read-only</description>
27779 <description>Reserved field- read-only</description>
27788 … <description>This register contains fields that configure the DMA transfer.</description>
27796 <description>Flow Control Mode.</description>
27802 <description>Unspecified</description>
27807 <description>Unspecified</description>
27814 <description>FIFO Mode Select.</description>
27820 <description>Unspecified</description>
27825 <description>Unspecified</description>
27832 … <description>Protection Control bits used to drive the AHB HPROT[3:1] bus.</description>
27838 <description>Reserved field- read-only</description>
27845 <description>Reserved field- read-only</description>
27852 <description>Source Hardware Interface.</description>
27858 <description>Reserved field - read-only</description>
27865 <description>Destination hardware interface.</description>
27873 <description>Source Gather register</description>
27881 <description>Source Gather Interval.</description>
27887 <description>Source Gather Count.</description>
27896 <description>Unspecified</description>
27902 …<description>Interrupt events are stored in this Raw Interrupt Status register before masking.</de…
27910 <description>Raw Status for IntTfr Interrupt</description>
27916 <description>Unspecified</description>
27921 <description>Unspecified</description>
27930 …<description>Interrupt events are stored in this Raw Interrupt Status register before masking.</de…
27938 <description>Raw Status for IntBlock Interrupt</description>
27944 <description>Unspecified</description>
27949 <description>Unspecified</description>
27958 …<description>Interrupt events are stored in this Raw Interrupt Status register before masking.</de…
27966 <description>Raw Status for IntSrcTran Interrupt</description>
27972 <description>Unspecified</description>
27977 <description>Unspecified</description>
27986 …<description>Interrupt events are stored in this Raw Interrupt Status register before masking.</de…
27994 <description>Raw Status for IntDstTran Interrupt</description>
28000 <description>Unspecified</description>
28005 <description>Unspecified</description>
28014 …<description>Interrupt events are stored in this Raw Interrupt Status register before masking.</de…
28022 <description>Raw Status for IntErr Interrupt</description>
28028 <description>Unspecified</description>
28033 <description>Unspecified</description>
28042 …<description>Channel DMA Transfer complete interrupt event from all channels is stored in this Int…
28050 <description>Status for IntTfr Interrupt</description>
28057 <description>Unspecified</description>
28062 <description>Unspecified</description>
28071 …<description>Channel Block complete interrupt event from all channels is stored in this Interrupt …
28079 <description>Status for IntBlock Interrupt</description>
28086 <description>Unspecified</description>
28091 <description>Unspecified</description>
28100 …description>Channel Source Transaction complete interrupt event from all channels is stored in thi…
28108 <description>Status for IntSrcTran Interrupt</description>
28115 <description>Unspecified</description>
28120 <description>Unspecified</description>
28129 …description>Channel destination transaction complete interrupt event from all channels is stored i…
28137 <description>Status for IntDstTran Interrupt</description>
28144 <description>Unspecified</description>
28149 <description>Unspecified</description>
28158 …<description>Channel Error interrupt event from all channels is stored in this Interrupt Status re…
28166 <description>Status for IntErr Interrupt</description>
28173 <description>Unspecified</description>
28178 <description>Unspecified</description>
28187 …<description>The contents of the Raw Status register RawTfr is masked with the contents of the Mas…
28195 <description>Mask for IntTfr Interrupt</description>
28201 <description>Unspecified</description>
28206 <description>Unspecified</description>
28213 <description>Reserved field - read-only</description>
28220 <description>Interrupt Mask Write Enable</description>
28227 <description>Unspecified</description>
28232 <description>Unspecified</description>
28241 …<description>The contents of the Raw Status register RawBlock is masked with the contents of the M…
28249 <description>Mask for IntBlock Interrupt</description>
28255 <description>Unspecified</description>
28260 <description>Unspecified</description>
28267 <description>Reserved field- read-only</description>
28274 <description>Interrupt Mask Write Enable</description>
28281 <description>Unspecified</description>
28286 <description>Unspecified</description>
28295 …<description>The contents of the Raw Status register RawSrcTran is masked with the contents of the…
28303 <description>Mask for IntSrcTran Interrupt</description>
28309 <description>Unspecified</description>
28314 <description>Unspecified</description>
28321 <description>Reserved field- read-only</description>
28328 <description>Interrupt Mask Write Enable</description>
28335 <description>Unspecified</description>
28340 <description>Unspecified</description>
28349 …<description>The contents of the Raw Status register RawDstTran is masked with the contents of the…
28357 <description>Mask for IntDstTran Interrupt</description>
28363 <description>Unspecified</description>
28368 <description>Unspecified</description>
28375 <description>Reserved field - read-only</description>
28382 <description>Interrupt Mask Write Enable</description>
28389 <description>Unspecified</description>
28394 <description>Unspecified</description>
28403 …<description>The contents of the Raw Status register RawErr is masked with the contents of the Mas…
28411 <description>Mask for IntErr Interrupt</description>
28417 <description>Unspecified</description>
28422 <description>Unspecified</description>
28429 <description>Reserved field- read-only</description>
28436 <description>Interrupt Mask Write Enable</description>
28443 <description>Unspecified</description>
28448 <description>Unspecified</description>
28457 …description>Each bit in the RawTfr and StatusTfr is cleared on the same cycle by writing a 1 to th…
28465 <description>Clear for IntTfr Interrupt</description>
28472 <description>Unspecified</description>
28477 <description>Unspecified</description>
28486 …description>Each bit in the RawBlock and StatusBlock is cleared on the same cycle by writing a 1 t…
28494 <description>Clear for IntBlock Interrupt</description>
28503 …description>Each bit in the RawSrcTran and StatusSrcTran is cleared on the same cycle by writing a…
28511 <description>Clear for IntSrcTran Interrupt</description>
28518 <description>Unspecified</description>
28523 <description>Unspecified</description>
28532 …description>Each bit in the RawDstTran and StatusDstTran is cleared on the same cycle by writing a…
28540 <description>Clear for IntDstTran Interrupt</description>
28547 <description>Unspecified</description>
28552 <description>Unspecified</description>
28561 …description>Each bit in the RawErr and StatusErr is cleared on the same cycle by writing a 1 to th…
28569 <description>Clear for IntErr Interrupt</description>
28576 <description>Unspecified</description>
28581 <description>Unspecified</description>
28590 …description>The contents of each of the five Status registers StatusTfr, StatusBlock, StatusSrcTr…
28598 <description>OR of the contents of StatusTfr register</description>
28605 <description>Unspecified</description>
28610 <description>Unspecified</description>
28617 <description>OR of the contents of StatusBlock register</description>
28624 <description>Unspecified</description>
28629 <description>Unspecified</description>
28636 <description>OR of the contents of StatusSrcTran</description>
28643 <description>Unspecified</description>
28648 <description>Unspecified</description>
28655 <description>OR of the contents of StatusDstTran</description>
28662 <description>Unspecified</description>
28667 <description>Unspecified</description>
28674 <description>OR of the contents of StatusErr</description>
28681 <description>Unspecified</description>
28686 <description>Unspecified</description>
28696 <description>Unspecified</description>
28702 <description>A bit is assigned for each channel in this register.</description>
28710 <description>Source Software Transaction Request</description>
28716 <description>Unspecified</description>
28721 <description>Unspecified</description>
28728 <description>Reserved field - read-only</description>
28735 <description>Source Software Transaction Request write enable</description>
28742 <description>Unspecified</description>
28747 <description>Unspecified</description>
28756 <description>A bit is assigned for each channel in this register.</description>
28764 <description>Destination Software Transaction Request</description>
28770 <description>Unspecified</description>
28775 <description>Unspecified</description>
28782 <description>Reserved field - read-only</description>
28789 <description>Destination Software Transaction Request write enable</description>
28796 <description>Unspecified</description>
28801 <description>Unspecified</description>
28810 <description>A bit is assigned for each channel in this register.</description>
28818 <description>Source Single Transaction Request</description>
28824 <description>Unspecified</description>
28829 <description>Unspecified</description>
28836 <description>Reserved field - read-only</description>
28843 <description>Source Single Transaction Request write enable</description>
28850 <description>Unspecified</description>
28855 <description>Unspecified</description>
28864 <description>A bit is assigned for each channel in this register.</description>
28872 <description>Destination Single Transaction Request</description>
28878 <description>Unspecified</description>
28883 <description>Unspecified</description>
28890 <description>Reserved field - read-only</description>
28897 <description>Destination Single Transaction Request write enable</description>
28904 <description>Unspecified</description>
28909 <description>Unspecified</description>
28918 <description>A bit is assigned for each channel in this register.</description>
28926 <description>Source Last Transaction Request register</description>
28932 <description>Unspecified</description>
28937 <description>Unspecified</description>
28944 <description>Reserved field- read-only</description>
28951 <description>Source Last Transaction Request write enable</description>
28958 <description>Unspecified</description>
28963 <description>Unspecified</description>
28972 <description>A bit is assigned for each channel in this register.</description>
28980 <description>Destination Last Transaction Request</description>
28986 <description>Unspecified</description>
28991 <description>Unspecified</description>
28998 <description>Reserved field - read-only</description>
29005 <description>Source Last Transaction Request write enable</description>
29012 <description>Unspecified</description>
29017 <description>Unspecified</description>
29027 <description>Unspecified</description>
29033 …<description>This register is used to enable the DW_ahb_dmac, which must be done before any channe…
29041 <description>DW_ahb_dmac Enable bit.</description>
29047 <description>Unspecified</description>
29052 <description>Unspecified</description>
29061 <description>This is the DW_ahb_dmac Channel Enable Register.</description>
29069 <description>Channel Enable.</description>
29075 <description>Unspecified</description>
29080 <description>Unspecified</description>
29087 <description>Reserved field - read-only</description>
29094 <description>Channel enable register</description>
29103 …description>This is the DW_ahb_dmac ID register, which is a read-only register that reads back the…
29111 <description>Hardcoded DW_ahb_dmac peripheral ID.</description>
29120 …description>This register is used to put the AHB slave interface into test mode, during which the …
29128 <description>DMA Test register</description>
29134 <description>Unspecified</description>
29139 <description>Unspecified</description>
29148 <description>This register holds the timeout value of Low Power Counter.</description>
29156 … <description>This field holds timeout value of low power counter register.</description>
29164 …description>DMA_COMP_PARAMS_6L is a constant read-only register that contains encoded information …
29172 …<description>The value of this register is derived from the DMAH_CH7_DTW coreConsultant parameter.…
29179 <description>Unspecified</description>
29184 <description>Unspecified</description>
29189 <description>Unspecified</description>
29194 <description>Unspecified</description>
29199 <description>Unspecified</description>
29204 <description>Unspecified</description>
29209 <description>Unspecified</description>
29216 …<description>The value of this register is derived from the DMAH_CH7_STW coreConsultant parameter.…
29223 <description>Unspecified</description>
29228 <description>Unspecified</description>
29233 <description>Unspecified</description>
29238 <description>Unspecified</description>
29243 <description>Unspecified</description>
29248 <description>Unspecified</description>
29253 <description>Unspecified</description>
29260 …<description>The value of this register is derived from the DMAH_CH7_STAT_DST coreConsultant param…
29267 <description>Unspecified</description>
29272 <description>Unspecified</description>
29279 …<description>The value of this register is derived from the DMAH_CH7_STAT_SRC coreConsultant param…
29286 <description>Unspecified</description>
29291 <description>Unspecified</description>
29298 …<description>The value of this register is derived from the DMAH_CH7_DST_SCA_EN coreConsultant par…
29305 <description>Unspecified</description>
29310 <description>Unspecified</description>
29317 …<description>The value of this register is derived from the DMAH_CH7_SRC_GAT_EN coreConsultant par…
29324 <description>Unspecified</description>
29329 <description>Unspecified</description>
29336 …<description>The value of this register is derived from the DMAH_CH7_LOCK_EN coreConsultant parame…
29343 <description>Unspecified</description>
29348 <description>Unspecified</description>
29355 …<description>The value of this register is derived from the DMAH_CH7_MULTI_BLK_EN coreConsultant p…
29362 <description>Unspecified</description>
29367 <description>Unspecified</description>
29374 …<description>The value of this register is derived from the DMAH_CH7_CTL_WB_EN coreConsultant para…
29381 <description>Unspecified</description>
29386 <description>Unspecified</description>
29393 …<description>The value of this register is derived from the DMAH_CH7_HC_LLP coreConsultant paramet…
29400 <description>Unspecified</description>
29405 <description>Unspecified</description>
29412 …<description>The value of this register is derived from the DMAH_CH7_FC coreConsultant parameter.<…
29419 <description>Unspecified</description>
29424 <description>Unspecified</description>
29429 <description>Unspecified</description>
29434 <description>Unspecified</description>
29441 …<description>The value of this register is derived from the DMAH_CH7_MULT_SIZE coreConsultant para…
29448 <description>Unspecified</description>
29453 <description>Unspecified</description>
29458 <description>Unspecified</description>
29463 <description>Unspecified</description>
29468 <description>Unspecified</description>
29473 <description>Unspecified</description>
29478 <description>Unspecified</description>
29485 …<description>The value of this register is derived from the DMAH_CH7_DMS coreConsultant parameter.…
29492 <description>Unspecified</description>
29497 <description>Unspecified</description>
29502 <description>Unspecified</description>
29507 <description>Unspecified</description>
29512 <description>Unspecified</description>
29519 …<description>The value of this register is derived from the DMAH_CH7_LMS coreConsultant parameter.…
29526 <description>Unspecified</description>
29531 <description>Unspecified</description>
29536 <description>Unspecified</description>
29541 <description>Unspecified</description>
29546 <description>Unspecified</description>
29553 …<description>The value of this register is derived from the DMAH_CH7_SMS coreConsultant parameter.…
29560 <description>Unspecified</description>
29565 <description>Unspecified</description>
29570 <description>Unspecified</description>
29575 <description>Unspecified</description>
29580 <description>Unspecified</description>
29587 …<description>The value of this register is derived from the DMAH_CH7_FIFO_DEPTH coreConsultant par…
29594 <description>Unspecified</description>
29599 <description>Unspecified</description>
29604 <description>Unspecified</description>
29609 <description>Unspecified</description>
29614 <description>Unspecified</description>
29619 <description>Unspecified</description>
29628 …description>DMA_COMP_PARAMS_5 is a constant read-only register that contains encoded information a…
29636 …<description>The value of this register is derived from the DMAH_CH6_DTW coreConsultant parameter.…
29643 <description>Unspecified</description>
29648 <description>Unspecified</description>
29653 <description>Unspecified</description>
29658 <description>Unspecified</description>
29663 <description>Unspecified</description>
29668 <description>Unspecified</description>
29673 <description>Unspecified</description>
29680 …<description>The value of this register is derived from the DMAH_CH6_STW coreConsultant parameter.…
29687 <description>Unspecified</description>
29692 <description>Unspecified</description>
29697 <description>Unspecified</description>
29702 <description>Unspecified</description>
29707 <description>Unspecified</description>
29712 <description>Unspecified</description>
29717 <description>Unspecified</description>
29724 …<description>The value of this register is derived from the DMAH_CH6_STAT_DST coreConsultant param…
29731 <description>Unspecified</description>
29736 <description>Unspecified</description>
29743 …<description>The value of this register is derived from the DMAH_CH6_STAT_SRC coreConsultant param…
29750 <description>Unspecified</description>
29755 <description>Unspecified</description>
29762 …<description>The value of this register is derived from the DMAH_CH6_DST_SCA_EN coreConsultant par…
29769 <description>Unspecified</description>
29774 <description>Unspecified</description>
29781 …<description>The value of this register is derived from the CH6_SRC_GAT_EN coreConsultant paramete…
29788 <description>Unspecified</description>
29793 <description>Unspecified</description>
29800 …<description>The value of this register is derived from the DMAH_CH6_LOCK_EN coreConsultant parame…
29807 <description>Unspecified</description>
29812 <description>Unspecified</description>
29819 …<description>The value of this register is derived from the DMAH_CH6_MULTI_BLK_EN coreConsultant p…
29826 <description>Unspecified</description>
29831 <description>Unspecified</description>
29838 …<description>The value of this register is derived from the DMAH_CH6_CTL_WB_EN coreConsultant para…
29845 <description>Unspecified</description>
29850 <description>Unspecified</description>
29857 …<description>The value of this register is derived from the DMAH_CH6_HC_LLP coreConsultant paramet…
29864 <description>Unspecified</description>
29869 <description>Unspecified</description>
29876 …<description>The value of this register is derived from the DMAH_CH6_FC coreConsultant parameter.<…
29883 <description>Unspecified</description>
29888 <description>Unspecified</description>
29893 <description>Unspecified</description>
29898 <description>Unspecified</description>
29905 …<description>The value of this register is derived from the DMAH_CH6_MULT_SIZE coreConsultant para…
29912 <description>Unspecified</description>
29917 <description>Unspecified</description>
29922 <description>Unspecified</description>
29927 <description>Unspecified</description>
29932 <description>Unspecified</description>
29937 <description>Unspecified</description>
29942 <description>Unspecified</description>
29949 …<description>The value of this register is derived from the DMAH_CH6_DMS coreConsultant parameter.…
29956 <description>Unspecified</description>
29961 <description>Unspecified</description>
29966 <description>Unspecified</description>
29971 <description>Unspecified</description>
29976 <description>Unspecified</description>
29983 …<description>The value of this register is derived from the DMAH_CH6_LMS coreConsultant parameter.…
29990 <description>Unspecified</description>
29995 <description>Unspecified</description>
30000 <description>Unspecified</description>
30005 <description>Unspecified</description>
30010 <description>Unspecified</description>
30017 …<description>The value of this register is derived from the DMAH_CH6_SMS coreConsultant parameter.…
30024 <description>Unspecified</description>
30029 <description>Unspecified</description>
30034 <description>Unspecified</description>
30039 <description>Unspecified</description>
30044 <description>Unspecified</description>
30051 …<description>The value of this register is derived from the DMAH_CH6_FIFO_DEPTH coreConsultant par…
30058 <description>Unspecified</description>
30063 <description>Unspecified</description>
30068 <description>Unspecified</description>
30073 <description>Unspecified</description>
30078 <description>Unspecified</description>
30083 <description>Unspecified</description>
30092 …description>DMA_COMP_PARAMS_5 is a constant read-only register that contains encoded information a…
30100 …<description>The value of this register is derived from the DMAH_CH5_DTW coreConsultant parameter.…
30107 <description>Unspecified</description>
30112 <description>Unspecified</description>
30117 <description>Unspecified</description>
30122 <description>Unspecified</description>
30127 <description>Unspecified</description>
30132 <description>Unspecified</description>
30137 <description>Unspecified</description>
30144 …<description>The value of this register is derived from the DMAH_CH5_STW coreConsultant parameter.…
30151 <description>Unspecified</description>
30156 <description>Unspecified</description>
30161 <description>Unspecified</description>
30166 <description>Unspecified</description>
30171 <description>Unspecified</description>
30176 <description>Unspecified</description>
30181 <description>Unspecified</description>
30188 …<description>The value of this register is derived from the DMAH_CH5_STAT_DST coreConsultant param…
30195 <description>Unspecified</description>
30200 <description>Unspecified</description>
30207 …<description>The value of this register is derived from the DMAH_CH5_STAT_SRC coreConsultant param…
30214 <description>Unspecified</description>
30219 <description>Unspecified</description>
30226 …<description>The value of this register is derived from the DMAH_CH5_DST_SCA_EN coreConsultant par…
30233 <description>Unspecified</description>
30238 <description>Unspecified</description>
30245 …<description>The value of this register is derived from the DMAH_CH5_SRC_GAT_EN coreConsultant par…
30252 <description>Unspecified</description>
30257 <description>Unspecified</description>
30264 …<description>The value of this register is derived from the DMAH_CH5_LOCK_EN coreConsultant parame…
30271 <description>Unspecified</description>
30276 <description>Unspecified</description>
30283 …<description>The value of this register is derived from the DMAH_CH5_MULTI_BLK_EN coreConsultant p…
30290 <description>Unspecified</description>
30295 <description>Unspecified</description>
30302 …<description>The value of this register is derived from the DMAH_CH5_CTL_WB_EN coreConsultant para…
30309 <description>Unspecified</description>
30314 <description>Unspecified</description>
30321 …<description>The value of this register is derived from the DMAH_CH5_HC_LLP coreConsultant paramet…
30328 <description>Unspecified</description>
30333 <description>Unspecified</description>
30340 …<description>The value of this register is derived from the DMAH_CH5_FC coreConsultant parameter.<…
30347 <description>Unspecified</description>
30352 <description>Unspecified</description>
30357 <description>Unspecified</description>
30362 <description>Unspecified</description>
30369 …<description>The value of this register is derived from the DMAH_CH5_MULT_SIZE coreConsultant para…
30376 <description>Unspecified</description>
30381 <description>Unspecified</description>
30386 <description>Unspecified</description>
30391 <description>Unspecified</description>
30396 <description>Unspecified</description>
30401 <description>Unspecified</description>
30406 <description>Unspecified</description>
30413 …<description>The value of this register is derived from the DMAH_CH5_DMS coreConsultant parameter.…
30420 <description>Unspecified</description>
30425 <description>Unspecified</description>
30430 <description>Unspecified</description>
30435 <description>Unspecified</description>
30440 <description>Unspecified</description>
30447 …<description>The value of this register is derived from the DMAH_CH5_LMS coreConsultant parameter.…
30454 <description>Unspecified</description>
30459 <description>Unspecified</description>
30464 <description>Unspecified</description>
30469 <description>Unspecified</description>
30474 <description>Unspecified</description>
30481 …<description>The value of this register is derived from the DMAH_CH5_SMS coreConsultant parameter.…
30488 <description>Unspecified</description>
30493 <description>Unspecified</description>
30498 <description>Unspecified</description>
30503 <description>Unspecified</description>
30508 <description>Unspecified</description>
30515 …<description>The value of this register is derived from the DMAH_CH5_FIFO_DEPTH coreConsultant par…
30522 <description>Unspecified</description>
30527 <description>Unspecified</description>
30532 <description>Unspecified</description>
30537 <description>Unspecified</description>
30542 <description>Unspecified</description>
30547 <description>Unspecified</description>
30556 …description>DMA_COMP_PARAMS_4 is a constant read-only register that contains encoded information a…
30564 …<description>The value of this register is derived from the DMAH_CH4_DTW coreConsultant parameter.…
30571 <description>Unspecified</description>
30576 <description>Unspecified</description>
30581 <description>Unspecified</description>
30586 <description>Unspecified</description>
30591 <description>Unspecified</description>
30596 <description>Unspecified</description>
30601 <description>Unspecified</description>
30608 …<description>The value of this register is derived from the DMAH_CH4_STW coreConsultant parameter.…
30615 <description>Unspecified</description>
30620 <description>Unspecified</description>
30625 <description>Unspecified</description>
30630 <description>Unspecified</description>
30635 <description>Unspecified</description>
30640 <description>Unspecified</description>
30645 <description>Unspecified</description>
30652 …<description>The value of this register is derived from the DMAH_CH4_STAT_DST coreConsultant param…
30659 <description>Unspecified</description>
30664 <description>Unspecified</description>
30671 …<description>The value of this register is derived from the DMAH_CH4_STAT_SRC coreConsultant param…
30678 <description>Unspecified</description>
30683 <description>Unspecified</description>
30690 …<description>The value of this register is derived from the DMAH_CH4_DST_SCA_EN coreConsultant par…
30697 <description>Unspecified</description>
30702 <description>Unspecified</description>
30709 …<description>The value of this register is derived from the DMAH_CH4_SRC_GAT_EN coreConsultant par…
30716 <description>Unspecified</description>
30721 <description>Unspecified</description>
30728 …<description>The value of this register is derived from the DMAH_CH4_LOCK_EN coreConsultant parame…
30735 <description>Unspecified</description>
30740 <description>Unspecified</description>
30747 …<description>The value of this register is derived from the DMAH_CH4_MULTI_BLK_EN coreConsultant p…
30754 <description>Unspecified</description>
30759 <description>Unspecified</description>
30766 …<description>The value of this register is derived from the DMAH_CH4_CTL_WB_EN coreConsultant para…
30773 <description>Unspecified</description>
30778 <description>Unspecified</description>
30785 …<description>The value of this register is derived from the DMAH_CH4_HC_LLP coreConsultant paramet…
30792 <description>Unspecified</description>
30797 <description>Unspecified</description>
30804 …<description>The value of this register is derived from the DMAH_CH4_FC coreConsultant parameter.<…
30811 <description>Unspecified</description>
30816 <description>Unspecified</description>
30821 <description>Unspecified</description>
30826 <description>Unspecified</description>
30833 …<description>The value of this register is derived from the DMAH_CH4_MULT_SIZE coreConsultant para…
30840 <description>Unspecified</description>
30845 <description>Unspecified</description>
30850 <description>Unspecified</description>
30855 <description>Unspecified</description>
30860 <description>Unspecified</description>
30865 <description>Unspecified</description>
30870 <description>Unspecified</description>
30877 …<description>The value of this register is derived from the DMAH_CH4_DMS coreConsultant parameter.…
30884 <description>Unspecified</description>
30889 <description>Unspecified</description>
30894 <description>Unspecified</description>
30899 <description>Unspecified</description>
30904 <description>Unspecified</description>
30911 …<description>The value of this register is derived from the DMAH_CH4_LMS coreConsultant parameter.…
30918 <description>Unspecified</description>
30923 <description>Unspecified</description>
30928 <description>Unspecified</description>
30933 <description>Unspecified</description>
30938 <description>Unspecified</description>
30945 …<description>The value of this register is derived from the DMAH_CH4_SMS coreConsultant parameter.…
30952 <description>Unspecified</description>
30957 <description>Unspecified</description>
30962 <description>Unspecified</description>
30967 <description>Unspecified</description>
30972 <description>Unspecified</description>
30979 …<description>The value of this register is derived from the DMAH_CH4_FIFO_DEPTH coreConsultant par…
30986 <description>Unspecified</description>
30991 <description>Unspecified</description>
30996 <description>Unspecified</description>
31001 <description>Unspecified</description>
31006 <description>Unspecified</description>
31011 <description>Unspecified</description>
31020 …description>DMA_COMP_PARAMS_4 is a constant read-only register that contains encoded information a…
31028 …<description>The value of this register is derived from the DMAH_CH3_DTW coreConsultant parameter.…
31035 <description>Unspecified</description>
31040 <description>Unspecified</description>
31045 <description>Unspecified</description>
31050 <description>Unspecified</description>
31055 <description>Unspecified</description>
31060 <description>Unspecified</description>
31065 <description>Unspecified</description>
31072 …<description>The value of this register is derived from the DMAH_CH3_STW coreConsultant parameter.…
31079 <description>Unspecified</description>
31084 <description>Unspecified</description>
31089 <description>Unspecified</description>
31094 <description>Unspecified</description>
31099 <description>Unspecified</description>
31104 <description>Unspecified</description>
31109 <description>Unspecified</description>
31116 …<description>The value of this register is derived from the DMAH_CH3_STAT_DST coreConsultant param…
31123 <description>Unspecified</description>
31128 <description>Unspecified</description>
31135 …<description>The value of this register is derived from the DMAH_CH3_STAT_SRC coreConsultant param…
31142 <description>Unspecified</description>
31147 <description>Unspecified</description>
31154 …<description>The value of this register is derived from the DMAH_CH3_DST_SCA_EN coreConsultant par…
31161 <description>Unspecified</description>
31166 <description>Unspecified</description>
31173 …<description>The value of this register is derived from the DMAH_CH3_SRC_GAT_EN coreConsultant par…
31180 <description>Unspecified</description>
31185 <description>Unspecified</description>
31192 …<description>The value of this register is derived from the DMAH_CH3_LOCK_EN coreConsultant parame…
31199 <description>Unspecified</description>
31204 <description>Unspecified</description>
31211 …<description>The value of this register is derived from the DMAH_CH3_MULTI_BLK_EN coreConsultant p…
31218 <description>Unspecified</description>
31223 <description>Unspecified</description>
31230 …<description>The value of this register is derived from the DMAH_CH3_CTL_WB_EN coreConsultant para…
31237 <description>Unspecified</description>
31242 <description>Unspecified</description>
31249 …<description>The value of this register is derived from the DMAH_CH3_HC_LLP coreConsultant paramet…
31256 <description>Unspecified</description>
31261 <description>Unspecified</description>
31268 …<description>The value of this register is derived from the DMAH_CH3_FC coreConsultant parameter.<…
31275 <description>Unspecified</description>
31280 <description>Unspecified</description>
31285 <description>Unspecified</description>
31290 <description>Unspecified</description>
31297 …<description>The value of this register is derived from the DMAH_CH3_MULT_SIZE coreConsultant para…
31304 <description>Unspecified</description>
31309 <description>Unspecified</description>
31314 <description>Unspecified</description>
31319 <description>Unspecified</description>
31324 <description>Unspecified</description>
31329 <description>Unspecified</description>
31334 <description>Unspecified</description>
31341 …<description>The value of this register is derived from the DMAH_CH3_DMS coreConsultant parameter.…
31348 <description>Unspecified</description>
31353 <description>Unspecified</description>
31358 <description>Unspecified</description>
31363 <description>Unspecified</description>
31368 <description>Unspecified</description>
31375 …<description>The value of this register is derived from the DMAH_CH3_LMS coreConsultant parameter.…
31382 <description>Unspecified</description>
31387 <description>Unspecified</description>
31392 <description>Unspecified</description>
31397 <description>Unspecified</description>
31402 <description>Unspecified</description>
31409 …<description>The value of this register is derived from the DMAH_CH3_SMS coreConsultant parameter.…
31416 <description>Unspecified</description>
31421 <description>Unspecified</description>
31426 <description>Unspecified</description>
31431 <description>Unspecified</description>
31436 <description>Unspecified</description>
31443 …<description>The value of this register is derived from the DMAH_CH3_FIFO_DEPTH coreConsultant par…
31450 <description>Unspecified</description>
31455 <description>Unspecified</description>
31460 <description>Unspecified</description>
31465 <description>Unspecified</description>
31470 <description>Unspecified</description>
31475 <description>Unspecified</description>
31484 …description>DMA_COMP_PARAMS_3 is a constant read-only register that contains encoded information a…
31492 …<description>The value of this register is derived from the DMAH_CH2_DTW coreConsultant parameter.…
31499 <description>Unspecified</description>
31504 <description>Unspecified</description>
31509 <description>Unspecified</description>
31514 <description>Unspecified</description>
31519 <description>Unspecified</description>
31524 <description>Unspecified</description>
31529 <description>Unspecified</description>
31536 …<description>The value of this register is derived from the DMAH_CH2_STW coreConsultant parameter.…
31543 <description>Unspecified</description>
31548 <description>Unspecified</description>
31553 <description>Unspecified</description>
31558 <description>Unspecified</description>
31563 <description>Unspecified</description>
31568 <description>Unspecified</description>
31573 <description>Unspecified</description>
31580 …<description>The value of this register is derived from the DMAH_CH2_STAT_DST coreConsultant param…
31587 <description>Unspecified</description>
31592 <description>Unspecified</description>
31599 …<description>The value of this register is derived from the DMAH_CH2_STAT_SRC coreConsultant param…
31606 <description>Unspecified</description>
31611 <description>Unspecified</description>
31618 …<description>The value of this register is derived from the DMAH_CH2_DST_SCA_EN coreConsultant par…
31625 <description>Unspecified</description>
31630 <description>Unspecified</description>
31637 …<description>The value of this register is derived from the DMAH_CH2_SRC_GAT_EN coreConsultant par…
31644 <description>Unspecified</description>
31649 <description>Unspecified</description>
31656 …<description>The value of this register is derived from the DMAH_CH2_LOCK_EN coreConsultant parame…
31663 <description>Unspecified</description>
31668 <description>Unspecified</description>
31675 …<description>The value of this register is derived from the DMAH_CH2_MULTI_BLK_EN coreConsultant p…
31682 <description>Unspecified</description>
31687 <description>Unspecified</description>
31694 …<description>The value of this register is derived from the DMAH_CH2_CTL_WB_EN coreConsultant para…
31701 <description>Unspecified</description>
31706 <description>Unspecified</description>
31713 …<description>The value of this register is derived from the DMAH_CH2_HC_LLP coreConsultant paramet…
31720 <description>Unspecified</description>
31725 <description>Unspecified</description>
31732 …<description>The value of this register is derived from the DMAH_CH2_FC coreConsultant parameter.<…
31739 <description>Unspecified</description>
31744 <description>Unspecified</description>
31749 <description>Unspecified</description>
31754 <description>Unspecified</description>
31761 …<description>The value of this register is derived from the DMAH_CH2_MULT_SIZE coreConsultant para…
31768 <description>Unspecified</description>
31773 <description>Unspecified</description>
31778 <description>Unspecified</description>
31783 <description>Unspecified</description>
31788 <description>Unspecified</description>
31793 <description>Unspecified</description>
31798 <description>Unspecified</description>
31805 …<description>The value of this register is derived from the DMAH_CH2_DMS coreConsultant parameter.…
31812 <description>Unspecified</description>
31817 <description>Unspecified</description>
31822 <description>Unspecified</description>
31827 <description>Unspecified</description>
31832 <description>Unspecified</description>
31839 …<description>The value of this register is derived from the DMAH_CH2_LMS coreConsultant parameter.…
31846 <description>Unspecified</description>
31851 <description>Unspecified</description>
31856 <description>Unspecified</description>
31861 <description>Unspecified</description>
31866 <description>Unspecified</description>
31873 …<description>The value of this register is derived from the DMAH_CH2_SMS coreConsultant parameter.…
31880 <description>Unspecified</description>
31885 <description>Unspecified</description>
31890 <description>Unspecified</description>
31895 <description>Unspecified</description>
31900 <description>Unspecified</description>
31907 …<description>The value of this register is derived from the DMAH_CH2_FIFO_DEPTH coreConsultant par…
31914 <description>Unspecified</description>
31919 <description>Unspecified</description>
31924 <description>Unspecified</description>
31929 <description>Unspecified</description>
31934 <description>Unspecified</description>
31939 <description>Unspecified</description>
31948 …description>DMA_COMP_PARAMS_3 is a constant read-only register that contains encoded information a…
31956 …<description>The value of this register is derived from the DMAH_CH1_DTW coreConsultant parameter.…
31963 <description>Unspecified</description>
31968 <description>Unspecified</description>
31973 <description>Unspecified</description>
31978 <description>Unspecified</description>
31983 <description>Unspecified</description>
31988 <description>Unspecified</description>
31993 <description>Unspecified</description>
32000 …<description>The value of this register is derived from the DMAH_CH1_STW coreConsultant parameter.…
32007 <description>Unspecified</description>
32012 <description>Unspecified</description>
32017 <description>Unspecified</description>
32022 <description>Unspecified</description>
32027 <description>Unspecified</description>
32032 <description>Unspecified</description>
32037 <description>Unspecified</description>
32044 …<description>The value of this register is derived from the DMAH_CH1_STAT_DST coreConsultant param…
32051 <description>Unspecified</description>
32056 <description>Unspecified</description>
32063 …<description>The value of this register is derived from the DMAH_CH1_STAT_SRC coreConsultant param…
32070 <description>Unspecified</description>
32075 <description>Unspecified</description>
32082 …<description>The value of this register is derived from the DMAH_CH1_DST_SCA_EN coreConsultant par…
32089 <description>Unspecified</description>
32094 <description>Unspecified</description>
32101 …<description>The value of this register is derived from the DMAH_CH1_SRC_GAT_EN coreConsultant par…
32108 <description>Unspecified</description>
32113 <description>Unspecified</description>
32120 …<description>The value of this register is derived from the DMAH_CH1_LOCK_EN coreConsultant parame…
32127 <description>Unspecified</description>
32132 <description>Unspecified</description>
32139 …<description>The value of this register is derived from the DMAH_CH1_MULTI_BLK_EN coreConsultant p…
32146 <description>Unspecified</description>
32151 <description>Unspecified</description>
32158 …<description>The value of this register is derived from the DMAH_CH1_CTL_WB_EN coreConsultant para…
32165 <description>Unspecified</description>
32170 <description>Unspecified</description>
32177 …<description>The value of this register is derived from the DMAH_CH1_HC_LLP coreConsultant paramet…
32184 <description>Unspecified</description>
32189 <description>Unspecified</description>
32196 …<description>The value of this register is derived from the DMAH_CH1_FC coreConsultant parameter.<…
32203 <description>Unspecified</description>
32208 <description>Unspecified</description>
32213 <description>Unspecified</description>
32218 <description>Unspecified</description>
32225 …<description>The value of this register is derived from the DMAH_CH1_MULT_SIZE coreConsultant para…
32232 <description>Unspecified</description>
32237 <description>Unspecified</description>
32242 <description>Unspecified</description>
32247 <description>Unspecified</description>
32252 <description>Unspecified</description>
32257 <description>Unspecified</description>
32262 <description>Unspecified</description>
32269 …<description>The value of this register is derived from the DMAH_CH1_DMS coreConsultant parameter.…
32276 <description>Unspecified</description>
32281 <description>Unspecified</description>
32286 <description>Unspecified</description>
32291 <description>Unspecified</description>
32296 <description>Unspecified</description>
32303 …<description>The value of this register is derived from the DMAH_CH1_LMS coreConsultant parameter.…
32310 <description>Unspecified</description>
32315 <description>Unspecified</description>
32320 <description>Unspecified</description>
32325 <description>Unspecified</description>
32330 <description>Unspecified</description>
32337 …<description>The value of this register is derived from the DMAH_CH1_SMS coreConsultant parameter.…
32344 <description>Unspecified</description>
32349 <description>Unspecified</description>
32354 <description>Unspecified</description>
32359 <description>Unspecified</description>
32364 <description>Unspecified</description>
32371 …<description>The value of this register is derived from the DMAH_CH1_FIFO_DEPTH coreConsultant par…
32378 <description>Unspecified</description>
32383 <description>Unspecified</description>
32388 <description>Unspecified</description>
32393 <description>Unspecified</description>
32398 <description>Unspecified</description>
32403 <description>Unspecified</description>
32412 …<description>DMA_COMP_PARAMS_2 is a constant read-only register that contains encoded information …
32420 …<description>The value of this register is derived from the DMAH_CH0_DTW coreConsultant parameter.…
32427 <description>Unspecified</description>
32432 <description>Unspecified</description>
32437 <description>Unspecified</description>
32442 <description>Unspecified</description>
32447 <description>Unspecified</description>
32452 <description>Unspecified</description>
32457 <description>Unspecified</description>
32464 …<description>The value of this register is derived from the DMAH_CH0_STW coreConsultant parameter.…
32471 <description>Unspecified</description>
32476 <description>Unspecified</description>
32481 <description>Unspecified</description>
32486 <description>Unspecified</description>
32491 <description>Unspecified</description>
32496 <description>Unspecified</description>
32501 <description>Unspecified</description>
32508 …<description>The value of this register is derived from the DMAH_CH0_STAT_DST coreConsultant param…
32515 <description>Unspecified</description>
32520 <description>Unspecified</description>
32527 …<description>The value of this register is derived from the DMAH_CH0_STAT_SRC coreConsultant param…
32534 <description>Unspecified</description>
32539 <description>Unspecified</description>
32546 …<description>The value of this register is derived from the DMAH_CH0_DST_SCA_EN coreConsultant par…
32553 <description>Unspecified</description>
32558 <description>Unspecified</description>
32565 …<description>The value of this register is derived from the DMAH_CH0_SRC_GAT_EN coreConsultant par…
32572 <description>Unspecified</description>
32577 <description>Unspecified</description>
32584 …<description>The value of this register is derived from the DMAH_CH0_LOCK_EN coreConsultant parame…
32591 <description>Unspecified</description>
32596 <description>Unspecified</description>
32603 …<description>The value of this register is derived from the DMAH_CH0_MULTI_BLK_EN coreConsultant p…
32610 <description>Unspecified</description>
32615 <description>Unspecified</description>
32622 …<description>The value of this register is derived from the DMAH_CH0_CTL_WB_EN coreConsultant para…
32629 <description>Unspecified</description>
32634 <description>Unspecified</description>
32641 …<description>The value of this register is derived from the DMAH_CH0_HC_LLP coreConsultant paramet…
32648 <description>Unspecified</description>
32653 <description>Unspecified</description>
32660 …<description>The value of this register is derived from the DMAH_CH0_FC coreConsultant parameter.<…
32667 <description>Unspecified</description>
32672 <description>Unspecified</description>
32677 <description>Unspecified</description>
32682 <description>Unspecified</description>
32689 …<description>The value of this register is derived from the DMAH_CH0_MULT_SIZE coreConsultant para…
32696 <description>Unspecified</description>
32701 <description>Unspecified</description>
32706 <description>Unspecified</description>
32711 <description>Unspecified</description>
32716 <description>Unspecified</description>
32721 <description>Unspecified</description>
32726 <description>Unspecified</description>
32733 …<description>The value of this register is derived from the DMAH_CH0_DMS coreConsultant parameter.…
32740 <description>Unspecified</description>
32745 <description>Unspecified</description>
32750 <description>Unspecified</description>
32755 <description>Unspecified</description>
32760 <description>Unspecified</description>
32767 …<description>The value of this register is derived from the DMAH_CH0_LMS coreConsultant parameter.…
32774 <description>Unspecified</description>
32779 <description>Unspecified</description>
32784 <description>Unspecified</description>
32789 <description>Unspecified</description>
32794 <description>Unspecified</description>
32801 …<description>The value of this register is derived from the DMAH_CH0_SMS coreConsultant parameter.…
32808 <description>Unspecified</description>
32813 <description>Unspecified</description>
32818 <description>Unspecified</description>
32823 <description>Unspecified</description>
32828 <description>Unspecified</description>
32835 …<description>The value of this register is derived from the DMAH_CH0_FIFO_DEPTH coreConsultant par…
32842 <description>Unspecified</description>
32847 <description>Unspecified</description>
32852 <description>Unspecified</description>
32857 <description>Unspecified</description>
32862 <description>Unspecified</description>
32867 <description>Unspecified</description>
32876 …<description>DMA_COMP_PARAMS_2 is a constant read-only register that contains encoded information …
32884 …<description>The values of these bit fields are derived from the DMAH_CH0_MULTI_BLK_TYPE coreConsu…
32891 <description>Unspecified</description>
32896 <description>Unspecified</description>
32901 <description>Unspecified</description>
32906 <description>Unspecified</description>
32911 <description>Unspecified</description>
32916 <description>Unspecified</description>
32921 <description>Unspecified</description>
32926 <description>Unspecified</description>
32931 <description>Unspecified</description>
32938 …<description>The values of these bit fields are derived from the DMAH_CH1_MULTI_BLK_TYPE coreConsu…
32945 <description>Unspecified</description>
32950 <description>Unspecified</description>
32955 <description>Unspecified</description>
32960 <description>Unspecified</description>
32965 <description>Unspecified</description>
32970 <description>Unspecified</description>
32975 <description>Unspecified</description>
32980 <description>Unspecified</description>
32985 <description>Unspecified</description>
32992 …<description>The values of these bit fields are derived from the DMAH_CH2_MULTI_BLK_TYPE coreConsu…
32999 <description>Unspecified</description>
33004 <description>Unspecified</description>
33009 <description>Unspecified</description>
33014 <description>Unspecified</description>
33019 <description>Unspecified</description>
33024 <description>Unspecified</description>
33029 <description>Unspecified</description>
33034 <description>Unspecified</description>
33039 <description>Unspecified</description>
33046 …<description>The values of these bit fields are derived from the DMAH_CH3_MULTI_BLK_TYPE coreConsu…
33053 <description>Unspecified</description>
33058 <description>Unspecified</description>
33063 <description>Unspecified</description>
33068 <description>Unspecified</description>
33073 <description>Unspecified</description>
33078 <description>Unspecified</description>
33083 <description>Unspecified</description>
33088 <description>Unspecified</description>
33093 <description>Unspecified</description>
33100 …<description>The values of these bit fields are derived from the DMAH_CH4_MULTI_BLK_TYPE coreConsu…
33107 <description>Unspecified</description>
33112 <description>Unspecified</description>
33117 <description>Unspecified</description>
33122 <description>Unspecified</description>
33127 <description>Unspecified</description>
33132 <description>Unspecified</description>
33137 <description>Unspecified</description>
33142 <description>Unspecified</description>
33147 <description>Unspecified</description>
33154 …<description>The values of these bit fields are derived from the DMAH_CH5_MULTI_BLK_TYPE coreConsu…
33161 <description>Unspecified</description>
33166 <description>Unspecified</description>
33171 <description>Unspecified</description>
33176 <description>Unspecified</description>
33181 <description>Unspecified</description>
33186 <description>Unspecified</description>
33191 <description>Unspecified</description>
33196 <description>Unspecified</description>
33201 <description>Unspecified</description>
33208 …<description>The values of these bit fields are derived from the DMAH_CH6_MULTI_BLK_TYPE coreConsu…
33215 <description>Unspecified</description>
33220 <description>Unspecified</description>
33225 <description>Unspecified</description>
33230 <description>Unspecified</description>
33235 <description>Unspecified</description>
33240 <description>Unspecified</description>
33245 <description>Unspecified</description>
33250 <description>Unspecified</description>
33255 <description>Unspecified</description>
33262 …<description>The values of these bit fields are derived from the DMAH_CH7_MULTI_BLK_TYPE coreConsu…
33269 <description>Unspecified</description>
33274 <description>Unspecified</description>
33279 <description>Unspecified</description>
33284 <description>Unspecified</description>
33289 <description>Unspecified</description>
33294 <description>Unspecified</description>
33299 <description>Unspecified</description>
33304 <description>Unspecified</description>
33309 <description>Unspecified</description>
33318 …<description>DMA_COMP_PARAMS_1 is a constant read-only register that contains encoded information …
33326 …<description>The values of these bit fields are derived from the DMAH_CH0_MAX_BLK_SIZE coreConsult…
33333 <description>Unspecified</description>
33338 <description>Unspecified</description>
33343 <description>Unspecified</description>
33348 <description>Unspecified</description>
33353 <description>Unspecified</description>
33358 <description>Unspecified</description>
33363 <description>Unspecified</description>
33368 <description>Unspecified</description>
33373 <description>Unspecified</description>
33378 <description>Unspecified</description>
33383 <description>Unspecified</description>
33390 …<description>The values of these bit fields are derived from the DMAH_CH1_MAX_BLK_SIZE coreConsult…
33397 <description>Unspecified</description>
33402 <description>Unspecified</description>
33407 <description>Unspecified</description>
33412 <description>Unspecified</description>
33417 <description>Unspecified</description>
33422 <description>Unspecified</description>
33427 <description>Unspecified</description>
33432 <description>Unspecified</description>
33437 <description>Unspecified</description>
33442 <description>Unspecified</description>
33447 <description>Unspecified</description>
33454 …<description>The values of these bit fields are derived from the DMAH_CH2_MAX_BLK_SIZE coreConsult…
33461 <description>Unspecified</description>
33466 <description>Unspecified</description>
33471 <description>Unspecified</description>
33476 <description>Unspecified</description>
33481 <description>Unspecified</description>
33486 <description>Unspecified</description>
33491 <description>Unspecified</description>
33496 <description>Unspecified</description>
33501 <description>Unspecified</description>
33506 <description>Unspecified</description>
33511 <description>Unspecified</description>
33518 …<description>The values of these bit fields are derived from the DMAH_CH3_MAX_BLK_SIZE coreConsult…
33525 <description>Unspecified</description>
33530 <description>Unspecified</description>
33535 <description>Unspecified</description>
33540 <description>Unspecified</description>
33545 <description>Unspecified</description>
33550 <description>Unspecified</description>
33555 <description>Unspecified</description>
33560 <description>Unspecified</description>
33565 <description>Unspecified</description>
33570 <description>Unspecified</description>
33575 <description>Unspecified</description>
33582 …<description>The values of these bit fields are derived from the DMAH_CH4_MAX_BLK_SIZE coreConsult…
33589 <description>Unspecified</description>
33594 <description>Unspecified</description>
33599 <description>Unspecified</description>
33604 <description>Unspecified</description>
33609 <description>Unspecified</description>
33614 <description>Unspecified</description>
33619 <description>Unspecified</description>
33624 <description>Unspecified</description>
33629 <description>Unspecified</description>
33634 <description>Unspecified</description>
33639 <description>Unspecified</description>
33646 …<description>The values of these bit fields are derived from the DMAH_CH5_MAX_BLK_SIZE coreConsult…
33653 <description>Unspecified</description>
33658 <description>Unspecified</description>
33663 <description>Unspecified</description>
33668 <description>Unspecified</description>
33673 <description>Unspecified</description>
33678 <description>Unspecified</description>
33683 <description>Unspecified</description>
33688 <description>Unspecified</description>
33693 <description>Unspecified</description>
33698 <description>Unspecified</description>
33703 <description>Unspecified</description>
33710 …<description>The values of these bit fields are derived from the DMAH_CH6_MAX_BLK_SIZE coreConsult…
33717 <description>Unspecified</description>
33722 <description>Unspecified</description>
33727 <description>Unspecified</description>
33732 <description>Unspecified</description>
33737 <description>Unspecified</description>
33742 <description>Unspecified</description>
33747 <description>Unspecified</description>
33752 <description>Unspecified</description>
33757 <description>Unspecified</description>
33762 <description>Unspecified</description>
33767 <description>Unspecified</description>
33774 …<description>The values of these bit fields are derived from the DMAH_CH7_MAX_BLK_SIZE coreConsult…
33781 <description>Unspecified</description>
33786 <description>Unspecified</description>
33791 <description>Unspecified</description>
33796 <description>Unspecified</description>
33801 <description>Unspecified</description>
33806 <description>Unspecified</description>
33811 <description>Unspecified</description>
33816 <description>Unspecified</description>
33821 <description>Unspecified</description>
33826 <description>Unspecified</description>
33831 <description>Unspecified</description>
33840 …<description>DMA_COMP_PARAMS_1 is a constant read-only register that contains encoded information …
33848 …<description>The value of this register is derived from the DMAH_BIG_ENDIAN coreConsultant paramet…
33855 <description>Unspecified</description>
33860 <description>Unspecified</description>
33867 …<description>The value of this register is derived from the DMAH_INTR_IO coreConsultant parameter.…
33874 <description>Unspecified</description>
33879 <description>Unspecified</description>
33884 <description>Unspecified</description>
33891 …<description>The value of this register is derived from the DMAH_MABRST coreConsultant parameter.<…
33898 <description>Unspecified</description>
33903 <description>Unspecified</description>
33910 <description>Reserved field- read-only</description>
33917 …<description>The value of this register is derived from the DMAH_NUM_CHANNELS coreConsultant param…
33924 <description>Unspecified</description>
33929 <description>Unspecified</description>
33934 <description>Unspecified</description>
33939 <description>Unspecified</description>
33944 <description>Unspecified</description>
33949 <description>Unspecified</description>
33954 <description>Unspecified</description>
33959 <description>Unspecified</description>
33966 …<description>The value of this register is derived from the DMAH_NUM_MASTER_INT coreConsultant par…
33973 <description>Unspecified</description>
33978 <description>Unspecified</description>
33983 <description>Unspecified</description>
33988 <description>Unspecified</description>
33995 …<description>The value of this register is derived from the DMAH_S_HDATA_WIDTH coreConsultant para…
34002 <description>Unspecified</description>
34007 <description>Unspecified</description>
34012 <description>Unspecified</description>
34017 <description>Unspecified</description>
34024 …<description>The value of this register is derived from the DMAH_M4_HDATA_WIDTH coreConsultant par…
34031 <description>Unspecified</description>
34036 <description>Unspecified</description>
34041 <description>Unspecified</description>
34046 <description>Unspecified</description>
34053 …<description>The value of this register is derived from the DMAH_M3_HDATA_WIDTH coreConsultant par…
34060 <description>Unspecified</description>
34065 <description>Unspecified</description>
34070 <description>Unspecified</description>
34075 <description>Unspecified</description>
34082 …<description>The value of this register is derived from the DMAH_M2_HDATA_WIDTH coreConsultant par…
34089 <description>Unspecified</description>
34094 <description>Unspecified</description>
34099 <description>Unspecified</description>
34104 <description>Unspecified</description>
34111 …<description>The value of this register is derived from the DMAH_M1_HDATA_WIDTH coreConsultant par…
34118 <description>Unspecified</description>
34123 <description>Unspecified</description>
34128 <description>Unspecified</description>
34133 <description>Unspecified</description>
34140 …<description>The value of this register is derived from the DMAH_NUM_HS_INT coreConsultant paramet…
34147 <description>Unspecified</description>
34152 <description>Unspecified</description>
34157 <description>Unspecified</description>
34162 <description>Unspecified</description>
34167 <description>Unspecified</description>
34172 <description>Unspecified</description>
34177 <description>Unspecified</description>
34182 <description>Unspecified</description>
34187 <description>Unspecified</description>
34192 <description>Unspecified</description>
34197 <description>Unspecified</description>
34202 <description>Unspecified</description>
34207 <description>Unspecified</description>
34212 <description>Unspecified</description>
34217 <description>Unspecified</description>
34222 <description>Unspecified</description>
34227 <description>Unspecified</description>
34234 …<description>The value of this register is derived from the DMAH_ADD_ENCODED_PARAMS coreConsultant…
34241 <description>Unspecified</description>
34246 <description>Unspecified</description>
34253 …<description>The value of this register is derived from the DMAH_STATIC_ENDIAN_SELECT coreConsulta…
34262 …<description>This is the DW_ahb_dmac Component Version register, which is a read-only register tha…
34270 <description>DMA Component Type Number = `h44571110.</description>
34279 …description>This is the DW_ahb_dmac Component Version register, which is a read-only register that…
34287 <description>DMA Component Version.</description>
34300 <description>I3CCORE 1</description>
34307 <description>DMU 0</description>
34322 <description>DMU Core Release</description>
34330 <description>Core Release</description>
34336 <description>Step of Core Release</description>
34342 <description>Sub-step of Core Release</description>
34348 <description>Time Stamp Year</description>
34354 <description>Time Stamp Month</description>
34360 <description>Time Stamp Day</description>
34368 <description>DMU Internals</description>
34376 <description>TX Service Request line of DMU</description>
34382 <description>No TX DMA service requested</description>
34387 <description>TX DMA Service requested</description>
34394 <description>RX0 Service Request line of DMU</description>
34400 <description>No RX0 DMA service requested</description>
34405 <description>RX0 DMA Service requested</description>
34412 <description>RX1 Service Request line of DMU</description>
34418 <description>No RX1 DMA service requested</description>
34423 <description>RX1 DMA Service requested</description>
34430 <description>TX Event Service Request line of DMU</description>
34436 <description>No TX Event DMA service requested</description>
34441 <description>TX Event DMA Service requested</description>
34448 <description>TX FIFO/Queue Put Index Previous</description>
34454 <description>DMU is enabled</description>
34460 <description>DMU is disabled</description>
34465 <description>DMU is enabled and can process DMA data</description>
34472 <description>Detect Element Handler State</description>
34478 <description>Detect DMU Element Service</description>
34484 … <description>Queueing of DMU Element does not activate interrupt flag</description>
34489 …<description>Queueing of DMU Element will activate interrupt flag when DMUI.EHS = DMUI.DEHS</descr…
34496 <description>Detect DMU Element Service</description>
34502 … <description>Queueing of DMU Element does not activate interrupt flag</description>
34507 …<description>Queueing of DMU Element will activate interrupt flag when DMUI.EHS = DMUI.DEHS</descr…
34514 <description>Detect DMU Element Service</description>
34520 … <description>Queueing of DMU Element does not activate interrupt flag</description>
34525 …<description>Queueing of DMU Element will activate interrupt flag when DMUI.EHS = DMUI.DEHS</descr…
34532 <description>Detect DMU Element Service</description>
34538 … <description>Queueing of DMU Element does not activate interrupt flag</description>
34543 …<description>Queueing of DMU Element will activate interrupt flag when DMUI.EHS = DMUI.DEHS</descr…
34550 <description>Element Handler State</description>
34556 <description>wait for bit MCAN:CCCR.CCE getting zero</description>
34561 <description>wait for Start Address</description>
34566 <description>wait for Trigger Address</description>
34571 <description>wait for transfer of Element word</description>
34576 <description>acknowledge to MCAN</description>
34581 <description>exception recovery</description>
34588 <description>Actual DMU Element Service</description>
34594 <description>DMU Virtual Buffer is currently not served</description>
34599 <description>DMU Virtual Buffer is currently served</description>
34606 <description>Actual DMU Element Service</description>
34612 <description>DMU Virtual Buffer is currently not served</description>
34617 <description>DMU Virtual Buffer is currently served</description>
34624 <description>Actual DMU Element Service</description>
34630 <description>DMU Virtual Buffer is currently not served</description>
34635 <description>DMU Virtual Buffer is currently served</description>
34642 <description>Actual DMU Element Service</description>
34648 <description>DMU Virtual Buffer is currently not served</description>
34653 <description>DMU Virtual Buffer is currently served</description>
34662 <description>DMU Queueing Counter</description>
34670 <description>TX Element Enqueueing Counter</description>
34676 <description>RX0 Element Dequeueing Counter</description>
34682 <description>RX1 Element Dequeueing Counter</description>
34688 <description>TX Event Element Dequeueing Counter</description>
34696 <description>DMU Interrupt Register</description>
34704 <description>TX Element Not Start Address</description>
34710 <description>Write '1' to clear interrupt flag</description>
34715 <description>No illegal write access</description>
34720 …<description>Write to TX Element begins without using start address, exception recovery started.</…
34727 <description>TX Element Illegal Enqueueing</description>
34733 <description>Write '1' to clear interrupt flag</description>
34738 <description>No illegal enqueueing</description>
34743 …<description>Start of enqueueing without request detected, exception recovery started.</descriptio…
34750 <description>TX Element Illegal Access Sequence</description>
34756 <description>Write '1' to clear interrupt flag</description>
34761 <description>No illegal addressing sequence detected</description>
34766 …<description>Accesses are not strictly linear to ascending and consecutive addresses, exception re…
34773 <description>TX Element Illegal DLC</description>
34779 <description>Write '1' to clear interrupt flag</description>
34784 <description>No illegal DLC detected</description>
34789 … <description>DLC exceeds Tx Buffer element size of MCAN, exception recovery started.</description>
34796 <description>TX Element Write After Trigger Address</description>
34802 <description>Write '1' to clear interrupt flag</description>
34807 <description>No write after Trigger Address</description>
34812 <description>Write after Trigger address detected</description>
34819 <description>TX Element Illegal Read</description>
34825 <description>Write '1' to clear interrupt flag</description>
34830 <description>No read access</description>
34835 …<description>Illegal read access to DMU TX Element section detected, exception recovery started.</…
34842 …<description>A successful enqueueing of a Tx message with the DMU TX Element section sets this fla…
34848 <description>Write '1' to clear interrupt flag</description>
34853 <description>No Tx message enqueued</description>
34858 <description>Tx message successfully enqueued</description>
34865 <description>RX0 Element Not Start Address</description>
34871 <description>Write '1' to clear interrupt flag</description>
34876 <description>No illegal read access</description>
34881 …<description>Read from RX0 Element begins without using start address, exception recovery started.…
34888 <description>RX0 Element Illegal Dequeueing</description>
34894 <description>Write '1' to clear interrupt flag</description>
34899 <description>No illegal dequeueing</description>
34904 …<description>Start of dequeueing without request detected, exception recovery started,</descriptio…
34911 <description>RX0 Element Illegal Access Sequence</description>
34917 <description>Write '1' to clear interrupt flag</description>
34922 <description>No illegal addressing sequence detected</description>
34927 …<description>Accesses are not strictly linear to ascending and consecutive addresses, exception re…
34934 <description>RX0 Element Illegal Write</description>
34940 <description>Write '1' to clear interrupt flag</description>
34945 <description>No write access detected</description>
34950 …<description>Illegal write access to DMU RX0 Element detected, exception recovery started.</descri…
34957 <description>RX0 Element Dequeued</description>
34963 <description>Write '1' to clear interrupt flag</description>
34968 <description>No Rx message dequeued</description>
34973 <description>Rx message successfully dequeued</description>
34980 <description>RX0 Element Illegal Overwrite by timestamp</description>
34986 <description>Write '1' to clear interrupt flag</description>
34991 <description>No illegal overwrite detected</description>
34996 … <description>DMU has internally overwritten the last element word of a SYNC message</description>
35003 <description>Bus Error Uncorrected</description>
35009 <description>Write '1' to clear interrupt flag</description>
35014 … <description>No read slave error detected when reading from Message RAM</description>
35019 <description>Read slave error detected</description>
35026 <description>RX1 Element Not Start Address</description>
35032 <description>Write '1' to clear interrupt flag</description>
35037 <description>No illegal read access</description>
35042 …<description>Read from RX1 Element begins without using start address, exception recovery started.…
35049 <description>RX1 Element Illegal Dequeueing</description>
35055 <description>Write '1' to clear interrupt flag</description>
35060 <description>No illegal dequeueing</description>
35065 …<description>Start of dequeueing without request detected, exception recovery started,</descriptio…
35072 <description>RX0 Element Illegal Access Sequence</description>
35078 <description>Write '1' to clear interrupt flag</description>
35083 <description>No illegal addressing sequence detected</description>
35088 …<description>Accesses are not strictly linear to ascending and consecutive addresses, exception re…
35095 <description>RX1 Element Illegal Write</description>
35101 <description>Write '1' to clear interrupt flag</description>
35106 <description>No write access detected</description>
35111 …<description>Illegal write access to DMU RX1 Element detected, exception recovery started.</descri…
35118 <description>RX0 Element Dequeued</description>
35124 <description>Write '1' to clear interrupt flag</description>
35129 <description>No Rx message dequeued</description>
35134 <description>Rx message successfully dequeued</description>
35141 <description>RX1 Element Illegal Overwrite by timestamp</description>
35147 <description>Write '1' to clear interrupt flag</description>
35152 <description>No illegal overwrite detected</description>
35157 … <description>DMU has internally overwritten the last element word of a SYNC message</description>
35164 <description>TX Event Element Not Start Address</description>
35170 <description>Write '1' to clear interrupt flag</description>
35175 <description>No illegal read access</description>
35180 …<description>Read from TX Event Element begins without using start address, exception recovery sta…
35187 <description>TX Event Element Illegal Dequeueing</description>
35193 <description>Write '1' to clear interrupt flag</description>
35198 <description>No illegal dequeueing</description>
35203 …<description>Start of dequeueing without request detected, exception recovery started.</descriptio…
35210 <description>TX Event Element Illegal Access Sequence</description>
35216 <description>Write '1' to clear interrupt flag</description>
35221 <description>No illegal addressing sequence detected</description>
35226 …<description>Accesses are not strictly linear to ascending and consecutive addresses, exception re…
35233 <description>TX Event Element Illegal Write</description>
35239 <description>Write '1' to clear interrupt flag</description>
35244 <description>No write access detected</description>
35249 …<description>Illegal write access to DMU TX Event Element detected, exception recovery started.</d…
35256 <description>TX Event Element Dequeued</description>
35262 <description>Write '1' to clear interrupt flag</description>
35267 <description>No TX Event Element dequeued</description>
35272 <description>TX Event Element successfully dequeued</description>
35279 <description>Debug Trigger</description>
35285 <description>Write '1' to clear interrupt flag</description>
35290 <description>Debug point not reached</description>
35295 <description>Debug point reached</description>
35302 <description>Illegal Access while in Configuration mode</description>
35308 <description>Write '1' to clear interrupt flag</description>
35313 <description>No Illegal Access while CCE mode</description>
35318 <description>Illegal Access while CCE mode</description>
35327 <description>DMU Interrupt Enable</description>
35335 <description>TX Element Not Start Address Enable</description>
35341 <description>Flag does not activate the interrupt line DMU</description>
35346 <description>the interrupt line DMU will be activated</description>
35355 <description>DMU Configuration</description>
35363 <description>Transfer Timestamp</description>
35369 <description>No timestamp will be transferred via DMU Virtual Buffer</description>
35374 …<description>Timestamp of message will be transferred from TSU via DMU Virtual Buffer</description>
35385 <description>MCAN 0</description>
35401 <description>Endian Register</description>
35409 <description>Endianness Test Value</description>
35417 <description>Data Bit Timing and Prescaler Register</description>
35425 <description>Data (Re)Synchronization Jump Width</description>
35431 <description>Data time segment after sample point</description>
35437 <description>Data time segment before sample point</description>
35443 <description>Data Bit Rate Prescaler</description>
35449 <description>Transmitter Delay Compensation</description>
35455 <description>Unspecified</description>
35460 <description>Unspecified</description>
35469 <description>Test Register</description>
35477 <description>Loop Back Mode</description>
35483 <description>Loop Back Mode is disabled</description>
35488 <description>Loop Back Mode is enabled</description>
35495 <description>Control of Transmit Pin</description>
35501 … <description>controlled by the CAN Core, updated at the end of the CAN bit time</description>
35506 <description>Sample Point can be monitored at pin m_can_tx</description>
35511 <description>Dominant (0) level at pin m_can_tx</description>
35516 <description>Recessive (1) at pin m_can_tx</description>
35523 <description>Receive Pin</description>
35529 <description>The CAN bus is dominant (m_can_rx = 0)</description>
35534 <description>The CAN bus is recessive (m_can_rx = '1')</description>
35541 <description>Tx Buffer Number Prepared</description>
35547 <description>Prepared Valid</description>
35553 <description>Value of TXBNP not valid</description>
35558 <description>Value of TXBNP valid</description>
35565 <description>Tx Buffer Number Started</description>
35571 <description>Started Valid</description>
35577 <description>Value of TXBNP not valid</description>
35582 <description>Value of TXBNP valid</description>
35591 <description>RAM Watchdog</description>
35599 …<description>Start value of the Message RAM Watchdog Counter. With the reset value of '00' the cou…
35600 disabled.</description>
35606 <description>Actual Message RAM Watchdog Counter Value.</description>
35614 <description>CC Control Register</description>
35622 <description>Initialization</description>
35628 <description>Normal Operation</description>
35633 <description>Initialization is started</description>
35640 <description>Configuration Change Enable</description>
35646 … <description>The CPU has no write access to the protected configuration registers</description>
35651 …<description>The CPU has write access to the protected configuration registers (while CCCR.INIT = …
35658 <description>Restricted Operation Mode</description>
35664 <description>Normal CAN operation</description>
35669 <description>Restricted Operation Mode active</description>
35676 <description>Clock Stop Acknowledge</description>
35682 <description>No clock stop acknowledged</description>
35687 … <description>MCAN may be set in power down by stopping m_can_hclk and m_can_cclk</description>
35694 <description>Clock Stop Request</description>
35700 <description>No clock stop is requested</description>
35705 <description>Clock stop requested.</description>
35712 <description>Bus Monitoring Mode</description>
35718 <description>Bus Monitoring Mode is disabled</description>
35723 <description>Bus Monitoring Mode is enabled</description>
35730 <description>Disable Automatic Retransmission</description>
35736 …<description>Automatic retransmission of messages not transmitted successfully enabled</descriptio…
35741 <description>Automatic retransmission disabled</description>
35748 <description>Test Mode Enable</description>
35754 <description>Normal operation, register TEST holds reset values</description>
35759 <description>Test Mode, write access to register TEST enabled</description>
35766 <description>FD Operation Enable</description>
35772 <description>FD operation disabled</description>
35777 <description>FD operation enabled</description>
35784 <description>Bit Rate Switch Enable</description>
35790 <description>Bit rate switching for transmissions disabled</description>
35795 <description>Bit rate switching for transmissions enabled</description>
35802 <description>Wide Message Marker</description>
35808 <description>8-bit Message Marker used</description>
35813 …<description>16-bit Message Marker used, replacing 16-bit timestamps in Tx Event FIFO</description>
35820 <description>Protocol Exception Handling Disable</description>
35826 <description>Protocol exception handling enabled</description>
35831 <description>Protocol exception handling disabled</description>
35838 <description>Edge Filtering during Bus Integration</description>
35844 <description>Edge filtering disabled</description>
35849 …<description>Two consecutive dominant tq required to detect an edge for hard synchronization</desc…
35856 <description>Transmit Pause</description>
35862 <description>Transmit pause disabled</description>
35867 <description>Transmit pause enabled</description>
35874 <description>Non ISO Operation</description>
35880 <description>CAN FD frame format according to ISO 11898-1:2015</description>
35885 … <description>CAN FD frame format according to Bosch CAN FD Specification V1.0</description>
35894 <description>Nominal Bit Timing and Prescaler Register</description>
35902 <description>Nominal Time segment after sample point</description>
35908 <description>Nominal Time segment before sample point</description>
35914 <description>Nominal Bit Rate Prescaler</description>
35920 <description>Nominal (Re)Synchronization Jump Width</description>
35928 <description>Timestamp Counter Configuration</description>
35936 <description>Timestamp Select</description>
35942 <description>Timestamp counter value always 0x0000</description>
35947 <description>Timestamp counter value incremented according to TCP</description>
35952 <description>External timestamp counter value used</description>
35957 <description>Same as Zero</description>
35964 <description>Timestamp Counter Prescaler</description>
35972 <description>Timestamp Counter Value</description>
35980 <description>Timestamp Counter</description>
35988 <description>Timeout Counter Configuration</description>
35996 <description>Enable Timeout Counter</description>
36002 <description>Timeout Counter disabled</description>
36007 <description>Timeout Counter enabled</description>
36014 <description>Timeout Select</description>
36020 <description>Continuous operation</description>
36025 <description>Timeout controlled by Tx Event FIFO</description>
36030 <description>Timeout controlled by Rx FIFO 0</description>
36035 <description>Timeout controlled by Rx FIFO 1</description>
36042 <description>Timeout Period</description>
36050 <description>Timeout Counter Value</description>
36058 <description>Timeout Counter</description>
36066 <description>Error Counter Register</description>
36074 <description>Transmit Error Counter</description>
36080 <description>Receive Error Counter</description>
36086 <description>Receive Error Passive</description>
36092 … <description>The Receive Error Counter is below the error passive level of 128</description>
36097 … <description>The Receive Error Counter has reached the error passive level of 128</description>
36104 <description>CAN Error Logging</description>
36112 <description>Protocol Status Register</description>
36120 <description>Last Error Code</description>
36126 …<description>No error occurred since LEC has been reset by successful reception or transmission.</…
36131 … <description>More than 5 equal bits in a sequence have occurred in a part of a received message
36132 where this is not allowed.</description>
36137 … <description>A fixed format part of a received frame has the wrong format.</description>
36142 …<description>The message transmitted by the MCAN was not acknowledged by another node.</descriptio…
36147 … <description>During the transmission of a message (with the exception of the arbitration field),
36149 value was dominant.</description>
36154 … <description>During the transmission of a message (or acknowledge bit, or active error flag, or
36159 dominant or continuously disturbed).</description>
36164 … <description>The CRC check sum of a received message was incorrect. The CRC of an incoming
36165 message does not match with the CRC calculated from the received data.</description>
36170 … <description>Any read access to the Protocol Status Register re-initializes the LEC to '7'.
36172 access to the Protocol Status Register.</description>
36179 <description>Activity</description>
36185 <description>Node is synchronizing on CAN communication</description>
36190 <description>Node is neither receiver nor tr ansmitter</description>
36195 <description>Node is operating as receiver</description>
36200 <description>Node is operating as transmitter</description>
36207 <description>Error Passive</description>
36213 …<description>The MCAN is in the Error_Active state. It normally takes part in bus communication and
36214 sends an active error flag when an error has been detected</description>
36219 <description>The MCAN is in the Error_Passive state</description>
36226 <description>Warning Status</description>
36232 … <description>Both error counters are below the Error_Warning limit of 96</description>
36237 … <description>At least one of error counter has reached the Error_Warning limit of 96</description>
36244 <description>Bus_Off Status</description>
36250 <description>The MCAN is not Bus_Off</description>
36255 <description>The MCAN is in Bus_Off state</description>
36262 <description>Data Phase Last Error Code</description>
36268 <description>ESI flag of last received CAN FD Message</description>
36274 … <description>Last received CAN FD message did not ha ve its ESI flag set</description>
36279 <description>Last received CAN FD message had its ESI flag set</description>
36286 <description>BRS flag of last received CAN FD Message</description>
36292 … <description>Last received CAN FD message did not ha ve its BRS flag set</description>
36297 <description>Last received CAN FD message had its BRS flag set</description>
36304 <description>Received a CAN FD Message</description>
36310 …<description>Since this bit was reset by the CPU, no CAN FD message has been received</description>
36315 … <description>Message in CAN FD format with FDF flag set has been received</description>
36322 <description>Protocol Exception Event</description>
36328 … <description>No protocol exception event occurred since last read access</description>
36333 <description>Protocol exception event occurred</description>
36340 <description>Transmitter Delay Compensation Value</description>
36348 <description>Transmitter Delay Compensation Register</description>
36356 <description>Transmitter Delay Compensation Filter Window Length</description>
36362 <description>Transmitter Delay Compensation SSP Offset</description>
36370 <description>Interrupt Register</description>
36378 <description>Rx FIFO 0 New Message</description>
36384 <description>Write '1' to clear interrupt flag</description>
36389 <description>No new message written to Rx FIFO 0</description>
36394 <description>New message written to Rx FIFO 0</description>
36401 <description>Rx FIFO 0 Watermark Reached</description>
36407 <description>Write '1' to clear interrupt flag</description>
36412 <description>Rx FIFO 0 fill level below watermark</description>
36417 <description>Rx FIFO 0 fill level reached watermark</description>
36424 <description>Rx FIFO 0 Full</description>
36430 <description>Write '1' to clear interrupt flag</description>
36435 <description>Rx FIFO 0 not full</description>
36440 <description>Rx FIFO 0 full</description>
36447 <description>Rx FIFO 0 Message Lost</description>
36453 <description>Write '1' to clear interrupt flag</description>
36458 <description>No Rx FIFO 0 message lost</description>
36463 …<description>Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero</descr…
36470 <description>Rx FIFO 1 New Message</description>
36476 <description>Write '1' to clear interrupt flag</description>
36481 <description>No new message written to Rx FIFO 1</description>
36486 <description>New message written to Rx FIFO 1</description>
36493 <description>Rx FIFO 1 Watermark Reached</description>
36499 <description>Write '1' to clear interrupt flag</description>
36504 <description>Rx FIFO 1 fill level below watermark</description>
36509 <description>Rx FIFO 1 fill level reached watermark</description>
36516 <description>Rx FIFO 1 Full</description>
36522 <description>Write '1' to clear interrupt flag</description>
36527 <description>Rx FIFO 1 not full</description>
36532 <description>Rx FIFO 1 full</description>
36539 <description>Rx FIFO 1 Message Lost</description>
36545 <description>Write '1' to clear interrupt flag</description>
36550 <description>No Rx FIFO 1 message lost</description>
36555 …<description>Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero</descr…
36562 <description>High Priority Message</description>
36568 <description>Write '1' to clear interrupt flag</description>
36573 <description>No high priority message received</description>
36578 <description>High priority message received</description>
36585 <description>Transmission Completed</description>
36591 <description>Write '1' to clear interrupt flag</description>
36596 <description>No transmission completed</description>
36601 <description>Transmission completed</description>
36608 <description>Transmission Cancellation Finished</description>
36614 <description>Write '1' to clear interrupt flag</description>
36619 <description>No transmission cancellation finished</description>
36624 <description>Transmission cancellation finished</description>
36631 <description>Tx FIFO Empty</description>
36637 <description>Write '1' to clear interrupt flag</description>
36642 <description>Tx FIFO non-empty</description>
36647 <description>Tx FIFO empty</description>
36654 <description>Tx Event FIFO New Entry</description>
36660 <description>Write '1' to clear interrupt flag</description>
36665 <description>Tx Event FIFO unchanged</description>
36670 <description>Tx Handler wrote Tx Event FIFO element</description>
36677 <description>Tx Event FIFO Watermark Reached</description>
36683 <description>Write '1' to clear interrupt flag</description>
36688 <description>Tx Event FIFO fill level below watermark</description>
36693 <description>Tx Event FIFO fill level reached watermark</description>
36700 <description>Tx Event FIFO Full</description>
36706 <description>Write '1' to clear interrupt flag</description>
36711 <description>Tx Event FIFO not full</description>
36716 <description>Tx Event FIFO full</description>
36723 <description>Tx Event FIFO Element Lost</description>
36729 <description>Write '1' to clear interrupt flag</description>
36734 <description>No Tx Event FIFO element lost</description>
36739 …<description>Tx Event FIFO element lost, also set after wr ite attempt to Tx Event FIFO of siz e z…
36746 <description>Timestamp Wraparound</description>
36752 <description>Write '1' to clear interrupt flag</description>
36757 <description>No timestamp counter wrap-around</description>
36762 <description>Timestamp counter wrapped around</description>
36769 <description>Message RAM Access Failure</description>
36775 <description>Write '1' to clear interrupt flag</description>
36780 <description>No Message RAM access failure occurred</description>
36785 <description>Message RAM access failure occurred</description>
36792 <description>Timeout Occurred</description>
36798 <description>Write '1' to clear interrupt flag</description>
36803 <description>No timeout</description>
36808 <description>Timeout reached</description>
36815 <description>Message stored to Dedicated Rx Buffer</description>
36821 <description>Write '1' to clear interrupt flag</description>
36826 <description>No Rx Buffer updated</description>
36831 <description>At least one received message stored into an Rx Buff er</description>
36838 <description>Bus Error Uncorrected</description>
36844 <description>Write '1' to clear interrupt flag</description>
36849 … <description>No read slave error detected when reading from Message RAM</description>
36854 <description>Read slave error detected</description>
36861 <description>Error Logging Overflow</description>
36867 <description>Write '1' to clear interrupt flag</description>
36872 <description>CAN Error Logging Counter did not overflow</description>
36877 <description>Overflow of CAN Error Logging Counter occurred</description>
36884 <description>Error Passive</description>
36890 <description>Write '1' to clear interrupt flag</description>
36895 <description>Error_Passive status unchanged</description>
36900 <description>Error_Passive status changed</description>
36907 <description>Warning Status</description>
36913 <description>Write '1' to clear interrupt flag</description>
36918 <description>Error_Warning status unchanged</description>
36923 <description>Error_Warning status changed</description>
36930 <description>Bus_Off Status</description>
36936 <description>Write '1' to clear interrupt flag</description>
36941 <description>Bus_Off status unchanged</description>
36946 <description>Bus_Off status changed</description>
36953 <description>Watchdog Interrupt</description>
36959 <description>Write '1' to clear interrupt flag</description>
36964 <description>No Message RAM Watchdog event occurred</description>
36969 <description>Message RAM Watchdog event due to missing READY</description>
36976 … <description>Protocol Error in Arbitration Phase (Nominal Bit Time is used)</description>
36982 <description>Write '1' to clear interrupt flag</description>
36987 <description>No protocol error in arbitration phase</description>
36992 … <description>Protocol error in arbitration phase detected (PSR.LEC ≠ 0,7)</description>
36999 <description>Protocol Error in Data Phase (Data Bit Time is used)</description>
37005 <description>Write '1' to clear interrupt flag</description>
37010 <description>No protocol error in data phase</description>
37015 <description>Protocol error in data phase detected (PSR.DLEC ≠ 0,7)</description>
37022 <description>Access to Reserved Address</description>
37028 <description>Write '1' to clear interrupt flag</description>
37033 <description>No access to reserved address occurred</description>
37038 <description>Access to reserved address occurred</description>
37047 <description>Interrupt Enable</description>
37055 <description>Rx FIFO 0 New Message Interrupt Enable</description>
37061 <description>Interrupt disabled.</description>
37066 <description>Interrupt enabled.</description>
37073 <description>Rx FIFO 0 Watermark Reached Interrupt Enable</description>
37079 <description>Interrupt disabled.</description>
37084 <description>Interrupt enabled.</description>
37091 <description>Rx FIFO 0 Full Interrupt Enable</description>
37097 <description>Interrupt disabled.</description>
37102 <description>Interrupt enabled.</description>
37109 <description>Rx FIFO 0 Message Lost Interrupt Enable</description>
37115 <description>Interrupt disabled.</description>
37120 <description>Interrupt enabled.</description>
37127 <description>Rx FIFO 1 New Message Interrupt Enable</description>
37133 <description>Interrupt disabled.</description>
37138 <description>Interrupt enabled.</description>
37145 <description>Rx FIFO 1 Watermark Reached Interrupt Enable</description>
37151 <description>Interrupt disabled.</description>
37156 <description>Interrupt enabled.</description>
37163 <description>Rx FIFO 1 Full Interrupt Enable</description>
37169 <description>Interrupt disabled.</description>
37174 <description>Interrupt enabled.</description>
37181 <description>Rx FIFO 1 Message Lost Interrupt Enable</description>
37187 <description>Interrupt disabled.</description>
37192 <description>Interrupt enabled.</description>
37199 <description>High Priority Message Interrupt Enable</description>
37205 <description>Interrupt disabled.</description>
37210 <description>Interrupt enabled.</description>
37217 <description>Transmission Completed Interrupt Enable</description>
37223 <description>Interrupt disabled.</description>
37228 <description>Interrupt enabled.</description>
37235 <description>Transmission Cancellation Finished Interrupt Enable</description>
37241 <description>Interrupt disabled.</description>
37246 <description>Interrupt enabled.</description>
37253 <description>Tx FIFO Empty Interrupt Enable</description>
37259 <description>Interrupt disabled.</description>
37264 <description>Interrupt enabled.</description>
37271 <description>Tx Event FIFO New Entry Interrupt Enable</description>
37277 <description>Interrupt disabled.</description>
37282 <description>Interrupt enabled.</description>
37289 <description>Tx Event FIFO Watermark Reached Interrupt Enable</description>
37295 <description>Interrupt disabled.</description>
37300 <description>Interrupt enabled.</description>
37307 <description>Tx Event FIFO Full Interrupt Enable</description>
37313 <description>Interrupt disabled.</description>
37318 <description>Interrupt enabled.</description>
37325 <description>Tx Event FIFO Event Lost Interrupt Enable</description>
37331 <description>Interrupt disabled.</description>
37336 <description>Interrupt enabled.</description>
37343 <description>Timestamp Wraparound Interrupt Enable</description>
37349 <description>Interrupt disabled.</description>
37354 <description>Interrupt enabled.</description>
37361 <description>Message RAM Access Failure Interrupt Enable</description>
37367 <description>Interrupt disabled.</description>
37372 <description>Interrupt enabled.</description>
37379 <description>Timeout Occurred Interrupt Enable</description>
37385 <description>Interrupt disabled.</description>
37390 <description>Interrupt enabled.</description>
37397 <description>Message stored to Dedicated Rx Buffer Interrupt Enable</description>
37403 <description>Interrupt disabled.</description>
37408 <description>Interrupt enabled.</description>
37415 <description>Bus Error Uncorrected Interrupt Enable</description>
37421 <description>Interrupt disabled.</description>
37426 <description>Interrupt enabled.</description>
37433 <description>Error Logging Overflow Interrupt Enable</description>
37439 <description>Interrupt disabled.</description>
37444 <description>Interrupt enabled.</description>
37451 <description>Error Passive Interrupt Enable</description>
37457 <description>Interrupt disabled.</description>
37462 <description>Interrupt enabled.</description>
37469 <description>Warning Status Interrupt Enable</description>
37475 <description>Interrupt disabled.</description>
37480 <description>Interrupt enabled.</description>
37487 <description>Bus_Off Status Interrupt Enable</description>
37493 <description>Interrupt disabled.</description>
37498 <description>Interrupt enabled.</description>
37505 <description>Watchdog Interrupt Enable</description>
37511 <description>Interrupt disabled.</description>
37516 <description>Interrupt enabled.</description>
37523 <description>Protocol Error in Arbitration Phase Enable</description>
37529 <description>Interrupt disabled.</description>
37534 <description>Interrupt enabled.</description>
37541 <description>Protocol Error in Data Phase Enable</description>
37547 <description>Interrupt disabled.</description>
37552 <description>Interrupt enabled.</description>
37559 <description>Access to Reserved Address Enable</description>
37565 <description>Interrupt disabled.</description>
37570 <description>Interrupt enabled.</description>
37579 <description>Interrupt Line Select</description>
37587 <description>Rx FIFO 0 New Message Interrupt Line</description>
37593 <description>Interrupt assigned to interrupt line CORE0.</description>
37598 <description>Interrupt assigned to interrupt line CORE1.</description>
37605 <description>Rx FIFO 0 Watermark Reached Interrupt Line</description>
37611 <description>Interrupt assigned to interrupt line CORE0.</description>
37616 <description>Interrupt assigned to interrupt line CORE1.</description>
37623 <description>Rx FIFO 0 Full Interrupt Line</description>
37629 <description>Interrupt assigned to interrupt line CORE0.</description>
37634 <description>Interrupt assigned to interrupt line CORE1.</description>
37641 <description>Rx FIFO 0 Message Lost Interrupt Line</description>
37647 <description>Interrupt assigned to interrupt line CORE0.</description>
37652 <description>Interrupt assigned to interrupt line CORE1.</description>
37659 <description>Rx FIFO 1 New Message Interrupt Line</description>
37665 <description>Interrupt assigned to interrupt line CORE0.</description>
37670 <description>Interrupt assigned to interrupt line CORE1.</description>
37677 <description>Rx FIFO 1 Watermark Reached Interrupt Line</description>
37683 <description>Interrupt assigned to interrupt line CORE0.</description>
37688 <description>Interrupt assigned to interrupt line CORE1.</description>
37695 <description>Rx FIFO 1 Full Interrupt Line</description>
37701 <description>Interrupt assigned to interrupt line CORE0.</description>
37706 <description>Interrupt assigned to interrupt line CORE1.</description>
37713 <description>Rx FIFO 1 Message Lost Interrupt Line</description>
37719 <description>Interrupt assigned to interrupt line CORE0.</description>
37724 <description>Interrupt assigned to interrupt line CORE1.</description>
37731 <description>High Priority Message Interrupt Line</description>
37737 <description>Interrupt assigned to interrupt line CORE0.</description>
37742 <description>Interrupt assigned to interrupt line CORE1.</description>
37749 <description>Transmission Completed Interrupt Line</description>
37755 <description>Interrupt assigned to interrupt line CORE0.</description>
37760 <description>Interrupt assigned to interrupt line CORE1.</description>
37767 <description>Transmission Cancellation Finished Interrupt Line</description>
37773 <description>Interrupt assigned to interrupt line CORE0.</description>
37778 <description>Interrupt assigned to interrupt line CORE1.</description>
37785 <description>Tx FIFO Empty Interrupt Line</description>
37791 <description>Interrupt assigned to interrupt line CORE0.</description>
37796 <description>Interrupt assigned to interrupt line CORE1.</description>
37803 <description>Tx Event FIFO New Entry Interrupt Line</description>
37809 <description>Interrupt assigned to interrupt line CORE0.</description>
37814 <description>Interrupt assigned to interrupt line CORE1.</description>
37821 <description>Tx Event FIFO Watermark Reached Interrupt Line</description>
37827 <description>Interrupt assigned to interrupt line CORE0.</description>
37832 <description>Interrupt assigned to interrupt line CORE1.</description>
37839 <description>Tx Event FIFO Full Interrupt Line</description>
37845 <description>Interrupt assigned to interrupt line CORE0.</description>
37850 <description>Interrupt assigned to interrupt line CORE1.</description>
37857 <description>Tx Event FIFO Event Lost Interrupt Line</description>
37863 <description>Interrupt assigned to interrupt line CORE0.</description>
37868 <description>Interrupt assigned to interrupt line CORE1.</description>
37875 <description>Timestamp Wraparound Interrupt Line</description>
37881 <description>Interrupt assigned to interrupt line CORE0.</description>
37886 <description>Interrupt assigned to interrupt line CORE1.</description>
37893 <description>Message RAM Access Failure Interrupt Line</description>
37899 <description>Interrupt assigned to interrupt line CORE0.</description>
37904 <description>Interrupt assigned to interrupt line CORE1.</description>
37911 <description>Timeout Occurred Interrupt Line</description>
37917 <description>Interrupt assigned to interrupt line CORE0.</description>
37922 <description>Interrupt assigned to interrupt line CORE1.</description>
37929 <description>Message stored to Dedicated Rx Buffer Interrupt Line</description>
37935 <description>Interrupt assigned to interrupt line CORE0.</description>
37940 <description>Interrupt assigned to interrupt line CORE1.</description>
37947 <description>Bus Error Uncorrected Interrupt Line</description>
37953 <description>Interrupt assigned to interrupt line CORE0.</description>
37958 <description>Interrupt assigned to interrupt line CORE1.</description>
37965 <description>Error Logging Overflow Interrupt Line</description>
37971 <description>Interrupt assigned to interrupt line CORE0.</description>
37976 <description>Interrupt assigned to interrupt line CORE1.</description>
37983 <description>Error Passive Interrupt Line</description>
37989 <description>Interrupt assigned to interrupt line CORE0.</description>
37994 <description>Interrupt assigned to interrupt line CORE1.</description>
38001 <description>Warning Status Interrupt Line</description>
38007 <description>Interrupt assigned to interrupt line CORE0.</description>
38012 <description>Interrupt assigned to interrupt line CORE1.</description>
38019 <description>Bus_Off Status Interrupt Line</description>
38025 <description>Interrupt assigned to interrupt line CORE0.</description>
38030 <description>Interrupt assigned to interrupt line CORE1.</description>
38037 <description>Watchdog Interrupt Line</description>
38043 <description>Interrupt assigned to interrupt line CORE0.</description>
38048 <description>Interrupt assigned to interrupt line CORE1.</description>
38055 <description>Protocol Error in Arbitration Phase Line</description>
38061 <description>Interrupt assigned to interrupt line CORE0.</description>
38066 <description>Interrupt assigned to interrupt line CORE1.</description>
38073 <description>Protocol Error in Data Phase Line</description>
38079 <description>Interrupt assigned to interrupt line CORE0.</description>
38084 <description>Interrupt assigned to interrupt line CORE1.</description>
38091 <description>Access to Reserved Address Line</description>
38097 <description>Interrupt assigned to interrupt line CORE0.</description>
38102 <description>Interrupt assigned to interrupt line CORE1.</description>
38111 <description>Interrupt Line Enable</description>
38119 <description>Enable Interrupt Line 0</description>
38125 <description>Interrupt line CORE0 disabled.</description>
38130 <description>Interrupt line CORE0 enabled.</description>
38137 <description>Enable Interrupt Line 1</description>
38143 <description>Interrupt line CORE1 disabled.</description>
38148 <description>Interrupt line CORE1 enabled.</description>
38157 <description>Global Filter Configuration</description>
38165 <description>Reject Remote Frames Extended</description>
38171 <description>Filter remote frames with 29-bit extended IDs.</description>
38176 <description>Reject all remote frames with 29-bit extended IDs.</description>
38183 <description>Reject Remote Frames Standard</description>
38189 <description>Filter remote frames with 11-bit standard IDs.</description>
38194 <description>Reject all remote frames with 11-bit standard IDs.</description>
38201 <description>Accept Non-matching Frames Extended</description>
38207 <description>Accept in Rx FIFO 0.</description>
38212 <description>Accept in Rx FIFO 1.</description>
38217 <description>Reject in both Rx FIFOs.</description>
38222 <description>Reject in both Rx FIFOs.</description>
38234 <description>Accept in Rx FIFO 0.</description>
38239 <description>Accept in Rx FIFO 1.</description>
38244 <description>Reject in both Rx FIFOs.</description>
38249 <description>Reject in both Rx FIFOs.</description>
38258 <description>Standard ID Filter Configuration</description>
38266 <description>Filter List Standard Start Address</description>
38272 <description>List Size Standard</description>
38280 <description>Extended ID Filter Configuration</description>
38288 <description>Filter List Extended Start Address</description>
38294 <description>List Size Extended</description>
38302 <description>Extended ID AND Mask</description>
38310 <description>Extended ID Mask</description>
38318 <description>High Priority Message Status</description>
38326 <description>Buffer Index</description>
38332 <description>Message Storage Indicator</description>
38338 <description>No FIFO selected.</description>
38343 <description>FIFO message lost.</description>
38348 <description>Message stored in FIFO 0.</description>
38353 <description>Message stored in FIFO 1.</description>
38360 <description>Filter Index</description>
38366 <description>Filter List</description>
38372 <description>Standard Filter List.</description>
38377 <description>Extended Filter List.</description>
38386 <description>New Data 1</description>
38394 <description>New Data</description>
38400 <description>Rx Buffer not updated.</description>
38405 <description>Rx Buffer updated from new message.</description>
38414 <description>New Data 2</description>
38422 <description>New Data</description>
38428 <description>Rx Buffer not updated.</description>
38433 <description>Rx Buffer updated from new message.</description>
38442 <description>Rx FIFO 0 Configuration</description>
38450 <description>Rx FIFO 0 Start Address</description>
38456 <description>Rx FIFO 0 Size</description>
38462 <description>Rx FIFO 0 Watermark</description>
38468 <description>FIFO 0 Operation Mode</description>
38474 <description>FIFO 0 blocking mode.</description>
38479 <description>FIFO 0 overwrite mode.</description>
38488 <description>Rx FIFO 0 Status</description>
38496 <description>Rx FIFO 0 Fill Leve</description>
38502 <description>Rx FIFO 0 Get Index</description>
38508 <description>Rx FIFO 0 Put Index</description>
38514 <description>Rx FIFO 0 Full</description>
38520 <description>Rx FIFO 0 not full.</description>
38525 <description>Rx FIFO 0 full.</description>
38532 <description>Rx FIFO 0 Message Lost</description>
38538 <description>No Rx FIFO 0 message lost.</description>
38543 …<description>Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero.</desc…
38552 <description>Rx FIFO 0 Acknowledge</description>
38560 <description>Rx FIFO 0 Acknowledge Index</description>
38568 <description>Rx Buffer Configuration</description>
38576 <description>Rx Buffer Start Address</description>
38584 <description>Rx FIFO 1 Configuration</description>
38592 <description>Rx FIFO 1 Start Address</description>
38598 <description>Rx FIFO 1 Size</description>
38604 <description>Rx FIFO 1 Watermark</description>
38610 <description>FIFO 1 Operation Mode</description>
38616 <description>FIFO 1 blocking mode</description>
38621 <description>FIFO 1 overwrite mode</description>
38630 <description>Rx FIFO 1 Status</description>
38638 <description>Rx FIFO 1 Fill Level</description>
38644 <description>Rx FIFO 1 Get Index</description>
38650 <description>Rx FIFO 1 Put Index</description>
38656 <description>Rx FIFO 1 Full</description>
38662 <description>Rx FIFO 1 not full</description>
38667 <description>Rx FIFO 1 full</description>
38674 <description>Rx FIFO 1 Message Lost</description>
38680 <description>No Rx FIFO 1 message lost</description>
38685 …<description>Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero</descr…
38692 <description>Debug Message Status</description>
38698 …<description>Idle state, wait for reception of debug messages, DMA request is cleared</description>
38703 <description>Debug message A received</description>
38708 <description>Debug messages A, B received</description>
38713 <description>Debug messages A, B, C received, DMA request is set</description>
38722 <description>Rx FIFO 1 Acknowledge</description>
38730 <description>Rx FIFO 1 Acknowledge Index</description>
38738 <description>Rx Buffer / FIFO Element Size Configuration</description>
38746 <description>Rx FIFO 0 Data Field Size</description>
38752 <description>8 byte data field</description>
38757 <description>12 byte data field</description>
38762 <description>16 byte data field</description>
38767 <description>20 byte data field</description>
38772 <description>24 byte data field</description>
38777 <description>32 byte data field</description>
38782 <description>48 byte data field</description>
38787 <description>64 byte data field</description>
38794 <description>Rx FIFO 1 Data Field Size</description>
38800 <description>8 byte data field</description>
38805 <description>12 byte data field</description>
38810 <description>16 byte data field</description>
38815 <description>20 byte data field</description>
38820 <description>24 byte data field</description>
38825 <description>32 byte data field</description>
38830 <description>48 byte data field</description>
38835 <description>64 byte data field</description>
38842 <description>Rx Buffer Data Field Size</description>
38848 <description>8 byte data field</description>
38853 <description>12 byte data field</description>
38858 <description>16 byte data field</description>
38863 <description>20 byte data field</description>
38868 <description>24 byte data field</description>
38873 <description>32 byte data field</description>
38878 <description>48 byte data field</description>
38883 <description>64 byte data field</description>
38892 <description>Tx Buffer Configuration</description>
38900 <description>Tx Buffers Start Address</description>
38906 <description>Number of Dedicated Transmit Buffers</description>
38912 <description>Transmit FIFO/Queue Size</description>
38918 <description>Tx FIFO/Queue Mode</description>
38924 <description>Tx FIFO operation</description>
38929 <description>Tx Queue operation</description>
38938 <description>Tx FIFO/Queue Status</description>
38946 <description>Tx FIFO Free Level</description>
38952 <description>Tx FIFO Get Index</description>
38958 <description>Tx FIFO/Queue Put Index</description>
38964 <description>Tx FIFO/Queue Full</description>
38970 <description>Tx FIFO/Queue not full</description>
38975 <description>Tx FIFO/Queue full</description>
38984 <description>Tx Buffer Element Size Configuration</description>
38992 <description>Tx Buffer Data Field Size</description>
38998 <description>8 byte data field</description>
39003 <description>12 byte data field</description>
39008 <description>16 byte data field</description>
39013 <description>20 byte data field</description>
39018 <description>24 byte data field</description>
39023 <description>32 byte data field</description>
39028 <description>48 byte data field</description>
39033 <description>64 byte data field</description>
39042 <description>Tx Buffer Request Pending</description>
39050 <description>Transmission Request Pending</description>
39056 <description>No transmission request pending</description>
39061 <description>Transmission request pending</description>
39070 <description>Tx Buffer Add Request</description>
39078 <description>Add Request</description>
39084 <description>No transmission request added</description>
39089 <description>Transmission requested added</description>
39098 <description>Tx Buffer Cancellation Request</description>
39106 <description>Cancellation Request</description>
39112 <description>No cancellation pending</description>
39117 <description>Cancellation pending</description>
39126 <description>Tx Buffer Transmission Occurred</description>
39134 <description>Transmission Occurred</description>
39140 <description>No transmission occurred</description>
39145 <description>Transmission occurred</description>
39154 <description>Tx Buffer Cancellation Finished</description>
39162 <description>Cancellation Finished</description>
39168 <description>No transmit buffer cancellation</description>
39173 <description>Transmit buffer cancellation finished</description>
39182 <description>Tx Buffer Transmission Interrupt Enable</description>
39190 <description>Transmission Interrupt Enable</description>
39196 <description>Transmission interrupt disabled</description>
39201 <description>Transmission interrupt enable</description>
39210 <description>Tx Buffer Cancellation Finished Interrupt Enable</description>
39218 <description>Cancellation Finished Interrupt Enable</description>
39224 <description>Cancellation finished interrupt disabled</description>
39229 <description>Cancellation finished interrupt enabled</description>
39238 <description>Tx Event FIFO Configuration</description>
39246 <description>Event FIFO Start Address</description>
39252 <description>Event FIFO Size</description>
39258 <description>Event FIFO Watermark</description>
39266 <description>Tx Event FIFO Status</description>
39274 <description>Event FIFO Fill Level</description>
39280 <description>Event FIFO Get Index</description>
39286 <description>Event FIFO Put Index</description>
39292 <description>Event FIFO Full</description>
39298 <description>Tx Event FIFO not full</description>
39303 <description>Tx Event FIFO full</description>
39310 <description>Tx Event FIFO Element Lost</description>
39316 <description>No Tx Event FIFO element lost</description>
39321 …<description>Tx Event FIFO element lost, also set after wr ite attempt to Tx Event FIFO of siz e z…
39330 <description>Tx Event FIFO Acknowledge</description>
39338 <description>Event FIFO Acknowledge Index</description>
39348 <description>DMU 1</description>
39355 <description>MCAN 1</description>
39363 <description>System Trace Macrocell data buffer</description>
39380 <description>Unspecified</description>
39388 …description>Description collection: STM extended stimulus port data buffer area for domain n. NonS…
39401 <description>TDDCONF</description>
39415 <description>System power-up request</description>
39423 <description>Activate power-up request</description>
39429 <description>Power-up request not active</description>
39434 <description>Power-up request active</description>
39443 <description>Debug power-up request</description>
39451 <description>Activate power-up request</description>
39457 <description>Power-up request not active</description>
39462 <description>Power-up request active</description>
39471 <description>Trace port trace clock speed</description>
39479 <description>Trace clock speed</description>
39485 <description>Speed 100MHz</description>
39490 <description>Speed 50MHz</description>
39495 <description>Speed 25MHz</description>
39500 <description>Speed 12.5MHz</description>
39509 …<description>Combined effective system status of both SWJ-DP and TDDCONF registers originated powe…
39517 <description>System powerup request status</description>
39523 <description>Power not requested</description>
39528 <description>Power requested</description>
39535 <description>Debug domain powerup request status</description>
39541 <description>Power not requested</description>
39546 <description>Power requested</description>
39557 <description>System Trace Macrocell</description>
39571 <description>Controls the DMA transfer request mechanism.</description>
39579 …<description>Determines the sensitivity of the DMA request to the current buffer level in the STM<…
39585 <description>Buffer is &lt;25 percent full.</description>
39590 <description>Buffer is &lt;50 percent full.</description>
39595 <description>Buffer is &lt;75 percent full.</description>
39600 <description>Buffer is &lt;100 percent full.</description>
39609 …<description>Indicates the STPv2 master number of hardware event trace. This number is the master …
39617 …<description>The STPv2 master number that hardware event traces should be associated with.</descri…
39625 <description>Indicates the features of the STM.</description>
39633 <description>STMHETER support</description>
39639 <description>The feature is not implemented.</description>
39644 <description>The feature is implemented.</description>
39651 <description>Hardware event error detection support</description>
39657 <description>The feature is not implemented.</description>
39662 <description>The feature is implemented.</description>
39669 <description>STMHEMASTR support</description>
39675 <description>The feature is not implemented.</description>
39680 <description>The feature is implemented.</description>
39687 <description>The number of hardware events supported by the STM</description>
39695 <description>Indicates the features of hardware event tracing in the STM.</description>
39703 <description>The CLASS field identifies the programmers model</description>
39709 <description>Hardware Event Control programmers model</description>
39716 … <description>The CLASSREV field identifies the revision of the programmers model</description>
39722 …<description>The VENDSPEC field identifies any vendor specific modifications or mappings</descript…
39730 <description>Controls the STM settings.</description>
39738 <description>Global STM enable</description>
39744 <description>The STM is disabled.</description>
39749 <description>The STM is enabled.</description>
39756 <description>Enable or disable timestamp bundling.</description>
39762 …description>Time stamps are disabled. Requests for timestamp generation are ignored, and stimulus …
39767 …<description>Time stamps are enabled. If stimulus writes select timestamping, a timestamp is outpu…
39774 <description>STMSYNCR is implemented so this value is Read As One.</description>
39780 <description>The STM Sync feature is disabled.</description>
39785 <description>The STM Sync feature is enabled.</description>
39792 <description>Compression Enable for Stimulus Ports.</description>
39798 …<description>Compression disabled, data transfers are transmitted at the size of the transaction.<…
39803 … <description>Compression enabled, data transfers are compressed to save bandwidth.</description>
39810 …<description>ATB Trace ID. Setting this value to all zeroes might result in Unpredictable tracing.…
39816 <description>STM is busy, for example the STM trace FIFO is not empty.</description>
39822 <description>STM is not busy.</description>
39827 <description>STM is busy.</description>
39836 <description>Used for implementation defined STM controls.</description>
39844 <description>FIFO Auto-flush.</description>
39850 <description>Auto-flush is disabled.</description>
39855 …<description>Auto-flush is enabled. The STM automatically drains all data it has even if the ATB i…
39862 <description>Is ASYNC priority higher than trace?</description>
39868 <description>ASYNC priority is always lower than trace.</description>
39873 … <description>ASYNC priority escalates on second synchronization request.</description>
39880 <description>Controls arbitration between AXI and HW during flush.</description>
39886 …<description>Priority inversion, when AXI flush is finished, HW gets priority until HW flush is do…
39891 … <description>Priority inversion disabled, AXI always has priority over HW.</description>
39898 … <description>Provides override control for architectural clock gate enable.</description>
39904 … <description>No override, clock gate is controlled by the state of STM.</description>
39909 <description>Override, clock is enabled.</description>
39916 <description>Provides override control for the AFREADY output</description>
39922 <description>No override, AFREADY is controlled by the state of STM.</description>
39927 <description>Override, AFREADY is driven HIGH.</description>
39936 <description>Indicates the features of the STM.</description>
39944 <description>Indicates the implemented STM protocol.</description>
39950 <description>STM implements the STPV2 protocol.</description>
39957 <description>Timestamp support.</description>
39963 <description>Absolute timestamps implemented.</description>
39970 <description>Timestamp frequency indication configuration.</description>
39976 <description>STMTSFREQR is read-only.</description>
39981 <description>STMTSFREQR is read-write.</description>
39988 <description>Timestamp force configuration.</description>
39994 <description>STMTSSTIMR bit 0 is read-only.</description>
39999 <description>STMTSSTIMR bit 0 is read-write.</description>
40006 <description>Trace bus support.</description>
40012 <description>Trigger control support.</description>
40018 <description>Timestamp prescale support</description>
40024 <description>Timestamp prescale is not implemented.</description>
40029 <description>Timestamp prescale is implemented.</description>
40036 <description>STMTCSR.HWTEN support</description>
40042 <description>STMTCSR.HWTEN is not implemented</description>
40049 <description>STMTCSR.SYNCEN support</description>
40055 <description>STMTCSR.SYNCEN implemented but always reads as b1</description>
40062 <description>STMTCSR.SWOEN support</description>
40068 <description>STMTCSR.SWOEN not implemented</description>
40077 <description>Indicates the features of the STM.</description>
40085 <description>STMSPTER support.</description>
40091 <description>STMSPTER is implemented.</description>
40098 <description>STMSPER presence.</description>
40104 <description>STMSPER is implemented.</description>
40109 <description>STMSPER is not implemented.</description>
40116 <description>Data compression on stimulus ports support.</description>
40122 …<description>Data compression support is programmable. STMTCSR.COMPEN is implemented.</description>
40129 <description>Timestamp force configuration.</description>
40135 <description>STMSPOVERRIDER and STMSPMOVERRIDER is not implemented.</description>
40140 <description>STMSPOVERRIDER and STMSPMOVERRIDER is implemented.</description>
40147 <description>STMPRIVMASKR support.</description>
40153 <description>STMPRIVMASKR is not implemented.</description>
40160 <description>Stimulus port transaction type support.</description>
40166 … <description>Both invariant timing and guaranteed transactions are supported.</description>
40173 <description>Fundamental data size.</description>
40179 <description>32-bit data.</description>
40186 <description>Stimulus port type support</description>
40192 <description>Only extended stimulus ports are implemented.</description>
40201 <description>Indicates the features of the STM.</description>
40209 <description>The number of stimulus ports masters implemented, minus 1.</description>
40215 <description>Example: 128 masters implemented.</description>
40224 <description>Integration Test for Cross-Trigger Outputs Register.</description>
40232 … <description>Sets the value of the TRIGOUTSPTE output in integration mode.</description>
40238 <description>Drive logic 0 on output.</description>
40243 <description>Drive logic 1 on output.</description>
40250 <description>Sets the value of the TRIGOUTSW output in integration mode.</description>
40256 <description>Drive logic 0 on output.</description>
40261 <description>Drive logic 1 on output.</description>
40268 … <description>Sets the value of the TRIGOUTHETE output in integration mode.</description>
40274 <description>Drive logic 0 on output.</description>
40279 <description>Drive logic 1 on output.</description>
40286 <description>Sets the value of the ASYNCOUT output in integration mode.</description>
40292 <description>Drive logic 0 on output.</description>
40297 <description>Drive logic 1 on output.</description>
40306 <description>Controls the value of the ATDATAM output in integration mode.</description>
40314 <description>Sets the value of the ATDATAM[0].</description>
40320 <description>Drive logic 0 on output.</description>
40325 <description>Drive logic 1 on output.</description>
40332 <description>Sets the value of the ATDATAM[7] output.</description>
40338 <description>Drive logic 0 on output.</description>
40343 <description>Drive logic 1 on output.</description>
40350 <description>Sets the value of the ATDATAM[15].</description>
40356 <description>Drive logic 0 on output.</description>
40361 <description>Drive logic 1 on output.</description>
40368 <description>Sets the value of the ATDATAM[23].</description>
40374 <description>Drive logic 0 on output.</description>
40379 <description>Drive logic 1 on output.</description>
40386 <description>Sets the value of the ATDATAM[31].</description>
40392 <description>Drive logic 0 on output.</description>
40397 <description>Drive logic 1 on output.</description>
40406 <description>Controls the value of the ATDATAM output in integration mode.</description>
40414 <description>Reads the value of the ATREADYM input.</description>
40420 <description>Pin is at logic 0.</description>
40425 <description>Pin is at logic 1.</description>
40432 <description>Reads the value of the AFVALIDM input.</description>
40438 <description>Pin is at logic 0.</description>
40443 <description>Pin is at logic 1.</description>
40452 <description>Controls the value of the ATIDM output in integration mode.</description>
40460 <description>Sets the value of pin 0 of the ATIDM output.</description>
40466 <description>Pin is at logic 0.</description>
40471 <description>Pin is at logic 1.</description>
40478 <description>Sets the value of pin 1 of the ATIDM output.</description>
40484 <description>Pin is at logic 0.</description>
40489 <description>Pin is at logic 1.</description>
40496 <description>Sets the value of pin 2 of the ATIDM output.</description>
40502 <description>Pin is at logic 0.</description>
40507 <description>Pin is at logic 1.</description>
40514 <description>Sets the value of pin 3 of the ATIDM output.</description>
40520 <description>Pin is at logic 0.</description>
40525 <description>Pin is at logic 1.</description>
40532 <description>Sets the value of pin 4 of the ATIDM output.</description>
40538 <description>Pin is at logic 0.</description>
40543 <description>Pin is at logic 1.</description>
40550 <description>Sets the value of pin 5 of the ATIDM output.</description>
40556 <description>Pin is at logic 0.</description>
40561 <description>Pin is at logic 1.</description>
40568 <description>Sets the value of pin 6 of the ATIDM output.</description>
40574 <description>Pin is at logic 0.</description>
40579 <description>Pin is at logic 1.</description>
40588 …<description>Controls the value of the ATVALIDM, AFREADYM, and ATBYTESM outputs in integration mod…
40596 <description>Sets the value of the ATVALIDM output.</description>
40602 <description>Pin is at logic 0.</description>
40607 <description>Pin is at logic 1.</description>
40614 <description>Sets the value of the AFREADYM_W output.</description>
40620 <description>Pin is at logic 0.</description>
40625 <description>Pin is at logic 1.</description>
40632 <description>Sets the value of pin 0 of the ATBYTESM output.</description>
40638 <description>Pin is at logic 0.</description>
40643 <description>Pin is at logic 1.</description>
40650 <description>Sets the value of pin 1 of the ATBYTESM output.</description>
40656 <description>Pin is at logic 0.</description>
40661 <description>Pin is at logic 1.</description>
40670 <description>Used to enable topology detection.
40672 …he component can be directly controlled for integration testing and topology solving.</description>
40680 …description>Enables the component to switch from functional mode to integration mode and back. If …
40686 <description>Integration mode is disabled.</description>
40691 <description>Integration mode is Enabled.</description>
40700 <description>This is used to enable write access to device registers.</description>
40708 …<description>A write of 0xC5ACCE55 enables further write access to this device. Any other write re…
40714 <description>Unlock register interface.</description>
40723 …<description>This indicates the status of the lock control mechanism. This lock prevents accidenta…
40727 … For most components this covers all registers except for the Lock Access Register.</description>
40735 … <description>Indicates that a lock control mechanism exists for this device.</description>
40741 …<description>No lock control mechanism exists, writes to the Lock Access Register are ignored.</de…
40746 <description>Lock control mechanism is present.</description>
40753 <description>Returns the current status of the Lock.</description>
40759 <description>Write access is allowed to this device.</description>
40764 …<description>Write access to the component is blocked. All writes to control registers are ignored…
40771 …<description>Indicates if the Lock Access Register is implemented as 8-bit or 32-bit.</description>
40777 … <description>This component implements a 32-bit Lock Access Register.</description>
40782 … <description>This component implements an 8-bit Lock Access Register.</description>
40791 <description>Indicates the current level of tracing permitted by the system</description>
40799 <description>Non-secure Invasive Debug</description>
40805 <description>The feature is not implemented.</description>
40810 <description>The feature is implemented.</description>
40817 <description>Non-secure Non-Invasive Debug</description>
40823 <description>The feature is not implemented.</description>
40828 <description>The feature is implemented.</description>
40835 <description>Secure Invasive Debug</description>
40841 <description>The feature is not implemented.</description>
40846 <description>The feature is implemented.</description>
40853 <description>Secure Non-Invasive Debug</description>
40859 <description>The feature is not implemented.</description>
40864 <description>The feature is implemented.</description>
40873 <description>Indicates the capabilities of the STM.</description>
40881 … <description>This value indicates the number of stimulus ports implemented.</description>
40887 <description>Maximum 65,536 stimulus ports can be implemented.</description>
40896 <description>Controls the single-shot comparator.</description>
40904 <description>The main type of the component</description>
40910 <description>Peripheral is a trace source.</description>
40917 <description>The sub-type of the component</description>
40923 <description>Peripheral is a stimulus trace source.</description>
40932 <description>Coresight peripheral identification registers.</description>
40940 <description>Coresight peripheral identification registers.</description>
40948 <description>Coresight peripheral identification registers.</description>
40956 <description>Coresight peripheral identification registers.</description>
40964 <description>Coresight peripheral identification registers.</description>
40972 <description>Coresight component identification registers.</description>
40980 <description>Coresight component identification registers.</description>
40988 <description>Coresight component identification registers.</description>
40996 <description>Coresight component identification registers.</description>
41006 <description>Trace Port Interface Unit</description>
41020 …<description>Each bit location is a single port size that is supported on the device.</description>
41028 <description>Indicates whether the TPIU supports port size of 1-bit.</description>
41034 <description>Port size 1 is not supported.</description>
41039 <description>Port size 1 is supported.</description>
41046 <description>Indicates whether the TPIU supports port size of 2-bit.</description>
41052 <description>Port size 2 is not supported.</description>
41057 <description>Port size 2 is supported.</description>
41064 <description>Indicates whether the TPIU supports port size of 3-bit.</description>
41070 <description>Port size 3 is not supported.</description>
41075 <description>Port size 3 is supported.</description>
41082 <description>Indicates whether the TPIU supports port size of 4-bit.</description>
41088 <description>Port size 4 is not supported.</description>
41093 <description>Port size 4 is supported.</description>
41100 <description>Indicates whether the TPIU supports port size of 5-bit.</description>
41106 <description>Port size 5 is not supported.</description>
41111 <description>Port size 5 is supported.</description>
41118 <description>Indicates whether the TPIU supports port size of 6-bit.</description>
41124 <description>Port size 6 is not supported.</description>
41129 <description>Port size 6 is supported.</description>
41136 <description>Indicates whether the TPIU supports port size of 7-bit.</description>
41142 <description>Port size 7 is not supported.</description>
41147 <description>Port size 7 is supported.</description>
41154 <description>Indicates whether the TPIU supports port size of 8-bit.</description>
41160 <description>Port size 8 is not supported.</description>
41165 <description>Port size 8 is supported.</description>
41172 <description>Indicates whether the TPIU supports port size of 9-bit.</description>
41178 <description>Port size 9 is not supported.</description>
41183 <description>Port size 9 is supported.</description>
41190 <description>Indicates whether the TPIU supports port size of 10-bit.</description>
41196 <description>Port size 10 is not supported.</description>
41201 <description>Port size 10 is supported.</description>
41208 <description>Indicates whether the TPIU supports port size of 11-bit.</description>
41214 <description>Port size 11 is not supported.</description>
41219 <description>Port size 11 is supported.</description>
41226 <description>Indicates whether the TPIU supports port size of 12-bit.</description>
41232 <description>Port size 12 is not supported.</description>
41237 <description>Port size 12 is supported.</description>
41244 <description>Indicates whether the TPIU supports port size of 13-bit.</description>
41250 <description>Port size 13 is not supported.</description>
41255 <description>Port size 13 is supported.</description>
41262 <description>Indicates whether the TPIU supports port size of 14-bit.</description>
41268 <description>Port size 14 is not supported.</description>
41273 <description>Port size 14 is supported.</description>
41280 <description>Indicates whether the TPIU supports port size of 15-bit.</description>
41286 <description>Port size 15 is not supported.</description>
41291 <description>Port size 15 is supported.</description>
41298 <description>Indicates whether the TPIU supports port size of 16-bit.</description>
41304 <description>Port size 16 is not supported.</description>
41309 <description>Port size 16 is supported.</description>
41316 <description>Indicates whether the TPIU supports port size of 17-bit.</description>
41322 <description>Port size 17 is not supported.</description>
41327 <description>Port size 17 is supported.</description>
41334 <description>Indicates whether the TPIU supports port size of 18-bit.</description>
41340 <description>Port size 18 is not supported.</description>
41345 <description>Port size 18 is supported.</description>
41352 <description>Indicates whether the TPIU supports port size of 19-bit.</description>
41358 <description>Port size 19 is not supported.</description>
41363 <description>Port size 19 is supported.</description>
41370 <description>Indicates whether the TPIU supports port size of 20-bit.</description>
41376 <description>Port size 20 is not supported.</description>
41381 <description>Port size 20 is supported.</description>
41388 <description>Indicates whether the TPIU supports port size of 21-bit.</description>
41394 <description>Port size 21 is not supported.</description>
41399 <description>Port size 21 is supported.</description>
41406 <description>Indicates whether the TPIU supports port size of 22-bit.</description>
41412 <description>Port size 22 is not supported.</description>
41417 <description>Port size 22 is supported.</description>
41424 <description>Indicates whether the TPIU supports port size of 23-bit.</description>
41430 <description>Port size 23 is not supported.</description>
41435 <description>Port size 23 is supported.</description>
41442 <description>Indicates whether the TPIU supports port size of 24-bit.</description>
41448 <description>Port size 24 is not supported.</description>
41453 <description>Port size 24 is supported.</description>
41460 <description>Indicates whether the TPIU supports port size of 25-bit.</description>
41466 <description>Port size 25 is not supported.</description>
41471 <description>Port size 25 is supported.</description>
41478 <description>Indicates whether the TPIU supports port size of 26-bit.</description>
41484 <description>Port size 26 is not supported.</description>
41489 <description>Port size 26 is supported.</description>
41496 <description>Indicates whether the TPIU supports port size of 27-bit.</description>
41502 <description>Port size 27 is not supported.</description>
41507 <description>Port size 27 is supported.</description>
41514 <description>Indicates whether the TPIU supports port size of 28-bit.</description>
41520 <description>Port size 28 is not supported.</description>
41525 <description>Port size 28 is supported.</description>
41532 <description>Indicates whether the TPIU supports port size of 29-bit.</description>
41538 <description>Port size 29 is not supported.</description>
41543 <description>Port size 29 is supported.</description>
41550 <description>Indicates whether the TPIU supports port size of 30-bit.</description>
41556 <description>Port size 30 is not supported.</description>
41561 <description>Port size 30 is supported.</description>
41568 <description>Indicates whether the TPIU supports port size of 31-bit.</description>
41574 <description>Port size 31 is not supported.</description>
41579 <description>Port size 31 is supported.</description>
41586 <description>Indicates whether the TPIU supports port size of 32-bit.</description>
41592 <description>Port size 32 is not supported.</description>
41597 <description>Port size 32 is supported.</description>
41606 …<description>Each bit location is a single port size. One bit can be set, and indicates the curren…
41614 <description>Indicates which port size is currently selected.</description>
41620 <description>Port size 1 is not selected.</description>
41625 <description>Port size 1 is selected.</description>
41632 <description>Indicates which port size is currently selected.</description>
41638 <description>Port size 2 is not selected.</description>
41643 <description>Port size 2 is selected.</description>
41650 <description>Indicates which port size is currently selected.</description>
41656 <description>Port size 3 is not selected.</description>
41661 <description>Port size 3 is selected.</description>
41668 <description>Indicates which port size is currently selected.</description>
41674 <description>Port size 4 is not selected.</description>
41679 <description>Port size 4 is selected.</description>
41686 <description>Indicates which port size is currently selected.</description>
41692 <description>Port size 5 is not selected.</description>
41697 <description>Port size 5 is selected.</description>
41704 <description>Indicates which port size is currently selected.</description>
41710 <description>Port size 6 is not selected.</description>
41715 <description>Port size 6 is selected.</description>
41722 <description>Indicates which port size is currently selected.</description>
41728 <description>Port size 7 is not selected.</description>
41733 <description>Port size 7 is selected.</description>
41740 <description>Indicates which port size is currently selected.</description>
41746 <description>Port size 8 is not selected.</description>
41751 <description>Port size 8 is selected.</description>
41758 <description>Indicates which port size is currently selected.</description>
41764 <description>Port size 9 is not selected.</description>
41769 <description>Port size 9 is selected.</description>
41776 <description>Indicates which port size is currently selected.</description>
41782 <description>Port size 10 is not selected.</description>
41787 <description>Port size 10 is selected.</description>
41794 <description>Indicates which port size is currently selected.</description>
41800 <description>Port size 11 is not selected.</description>
41805 <description>Port size 11 is selected.</description>
41812 <description>Indicates which port size is currently selected.</description>
41818 <description>Port size 12 is not selected.</description>
41823 <description>Port size 12 is selected.</description>
41830 <description>Indicates which port size is currently selected.</description>
41836 <description>Port size 13 is not selected.</description>
41841 <description>Port size 13 is selected.</description>
41848 <description>Indicates which port size is currently selected.</description>
41854 <description>Port size 14 is not selected.</description>
41859 <description>Port size 14 is selected.</description>
41866 <description>Indicates which port size is currently selected.</description>
41872 <description>Port size 15 is not selected.</description>
41877 <description>Port size 15 is selected.</description>
41884 <description>Indicates which port size is currently selected.</description>
41890 <description>Port size 16 is not selected.</description>
41895 <description>Port size 16 is selected.</description>
41902 <description>Indicates which port size is currently selected.</description>
41908 <description>Port size 17 is not selected.</description>
41913 <description>Port size 17 is selected.</description>
41920 <description>Indicates which port size is currently selected.</description>
41926 <description>Port size 18 is not selected.</description>
41931 <description>Port size 18 is selected.</description>
41938 <description>Indicates which port size is currently selected.</description>
41944 <description>Port size 19 is not selected.</description>
41949 <description>Port size 19 is selected.</description>
41956 <description>Indicates which port size is currently selected.</description>
41962 <description>Port size 20 is not selected.</description>
41967 <description>Port size 20 is selected.</description>
41974 <description>Indicates which port size is currently selected.</description>
41980 <description>Port size 21 is not selected.</description>
41985 <description>Port size 21 is selected.</description>
41992 <description>Indicates which port size is currently selected.</description>
41998 <description>Port size 22 is not selected.</description>
42003 <description>Port size 22 is selected.</description>
42010 <description>Indicates which port size is currently selected.</description>
42016 <description>Port size 23 is not selected.</description>
42021 <description>Port size 23 is selected.</description>
42028 <description>Indicates which port size is currently selected.</description>
42034 <description>Port size 24 is not selected.</description>
42039 <description>Port size 24 is selected.</description>
42046 <description>Indicates which port size is currently selected.</description>
42052 <description>Port size 25 is not selected.</description>
42057 <description>Port size 25 is selected.</description>
42064 <description>Indicates which port size is currently selected.</description>
42070 <description>Port size 26 is not selected.</description>
42075 <description>Port size 26 is selected.</description>
42082 <description>Indicates which port size is currently selected.</description>
42088 <description>Port size 27 is not selected.</description>
42093 <description>Port size 27 is selected.</description>
42100 <description>Indicates which port size is currently selected.</description>
42106 <description>Port size 28 is not selected.</description>
42111 <description>Port size 28 is selected.</description>
42118 <description>Indicates which port size is currently selected.</description>
42124 <description>Port size 29 is not selected.</description>
42129 <description>Port size 29 is selected.</description>
42136 <description>Indicates which port size is currently selected.</description>
42142 <description>Port size 30 is not selected.</description>
42147 <description>Port size 30 is selected.</description>
42154 <description>Indicates which port size is currently selected.</description>
42160 <description>Port size 31 is not selected.</description>
42165 <description>Port size 31 is selected.</description>
42172 <description>Indicates which port size is currently selected.</description>
42178 <description>Port size 32 is not selected.</description>
42183 <description>Port size 32 is selected.</description>
42192 …description>The Supported_trigger_modes register indicates the implemented trigger counter multipl…
42200 …<description>Indicates whether multiplying the trigger counter by 2^(0+1) is supported.</descripti…
42206 … <description>Multiplying the trigger counter by 2^(0+1) is supported.</description>
42211 … <description>Multiplying the trigger counter by 2^(0+1) is supported.</description>
42218 …<description>Indicates whether multiplying the trigger counter by 2^(1+1) is supported.</descripti…
42224 … <description>Multiplying the trigger counter by 2^(1+1) is supported.</description>
42229 … <description>Multiplying the trigger counter by 2^(1+1) is supported.</description>
42236 …<description>Indicates whether multiplying the trigger counter by 2^(2+1) is supported.</descripti…
42242 … <description>Multiplying the trigger counter by 2^(2+1) is supported.</description>
42247 … <description>Multiplying the trigger counter by 2^(2+1) is supported.</description>
42254 …<description>Indicates whether multiplying the trigger counter by 2^(3+1) is supported.</descripti…
42260 … <description>Multiplying the trigger counter by 2^(3+1) is supported.</description>
42265 … <description>Multiplying the trigger counter by 2^(3+1) is supported.</description>
42272 …<description>Indicates whether multiplying the trigger counter by 2^(4+1) is supported.</descripti…
42278 … <description>Multiplying the trigger counter by 2^(4+1) is supported.</description>
42283 … <description>Multiplying the trigger counter by 2^(4+1) is supported.</description>
42290 … <description>Indicates whether an 8-bit wide counter register is implemented.</description>
42296 <description>An 8-bit wide counter register is implemented.</description>
42301 <description>An 8-bit wide counter register is implemented.</description>
42308 <description>A trigger has occurred and the counter has reached 0.</description>
42314 <description>Trigger has not occurred.</description>
42319 <description>Trigger has occurred.</description>
42326 <description>A trigger has occurred but the counter is not at 0.</description>
42332 … <description>Either a trigger has not occurred or the counter is at 0.</description>
42337 <description>A trigger has occurred but the counter is not at 0.</description>
42346 …description>The Trigger_counter_value register enables delaying the indication of triggers to any …
42354 …<description>8-bit counter value for the number of words to be output from the formatter before a …
42362 …<description>The Trigger_multiplier register contains the selectors for the trigger counter multip…
42370 <description>Multiply the Trigger Counter by 2^n.</description>
42376 <description>Multiplier disabled.</description>
42381 <description>Multiplier enabled.</description>
42388 <description>Multiply the Trigger Counter by 2^n.</description>
42394 <description>Multiplier disabled.</description>
42399 <description>Multiplier enabled.</description>
42406 <description>Multiply the Trigger Counter by 2^n.</description>
42412 <description>Multiplier disabled.</description>
42417 <description>Multiplier enabled.</description>
42424 <description>Multiply the Trigger Counter by 2^n.</description>
42430 <description>Multiplier disabled.</description>
42435 <description>Multiplier enabled.</description>
42442 <description>Multiply the Trigger Counter by 2^n.</description>
42448 <description>Multiplier disabled.</description>
42453 <description>Multiplier enabled.</description>
42462 …description>The Supported_test_pattern_modes register provides a set of known bit sequences or pat…
42470 …<description>Indicates whether the walking 1s pattern is supported as output over the trace port.<…
42476 <description>Test pattern is not supported.</description>
42481 <description>Test pattern is supported.</description>
42488 …<description>Indicates whether the walking 0s pattern is supported as output over the trace port.<…
42494 <description>Test pattern is not supported.</description>
42499 <description>Test pattern is supported.</description>
42506 …<description>Indicates whether the AA/55 pattern is supported as output over the trace port.</desc…
42512 <description>Test pattern is not supported.</description>
42517 <description>Test pattern is supported.</description>
42524 …<description>Indicates whether the FF/00 pattern is supported as output over the trace port.</desc…
42530 <description>Test pattern is not supported.</description>
42535 <description>Test pattern is supported.</description>
42542 <description>Indicates whether timed mode is supported.</description>
42548 <description>Mode is not supported.</description>
42553 <description>Mode is supported.</description>
42560 <description>Indicates whether continuous mode is supported.</description>
42566 <description>Mode is not supported.</description>
42571 <description>Mode is supported.</description>
42580 …<description>Current_test_pattern_mode indicates the current test pattern or mode selected.</descr…
42588 …<description>Indicates whether the walking 1s pattern is supported as output over the trace port.<…
42594 <description>Test pattern is disabled.</description>
42599 <description>Test pattern is enabled.</description>
42606 …<description>Indicates whether the walking 0s pattern is supported as output over the trace port.<…
42612 <description>Test pattern is disabled.</description>
42617 <description>Test pattern is enabled.</description>
42624 …<description>Indicates whether the AA/55 pattern is supported as output over the trace port.</desc…
42630 <description>Test pattern is disabled.</description>
42635 <description>Test pattern is enabled.</description>
42642 …<description>Indicates whether the FF/00 pattern is supported as output over the trace port.</desc…
42648 <description>Test pattern is disabled.</description>
42653 <description>Test pattern is enabled.</description>
42660 <description>Indicates whether timed mode is supported.</description>
42666 <description>Mode is disabled.</description>
42671 <description>Mode is enabled.</description>
42678 <description>Indicates whether continuous mode is supported.</description>
42684 <description>Mode is disabled.</description>
42689 <description>Mode is enabled.</description>
42698 …description>The TPRCR register is an 8-bit counter start value that is decremented. A write sets t…
42706 …description>8-bit counter value to indicate the number of traceclkin cycles for which a pattern ru…
42714 …<description>The FFSR register indicates the current status of the formatter and flush features av…
42722 <description>Flush in progress.</description>
42728 <description>A flush is not in progress.</description>
42733 <description>A flush is in progress.</description>
42740 …description>The formatter has received a stop request signal and all trace data and post-amble is …
42746 <description>Formatter has not stopped.</description>
42751 <description>Formatter has stopped.</description>
42758 <description>Indicates whether the TRACECTL pin is available for use.</description>
42764 <description>TRACECTL pin is not present.</description>
42769 <description>TRACECTL pin is present.</description>
42778 …<description>The FFCR register controls the generation of stop, trigger, and flush events.</descri…
42786 …<description>Do not embed triggers into the formatted stream. Trace disable cycles and triggers ar…
42792 <description>The formatting feature is disabled.</description>
42797 <description>The formatting feature is enabled.</description>
42804 …<description>Is embedded in trigger packets and indicates that no cycle is using sync packets.</de…
42810 <description>The formatting feature is disabled.</description>
42815 <description>The formatting feature is enabled.</description>
42822 <description>Enables the use of the flushin connection.</description>
42828 <description>The formatting feature is disabled.</description>
42833 <description>The formatting feature is enabled.</description>
42840 …<description>Initiates a manual flush of data in the system when a trigger event occurs.</descript…
42846 <description>The formatting feature is disabled.</description>
42851 <description>The formatting feature is enabled.</description>
42858 … <description>Generates a flush. This bit is set to 0 when this flush is serviced.</description>
42864 <description>The formatting feature is disabled.</description>
42869 <description>The formatting feature is enabled.</description>
42876 … <description>Generates a flush. This bit is set to 1 when this flush is serviced.</description>
42882 <description>The formatting feature is disabled.</description>
42887 <description>The formatting feature is enabled.</description>
42894 <description>Indicates a trigger when trigin is asserted.</description>
42900 <description>The formatting feature is disabled.</description>
42905 <description>The formatting feature is enabled.</description>
42912 <description>Indicates a trigger on a trigger event.</description>
42918 <description>The formatting feature is disabled.</description>
42923 <description>The formatting feature is enabled.</description>
42930 … <description>Indicates a trigger when flush completion on afreadys is returned.</description>
42936 <description>The formatting feature is disabled.</description>
42941 <description>The formatting feature is enabled.</description>
42948 <description>Forces the FIFO to drain off any part-completed packets.</description>
42954 <description>The formatting feature is disabled.</description>
42959 <description>The formatting feature is enabled.</description>
42966 …<description>Stops the formatter after a trigger event is observed. Reset to disabled or 0.</descr…
42972 <description>The formatting feature is disabled.</description>
42977 <description>The formatting feature is enabled.</description>
42986 …description>The FSCR register enables the frequency of synchronization information to be optimized…
42994 …<description>12-bit counter reload value. Indicates the number of complete frames between full syn…
43002 …description>Two ports can be used as a control and feedback mechanism for any serializers, pin sha…
43010 <description>EXTCTL inputs.</description>
43016 <description>Input EXTCTL0 is low.</description>
43021 <description>Input EXTCTL0 is high.</description>
43028 <description>EXTCTL inputs.</description>
43034 <description>Input EXTCTL1 is low.</description>
43039 <description>Input EXTCTL1 is high.</description>
43046 <description>EXTCTL inputs.</description>
43052 <description>Input EXTCTL2 is low.</description>
43057 <description>Input EXTCTL2 is high.</description>
43064 <description>EXTCTL inputs.</description>
43070 <description>Input EXTCTL3 is low.</description>
43075 <description>Input EXTCTL3 is high.</description>
43082 <description>EXTCTL inputs.</description>
43088 <description>Input EXTCTL4 is low.</description>
43093 <description>Input EXTCTL4 is high.</description>
43100 <description>EXTCTL inputs.</description>
43106 <description>Input EXTCTL5 is low.</description>
43111 <description>Input EXTCTL5 is high.</description>
43118 <description>EXTCTL inputs.</description>
43124 <description>Input EXTCTL6 is low.</description>
43129 <description>Input EXTCTL6 is high.</description>
43136 <description>EXTCTL inputs.</description>
43142 <description>Input EXTCTL7 is low.</description>
43147 <description>Input EXTCTL7 is high.</description>
43156 …description>Two ports can be used as a control and feedback mechanism for any serializers, pin sha…
43164 <description>EXTCTL outputs.</description>
43170 <description>Output EXTCTL0 is low.</description>
43175 <description>Output EXTCTL0 is high.</description>
43182 <description>EXTCTL outputs.</description>
43188 <description>Output EXTCTL1 is low.</description>
43193 <description>Output EXTCTL1 is high.</description>
43200 <description>EXTCTL outputs.</description>
43206 <description>Output EXTCTL2 is low.</description>
43211 <description>Output EXTCTL2 is high.</description>
43218 <description>EXTCTL outputs.</description>
43224 <description>Output EXTCTL3 is low.</description>
43229 <description>Output EXTCTL3 is high.</description>
43236 <description>EXTCTL outputs.</description>
43242 <description>Output EXTCTL4 is low.</description>
43247 <description>Output EXTCTL4 is high.</description>
43254 <description>EXTCTL outputs.</description>
43260 <description>Output EXTCTL5 is low.</description>
43265 <description>Output EXTCTL5 is high.</description>
43272 <description>EXTCTL outputs.</description>
43278 <description>Output EXTCTL6 is low.</description>
43283 <description>Output EXTCTL6 is high.</description>
43290 <description>EXTCTL outputs.</description>
43296 <description>Output EXTCTL7 is low.</description>
43301 <description>Output EXTCTL7 is high.</description>
43310 …<description>The ITTRFLINACK register enables control of the triginack and flushinack outputs from…
43318 <description>Sets the value of triginack.</description>
43324 <description>Pin is logic 0.</description>
43329 <description>Pin is logic 1.</description>
43336 <description>Sets the value of flushinack.</description>
43342 <description>Pin is logic 0.</description>
43347 <description>Pin is logic 1.</description>
43356 …<description>The ITTRFLIN register contains the values of the flushin and trigin inputs to the TPI…
43364 <description>Reads the value of trigin.</description>
43370 <description>Pin is logic 0.</description>
43375 <description>Pin is logic 1.</description>
43382 <description>Reads the value of flushin.</description>
43388 <description>Pin is logic 0.</description>
43393 <description>Pin is logic 1.</description>
43402 …<description>The ITATBDATA0 register contains the value of the atdatas inputs to the TPIU. The val…
43410 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
43416 <description>Pin is logic 0.</description>
43421 <description>Pin is logic 1.</description>
43428 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
43434 <description>Pin is logic 0.</description>
43439 <description>Pin is logic 1.</description>
43446 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
43452 <description>Pin is logic 0.</description>
43457 <description>Pin is logic 1.</description>
43464 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
43470 <description>Pin is logic 0.</description>
43475 <description>Pin is logic 1.</description>
43482 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
43488 <description>Pin is logic 0.</description>
43493 <description>Pin is logic 1.</description>
43502 … <description>Enables control of the atreadys and afvalids outputs of the TPIU.</description>
43510 <description>Sets the value of afvalid.</description>
43516 <description>Pin is logic 0.</description>
43521 <description>Pin is logic 1.</description>
43528 <description>Sets the value of atready.</description>
43534 <description>Pin is logic 0.</description>
43539 <description>Pin is logic 1.</description>
43548 …<description>The ITATBCTR1 register contains the value of the atids input to the TPIU. This is onl…
43556 <description>Reads the value of atids.</description>
43562 <description>Pin is logic 0.</description>
43567 <description>Pin is logic 1.</description>
43576 …<description>The ITATBCTR0 register captures the values of the atvalids, afreadys, and atbytess in…
43577 …ctly in a system, the value of atbytess is only valid when atvalids, bit[0], is HIGH.</description>
43585 <description>Reads the value of atvalids.</description>
43591 <description>Pin is logic 0.</description>
43596 <description>Pin is logic 1.</description>
43603 <description>Reads the value of afreadys.</description>
43609 <description>Pin is logic 0.</description>
43614 <description>Pin is logic 1.</description>
43621 <description>Reads the value of atbytess.</description>
43627 <description>Pin is logic 0.</description>
43632 <description>Pin is logic 1.</description>
43641 <description>Used to enable topology detection.
43643 …he component can be directly controlled for integration testing and topology solving.</description>
43651 …description>Enables the component to switch from functional mode to integration mode and back. If …
43657 <description>Integration mode is disabled.</description>
43662 <description>Integration mode is Enabled.</description>
43671 …<description>Software can use the claim tag to coordinate application and debugger access to trace…
43672 …ster sets bits in the claim tag, and determines the number of claim bits implemented.</description>
43680 <description>Set claim bit 0 and check if bit is implemented or not.</description>
43687 <description>Claim bit 0 is not implemented.</description>
43692 <description>Claim bit 0 is implemented.</description>
43700 <description>Set claim bit 0.</description>
43707 <description>Set claim bit 1 and check if bit is implemented or not.</description>
43714 <description>Claim bit 1 is not implemented.</description>
43719 <description>Claim bit 1 is implemented.</description>
43727 <description>Set claim bit 1.</description>
43734 <description>Set claim bit 2 and check if bit is implemented or not.</description>
43741 <description>Claim bit 2 is not implemented.</description>
43746 <description>Claim bit 2 is implemented.</description>
43754 <description>Set claim bit 2.</description>
43761 <description>Set claim bit 3 and check if bit is implemented or not.</description>
43768 <description>Claim bit 3 is not implemented.</description>
43773 <description>Claim bit 3 is implemented.</description>
43781 <description>Set claim bit 3.</description>
43790 …<description>Software can use the claim tag to coordinate application and debugger access to trace…
43792 …ets the bits in the claim tag to 0 and determines the current value of the claim tag.</description>
43800 <description>Read or clear claim bit 0.</description>
43807 <description>Claim bit 0 is not set.</description>
43812 <description>Claim bit 0 is set.</description>
43820 <description>Clear claim bit 0.</description>
43827 <description>Read or clear claim bit 1.</description>
43834 <description>Claim bit 1 is not set.</description>
43839 <description>Claim bit 1 is set.</description>
43847 <description>Clear claim bit 1.</description>
43854 <description>Read or clear claim bit 2.</description>
43861 <description>Claim bit 2 is not set.</description>
43866 <description>Claim bit 2 is set.</description>
43874 <description>Clear claim bit 2.</description>
43881 <description>Read or clear claim bit 3.</description>
43888 <description>Claim bit 3 is not set.</description>
43893 <description>Claim bit 3 is set.</description>
43901 <description>Clear claim bit 3.</description>
43910 <description>This is used to enable write access to device registers.</description>
43918 …<description>A write of 0xC5ACCE55 enables further write access to this device. Any other write re…
43924 <description>Unlock register interface.</description>
43933 …<description>This indicates the status of the lock control mechanism. This lock prevents accidenta…
43937 … For most components this covers all registers except for the Lock Access Register.</description>
43945 … <description>Indicates that a lock control mechanism exists for this device.</description>
43951 …<description>No lock control mechanism exists, writes to the Lock Access Register are ignored.</de…
43956 <description>Lock control mechanism is present.</description>
43963 <description>Returns the current status of the Lock.</description>
43969 <description>Write access is allowed to this device.</description>
43974 …<description>Write access to the component is blocked. All writes to control registers are ignored…
43981 …<description>Indicates if the Lock Access Register is implemented as 8-bit or 32-bit.</description>
43987 … <description>This component implements a 32-bit Lock Access Register.</description>
43992 … <description>This component implements an 8-bit Lock Access Register.</description>
44001 <description>Indicates the current level of tracing permitted by the system</description>
44009 <description>Non-secure Invasive Debug</description>
44015 <description>The feature is not implemented.</description>
44020 <description>The feature is implemented.</description>
44027 <description>Non-secure Non-Invasive Debug</description>
44033 <description>The feature is not implemented.</description>
44038 <description>The feature is implemented.</description>
44045 <description>Secure Invasive Debug</description>
44051 <description>The feature is not implemented.</description>
44056 <description>The feature is implemented.</description>
44063 <description>Secure Non-Invasive Debug</description>
44069 <description>The feature is not implemented.</description>
44074 <description>The feature is implemented.</description>
44083 <description>Indicates the capabilities of the component.</description>
44091 …<description>Indicates the hidden level of input multiplexing. When non-zero, this value indicates…
44092 …rted, that is, no multiplexing is present. This value helps detect the ATB structure.</description>
44098 <description>Indicates the relationship between atclk and traceclkin.</description>
44104 <description>atclk and traceclkin are synchronous.</description>
44109 <description>atclk and traceclkin are asynchronous.</description>
44116 <description>FIFO size in powers of 2.</description>
44122 <description>FIFO size of 4 entries, that is, 16 bytes.</description>
44129 <description>Indicates whether trace clock plus data is supported.</description>
44135 <description>Trace clock and data is supported.</description>
44140 <description>Trace clock and data is not supported.</description>
44147 …<description>Indicates whether Serial Wire Output, Manchester encoded format, is supported.</descr…
44153 … <description>Serial Wire Output, Manchester encoded format, is not supported.</description>
44158 … <description>Serial Wire Output, Manchester encoded format, is supported.</description>
44165 … <description>Indicates whether Serial Wire Output, UART or NRZ, is supported.</description>
44171 <description>Serial Wire Output, UART or NRZ, is not supported.</description>
44176 <description>Serial Wire Output, UART or NRZ, is supported.</description>
44185 …description>The DEVTYPE register provides a debugger with information about the component when the…
44193 <description>The main type of the component</description>
44199 <description>Peripheral is a trace sink.</description>
44206 <description>The sub-type of the component</description>
44212 … <description>Indicates that this component is a trace port component.</description>
44221 <description>Coresight peripheral identification registers.</description>
44229 <description>Coresight peripheral identification registers.</description>
44237 <description>Coresight peripheral identification registers.</description>
44245 <description>Coresight peripheral identification registers.</description>
44253 <description>Coresight peripheral identification registers.</description>
44261 <description>Coresight component identification registers.</description>
44269 <description>Coresight component identification registers.</description>
44277 <description>Coresight component identification registers.</description>
44285 <description>Coresight component identification registers.</description>
44295 <description>Cross-Trigger Interface control 0</description>
44310 <description>CTI Control register</description>
44318 <description>Enables or disables the CTI.</description>
44324 … <description>All cross-triggering mapping logic functionality is disabled.</description>
44329 … <description>Cross-triggering mapping logic functionality is enabled.</description>
44338 <description>CTI Interrupt Acknowledge register</description>
44346 <description>Acknowledges the ctitrigout 0 output.</description>
44353 <description>Clears the ctitrigout.</description>
44360 <description>Acknowledges the ctitrigout 1 output.</description>
44367 <description>Clears the ctitrigout.</description>
44374 <description>Acknowledges the ctitrigout 2 output.</description>
44381 <description>Clears the ctitrigout.</description>
44388 <description>Acknowledges the ctitrigout 3 output.</description>
44395 <description>Clears the ctitrigout.</description>
44402 <description>Acknowledges the ctitrigout 4 output.</description>
44409 <description>Clears the ctitrigout.</description>
44416 <description>Acknowledges the ctitrigout 5 output.</description>
44423 <description>Clears the ctitrigout.</description>
44430 <description>Acknowledges the ctitrigout 6 output.</description>
44437 <description>Clears the ctitrigout.</description>
44444 <description>Acknowledges the ctitrigout 7 output.</description>
44451 <description>Clears the ctitrigout.</description>
44460 <description>CTI Application Trigger Set register</description>
44468 <description>Application trigger event for channel 0.</description>
44475 <description>Application trigger 0 is inactive.</description>
44480 <description>Application trigger 0 is active.</description>
44488 <description>Generate channel event for channel 0.</description>
44495 <description>Application trigger event for channel 1.</description>
44502 <description>Application trigger 1 is inactive.</description>
44507 <description>Application trigger 1 is active.</description>
44515 <description>Generate channel event for channel 1.</description>
44522 <description>Application trigger event for channel 2.</description>
44529 <description>Application trigger 2 is inactive.</description>
44534 <description>Application trigger 2 is active.</description>
44542 <description>Generate channel event for channel 2.</description>
44549 <description>Application trigger event for channel 3.</description>
44556 <description>Application trigger 3 is inactive.</description>
44561 <description>Application trigger 3 is active.</description>
44569 <description>Generate channel event for channel 3.</description>
44578 <description>CTI Application Trigger Clear register</description>
44586 …<description>Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register f…
44593 <description>Clears the event for channel 0.</description>
44600 …<description>Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register f…
44607 <description>Clears the event for channel 1.</description>
44614 …<description>Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register f…
44621 <description>Clears the event for channel 2.</description>
44628 …<description>Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register f…
44635 <description>Clears the event for channel 3.</description>
44644 <description>CTI Application Pulse register</description>
44652 …description>Setting a bit HIGH generates a channel event pulse for the selected channel. There is …
44659 <description>Generates an event pulse on channel 0.</description>
44666 …description>Setting a bit HIGH generates a channel event pulse for the selected channel. There is …
44673 <description>Generates an event pulse on channel 1.</description>
44680 …description>Setting a bit HIGH generates a channel event pulse for the selected channel. There is …
44687 <description>Generates an event pulse on channel 2.</description>
44694 …description>Setting a bit HIGH generates a channel event pulse for the selected channel. There is …
44701 <description>Generates an event pulse on channel 3.</description>
44712 <description>Description collection: CTI Trigger to Channel Enable register</description>
44720 …<description>Enables a cross trigger event to channel 0 when a ctitrigin input is activated.</desc…
44726 <description>Input trigger n events are ignored by channel 0.</description>
44731 …<description>When an event is received on input trigger n (ctitrigin[n]), generate an event on cha…
44738 …<description>Enables a cross trigger event to channel 1 when a ctitrigin input is activated.</desc…
44744 <description>Input trigger n events are ignored by channel 1.</description>
44749 …<description>When an event is received on input trigger n (ctitrigin[n]), generate an event on cha…
44756 …<description>Enables a cross trigger event to channel 2 when a ctitrigin input is activated.</desc…
44762 <description>Input trigger n events are ignored by channel 2.</description>
44767 …<description>When an event is received on input trigger n (ctitrigin[n]), generate an event on cha…
44774 …<description>Enables a cross trigger event to channel 3 when a ctitrigin input is activated.</desc…
44780 <description>Input trigger n events are ignored by channel 3.</description>
44785 …<description>When an event is received on input trigger n (ctitrigin[n]), generate an event on cha…
44796 <description>Description collection: CTI Channel to Trigger Enable register</description>
44804 …<description>Enables a cross trigger event to ctitrigout when channel 0 is activated.</description>
44810 <description>Channel 0 is ignored by output trigger n.</description>
44815 …<description>When an event occurs on channel 0, generate an event on output event n (ctitrigout[n]…
44822 …<description>Enables a cross trigger event to ctitrigout when channel 1 is activated.</description>
44828 <description>Channel 1 is ignored by output trigger n.</description>
44833 …<description>When an event occurs on channel 1, generate an event on output event n (ctitrigout[n]…
44840 …<description>Enables a cross trigger event to ctitrigout when channel 2 is activated.</description>
44846 <description>Channel 2 is ignored by output trigger n.</description>
44851 …<description>When an event occurs on channel 2, generate an event on output event n (ctitrigout[n]…
44858 …<description>Enables a cross trigger event to ctitrigout when channel 3 is activated.</description>
44864 <description>Channel 3 is ignored by output trigger n.</description>
44869 …<description>When an event occurs on channel 3, generate an event on output event n (ctitrigout[n]…
44878 <description>CTI Trigger In Status register</description>
44886 <description>Shows the status of ctitrigin0 input.</description>
44892 <description>Ctitrigin 0 is active.</description>
44897 <description>Ctitrigin 0 is inactive.</description>
44904 <description>Shows the status of ctitrigin1 input.</description>
44910 <description>Ctitrigin 1 is active.</description>
44915 <description>Ctitrigin 1 is inactive.</description>
44922 <description>Shows the status of ctitrigin2 input.</description>
44928 <description>Ctitrigin 2 is active.</description>
44933 <description>Ctitrigin 2 is inactive.</description>
44940 <description>Shows the status of ctitrigin3 input.</description>
44946 <description>Ctitrigin 3 is active.</description>
44951 <description>Ctitrigin 3 is inactive.</description>
44958 <description>Shows the status of ctitrigin4 input.</description>
44964 <description>Ctitrigin 4 is active.</description>
44969 <description>Ctitrigin 4 is inactive.</description>
44976 <description>Shows the status of ctitrigin5 input.</description>
44982 <description>Ctitrigin 5 is active.</description>
44987 <description>Ctitrigin 5 is inactive.</description>
44994 <description>Shows the status of ctitrigin6 input.</description>
45000 <description>Ctitrigin 6 is active.</description>
45005 <description>Ctitrigin 6 is inactive.</description>
45012 <description>Shows the status of ctitrigin7 input.</description>
45018 <description>Ctitrigin 7 is active.</description>
45023 <description>Ctitrigin 7 is inactive.</description>
45032 <description>CTI Trigger Out Status register</description>
45040 <description>Shows the status of ctitrigout0 output.</description>
45046 <description>Ctitrigout 0 is active.</description>
45051 <description>Ctitrigout 0 is inactive.</description>
45058 <description>Shows the status of ctitrigout1 output.</description>
45064 <description>Ctitrigout 1 is active.</description>
45069 <description>Ctitrigout 1 is inactive.</description>
45076 <description>Shows the status of ctitrigout2 output.</description>
45082 <description>Ctitrigout 2 is active.</description>
45087 <description>Ctitrigout 2 is inactive.</description>
45094 <description>Shows the status of ctitrigout3 output.</description>
45100 <description>Ctitrigout 3 is active.</description>
45105 <description>Ctitrigout 3 is inactive.</description>
45112 <description>Shows the status of ctitrigout4 output.</description>
45118 <description>Ctitrigout 4 is active.</description>
45123 <description>Ctitrigout 4 is inactive.</description>
45130 <description>Shows the status of ctitrigout5 output.</description>
45136 <description>Ctitrigout 5 is active.</description>
45141 <description>Ctitrigout 5 is inactive.</description>
45148 <description>Shows the status of ctitrigout6 output.</description>
45154 <description>Ctitrigout 6 is active.</description>
45159 <description>Ctitrigout 6 is inactive.</description>
45166 <description>Shows the status of ctitrigout7 output.</description>
45172 <description>Ctitrigout 7 is active.</description>
45177 <description>Ctitrigout 7 is inactive.</description>
45186 <description>CTI Channel In Status register</description>
45194 <description>Shows the status of the ctitrigin 0 input.</description>
45200 <description>Ctichin 0 is active.</description>
45205 <description>Ctichin 0 is inactive.</description>
45212 <description>Shows the status of the ctitrigin 1 input.</description>
45218 <description>Ctichin 1 is active.</description>
45223 <description>Ctichin 1 is inactive.</description>
45230 <description>Shows the status of the ctitrigin 2 input.</description>
45236 <description>Ctichin 2 is active.</description>
45241 <description>Ctichin 2 is inactive.</description>
45248 <description>Shows the status of the ctitrigin 3 input.</description>
45254 <description>Ctichin 3 is active.</description>
45259 <description>Ctichin 3 is inactive.</description>
45268 <description>Enable CTI Channel Gate register</description>
45276 <description>Enable ctichout0.</description>
45282 <description>Enable ctichout channel 0 propagation.</description>
45287 <description>Disable ctichout channel 0 propagation.</description>
45294 <description>Enable ctichout1.</description>
45300 <description>Enable ctichout channel 1 propagation.</description>
45305 <description>Disable ctichout channel 1 propagation.</description>
45312 <description>Enable ctichout2.</description>
45318 <description>Enable ctichout channel 2 propagation.</description>
45323 <description>Disable ctichout channel 2 propagation.</description>
45330 <description>Enable ctichout3.</description>
45336 <description>Enable ctichout channel 3 propagation.</description>
45341 <description>Disable ctichout channel 3 propagation.</description>
45350 <description>Device Architecture register</description>
45358 <description>Contains the CTI device architecture.</description>
45366 <description>Device Configuration register</description>
45374 …<description>Indicates the number of multiplexers available on Trigger Inputs and Trigger Outputs …
45375 … The default value of 0b00000 indicates that no multiplexing is present.</description>
45381 <description>Number of ECT triggers available.</description>
45387 <description>Number of ECT channels available.</description>
45395 <description>Device Type Identifier register</description>
45403 …<description>Major classification of the type of the debug component as specified in the Arm Archi…
45404 debug and trace component.</description>
45410 …<description>Indicates that this component allows a debugger to control other components in an Arm…
45417 …<description>Sub-classification of the type of the debug component as specified in the Arm Archite…
45418 the major classification as specified in the MAJOR field.</description>
45424 … <description>Indicates that this component is a sub-triggering component.</description>
45433 <description>Peripheral ID4 Register</description>
45441 …<description>Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the comp…
45447 <description>JEDEC continuation code.</description>
45454 … <description>Always 0b0000. Indicates that the device only occupies 4KB of memory.</description>
45462 <description>Peripheral ID5 register</description>
45470 <description>Peripheral ID6 register</description>
45478 <description>Peripheral ID7 register</description>
45486 <description>Peripheral ID0 Register</description>
45494 …<description>Bits[7:0] of the 12-bit part number of the component. The designer of the component a…
45500 … <description>Indicates bits[7:0] of the part number of the component.</description>
45509 <description>Peripheral ID1 Register</description>
45517 …<description>Bits[11:8] of the 12-bit part number of the component. The designer of the component …
45523 … <description>Indicates bits[11:8] of the part number of the component.</description>
45530 …<description>Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the comp…
45536 <description>Arm. Bits[3:0] of the JEDEC JEP106 Identity Code</description>
45545 <description>Peripheral ID2 Register</description>
45553 …<description>Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the comp…
45559 <description>Arm. Bits[6:4] of the JEDEC JEP106 Identity Code</description>
45566 … <description>Always 1. Indicates that the JEDEC-assigned designer ID is used.</description>
45572 <description>Peripheral revision</description>
45578 <description>This device is at r0p0</description>
45587 <description>Peripheral ID3 Register</description>
45595 …<description>Customer Modified. Indicates whether the customer has modified the behavior of the co…
45596 …ustomers change this value when they make authorized modifications to this component.</description>
45602 … <description>Indicates that the customer has not modified this component.</description>
45609 …<description>Indicates minor errata fixes specific to the revision of the component being used, fo…
45611 …is field if required, for example, by driving it from registers that reset to 0b0000.</description>
45617 … <description>Indicates that there are no errata fixes to this component.</description>
45626 <description>Component ID0 Register</description>
45634 … <description>Preamble[0]. Contains bits[7:0] of the component identification code.</description>
45640 <description>Bits[7:0] of the identification code.</description>
45649 <description>Component ID1 Register</description>
45657 … <description>Preamble[1]. Contains bits[11:8] of the component identification code.</description>
45663 <description>Bits[11:8] of the identification code.</description>
45670 …<description>Class of the component, for example, whether the component is a ROM table or a generi…
45671 Contains bits[15:12] of the component identification code</description>
45677 <description>Indicates that the component is a CoreSight component.</description>
45686 <description>Component ID2 Register</description>
45694 … <description>Preamble[2]. Contains bits[23:16] of the component identification code.</description>
45700 <description>Bits[23:16] of the identification code.</description>
45709 <description>Component ID3 Register</description>
45717 … <description>Preamble[3]. Contains bits[31:24] of the component identification code.</description>
45723 <description>Bits[31:24] of the identification code.</description>
45734 <description>Cross-Trigger Interface control 1</description>
45741 <description>ATB Replicator module 0</description>
45756 …<description>The IDFILTER0 register enables the programming of ID filtering for master port 0.</de…
45764 <description>Enable or disable ID filtering for IDs 0x00_0x0F.</description>
45770 … <description>Transactions with these IDs are passed on to ATB master port 0.</description>
45775 … <description>Transactions with these IDs are discarded by the replicator.</description>
45782 <description>Enable or disable ID filtering for IDs 0x10_0x1F.</description>
45788 … <description>Transactions with these IDs are passed on to ATB master port 0.</description>
45793 … <description>Transactions with these IDs are discarded by the replicator.</description>
45800 <description>Enable or disable ID filtering for IDs 0x20_0x2F.</description>
45806 … <description>Transactions with these IDs are passed on to ATB master port 0.</description>
45811 … <description>Transactions with these IDs are discarded by the replicator.</description>
45818 <description>Enable or disable ID filtering for IDs 0x30_0x3F.</description>
45824 … <description>Transactions with these IDs are passed on to ATB master port 0.</description>
45829 … <description>Transactions with these IDs are discarded by the replicator.</description>
45836 <description>Enable or disable ID filtering for IDs 0x40_0x4F.</description>
45842 … <description>Transactions with these IDs are passed on to ATB master port 0.</description>
45847 … <description>Transactions with these IDs are discarded by the replicator.</description>
45854 <description>Enable or disable ID filtering for IDs 0x50_0x5F.</description>
45860 … <description>Transactions with these IDs are passed on to ATB master port 0.</description>
45865 … <description>Transactions with these IDs are discarded by the replicator.</description>
45872 <description>Enable or disable ID filtering for IDs 0x60_0x6F.</description>
45878 … <description>Transactions with these IDs are passed on to ATB master port 0.</description>
45883 … <description>Transactions with these IDs are discarded by the replicator.</description>
45890 <description>Enable or disable ID filtering for IDs 0x70_0x7F.</description>
45896 … <description>Transactions with these IDs are passed on to ATB master port 0.</description>
45901 … <description>Transactions with these IDs are discarded by the replicator.</description>
45910 …<description>The IDFILTER1 register enables the programming of ID filtering for master port 1.</de…
45918 <description>Enable or disable ID filtering for IDs 0x00_0x0F.</description>
45924 … <description>Transactions with these IDs are passed on to ATB master port 1.</description>
45929 … <description>Transactions with these IDs are discarded by the replicator.</description>
45936 <description>Enable or disable ID filtering for IDs 0x10_0x1F.</description>
45942 … <description>Transactions with these IDs are passed on to ATB master port 1.</description>
45947 … <description>Transactions with these IDs are discarded by the replicator.</description>
45954 <description>Enable or disable ID filtering for IDs 0x20_0x2F.</description>
45960 … <description>Transactions with these IDs are passed on to ATB master port 1.</description>
45965 … <description>Transactions with these IDs are discarded by the replicator.</description>
45972 <description>Enable or disable ID filtering for IDs 0x30_0x3F.</description>
45978 … <description>Transactions with these IDs are passed on to ATB master port 1.</description>
45983 … <description>Transactions with these IDs are discarded by the replicator.</description>
45990 <description>Enable or disable ID filtering for IDs 0x40_0x4F.</description>
45996 … <description>Transactions with these IDs are passed on to ATB master port 1.</description>
46001 … <description>Transactions with these IDs are discarded by the replicator.</description>
46008 <description>Enable or disable ID filtering for IDs 0x50_0x5F.</description>
46014 … <description>Transactions with these IDs are passed on to ATB master port 1.</description>
46019 … <description>Transactions with these IDs are discarded by the replicator.</description>
46026 <description>Enable or disable ID filtering for IDs 0x60_0x6F.</description>
46032 … <description>Transactions with these IDs are passed on to ATB master port 1.</description>
46037 … <description>Transactions with these IDs are discarded by the replicator.</description>
46044 <description>Enable or disable ID filtering for IDs 0x70_0x7F.</description>
46050 … <description>Transactions with these IDs are passed on to ATB master port 1.</description>
46055 … <description>Transactions with these IDs are discarded by the replicator.</description>
46064 …<description>The ITATBCTR1 register returns the value of the atreadym0, atreadym1, and atvalids in…
46072 <description>Reads the value of the atreadym0 input.</description>
46078 <description>Pin is logic 0.</description>
46083 <description>Pin is logic 1.</description>
46090 <description>Reads the value of the atreadym1 input.</description>
46096 <description>Pin is logic 0.</description>
46101 <description>Pin is logic 1.</description>
46108 <description>Reads the value of the atvalids input.</description>
46114 <description>Pin is logic 0.</description>
46119 <description>Pin is logic 1.</description>
46128 …<description>The ITATBCTR0 register controls the value of the atvalidm0, atvalidm1, and atreadys o…
46136 <description>Sets the value of the atvalidm0 output.</description>
46142 <description>Pin is logic 0.</description>
46147 <description>Pin is logic 1.</description>
46154 <description>Sets the value of the atvalidm1 output.</description>
46160 <description>Pin is logic 0.</description>
46165 <description>Pin is logic 1.</description>
46172 <description>Sets the value of the atreadys output.</description>
46178 <description>Pin is logic 0.</description>
46183 <description>Pin is logic 1.</description>
46192 …<description>The ITCTRL register enables the component to switch from a functional mode, which is …
46193 …e directly controlled for the purposes of integration testing and topology detection.</description>
46201 <description>Integration Mode Enable.</description>
46207 <description>Integration mode disabled.</description>
46212 <description>Integration mode enabled.</description>
46221 …<description>Software can use the claim tag to coordinate application and debugger access to trace…
46222 …ster sets bits in the claim tag, and determines the number of claim bits implemented.</description>
46230 <description>Set claim bit 0 and check if bit is implemented or not.</description>
46237 <description>Claim bit 0 is not implemented.</description>
46242 <description>Claim bit 0 is implemented.</description>
46250 <description>Set claim bit 0.</description>
46257 <description>Set claim bit 1 and check if bit is implemented or not.</description>
46264 <description>Claim bit 1 is not implemented.</description>
46269 <description>Claim bit 1 is implemented.</description>
46277 <description>Set claim bit 1.</description>
46284 <description>Set claim bit 2 and check if bit is implemented or not.</description>
46291 <description>Claim bit 2 is not implemented.</description>
46296 <description>Claim bit 2 is implemented.</description>
46304 <description>Set claim bit 2.</description>
46311 <description>Set claim bit 3 and check if bit is implemented or not.</description>
46318 <description>Claim bit 3 is not implemented.</description>
46323 <description>Claim bit 3 is implemented.</description>
46331 <description>Set claim bit 3.</description>
46340 …<description>Software can use the claim tag to coordinate application and debugger access to trace…
46342 …ets the bits in the claim tag to 0 and determines the current value of the claim tag.</description>
46350 <description>Read or clear claim bit 0.</description>
46357 <description>Claim bit 0 is not set.</description>
46362 <description>Claim bit 0 is set.</description>
46370 <description>Clear claim bit 0.</description>
46377 <description>Read or clear claim bit 1.</description>
46384 <description>Claim bit 1 is not set.</description>
46389 <description>Claim bit 1 is set.</description>
46397 <description>Clear claim bit 1.</description>
46404 <description>Read or clear claim bit 2.</description>
46411 <description>Claim bit 2 is not set.</description>
46416 <description>Claim bit 2 is set.</description>
46424 <description>Clear claim bit 2.</description>
46431 <description>Read or clear claim bit 3.</description>
46438 <description>Claim bit 3 is not set.</description>
46443 <description>Claim bit 3 is set.</description>
46451 <description>Clear claim bit 3.</description>
46460 <description>This is used to enable write access to device registers.</description>
46468 …<description>A write of 0xC5ACCE55 enables further write access to this device. Any other write re…
46474 <description>Unlock register interface.</description>
46483 …<description>This indicates the status of the lock control mechanism. This lock prevents accidenta…
46487 … For most components this covers all registers except for the Lock Access Register.</description>
46495 … <description>Indicates that a lock control mechanism exists for this device.</description>
46501 …<description>No lock control mechanism exists, writes to the Lock Access Register are ignored.</de…
46506 <description>Lock control mechanism is present.</description>
46513 <description>Returns the current status of the Lock.</description>
46519 <description>Write access is allowed to this device.</description>
46524 …<description>Write access to the component is blocked. All writes to control registers are ignored…
46531 …<description>Indicates if the Lock Access Register is implemented as 8-bit or 32-bit.</description>
46537 … <description>This component implements a 32-bit Lock Access Register.</description>
46542 … <description>This component implements an 8-bit Lock Access Register.</description>
46551 <description>Indicates the current level of tracing permitted by the system</description>
46559 <description>Non-secure Invasive Debug</description>
46565 <description>The feature is not implemented.</description>
46570 <description>The feature is implemented.</description>
46577 <description>Non-secure Non-Invasive Debug</description>
46583 <description>The feature is not implemented.</description>
46588 <description>The feature is implemented.</description>
46595 <description>Secure Invasive Debug</description>
46601 <description>The feature is not implemented.</description>
46606 <description>The feature is implemented.</description>
46613 <description>Secure Non-Invasive Debug</description>
46619 <description>The feature is not implemented.</description>
46624 <description>The feature is implemented.</description>
46633 <description>Indicates the capabilities of the component.</description>
46641 <description>Indicates the number of master ports implemented.</description>
46649 …description>The DEVTYPE register provides a debugger with information about the component when the…
46657 <description>The main type of the component</description>
46663 … <description>Indicates that this component has ATB inputs and outputs.</description>
46670 <description>The sub-type of the component</description>
46676 …<description>Indicates that this component replicates trace from a single source to multiple targe…
46685 <description>Coresight peripheral identification registers.</description>
46693 <description>Coresight peripheral identification registers.</description>
46701 <description>Coresight peripheral identification registers.</description>
46709 <description>Coresight peripheral identification registers.</description>
46717 <description>Coresight peripheral identification registers.</description>
46725 <description>Coresight component identification registers.</description>
46733 <description>Coresight component identification registers.</description>
46741 <description>Coresight component identification registers.</description>
46749 <description>Coresight component identification registers.</description>
46759 <description>ATB Replicator module 1</description>
46766 <description>ATB Replicator module 2</description>
46773 <description>ATB Replicator module 3</description>
46780 <description>ATB funnel module 0</description>
46795 …<description>The IDFILTER0 register enables the programming of ID filtering for master port 0.</de…
46803 <description>Enable slave port 0.</description>
46809 …<description>Slave port disabled. This excludes the port from the priority selection scheme.</desc…
46814 <description>Slave port enabled.</description>
46821 <description>Enable slave port 1.</description>
46827 …<description>Slave port disabled. This excludes the port from the priority selection scheme.</desc…
46832 <description>Slave port enabled.</description>
46839 <description>Enable slave port 2.</description>
46845 …<description>Slave port disabled. This excludes the port from the priority selection scheme.</desc…
46850 <description>Slave port enabled.</description>
46857 <description>Enable slave port 3.</description>
46863 …<description>Slave port disabled. This excludes the port from the priority selection scheme.</desc…
46868 <description>Slave port enabled.</description>
46875 <description>Enable slave port 4.</description>
46881 …<description>Slave port disabled. This excludes the port from the priority selection scheme.</desc…
46886 <description>Slave port enabled.</description>
46893 <description>Enable slave port 5.</description>
46899 …<description>Slave port disabled. This excludes the port from the priority selection scheme.</desc…
46904 <description>Slave port enabled.</description>
46911 <description>Enable slave port 6.</description>
46917 …<description>Slave port disabled. This excludes the port from the priority selection scheme.</desc…
46922 <description>Slave port enabled.</description>
46929 <description>Enable slave port 7.</description>
46935 …<description>Slave port disabled. This excludes the port from the priority selection scheme.</desc…
46940 <description>Slave port enabled.</description>
46947 …<description>Hold Time. The formatting scheme can become inefficient when fast switching occurs, a…
46950 …hat can be entered is 0b1110 and this equates to 15 transactions. 0b1111 is reserved.</description>
46958 …description>The Priority_Ctrl_Reg register defines the order in which inputs are selected. Each 3-…
46966 <description>Priority value of port number 0.</description>
46972 <description>Priority value of port number 1.</description>
46978 <description>Priority value of port number 2.</description>
46984 <description>Priority value of port number 3.</description>
46990 <description>Priority value of port number 4.</description>
46996 <description>Priority value of port number 5.</description>
47002 <description>Priority value of port number 6.</description>
47008 <description>Priority value of port number 7.</description>
47016 …<description>The ITATBDATA0 register performs different functions depending on whether the access …
47024 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47030 <description>Pin is logic 0.</description>
47035 <description>Pin is logic 1.</description>
47042 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47048 <description>Pin is logic 0.</description>
47053 <description>Pin is logic 1.</description>
47060 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47066 <description>Pin is logic 0.</description>
47071 <description>Pin is logic 1.</description>
47078 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47084 <description>Pin is logic 0.</description>
47089 <description>Pin is logic 1.</description>
47096 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47102 <description>Pin is logic 0.</description>
47107 <description>Pin is logic 1.</description>
47114 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47120 <description>Pin is logic 0.</description>
47125 <description>Pin is logic 1.</description>
47132 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47138 <description>Pin is logic 0.</description>
47143 <description>Pin is logic 1.</description>
47150 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47156 <description>Pin is logic 0.</description>
47161 <description>Pin is logic 1.</description>
47168 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47174 <description>Pin is logic 0.</description>
47179 <description>Pin is logic 1.</description>
47186 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47192 <description>Pin is logic 0.</description>
47197 <description>Pin is logic 1.</description>
47204 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47210 <description>Pin is logic 0.</description>
47215 <description>Pin is logic 1.</description>
47222 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47228 <description>Pin is logic 0.</description>
47233 <description>Pin is logic 1.</description>
47240 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47246 <description>Pin is logic 0.</description>
47251 <description>Pin is logic 1.</description>
47258 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47264 <description>Pin is logic 0.</description>
47269 <description>Pin is logic 1.</description>
47276 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47282 <description>Pin is logic 0.</description>
47287 <description>Pin is logic 1.</description>
47294 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47300 <description>Pin is logic 0.</description>
47305 <description>Pin is logic 1.</description>
47312 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47318 <description>Pin is logic 0.</description>
47323 <description>Pin is logic 1.</description>
47332 …<description>The ITATBCTR2 register performs different functions depending on whether the access i…
47340 <description>A read access returns the value of atreadym.
47341 …s outputs the data to afvalids[n], where the value of the CTRLREG at 0x000 defines n.</description>
47347 <description>Pin is logic 0.</description>
47352 <description>Pin is logic 1.</description>
47359 <description>A read access returns the value of afvalidm.
47360 …s outputs the data to atreadys[n], where the value of the CTRLREG at 0x000 defines n.</description>
47366 <description>Pin is logic 0.</description>
47371 <description>Pin is logic 1.</description>
47380 …<description>The ITATBCTR1 register performs different functions depending on whether the access i…
47388 …<description>A read returns the value of the atids[n] signals, where the value of the Control Regi…
47389 A write outputs the value to the atidm port.</description>
47395 <description>Pin is logic 0.</description>
47400 <description>Pin is logic 1.</description>
47409 …<description>The ITATBCTR0 register performs different functions depending on whether the access i…
47417 …<description>A read returns the value of the atvalids[n] signal, where the value of the CTRLREG at…
47418 A write outputs the value to atvalidm.</description>
47424 <description>Pin is logic 0.</description>
47429 <description>Pin is logic 1.</description>
47436 …<description>A read returns the value of the afreadys[n] signal, where the value of the Ctrl_Reg a…
47437 A write outputs the value to afreadym.</description>
47443 <description>Pin is logic 0.</description>
47448 <description>Pin is logic 1.</description>
47455 …<description>A read returns the value of the atbytess[n] signal, where the value of the Ctrl_Reg a…
47456 A write outputs the value to atbytesm.</description>
47462 <description>Pin is logic 0.</description>
47467 <description>Pin is logic 1.</description>
47476 …<description>The ITCTRL register enables the component to switch from a functional mode, which is …
47477 …e directly controlled for the purposes of integration testing and topology detection.</description>
47485 <description>Integration Mode Enable.</description>
47491 <description>Integration mode disabled.</description>
47496 <description>Integration mode enabled.</description>
47505 …<description>Software can use the claim tag to coordinate application and debugger access to trace…
47506 …ster sets bits in the claim tag, and determines the number of claim bits implemented.</description>
47514 <description>Set claim bit 0 and check if bit is implemented or not.</description>
47521 <description>Claim bit 0 is not implemented.</description>
47526 <description>Claim bit 0 is implemented.</description>
47534 <description>Set claim bit 0.</description>
47541 <description>Set claim bit 1 and check if bit is implemented or not.</description>
47548 <description>Claim bit 1 is not implemented.</description>
47553 <description>Claim bit 1 is implemented.</description>
47561 <description>Set claim bit 1.</description>
47568 <description>Set claim bit 2 and check if bit is implemented or not.</description>
47575 <description>Claim bit 2 is not implemented.</description>
47580 <description>Claim bit 2 is implemented.</description>
47588 <description>Set claim bit 2.</description>
47595 <description>Set claim bit 3 and check if bit is implemented or not.</description>
47602 <description>Claim bit 3 is not implemented.</description>
47607 <description>Claim bit 3 is implemented.</description>
47615 <description>Set claim bit 3.</description>
47624 …<description>Software can use the claim tag to coordinate application and debugger access to trace…
47626 …ets the bits in the claim tag to 0 and determines the current value of the claim tag.</description>
47634 <description>Read or clear claim bit 0.</description>
47641 <description>Claim bit 0 is not set.</description>
47646 <description>Claim bit 0 is set.</description>
47654 <description>Clear claim bit 0.</description>
47661 <description>Read or clear claim bit 1.</description>
47668 <description>Claim bit 1 is not set.</description>
47673 <description>Claim bit 1 is set.</description>
47681 <description>Clear claim bit 1.</description>
47688 <description>Read or clear claim bit 2.</description>
47695 <description>Claim bit 2 is not set.</description>
47700 <description>Claim bit 2 is set.</description>
47708 <description>Clear claim bit 2.</description>
47715 <description>Read or clear claim bit 3.</description>
47722 <description>Claim bit 3 is not set.</description>
47727 <description>Claim bit 3 is set.</description>
47735 <description>Clear claim bit 3.</description>
47744 <description>This is used to enable write access to device registers.</description>
47752 …<description>A write of 0xC5ACCE55 enables further write access to this device. Any other write re…
47758 <description>Unlock register interface.</description>
47767 …<description>This indicates the status of the lock control mechanism. This lock prevents accidenta…
47771 … For most components this covers all registers except for the Lock Access Register.</description>
47779 … <description>Indicates that a lock control mechanism exists for this device.</description>
47785 …<description>No lock control mechanism exists, writes to the Lock Access Register are ignored.</de…
47790 <description>Lock control mechanism is present.</description>
47797 <description>Returns the current status of the Lock.</description>
47803 <description>Write access is allowed to this device.</description>
47808 …<description>Write access to the component is blocked. All writes to control registers are ignored…
47815 …<description>Indicates if the Lock Access Register is implemented as 8-bit or 32-bit.</description>
47821 … <description>This component implements a 32-bit Lock Access Register.</description>
47826 … <description>This component implements an 8-bit Lock Access Register.</description>
47835 <description>Indicates the current level of tracing permitted by the system</description>
47843 <description>Non-secure Invasive Debug</description>
47849 <description>The feature is not implemented.</description>
47854 <description>The feature is implemented.</description>
47861 <description>Non-secure Non-Invasive Debug</description>
47867 <description>The feature is not implemented.</description>
47872 <description>The feature is implemented.</description>
47879 <description>Secure Invasive Debug</description>
47885 <description>The feature is not implemented.</description>
47890 <description>The feature is implemented.</description>
47897 <description>Secure Non-Invasive Debug</description>
47903 <description>The feature is not implemented.</description>
47908 <description>The feature is implemented.</description>
47917 <description>Indicates the capabilities of the component.</description>
47925 …<description>Indicates the number of input ports connected. 0x0 and 0x1 are illegal values.</descr…
47933 …description>The DEVTYPE register provides a debugger with information about the component when the…
47941 <description>The main type of the component</description>
47947 … <description>Indicates that this component has ATB inputs and outputs.</description>
47954 <description>The sub-type of the component</description>
47960 … <description>This component arbitrates ATB inputs mapping to ATB outputs.</description>
47969 <description>Coresight peripheral identification registers.</description>
47977 <description>Coresight peripheral identification registers.</description>
47985 <description>Coresight peripheral identification registers.</description>
47993 <description>Coresight peripheral identification registers.</description>
48001 <description>Coresight peripheral identification registers.</description>
48009 <description>Coresight component identification registers.</description>
48017 <description>Coresight component identification registers.</description>
48025 <description>Coresight component identification registers.</description>
48033 <description>Coresight component identification registers.</description>
48043 <description>ATB funnel module 1</description>
48050 <description>ATB funnel module 2</description>
48057 <description>ATB funnel module 3</description>
48064 <description>VPR CLIC registers</description>
48141 <description>Unspecified</description>
48147 <description>CLIC configuration.</description>
48155 <description>Selective interrupt hardware vectoring.</description>
48161 <description>Selective interrupt hardware vectoring is implemented</description>
48168 <description>Interrupt level encoding.</description>
48174 <description>8 bits = interrupt levels encoded in eight bits</description>
48181 <description>Interrupt privilege mode.</description>
48187 <description>All interrupts are M-mode only</description>
48196 <description>CLIC information.</description>
48204 <description>Maximum number of interrupts supported.</description>
48210 <description>Version</description>
48216 <description>Number of maximum interrupt triggers supported</description>
48226 … <description>Description collection: Interrupt control register for IRQ number [n].</description>
48234 <description>Interrupt Pending bit.</description>
48240 <description>Interrupt not pending</description>
48245 <description>Interrupt pending</description>
48252 <description>Read as 0, write ignored.</description>
48259 <description>Interrupt enable bit.</description>
48265 <description>Interrupt disabled</description>
48270 <description>Interrupt enabled</description>
48277 <description>Read as 0, write ignored.</description>
48284 <description>Selective Hardware Vectoring.</description>
48291 <description>Hardware vectored</description>
48298 <description>Trigger type and polarity for each interrupt input.</description>
48305 <description>Interrupts are edge-triggered</description>
48312 <description>Privilege mode.</description>
48319 <description>Machine mode</description>
48326 <description>Interrupt priority level</description>
48332 <description>Priority level 0</description>
48337 <description>Priority level 1</description>
48342 <description>Priority level 2</description>
48347 <description>Priority level 3</description>
48359 <description>VTIM CSR registers</description>
48375 <description>Unused.</description>
48384 <description>GPIO Tasks and Events 0</description>
48410 …description>Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on…
48418 …<description>Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in C…
48424 <description>Trigger task</description>
48435 …<description>Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action o…
48443 …<description>Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high.…
48449 <description>Trigger task</description>
48460 …<description>Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action o…
48468 …<description>Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low.<…
48474 <description>Trigger task</description>
48485 <description>Description collection: Subscribe configuration for task OUT[n]</description>
48493 <description>DPPI channel that task OUT[n] will subscribe to</description>
48504 <description>Disable subscription</description>
48509 <description>Enable subscription</description>
48520 <description>Description collection: Subscribe configuration for task SET[n]</description>
48528 <description>DPPI channel that task SET[n] will subscribe to</description>
48539 <description>Disable subscription</description>
48544 <description>Enable subscription</description>
48555 <description>Description collection: Subscribe configuration for task CLR[n]</description>
48563 <description>DPPI channel that task CLR[n] will subscribe to</description>
48574 <description>Disable subscription</description>
48579 <description>Enable subscription</description>
48590 … <description>Description collection: Event from pin specified in CONFIG[n].PSEL</description>
48598 <description>Event from pin specified in CONFIG[n].PSEL</description>
48604 <description>Event not generated</description>
48609 <description>Event generated</description>
48620 <description>Peripheral events.</description>
48626 <description>Description cluster: Non-secure port event from owner n</description>
48635 <description>Non-secure port event from owner n</description>
48641 <description>Event not generated</description>
48646 <description>Event generated</description>
48655 <description>Description cluster: Secure port event from owner n</description>
48664 <description>Secure port event from owner n</description>
48670 <description>Event not generated</description>
48675 <description>Event generated</description>
48687 <description>Description collection: Publish configuration for event IN[n]</description>
48695 <description>DPPI channel that event IN[n] will publish to</description>
48706 <description>Disable publishing</description>
48711 <description>Enable publishing</description>
48722 <description>Publish configuration for events</description>
48728 … <description>Description cluster: Publish configuration for event PORT[n].NONSECURE</description>
48737 <description>DPPI channel that event PORT[n].NONSECURE will publish to</description>
48748 <description>Disable publishing</description>
48753 <description>Enable publishing</description>
48762 … <description>Description cluster: Publish configuration for event PORT[n].SECURE</description>
48771 <description>DPPI channel that event PORT[n].SECURE will publish to</description>
48782 <description>Disable publishing</description>
48787 <description>Enable publishing</description>
48797 <description>Enable interrupt</description>
48805 <description>Write '1' to enable interrupt for event IN[0]</description>
48812 <description>Read: Disabled</description>
48817 <description>Read: Enabled</description>
48825 <description>Enable</description>
48832 <description>Write '1' to enable interrupt for event IN[1]</description>
48839 <description>Read: Disabled</description>
48844 <description>Read: Enabled</description>
48852 <description>Enable</description>
48859 <description>Write '1' to enable interrupt for event IN[2]</description>
48866 <description>Read: Disabled</description>
48871 <description>Read: Enabled</description>
48879 <description>Enable</description>
48886 <description>Write '1' to enable interrupt for event IN[3]</description>
48893 <description>Read: Disabled</description>
48898 <description>Read: Enabled</description>
48906 <description>Enable</description>
48913 <description>Write '1' to enable interrupt for event IN[4]</description>
48920 <description>Read: Disabled</description>
48925 <description>Read: Enabled</description>
48933 <description>Enable</description>
48940 <description>Write '1' to enable interrupt for event IN[5]</description>
48947 <description>Read: Disabled</description>
48952 <description>Read: Enabled</description>
48960 <description>Enable</description>
48967 <description>Write '1' to enable interrupt for event IN[6]</description>
48974 <description>Read: Disabled</description>
48979 <description>Read: Enabled</description>
48987 <description>Enable</description>
48994 <description>Write '1' to enable interrupt for event IN[7]</description>
49001 <description>Read: Disabled</description>
49006 <description>Read: Enabled</description>
49014 <description>Enable</description>
49021 <description>Write '1' to enable interrupt for event PORT0NONSECURE</description>
49028 <description>Read: Disabled</description>
49033 <description>Read: Enabled</description>
49041 <description>Enable</description>
49048 <description>Write '1' to enable interrupt for event PORT0SECURE</description>
49055 <description>Read: Disabled</description>
49060 <description>Read: Enabled</description>
49068 <description>Enable</description>
49075 <description>Write '1' to enable interrupt for event PORT1NONSECURE</description>
49082 <description>Read: Disabled</description>
49087 <description>Read: Enabled</description>
49095 <description>Enable</description>
49102 <description>Write '1' to enable interrupt for event PORT1SECURE</description>
49109 <description>Read: Disabled</description>
49114 <description>Read: Enabled</description>
49122 <description>Enable</description>
49129 <description>Write '1' to enable interrupt for event PORT2NONSECURE</description>
49136 <description>Read: Disabled</description>
49141 <description>Read: Enabled</description>
49149 <description>Enable</description>
49156 <description>Write '1' to enable interrupt for event PORT2SECURE</description>
49163 <description>Read: Disabled</description>
49168 <description>Read: Enabled</description>
49176 <description>Enable</description>
49183 <description>Write '1' to enable interrupt for event PORT3NONSECURE</description>
49190 <description>Read: Disabled</description>
49195 <description>Read: Enabled</description>
49203 <description>Enable</description>
49210 <description>Write '1' to enable interrupt for event PORT3SECURE</description>
49217 <description>Read: Disabled</description>
49222 <description>Read: Enabled</description>
49230 <description>Enable</description>
49239 <description>Disable interrupt</description>
49247 <description>Write '1' to disable interrupt for event IN[0]</description>
49254 <description>Read: Disabled</description>
49259 <description>Read: Enabled</description>
49267 <description>Disable</description>
49274 <description>Write '1' to disable interrupt for event IN[1]</description>
49281 <description>Read: Disabled</description>
49286 <description>Read: Enabled</description>
49294 <description>Disable</description>
49301 <description>Write '1' to disable interrupt for event IN[2]</description>
49308 <description>Read: Disabled</description>
49313 <description>Read: Enabled</description>
49321 <description>Disable</description>
49328 <description>Write '1' to disable interrupt for event IN[3]</description>
49335 <description>Read: Disabled</description>
49340 <description>Read: Enabled</description>
49348 <description>Disable</description>
49355 <description>Write '1' to disable interrupt for event IN[4]</description>
49362 <description>Read: Disabled</description>
49367 <description>Read: Enabled</description>
49375 <description>Disable</description>
49382 <description>Write '1' to disable interrupt for event IN[5]</description>
49389 <description>Read: Disabled</description>
49394 <description>Read: Enabled</description>
49402 <description>Disable</description>
49409 <description>Write '1' to disable interrupt for event IN[6]</description>
49416 <description>Read: Disabled</description>
49421 <description>Read: Enabled</description>
49429 <description>Disable</description>
49436 <description>Write '1' to disable interrupt for event IN[7]</description>
49443 <description>Read: Disabled</description>
49448 <description>Read: Enabled</description>
49456 <description>Disable</description>
49463 <description>Write '1' to disable interrupt for event PORT0NONSECURE</description>
49470 <description>Read: Disabled</description>
49475 <description>Read: Enabled</description>
49483 <description>Disable</description>
49490 <description>Write '1' to disable interrupt for event PORT0SECURE</description>
49497 <description>Read: Disabled</description>
49502 <description>Read: Enabled</description>
49510 <description>Disable</description>
49517 <description>Write '1' to disable interrupt for event PORT1NONSECURE</description>
49524 <description>Read: Disabled</description>
49529 <description>Read: Enabled</description>
49537 <description>Disable</description>
49544 <description>Write '1' to disable interrupt for event PORT1SECURE</description>
49551 <description>Read: Disabled</description>
49556 <description>Read: Enabled</description>
49564 <description>Disable</description>
49571 <description>Write '1' to disable interrupt for event PORT2NONSECURE</description>
49578 <description>Read: Disabled</description>
49583 <description>Read: Enabled</description>
49591 <description>Disable</description>
49598 <description>Write '1' to disable interrupt for event PORT2SECURE</description>
49605 <description>Read: Disabled</description>
49610 <description>Read: Enabled</description>
49618 <description>Disable</description>
49625 <description>Write '1' to disable interrupt for event PORT3NONSECURE</description>
49632 <description>Read: Disabled</description>
49637 <description>Read: Enabled</description>
49645 <description>Disable</description>
49652 <description>Write '1' to disable interrupt for event PORT3SECURE</description>
49659 <description>Read: Disabled</description>
49664 <description>Read: Enabled</description>
49672 <description>Disable</description>
49681 <description>Enable interrupt</description>
49689 <description>Write '1' to enable interrupt for event IN[0]</description>
49696 <description>Read: Disabled</description>
49701 <description>Read: Enabled</description>
49709 <description>Enable</description>
49716 <description>Write '1' to enable interrupt for event IN[1]</description>
49723 <description>Read: Disabled</description>
49728 <description>Read: Enabled</description>
49736 <description>Enable</description>
49743 <description>Write '1' to enable interrupt for event IN[2]</description>
49750 <description>Read: Disabled</description>
49755 <description>Read: Enabled</description>
49763 <description>Enable</description>
49770 <description>Write '1' to enable interrupt for event IN[3]</description>
49777 <description>Read: Disabled</description>
49782 <description>Read: Enabled</description>
49790 <description>Enable</description>
49797 <description>Write '1' to enable interrupt for event IN[4]</description>
49804 <description>Read: Disabled</description>
49809 <description>Read: Enabled</description>
49817 <description>Enable</description>
49824 <description>Write '1' to enable interrupt for event IN[5]</description>
49831 <description>Read: Disabled</description>
49836 <description>Read: Enabled</description>
49844 <description>Enable</description>
49851 <description>Write '1' to enable interrupt for event IN[6]</description>
49858 <description>Read: Disabled</description>
49863 <description>Read: Enabled</description>
49871 <description>Enable</description>
49878 <description>Write '1' to enable interrupt for event IN[7]</description>
49885 <description>Read: Disabled</description>
49890 <description>Read: Enabled</description>
49898 <description>Enable</description>
49905 <description>Write '1' to enable interrupt for event PORT0NONSECURE</description>
49912 <description>Read: Disabled</description>
49917 <description>Read: Enabled</description>
49925 <description>Enable</description>
49932 <description>Write '1' to enable interrupt for event PORT0SECURE</description>
49939 <description>Read: Disabled</description>
49944 <description>Read: Enabled</description>
49952 <description>Enable</description>
49959 <description>Write '1' to enable interrupt for event PORT1NONSECURE</description>
49966 <description>Read: Disabled</description>
49971 <description>Read: Enabled</description>
49979 <description>Enable</description>
49986 <description>Write '1' to enable interrupt for event PORT1SECURE</description>
49993 <description>Read: Disabled</description>
49998 <description>Read: Enabled</description>
50006 <description>Enable</description>
50013 <description>Write '1' to enable interrupt for event PORT2NONSECURE</description>
50020 <description>Read: Disabled</description>
50025 <description>Read: Enabled</description>
50033 <description>Enable</description>
50040 <description>Write '1' to enable interrupt for event PORT2SECURE</description>
50047 <description>Read: Disabled</description>
50052 <description>Read: Enabled</description>
50060 <description>Enable</description>
50067 <description>Write '1' to enable interrupt for event PORT3NONSECURE</description>
50074 <description>Read: Disabled</description>
50079 <description>Read: Enabled</description>
50087 <description>Enable</description>
50094 <description>Write '1' to enable interrupt for event PORT3SECURE</description>
50101 <description>Read: Disabled</description>
50106 <description>Read: Enabled</description>
50114 <description>Enable</description>
50123 <description>Disable interrupt</description>
50131 <description>Write '1' to disable interrupt for event IN[0]</description>
50138 <description>Read: Disabled</description>
50143 <description>Read: Enabled</description>
50151 <description>Disable</description>
50158 <description>Write '1' to disable interrupt for event IN[1]</description>
50165 <description>Read: Disabled</description>
50170 <description>Read: Enabled</description>
50178 <description>Disable</description>
50185 <description>Write '1' to disable interrupt for event IN[2]</description>
50192 <description>Read: Disabled</description>
50197 <description>Read: Enabled</description>
50205 <description>Disable</description>
50212 <description>Write '1' to disable interrupt for event IN[3]</description>
50219 <description>Read: Disabled</description>
50224 <description>Read: Enabled</description>
50232 <description>Disable</description>
50239 <description>Write '1' to disable interrupt for event IN[4]</description>
50246 <description>Read: Disabled</description>
50251 <description>Read: Enabled</description>
50259 <description>Disable</description>
50266 <description>Write '1' to disable interrupt for event IN[5]</description>
50273 <description>Read: Disabled</description>
50278 <description>Read: Enabled</description>
50286 <description>Disable</description>
50293 <description>Write '1' to disable interrupt for event IN[6]</description>
50300 <description>Read: Disabled</description>
50305 <description>Read: Enabled</description>
50313 <description>Disable</description>
50320 <description>Write '1' to disable interrupt for event IN[7]</description>
50327 <description>Read: Disabled</description>
50332 <description>Read: Enabled</description>
50340 <description>Disable</description>
50347 <description>Write '1' to disable interrupt for event PORT0NONSECURE</description>
50354 <description>Read: Disabled</description>
50359 <description>Read: Enabled</description>
50367 <description>Disable</description>
50374 <description>Write '1' to disable interrupt for event PORT0SECURE</description>
50381 <description>Read: Disabled</description>
50386 <description>Read: Enabled</description>
50394 <description>Disable</description>
50401 <description>Write '1' to disable interrupt for event PORT1NONSECURE</description>
50408 <description>Read: Disabled</description>
50413 <description>Read: Enabled</description>
50421 <description>Disable</description>
50428 <description>Write '1' to disable interrupt for event PORT1SECURE</description>
50435 <description>Read: Disabled</description>
50440 <description>Read: Enabled</description>
50448 <description>Disable</description>
50455 <description>Write '1' to disable interrupt for event PORT2NONSECURE</description>
50462 <description>Read: Disabled</description>
50467 <description>Read: Enabled</description>
50475 <description>Disable</description>
50482 <description>Write '1' to disable interrupt for event PORT2SECURE</description>
50489 <description>Read: Disabled</description>
50494 <description>Read: Enabled</description>
50502 <description>Disable</description>
50509 <description>Write '1' to disable interrupt for event PORT3NONSECURE</description>
50516 <description>Read: Disabled</description>
50521 <description>Read: Enabled</description>
50529 <description>Disable</description>
50536 <description>Write '1' to disable interrupt for event PORT3SECURE</description>
50543 <description>Read: Disabled</description>
50548 <description>Read: Enabled</description>
50556 <description>Disable</description>
50565 …<description>Latency selection for Event mode (MODE=Event) with rising or falling edge detection o…
50574 <description>Latency setting</description>
50580 <description>Low power setting</description>
50585 <description>Low latency setting</description>
50596 …<description>Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] …
50604 <description>Mode</description>
50610 …<description>Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module.</descripti…
50615 <description>Event mode</description>
50620 <description>Task mode</description>
50627 …<description>GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event</descrip…
50633 <description>Port number</description>
50639 …description>When In task mode: Operation to be performed on output when OUT[n] task is triggered. …
50645 …<description>Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on…
50650 …<description>Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edg…
50655 …<description>Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling …
50660 …<description>Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin.…
50667 …<description>When in task mode: Initial value of the output when the GPIOTE channel is configured.…
50673 … <description>Task mode: Initial value of pin before task triggering is low</description>
50678 … <description>Task mode: Initial value of pin before task triggering is high</description>
50689 <description>GPIO Tasks and Events 1</description>
50705 <description>Global Real-time counter</description>
50734 … <description>Description collection: Capture the counter value to CC[n] register</description>
50742 <description>Capture the counter value to CC[n] register</description>
50748 <description>Trigger task</description>
50757 <description>Start the PWM</description>
50765 <description>Start the PWM</description>
50771 <description>Trigger task</description>
50780 <description>Stop the PWM</description>
50788 <description>Stop the PWM</description>
50794 <description>Trigger task</description>
50805 … <description>Description collection: Subscribe configuration for task CAPTURE[n]</description>
50813 <description>DPPI channel that task CAPTURE[n] will subscribe to</description>
50824 <description>Disable subscription</description>
50829 <description>Enable subscription</description>
50840 <description>Description collection: Compare event on CC[n] match</description>
50848 <description>Compare event on CC[n] match</description>
50854 <description>Event not generated</description>
50859 <description>Event generated</description>
50868 <description>Synchronize always-on LFCLK clock domain</description>
50876 <description>Synchronize always-on LFCLK clock domain</description>
50882 <description>Event not generated</description>
50887 <description>Event generated</description>
50896 <description>The SYSCOUNTER is in active state and value is valid</description>
50904 <description>The SYSCOUNTER is in active state and value is valid</description>
50910 <description>Event not generated</description>
50915 <description>Event generated</description>
50924 <description>Event on end of each PWM period</description>
50932 <description>Event on end of each PWM period</description>
50938 <description>Event not generated</description>
50943 <description>Event generated</description>
50954 … <description>Description collection: Publish configuration for event COMPARE[n]</description>
50962 <description>DPPI channel that event COMPARE[n] will publish to</description>
50973 <description>Disable publishing</description>
50978 <description>Enable publishing</description>
50987 <description>Shortcuts between local events and tasks</description>
50995 <description>Enable or disable interrupt</description>
51003 <description>Enable or disable interrupt for event COMPARE[0]</description>
51009 <description>Disable</description>
51014 <description>Enable</description>
51021 <description>Enable or disable interrupt for event COMPARE[1]</description>
51027 <description>Disable</description>
51032 <description>Enable</description>
51039 <description>Enable or disable interrupt for event COMPARE[2]</description>
51045 <description>Disable</description>
51050 <description>Enable</description>
51057 <description>Enable or disable interrupt for event COMPARE[3]</description>
51063 <description>Disable</description>
51068 <description>Enable</description>
51075 <description>Enable or disable interrupt for event COMPARE[4]</description>
51081 <description>Disable</description>
51086 <description>Enable</description>
51093 <description>Enable or disable interrupt for event COMPARE[5]</description>
51099 <description>Disable</description>
51104 <description>Enable</description>
51111 <description>Enable or disable interrupt for event COMPARE[6]</description>
51117 <description>Disable</description>
51122 <description>Enable</description>
51129 <description>Enable or disable interrupt for event COMPARE[7]</description>
51135 <description>Disable</description>
51140 <description>Enable</description>
51147 <description>Enable or disable interrupt for event COMPARE[8]</description>
51153 <description>Disable</description>
51158 <description>Enable</description>
51165 <description>Enable or disable interrupt for event COMPARE[9]</description>
51171 <description>Disable</description>
51176 <description>Enable</description>
51183 <description>Enable or disable interrupt for event COMPARE[10]</description>
51189 <description>Disable</description>
51194 <description>Enable</description>
51201 <description>Enable or disable interrupt for event COMPARE[11]</description>
51207 <description>Disable</description>
51212 <description>Enable</description>
51219 <description>Enable or disable interrupt for event COMPARE[12]</description>
51225 <description>Disable</description>
51230 <description>Enable</description>
51237 <description>Enable or disable interrupt for event COMPARE[13]</description>
51243 <description>Disable</description>
51248 <description>Enable</description>
51255 <description>Enable or disable interrupt for event COMPARE[14]</description>
51261 <description>Disable</description>
51266 <description>Enable</description>
51273 <description>Enable or disable interrupt for event COMPARE[15]</description>
51279 <description>Disable</description>
51284 <description>Enable</description>
51291 <description>Enable or disable interrupt for event RTCOMPARESYNC</description>
51297 <description>Disable</description>
51302 <description>Enable</description>
51309 <description>Enable or disable interrupt for event SYSCOUNTERVALID</description>
51315 <description>Disable</description>
51320 <description>Enable</description>
51327 <description>Enable or disable interrupt for event PWMPERIODEND</description>
51333 <description>Disable</description>
51338 <description>Enable</description>
51347 <description>Enable interrupt</description>
51355 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
51362 <description>Read: Disabled</description>
51367 <description>Read: Enabled</description>
51375 <description>Enable</description>
51382 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
51389 <description>Read: Disabled</description>
51394 <description>Read: Enabled</description>
51402 <description>Enable</description>
51409 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
51416 <description>Read: Disabled</description>
51421 <description>Read: Enabled</description>
51429 <description>Enable</description>
51436 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
51443 <description>Read: Disabled</description>
51448 <description>Read: Enabled</description>
51456 <description>Enable</description>
51463 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
51470 <description>Read: Disabled</description>
51475 <description>Read: Enabled</description>
51483 <description>Enable</description>
51490 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
51497 <description>Read: Disabled</description>
51502 <description>Read: Enabled</description>
51510 <description>Enable</description>
51517 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
51524 <description>Read: Disabled</description>
51529 <description>Read: Enabled</description>
51537 <description>Enable</description>
51544 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
51551 <description>Read: Disabled</description>
51556 <description>Read: Enabled</description>
51564 <description>Enable</description>
51571 <description>Write '1' to enable interrupt for event COMPARE[8]</description>
51578 <description>Read: Disabled</description>
51583 <description>Read: Enabled</description>
51591 <description>Enable</description>
51598 <description>Write '1' to enable interrupt for event COMPARE[9]</description>
51605 <description>Read: Disabled</description>
51610 <description>Read: Enabled</description>
51618 <description>Enable</description>
51625 <description>Write '1' to enable interrupt for event COMPARE[10]</description>
51632 <description>Read: Disabled</description>
51637 <description>Read: Enabled</description>
51645 <description>Enable</description>
51652 <description>Write '1' to enable interrupt for event COMPARE[11]</description>
51659 <description>Read: Disabled</description>
51664 <description>Read: Enabled</description>
51672 <description>Enable</description>
51679 <description>Write '1' to enable interrupt for event COMPARE[12]</description>
51686 <description>Read: Disabled</description>
51691 <description>Read: Enabled</description>
51699 <description>Enable</description>
51706 <description>Write '1' to enable interrupt for event COMPARE[13]</description>
51713 <description>Read: Disabled</description>
51718 <description>Read: Enabled</description>
51726 <description>Enable</description>
51733 <description>Write '1' to enable interrupt for event COMPARE[14]</description>
51740 <description>Read: Disabled</description>
51745 <description>Read: Enabled</description>
51753 <description>Enable</description>
51760 <description>Write '1' to enable interrupt for event COMPARE[15]</description>
51767 <description>Read: Disabled</description>
51772 <description>Read: Enabled</description>
51780 <description>Enable</description>
51787 <description>Write '1' to enable interrupt for event RTCOMPARESYNC</description>
51794 <description>Read: Disabled</description>
51799 <description>Read: Enabled</description>
51807 <description>Enable</description>
51814 <description>Write '1' to enable interrupt for event SYSCOUNTERVALID</description>
51821 <description>Read: Disabled</description>
51826 <description>Read: Enabled</description>
51834 <description>Enable</description>
51841 <description>Write '1' to enable interrupt for event PWMPERIODEND</description>
51848 <description>Read: Disabled</description>
51853 <description>Read: Enabled</description>
51861 <description>Enable</description>
51870 <description>Disable interrupt</description>
51878 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
51885 <description>Read: Disabled</description>
51890 <description>Read: Enabled</description>
51898 <description>Disable</description>
51905 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
51912 <description>Read: Disabled</description>
51917 <description>Read: Enabled</description>
51925 <description>Disable</description>
51932 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
51939 <description>Read: Disabled</description>
51944 <description>Read: Enabled</description>
51952 <description>Disable</description>
51959 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
51966 <description>Read: Disabled</description>
51971 <description>Read: Enabled</description>
51979 <description>Disable</description>
51986 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
51993 <description>Read: Disabled</description>
51998 <description>Read: Enabled</description>
52006 <description>Disable</description>
52013 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
52020 <description>Read: Disabled</description>
52025 <description>Read: Enabled</description>
52033 <description>Disable</description>
52040 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
52047 <description>Read: Disabled</description>
52052 <description>Read: Enabled</description>
52060 <description>Disable</description>
52067 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
52074 <description>Read: Disabled</description>
52079 <description>Read: Enabled</description>
52087 <description>Disable</description>
52094 <description>Write '1' to disable interrupt for event COMPARE[8]</description>
52101 <description>Read: Disabled</description>
52106 <description>Read: Enabled</description>
52114 <description>Disable</description>
52121 <description>Write '1' to disable interrupt for event COMPARE[9]</description>
52128 <description>Read: Disabled</description>
52133 <description>Read: Enabled</description>
52141 <description>Disable</description>
52148 <description>Write '1' to disable interrupt for event COMPARE[10]</description>
52155 <description>Read: Disabled</description>
52160 <description>Read: Enabled</description>
52168 <description>Disable</description>
52175 <description>Write '1' to disable interrupt for event COMPARE[11]</description>
52182 <description>Read: Disabled</description>
52187 <description>Read: Enabled</description>
52195 <description>Disable</description>
52202 <description>Write '1' to disable interrupt for event COMPARE[12]</description>
52209 <description>Read: Disabled</description>
52214 <description>Read: Enabled</description>
52222 <description>Disable</description>
52229 <description>Write '1' to disable interrupt for event COMPARE[13]</description>
52236 <description>Read: Disabled</description>
52241 <description>Read: Enabled</description>
52249 <description>Disable</description>
52256 <description>Write '1' to disable interrupt for event COMPARE[14]</description>
52263 <description>Read: Disabled</description>
52268 <description>Read: Enabled</description>
52276 <description>Disable</description>
52283 <description>Write '1' to disable interrupt for event COMPARE[15]</description>
52290 <description>Read: Disabled</description>
52295 <description>Read: Enabled</description>
52303 <description>Disable</description>
52310 <description>Write '1' to disable interrupt for event RTCOMPARESYNC</description>
52317 <description>Read: Disabled</description>
52322 <description>Read: Enabled</description>
52330 <description>Disable</description>
52337 <description>Write '1' to disable interrupt for event SYSCOUNTERVALID</description>
52344 <description>Read: Disabled</description>
52349 <description>Read: Enabled</description>
52357 <description>Disable</description>
52364 <description>Write '1' to disable interrupt for event PWMPERIODEND</description>
52371 <description>Read: Disabled</description>
52376 <description>Read: Enabled</description>
52384 <description>Disable</description>
52393 <description>Pending interrupts</description>
52401 <description>Read pending status of interrupt for event COMPARE[0]</description>
52408 <description>Read: Not pending</description>
52413 <description>Read: Pending</description>
52420 <description>Read pending status of interrupt for event COMPARE[1]</description>
52427 <description>Read: Not pending</description>
52432 <description>Read: Pending</description>
52439 <description>Read pending status of interrupt for event COMPARE[2]</description>
52446 <description>Read: Not pending</description>
52451 <description>Read: Pending</description>
52458 <description>Read pending status of interrupt for event COMPARE[3]</description>
52465 <description>Read: Not pending</description>
52470 <description>Read: Pending</description>
52477 <description>Read pending status of interrupt for event COMPARE[4]</description>
52484 <description>Read: Not pending</description>
52489 <description>Read: Pending</description>
52496 <description>Read pending status of interrupt for event COMPARE[5]</description>
52503 <description>Read: Not pending</description>
52508 <description>Read: Pending</description>
52515 <description>Read pending status of interrupt for event COMPARE[6]</description>
52522 <description>Read: Not pending</description>
52527 <description>Read: Pending</description>
52534 <description>Read pending status of interrupt for event COMPARE[7]</description>
52541 <description>Read: Not pending</description>
52546 <description>Read: Pending</description>
52553 <description>Read pending status of interrupt for event COMPARE[8]</description>
52560 <description>Read: Not pending</description>
52565 <description>Read: Pending</description>
52572 <description>Read pending status of interrupt for event COMPARE[9]</description>
52579 <description>Read: Not pending</description>
52584 <description>Read: Pending</description>
52591 <description>Read pending status of interrupt for event COMPARE[10]</description>
52598 <description>Read: Not pending</description>
52603 <description>Read: Pending</description>
52610 <description>Read pending status of interrupt for event COMPARE[11]</description>
52617 <description>Read: Not pending</description>
52622 <description>Read: Pending</description>
52629 <description>Read pending status of interrupt for event COMPARE[12]</description>
52636 <description>Read: Not pending</description>
52641 <description>Read: Pending</description>
52648 <description>Read pending status of interrupt for event COMPARE[13]</description>
52655 <description>Read: Not pending</description>
52660 <description>Read: Pending</description>
52667 <description>Read pending status of interrupt for event COMPARE[14]</description>
52674 <description>Read: Not pending</description>
52679 <description>Read: Pending</description>
52686 <description>Read pending status of interrupt for event COMPARE[15]</description>
52693 <description>Read: Not pending</description>
52698 <description>Read: Pending</description>
52705 <description>Read pending status of interrupt for event RTCOMPARESYNC</description>
52712 <description>Read: Not pending</description>
52717 <description>Read: Pending</description>
52724 <description>Read pending status of interrupt for event SYSCOUNTERVALID</description>
52731 <description>Read: Not pending</description>
52736 <description>Read: Pending</description>
52743 <description>Read pending status of interrupt for event PWMPERIODEND</description>
52750 <description>Read: Not pending</description>
52755 <description>Read: Pending</description>
52764 <description>Enable or disable interrupt</description>
52772 <description>Enable or disable interrupt for event COMPARE[0]</description>
52778 <description>Disable</description>
52783 <description>Enable</description>
52790 <description>Enable or disable interrupt for event COMPARE[1]</description>
52796 <description>Disable</description>
52801 <description>Enable</description>
52808 <description>Enable or disable interrupt for event COMPARE[2]</description>
52814 <description>Disable</description>
52819 <description>Enable</description>
52826 <description>Enable or disable interrupt for event COMPARE[3]</description>
52832 <description>Disable</description>
52837 <description>Enable</description>
52844 <description>Enable or disable interrupt for event COMPARE[4]</description>
52850 <description>Disable</description>
52855 <description>Enable</description>
52862 <description>Enable or disable interrupt for event COMPARE[5]</description>
52868 <description>Disable</description>
52873 <description>Enable</description>
52880 <description>Enable or disable interrupt for event COMPARE[6]</description>
52886 <description>Disable</description>
52891 <description>Enable</description>
52898 <description>Enable or disable interrupt for event COMPARE[7]</description>
52904 <description>Disable</description>
52909 <description>Enable</description>
52916 <description>Enable or disable interrupt for event COMPARE[8]</description>
52922 <description>Disable</description>
52927 <description>Enable</description>
52934 <description>Enable or disable interrupt for event COMPARE[9]</description>
52940 <description>Disable</description>
52945 <description>Enable</description>
52952 <description>Enable or disable interrupt for event COMPARE[10]</description>
52958 <description>Disable</description>
52963 <description>Enable</description>
52970 <description>Enable or disable interrupt for event COMPARE[11]</description>
52976 <description>Disable</description>
52981 <description>Enable</description>
52988 <description>Enable or disable interrupt for event COMPARE[12]</description>
52994 <description>Disable</description>
52999 <description>Enable</description>
53006 <description>Enable or disable interrupt for event COMPARE[13]</description>
53012 <description>Disable</description>
53017 <description>Enable</description>
53024 <description>Enable or disable interrupt for event COMPARE[14]</description>
53030 <description>Disable</description>
53035 <description>Enable</description>
53042 <description>Enable or disable interrupt for event COMPARE[15]</description>
53048 <description>Disable</description>
53053 <description>Enable</description>
53060 <description>Enable or disable interrupt for event RTCOMPARESYNC</description>
53066 <description>Disable</description>
53071 <description>Enable</description>
53078 <description>Enable or disable interrupt for event SYSCOUNTERVALID</description>
53084 <description>Disable</description>
53089 <description>Enable</description>
53096 <description>Enable or disable interrupt for event PWMPERIODEND</description>
53102 <description>Disable</description>
53107 <description>Enable</description>
53116 <description>Enable interrupt</description>
53124 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
53131 <description>Read: Disabled</description>
53136 <description>Read: Enabled</description>
53144 <description>Enable</description>
53151 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
53158 <description>Read: Disabled</description>
53163 <description>Read: Enabled</description>
53171 <description>Enable</description>
53178 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
53185 <description>Read: Disabled</description>
53190 <description>Read: Enabled</description>
53198 <description>Enable</description>
53205 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
53212 <description>Read: Disabled</description>
53217 <description>Read: Enabled</description>
53225 <description>Enable</description>
53232 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
53239 <description>Read: Disabled</description>
53244 <description>Read: Enabled</description>
53252 <description>Enable</description>
53259 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
53266 <description>Read: Disabled</description>
53271 <description>Read: Enabled</description>
53279 <description>Enable</description>
53286 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
53293 <description>Read: Disabled</description>
53298 <description>Read: Enabled</description>
53306 <description>Enable</description>
53313 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
53320 <description>Read: Disabled</description>
53325 <description>Read: Enabled</description>
53333 <description>Enable</description>
53340 <description>Write '1' to enable interrupt for event COMPARE[8]</description>
53347 <description>Read: Disabled</description>
53352 <description>Read: Enabled</description>
53360 <description>Enable</description>
53367 <description>Write '1' to enable interrupt for event COMPARE[9]</description>
53374 <description>Read: Disabled</description>
53379 <description>Read: Enabled</description>
53387 <description>Enable</description>
53394 <description>Write '1' to enable interrupt for event COMPARE[10]</description>
53401 <description>Read: Disabled</description>
53406 <description>Read: Enabled</description>
53414 <description>Enable</description>
53421 <description>Write '1' to enable interrupt for event COMPARE[11]</description>
53428 <description>Read: Disabled</description>
53433 <description>Read: Enabled</description>
53441 <description>Enable</description>
53448 <description>Write '1' to enable interrupt for event COMPARE[12]</description>
53455 <description>Read: Disabled</description>
53460 <description>Read: Enabled</description>
53468 <description>Enable</description>
53475 <description>Write '1' to enable interrupt for event COMPARE[13]</description>
53482 <description>Read: Disabled</description>
53487 <description>Read: Enabled</description>
53495 <description>Enable</description>
53502 <description>Write '1' to enable interrupt for event COMPARE[14]</description>
53509 <description>Read: Disabled</description>
53514 <description>Read: Enabled</description>
53522 <description>Enable</description>
53529 <description>Write '1' to enable interrupt for event COMPARE[15]</description>
53536 <description>Read: Disabled</description>
53541 <description>Read: Enabled</description>
53549 <description>Enable</description>
53556 <description>Write '1' to enable interrupt for event RTCOMPARESYNC</description>
53563 <description>Read: Disabled</description>
53568 <description>Read: Enabled</description>
53576 <description>Enable</description>
53583 <description>Write '1' to enable interrupt for event SYSCOUNTERVALID</description>
53590 <description>Read: Disabled</description>
53595 <description>Read: Enabled</description>
53603 <description>Enable</description>
53610 <description>Write '1' to enable interrupt for event PWMPERIODEND</description>
53617 <description>Read: Disabled</description>
53622 <description>Read: Enabled</description>
53630 <description>Enable</description>
53639 <description>Disable interrupt</description>
53647 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
53654 <description>Read: Disabled</description>
53659 <description>Read: Enabled</description>
53667 <description>Disable</description>
53674 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
53681 <description>Read: Disabled</description>
53686 <description>Read: Enabled</description>
53694 <description>Disable</description>
53701 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
53708 <description>Read: Disabled</description>
53713 <description>Read: Enabled</description>
53721 <description>Disable</description>
53728 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
53735 <description>Read: Disabled</description>
53740 <description>Read: Enabled</description>
53748 <description>Disable</description>
53755 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
53762 <description>Read: Disabled</description>
53767 <description>Read: Enabled</description>
53775 <description>Disable</description>
53782 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
53789 <description>Read: Disabled</description>
53794 <description>Read: Enabled</description>
53802 <description>Disable</description>
53809 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
53816 <description>Read: Disabled</description>
53821 <description>Read: Enabled</description>
53829 <description>Disable</description>
53836 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
53843 <description>Read: Disabled</description>
53848 <description>Read: Enabled</description>
53856 <description>Disable</description>
53863 <description>Write '1' to disable interrupt for event COMPARE[8]</description>
53870 <description>Read: Disabled</description>
53875 <description>Read: Enabled</description>
53883 <description>Disable</description>
53890 <description>Write '1' to disable interrupt for event COMPARE[9]</description>
53897 <description>Read: Disabled</description>
53902 <description>Read: Enabled</description>
53910 <description>Disable</description>
53917 <description>Write '1' to disable interrupt for event COMPARE[10]</description>
53924 <description>Read: Disabled</description>
53929 <description>Read: Enabled</description>
53937 <description>Disable</description>
53944 <description>Write '1' to disable interrupt for event COMPARE[11]</description>
53951 <description>Read: Disabled</description>
53956 <description>Read: Enabled</description>
53964 <description>Disable</description>
53971 <description>Write '1' to disable interrupt for event COMPARE[12]</description>
53978 <description>Read: Disabled</description>
53983 <description>Read: Enabled</description>
53991 <description>Disable</description>
53998 <description>Write '1' to disable interrupt for event COMPARE[13]</description>
54005 <description>Read: Disabled</description>
54010 <description>Read: Enabled</description>
54018 <description>Disable</description>
54025 <description>Write '1' to disable interrupt for event COMPARE[14]</description>
54032 <description>Read: Disabled</description>
54037 <description>Read: Enabled</description>
54045 <description>Disable</description>
54052 <description>Write '1' to disable interrupt for event COMPARE[15]</description>
54059 <description>Read: Disabled</description>
54064 <description>Read: Enabled</description>
54072 <description>Disable</description>
54079 <description>Write '1' to disable interrupt for event RTCOMPARESYNC</description>
54086 <description>Read: Disabled</description>
54091 <description>Read: Enabled</description>
54099 <description>Disable</description>
54106 <description>Write '1' to disable interrupt for event SYSCOUNTERVALID</description>
54113 <description>Read: Disabled</description>
54118 <description>Read: Enabled</description>
54126 <description>Disable</description>
54133 <description>Write '1' to disable interrupt for event PWMPERIODEND</description>
54140 <description>Read: Disabled</description>
54145 <description>Read: Enabled</description>
54153 <description>Disable</description>
54162 <description>Pending interrupts</description>
54170 <description>Read pending status of interrupt for event COMPARE[0]</description>
54177 <description>Read: Not pending</description>
54182 <description>Read: Pending</description>
54189 <description>Read pending status of interrupt for event COMPARE[1]</description>
54196 <description>Read: Not pending</description>
54201 <description>Read: Pending</description>
54208 <description>Read pending status of interrupt for event COMPARE[2]</description>
54215 <description>Read: Not pending</description>
54220 <description>Read: Pending</description>
54227 <description>Read pending status of interrupt for event COMPARE[3]</description>
54234 <description>Read: Not pending</description>
54239 <description>Read: Pending</description>
54246 <description>Read pending status of interrupt for event COMPARE[4]</description>
54253 <description>Read: Not pending</description>
54258 <description>Read: Pending</description>
54265 <description>Read pending status of interrupt for event COMPARE[5]</description>
54272 <description>Read: Not pending</description>
54277 <description>Read: Pending</description>
54284 <description>Read pending status of interrupt for event COMPARE[6]</description>
54291 <description>Read: Not pending</description>
54296 <description>Read: Pending</description>
54303 <description>Read pending status of interrupt for event COMPARE[7]</description>
54310 <description>Read: Not pending</description>
54315 <description>Read: Pending</description>
54322 <description>Read pending status of interrupt for event COMPARE[8]</description>
54329 <description>Read: Not pending</description>
54334 <description>Read: Pending</description>
54341 <description>Read pending status of interrupt for event COMPARE[9]</description>
54348 <description>Read: Not pending</description>
54353 <description>Read: Pending</description>
54360 <description>Read pending status of interrupt for event COMPARE[10]</description>
54367 <description>Read: Not pending</description>
54372 <description>Read: Pending</description>
54379 <description>Read pending status of interrupt for event COMPARE[11]</description>
54386 <description>Read: Not pending</description>
54391 <description>Read: Pending</description>
54398 <description>Read pending status of interrupt for event COMPARE[12]</description>
54405 <description>Read: Not pending</description>
54410 <description>Read: Pending</description>
54417 <description>Read pending status of interrupt for event COMPARE[13]</description>
54424 <description>Read: Not pending</description>
54429 <description>Read: Pending</description>
54436 <description>Read pending status of interrupt for event COMPARE[14]</description>
54443 <description>Read: Not pending</description>
54448 <description>Read: Pending</description>
54455 <description>Read pending status of interrupt for event COMPARE[15]</description>
54462 <description>Read: Not pending</description>
54467 <description>Read: Pending</description>
54474 <description>Read pending status of interrupt for event RTCOMPARESYNC</description>
54481 <description>Read: Not pending</description>
54486 <description>Read: Pending</description>
54493 <description>Read pending status of interrupt for event SYSCOUNTERVALID</description>
54500 <description>Read: Not pending</description>
54505 <description>Read: Pending</description>
54512 <description>Read pending status of interrupt for event PWMPERIODEND</description>
54519 <description>Read: Not pending</description>
54524 <description>Read: Pending</description>
54533 <description>Enable or disable interrupt</description>
54541 <description>Enable or disable interrupt for event COMPARE[0]</description>
54547 <description>Disable</description>
54552 <description>Enable</description>
54559 <description>Enable or disable interrupt for event COMPARE[1]</description>
54565 <description>Disable</description>
54570 <description>Enable</description>
54577 <description>Enable or disable interrupt for event COMPARE[2]</description>
54583 <description>Disable</description>
54588 <description>Enable</description>
54595 <description>Enable or disable interrupt for event COMPARE[3]</description>
54601 <description>Disable</description>
54606 <description>Enable</description>
54613 <description>Enable or disable interrupt for event COMPARE[4]</description>
54619 <description>Disable</description>
54624 <description>Enable</description>
54631 <description>Enable or disable interrupt for event COMPARE[5]</description>
54637 <description>Disable</description>
54642 <description>Enable</description>
54649 <description>Enable or disable interrupt for event COMPARE[6]</description>
54655 <description>Disable</description>
54660 <description>Enable</description>
54667 <description>Enable or disable interrupt for event COMPARE[7]</description>
54673 <description>Disable</description>
54678 <description>Enable</description>
54685 <description>Enable or disable interrupt for event COMPARE[8]</description>
54691 <description>Disable</description>
54696 <description>Enable</description>
54703 <description>Enable or disable interrupt for event COMPARE[9]</description>
54709 <description>Disable</description>
54714 <description>Enable</description>
54721 <description>Enable or disable interrupt for event COMPARE[10]</description>
54727 <description>Disable</description>
54732 <description>Enable</description>
54739 <description>Enable or disable interrupt for event COMPARE[11]</description>
54745 <description>Disable</description>
54750 <description>Enable</description>
54757 <description>Enable or disable interrupt for event COMPARE[12]</description>
54763 <description>Disable</description>
54768 <description>Enable</description>
54775 <description>Enable or disable interrupt for event COMPARE[13]</description>
54781 <description>Disable</description>
54786 <description>Enable</description>
54793 <description>Enable or disable interrupt for event COMPARE[14]</description>
54799 <description>Disable</description>
54804 <description>Enable</description>
54811 <description>Enable or disable interrupt for event COMPARE[15]</description>
54817 <description>Disable</description>
54822 <description>Enable</description>
54829 <description>Enable or disable interrupt for event RTCOMPARESYNC</description>
54835 <description>Disable</description>
54840 <description>Enable</description>
54847 <description>Enable or disable interrupt for event SYSCOUNTERVALID</description>
54853 <description>Disable</description>
54858 <description>Enable</description>
54865 <description>Enable or disable interrupt for event PWMPERIODEND</description>
54871 <description>Disable</description>
54876 <description>Enable</description>
54885 <description>Enable interrupt</description>
54893 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
54900 <description>Read: Disabled</description>
54905 <description>Read: Enabled</description>
54913 <description>Enable</description>
54920 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
54927 <description>Read: Disabled</description>
54932 <description>Read: Enabled</description>
54940 <description>Enable</description>
54947 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
54954 <description>Read: Disabled</description>
54959 <description>Read: Enabled</description>
54967 <description>Enable</description>
54974 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
54981 <description>Read: Disabled</description>
54986 <description>Read: Enabled</description>
54994 <description>Enable</description>
55001 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
55008 <description>Read: Disabled</description>
55013 <description>Read: Enabled</description>
55021 <description>Enable</description>
55028 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
55035 <description>Read: Disabled</description>
55040 <description>Read: Enabled</description>
55048 <description>Enable</description>
55055 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
55062 <description>Read: Disabled</description>
55067 <description>Read: Enabled</description>
55075 <description>Enable</description>
55082 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
55089 <description>Read: Disabled</description>
55094 <description>Read: Enabled</description>
55102 <description>Enable</description>
55109 <description>Write '1' to enable interrupt for event COMPARE[8]</description>
55116 <description>Read: Disabled</description>
55121 <description>Read: Enabled</description>
55129 <description>Enable</description>
55136 <description>Write '1' to enable interrupt for event COMPARE[9]</description>
55143 <description>Read: Disabled</description>
55148 <description>Read: Enabled</description>
55156 <description>Enable</description>
55163 <description>Write '1' to enable interrupt for event COMPARE[10]</description>
55170 <description>Read: Disabled</description>
55175 <description>Read: Enabled</description>
55183 <description>Enable</description>
55190 <description>Write '1' to enable interrupt for event COMPARE[11]</description>
55197 <description>Read: Disabled</description>
55202 <description>Read: Enabled</description>
55210 <description>Enable</description>
55217 <description>Write '1' to enable interrupt for event COMPARE[12]</description>
55224 <description>Read: Disabled</description>
55229 <description>Read: Enabled</description>
55237 <description>Enable</description>
55244 <description>Write '1' to enable interrupt for event COMPARE[13]</description>
55251 <description>Read: Disabled</description>
55256 <description>Read: Enabled</description>
55264 <description>Enable</description>
55271 <description>Write '1' to enable interrupt for event COMPARE[14]</description>
55278 <description>Read: Disabled</description>
55283 <description>Read: Enabled</description>
55291 <description>Enable</description>
55298 <description>Write '1' to enable interrupt for event COMPARE[15]</description>
55305 <description>Read: Disabled</description>
55310 <description>Read: Enabled</description>
55318 <description>Enable</description>
55325 <description>Write '1' to enable interrupt for event RTCOMPARESYNC</description>
55332 <description>Read: Disabled</description>
55337 <description>Read: Enabled</description>
55345 <description>Enable</description>
55352 <description>Write '1' to enable interrupt for event SYSCOUNTERVALID</description>
55359 <description>Read: Disabled</description>
55364 <description>Read: Enabled</description>
55372 <description>Enable</description>
55379 <description>Write '1' to enable interrupt for event PWMPERIODEND</description>
55386 <description>Read: Disabled</description>
55391 <description>Read: Enabled</description>
55399 <description>Enable</description>
55408 <description>Disable interrupt</description>
55416 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
55423 <description>Read: Disabled</description>
55428 <description>Read: Enabled</description>
55436 <description>Disable</description>
55443 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
55450 <description>Read: Disabled</description>
55455 <description>Read: Enabled</description>
55463 <description>Disable</description>
55470 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
55477 <description>Read: Disabled</description>
55482 <description>Read: Enabled</description>
55490 <description>Disable</description>
55497 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
55504 <description>Read: Disabled</description>
55509 <description>Read: Enabled</description>
55517 <description>Disable</description>
55524 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
55531 <description>Read: Disabled</description>
55536 <description>Read: Enabled</description>
55544 <description>Disable</description>
55551 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
55558 <description>Read: Disabled</description>
55563 <description>Read: Enabled</description>
55571 <description>Disable</description>
55578 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
55585 <description>Read: Disabled</description>
55590 <description>Read: Enabled</description>
55598 <description>Disable</description>
55605 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
55612 <description>Read: Disabled</description>
55617 <description>Read: Enabled</description>
55625 <description>Disable</description>
55632 <description>Write '1' to disable interrupt for event COMPARE[8]</description>
55639 <description>Read: Disabled</description>
55644 <description>Read: Enabled</description>
55652 <description>Disable</description>
55659 <description>Write '1' to disable interrupt for event COMPARE[9]</description>
55666 <description>Read: Disabled</description>
55671 <description>Read: Enabled</description>
55679 <description>Disable</description>
55686 <description>Write '1' to disable interrupt for event COMPARE[10]</description>
55693 <description>Read: Disabled</description>
55698 <description>Read: Enabled</description>
55706 <description>Disable</description>
55713 <description>Write '1' to disable interrupt for event COMPARE[11]</description>
55720 <description>Read: Disabled</description>
55725 <description>Read: Enabled</description>
55733 <description>Disable</description>
55740 <description>Write '1' to disable interrupt for event COMPARE[12]</description>
55747 <description>Read: Disabled</description>
55752 <description>Read: Enabled</description>
55760 <description>Disable</description>
55767 <description>Write '1' to disable interrupt for event COMPARE[13]</description>
55774 <description>Read: Disabled</description>
55779 <description>Read: Enabled</description>
55787 <description>Disable</description>
55794 <description>Write '1' to disable interrupt for event COMPARE[14]</description>
55801 <description>Read: Disabled</description>
55806 <description>Read: Enabled</description>
55814 <description>Disable</description>
55821 <description>Write '1' to disable interrupt for event COMPARE[15]</description>
55828 <description>Read: Disabled</description>
55833 <description>Read: Enabled</description>
55841 <description>Disable</description>
55848 <description>Write '1' to disable interrupt for event RTCOMPARESYNC</description>
55855 <description>Read: Disabled</description>
55860 <description>Read: Enabled</description>
55868 <description>Disable</description>
55875 <description>Write '1' to disable interrupt for event SYSCOUNTERVALID</description>
55882 <description>Read: Disabled</description>
55887 <description>Read: Enabled</description>
55895 <description>Disable</description>
55902 <description>Write '1' to disable interrupt for event PWMPERIODEND</description>
55909 <description>Read: Disabled</description>
55914 <description>Read: Enabled</description>
55922 <description>Disable</description>
55931 <description>Pending interrupts</description>
55939 <description>Read pending status of interrupt for event COMPARE[0]</description>
55946 <description>Read: Not pending</description>
55951 <description>Read: Pending</description>
55958 <description>Read pending status of interrupt for event COMPARE[1]</description>
55965 <description>Read: Not pending</description>
55970 <description>Read: Pending</description>
55977 <description>Read pending status of interrupt for event COMPARE[2]</description>
55984 <description>Read: Not pending</description>
55989 <description>Read: Pending</description>
55996 <description>Read pending status of interrupt for event COMPARE[3]</description>
56003 <description>Read: Not pending</description>
56008 <description>Read: Pending</description>
56015 <description>Read pending status of interrupt for event COMPARE[4]</description>
56022 <description>Read: Not pending</description>
56027 <description>Read: Pending</description>
56034 <description>Read pending status of interrupt for event COMPARE[5]</description>
56041 <description>Read: Not pending</description>
56046 <description>Read: Pending</description>
56053 <description>Read pending status of interrupt for event COMPARE[6]</description>
56060 <description>Read: Not pending</description>
56065 <description>Read: Pending</description>
56072 <description>Read pending status of interrupt for event COMPARE[7]</description>
56079 <description>Read: Not pending</description>
56084 <description>Read: Pending</description>
56091 <description>Read pending status of interrupt for event COMPARE[8]</description>
56098 <description>Read: Not pending</description>
56103 <description>Read: Pending</description>
56110 <description>Read pending status of interrupt for event COMPARE[9]</description>
56117 <description>Read: Not pending</description>
56122 <description>Read: Pending</description>
56129 <description>Read pending status of interrupt for event COMPARE[10]</description>
56136 <description>Read: Not pending</description>
56141 <description>Read: Pending</description>
56148 <description>Read pending status of interrupt for event COMPARE[11]</description>
56155 <description>Read: Not pending</description>
56160 <description>Read: Pending</description>
56167 <description>Read pending status of interrupt for event COMPARE[12]</description>
56174 <description>Read: Not pending</description>
56179 <description>Read: Pending</description>
56186 <description>Read pending status of interrupt for event COMPARE[13]</description>
56193 <description>Read: Not pending</description>
56198 <description>Read: Pending</description>
56205 <description>Read pending status of interrupt for event COMPARE[14]</description>
56212 <description>Read: Not pending</description>
56217 <description>Read: Pending</description>
56224 <description>Read pending status of interrupt for event COMPARE[15]</description>
56231 <description>Read: Not pending</description>
56236 <description>Read: Pending</description>
56243 <description>Read pending status of interrupt for event RTCOMPARESYNC</description>
56250 <description>Read: Not pending</description>
56255 <description>Read: Pending</description>
56262 <description>Read pending status of interrupt for event SYSCOUNTERVALID</description>
56269 <description>Read: Not pending</description>
56274 <description>Read: Pending</description>
56281 <description>Read pending status of interrupt for event PWMPERIODEND</description>
56288 <description>Read: Not pending</description>
56293 <description>Read: Pending</description>
56302 <description>Enable or disable interrupt</description>
56310 <description>Enable or disable interrupt for event COMPARE[0]</description>
56316 <description>Disable</description>
56321 <description>Enable</description>
56328 <description>Enable or disable interrupt for event COMPARE[1]</description>
56334 <description>Disable</description>
56339 <description>Enable</description>
56346 <description>Enable or disable interrupt for event COMPARE[2]</description>
56352 <description>Disable</description>
56357 <description>Enable</description>
56364 <description>Enable or disable interrupt for event COMPARE[3]</description>
56370 <description>Disable</description>
56375 <description>Enable</description>
56382 <description>Enable or disable interrupt for event COMPARE[4]</description>
56388 <description>Disable</description>
56393 <description>Enable</description>
56400 <description>Enable or disable interrupt for event COMPARE[5]</description>
56406 <description>Disable</description>
56411 <description>Enable</description>
56418 <description>Enable or disable interrupt for event COMPARE[6]</description>
56424 <description>Disable</description>
56429 <description>Enable</description>
56436 <description>Enable or disable interrupt for event COMPARE[7]</description>
56442 <description>Disable</description>
56447 <description>Enable</description>
56454 <description>Enable or disable interrupt for event COMPARE[8]</description>
56460 <description>Disable</description>
56465 <description>Enable</description>
56472 <description>Enable or disable interrupt for event COMPARE[9]</description>
56478 <description>Disable</description>
56483 <description>Enable</description>
56490 <description>Enable or disable interrupt for event COMPARE[10]</description>
56496 <description>Disable</description>
56501 <description>Enable</description>
56508 <description>Enable or disable interrupt for event COMPARE[11]</description>
56514 <description>Disable</description>
56519 <description>Enable</description>
56526 <description>Enable or disable interrupt for event COMPARE[12]</description>
56532 <description>Disable</description>
56537 <description>Enable</description>
56544 <description>Enable or disable interrupt for event COMPARE[13]</description>
56550 <description>Disable</description>
56555 <description>Enable</description>
56562 <description>Enable or disable interrupt for event COMPARE[14]</description>
56568 <description>Disable</description>
56573 <description>Enable</description>
56580 <description>Enable or disable interrupt for event COMPARE[15]</description>
56586 <description>Disable</description>
56591 <description>Enable</description>
56598 <description>Enable or disable interrupt for event RTCOMPARESYNC</description>
56604 <description>Disable</description>
56609 <description>Enable</description>
56616 <description>Enable or disable interrupt for event SYSCOUNTERVALID</description>
56622 <description>Disable</description>
56627 <description>Enable</description>
56634 <description>Enable or disable interrupt for event PWMPERIODEND</description>
56640 <description>Disable</description>
56645 <description>Enable</description>
56654 <description>Enable interrupt</description>
56662 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
56669 <description>Read: Disabled</description>
56674 <description>Read: Enabled</description>
56682 <description>Enable</description>
56689 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
56696 <description>Read: Disabled</description>
56701 <description>Read: Enabled</description>
56709 <description>Enable</description>
56716 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
56723 <description>Read: Disabled</description>
56728 <description>Read: Enabled</description>
56736 <description>Enable</description>
56743 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
56750 <description>Read: Disabled</description>
56755 <description>Read: Enabled</description>
56763 <description>Enable</description>
56770 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
56777 <description>Read: Disabled</description>
56782 <description>Read: Enabled</description>
56790 <description>Enable</description>
56797 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
56804 <description>Read: Disabled</description>
56809 <description>Read: Enabled</description>
56817 <description>Enable</description>
56824 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
56831 <description>Read: Disabled</description>
56836 <description>Read: Enabled</description>
56844 <description>Enable</description>
56851 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
56858 <description>Read: Disabled</description>
56863 <description>Read: Enabled</description>
56871 <description>Enable</description>
56878 <description>Write '1' to enable interrupt for event COMPARE[8]</description>
56885 <description>Read: Disabled</description>
56890 <description>Read: Enabled</description>
56898 <description>Enable</description>
56905 <description>Write '1' to enable interrupt for event COMPARE[9]</description>
56912 <description>Read: Disabled</description>
56917 <description>Read: Enabled</description>
56925 <description>Enable</description>
56932 <description>Write '1' to enable interrupt for event COMPARE[10]</description>
56939 <description>Read: Disabled</description>
56944 <description>Read: Enabled</description>
56952 <description>Enable</description>
56959 <description>Write '1' to enable interrupt for event COMPARE[11]</description>
56966 <description>Read: Disabled</description>
56971 <description>Read: Enabled</description>
56979 <description>Enable</description>
56986 <description>Write '1' to enable interrupt for event COMPARE[12]</description>
56993 <description>Read: Disabled</description>
56998 <description>Read: Enabled</description>
57006 <description>Enable</description>
57013 <description>Write '1' to enable interrupt for event COMPARE[13]</description>
57020 <description>Read: Disabled</description>
57025 <description>Read: Enabled</description>
57033 <description>Enable</description>
57040 <description>Write '1' to enable interrupt for event COMPARE[14]</description>
57047 <description>Read: Disabled</description>
57052 <description>Read: Enabled</description>
57060 <description>Enable</description>
57067 <description>Write '1' to enable interrupt for event COMPARE[15]</description>
57074 <description>Read: Disabled</description>
57079 <description>Read: Enabled</description>
57087 <description>Enable</description>
57094 <description>Write '1' to enable interrupt for event RTCOMPARESYNC</description>
57101 <description>Read: Disabled</description>
57106 <description>Read: Enabled</description>
57114 <description>Enable</description>
57121 <description>Write '1' to enable interrupt for event SYSCOUNTERVALID</description>
57128 <description>Read: Disabled</description>
57133 <description>Read: Enabled</description>
57141 <description>Enable</description>
57148 <description>Write '1' to enable interrupt for event PWMPERIODEND</description>
57155 <description>Read: Disabled</description>
57160 <description>Read: Enabled</description>
57168 <description>Enable</description>
57177 <description>Disable interrupt</description>
57185 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
57192 <description>Read: Disabled</description>
57197 <description>Read: Enabled</description>
57205 <description>Disable</description>
57212 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
57219 <description>Read: Disabled</description>
57224 <description>Read: Enabled</description>
57232 <description>Disable</description>
57239 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
57246 <description>Read: Disabled</description>
57251 <description>Read: Enabled</description>
57259 <description>Disable</description>
57266 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
57273 <description>Read: Disabled</description>
57278 <description>Read: Enabled</description>
57286 <description>Disable</description>
57293 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
57300 <description>Read: Disabled</description>
57305 <description>Read: Enabled</description>
57313 <description>Disable</description>
57320 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
57327 <description>Read: Disabled</description>
57332 <description>Read: Enabled</description>
57340 <description>Disable</description>
57347 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
57354 <description>Read: Disabled</description>
57359 <description>Read: Enabled</description>
57367 <description>Disable</description>
57374 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
57381 <description>Read: Disabled</description>
57386 <description>Read: Enabled</description>
57394 <description>Disable</description>
57401 <description>Write '1' to disable interrupt for event COMPARE[8]</description>
57408 <description>Read: Disabled</description>
57413 <description>Read: Enabled</description>
57421 <description>Disable</description>
57428 <description>Write '1' to disable interrupt for event COMPARE[9]</description>
57435 <description>Read: Disabled</description>
57440 <description>Read: Enabled</description>
57448 <description>Disable</description>
57455 <description>Write '1' to disable interrupt for event COMPARE[10]</description>
57462 <description>Read: Disabled</description>
57467 <description>Read: Enabled</description>
57475 <description>Disable</description>
57482 <description>Write '1' to disable interrupt for event COMPARE[11]</description>
57489 <description>Read: Disabled</description>
57494 <description>Read: Enabled</description>
57502 <description>Disable</description>
57509 <description>Write '1' to disable interrupt for event COMPARE[12]</description>
57516 <description>Read: Disabled</description>
57521 <description>Read: Enabled</description>
57529 <description>Disable</description>
57536 <description>Write '1' to disable interrupt for event COMPARE[13]</description>
57543 <description>Read: Disabled</description>
57548 <description>Read: Enabled</description>
57556 <description>Disable</description>
57563 <description>Write '1' to disable interrupt for event COMPARE[14]</description>
57570 <description>Read: Disabled</description>
57575 <description>Read: Enabled</description>
57583 <description>Disable</description>
57590 <description>Write '1' to disable interrupt for event COMPARE[15]</description>
57597 <description>Read: Disabled</description>
57602 <description>Read: Enabled</description>
57610 <description>Disable</description>
57617 <description>Write '1' to disable interrupt for event RTCOMPARESYNC</description>
57624 <description>Read: Disabled</description>
57629 <description>Read: Enabled</description>
57637 <description>Disable</description>
57644 <description>Write '1' to disable interrupt for event SYSCOUNTERVALID</description>
57651 <description>Read: Disabled</description>
57656 <description>Read: Enabled</description>
57664 <description>Disable</description>
57671 <description>Write '1' to disable interrupt for event PWMPERIODEND</description>
57678 <description>Read: Disabled</description>
57683 <description>Read: Enabled</description>
57691 <description>Disable</description>
57700 <description>Pending interrupts</description>
57708 <description>Read pending status of interrupt for event COMPARE[0]</description>
57715 <description>Read: Not pending</description>
57720 <description>Read: Pending</description>
57727 <description>Read pending status of interrupt for event COMPARE[1]</description>
57734 <description>Read: Not pending</description>
57739 <description>Read: Pending</description>
57746 <description>Read pending status of interrupt for event COMPARE[2]</description>
57753 <description>Read: Not pending</description>
57758 <description>Read: Pending</description>
57765 <description>Read pending status of interrupt for event COMPARE[3]</description>
57772 <description>Read: Not pending</description>
57777 <description>Read: Pending</description>
57784 <description>Read pending status of interrupt for event COMPARE[4]</description>
57791 <description>Read: Not pending</description>
57796 <description>Read: Pending</description>
57803 <description>Read pending status of interrupt for event COMPARE[5]</description>
57810 <description>Read: Not pending</description>
57815 <description>Read: Pending</description>
57822 <description>Read pending status of interrupt for event COMPARE[6]</description>
57829 <description>Read: Not pending</description>
57834 <description>Read: Pending</description>
57841 <description>Read pending status of interrupt for event COMPARE[7]</description>
57848 <description>Read: Not pending</description>
57853 <description>Read: Pending</description>
57860 <description>Read pending status of interrupt for event COMPARE[8]</description>
57867 <description>Read: Not pending</description>
57872 <description>Read: Pending</description>
57879 <description>Read pending status of interrupt for event COMPARE[9]</description>
57886 <description>Read: Not pending</description>
57891 <description>Read: Pending</description>
57898 <description>Read pending status of interrupt for event COMPARE[10]</description>
57905 <description>Read: Not pending</description>
57910 <description>Read: Pending</description>
57917 <description>Read pending status of interrupt for event COMPARE[11]</description>
57924 <description>Read: Not pending</description>
57929 <description>Read: Pending</description>
57936 <description>Read pending status of interrupt for event COMPARE[12]</description>
57943 <description>Read: Not pending</description>
57948 <description>Read: Pending</description>
57955 <description>Read pending status of interrupt for event COMPARE[13]</description>
57962 <description>Read: Not pending</description>
57967 <description>Read: Pending</description>
57974 <description>Read pending status of interrupt for event COMPARE[14]</description>
57981 <description>Read: Not pending</description>
57986 <description>Read: Pending</description>
57993 <description>Read pending status of interrupt for event COMPARE[15]</description>
58000 <description>Read: Not pending</description>
58005 <description>Read: Pending</description>
58012 <description>Read pending status of interrupt for event RTCOMPARESYNC</description>
58019 <description>Read: Not pending</description>
58024 <description>Read: Pending</description>
58031 <description>Read pending status of interrupt for event SYSCOUNTERVALID</description>
58038 <description>Read: Not pending</description>
58043 <description>Read: Pending</description>
58050 <description>Read pending status of interrupt for event PWMPERIODEND</description>
58057 <description>Read: Not pending</description>
58062 <description>Read: Pending</description>
58071 <description>Enable or disable interrupt</description>
58079 <description>Enable or disable interrupt for event COMPARE[0]</description>
58085 <description>Disable</description>
58090 <description>Enable</description>
58097 <description>Enable or disable interrupt for event COMPARE[1]</description>
58103 <description>Disable</description>
58108 <description>Enable</description>
58115 <description>Enable or disable interrupt for event COMPARE[2]</description>
58121 <description>Disable</description>
58126 <description>Enable</description>
58133 <description>Enable or disable interrupt for event COMPARE[3]</description>
58139 <description>Disable</description>
58144 <description>Enable</description>
58151 <description>Enable or disable interrupt for event COMPARE[4]</description>
58157 <description>Disable</description>
58162 <description>Enable</description>
58169 <description>Enable or disable interrupt for event COMPARE[5]</description>
58175 <description>Disable</description>
58180 <description>Enable</description>
58187 <description>Enable or disable interrupt for event COMPARE[6]</description>
58193 <description>Disable</description>
58198 <description>Enable</description>
58205 <description>Enable or disable interrupt for event COMPARE[7]</description>
58211 <description>Disable</description>
58216 <description>Enable</description>
58223 <description>Enable or disable interrupt for event COMPARE[8]</description>
58229 <description>Disable</description>
58234 <description>Enable</description>
58241 <description>Enable or disable interrupt for event COMPARE[9]</description>
58247 <description>Disable</description>
58252 <description>Enable</description>
58259 <description>Enable or disable interrupt for event COMPARE[10]</description>
58265 <description>Disable</description>
58270 <description>Enable</description>
58277 <description>Enable or disable interrupt for event COMPARE[11]</description>
58283 <description>Disable</description>
58288 <description>Enable</description>
58295 <description>Enable or disable interrupt for event COMPARE[12]</description>
58301 <description>Disable</description>
58306 <description>Enable</description>
58313 <description>Enable or disable interrupt for event COMPARE[13]</description>
58319 <description>Disable</description>
58324 <description>Enable</description>
58331 <description>Enable or disable interrupt for event COMPARE[14]</description>
58337 <description>Disable</description>
58342 <description>Enable</description>
58349 <description>Enable or disable interrupt for event COMPARE[15]</description>
58355 <description>Disable</description>
58360 <description>Enable</description>
58367 <description>Enable or disable interrupt for event RTCOMPARESYNC</description>
58373 <description>Disable</description>
58378 <description>Enable</description>
58385 <description>Enable or disable interrupt for event SYSCOUNTERVALID</description>
58391 <description>Disable</description>
58396 <description>Enable</description>
58403 <description>Enable or disable interrupt for event PWMPERIODEND</description>
58409 <description>Disable</description>
58414 <description>Enable</description>
58423 <description>Enable interrupt</description>
58431 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
58438 <description>Read: Disabled</description>
58443 <description>Read: Enabled</description>
58451 <description>Enable</description>
58458 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
58465 <description>Read: Disabled</description>
58470 <description>Read: Enabled</description>
58478 <description>Enable</description>
58485 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
58492 <description>Read: Disabled</description>
58497 <description>Read: Enabled</description>
58505 <description>Enable</description>
58512 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
58519 <description>Read: Disabled</description>
58524 <description>Read: Enabled</description>
58532 <description>Enable</description>
58539 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
58546 <description>Read: Disabled</description>
58551 <description>Read: Enabled</description>
58559 <description>Enable</description>
58566 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
58573 <description>Read: Disabled</description>
58578 <description>Read: Enabled</description>
58586 <description>Enable</description>
58593 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
58600 <description>Read: Disabled</description>
58605 <description>Read: Enabled</description>
58613 <description>Enable</description>
58620 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
58627 <description>Read: Disabled</description>
58632 <description>Read: Enabled</description>
58640 <description>Enable</description>
58647 <description>Write '1' to enable interrupt for event COMPARE[8]</description>
58654 <description>Read: Disabled</description>
58659 <description>Read: Enabled</description>
58667 <description>Enable</description>
58674 <description>Write '1' to enable interrupt for event COMPARE[9]</description>
58681 <description>Read: Disabled</description>
58686 <description>Read: Enabled</description>
58694 <description>Enable</description>
58701 <description>Write '1' to enable interrupt for event COMPARE[10]</description>
58708 <description>Read: Disabled</description>
58713 <description>Read: Enabled</description>
58721 <description>Enable</description>
58728 <description>Write '1' to enable interrupt for event COMPARE[11]</description>
58735 <description>Read: Disabled</description>
58740 <description>Read: Enabled</description>
58748 <description>Enable</description>
58755 <description>Write '1' to enable interrupt for event COMPARE[12]</description>
58762 <description>Read: Disabled</description>
58767 <description>Read: Enabled</description>
58775 <description>Enable</description>
58782 <description>Write '1' to enable interrupt for event COMPARE[13]</description>
58789 <description>Read: Disabled</description>
58794 <description>Read: Enabled</description>
58802 <description>Enable</description>
58809 <description>Write '1' to enable interrupt for event COMPARE[14]</description>
58816 <description>Read: Disabled</description>
58821 <description>Read: Enabled</description>
58829 <description>Enable</description>
58836 <description>Write '1' to enable interrupt for event COMPARE[15]</description>
58843 <description>Read: Disabled</description>
58848 <description>Read: Enabled</description>
58856 <description>Enable</description>
58863 <description>Write '1' to enable interrupt for event RTCOMPARESYNC</description>
58870 <description>Read: Disabled</description>
58875 <description>Read: Enabled</description>
58883 <description>Enable</description>
58890 <description>Write '1' to enable interrupt for event SYSCOUNTERVALID</description>
58897 <description>Read: Disabled</description>
58902 <description>Read: Enabled</description>
58910 <description>Enable</description>
58917 <description>Write '1' to enable interrupt for event PWMPERIODEND</description>
58924 <description>Read: Disabled</description>
58929 <description>Read: Enabled</description>
58937 <description>Enable</description>
58946 <description>Disable interrupt</description>
58954 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
58961 <description>Read: Disabled</description>
58966 <description>Read: Enabled</description>
58974 <description>Disable</description>
58981 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
58988 <description>Read: Disabled</description>
58993 <description>Read: Enabled</description>
59001 <description>Disable</description>
59008 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
59015 <description>Read: Disabled</description>
59020 <description>Read: Enabled</description>
59028 <description>Disable</description>
59035 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
59042 <description>Read: Disabled</description>
59047 <description>Read: Enabled</description>
59055 <description>Disable</description>
59062 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
59069 <description>Read: Disabled</description>
59074 <description>Read: Enabled</description>
59082 <description>Disable</description>
59089 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
59096 <description>Read: Disabled</description>
59101 <description>Read: Enabled</description>
59109 <description>Disable</description>
59116 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
59123 <description>Read: Disabled</description>
59128 <description>Read: Enabled</description>
59136 <description>Disable</description>
59143 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
59150 <description>Read: Disabled</description>
59155 <description>Read: Enabled</description>
59163 <description>Disable</description>
59170 <description>Write '1' to disable interrupt for event COMPARE[8]</description>
59177 <description>Read: Disabled</description>
59182 <description>Read: Enabled</description>
59190 <description>Disable</description>
59197 <description>Write '1' to disable interrupt for event COMPARE[9]</description>
59204 <description>Read: Disabled</description>
59209 <description>Read: Enabled</description>
59217 <description>Disable</description>
59224 <description>Write '1' to disable interrupt for event COMPARE[10]</description>
59231 <description>Read: Disabled</description>
59236 <description>Read: Enabled</description>
59244 <description>Disable</description>
59251 <description>Write '1' to disable interrupt for event COMPARE[11]</description>
59258 <description>Read: Disabled</description>
59263 <description>Read: Enabled</description>
59271 <description>Disable</description>
59278 <description>Write '1' to disable interrupt for event COMPARE[12]</description>
59285 <description>Read: Disabled</description>
59290 <description>Read: Enabled</description>
59298 <description>Disable</description>
59305 <description>Write '1' to disable interrupt for event COMPARE[13]</description>
59312 <description>Read: Disabled</description>
59317 <description>Read: Enabled</description>
59325 <description>Disable</description>
59332 <description>Write '1' to disable interrupt for event COMPARE[14]</description>
59339 <description>Read: Disabled</description>
59344 <description>Read: Enabled</description>
59352 <description>Disable</description>
59359 <description>Write '1' to disable interrupt for event COMPARE[15]</description>
59366 <description>Read: Disabled</description>
59371 <description>Read: Enabled</description>
59379 <description>Disable</description>
59386 <description>Write '1' to disable interrupt for event RTCOMPARESYNC</description>
59393 <description>Read: Disabled</description>
59398 <description>Read: Enabled</description>
59406 <description>Disable</description>
59413 <description>Write '1' to disable interrupt for event SYSCOUNTERVALID</description>
59420 <description>Read: Disabled</description>
59425 <description>Read: Enabled</description>
59433 <description>Disable</description>
59440 <description>Write '1' to disable interrupt for event PWMPERIODEND</description>
59447 <description>Read: Disabled</description>
59452 <description>Read: Enabled</description>
59460 <description>Disable</description>
59469 <description>Pending interrupts</description>
59477 <description>Read pending status of interrupt for event COMPARE[0]</description>
59484 <description>Read: Not pending</description>
59489 <description>Read: Pending</description>
59496 <description>Read pending status of interrupt for event COMPARE[1]</description>
59503 <description>Read: Not pending</description>
59508 <description>Read: Pending</description>
59515 <description>Read pending status of interrupt for event COMPARE[2]</description>
59522 <description>Read: Not pending</description>
59527 <description>Read: Pending</description>
59534 <description>Read pending status of interrupt for event COMPARE[3]</description>
59541 <description>Read: Not pending</description>
59546 <description>Read: Pending</description>
59553 <description>Read pending status of interrupt for event COMPARE[4]</description>
59560 <description>Read: Not pending</description>
59565 <description>Read: Pending</description>
59572 <description>Read pending status of interrupt for event COMPARE[5]</description>
59579 <description>Read: Not pending</description>
59584 <description>Read: Pending</description>
59591 <description>Read pending status of interrupt for event COMPARE[6]</description>
59598 <description>Read: Not pending</description>
59603 <description>Read: Pending</description>
59610 <description>Read pending status of interrupt for event COMPARE[7]</description>
59617 <description>Read: Not pending</description>
59622 <description>Read: Pending</description>
59629 <description>Read pending status of interrupt for event COMPARE[8]</description>
59636 <description>Read: Not pending</description>
59641 <description>Read: Pending</description>
59648 <description>Read pending status of interrupt for event COMPARE[9]</description>
59655 <description>Read: Not pending</description>
59660 <description>Read: Pending</description>
59667 <description>Read pending status of interrupt for event COMPARE[10]</description>
59674 <description>Read: Not pending</description>
59679 <description>Read: Pending</description>
59686 <description>Read pending status of interrupt for event COMPARE[11]</description>
59693 <description>Read: Not pending</description>
59698 <description>Read: Pending</description>
59705 <description>Read pending status of interrupt for event COMPARE[12]</description>
59712 <description>Read: Not pending</description>
59717 <description>Read: Pending</description>
59724 <description>Read pending status of interrupt for event COMPARE[13]</description>
59731 <description>Read: Not pending</description>
59736 <description>Read: Pending</description>
59743 <description>Read pending status of interrupt for event COMPARE[14]</description>
59750 <description>Read: Not pending</description>
59755 <description>Read: Pending</description>
59762 <description>Read pending status of interrupt for event COMPARE[15]</description>
59769 <description>Read: Not pending</description>
59774 <description>Read: Pending</description>
59781 <description>Read pending status of interrupt for event RTCOMPARESYNC</description>
59788 <description>Read: Not pending</description>
59793 <description>Read: Pending</description>
59800 <description>Read pending status of interrupt for event SYSCOUNTERVALID</description>
59807 <description>Read: Not pending</description>
59812 <description>Read: Pending</description>
59819 <description>Read pending status of interrupt for event PWMPERIODEND</description>
59826 <description>Read: Not pending</description>
59831 <description>Read: Pending</description>
59840 <description>Enable or disable interrupt</description>
59848 <description>Enable or disable interrupt for event COMPARE[0]</description>
59854 <description>Disable</description>
59859 <description>Enable</description>
59866 <description>Enable or disable interrupt for event COMPARE[1]</description>
59872 <description>Disable</description>
59877 <description>Enable</description>
59884 <description>Enable or disable interrupt for event COMPARE[2]</description>
59890 <description>Disable</description>
59895 <description>Enable</description>
59902 <description>Enable or disable interrupt for event COMPARE[3]</description>
59908 <description>Disable</description>
59913 <description>Enable</description>
59920 <description>Enable or disable interrupt for event COMPARE[4]</description>
59926 <description>Disable</description>
59931 <description>Enable</description>
59938 <description>Enable or disable interrupt for event COMPARE[5]</description>
59944 <description>Disable</description>
59949 <description>Enable</description>
59956 <description>Enable or disable interrupt for event COMPARE[6]</description>
59962 <description>Disable</description>
59967 <description>Enable</description>
59974 <description>Enable or disable interrupt for event COMPARE[7]</description>
59980 <description>Disable</description>
59985 <description>Enable</description>
59992 <description>Enable or disable interrupt for event COMPARE[8]</description>
59998 <description>Disable</description>
60003 <description>Enable</description>
60010 <description>Enable or disable interrupt for event COMPARE[9]</description>
60016 <description>Disable</description>
60021 <description>Enable</description>
60028 <description>Enable or disable interrupt for event COMPARE[10]</description>
60034 <description>Disable</description>
60039 <description>Enable</description>
60046 <description>Enable or disable interrupt for event COMPARE[11]</description>
60052 <description>Disable</description>
60057 <description>Enable</description>
60064 <description>Enable or disable interrupt for event COMPARE[12]</description>
60070 <description>Disable</description>
60075 <description>Enable</description>
60082 <description>Enable or disable interrupt for event COMPARE[13]</description>
60088 <description>Disable</description>
60093 <description>Enable</description>
60100 <description>Enable or disable interrupt for event COMPARE[14]</description>
60106 <description>Disable</description>
60111 <description>Enable</description>
60118 <description>Enable or disable interrupt for event COMPARE[15]</description>
60124 <description>Disable</description>
60129 <description>Enable</description>
60136 <description>Enable or disable interrupt for event RTCOMPARESYNC</description>
60142 <description>Disable</description>
60147 <description>Enable</description>
60154 <description>Enable or disable interrupt for event SYSCOUNTERVALID</description>
60160 <description>Disable</description>
60165 <description>Enable</description>
60172 <description>Enable or disable interrupt for event PWMPERIODEND</description>
60178 <description>Disable</description>
60183 <description>Enable</description>
60192 <description>Enable interrupt</description>
60200 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
60207 <description>Read: Disabled</description>
60212 <description>Read: Enabled</description>
60220 <description>Enable</description>
60227 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
60234 <description>Read: Disabled</description>
60239 <description>Read: Enabled</description>
60247 <description>Enable</description>
60254 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
60261 <description>Read: Disabled</description>
60266 <description>Read: Enabled</description>
60274 <description>Enable</description>
60281 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
60288 <description>Read: Disabled</description>
60293 <description>Read: Enabled</description>
60301 <description>Enable</description>
60308 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
60315 <description>Read: Disabled</description>
60320 <description>Read: Enabled</description>
60328 <description>Enable</description>
60335 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
60342 <description>Read: Disabled</description>
60347 <description>Read: Enabled</description>
60355 <description>Enable</description>
60362 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
60369 <description>Read: Disabled</description>
60374 <description>Read: Enabled</description>
60382 <description>Enable</description>
60389 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
60396 <description>Read: Disabled</description>
60401 <description>Read: Enabled</description>
60409 <description>Enable</description>
60416 <description>Write '1' to enable interrupt for event COMPARE[8]</description>
60423 <description>Read: Disabled</description>
60428 <description>Read: Enabled</description>
60436 <description>Enable</description>
60443 <description>Write '1' to enable interrupt for event COMPARE[9]</description>
60450 <description>Read: Disabled</description>
60455 <description>Read: Enabled</description>
60463 <description>Enable</description>
60470 <description>Write '1' to enable interrupt for event COMPARE[10]</description>
60477 <description>Read: Disabled</description>
60482 <description>Read: Enabled</description>
60490 <description>Enable</description>
60497 <description>Write '1' to enable interrupt for event COMPARE[11]</description>
60504 <description>Read: Disabled</description>
60509 <description>Read: Enabled</description>
60517 <description>Enable</description>
60524 <description>Write '1' to enable interrupt for event COMPARE[12]</description>
60531 <description>Read: Disabled</description>
60536 <description>Read: Enabled</description>
60544 <description>Enable</description>
60551 <description>Write '1' to enable interrupt for event COMPARE[13]</description>
60558 <description>Read: Disabled</description>
60563 <description>Read: Enabled</description>
60571 <description>Enable</description>
60578 <description>Write '1' to enable interrupt for event COMPARE[14]</description>
60585 <description>Read: Disabled</description>
60590 <description>Read: Enabled</description>
60598 <description>Enable</description>
60605 <description>Write '1' to enable interrupt for event COMPARE[15]</description>
60612 <description>Read: Disabled</description>
60617 <description>Read: Enabled</description>
60625 <description>Enable</description>
60632 <description>Write '1' to enable interrupt for event RTCOMPARESYNC</description>
60639 <description>Read: Disabled</description>
60644 <description>Read: Enabled</description>
60652 <description>Enable</description>
60659 <description>Write '1' to enable interrupt for event SYSCOUNTERVALID</description>
60666 <description>Read: Disabled</description>
60671 <description>Read: Enabled</description>
60679 <description>Enable</description>
60686 <description>Write '1' to enable interrupt for event PWMPERIODEND</description>
60693 <description>Read: Disabled</description>
60698 <description>Read: Enabled</description>
60706 <description>Enable</description>
60715 <description>Disable interrupt</description>
60723 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
60730 <description>Read: Disabled</description>
60735 <description>Read: Enabled</description>
60743 <description>Disable</description>
60750 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
60757 <description>Read: Disabled</description>
60762 <description>Read: Enabled</description>
60770 <description>Disable</description>
60777 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
60784 <description>Read: Disabled</description>
60789 <description>Read: Enabled</description>
60797 <description>Disable</description>
60804 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
60811 <description>Read: Disabled</description>
60816 <description>Read: Enabled</description>
60824 <description>Disable</description>
60831 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
60838 <description>Read: Disabled</description>
60843 <description>Read: Enabled</description>
60851 <description>Disable</description>
60858 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
60865 <description>Read: Disabled</description>
60870 <description>Read: Enabled</description>
60878 <description>Disable</description>
60885 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
60892 <description>Read: Disabled</description>
60897 <description>Read: Enabled</description>
60905 <description>Disable</description>
60912 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
60919 <description>Read: Disabled</description>
60924 <description>Read: Enabled</description>
60932 <description>Disable</description>
60939 <description>Write '1' to disable interrupt for event COMPARE[8]</description>
60946 <description>Read: Disabled</description>
60951 <description>Read: Enabled</description>
60959 <description>Disable</description>
60966 <description>Write '1' to disable interrupt for event COMPARE[9]</description>
60973 <description>Read: Disabled</description>
60978 <description>Read: Enabled</description>
60986 <description>Disable</description>
60993 <description>Write '1' to disable interrupt for event COMPARE[10]</description>
61000 <description>Read: Disabled</description>
61005 <description>Read: Enabled</description>
61013 <description>Disable</description>
61020 <description>Write '1' to disable interrupt for event COMPARE[11]</description>
61027 <description>Read: Disabled</description>
61032 <description>Read: Enabled</description>
61040 <description>Disable</description>
61047 <description>Write '1' to disable interrupt for event COMPARE[12]</description>
61054 <description>Read: Disabled</description>
61059 <description>Read: Enabled</description>
61067 <description>Disable</description>
61074 <description>Write '1' to disable interrupt for event COMPARE[13]</description>
61081 <description>Read: Disabled</description>
61086 <description>Read: Enabled</description>
61094 <description>Disable</description>
61101 <description>Write '1' to disable interrupt for event COMPARE[14]</description>
61108 <description>Read: Disabled</description>
61113 <description>Read: Enabled</description>
61121 <description>Disable</description>
61128 <description>Write '1' to disable interrupt for event COMPARE[15]</description>
61135 <description>Read: Disabled</description>
61140 <description>Read: Enabled</description>
61148 <description>Disable</description>
61155 <description>Write '1' to disable interrupt for event RTCOMPARESYNC</description>
61162 <description>Read: Disabled</description>
61167 <description>Read: Enabled</description>
61175 <description>Disable</description>
61182 <description>Write '1' to disable interrupt for event SYSCOUNTERVALID</description>
61189 <description>Read: Disabled</description>
61194 <description>Read: Enabled</description>
61202 <description>Disable</description>
61209 <description>Write '1' to disable interrupt for event PWMPERIODEND</description>
61216 <description>Read: Disabled</description>
61221 <description>Read: Enabled</description>
61229 <description>Disable</description>
61238 <description>Pending interrupts</description>
61246 <description>Read pending status of interrupt for event COMPARE[0]</description>
61253 <description>Read: Not pending</description>
61258 <description>Read: Pending</description>
61265 <description>Read pending status of interrupt for event COMPARE[1]</description>
61272 <description>Read: Not pending</description>
61277 <description>Read: Pending</description>
61284 <description>Read pending status of interrupt for event COMPARE[2]</description>
61291 <description>Read: Not pending</description>
61296 <description>Read: Pending</description>
61303 <description>Read pending status of interrupt for event COMPARE[3]</description>
61310 <description>Read: Not pending</description>
61315 <description>Read: Pending</description>
61322 <description>Read pending status of interrupt for event COMPARE[4]</description>
61329 <description>Read: Not pending</description>
61334 <description>Read: Pending</description>
61341 <description>Read pending status of interrupt for event COMPARE[5]</description>
61348 <description>Read: Not pending</description>
61353 <description>Read: Pending</description>
61360 <description>Read pending status of interrupt for event COMPARE[6]</description>
61367 <description>Read: Not pending</description>
61372 <description>Read: Pending</description>
61379 <description>Read pending status of interrupt for event COMPARE[7]</description>
61386 <description>Read: Not pending</description>
61391 <description>Read: Pending</description>
61398 <description>Read pending status of interrupt for event COMPARE[8]</description>
61405 <description>Read: Not pending</description>
61410 <description>Read: Pending</description>
61417 <description>Read pending status of interrupt for event COMPARE[9]</description>
61424 <description>Read: Not pending</description>
61429 <description>Read: Pending</description>
61436 <description>Read pending status of interrupt for event COMPARE[10]</description>
61443 <description>Read: Not pending</description>
61448 <description>Read: Pending</description>
61455 <description>Read pending status of interrupt for event COMPARE[11]</description>
61462 <description>Read: Not pending</description>
61467 <description>Read: Pending</description>
61474 <description>Read pending status of interrupt for event COMPARE[12]</description>
61481 <description>Read: Not pending</description>
61486 <description>Read: Pending</description>
61493 <description>Read pending status of interrupt for event COMPARE[13]</description>
61500 <description>Read: Not pending</description>
61505 <description>Read: Pending</description>
61512 <description>Read pending status of interrupt for event COMPARE[14]</description>
61519 <description>Read: Not pending</description>
61524 <description>Read: Pending</description>
61531 <description>Read pending status of interrupt for event COMPARE[15]</description>
61538 <description>Read: Not pending</description>
61543 <description>Read: Pending</description>
61550 <description>Read pending status of interrupt for event RTCOMPARESYNC</description>
61557 <description>Read: Not pending</description>
61562 <description>Read: Pending</description>
61569 <description>Read pending status of interrupt for event SYSCOUNTERVALID</description>
61576 <description>Read: Not pending</description>
61581 <description>Read: Pending</description>
61588 <description>Read pending status of interrupt for event PWMPERIODEND</description>
61595 <description>Read: Not pending</description>
61600 <description>Read: Pending</description>
61609 <description>Enable or disable interrupt</description>
61617 <description>Enable or disable interrupt for event COMPARE[0]</description>
61623 <description>Disable</description>
61628 <description>Enable</description>
61635 <description>Enable or disable interrupt for event COMPARE[1]</description>
61641 <description>Disable</description>
61646 <description>Enable</description>
61653 <description>Enable or disable interrupt for event COMPARE[2]</description>
61659 <description>Disable</description>
61664 <description>Enable</description>
61671 <description>Enable or disable interrupt for event COMPARE[3]</description>
61677 <description>Disable</description>
61682 <description>Enable</description>
61689 <description>Enable or disable interrupt for event COMPARE[4]</description>
61695 <description>Disable</description>
61700 <description>Enable</description>
61707 <description>Enable or disable interrupt for event COMPARE[5]</description>
61713 <description>Disable</description>
61718 <description>Enable</description>
61725 <description>Enable or disable interrupt for event COMPARE[6]</description>
61731 <description>Disable</description>
61736 <description>Enable</description>
61743 <description>Enable or disable interrupt for event COMPARE[7]</description>
61749 <description>Disable</description>
61754 <description>Enable</description>
61761 <description>Enable or disable interrupt for event COMPARE[8]</description>
61767 <description>Disable</description>
61772 <description>Enable</description>
61779 <description>Enable or disable interrupt for event COMPARE[9]</description>
61785 <description>Disable</description>
61790 <description>Enable</description>
61797 <description>Enable or disable interrupt for event COMPARE[10]</description>
61803 <description>Disable</description>
61808 <description>Enable</description>
61815 <description>Enable or disable interrupt for event COMPARE[11]</description>
61821 <description>Disable</description>
61826 <description>Enable</description>
61833 <description>Enable or disable interrupt for event COMPARE[12]</description>
61839 <description>Disable</description>
61844 <description>Enable</description>
61851 <description>Enable or disable interrupt for event COMPARE[13]</description>
61857 <description>Disable</description>
61862 <description>Enable</description>
61869 <description>Enable or disable interrupt for event COMPARE[14]</description>
61875 <description>Disable</description>
61880 <description>Enable</description>
61887 <description>Enable or disable interrupt for event COMPARE[15]</description>
61893 <description>Disable</description>
61898 <description>Enable</description>
61905 <description>Enable or disable interrupt for event RTCOMPARESYNC</description>
61911 <description>Disable</description>
61916 <description>Enable</description>
61923 <description>Enable or disable interrupt for event SYSCOUNTERVALID</description>
61929 <description>Disable</description>
61934 <description>Enable</description>
61941 <description>Enable or disable interrupt for event PWMPERIODEND</description>
61947 <description>Disable</description>
61952 <description>Enable</description>
61961 <description>Enable interrupt</description>
61969 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
61976 <description>Read: Disabled</description>
61981 <description>Read: Enabled</description>
61989 <description>Enable</description>
61996 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
62003 <description>Read: Disabled</description>
62008 <description>Read: Enabled</description>
62016 <description>Enable</description>
62023 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
62030 <description>Read: Disabled</description>
62035 <description>Read: Enabled</description>
62043 <description>Enable</description>
62050 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
62057 <description>Read: Disabled</description>
62062 <description>Read: Enabled</description>
62070 <description>Enable</description>
62077 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
62084 <description>Read: Disabled</description>
62089 <description>Read: Enabled</description>
62097 <description>Enable</description>
62104 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
62111 <description>Read: Disabled</description>
62116 <description>Read: Enabled</description>
62124 <description>Enable</description>
62131 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
62138 <description>Read: Disabled</description>
62143 <description>Read: Enabled</description>
62151 <description>Enable</description>
62158 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
62165 <description>Read: Disabled</description>
62170 <description>Read: Enabled</description>
62178 <description>Enable</description>
62185 <description>Write '1' to enable interrupt for event COMPARE[8]</description>
62192 <description>Read: Disabled</description>
62197 <description>Read: Enabled</description>
62205 <description>Enable</description>
62212 <description>Write '1' to enable interrupt for event COMPARE[9]</description>
62219 <description>Read: Disabled</description>
62224 <description>Read: Enabled</description>
62232 <description>Enable</description>
62239 <description>Write '1' to enable interrupt for event COMPARE[10]</description>
62246 <description>Read: Disabled</description>
62251 <description>Read: Enabled</description>
62259 <description>Enable</description>
62266 <description>Write '1' to enable interrupt for event COMPARE[11]</description>
62273 <description>Read: Disabled</description>
62278 <description>Read: Enabled</description>
62286 <description>Enable</description>
62293 <description>Write '1' to enable interrupt for event COMPARE[12]</description>
62300 <description>Read: Disabled</description>
62305 <description>Read: Enabled</description>
62313 <description>Enable</description>
62320 <description>Write '1' to enable interrupt for event COMPARE[13]</description>
62327 <description>Read: Disabled</description>
62332 <description>Read: Enabled</description>
62340 <description>Enable</description>
62347 <description>Write '1' to enable interrupt for event COMPARE[14]</description>
62354 <description>Read: Disabled</description>
62359 <description>Read: Enabled</description>
62367 <description>Enable</description>
62374 <description>Write '1' to enable interrupt for event COMPARE[15]</description>
62381 <description>Read: Disabled</description>
62386 <description>Read: Enabled</description>
62394 <description>Enable</description>
62401 <description>Write '1' to enable interrupt for event RTCOMPARESYNC</description>
62408 <description>Read: Disabled</description>
62413 <description>Read: Enabled</description>
62421 <description>Enable</description>
62428 <description>Write '1' to enable interrupt for event SYSCOUNTERVALID</description>
62435 <description>Read: Disabled</description>
62440 <description>Read: Enabled</description>
62448 <description>Enable</description>
62455 <description>Write '1' to enable interrupt for event PWMPERIODEND</description>
62462 <description>Read: Disabled</description>
62467 <description>Read: Enabled</description>
62475 <description>Enable</description>
62484 <description>Disable interrupt</description>
62492 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
62499 <description>Read: Disabled</description>
62504 <description>Read: Enabled</description>
62512 <description>Disable</description>
62519 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
62526 <description>Read: Disabled</description>
62531 <description>Read: Enabled</description>
62539 <description>Disable</description>
62546 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
62553 <description>Read: Disabled</description>
62558 <description>Read: Enabled</description>
62566 <description>Disable</description>
62573 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
62580 <description>Read: Disabled</description>
62585 <description>Read: Enabled</description>
62593 <description>Disable</description>
62600 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
62607 <description>Read: Disabled</description>
62612 <description>Read: Enabled</description>
62620 <description>Disable</description>
62627 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
62634 <description>Read: Disabled</description>
62639 <description>Read: Enabled</description>
62647 <description>Disable</description>
62654 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
62661 <description>Read: Disabled</description>
62666 <description>Read: Enabled</description>
62674 <description>Disable</description>
62681 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
62688 <description>Read: Disabled</description>
62693 <description>Read: Enabled</description>
62701 <description>Disable</description>
62708 <description>Write '1' to disable interrupt for event COMPARE[8]</description>
62715 <description>Read: Disabled</description>
62720 <description>Read: Enabled</description>
62728 <description>Disable</description>
62735 <description>Write '1' to disable interrupt for event COMPARE[9]</description>
62742 <description>Read: Disabled</description>
62747 <description>Read: Enabled</description>
62755 <description>Disable</description>
62762 <description>Write '1' to disable interrupt for event COMPARE[10]</description>
62769 <description>Read: Disabled</description>
62774 <description>Read: Enabled</description>
62782 <description>Disable</description>
62789 <description>Write '1' to disable interrupt for event COMPARE[11]</description>
62796 <description>Read: Disabled</description>
62801 <description>Read: Enabled</description>
62809 <description>Disable</description>
62816 <description>Write '1' to disable interrupt for event COMPARE[12]</description>
62823 <description>Read: Disabled</description>
62828 <description>Read: Enabled</description>
62836 <description>Disable</description>
62843 <description>Write '1' to disable interrupt for event COMPARE[13]</description>
62850 <description>Read: Disabled</description>
62855 <description>Read: Enabled</description>
62863 <description>Disable</description>
62870 <description>Write '1' to disable interrupt for event COMPARE[14]</description>
62877 <description>Read: Disabled</description>
62882 <description>Read: Enabled</description>
62890 <description>Disable</description>
62897 <description>Write '1' to disable interrupt for event COMPARE[15]</description>
62904 <description>Read: Disabled</description>
62909 <description>Read: Enabled</description>
62917 <description>Disable</description>
62924 <description>Write '1' to disable interrupt for event RTCOMPARESYNC</description>
62931 <description>Read: Disabled</description>
62936 <description>Read: Enabled</description>
62944 <description>Disable</description>
62951 <description>Write '1' to disable interrupt for event SYSCOUNTERVALID</description>
62958 <description>Read: Disabled</description>
62963 <description>Read: Enabled</description>
62971 <description>Disable</description>
62978 <description>Write '1' to disable interrupt for event PWMPERIODEND</description>
62985 <description>Read: Disabled</description>
62990 <description>Read: Enabled</description>
62998 <description>Disable</description>
63007 <description>Pending interrupts</description>
63015 <description>Read pending status of interrupt for event COMPARE[0]</description>
63022 <description>Read: Not pending</description>
63027 <description>Read: Pending</description>
63034 <description>Read pending status of interrupt for event COMPARE[1]</description>
63041 <description>Read: Not pending</description>
63046 <description>Read: Pending</description>
63053 <description>Read pending status of interrupt for event COMPARE[2]</description>
63060 <description>Read: Not pending</description>
63065 <description>Read: Pending</description>
63072 <description>Read pending status of interrupt for event COMPARE[3]</description>
63079 <description>Read: Not pending</description>
63084 <description>Read: Pending</description>
63091 <description>Read pending status of interrupt for event COMPARE[4]</description>
63098 <description>Read: Not pending</description>
63103 <description>Read: Pending</description>
63110 <description>Read pending status of interrupt for event COMPARE[5]</description>
63117 <description>Read: Not pending</description>
63122 <description>Read: Pending</description>
63129 <description>Read pending status of interrupt for event COMPARE[6]</description>
63136 <description>Read: Not pending</description>
63141 <description>Read: Pending</description>
63148 <description>Read pending status of interrupt for event COMPARE[7]</description>
63155 <description>Read: Not pending</description>
63160 <description>Read: Pending</description>
63167 <description>Read pending status of interrupt for event COMPARE[8]</description>
63174 <description>Read: Not pending</description>
63179 <description>Read: Pending</description>
63186 <description>Read pending status of interrupt for event COMPARE[9]</description>
63193 <description>Read: Not pending</description>
63198 <description>Read: Pending</description>
63205 <description>Read pending status of interrupt for event COMPARE[10]</description>
63212 <description>Read: Not pending</description>
63217 <description>Read: Pending</description>
63224 <description>Read pending status of interrupt for event COMPARE[11]</description>
63231 <description>Read: Not pending</description>
63236 <description>Read: Pending</description>
63243 <description>Read pending status of interrupt for event COMPARE[12]</description>
63250 <description>Read: Not pending</description>
63255 <description>Read: Pending</description>
63262 <description>Read pending status of interrupt for event COMPARE[13]</description>
63269 <description>Read: Not pending</description>
63274 <description>Read: Pending</description>
63281 <description>Read pending status of interrupt for event COMPARE[14]</description>
63288 <description>Read: Not pending</description>
63293 <description>Read: Pending</description>
63300 <description>Read pending status of interrupt for event COMPARE[15]</description>
63307 <description>Read: Not pending</description>
63312 <description>Read: Pending</description>
63319 <description>Read pending status of interrupt for event RTCOMPARESYNC</description>
63326 <description>Read: Not pending</description>
63331 <description>Read: Pending</description>
63338 <description>Read pending status of interrupt for event SYSCOUNTERVALID</description>
63345 <description>Read: Not pending</description>
63350 <description>Read: Pending</description>
63357 <description>Read pending status of interrupt for event PWMPERIODEND</description>
63364 <description>Read: Not pending</description>
63369 <description>Read: Pending</description>
63378 <description>Enable or disable interrupt</description>
63386 <description>Enable or disable interrupt for event COMPARE[0]</description>
63392 <description>Disable</description>
63397 <description>Enable</description>
63404 <description>Enable or disable interrupt for event COMPARE[1]</description>
63410 <description>Disable</description>
63415 <description>Enable</description>
63422 <description>Enable or disable interrupt for event COMPARE[2]</description>
63428 <description>Disable</description>
63433 <description>Enable</description>
63440 <description>Enable or disable interrupt for event COMPARE[3]</description>
63446 <description>Disable</description>
63451 <description>Enable</description>
63458 <description>Enable or disable interrupt for event COMPARE[4]</description>
63464 <description>Disable</description>
63469 <description>Enable</description>
63476 <description>Enable or disable interrupt for event COMPARE[5]</description>
63482 <description>Disable</description>
63487 <description>Enable</description>
63494 <description>Enable or disable interrupt for event COMPARE[6]</description>
63500 <description>Disable</description>
63505 <description>Enable</description>
63512 <description>Enable or disable interrupt for event COMPARE[7]</description>
63518 <description>Disable</description>
63523 <description>Enable</description>
63530 <description>Enable or disable interrupt for event COMPARE[8]</description>
63536 <description>Disable</description>
63541 <description>Enable</description>
63548 <description>Enable or disable interrupt for event COMPARE[9]</description>
63554 <description>Disable</description>
63559 <description>Enable</description>
63566 <description>Enable or disable interrupt for event COMPARE[10]</description>
63572 <description>Disable</description>
63577 <description>Enable</description>
63584 <description>Enable or disable interrupt for event COMPARE[11]</description>
63590 <description>Disable</description>
63595 <description>Enable</description>
63602 <description>Enable or disable interrupt for event COMPARE[12]</description>
63608 <description>Disable</description>
63613 <description>Enable</description>
63620 <description>Enable or disable interrupt for event COMPARE[13]</description>
63626 <description>Disable</description>
63631 <description>Enable</description>
63638 <description>Enable or disable interrupt for event COMPARE[14]</description>
63644 <description>Disable</description>
63649 <description>Enable</description>
63656 <description>Enable or disable interrupt for event COMPARE[15]</description>
63662 <description>Disable</description>
63667 <description>Enable</description>
63674 <description>Enable or disable interrupt for event RTCOMPARESYNC</description>
63680 <description>Disable</description>
63685 <description>Enable</description>
63692 <description>Enable or disable interrupt for event SYSCOUNTERVALID</description>
63698 <description>Disable</description>
63703 <description>Enable</description>
63710 <description>Enable or disable interrupt for event PWMPERIODEND</description>
63716 <description>Disable</description>
63721 <description>Enable</description>
63730 <description>Enable interrupt</description>
63738 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
63745 <description>Read: Disabled</description>
63750 <description>Read: Enabled</description>
63758 <description>Enable</description>
63765 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
63772 <description>Read: Disabled</description>
63777 <description>Read: Enabled</description>
63785 <description>Enable</description>
63792 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
63799 <description>Read: Disabled</description>
63804 <description>Read: Enabled</description>
63812 <description>Enable</description>
63819 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
63826 <description>Read: Disabled</description>
63831 <description>Read: Enabled</description>
63839 <description>Enable</description>
63846 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
63853 <description>Read: Disabled</description>
63858 <description>Read: Enabled</description>
63866 <description>Enable</description>
63873 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
63880 <description>Read: Disabled</description>
63885 <description>Read: Enabled</description>
63893 <description>Enable</description>
63900 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
63907 <description>Read: Disabled</description>
63912 <description>Read: Enabled</description>
63920 <description>Enable</description>
63927 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
63934 <description>Read: Disabled</description>
63939 <description>Read: Enabled</description>
63947 <description>Enable</description>
63954 <description>Write '1' to enable interrupt for event COMPARE[8]</description>
63961 <description>Read: Disabled</description>
63966 <description>Read: Enabled</description>
63974 <description>Enable</description>
63981 <description>Write '1' to enable interrupt for event COMPARE[9]</description>
63988 <description>Read: Disabled</description>
63993 <description>Read: Enabled</description>
64001 <description>Enable</description>
64008 <description>Write '1' to enable interrupt for event COMPARE[10]</description>
64015 <description>Read: Disabled</description>
64020 <description>Read: Enabled</description>
64028 <description>Enable</description>
64035 <description>Write '1' to enable interrupt for event COMPARE[11]</description>
64042 <description>Read: Disabled</description>
64047 <description>Read: Enabled</description>
64055 <description>Enable</description>
64062 <description>Write '1' to enable interrupt for event COMPARE[12]</description>
64069 <description>Read: Disabled</description>
64074 <description>Read: Enabled</description>
64082 <description>Enable</description>
64089 <description>Write '1' to enable interrupt for event COMPARE[13]</description>
64096 <description>Read: Disabled</description>
64101 <description>Read: Enabled</description>
64109 <description>Enable</description>
64116 <description>Write '1' to enable interrupt for event COMPARE[14]</description>
64123 <description>Read: Disabled</description>
64128 <description>Read: Enabled</description>
64136 <description>Enable</description>
64143 <description>Write '1' to enable interrupt for event COMPARE[15]</description>
64150 <description>Read: Disabled</description>
64155 <description>Read: Enabled</description>
64163 <description>Enable</description>
64170 <description>Write '1' to enable interrupt for event RTCOMPARESYNC</description>
64177 <description>Read: Disabled</description>
64182 <description>Read: Enabled</description>
64190 <description>Enable</description>
64197 <description>Write '1' to enable interrupt for event SYSCOUNTERVALID</description>
64204 <description>Read: Disabled</description>
64209 <description>Read: Enabled</description>
64217 <description>Enable</description>
64224 <description>Write '1' to enable interrupt for event PWMPERIODEND</description>
64231 <description>Read: Disabled</description>
64236 <description>Read: Enabled</description>
64244 <description>Enable</description>
64253 <description>Disable interrupt</description>
64261 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
64268 <description>Read: Disabled</description>
64273 <description>Read: Enabled</description>
64281 <description>Disable</description>
64288 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
64295 <description>Read: Disabled</description>
64300 <description>Read: Enabled</description>
64308 <description>Disable</description>
64315 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
64322 <description>Read: Disabled</description>
64327 <description>Read: Enabled</description>
64335 <description>Disable</description>
64342 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
64349 <description>Read: Disabled</description>
64354 <description>Read: Enabled</description>
64362 <description>Disable</description>
64369 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
64376 <description>Read: Disabled</description>
64381 <description>Read: Enabled</description>
64389 <description>Disable</description>
64396 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
64403 <description>Read: Disabled</description>
64408 <description>Read: Enabled</description>
64416 <description>Disable</description>
64423 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
64430 <description>Read: Disabled</description>
64435 <description>Read: Enabled</description>
64443 <description>Disable</description>
64450 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
64457 <description>Read: Disabled</description>
64462 <description>Read: Enabled</description>
64470 <description>Disable</description>
64477 <description>Write '1' to disable interrupt for event COMPARE[8]</description>
64484 <description>Read: Disabled</description>
64489 <description>Read: Enabled</description>
64497 <description>Disable</description>
64504 <description>Write '1' to disable interrupt for event COMPARE[9]</description>
64511 <description>Read: Disabled</description>
64516 <description>Read: Enabled</description>
64524 <description>Disable</description>
64531 <description>Write '1' to disable interrupt for event COMPARE[10]</description>
64538 <description>Read: Disabled</description>
64543 <description>Read: Enabled</description>
64551 <description>Disable</description>
64558 <description>Write '1' to disable interrupt for event COMPARE[11]</description>
64565 <description>Read: Disabled</description>
64570 <description>Read: Enabled</description>
64578 <description>Disable</description>
64585 <description>Write '1' to disable interrupt for event COMPARE[12]</description>
64592 <description>Read: Disabled</description>
64597 <description>Read: Enabled</description>
64605 <description>Disable</description>
64612 <description>Write '1' to disable interrupt for event COMPARE[13]</description>
64619 <description>Read: Disabled</description>
64624 <description>Read: Enabled</description>
64632 <description>Disable</description>
64639 <description>Write '1' to disable interrupt for event COMPARE[14]</description>
64646 <description>Read: Disabled</description>
64651 <description>Read: Enabled</description>
64659 <description>Disable</description>
64666 <description>Write '1' to disable interrupt for event COMPARE[15]</description>
64673 <description>Read: Disabled</description>
64678 <description>Read: Enabled</description>
64686 <description>Disable</description>
64693 <description>Write '1' to disable interrupt for event RTCOMPARESYNC</description>
64700 <description>Read: Disabled</description>
64705 <description>Read: Enabled</description>
64713 <description>Disable</description>
64720 <description>Write '1' to disable interrupt for event SYSCOUNTERVALID</description>
64727 <description>Read: Disabled</description>
64732 <description>Read: Enabled</description>
64740 <description>Disable</description>
64747 <description>Write '1' to disable interrupt for event PWMPERIODEND</description>
64754 <description>Read: Disabled</description>
64759 <description>Read: Enabled</description>
64767 <description>Disable</description>
64776 <description>Pending interrupts</description>
64784 <description>Read pending status of interrupt for event COMPARE[0]</description>
64791 <description>Read: Not pending</description>
64796 <description>Read: Pending</description>
64803 <description>Read pending status of interrupt for event COMPARE[1]</description>
64810 <description>Read: Not pending</description>
64815 <description>Read: Pending</description>
64822 <description>Read pending status of interrupt for event COMPARE[2]</description>
64829 <description>Read: Not pending</description>
64834 <description>Read: Pending</description>
64841 <description>Read pending status of interrupt for event COMPARE[3]</description>
64848 <description>Read: Not pending</description>
64853 <description>Read: Pending</description>
64860 <description>Read pending status of interrupt for event COMPARE[4]</description>
64867 <description>Read: Not pending</description>
64872 <description>Read: Pending</description>
64879 <description>Read pending status of interrupt for event COMPARE[5]</description>
64886 <description>Read: Not pending</description>
64891 <description>Read: Pending</description>
64898 <description>Read pending status of interrupt for event COMPARE[6]</description>
64905 <description>Read: Not pending</description>
64910 <description>Read: Pending</description>
64917 <description>Read pending status of interrupt for event COMPARE[7]</description>
64924 <description>Read: Not pending</description>
64929 <description>Read: Pending</description>
64936 <description>Read pending status of interrupt for event COMPARE[8]</description>
64943 <description>Read: Not pending</description>
64948 <description>Read: Pending</description>
64955 <description>Read pending status of interrupt for event COMPARE[9]</description>
64962 <description>Read: Not pending</description>
64967 <description>Read: Pending</description>
64974 <description>Read pending status of interrupt for event COMPARE[10]</description>
64981 <description>Read: Not pending</description>
64986 <description>Read: Pending</description>
64993 <description>Read pending status of interrupt for event COMPARE[11]</description>
65000 <description>Read: Not pending</description>
65005 <description>Read: Pending</description>
65012 <description>Read pending status of interrupt for event COMPARE[12]</description>
65019 <description>Read: Not pending</description>
65024 <description>Read: Pending</description>
65031 <description>Read pending status of interrupt for event COMPARE[13]</description>
65038 <description>Read: Not pending</description>
65043 <description>Read: Pending</description>
65050 <description>Read pending status of interrupt for event COMPARE[14]</description>
65057 <description>Read: Not pending</description>
65062 <description>Read: Pending</description>
65069 <description>Read pending status of interrupt for event COMPARE[15]</description>
65076 <description>Read: Not pending</description>
65081 <description>Read: Pending</description>
65088 <description>Read pending status of interrupt for event RTCOMPARESYNC</description>
65095 <description>Read: Not pending</description>
65100 <description>Read: Pending</description>
65107 <description>Read pending status of interrupt for event SYSCOUNTERVALID</description>
65114 <description>Read: Not pending</description>
65119 <description>Read: Pending</description>
65126 <description>Read pending status of interrupt for event PWMPERIODEND</description>
65133 <description>Read: Not pending</description>
65138 <description>Read: Pending</description>
65147 <description>Enable or disable interrupt</description>
65155 <description>Enable or disable interrupt for event COMPARE[0]</description>
65161 <description>Disable</description>
65166 <description>Enable</description>
65173 <description>Enable or disable interrupt for event COMPARE[1]</description>
65179 <description>Disable</description>
65184 <description>Enable</description>
65191 <description>Enable or disable interrupt for event COMPARE[2]</description>
65197 <description>Disable</description>
65202 <description>Enable</description>
65209 <description>Enable or disable interrupt for event COMPARE[3]</description>
65215 <description>Disable</description>
65220 <description>Enable</description>
65227 <description>Enable or disable interrupt for event COMPARE[4]</description>
65233 <description>Disable</description>
65238 <description>Enable</description>
65245 <description>Enable or disable interrupt for event COMPARE[5]</description>
65251 <description>Disable</description>
65256 <description>Enable</description>
65263 <description>Enable or disable interrupt for event COMPARE[6]</description>
65269 <description>Disable</description>
65274 <description>Enable</description>
65281 <description>Enable or disable interrupt for event COMPARE[7]</description>
65287 <description>Disable</description>
65292 <description>Enable</description>
65299 <description>Enable or disable interrupt for event COMPARE[8]</description>
65305 <description>Disable</description>
65310 <description>Enable</description>
65317 <description>Enable or disable interrupt for event COMPARE[9]</description>
65323 <description>Disable</description>
65328 <description>Enable</description>
65335 <description>Enable or disable interrupt for event COMPARE[10]</description>
65341 <description>Disable</description>
65346 <description>Enable</description>
65353 <description>Enable or disable interrupt for event COMPARE[11]</description>
65359 <description>Disable</description>
65364 <description>Enable</description>
65371 <description>Enable or disable interrupt for event COMPARE[12]</description>
65377 <description>Disable</description>
65382 <description>Enable</description>
65389 <description>Enable or disable interrupt for event COMPARE[13]</description>
65395 <description>Disable</description>
65400 <description>Enable</description>
65407 <description>Enable or disable interrupt for event COMPARE[14]</description>
65413 <description>Disable</description>
65418 <description>Enable</description>
65425 <description>Enable or disable interrupt for event COMPARE[15]</description>
65431 <description>Disable</description>
65436 <description>Enable</description>
65443 <description>Enable or disable interrupt for event RTCOMPARESYNC</description>
65449 <description>Disable</description>
65454 <description>Enable</description>
65461 <description>Enable or disable interrupt for event SYSCOUNTERVALID</description>
65467 <description>Disable</description>
65472 <description>Enable</description>
65479 <description>Enable or disable interrupt for event PWMPERIODEND</description>
65485 <description>Disable</description>
65490 <description>Enable</description>
65499 <description>Enable interrupt</description>
65507 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
65514 <description>Read: Disabled</description>
65519 <description>Read: Enabled</description>
65527 <description>Enable</description>
65534 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
65541 <description>Read: Disabled</description>
65546 <description>Read: Enabled</description>
65554 <description>Enable</description>
65561 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
65568 <description>Read: Disabled</description>
65573 <description>Read: Enabled</description>
65581 <description>Enable</description>
65588 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
65595 <description>Read: Disabled</description>
65600 <description>Read: Enabled</description>
65608 <description>Enable</description>
65615 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
65622 <description>Read: Disabled</description>
65627 <description>Read: Enabled</description>
65635 <description>Enable</description>
65642 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
65649 <description>Read: Disabled</description>
65654 <description>Read: Enabled</description>
65662 <description>Enable</description>
65669 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
65676 <description>Read: Disabled</description>
65681 <description>Read: Enabled</description>
65689 <description>Enable</description>
65696 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
65703 <description>Read: Disabled</description>
65708 <description>Read: Enabled</description>
65716 <description>Enable</description>
65723 <description>Write '1' to enable interrupt for event COMPARE[8]</description>
65730 <description>Read: Disabled</description>
65735 <description>Read: Enabled</description>
65743 <description>Enable</description>
65750 <description>Write '1' to enable interrupt for event COMPARE[9]</description>
65757 <description>Read: Disabled</description>
65762 <description>Read: Enabled</description>
65770 <description>Enable</description>
65777 <description>Write '1' to enable interrupt for event COMPARE[10]</description>
65784 <description>Read: Disabled</description>
65789 <description>Read: Enabled</description>
65797 <description>Enable</description>
65804 <description>Write '1' to enable interrupt for event COMPARE[11]</description>
65811 <description>Read: Disabled</description>
65816 <description>Read: Enabled</description>
65824 <description>Enable</description>
65831 <description>Write '1' to enable interrupt for event COMPARE[12]</description>
65838 <description>Read: Disabled</description>
65843 <description>Read: Enabled</description>
65851 <description>Enable</description>
65858 <description>Write '1' to enable interrupt for event COMPARE[13]</description>
65865 <description>Read: Disabled</description>
65870 <description>Read: Enabled</description>
65878 <description>Enable</description>
65885 <description>Write '1' to enable interrupt for event COMPARE[14]</description>
65892 <description>Read: Disabled</description>
65897 <description>Read: Enabled</description>
65905 <description>Enable</description>
65912 <description>Write '1' to enable interrupt for event COMPARE[15]</description>
65919 <description>Read: Disabled</description>
65924 <description>Read: Enabled</description>
65932 <description>Enable</description>
65939 <description>Write '1' to enable interrupt for event RTCOMPARESYNC</description>
65946 <description>Read: Disabled</description>
65951 <description>Read: Enabled</description>
65959 <description>Enable</description>
65966 <description>Write '1' to enable interrupt for event SYSCOUNTERVALID</description>
65973 <description>Read: Disabled</description>
65978 <description>Read: Enabled</description>
65986 <description>Enable</description>
65993 <description>Write '1' to enable interrupt for event PWMPERIODEND</description>
66000 <description>Read: Disabled</description>
66005 <description>Read: Enabled</description>
66013 <description>Enable</description>
66022 <description>Disable interrupt</description>
66030 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
66037 <description>Read: Disabled</description>
66042 <description>Read: Enabled</description>
66050 <description>Disable</description>
66057 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
66064 <description>Read: Disabled</description>
66069 <description>Read: Enabled</description>
66077 <description>Disable</description>
66084 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
66091 <description>Read: Disabled</description>
66096 <description>Read: Enabled</description>
66104 <description>Disable</description>
66111 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
66118 <description>Read: Disabled</description>
66123 <description>Read: Enabled</description>
66131 <description>Disable</description>
66138 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
66145 <description>Read: Disabled</description>
66150 <description>Read: Enabled</description>
66158 <description>Disable</description>
66165 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
66172 <description>Read: Disabled</description>
66177 <description>Read: Enabled</description>
66185 <description>Disable</description>
66192 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
66199 <description>Read: Disabled</description>
66204 <description>Read: Enabled</description>
66212 <description>Disable</description>
66219 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
66226 <description>Read: Disabled</description>
66231 <description>Read: Enabled</description>
66239 <description>Disable</description>
66246 <description>Write '1' to disable interrupt for event COMPARE[8]</description>
66253 <description>Read: Disabled</description>
66258 <description>Read: Enabled</description>
66266 <description>Disable</description>
66273 <description>Write '1' to disable interrupt for event COMPARE[9]</description>
66280 <description>Read: Disabled</description>
66285 <description>Read: Enabled</description>
66293 <description>Disable</description>
66300 <description>Write '1' to disable interrupt for event COMPARE[10]</description>
66307 <description>Read: Disabled</description>
66312 <description>Read: Enabled</description>
66320 <description>Disable</description>
66327 <description>Write '1' to disable interrupt for event COMPARE[11]</description>
66334 <description>Read: Disabled</description>
66339 <description>Read: Enabled</description>
66347 <description>Disable</description>
66354 <description>Write '1' to disable interrupt for event COMPARE[12]</description>
66361 <description>Read: Disabled</description>
66366 <description>Read: Enabled</description>
66374 <description>Disable</description>
66381 <description>Write '1' to disable interrupt for event COMPARE[13]</description>
66388 <description>Read: Disabled</description>
66393 <description>Read: Enabled</description>
66401 <description>Disable</description>
66408 <description>Write '1' to disable interrupt for event COMPARE[14]</description>
66415 <description>Read: Disabled</description>
66420 <description>Read: Enabled</description>
66428 <description>Disable</description>
66435 <description>Write '1' to disable interrupt for event COMPARE[15]</description>
66442 <description>Read: Disabled</description>
66447 <description>Read: Enabled</description>
66455 <description>Disable</description>
66462 <description>Write '1' to disable interrupt for event RTCOMPARESYNC</description>
66469 <description>Read: Disabled</description>
66474 <description>Read: Enabled</description>
66482 <description>Disable</description>
66489 <description>Write '1' to disable interrupt for event SYSCOUNTERVALID</description>
66496 <description>Read: Disabled</description>
66501 <description>Read: Enabled</description>
66509 <description>Disable</description>
66516 <description>Write '1' to disable interrupt for event PWMPERIODEND</description>
66523 <description>Read: Disabled</description>
66528 <description>Read: Enabled</description>
66536 <description>Disable</description>
66545 <description>Pending interrupts</description>
66553 <description>Read pending status of interrupt for event COMPARE[0]</description>
66560 <description>Read: Not pending</description>
66565 <description>Read: Pending</description>
66572 <description>Read pending status of interrupt for event COMPARE[1]</description>
66579 <description>Read: Not pending</description>
66584 <description>Read: Pending</description>
66591 <description>Read pending status of interrupt for event COMPARE[2]</description>
66598 <description>Read: Not pending</description>
66603 <description>Read: Pending</description>
66610 <description>Read pending status of interrupt for event COMPARE[3]</description>
66617 <description>Read: Not pending</description>
66622 <description>Read: Pending</description>
66629 <description>Read pending status of interrupt for event COMPARE[4]</description>
66636 <description>Read: Not pending</description>
66641 <description>Read: Pending</description>
66648 <description>Read pending status of interrupt for event COMPARE[5]</description>
66655 <description>Read: Not pending</description>
66660 <description>Read: Pending</description>
66667 <description>Read pending status of interrupt for event COMPARE[6]</description>
66674 <description>Read: Not pending</description>
66679 <description>Read: Pending</description>
66686 <description>Read pending status of interrupt for event COMPARE[7]</description>
66693 <description>Read: Not pending</description>
66698 <description>Read: Pending</description>
66705 <description>Read pending status of interrupt for event COMPARE[8]</description>
66712 <description>Read: Not pending</description>
66717 <description>Read: Pending</description>
66724 <description>Read pending status of interrupt for event COMPARE[9]</description>
66731 <description>Read: Not pending</description>
66736 <description>Read: Pending</description>
66743 <description>Read pending status of interrupt for event COMPARE[10]</description>
66750 <description>Read: Not pending</description>
66755 <description>Read: Pending</description>
66762 <description>Read pending status of interrupt for event COMPARE[11]</description>
66769 <description>Read: Not pending</description>
66774 <description>Read: Pending</description>
66781 <description>Read pending status of interrupt for event COMPARE[12]</description>
66788 <description>Read: Not pending</description>
66793 <description>Read: Pending</description>
66800 <description>Read pending status of interrupt for event COMPARE[13]</description>
66807 <description>Read: Not pending</description>
66812 <description>Read: Pending</description>
66819 <description>Read pending status of interrupt for event COMPARE[14]</description>
66826 <description>Read: Not pending</description>
66831 <description>Read: Pending</description>
66838 <description>Read pending status of interrupt for event COMPARE[15]</description>
66845 <description>Read: Not pending</description>
66850 <description>Read: Pending</description>
66857 <description>Read pending status of interrupt for event RTCOMPARESYNC</description>
66864 <description>Read: Not pending</description>
66869 <description>Read: Pending</description>
66876 <description>Read pending status of interrupt for event SYSCOUNTERVALID</description>
66883 <description>Read: Not pending</description>
66888 <description>Read: Pending</description>
66895 <description>Read pending status of interrupt for event PWMPERIODEND</description>
66902 <description>Read: Not pending</description>
66907 <description>Read: Pending</description>
66916 <description>Enable or disable interrupt</description>
66924 <description>Enable or disable interrupt for event COMPARE[0]</description>
66930 <description>Disable</description>
66935 <description>Enable</description>
66942 <description>Enable or disable interrupt for event COMPARE[1]</description>
66948 <description>Disable</description>
66953 <description>Enable</description>
66960 <description>Enable or disable interrupt for event COMPARE[2]</description>
66966 <description>Disable</description>
66971 <description>Enable</description>
66978 <description>Enable or disable interrupt for event COMPARE[3]</description>
66984 <description>Disable</description>
66989 <description>Enable</description>
66996 <description>Enable or disable interrupt for event COMPARE[4]</description>
67002 <description>Disable</description>
67007 <description>Enable</description>
67014 <description>Enable or disable interrupt for event COMPARE[5]</description>
67020 <description>Disable</description>
67025 <description>Enable</description>
67032 <description>Enable or disable interrupt for event COMPARE[6]</description>
67038 <description>Disable</description>
67043 <description>Enable</description>
67050 <description>Enable or disable interrupt for event COMPARE[7]</description>
67056 <description>Disable</description>
67061 <description>Enable</description>
67068 <description>Enable or disable interrupt for event COMPARE[8]</description>
67074 <description>Disable</description>
67079 <description>Enable</description>
67086 <description>Enable or disable interrupt for event COMPARE[9]</description>
67092 <description>Disable</description>
67097 <description>Enable</description>
67104 <description>Enable or disable interrupt for event COMPARE[10]</description>
67110 <description>Disable</description>
67115 <description>Enable</description>
67122 <description>Enable or disable interrupt for event COMPARE[11]</description>
67128 <description>Disable</description>
67133 <description>Enable</description>
67140 <description>Enable or disable interrupt for event COMPARE[12]</description>
67146 <description>Disable</description>
67151 <description>Enable</description>
67158 <description>Enable or disable interrupt for event COMPARE[13]</description>
67164 <description>Disable</description>
67169 <description>Enable</description>
67176 <description>Enable or disable interrupt for event COMPARE[14]</description>
67182 <description>Disable</description>
67187 <description>Enable</description>
67194 <description>Enable or disable interrupt for event COMPARE[15]</description>
67200 <description>Disable</description>
67205 <description>Enable</description>
67212 <description>Enable or disable interrupt for event RTCOMPARESYNC</description>
67218 <description>Disable</description>
67223 <description>Enable</description>
67230 <description>Enable or disable interrupt for event SYSCOUNTERVALID</description>
67236 <description>Disable</description>
67241 <description>Enable</description>
67248 <description>Enable or disable interrupt for event PWMPERIODEND</description>
67254 <description>Disable</description>
67259 <description>Enable</description>
67268 <description>Enable interrupt</description>
67276 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
67283 <description>Read: Disabled</description>
67288 <description>Read: Enabled</description>
67296 <description>Enable</description>
67303 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
67310 <description>Read: Disabled</description>
67315 <description>Read: Enabled</description>
67323 <description>Enable</description>
67330 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
67337 <description>Read: Disabled</description>
67342 <description>Read: Enabled</description>
67350 <description>Enable</description>
67357 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
67364 <description>Read: Disabled</description>
67369 <description>Read: Enabled</description>
67377 <description>Enable</description>
67384 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
67391 <description>Read: Disabled</description>
67396 <description>Read: Enabled</description>
67404 <description>Enable</description>
67411 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
67418 <description>Read: Disabled</description>
67423 <description>Read: Enabled</description>
67431 <description>Enable</description>
67438 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
67445 <description>Read: Disabled</description>
67450 <description>Read: Enabled</description>
67458 <description>Enable</description>
67465 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
67472 <description>Read: Disabled</description>
67477 <description>Read: Enabled</description>
67485 <description>Enable</description>
67492 <description>Write '1' to enable interrupt for event COMPARE[8]</description>
67499 <description>Read: Disabled</description>
67504 <description>Read: Enabled</description>
67512 <description>Enable</description>
67519 <description>Write '1' to enable interrupt for event COMPARE[9]</description>
67526 <description>Read: Disabled</description>
67531 <description>Read: Enabled</description>
67539 <description>Enable</description>
67546 <description>Write '1' to enable interrupt for event COMPARE[10]</description>
67553 <description>Read: Disabled</description>
67558 <description>Read: Enabled</description>
67566 <description>Enable</description>
67573 <description>Write '1' to enable interrupt for event COMPARE[11]</description>
67580 <description>Read: Disabled</description>
67585 <description>Read: Enabled</description>
67593 <description>Enable</description>
67600 <description>Write '1' to enable interrupt for event COMPARE[12]</description>
67607 <description>Read: Disabled</description>
67612 <description>Read: Enabled</description>
67620 <description>Enable</description>
67627 <description>Write '1' to enable interrupt for event COMPARE[13]</description>
67634 <description>Read: Disabled</description>
67639 <description>Read: Enabled</description>
67647 <description>Enable</description>
67654 <description>Write '1' to enable interrupt for event COMPARE[14]</description>
67661 <description>Read: Disabled</description>
67666 <description>Read: Enabled</description>
67674 <description>Enable</description>
67681 <description>Write '1' to enable interrupt for event COMPARE[15]</description>
67688 <description>Read: Disabled</description>
67693 <description>Read: Enabled</description>
67701 <description>Enable</description>
67708 <description>Write '1' to enable interrupt for event RTCOMPARESYNC</description>
67715 <description>Read: Disabled</description>
67720 <description>Read: Enabled</description>
67728 <description>Enable</description>
67735 <description>Write '1' to enable interrupt for event SYSCOUNTERVALID</description>
67742 <description>Read: Disabled</description>
67747 <description>Read: Enabled</description>
67755 <description>Enable</description>
67762 <description>Write '1' to enable interrupt for event PWMPERIODEND</description>
67769 <description>Read: Disabled</description>
67774 <description>Read: Enabled</description>
67782 <description>Enable</description>
67791 <description>Disable interrupt</description>
67799 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
67806 <description>Read: Disabled</description>
67811 <description>Read: Enabled</description>
67819 <description>Disable</description>
67826 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
67833 <description>Read: Disabled</description>
67838 <description>Read: Enabled</description>
67846 <description>Disable</description>
67853 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
67860 <description>Read: Disabled</description>
67865 <description>Read: Enabled</description>
67873 <description>Disable</description>
67880 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
67887 <description>Read: Disabled</description>
67892 <description>Read: Enabled</description>
67900 <description>Disable</description>
67907 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
67914 <description>Read: Disabled</description>
67919 <description>Read: Enabled</description>
67927 <description>Disable</description>
67934 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
67941 <description>Read: Disabled</description>
67946 <description>Read: Enabled</description>
67954 <description>Disable</description>
67961 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
67968 <description>Read: Disabled</description>
67973 <description>Read: Enabled</description>
67981 <description>Disable</description>
67988 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
67995 <description>Read: Disabled</description>
68000 <description>Read: Enabled</description>
68008 <description>Disable</description>
68015 <description>Write '1' to disable interrupt for event COMPARE[8]</description>
68022 <description>Read: Disabled</description>
68027 <description>Read: Enabled</description>
68035 <description>Disable</description>
68042 <description>Write '1' to disable interrupt for event COMPARE[9]</description>
68049 <description>Read: Disabled</description>
68054 <description>Read: Enabled</description>
68062 <description>Disable</description>
68069 <description>Write '1' to disable interrupt for event COMPARE[10]</description>
68076 <description>Read: Disabled</description>
68081 <description>Read: Enabled</description>
68089 <description>Disable</description>
68096 <description>Write '1' to disable interrupt for event COMPARE[11]</description>
68103 <description>Read: Disabled</description>
68108 <description>Read: Enabled</description>
68116 <description>Disable</description>
68123 <description>Write '1' to disable interrupt for event COMPARE[12]</description>
68130 <description>Read: Disabled</description>
68135 <description>Read: Enabled</description>
68143 <description>Disable</description>
68150 <description>Write '1' to disable interrupt for event COMPARE[13]</description>
68157 <description>Read: Disabled</description>
68162 <description>Read: Enabled</description>
68170 <description>Disable</description>
68177 <description>Write '1' to disable interrupt for event COMPARE[14]</description>
68184 <description>Read: Disabled</description>
68189 <description>Read: Enabled</description>
68197 <description>Disable</description>
68204 <description>Write '1' to disable interrupt for event COMPARE[15]</description>
68211 <description>Read: Disabled</description>
68216 <description>Read: Enabled</description>
68224 <description>Disable</description>
68231 <description>Write '1' to disable interrupt for event RTCOMPARESYNC</description>
68238 <description>Read: Disabled</description>
68243 <description>Read: Enabled</description>
68251 <description>Disable</description>
68258 <description>Write '1' to disable interrupt for event SYSCOUNTERVALID</description>
68265 <description>Read: Disabled</description>
68270 <description>Read: Enabled</description>
68278 <description>Disable</description>
68285 <description>Write '1' to disable interrupt for event PWMPERIODEND</description>
68292 <description>Read: Disabled</description>
68297 <description>Read: Enabled</description>
68305 <description>Disable</description>
68314 <description>Pending interrupts</description>
68322 <description>Read pending status of interrupt for event COMPARE[0]</description>
68329 <description>Read: Not pending</description>
68334 <description>Read: Pending</description>
68341 <description>Read pending status of interrupt for event COMPARE[1]</description>
68348 <description>Read: Not pending</description>
68353 <description>Read: Pending</description>
68360 <description>Read pending status of interrupt for event COMPARE[2]</description>
68367 <description>Read: Not pending</description>
68372 <description>Read: Pending</description>
68379 <description>Read pending status of interrupt for event COMPARE[3]</description>
68386 <description>Read: Not pending</description>
68391 <description>Read: Pending</description>
68398 <description>Read pending status of interrupt for event COMPARE[4]</description>
68405 <description>Read: Not pending</description>
68410 <description>Read: Pending</description>
68417 <description>Read pending status of interrupt for event COMPARE[5]</description>
68424 <description>Read: Not pending</description>
68429 <description>Read: Pending</description>
68436 <description>Read pending status of interrupt for event COMPARE[6]</description>
68443 <description>Read: Not pending</description>
68448 <description>Read: Pending</description>
68455 <description>Read pending status of interrupt for event COMPARE[7]</description>
68462 <description>Read: Not pending</description>
68467 <description>Read: Pending</description>
68474 <description>Read pending status of interrupt for event COMPARE[8]</description>
68481 <description>Read: Not pending</description>
68486 <description>Read: Pending</description>
68493 <description>Read pending status of interrupt for event COMPARE[9]</description>
68500 <description>Read: Not pending</description>
68505 <description>Read: Pending</description>
68512 <description>Read pending status of interrupt for event COMPARE[10]</description>
68519 <description>Read: Not pending</description>
68524 <description>Read: Pending</description>
68531 <description>Read pending status of interrupt for event COMPARE[11]</description>
68538 <description>Read: Not pending</description>
68543 <description>Read: Pending</description>
68550 <description>Read pending status of interrupt for event COMPARE[12]</description>
68557 <description>Read: Not pending</description>
68562 <description>Read: Pending</description>
68569 <description>Read pending status of interrupt for event COMPARE[13]</description>
68576 <description>Read: Not pending</description>
68581 <description>Read: Pending</description>
68588 <description>Read pending status of interrupt for event COMPARE[14]</description>
68595 <description>Read: Not pending</description>
68600 <description>Read: Pending</description>
68607 <description>Read pending status of interrupt for event COMPARE[15]</description>
68614 <description>Read: Not pending</description>
68619 <description>Read: Pending</description>
68626 <description>Read pending status of interrupt for event RTCOMPARESYNC</description>
68633 <description>Read: Not pending</description>
68638 <description>Read: Pending</description>
68645 <description>Read pending status of interrupt for event SYSCOUNTERVALID</description>
68652 <description>Read: Not pending</description>
68657 <description>Read: Pending</description>
68664 <description>Read pending status of interrupt for event PWMPERIODEND</description>
68671 <description>Read: Not pending</description>
68676 <description>Read: Pending</description>
68685 <description>Enable or disable interrupt</description>
68693 <description>Enable or disable interrupt for event COMPARE[0]</description>
68699 <description>Disable</description>
68704 <description>Enable</description>
68711 <description>Enable or disable interrupt for event COMPARE[1]</description>
68717 <description>Disable</description>
68722 <description>Enable</description>
68729 <description>Enable or disable interrupt for event COMPARE[2]</description>
68735 <description>Disable</description>
68740 <description>Enable</description>
68747 <description>Enable or disable interrupt for event COMPARE[3]</description>
68753 <description>Disable</description>
68758 <description>Enable</description>
68765 <description>Enable or disable interrupt for event COMPARE[4]</description>
68771 <description>Disable</description>
68776 <description>Enable</description>
68783 <description>Enable or disable interrupt for event COMPARE[5]</description>
68789 <description>Disable</description>
68794 <description>Enable</description>
68801 <description>Enable or disable interrupt for event COMPARE[6]</description>
68807 <description>Disable</description>
68812 <description>Enable</description>
68819 <description>Enable or disable interrupt for event COMPARE[7]</description>
68825 <description>Disable</description>
68830 <description>Enable</description>
68837 <description>Enable or disable interrupt for event COMPARE[8]</description>
68843 <description>Disable</description>
68848 <description>Enable</description>
68855 <description>Enable or disable interrupt for event COMPARE[9]</description>
68861 <description>Disable</description>
68866 <description>Enable</description>
68873 <description>Enable or disable interrupt for event COMPARE[10]</description>
68879 <description>Disable</description>
68884 <description>Enable</description>
68891 <description>Enable or disable interrupt for event COMPARE[11]</description>
68897 <description>Disable</description>
68902 <description>Enable</description>
68909 <description>Enable or disable interrupt for event COMPARE[12]</description>
68915 <description>Disable</description>
68920 <description>Enable</description>
68927 <description>Enable or disable interrupt for event COMPARE[13]</description>
68933 <description>Disable</description>
68938 <description>Enable</description>
68945 <description>Enable or disable interrupt for event COMPARE[14]</description>
68951 <description>Disable</description>
68956 <description>Enable</description>
68963 <description>Enable or disable interrupt for event COMPARE[15]</description>
68969 <description>Disable</description>
68974 <description>Enable</description>
68981 <description>Enable or disable interrupt for event RTCOMPARESYNC</description>
68987 <description>Disable</description>
68992 <description>Enable</description>
68999 <description>Enable or disable interrupt for event SYSCOUNTERVALID</description>
69005 <description>Disable</description>
69010 <description>Enable</description>
69017 <description>Enable or disable interrupt for event PWMPERIODEND</description>
69023 <description>Disable</description>
69028 <description>Enable</description>
69037 <description>Enable interrupt</description>
69045 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
69052 <description>Read: Disabled</description>
69057 <description>Read: Enabled</description>
69065 <description>Enable</description>
69072 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
69079 <description>Read: Disabled</description>
69084 <description>Read: Enabled</description>
69092 <description>Enable</description>
69099 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
69106 <description>Read: Disabled</description>
69111 <description>Read: Enabled</description>
69119 <description>Enable</description>
69126 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
69133 <description>Read: Disabled</description>
69138 <description>Read: Enabled</description>
69146 <description>Enable</description>
69153 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
69160 <description>Read: Disabled</description>
69165 <description>Read: Enabled</description>
69173 <description>Enable</description>
69180 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
69187 <description>Read: Disabled</description>
69192 <description>Read: Enabled</description>
69200 <description>Enable</description>
69207 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
69214 <description>Read: Disabled</description>
69219 <description>Read: Enabled</description>
69227 <description>Enable</description>
69234 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
69241 <description>Read: Disabled</description>
69246 <description>Read: Enabled</description>
69254 <description>Enable</description>
69261 <description>Write '1' to enable interrupt for event COMPARE[8]</description>
69268 <description>Read: Disabled</description>
69273 <description>Read: Enabled</description>
69281 <description>Enable</description>
69288 <description>Write '1' to enable interrupt for event COMPARE[9]</description>
69295 <description>Read: Disabled</description>
69300 <description>Read: Enabled</description>
69308 <description>Enable</description>
69315 <description>Write '1' to enable interrupt for event COMPARE[10]</description>
69322 <description>Read: Disabled</description>
69327 <description>Read: Enabled</description>
69335 <description>Enable</description>
69342 <description>Write '1' to enable interrupt for event COMPARE[11]</description>
69349 <description>Read: Disabled</description>
69354 <description>Read: Enabled</description>
69362 <description>Enable</description>
69369 <description>Write '1' to enable interrupt for event COMPARE[12]</description>
69376 <description>Read: Disabled</description>
69381 <description>Read: Enabled</description>
69389 <description>Enable</description>
69396 <description>Write '1' to enable interrupt for event COMPARE[13]</description>
69403 <description>Read: Disabled</description>
69408 <description>Read: Enabled</description>
69416 <description>Enable</description>
69423 <description>Write '1' to enable interrupt for event COMPARE[14]</description>
69430 <description>Read: Disabled</description>
69435 <description>Read: Enabled</description>
69443 <description>Enable</description>
69450 <description>Write '1' to enable interrupt for event COMPARE[15]</description>
69457 <description>Read: Disabled</description>
69462 <description>Read: Enabled</description>
69470 <description>Enable</description>
69477 <description>Write '1' to enable interrupt for event RTCOMPARESYNC</description>
69484 <description>Read: Disabled</description>
69489 <description>Read: Enabled</description>
69497 <description>Enable</description>
69504 <description>Write '1' to enable interrupt for event SYSCOUNTERVALID</description>
69511 <description>Read: Disabled</description>
69516 <description>Read: Enabled</description>
69524 <description>Enable</description>
69531 <description>Write '1' to enable interrupt for event PWMPERIODEND</description>
69538 <description>Read: Disabled</description>
69543 <description>Read: Enabled</description>
69551 <description>Enable</description>
69560 <description>Disable interrupt</description>
69568 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
69575 <description>Read: Disabled</description>
69580 <description>Read: Enabled</description>
69588 <description>Disable</description>
69595 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
69602 <description>Read: Disabled</description>
69607 <description>Read: Enabled</description>
69615 <description>Disable</description>
69622 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
69629 <description>Read: Disabled</description>
69634 <description>Read: Enabled</description>
69642 <description>Disable</description>
69649 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
69656 <description>Read: Disabled</description>
69661 <description>Read: Enabled</description>
69669 <description>Disable</description>
69676 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
69683 <description>Read: Disabled</description>
69688 <description>Read: Enabled</description>
69696 <description>Disable</description>
69703 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
69710 <description>Read: Disabled</description>
69715 <description>Read: Enabled</description>
69723 <description>Disable</description>
69730 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
69737 <description>Read: Disabled</description>
69742 <description>Read: Enabled</description>
69750 <description>Disable</description>
69757 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
69764 <description>Read: Disabled</description>
69769 <description>Read: Enabled</description>
69777 <description>Disable</description>
69784 <description>Write '1' to disable interrupt for event COMPARE[8]</description>
69791 <description>Read: Disabled</description>
69796 <description>Read: Enabled</description>
69804 <description>Disable</description>
69811 <description>Write '1' to disable interrupt for event COMPARE[9]</description>
69818 <description>Read: Disabled</description>
69823 <description>Read: Enabled</description>
69831 <description>Disable</description>
69838 <description>Write '1' to disable interrupt for event COMPARE[10]</description>
69845 <description>Read: Disabled</description>
69850 <description>Read: Enabled</description>
69858 <description>Disable</description>
69865 <description>Write '1' to disable interrupt for event COMPARE[11]</description>
69872 <description>Read: Disabled</description>
69877 <description>Read: Enabled</description>
69885 <description>Disable</description>
69892 <description>Write '1' to disable interrupt for event COMPARE[12]</description>
69899 <description>Read: Disabled</description>
69904 <description>Read: Enabled</description>
69912 <description>Disable</description>
69919 <description>Write '1' to disable interrupt for event COMPARE[13]</description>
69926 <description>Read: Disabled</description>
69931 <description>Read: Enabled</description>
69939 <description>Disable</description>
69946 <description>Write '1' to disable interrupt for event COMPARE[14]</description>
69953 <description>Read: Disabled</description>
69958 <description>Read: Enabled</description>
69966 <description>Disable</description>
69973 <description>Write '1' to disable interrupt for event COMPARE[15]</description>
69980 <description>Read: Disabled</description>
69985 <description>Read: Enabled</description>
69993 <description>Disable</description>
70000 <description>Write '1' to disable interrupt for event RTCOMPARESYNC</description>
70007 <description>Read: Disabled</description>
70012 <description>Read: Enabled</description>
70020 <description>Disable</description>
70027 <description>Write '1' to disable interrupt for event SYSCOUNTERVALID</description>
70034 <description>Read: Disabled</description>
70039 <description>Read: Enabled</description>
70047 <description>Disable</description>
70054 <description>Write '1' to disable interrupt for event PWMPERIODEND</description>
70061 <description>Read: Disabled</description>
70066 <description>Read: Enabled</description>
70074 <description>Disable</description>
70083 <description>Pending interrupts</description>
70091 <description>Read pending status of interrupt for event COMPARE[0]</description>
70098 <description>Read: Not pending</description>
70103 <description>Read: Pending</description>
70110 <description>Read pending status of interrupt for event COMPARE[1]</description>
70117 <description>Read: Not pending</description>
70122 <description>Read: Pending</description>
70129 <description>Read pending status of interrupt for event COMPARE[2]</description>
70136 <description>Read: Not pending</description>
70141 <description>Read: Pending</description>
70148 <description>Read pending status of interrupt for event COMPARE[3]</description>
70155 <description>Read: Not pending</description>
70160 <description>Read: Pending</description>
70167 <description>Read pending status of interrupt for event COMPARE[4]</description>
70174 <description>Read: Not pending</description>
70179 <description>Read: Pending</description>
70186 <description>Read pending status of interrupt for event COMPARE[5]</description>
70193 <description>Read: Not pending</description>
70198 <description>Read: Pending</description>
70205 <description>Read pending status of interrupt for event COMPARE[6]</description>
70212 <description>Read: Not pending</description>
70217 <description>Read: Pending</description>
70224 <description>Read pending status of interrupt for event COMPARE[7]</description>
70231 <description>Read: Not pending</description>
70236 <description>Read: Pending</description>
70243 <description>Read pending status of interrupt for event COMPARE[8]</description>
70250 <description>Read: Not pending</description>
70255 <description>Read: Pending</description>
70262 <description>Read pending status of interrupt for event COMPARE[9]</description>
70269 <description>Read: Not pending</description>
70274 <description>Read: Pending</description>
70281 <description>Read pending status of interrupt for event COMPARE[10]</description>
70288 <description>Read: Not pending</description>
70293 <description>Read: Pending</description>
70300 <description>Read pending status of interrupt for event COMPARE[11]</description>
70307 <description>Read: Not pending</description>
70312 <description>Read: Pending</description>
70319 <description>Read pending status of interrupt for event COMPARE[12]</description>
70326 <description>Read: Not pending</description>
70331 <description>Read: Pending</description>
70338 <description>Read pending status of interrupt for event COMPARE[13]</description>
70345 <description>Read: Not pending</description>
70350 <description>Read: Pending</description>
70357 <description>Read pending status of interrupt for event COMPARE[14]</description>
70364 <description>Read: Not pending</description>
70369 <description>Read: Pending</description>
70376 <description>Read pending status of interrupt for event COMPARE[15]</description>
70383 <description>Read: Not pending</description>
70388 <description>Read: Pending</description>
70395 <description>Read pending status of interrupt for event RTCOMPARESYNC</description>
70402 <description>Read: Not pending</description>
70407 <description>Read: Pending</description>
70414 <description>Read pending status of interrupt for event SYSCOUNTERVALID</description>
70421 <description>Read: Not pending</description>
70426 <description>Read: Pending</description>
70433 <description>Read pending status of interrupt for event PWMPERIODEND</description>
70440 <description>Read: Not pending</description>
70445 <description>Read: Pending</description>
70454 <description>Enable or disable interrupt</description>
70462 <description>Enable or disable interrupt for event COMPARE[0]</description>
70468 <description>Disable</description>
70473 <description>Enable</description>
70480 <description>Enable or disable interrupt for event COMPARE[1]</description>
70486 <description>Disable</description>
70491 <description>Enable</description>
70498 <description>Enable or disable interrupt for event COMPARE[2]</description>
70504 <description>Disable</description>
70509 <description>Enable</description>
70516 <description>Enable or disable interrupt for event COMPARE[3]</description>
70522 <description>Disable</description>
70527 <description>Enable</description>
70534 <description>Enable or disable interrupt for event COMPARE[4]</description>
70540 <description>Disable</description>
70545 <description>Enable</description>
70552 <description>Enable or disable interrupt for event COMPARE[5]</description>
70558 <description>Disable</description>
70563 <description>Enable</description>
70570 <description>Enable or disable interrupt for event COMPARE[6]</description>
70576 <description>Disable</description>
70581 <description>Enable</description>
70588 <description>Enable or disable interrupt for event COMPARE[7]</description>
70594 <description>Disable</description>
70599 <description>Enable</description>
70606 <description>Enable or disable interrupt for event COMPARE[8]</description>
70612 <description>Disable</description>
70617 <description>Enable</description>
70624 <description>Enable or disable interrupt for event COMPARE[9]</description>
70630 <description>Disable</description>
70635 <description>Enable</description>
70642 <description>Enable or disable interrupt for event COMPARE[10]</description>
70648 <description>Disable</description>
70653 <description>Enable</description>
70660 <description>Enable or disable interrupt for event COMPARE[11]</description>
70666 <description>Disable</description>
70671 <description>Enable</description>
70678 <description>Enable or disable interrupt for event COMPARE[12]</description>
70684 <description>Disable</description>
70689 <description>Enable</description>
70696 <description>Enable or disable interrupt for event COMPARE[13]</description>
70702 <description>Disable</description>
70707 <description>Enable</description>
70714 <description>Enable or disable interrupt for event COMPARE[14]</description>
70720 <description>Disable</description>
70725 <description>Enable</description>
70732 <description>Enable or disable interrupt for event COMPARE[15]</description>
70738 <description>Disable</description>
70743 <description>Enable</description>
70750 <description>Enable or disable interrupt for event RTCOMPARESYNC</description>
70756 <description>Disable</description>
70761 <description>Enable</description>
70768 <description>Enable or disable interrupt for event SYSCOUNTERVALID</description>
70774 <description>Disable</description>
70779 <description>Enable</description>
70786 <description>Enable or disable interrupt for event PWMPERIODEND</description>
70792 <description>Disable</description>
70797 <description>Enable</description>
70806 <description>Enable interrupt</description>
70814 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
70821 <description>Read: Disabled</description>
70826 <description>Read: Enabled</description>
70834 <description>Enable</description>
70841 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
70848 <description>Read: Disabled</description>
70853 <description>Read: Enabled</description>
70861 <description>Enable</description>
70868 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
70875 <description>Read: Disabled</description>
70880 <description>Read: Enabled</description>
70888 <description>Enable</description>
70895 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
70902 <description>Read: Disabled</description>
70907 <description>Read: Enabled</description>
70915 <description>Enable</description>
70922 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
70929 <description>Read: Disabled</description>
70934 <description>Read: Enabled</description>
70942 <description>Enable</description>
70949 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
70956 <description>Read: Disabled</description>
70961 <description>Read: Enabled</description>
70969 <description>Enable</description>
70976 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
70983 <description>Read: Disabled</description>
70988 <description>Read: Enabled</description>
70996 <description>Enable</description>
71003 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
71010 <description>Read: Disabled</description>
71015 <description>Read: Enabled</description>
71023 <description>Enable</description>
71030 <description>Write '1' to enable interrupt for event COMPARE[8]</description>
71037 <description>Read: Disabled</description>
71042 <description>Read: Enabled</description>
71050 <description>Enable</description>
71057 <description>Write '1' to enable interrupt for event COMPARE[9]</description>
71064 <description>Read: Disabled</description>
71069 <description>Read: Enabled</description>
71077 <description>Enable</description>
71084 <description>Write '1' to enable interrupt for event COMPARE[10]</description>
71091 <description>Read: Disabled</description>
71096 <description>Read: Enabled</description>
71104 <description>Enable</description>
71111 <description>Write '1' to enable interrupt for event COMPARE[11]</description>
71118 <description>Read: Disabled</description>
71123 <description>Read: Enabled</description>
71131 <description>Enable</description>
71138 <description>Write '1' to enable interrupt for event COMPARE[12]</description>
71145 <description>Read: Disabled</description>
71150 <description>Read: Enabled</description>
71158 <description>Enable</description>
71165 <description>Write '1' to enable interrupt for event COMPARE[13]</description>
71172 <description>Read: Disabled</description>
71177 <description>Read: Enabled</description>
71185 <description>Enable</description>
71192 <description>Write '1' to enable interrupt for event COMPARE[14]</description>
71199 <description>Read: Disabled</description>
71204 <description>Read: Enabled</description>
71212 <description>Enable</description>
71219 <description>Write '1' to enable interrupt for event COMPARE[15]</description>
71226 <description>Read: Disabled</description>
71231 <description>Read: Enabled</description>
71239 <description>Enable</description>
71246 <description>Write '1' to enable interrupt for event RTCOMPARESYNC</description>
71253 <description>Read: Disabled</description>
71258 <description>Read: Enabled</description>
71266 <description>Enable</description>
71273 <description>Write '1' to enable interrupt for event SYSCOUNTERVALID</description>
71280 <description>Read: Disabled</description>
71285 <description>Read: Enabled</description>
71293 <description>Enable</description>
71300 <description>Write '1' to enable interrupt for event PWMPERIODEND</description>
71307 <description>Read: Disabled</description>
71312 <description>Read: Enabled</description>
71320 <description>Enable</description>
71329 <description>Disable interrupt</description>
71337 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
71344 <description>Read: Disabled</description>
71349 <description>Read: Enabled</description>
71357 <description>Disable</description>
71364 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
71371 <description>Read: Disabled</description>
71376 <description>Read: Enabled</description>
71384 <description>Disable</description>
71391 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
71398 <description>Read: Disabled</description>
71403 <description>Read: Enabled</description>
71411 <description>Disable</description>
71418 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
71425 <description>Read: Disabled</description>
71430 <description>Read: Enabled</description>
71438 <description>Disable</description>
71445 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
71452 <description>Read: Disabled</description>
71457 <description>Read: Enabled</description>
71465 <description>Disable</description>
71472 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
71479 <description>Read: Disabled</description>
71484 <description>Read: Enabled</description>
71492 <description>Disable</description>
71499 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
71506 <description>Read: Disabled</description>
71511 <description>Read: Enabled</description>
71519 <description>Disable</description>
71526 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
71533 <description>Read: Disabled</description>
71538 <description>Read: Enabled</description>
71546 <description>Disable</description>
71553 <description>Write '1' to disable interrupt for event COMPARE[8]</description>
71560 <description>Read: Disabled</description>
71565 <description>Read: Enabled</description>
71573 <description>Disable</description>
71580 <description>Write '1' to disable interrupt for event COMPARE[9]</description>
71587 <description>Read: Disabled</description>
71592 <description>Read: Enabled</description>
71600 <description>Disable</description>
71607 <description>Write '1' to disable interrupt for event COMPARE[10]</description>
71614 <description>Read: Disabled</description>
71619 <description>Read: Enabled</description>
71627 <description>Disable</description>
71634 <description>Write '1' to disable interrupt for event COMPARE[11]</description>
71641 <description>Read: Disabled</description>
71646 <description>Read: Enabled</description>
71654 <description>Disable</description>
71661 <description>Write '1' to disable interrupt for event COMPARE[12]</description>
71668 <description>Read: Disabled</description>
71673 <description>Read: Enabled</description>
71681 <description>Disable</description>
71688 <description>Write '1' to disable interrupt for event COMPARE[13]</description>
71695 <description>Read: Disabled</description>
71700 <description>Read: Enabled</description>
71708 <description>Disable</description>
71715 <description>Write '1' to disable interrupt for event COMPARE[14]</description>
71722 <description>Read: Disabled</description>
71727 <description>Read: Enabled</description>
71735 <description>Disable</description>
71742 <description>Write '1' to disable interrupt for event COMPARE[15]</description>
71749 <description>Read: Disabled</description>
71754 <description>Read: Enabled</description>
71762 <description>Disable</description>
71769 <description>Write '1' to disable interrupt for event RTCOMPARESYNC</description>
71776 <description>Read: Disabled</description>
71781 <description>Read: Enabled</description>
71789 <description>Disable</description>
71796 <description>Write '1' to disable interrupt for event SYSCOUNTERVALID</description>
71803 <description>Read: Disabled</description>
71808 <description>Read: Enabled</description>
71816 <description>Disable</description>
71823 <description>Write '1' to disable interrupt for event PWMPERIODEND</description>
71830 <description>Read: Disabled</description>
71835 <description>Read: Enabled</description>
71843 <description>Disable</description>
71852 <description>Pending interrupts</description>
71860 <description>Read pending status of interrupt for event COMPARE[0]</description>
71867 <description>Read: Not pending</description>
71872 <description>Read: Pending</description>
71879 <description>Read pending status of interrupt for event COMPARE[1]</description>
71886 <description>Read: Not pending</description>
71891 <description>Read: Pending</description>
71898 <description>Read pending status of interrupt for event COMPARE[2]</description>
71905 <description>Read: Not pending</description>
71910 <description>Read: Pending</description>
71917 <description>Read pending status of interrupt for event COMPARE[3]</description>
71924 <description>Read: Not pending</description>
71929 <description>Read: Pending</description>
71936 <description>Read pending status of interrupt for event COMPARE[4]</description>
71943 <description>Read: Not pending</description>
71948 <description>Read: Pending</description>
71955 <description>Read pending status of interrupt for event COMPARE[5]</description>
71962 <description>Read: Not pending</description>
71967 <description>Read: Pending</description>
71974 <description>Read pending status of interrupt for event COMPARE[6]</description>
71981 <description>Read: Not pending</description>
71986 <description>Read: Pending</description>
71993 <description>Read pending status of interrupt for event COMPARE[7]</description>
72000 <description>Read: Not pending</description>
72005 <description>Read: Pending</description>
72012 <description>Read pending status of interrupt for event COMPARE[8]</description>
72019 <description>Read: Not pending</description>
72024 <description>Read: Pending</description>
72031 <description>Read pending status of interrupt for event COMPARE[9]</description>
72038 <description>Read: Not pending</description>
72043 <description>Read: Pending</description>
72050 <description>Read pending status of interrupt for event COMPARE[10]</description>
72057 <description>Read: Not pending</description>
72062 <description>Read: Pending</description>
72069 <description>Read pending status of interrupt for event COMPARE[11]</description>
72076 <description>Read: Not pending</description>
72081 <description>Read: Pending</description>
72088 <description>Read pending status of interrupt for event COMPARE[12]</description>
72095 <description>Read: Not pending</description>
72100 <description>Read: Pending</description>
72107 <description>Read pending status of interrupt for event COMPARE[13]</description>
72114 <description>Read: Not pending</description>
72119 <description>Read: Pending</description>
72126 <description>Read pending status of interrupt for event COMPARE[14]</description>
72133 <description>Read: Not pending</description>
72138 <description>Read: Pending</description>
72145 <description>Read pending status of interrupt for event COMPARE[15]</description>
72152 <description>Read: Not pending</description>
72157 <description>Read: Pending</description>
72164 <description>Read pending status of interrupt for event RTCOMPARESYNC</description>
72171 <description>Read: Not pending</description>
72176 <description>Read: Pending</description>
72183 <description>Read pending status of interrupt for event SYSCOUNTERVALID</description>
72190 <description>Read: Not pending</description>
72195 <description>Read: Pending</description>
72202 <description>Read pending status of interrupt for event PWMPERIODEND</description>
72209 <description>Read: Not pending</description>
72214 <description>Read: Pending</description>
72223 <description>Enable or disable interrupt</description>
72231 <description>Enable or disable interrupt for event COMPARE[0]</description>
72237 <description>Disable</description>
72242 <description>Enable</description>
72249 <description>Enable or disable interrupt for event COMPARE[1]</description>
72255 <description>Disable</description>
72260 <description>Enable</description>
72267 <description>Enable or disable interrupt for event COMPARE[2]</description>
72273 <description>Disable</description>
72278 <description>Enable</description>
72285 <description>Enable or disable interrupt for event COMPARE[3]</description>
72291 <description>Disable</description>
72296 <description>Enable</description>
72303 <description>Enable or disable interrupt for event COMPARE[4]</description>
72309 <description>Disable</description>
72314 <description>Enable</description>
72321 <description>Enable or disable interrupt for event COMPARE[5]</description>
72327 <description>Disable</description>
72332 <description>Enable</description>
72339 <description>Enable or disable interrupt for event COMPARE[6]</description>
72345 <description>Disable</description>
72350 <description>Enable</description>
72357 <description>Enable or disable interrupt for event COMPARE[7]</description>
72363 <description>Disable</description>
72368 <description>Enable</description>
72375 <description>Enable or disable interrupt for event COMPARE[8]</description>
72381 <description>Disable</description>
72386 <description>Enable</description>
72393 <description>Enable or disable interrupt for event COMPARE[9]</description>
72399 <description>Disable</description>
72404 <description>Enable</description>
72411 <description>Enable or disable interrupt for event COMPARE[10]</description>
72417 <description>Disable</description>
72422 <description>Enable</description>
72429 <description>Enable or disable interrupt for event COMPARE[11]</description>
72435 <description>Disable</description>
72440 <description>Enable</description>
72447 <description>Enable or disable interrupt for event COMPARE[12]</description>
72453 <description>Disable</description>
72458 <description>Enable</description>
72465 <description>Enable or disable interrupt for event COMPARE[13]</description>
72471 <description>Disable</description>
72476 <description>Enable</description>
72483 <description>Enable or disable interrupt for event COMPARE[14]</description>
72489 <description>Disable</description>
72494 <description>Enable</description>
72501 <description>Enable or disable interrupt for event COMPARE[15]</description>
72507 <description>Disable</description>
72512 <description>Enable</description>
72519 <description>Enable or disable interrupt for event RTCOMPARESYNC</description>
72525 <description>Disable</description>
72530 <description>Enable</description>
72537 <description>Enable or disable interrupt for event SYSCOUNTERVALID</description>
72543 <description>Disable</description>
72548 <description>Enable</description>
72555 <description>Enable or disable interrupt for event PWMPERIODEND</description>
72561 <description>Disable</description>
72566 <description>Enable</description>
72575 <description>Enable interrupt</description>
72583 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
72590 <description>Read: Disabled</description>
72595 <description>Read: Enabled</description>
72603 <description>Enable</description>
72610 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
72617 <description>Read: Disabled</description>
72622 <description>Read: Enabled</description>
72630 <description>Enable</description>
72637 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
72644 <description>Read: Disabled</description>
72649 <description>Read: Enabled</description>
72657 <description>Enable</description>
72664 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
72671 <description>Read: Disabled</description>
72676 <description>Read: Enabled</description>
72684 <description>Enable</description>
72691 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
72698 <description>Read: Disabled</description>
72703 <description>Read: Enabled</description>
72711 <description>Enable</description>
72718 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
72725 <description>Read: Disabled</description>
72730 <description>Read: Enabled</description>
72738 <description>Enable</description>
72745 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
72752 <description>Read: Disabled</description>
72757 <description>Read: Enabled</description>
72765 <description>Enable</description>
72772 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
72779 <description>Read: Disabled</description>
72784 <description>Read: Enabled</description>
72792 <description>Enable</description>
72799 <description>Write '1' to enable interrupt for event COMPARE[8]</description>
72806 <description>Read: Disabled</description>
72811 <description>Read: Enabled</description>
72819 <description>Enable</description>
72826 <description>Write '1' to enable interrupt for event COMPARE[9]</description>
72833 <description>Read: Disabled</description>
72838 <description>Read: Enabled</description>
72846 <description>Enable</description>
72853 <description>Write '1' to enable interrupt for event COMPARE[10]</description>
72860 <description>Read: Disabled</description>
72865 <description>Read: Enabled</description>
72873 <description>Enable</description>
72880 <description>Write '1' to enable interrupt for event COMPARE[11]</description>
72887 <description>Read: Disabled</description>
72892 <description>Read: Enabled</description>
72900 <description>Enable</description>
72907 <description>Write '1' to enable interrupt for event COMPARE[12]</description>
72914 <description>Read: Disabled</description>
72919 <description>Read: Enabled</description>
72927 <description>Enable</description>
72934 <description>Write '1' to enable interrupt for event COMPARE[13]</description>
72941 <description>Read: Disabled</description>
72946 <description>Read: Enabled</description>
72954 <description>Enable</description>
72961 <description>Write '1' to enable interrupt for event COMPARE[14]</description>
72968 <description>Read: Disabled</description>
72973 <description>Read: Enabled</description>
72981 <description>Enable</description>
72988 <description>Write '1' to enable interrupt for event COMPARE[15]</description>
72995 <description>Read: Disabled</description>
73000 <description>Read: Enabled</description>
73008 <description>Enable</description>
73015 <description>Write '1' to enable interrupt for event RTCOMPARESYNC</description>
73022 <description>Read: Disabled</description>
73027 <description>Read: Enabled</description>
73035 <description>Enable</description>
73042 <description>Write '1' to enable interrupt for event SYSCOUNTERVALID</description>
73049 <description>Read: Disabled</description>
73054 <description>Read: Enabled</description>
73062 <description>Enable</description>
73069 <description>Write '1' to enable interrupt for event PWMPERIODEND</description>
73076 <description>Read: Disabled</description>
73081 <description>Read: Enabled</description>
73089 <description>Enable</description>
73098 <description>Disable interrupt</description>
73106 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
73113 <description>Read: Disabled</description>
73118 <description>Read: Enabled</description>
73126 <description>Disable</description>
73133 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
73140 <description>Read: Disabled</description>
73145 <description>Read: Enabled</description>
73153 <description>Disable</description>
73160 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
73167 <description>Read: Disabled</description>
73172 <description>Read: Enabled</description>
73180 <description>Disable</description>
73187 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
73194 <description>Read: Disabled</description>
73199 <description>Read: Enabled</description>
73207 <description>Disable</description>
73214 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
73221 <description>Read: Disabled</description>
73226 <description>Read: Enabled</description>
73234 <description>Disable</description>
73241 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
73248 <description>Read: Disabled</description>
73253 <description>Read: Enabled</description>
73261 <description>Disable</description>
73268 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
73275 <description>Read: Disabled</description>
73280 <description>Read: Enabled</description>
73288 <description>Disable</description>
73295 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
73302 <description>Read: Disabled</description>
73307 <description>Read: Enabled</description>
73315 <description>Disable</description>
73322 <description>Write '1' to disable interrupt for event COMPARE[8]</description>
73329 <description>Read: Disabled</description>
73334 <description>Read: Enabled</description>
73342 <description>Disable</description>
73349 <description>Write '1' to disable interrupt for event COMPARE[9]</description>
73356 <description>Read: Disabled</description>
73361 <description>Read: Enabled</description>
73369 <description>Disable</description>
73376 <description>Write '1' to disable interrupt for event COMPARE[10]</description>
73383 <description>Read: Disabled</description>
73388 <description>Read: Enabled</description>
73396 <description>Disable</description>
73403 <description>Write '1' to disable interrupt for event COMPARE[11]</description>
73410 <description>Read: Disabled</description>
73415 <description>Read: Enabled</description>
73423 <description>Disable</description>
73430 <description>Write '1' to disable interrupt for event COMPARE[12]</description>
73437 <description>Read: Disabled</description>
73442 <description>Read: Enabled</description>
73450 <description>Disable</description>
73457 <description>Write '1' to disable interrupt for event COMPARE[13]</description>
73464 <description>Read: Disabled</description>
73469 <description>Read: Enabled</description>
73477 <description>Disable</description>
73484 <description>Write '1' to disable interrupt for event COMPARE[14]</description>
73491 <description>Read: Disabled</description>
73496 <description>Read: Enabled</description>
73504 <description>Disable</description>
73511 <description>Write '1' to disable interrupt for event COMPARE[15]</description>
73518 <description>Read: Disabled</description>
73523 <description>Read: Enabled</description>
73531 <description>Disable</description>
73538 <description>Write '1' to disable interrupt for event RTCOMPARESYNC</description>
73545 <description>Read: Disabled</description>
73550 <description>Read: Enabled</description>
73558 <description>Disable</description>
73565 <description>Write '1' to disable interrupt for event SYSCOUNTERVALID</description>
73572 <description>Read: Disabled</description>
73577 <description>Read: Enabled</description>
73585 <description>Disable</description>
73592 <description>Write '1' to disable interrupt for event PWMPERIODEND</description>
73599 <description>Read: Disabled</description>
73604 <description>Read: Enabled</description>
73612 <description>Disable</description>
73621 <description>Pending interrupts</description>
73629 <description>Read pending status of interrupt for event COMPARE[0]</description>
73636 <description>Read: Not pending</description>
73641 <description>Read: Pending</description>
73648 <description>Read pending status of interrupt for event COMPARE[1]</description>
73655 <description>Read: Not pending</description>
73660 <description>Read: Pending</description>
73667 <description>Read pending status of interrupt for event COMPARE[2]</description>
73674 <description>Read: Not pending</description>
73679 <description>Read: Pending</description>
73686 <description>Read pending status of interrupt for event COMPARE[3]</description>
73693 <description>Read: Not pending</description>
73698 <description>Read: Pending</description>
73705 <description>Read pending status of interrupt for event COMPARE[4]</description>
73712 <description>Read: Not pending</description>
73717 <description>Read: Pending</description>
73724 <description>Read pending status of interrupt for event COMPARE[5]</description>
73731 <description>Read: Not pending</description>
73736 <description>Read: Pending</description>
73743 <description>Read pending status of interrupt for event COMPARE[6]</description>
73750 <description>Read: Not pending</description>
73755 <description>Read: Pending</description>
73762 <description>Read pending status of interrupt for event COMPARE[7]</description>
73769 <description>Read: Not pending</description>
73774 <description>Read: Pending</description>
73781 <description>Read pending status of interrupt for event COMPARE[8]</description>
73788 <description>Read: Not pending</description>
73793 <description>Read: Pending</description>
73800 <description>Read pending status of interrupt for event COMPARE[9]</description>
73807 <description>Read: Not pending</description>
73812 <description>Read: Pending</description>
73819 <description>Read pending status of interrupt for event COMPARE[10]</description>
73826 <description>Read: Not pending</description>
73831 <description>Read: Pending</description>
73838 <description>Read pending status of interrupt for event COMPARE[11]</description>
73845 <description>Read: Not pending</description>
73850 <description>Read: Pending</description>
73857 <description>Read pending status of interrupt for event COMPARE[12]</description>
73864 <description>Read: Not pending</description>
73869 <description>Read: Pending</description>
73876 <description>Read pending status of interrupt for event COMPARE[13]</description>
73883 <description>Read: Not pending</description>
73888 <description>Read: Pending</description>
73895 <description>Read pending status of interrupt for event COMPARE[14]</description>
73902 <description>Read: Not pending</description>
73907 <description>Read: Pending</description>
73914 <description>Read pending status of interrupt for event COMPARE[15]</description>
73921 <description>Read: Not pending</description>
73926 <description>Read: Pending</description>
73933 <description>Read pending status of interrupt for event RTCOMPARESYNC</description>
73940 <description>Read: Not pending</description>
73945 <description>Read: Pending</description>
73952 <description>Read pending status of interrupt for event SYSCOUNTERVALID</description>
73959 <description>Read: Not pending</description>
73964 <description>Read: Pending</description>
73971 <description>Read pending status of interrupt for event PWMPERIODEND</description>
73978 <description>Read: Not pending</description>
73983 <description>Read: Pending</description>
73992 <description>Enable or disable interrupt</description>
74000 <description>Enable or disable interrupt for event COMPARE[0]</description>
74006 <description>Disable</description>
74011 <description>Enable</description>
74018 <description>Enable or disable interrupt for event COMPARE[1]</description>
74024 <description>Disable</description>
74029 <description>Enable</description>
74036 <description>Enable or disable interrupt for event COMPARE[2]</description>
74042 <description>Disable</description>
74047 <description>Enable</description>
74054 <description>Enable or disable interrupt for event COMPARE[3]</description>
74060 <description>Disable</description>
74065 <description>Enable</description>
74072 <description>Enable or disable interrupt for event COMPARE[4]</description>
74078 <description>Disable</description>
74083 <description>Enable</description>
74090 <description>Enable or disable interrupt for event COMPARE[5]</description>
74096 <description>Disable</description>
74101 <description>Enable</description>
74108 <description>Enable or disable interrupt for event COMPARE[6]</description>
74114 <description>Disable</description>
74119 <description>Enable</description>
74126 <description>Enable or disable interrupt for event COMPARE[7]</description>
74132 <description>Disable</description>
74137 <description>Enable</description>
74144 <description>Enable or disable interrupt for event COMPARE[8]</description>
74150 <description>Disable</description>
74155 <description>Enable</description>
74162 <description>Enable or disable interrupt for event COMPARE[9]</description>
74168 <description>Disable</description>
74173 <description>Enable</description>
74180 <description>Enable or disable interrupt for event COMPARE[10]</description>
74186 <description>Disable</description>
74191 <description>Enable</description>
74198 <description>Enable or disable interrupt for event COMPARE[11]</description>
74204 <description>Disable</description>
74209 <description>Enable</description>
74216 <description>Enable or disable interrupt for event COMPARE[12]</description>
74222 <description>Disable</description>
74227 <description>Enable</description>
74234 <description>Enable or disable interrupt for event COMPARE[13]</description>
74240 <description>Disable</description>
74245 <description>Enable</description>
74252 <description>Enable or disable interrupt for event COMPARE[14]</description>
74258 <description>Disable</description>
74263 <description>Enable</description>
74270 <description>Enable or disable interrupt for event COMPARE[15]</description>
74276 <description>Disable</description>
74281 <description>Enable</description>
74288 <description>Enable or disable interrupt for event RTCOMPARESYNC</description>
74294 <description>Disable</description>
74299 <description>Enable</description>
74306 <description>Enable or disable interrupt for event SYSCOUNTERVALID</description>
74312 <description>Disable</description>
74317 <description>Enable</description>
74324 <description>Enable or disable interrupt for event PWMPERIODEND</description>
74330 <description>Disable</description>
74335 <description>Enable</description>
74344 <description>Enable interrupt</description>
74352 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
74359 <description>Read: Disabled</description>
74364 <description>Read: Enabled</description>
74372 <description>Enable</description>
74379 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
74386 <description>Read: Disabled</description>
74391 <description>Read: Enabled</description>
74399 <description>Enable</description>
74406 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
74413 <description>Read: Disabled</description>
74418 <description>Read: Enabled</description>
74426 <description>Enable</description>
74433 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
74440 <description>Read: Disabled</description>
74445 <description>Read: Enabled</description>
74453 <description>Enable</description>
74460 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
74467 <description>Read: Disabled</description>
74472 <description>Read: Enabled</description>
74480 <description>Enable</description>
74487 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
74494 <description>Read: Disabled</description>
74499 <description>Read: Enabled</description>
74507 <description>Enable</description>
74514 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
74521 <description>Read: Disabled</description>
74526 <description>Read: Enabled</description>
74534 <description>Enable</description>
74541 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
74548 <description>Read: Disabled</description>
74553 <description>Read: Enabled</description>
74561 <description>Enable</description>
74568 <description>Write '1' to enable interrupt for event COMPARE[8]</description>
74575 <description>Read: Disabled</description>
74580 <description>Read: Enabled</description>
74588 <description>Enable</description>
74595 <description>Write '1' to enable interrupt for event COMPARE[9]</description>
74602 <description>Read: Disabled</description>
74607 <description>Read: Enabled</description>
74615 <description>Enable</description>
74622 <description>Write '1' to enable interrupt for event COMPARE[10]</description>
74629 <description>Read: Disabled</description>
74634 <description>Read: Enabled</description>
74642 <description>Enable</description>
74649 <description>Write '1' to enable interrupt for event COMPARE[11]</description>
74656 <description>Read: Disabled</description>
74661 <description>Read: Enabled</description>
74669 <description>Enable</description>
74676 <description>Write '1' to enable interrupt for event COMPARE[12]</description>
74683 <description>Read: Disabled</description>
74688 <description>Read: Enabled</description>
74696 <description>Enable</description>
74703 <description>Write '1' to enable interrupt for event COMPARE[13]</description>
74710 <description>Read: Disabled</description>
74715 <description>Read: Enabled</description>
74723 <description>Enable</description>
74730 <description>Write '1' to enable interrupt for event COMPARE[14]</description>
74737 <description>Read: Disabled</description>
74742 <description>Read: Enabled</description>
74750 <description>Enable</description>
74757 <description>Write '1' to enable interrupt for event COMPARE[15]</description>
74764 <description>Read: Disabled</description>
74769 <description>Read: Enabled</description>
74777 <description>Enable</description>
74784 <description>Write '1' to enable interrupt for event RTCOMPARESYNC</description>
74791 <description>Read: Disabled</description>
74796 <description>Read: Enabled</description>
74804 <description>Enable</description>
74811 <description>Write '1' to enable interrupt for event SYSCOUNTERVALID</description>
74818 <description>Read: Disabled</description>
74823 <description>Read: Enabled</description>
74831 <description>Enable</description>
74838 <description>Write '1' to enable interrupt for event PWMPERIODEND</description>
74845 <description>Read: Disabled</description>
74850 <description>Read: Enabled</description>
74858 <description>Enable</description>
74867 <description>Disable interrupt</description>
74875 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
74882 <description>Read: Disabled</description>
74887 <description>Read: Enabled</description>
74895 <description>Disable</description>
74902 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
74909 <description>Read: Disabled</description>
74914 <description>Read: Enabled</description>
74922 <description>Disable</description>
74929 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
74936 <description>Read: Disabled</description>
74941 <description>Read: Enabled</description>
74949 <description>Disable</description>
74956 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
74963 <description>Read: Disabled</description>
74968 <description>Read: Enabled</description>
74976 <description>Disable</description>
74983 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
74990 <description>Read: Disabled</description>
74995 <description>Read: Enabled</description>
75003 <description>Disable</description>
75010 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
75017 <description>Read: Disabled</description>
75022 <description>Read: Enabled</description>
75030 <description>Disable</description>
75037 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
75044 <description>Read: Disabled</description>
75049 <description>Read: Enabled</description>
75057 <description>Disable</description>
75064 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
75071 <description>Read: Disabled</description>
75076 <description>Read: Enabled</description>
75084 <description>Disable</description>
75091 <description>Write '1' to disable interrupt for event COMPARE[8]</description>
75098 <description>Read: Disabled</description>
75103 <description>Read: Enabled</description>
75111 <description>Disable</description>
75118 <description>Write '1' to disable interrupt for event COMPARE[9]</description>
75125 <description>Read: Disabled</description>
75130 <description>Read: Enabled</description>
75138 <description>Disable</description>
75145 <description>Write '1' to disable interrupt for event COMPARE[10]</description>
75152 <description>Read: Disabled</description>
75157 <description>Read: Enabled</description>
75165 <description>Disable</description>
75172 <description>Write '1' to disable interrupt for event COMPARE[11]</description>
75179 <description>Read: Disabled</description>
75184 <description>Read: Enabled</description>
75192 <description>Disable</description>
75199 <description>Write '1' to disable interrupt for event COMPARE[12]</description>
75206 <description>Read: Disabled</description>
75211 <description>Read: Enabled</description>
75219 <description>Disable</description>
75226 <description>Write '1' to disable interrupt for event COMPARE[13]</description>
75233 <description>Read: Disabled</description>
75238 <description>Read: Enabled</description>
75246 <description>Disable</description>
75253 <description>Write '1' to disable interrupt for event COMPARE[14]</description>
75260 <description>Read: Disabled</description>
75265 <description>Read: Enabled</description>
75273 <description>Disable</description>
75280 <description>Write '1' to disable interrupt for event COMPARE[15]</description>
75287 <description>Read: Disabled</description>
75292 <description>Read: Enabled</description>
75300 <description>Disable</description>
75307 <description>Write '1' to disable interrupt for event RTCOMPARESYNC</description>
75314 <description>Read: Disabled</description>
75319 <description>Read: Enabled</description>
75327 <description>Disable</description>
75334 <description>Write '1' to disable interrupt for event SYSCOUNTERVALID</description>
75341 <description>Read: Disabled</description>
75346 <description>Read: Enabled</description>
75354 <description>Disable</description>
75361 <description>Write '1' to disable interrupt for event PWMPERIODEND</description>
75368 <description>Read: Disabled</description>
75373 <description>Read: Enabled</description>
75381 <description>Disable</description>
75390 <description>Pending interrupts</description>
75398 <description>Read pending status of interrupt for event COMPARE[0]</description>
75405 <description>Read: Not pending</description>
75410 <description>Read: Pending</description>
75417 <description>Read pending status of interrupt for event COMPARE[1]</description>
75424 <description>Read: Not pending</description>
75429 <description>Read: Pending</description>
75436 <description>Read pending status of interrupt for event COMPARE[2]</description>
75443 <description>Read: Not pending</description>
75448 <description>Read: Pending</description>
75455 <description>Read pending status of interrupt for event COMPARE[3]</description>
75462 <description>Read: Not pending</description>
75467 <description>Read: Pending</description>
75474 <description>Read pending status of interrupt for event COMPARE[4]</description>
75481 <description>Read: Not pending</description>
75486 <description>Read: Pending</description>
75493 <description>Read pending status of interrupt for event COMPARE[5]</description>
75500 <description>Read: Not pending</description>
75505 <description>Read: Pending</description>
75512 <description>Read pending status of interrupt for event COMPARE[6]</description>
75519 <description>Read: Not pending</description>
75524 <description>Read: Pending</description>
75531 <description>Read pending status of interrupt for event COMPARE[7]</description>
75538 <description>Read: Not pending</description>
75543 <description>Read: Pending</description>
75550 <description>Read pending status of interrupt for event COMPARE[8]</description>
75557 <description>Read: Not pending</description>
75562 <description>Read: Pending</description>
75569 <description>Read pending status of interrupt for event COMPARE[9]</description>
75576 <description>Read: Not pending</description>
75581 <description>Read: Pending</description>
75588 <description>Read pending status of interrupt for event COMPARE[10]</description>
75595 <description>Read: Not pending</description>
75600 <description>Read: Pending</description>
75607 <description>Read pending status of interrupt for event COMPARE[11]</description>
75614 <description>Read: Not pending</description>
75619 <description>Read: Pending</description>
75626 <description>Read pending status of interrupt for event COMPARE[12]</description>
75633 <description>Read: Not pending</description>
75638 <description>Read: Pending</description>
75645 <description>Read pending status of interrupt for event COMPARE[13]</description>
75652 <description>Read: Not pending</description>
75657 <description>Read: Pending</description>
75664 <description>Read pending status of interrupt for event COMPARE[14]</description>
75671 <description>Read: Not pending</description>
75676 <description>Read: Pending</description>
75683 <description>Read pending status of interrupt for event COMPARE[15]</description>
75690 <description>Read: Not pending</description>
75695 <description>Read: Pending</description>
75702 <description>Read pending status of interrupt for event RTCOMPARESYNC</description>
75709 <description>Read: Not pending</description>
75714 <description>Read: Pending</description>
75721 <description>Read pending status of interrupt for event SYSCOUNTERVALID</description>
75728 <description>Read: Not pending</description>
75733 <description>Read: Pending</description>
75740 <description>Read pending status of interrupt for event PWMPERIODEND</description>
75747 <description>Read: Not pending</description>
75752 <description>Read: Pending</description>
75761 <description>Enable or disable interrupt</description>
75769 <description>Enable or disable interrupt for event COMPARE[0]</description>
75775 <description>Disable</description>
75780 <description>Enable</description>
75787 <description>Enable or disable interrupt for event COMPARE[1]</description>
75793 <description>Disable</description>
75798 <description>Enable</description>
75805 <description>Enable or disable interrupt for event COMPARE[2]</description>
75811 <description>Disable</description>
75816 <description>Enable</description>
75823 <description>Enable or disable interrupt for event COMPARE[3]</description>
75829 <description>Disable</description>
75834 <description>Enable</description>
75841 <description>Enable or disable interrupt for event COMPARE[4]</description>
75847 <description>Disable</description>
75852 <description>Enable</description>
75859 <description>Enable or disable interrupt for event COMPARE[5]</description>
75865 <description>Disable</description>
75870 <description>Enable</description>
75877 <description>Enable or disable interrupt for event COMPARE[6]</description>
75883 <description>Disable</description>
75888 <description>Enable</description>
75895 <description>Enable or disable interrupt for event COMPARE[7]</description>
75901 <description>Disable</description>
75906 <description>Enable</description>
75913 <description>Enable or disable interrupt for event COMPARE[8]</description>
75919 <description>Disable</description>
75924 <description>Enable</description>
75931 <description>Enable or disable interrupt for event COMPARE[9]</description>
75937 <description>Disable</description>
75942 <description>Enable</description>
75949 <description>Enable or disable interrupt for event COMPARE[10]</description>
75955 <description>Disable</description>
75960 <description>Enable</description>
75967 <description>Enable or disable interrupt for event COMPARE[11]</description>
75973 <description>Disable</description>
75978 <description>Enable</description>
75985 <description>Enable or disable interrupt for event COMPARE[12]</description>
75991 <description>Disable</description>
75996 <description>Enable</description>
76003 <description>Enable or disable interrupt for event COMPARE[13]</description>
76009 <description>Disable</description>
76014 <description>Enable</description>
76021 <description>Enable or disable interrupt for event COMPARE[14]</description>
76027 <description>Disable</description>
76032 <description>Enable</description>
76039 <description>Enable or disable interrupt for event COMPARE[15]</description>
76045 <description>Disable</description>
76050 <description>Enable</description>
76057 <description>Enable or disable interrupt for event RTCOMPARESYNC</description>
76063 <description>Disable</description>
76068 <description>Enable</description>
76075 <description>Enable or disable interrupt for event SYSCOUNTERVALID</description>
76081 <description>Disable</description>
76086 <description>Enable</description>
76093 <description>Enable or disable interrupt for event PWMPERIODEND</description>
76099 <description>Disable</description>
76104 <description>Enable</description>
76113 <description>Enable interrupt</description>
76121 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
76128 <description>Read: Disabled</description>
76133 <description>Read: Enabled</description>
76141 <description>Enable</description>
76148 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
76155 <description>Read: Disabled</description>
76160 <description>Read: Enabled</description>
76168 <description>Enable</description>
76175 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
76182 <description>Read: Disabled</description>
76187 <description>Read: Enabled</description>
76195 <description>Enable</description>
76202 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
76209 <description>Read: Disabled</description>
76214 <description>Read: Enabled</description>
76222 <description>Enable</description>
76229 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
76236 <description>Read: Disabled</description>
76241 <description>Read: Enabled</description>
76249 <description>Enable</description>
76256 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
76263 <description>Read: Disabled</description>
76268 <description>Read: Enabled</description>
76276 <description>Enable</description>
76283 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
76290 <description>Read: Disabled</description>
76295 <description>Read: Enabled</description>
76303 <description>Enable</description>
76310 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
76317 <description>Read: Disabled</description>
76322 <description>Read: Enabled</description>
76330 <description>Enable</description>
76337 <description>Write '1' to enable interrupt for event COMPARE[8]</description>
76344 <description>Read: Disabled</description>
76349 <description>Read: Enabled</description>
76357 <description>Enable</description>
76364 <description>Write '1' to enable interrupt for event COMPARE[9]</description>
76371 <description>Read: Disabled</description>
76376 <description>Read: Enabled</description>
76384 <description>Enable</description>
76391 <description>Write '1' to enable interrupt for event COMPARE[10]</description>
76398 <description>Read: Disabled</description>
76403 <description>Read: Enabled</description>
76411 <description>Enable</description>
76418 <description>Write '1' to enable interrupt for event COMPARE[11]</description>
76425 <description>Read: Disabled</description>
76430 <description>Read: Enabled</description>
76438 <description>Enable</description>
76445 <description>Write '1' to enable interrupt for event COMPARE[12]</description>
76452 <description>Read: Disabled</description>
76457 <description>Read: Enabled</description>
76465 <description>Enable</description>
76472 <description>Write '1' to enable interrupt for event COMPARE[13]</description>
76479 <description>Read: Disabled</description>
76484 <description>Read: Enabled</description>
76492 <description>Enable</description>
76499 <description>Write '1' to enable interrupt for event COMPARE[14]</description>
76506 <description>Read: Disabled</description>
76511 <description>Read: Enabled</description>
76519 <description>Enable</description>
76526 <description>Write '1' to enable interrupt for event COMPARE[15]</description>
76533 <description>Read: Disabled</description>
76538 <description>Read: Enabled</description>
76546 <description>Enable</description>
76553 <description>Write '1' to enable interrupt for event RTCOMPARESYNC</description>
76560 <description>Read: Disabled</description>
76565 <description>Read: Enabled</description>
76573 <description>Enable</description>
76580 <description>Write '1' to enable interrupt for event SYSCOUNTERVALID</description>
76587 <description>Read: Disabled</description>
76592 <description>Read: Enabled</description>
76600 <description>Enable</description>
76607 <description>Write '1' to enable interrupt for event PWMPERIODEND</description>
76614 <description>Read: Disabled</description>
76619 <description>Read: Enabled</description>
76627 <description>Enable</description>
76636 <description>Disable interrupt</description>
76644 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
76651 <description>Read: Disabled</description>
76656 <description>Read: Enabled</description>
76664 <description>Disable</description>
76671 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
76678 <description>Read: Disabled</description>
76683 <description>Read: Enabled</description>
76691 <description>Disable</description>
76698 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
76705 <description>Read: Disabled</description>
76710 <description>Read: Enabled</description>
76718 <description>Disable</description>
76725 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
76732 <description>Read: Disabled</description>
76737 <description>Read: Enabled</description>
76745 <description>Disable</description>
76752 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
76759 <description>Read: Disabled</description>
76764 <description>Read: Enabled</description>
76772 <description>Disable</description>
76779 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
76786 <description>Read: Disabled</description>
76791 <description>Read: Enabled</description>
76799 <description>Disable</description>
76806 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
76813 <description>Read: Disabled</description>
76818 <description>Read: Enabled</description>
76826 <description>Disable</description>
76833 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
76840 <description>Read: Disabled</description>
76845 <description>Read: Enabled</description>
76853 <description>Disable</description>
76860 <description>Write '1' to disable interrupt for event COMPARE[8]</description>
76867 <description>Read: Disabled</description>
76872 <description>Read: Enabled</description>
76880 <description>Disable</description>
76887 <description>Write '1' to disable interrupt for event COMPARE[9]</description>
76894 <description>Read: Disabled</description>
76899 <description>Read: Enabled</description>
76907 <description>Disable</description>
76914 <description>Write '1' to disable interrupt for event COMPARE[10]</description>
76921 <description>Read: Disabled</description>
76926 <description>Read: Enabled</description>
76934 <description>Disable</description>
76941 <description>Write '1' to disable interrupt for event COMPARE[11]</description>
76948 <description>Read: Disabled</description>
76953 <description>Read: Enabled</description>
76961 <description>Disable</description>
76968 <description>Write '1' to disable interrupt for event COMPARE[12]</description>
76975 <description>Read: Disabled</description>
76980 <description>Read: Enabled</description>
76988 <description>Disable</description>
76995 <description>Write '1' to disable interrupt for event COMPARE[13]</description>
77002 <description>Read: Disabled</description>
77007 <description>Read: Enabled</description>
77015 <description>Disable</description>
77022 <description>Write '1' to disable interrupt for event COMPARE[14]</description>
77029 <description>Read: Disabled</description>
77034 <description>Read: Enabled</description>
77042 <description>Disable</description>
77049 <description>Write '1' to disable interrupt for event COMPARE[15]</description>
77056 <description>Read: Disabled</description>
77061 <description>Read: Enabled</description>
77069 <description>Disable</description>
77076 <description>Write '1' to disable interrupt for event RTCOMPARESYNC</description>
77083 <description>Read: Disabled</description>
77088 <description>Read: Enabled</description>
77096 <description>Disable</description>
77103 <description>Write '1' to disable interrupt for event SYSCOUNTERVALID</description>
77110 <description>Read: Disabled</description>
77115 <description>Read: Enabled</description>
77123 <description>Disable</description>
77130 <description>Write '1' to disable interrupt for event PWMPERIODEND</description>
77137 <description>Read: Disabled</description>
77142 <description>Read: Enabled</description>
77150 <description>Disable</description>
77159 <description>Pending interrupts</description>
77167 <description>Read pending status of interrupt for event COMPARE[0]</description>
77174 <description>Read: Not pending</description>
77179 <description>Read: Pending</description>
77186 <description>Read pending status of interrupt for event COMPARE[1]</description>
77193 <description>Read: Not pending</description>
77198 <description>Read: Pending</description>
77205 <description>Read pending status of interrupt for event COMPARE[2]</description>
77212 <description>Read: Not pending</description>
77217 <description>Read: Pending</description>
77224 <description>Read pending status of interrupt for event COMPARE[3]</description>
77231 <description>Read: Not pending</description>
77236 <description>Read: Pending</description>
77243 <description>Read pending status of interrupt for event COMPARE[4]</description>
77250 <description>Read: Not pending</description>
77255 <description>Read: Pending</description>
77262 <description>Read pending status of interrupt for event COMPARE[5]</description>
77269 <description>Read: Not pending</description>
77274 <description>Read: Pending</description>
77281 <description>Read pending status of interrupt for event COMPARE[6]</description>
77288 <description>Read: Not pending</description>
77293 <description>Read: Pending</description>
77300 <description>Read pending status of interrupt for event COMPARE[7]</description>
77307 <description>Read: Not pending</description>
77312 <description>Read: Pending</description>
77319 <description>Read pending status of interrupt for event COMPARE[8]</description>
77326 <description>Read: Not pending</description>
77331 <description>Read: Pending</description>
77338 <description>Read pending status of interrupt for event COMPARE[9]</description>
77345 <description>Read: Not pending</description>
77350 <description>Read: Pending</description>
77357 <description>Read pending status of interrupt for event COMPARE[10]</description>
77364 <description>Read: Not pending</description>
77369 <description>Read: Pending</description>
77376 <description>Read pending status of interrupt for event COMPARE[11]</description>
77383 <description>Read: Not pending</description>
77388 <description>Read: Pending</description>
77395 <description>Read pending status of interrupt for event COMPARE[12]</description>
77402 <description>Read: Not pending</description>
77407 <description>Read: Pending</description>
77414 <description>Read pending status of interrupt for event COMPARE[13]</description>
77421 <description>Read: Not pending</description>
77426 <description>Read: Pending</description>
77433 <description>Read pending status of interrupt for event COMPARE[14]</description>
77440 <description>Read: Not pending</description>
77445 <description>Read: Pending</description>
77452 <description>Read pending status of interrupt for event COMPARE[15]</description>
77459 <description>Read: Not pending</description>
77464 <description>Read: Pending</description>
77471 <description>Read pending status of interrupt for event RTCOMPARESYNC</description>
77478 <description>Read: Not pending</description>
77483 <description>Read: Pending</description>
77490 <description>Read pending status of interrupt for event SYSCOUNTERVALID</description>
77497 <description>Read: Not pending</description>
77502 <description>Read: Pending</description>
77509 <description>Read pending status of interrupt for event PWMPERIODEND</description>
77516 <description>Read: Not pending</description>
77521 <description>Read: Pending</description>
77530 <description>Enable or disable interrupt</description>
77538 <description>Enable or disable interrupt for event COMPARE[0]</description>
77544 <description>Disable</description>
77549 <description>Enable</description>
77556 <description>Enable or disable interrupt for event COMPARE[1]</description>
77562 <description>Disable</description>
77567 <description>Enable</description>
77574 <description>Enable or disable interrupt for event COMPARE[2]</description>
77580 <description>Disable</description>
77585 <description>Enable</description>
77592 <description>Enable or disable interrupt for event COMPARE[3]</description>
77598 <description>Disable</description>
77603 <description>Enable</description>
77610 <description>Enable or disable interrupt for event COMPARE[4]</description>
77616 <description>Disable</description>
77621 <description>Enable</description>
77628 <description>Enable or disable interrupt for event COMPARE[5]</description>
77634 <description>Disable</description>
77639 <description>Enable</description>
77646 <description>Enable or disable interrupt for event COMPARE[6]</description>
77652 <description>Disable</description>
77657 <description>Enable</description>
77664 <description>Enable or disable interrupt for event COMPARE[7]</description>
77670 <description>Disable</description>
77675 <description>Enable</description>
77682 <description>Enable or disable interrupt for event COMPARE[8]</description>
77688 <description>Disable</description>
77693 <description>Enable</description>
77700 <description>Enable or disable interrupt for event COMPARE[9]</description>
77706 <description>Disable</description>
77711 <description>Enable</description>
77718 <description>Enable or disable interrupt for event COMPARE[10]</description>
77724 <description>Disable</description>
77729 <description>Enable</description>
77736 <description>Enable or disable interrupt for event COMPARE[11]</description>
77742 <description>Disable</description>
77747 <description>Enable</description>
77754 <description>Enable or disable interrupt for event COMPARE[12]</description>
77760 <description>Disable</description>
77765 <description>Enable</description>
77772 <description>Enable or disable interrupt for event COMPARE[13]</description>
77778 <description>Disable</description>
77783 <description>Enable</description>
77790 <description>Enable or disable interrupt for event COMPARE[14]</description>
77796 <description>Disable</description>
77801 <description>Enable</description>
77808 <description>Enable or disable interrupt for event COMPARE[15]</description>
77814 <description>Disable</description>
77819 <description>Enable</description>
77826 <description>Enable or disable interrupt for event RTCOMPARESYNC</description>
77832 <description>Disable</description>
77837 <description>Enable</description>
77844 <description>Enable or disable interrupt for event SYSCOUNTERVALID</description>
77850 <description>Disable</description>
77855 <description>Enable</description>
77862 <description>Enable or disable interrupt for event PWMPERIODEND</description>
77868 <description>Disable</description>
77873 <description>Enable</description>
77882 <description>Enable interrupt</description>
77890 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
77897 <description>Read: Disabled</description>
77902 <description>Read: Enabled</description>
77910 <description>Enable</description>
77917 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
77924 <description>Read: Disabled</description>
77929 <description>Read: Enabled</description>
77937 <description>Enable</description>
77944 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
77951 <description>Read: Disabled</description>
77956 <description>Read: Enabled</description>
77964 <description>Enable</description>
77971 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
77978 <description>Read: Disabled</description>
77983 <description>Read: Enabled</description>
77991 <description>Enable</description>
77998 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
78005 <description>Read: Disabled</description>
78010 <description>Read: Enabled</description>
78018 <description>Enable</description>
78025 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
78032 <description>Read: Disabled</description>
78037 <description>Read: Enabled</description>
78045 <description>Enable</description>
78052 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
78059 <description>Read: Disabled</description>
78064 <description>Read: Enabled</description>
78072 <description>Enable</description>
78079 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
78086 <description>Read: Disabled</description>
78091 <description>Read: Enabled</description>
78099 <description>Enable</description>
78106 <description>Write '1' to enable interrupt for event COMPARE[8]</description>
78113 <description>Read: Disabled</description>
78118 <description>Read: Enabled</description>
78126 <description>Enable</description>
78133 <description>Write '1' to enable interrupt for event COMPARE[9]</description>
78140 <description>Read: Disabled</description>
78145 <description>Read: Enabled</description>
78153 <description>Enable</description>
78160 <description>Write '1' to enable interrupt for event COMPARE[10]</description>
78167 <description>Read: Disabled</description>
78172 <description>Read: Enabled</description>
78180 <description>Enable</description>
78187 <description>Write '1' to enable interrupt for event COMPARE[11]</description>
78194 <description>Read: Disabled</description>
78199 <description>Read: Enabled</description>
78207 <description>Enable</description>
78214 <description>Write '1' to enable interrupt for event COMPARE[12]</description>
78221 <description>Read: Disabled</description>
78226 <description>Read: Enabled</description>
78234 <description>Enable</description>
78241 <description>Write '1' to enable interrupt for event COMPARE[13]</description>
78248 <description>Read: Disabled</description>
78253 <description>Read: Enabled</description>
78261 <description>Enable</description>
78268 <description>Write '1' to enable interrupt for event COMPARE[14]</description>
78275 <description>Read: Disabled</description>
78280 <description>Read: Enabled</description>
78288 <description>Enable</description>
78295 <description>Write '1' to enable interrupt for event COMPARE[15]</description>
78302 <description>Read: Disabled</description>
78307 <description>Read: Enabled</description>
78315 <description>Enable</description>
78322 <description>Write '1' to enable interrupt for event RTCOMPARESYNC</description>
78329 <description>Read: Disabled</description>
78334 <description>Read: Enabled</description>
78342 <description>Enable</description>
78349 <description>Write '1' to enable interrupt for event SYSCOUNTERVALID</description>
78356 <description>Read: Disabled</description>
78361 <description>Read: Enabled</description>
78369 <description>Enable</description>
78376 <description>Write '1' to enable interrupt for event PWMPERIODEND</description>
78383 <description>Read: Disabled</description>
78388 <description>Read: Enabled</description>
78396 <description>Enable</description>
78405 <description>Disable interrupt</description>
78413 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
78420 <description>Read: Disabled</description>
78425 <description>Read: Enabled</description>
78433 <description>Disable</description>
78440 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
78447 <description>Read: Disabled</description>
78452 <description>Read: Enabled</description>
78460 <description>Disable</description>
78467 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
78474 <description>Read: Disabled</description>
78479 <description>Read: Enabled</description>
78487 <description>Disable</description>
78494 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
78501 <description>Read: Disabled</description>
78506 <description>Read: Enabled</description>
78514 <description>Disable</description>
78521 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
78528 <description>Read: Disabled</description>
78533 <description>Read: Enabled</description>
78541 <description>Disable</description>
78548 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
78555 <description>Read: Disabled</description>
78560 <description>Read: Enabled</description>
78568 <description>Disable</description>
78575 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
78582 <description>Read: Disabled</description>
78587 <description>Read: Enabled</description>
78595 <description>Disable</description>
78602 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
78609 <description>Read: Disabled</description>
78614 <description>Read: Enabled</description>
78622 <description>Disable</description>
78629 <description>Write '1' to disable interrupt for event COMPARE[8]</description>
78636 <description>Read: Disabled</description>
78641 <description>Read: Enabled</description>
78649 <description>Disable</description>
78656 <description>Write '1' to disable interrupt for event COMPARE[9]</description>
78663 <description>Read: Disabled</description>
78668 <description>Read: Enabled</description>
78676 <description>Disable</description>
78683 <description>Write '1' to disable interrupt for event COMPARE[10]</description>
78690 <description>Read: Disabled</description>
78695 <description>Read: Enabled</description>
78703 <description>Disable</description>
78710 <description>Write '1' to disable interrupt for event COMPARE[11]</description>
78717 <description>Read: Disabled</description>
78722 <description>Read: Enabled</description>
78730 <description>Disable</description>
78737 <description>Write '1' to disable interrupt for event COMPARE[12]</description>
78744 <description>Read: Disabled</description>
78749 <description>Read: Enabled</description>
78757 <description>Disable</description>
78764 <description>Write '1' to disable interrupt for event COMPARE[13]</description>
78771 <description>Read: Disabled</description>
78776 <description>Read: Enabled</description>
78784 <description>Disable</description>
78791 <description>Write '1' to disable interrupt for event COMPARE[14]</description>
78798 <description>Read: Disabled</description>
78803 <description>Read: Enabled</description>
78811 <description>Disable</description>
78818 <description>Write '1' to disable interrupt for event COMPARE[15]</description>
78825 <description>Read: Disabled</description>
78830 <description>Read: Enabled</description>
78838 <description>Disable</description>
78845 <description>Write '1' to disable interrupt for event RTCOMPARESYNC</description>
78852 <description>Read: Disabled</description>
78857 <description>Read: Enabled</description>
78865 <description>Disable</description>
78872 <description>Write '1' to disable interrupt for event SYSCOUNTERVALID</description>
78879 <description>Read: Disabled</description>
78884 <description>Read: Enabled</description>
78892 <description>Disable</description>
78899 <description>Write '1' to disable interrupt for event PWMPERIODEND</description>
78906 <description>Read: Disabled</description>
78911 <description>Read: Enabled</description>
78919 <description>Disable</description>
78928 <description>Pending interrupts</description>
78936 <description>Read pending status of interrupt for event COMPARE[0]</description>
78943 <description>Read: Not pending</description>
78948 <description>Read: Pending</description>
78955 <description>Read pending status of interrupt for event COMPARE[1]</description>
78962 <description>Read: Not pending</description>
78967 <description>Read: Pending</description>
78974 <description>Read pending status of interrupt for event COMPARE[2]</description>
78981 <description>Read: Not pending</description>
78986 <description>Read: Pending</description>
78993 <description>Read pending status of interrupt for event COMPARE[3]</description>
79000 <description>Read: Not pending</description>
79005 <description>Read: Pending</description>
79012 <description>Read pending status of interrupt for event COMPARE[4]</description>
79019 <description>Read: Not pending</description>
79024 <description>Read: Pending</description>
79031 <description>Read pending status of interrupt for event COMPARE[5]</description>
79038 <description>Read: Not pending</description>
79043 <description>Read: Pending</description>
79050 <description>Read pending status of interrupt for event COMPARE[6]</description>
79057 <description>Read: Not pending</description>
79062 <description>Read: Pending</description>
79069 <description>Read pending status of interrupt for event COMPARE[7]</description>
79076 <description>Read: Not pending</description>
79081 <description>Read: Pending</description>
79088 <description>Read pending status of interrupt for event COMPARE[8]</description>
79095 <description>Read: Not pending</description>
79100 <description>Read: Pending</description>
79107 <description>Read pending status of interrupt for event COMPARE[9]</description>
79114 <description>Read: Not pending</description>
79119 <description>Read: Pending</description>
79126 <description>Read pending status of interrupt for event COMPARE[10]</description>
79133 <description>Read: Not pending</description>
79138 <description>Read: Pending</description>
79145 <description>Read pending status of interrupt for event COMPARE[11]</description>
79152 <description>Read: Not pending</description>
79157 <description>Read: Pending</description>
79164 <description>Read pending status of interrupt for event COMPARE[12]</description>
79171 <description>Read: Not pending</description>
79176 <description>Read: Pending</description>
79183 <description>Read pending status of interrupt for event COMPARE[13]</description>
79190 <description>Read: Not pending</description>
79195 <description>Read: Pending</description>
79202 <description>Read pending status of interrupt for event COMPARE[14]</description>
79209 <description>Read: Not pending</description>
79214 <description>Read: Pending</description>
79221 <description>Read pending status of interrupt for event COMPARE[15]</description>
79228 <description>Read: Not pending</description>
79233 <description>Read: Pending</description>
79240 <description>Read pending status of interrupt for event RTCOMPARESYNC</description>
79247 <description>Read: Not pending</description>
79252 <description>Read: Pending</description>
79259 <description>Read pending status of interrupt for event SYSCOUNTERVALID</description>
79266 <description>Read: Not pending</description>
79271 <description>Read: Pending</description>
79278 <description>Read pending status of interrupt for event PWMPERIODEND</description>
79285 <description>Read: Not pending</description>
79290 <description>Read: Pending</description>
79299 <description>Enable or disable event routing</description>
79307 <description>Enable or disable event routing for event PWMPERIODEND</description>
79313 <description>Disable</description>
79318 <description>Enable</description>
79327 <description>Enable event routing</description>
79335 <description>Write '1' to enable event routing for event PWMPERIODEND</description>
79342 <description>Read: Disabled</description>
79347 <description>Read: Enabled</description>
79355 <description>Enable</description>
79364 <description>Disable event routing</description>
79372 <description>Write '1' to disable event routing for event PWMPERIODEND</description>
79379 <description>Read: Disabled</description>
79384 <description>Read: Enabled</description>
79392 <description>Disable</description>
79401 <description>Counter mode selection</description>
79409 <description>Automatic enable to keep the SYSCOUNTER active.</description>
79415 <description>Default configuration to keep the SYSCOUNTER active.</description>
79420 …<description>In addition to the above mode, any local CPU that is not sleeping keep the SYSCOUNTER…
79427 <description>Enable the SYSCOUNTER</description>
79433 <description>SYSCOUNTER disabled</description>
79438 <description>SYSCOUNTER enabled</description>
79449 <description>Unspecified</description>
79455 …<description>Description cluster: The lower 32-bits of Capture/Compare register CC[n]</description>
79463 <description>Capture/Compare low value in 1 us</description>
79471 …<description>Description cluster: The higher 32-bits of Capture/Compare register CC[n]</descriptio…
79479 <description>Capture/Compare high value in 1 us</description>
79487 …<description>Description cluster: Count to add to CC[n] when this register is written.</descriptio…
79495 <description>Count to add to CC[n]</description>
79501 <description>Configure the Capture/Compare register</description>
79507 <description>Adds SYSCOUNTER value.</description>
79512 <description>Adds CC value.</description>
79521 <description>Description cluster: Configure Capture/Compare register CC[n]</description>
79529 <description>Configure the Capture/Compare register</description>
79535 <description>Capture/Compare register CC[n] Disabled.</description>
79540 <description>Capture/Compare register CC[n] enabled.</description>
79550 …<description>Request to keep the SYSCOUNTER in the active state and prevent going to sleep</descri…
79558 <description>Request from index [0]</description>
79564 <description>Allow SYSCOUNTER to go to sleep</description>
79569 <description>Keep SYSCOUNTER active</description>
79576 <description>Request from index [1]</description>
79582 <description>Allow SYSCOUNTER to go to sleep</description>
79587 <description>Keep SYSCOUNTER active</description>
79594 <description>Request from index [2]</description>
79600 <description>Allow SYSCOUNTER to go to sleep</description>
79605 <description>Keep SYSCOUNTER active</description>
79612 <description>Request from index [3]</description>
79618 <description>Allow SYSCOUNTER to go to sleep</description>
79623 <description>Keep SYSCOUNTER active</description>
79630 <description>Request from index [4]</description>
79636 <description>Allow SYSCOUNTER to go to sleep</description>
79641 <description>Keep SYSCOUNTER active</description>
79648 <description>Request from index [5]</description>
79654 <description>Allow SYSCOUNTER to go to sleep</description>
79659 <description>Keep SYSCOUNTER active</description>
79666 <description>Request from index [6]</description>
79672 <description>Allow SYSCOUNTER to go to sleep</description>
79677 <description>Keep SYSCOUNTER active</description>
79684 <description>Request from index [7]</description>
79690 <description>Allow SYSCOUNTER to go to sleep</description>
79695 <description>Keep SYSCOUNTER active</description>
79702 <description>Request from index [8]</description>
79708 <description>Allow SYSCOUNTER to go to sleep</description>
79713 <description>Keep SYSCOUNTER active</description>
79720 <description>Request from index [9]</description>
79726 <description>Allow SYSCOUNTER to go to sleep</description>
79731 <description>Keep SYSCOUNTER active</description>
79738 <description>Request from index [10]</description>
79744 <description>Allow SYSCOUNTER to go to sleep</description>
79749 <description>Keep SYSCOUNTER active</description>
79756 <description>Request from index [11]</description>
79762 <description>Allow SYSCOUNTER to go to sleep</description>
79767 <description>Keep SYSCOUNTER active</description>
79774 <description>Request from index [12]</description>
79780 <description>Allow SYSCOUNTER to go to sleep</description>
79785 <description>Keep SYSCOUNTER active</description>
79792 <description>Request from index [13]</description>
79798 <description>Allow SYSCOUNTER to go to sleep</description>
79803 <description>Keep SYSCOUNTER active</description>
79810 <description>Request from index [14]</description>
79816 <description>Allow SYSCOUNTER to go to sleep</description>
79821 <description>Keep SYSCOUNTER active</description>
79828 <description>Request from index [15]</description>
79834 <description>Allow SYSCOUNTER to go to sleep</description>
79839 <description>Keep SYSCOUNTER active</description>
79848 … <description>Timeout after all CPUs gone into sleep state to stop the SYSCOUNTER</description>
79856 <description>Number of 32Ki cycles</description>
79864 … <description>Count to add to CC[0] when the event EVENTS_COMPARE[0] triggers.</description>
79872 <description>Count to add to CC[0]</description>
79880 <description>PWM configuration.</description>
79888 <description>The PWM compare value</description>
79896 <description>Configuration of clock output</description>
79904 <description>Enable 32Ki clock output on pin</description>
79910 <description>Disabled</description>
79915 <description>Enabled</description>
79922 <description>Enable fast clock output on pin</description>
79928 <description>Disabled</description>
79933 <description>Enabled</description>
79942 <description>Clock Configuration</description>
79950 <description>Fast clock divisor value of clock output</description>
79956 <description>GRTC LFCLK clock source selection</description>
79962 <description>GRTC LFCLK clock source is LFXO</description>
79967 <description>GRTC LFCLK clock source is system LFCLK</description>
79978 <description>Unspecified</description>
79984 … <description>Description cluster: The lower 32-bits of the SYSCOUNTER for index [n]</description>
79992 <description>The lower 32-bits of the SYSCOUNTER value.</description>
80000 … <description>Description cluster: The higher 20-bits of the SYSCOUNTER for index [n]</description>
80008 <description>The higher 20-bits of the SYSCOUNTER value.</description>
80014 <description>SYSCOUNTER busy status</description>
80020 <description>SYSCOUNTER is ready for read</description>
80025 …<description>SYSCOUNTER is busy, so not ready for read (value returned in the VALUE field of this …
80032 <description>The SYSCOUNTERL overflow indication after reading it.</description>
80038 <description>SYSCOUNTERL is not overflown</description>
80043 <description>SYSCOUNTERL overflown</description>
80052 …<description>Description cluster: Request to keep the SYSCOUNTER in the active state and prevent g…
80060 <description>Keep SYSCOUNTER in active state</description>
80066 <description>Allow SYSCOUNTER to go to sleep</description>
80071 <description>Keep SYSCOUNTER active</description>
80083 <description>Trace buffer monitor</description>
80101 <description>Start counter</description>
80109 <description>Start counter</description>
80115 <description>Trigger task</description>
80124 <description>Stop counter, clear counter value</description>
80132 <description>Stop counter, clear counter value</description>
80138 <description>Trigger task</description>
80147 <description>Save current counter value to COUNTSNAPSHOT</description>
80155 <description>Save current counter value to COUNTSNAPSHOT</description>
80161 <description>Trigger task</description>
80170 <description>Counter value equals half-full</description>
80178 <description>Counter value equals half-full</description>
80184 <description>Event not generated</description>
80189 <description>Event generated</description>
80198 <description>Counter value equals full</description>
80206 <description>Counter value equals full</description>
80212 <description>Event not generated</description>
80217 <description>Event generated</description>
80226 <description>Counter value saved to COUNTSNAPSHOT due to flush</description>
80234 <description>Counter value saved to COUNTSNAPSHOT due to flush</description>
80240 <description>Event not generated</description>
80245 <description>Event generated</description>
80254 <description>Enable or disable interrupt</description>
80262 <description>Enable or disable interrupt for event HALFFULL</description>
80268 <description>Disable</description>
80273 <description>Enable</description>
80280 <description>Enable or disable interrupt for event FULL</description>
80286 <description>Disable</description>
80291 <description>Enable</description>
80298 <description>Enable or disable interrupt for event FLUSH</description>
80304 <description>Disable</description>
80309 <description>Enable</description>
80318 <description>Enable interrupt</description>
80326 <description>Write '1' to enable interrupt for event HALFFULL</description>
80333 <description>Read: Disabled</description>
80338 <description>Read: Enabled</description>
80346 <description>Enable</description>
80353 <description>Write '1' to enable interrupt for event FULL</description>
80360 <description>Read: Disabled</description>
80365 <description>Read: Enabled</description>
80373 <description>Enable</description>
80380 <description>Write '1' to enable interrupt for event FLUSH</description>
80387 <description>Read: Disabled</description>
80392 <description>Read: Enabled</description>
80400 <description>Enable</description>
80409 <description>Disable interrupt</description>
80417 <description>Write '1' to disable interrupt for event HALFFULL</description>
80424 <description>Read: Disabled</description>
80429 <description>Read: Enabled</description>
80437 <description>Disable</description>
80444 <description>Write '1' to disable interrupt for event FULL</description>
80451 <description>Read: Disabled</description>
80456 <description>Read: Enabled</description>
80464 <description>Disable</description>
80471 <description>Write '1' to disable interrupt for event FLUSH</description>
80478 <description>Read: Disabled</description>
80483 <description>Read: Enabled</description>
80491 <description>Disable</description>
80500 <description>Pending interrupts</description>
80508 <description>Read pending status of interrupt for event HALFFULL</description>
80515 <description>Read: Not pending</description>
80520 <description>Read: Pending</description>
80527 <description>Read pending status of interrupt for event FULL</description>
80534 <description>Read: Not pending</description>
80539 <description>Read: Pending</description>
80546 <description>Read pending status of interrupt for event FLUSH</description>
80553 <description>Read: Not pending</description>
80558 <description>Read: Pending</description>
80567 <description>System RAM trace buffer total size in bytes</description>
80575 …<description>Must only be configured in STOP mode. Must be programmed to multiple of 16 bytes to m…
80577 maximum value 0x1000 i.e. 4096 bytes.</description>
80583 <description>0 bytes</description>
80588 <description>16 bytes</description>
80593 <description>4096 bytes</description>
80602 <description>Counter current value</description>
80610 …<description>Counter current value. Only writable when counter is in stopped state. Writing when n…
80611 state will generate a bus fault.</description>
80619 <description>Copy of the current COUNT value</description>
80627 … <description>TASKS_FLUSH will copy the current COUNT value to this register.</description>
80637 <description>USBHS</description>
80655 <description>Start the USB peripheral.</description>
80663 <description>Start the USB peripheral.</description>
80669 <description>Trigger task</description>
80678 <description>Event indicating that interrupt triggered at USBHS core</description>
80686 <description>Event indicating that interrupt triggered at USBHS core</description>
80692 <description>Event not generated</description>
80697 <description>Event generated</description>
80706 <description>Enable or disable interrupt</description>
80714 <description>Enable or disable interrupt for event CORE</description>
80720 <description>Disable</description>
80725 <description>Enable</description>
80734 <description>Enable interrupt</description>
80742 <description>Write '1' to enable interrupt for event CORE</description>
80749 <description>Read: Disabled</description>
80754 <description>Read: Enabled</description>
80762 <description>Enable</description>
80771 <description>Disable interrupt</description>
80779 <description>Write '1' to disable interrupt for event CORE</description>
80786 <description>Read: Disabled</description>
80791 <description>Read: Enabled</description>
80799 <description>Disable</description>
80808 <description>Pending interrupts</description>
80816 <description>Read pending status of interrupt for event CORE</description>
80823 <description>Read: Not pending</description>
80828 <description>Read: Pending</description>
80837 <description>Enable USB peripheral.</description>
80845 <description>Enable USB Controller</description>
80851 <description>USB Controller disabled.</description>
80856 <description>USB Controller enabled.</description>
80863 <description>Enable USB PHY</description>
80869 <description>USB PHY disabled.</description>
80874 <description>USB PHY enabled.</description>
80885 <description>External Memory Interface</description>
80903 <description>Start operation.</description>
80911 <description>Start operation.</description>
80917 <description>Trigger task</description>
80926 <description>Stop operation.</description>
80934 <description>Stop operation.</description>
80940 <description>Trigger task</description>
80949 … <description>Enable or disable locked APB access to serial memory controller.</description>
80957 <description>Enable or disable locked APB access to SSI.</description>
80963 <description>Disable locked APB access.</description>
80968 <description>Enable locked APB access.</description>
80977 <description>Reset the external memory.</description>
80990 <description>Reset is cleared.</description>
80995 <description>Reset is set.</description>
81004 <description>Event indicating that interrupt triggered at EXMIF core</description>
81012 <description>Event indicating that interrupt triggered at EXMIF core</description>
81018 <description>Event not generated</description>
81023 <description>Event generated</description>
81032 …<description>Event indicating that the START task is completed and the EXMIF has started.</descrip…
81040 …<description>Event indicating that the START task is completed and the EXMIF has started.</descrip…
81046 <description>Event not generated</description>
81051 <description>Event generated</description>
81060 <description>Enable or disable interrupt</description>
81068 <description>Enable or disable interrupt for event CORE</description>
81074 <description>Disable</description>
81079 <description>Enable</description>
81086 <description>Enable or disable interrupt for event STARTED</description>
81092 <description>Disable</description>
81097 <description>Enable</description>
81106 <description>Enable interrupt</description>
81114 <description>Write '1' to enable interrupt for event CORE</description>
81121 <description>Read: Disabled</description>
81126 <description>Read: Enabled</description>
81134 <description>Enable</description>
81141 <description>Write '1' to enable interrupt for event STARTED</description>
81148 <description>Read: Disabled</description>
81153 <description>Read: Enabled</description>
81161 <description>Enable</description>
81170 <description>Disable interrupt</description>
81178 <description>Write '1' to disable interrupt for event CORE</description>
81185 <description>Read: Disabled</description>
81190 <description>Read: Enabled</description>
81198 <description>Disable</description>
81205 <description>Write '1' to disable interrupt for event STARTED</description>
81212 <description>Read: Disabled</description>
81217 <description>Read: Enabled</description>
81225 <description>Disable</description>
81234 <description>Pending interrupts</description>
81242 <description>Read pending status of interrupt for event CORE</description>
81249 <description>Read: Not pending</description>
81254 <description>Read: Pending</description>
81261 <description>Read pending status of interrupt for event STARTED</description>
81268 <description>Read: Not pending</description>
81273 <description>Read: Pending</description>
81282 <description>Configuration for external memory device 1.</description>
81288 <description>Address offset for external memory device 1.</description>
81296 <description>External memory Offset.</description>
81304 <description>Upper address range for external memory device 1.</description>
81312 <description>Upper limit address.</description>
81320 <description>Enable or disable external memory access.</description>
81328 … <description>Enable or disable external memory access from AXI interface.</description>
81334 <description>Disable external memory.</description>
81339 <description>Enable external memory.</description>
81349 <description>Configuration for external memory device 2.</description>
81356 <description>Address offset for external memory device 2.</description>
81364 <description>External memory Offset.</description>
81372 <description>Upper address range for external memory device 2.</description>
81380 <description>Upper limit address.</description>
81388 <description>Enable or disable external memory access.</description>
81396 … <description>Enable or disable external memory access from AXI interface.</description>
81402 <description>Disable external memory.</description>
81407 <description>Enable external memory.</description>
81417 <description>Unspecified</description>
81423 <description>Unspecified</description>
81429 <description>This register controls the serial data transfer.</description>
81437 <description>Data Frame Size.</description>
81443 <description>Unspecified</description>
81448 <description>Unspecified</description>
81453 <description>Unspecified</description>
81458 <description>Unspecified</description>
81463 <description>Unspecified</description>
81468 <description>Unspecified</description>
81473 <description>Unspecified</description>
81478 <description>Unspecified</description>
81483 <description>Unspecified</description>
81488 <description>Unspecified</description>
81493 <description>Unspecified</description>
81498 <description>Unspecified</description>
81503 <description>Unspecified</description>
81508 <description>Unspecified</description>
81513 <description>Unspecified</description>
81518 <description>Unspecified</description>
81523 <description>Unspecified</description>
81528 <description>Unspecified</description>
81533 <description>Unspecified</description>
81538 <description>Unspecified</description>
81543 <description>Unspecified</description>
81548 <description>Unspecified</description>
81553 <description>Unspecified</description>
81558 <description>Unspecified</description>
81563 <description>Unspecified</description>
81568 <description>Unspecified</description>
81573 <description>Unspecified</description>
81578 <description>Unspecified</description>
81583 <description>Unspecified</description>
81588 <description>Unspecified</description>
81593 <description>Unspecified</description>
81598 <description>Unspecified</description>
81605 <description>Frame Format.</description>
81611 <description>Unspecified</description>
81616 <description>Unspecified</description>
81621 <description>Unspecified</description>
81628 <description>Serial Clock Phase.</description>
81634 <description>Unspecified</description>
81639 <description>Unspecified</description>
81646 <description>Serial Clock Polarity.</description>
81652 <description>Unspecified</description>
81657 <description>Unspecified</description>
81664 <description>Transfer Mode.</description>
81670 <description>Unspecified</description>
81675 <description>Unspecified</description>
81680 <description>Unspecified</description>
81685 <description>Unspecified</description>
81692 <description>Slave Output Enable.</description>
81698 <description>Unspecified</description>
81703 <description>Unspecified</description>
81710 <description>Shift Register Loop.</description>
81716 <description>Unspecified</description>
81721 <description>Unspecified</description>
81728 <description>Slave Select Toggle Enable.</description>
81734 <description>Unspecified</description>
81739 <description>Unspecified</description>
81746 <description>Control Frame Size.</description>
81752 <description>Unspecified</description>
81757 <description>Unspecified</description>
81762 <description>Unspecified</description>
81767 <description>Unspecified</description>
81772 <description>Unspecified</description>
81777 <description>Unspecified</description>
81782 <description>Unspecified</description>
81787 <description>Unspecified</description>
81792 <description>Unspecified</description>
81797 <description>Unspecified</description>
81802 <description>Unspecified</description>
81807 <description>Unspecified</description>
81812 <description>Unspecified</description>
81817 <description>Unspecified</description>
81822 <description>Unspecified</description>
81827 <description>Unspecified</description>
81834 <description>SPI Frame Format</description>
81840 <description>Unspecified</description>
81845 <description>Unspecified</description>
81850 <description>Unspecified</description>
81855 <description>Unspecified</description>
81862 <description>SPI Hyperbus Frame format enable.</description>
81868 <description>Unspecified</description>
81873 <description>Unspecified</description>
81880 <description>Enable Dynamic wait states in SPI mode of operation.</description>
81887 <description>Unspecified</description>
81892 <description>Unspecified</description>
81899 … <description>This field selects if DWC_ssi is working in Master or Slave mode</description>
81906 <description>Unspecified</description>
81911 <description>Unspecified</description>
81920 …<description>This register exists only when the DWC_ssi is configured as a master device.</descrip…
81928 <description>Number of Data Frames.</description>
81936 <description>This register enables and disables the DWC_ssi.</description>
81944 <description>SSI Enable.</description>
81950 <description>Unspecified</description>
81955 <description>Unspecified</description>
81964 …<description>This register controls the direction of the data word for the half-duplex Microwire s…
81972 <description>Microwire Transfer Mode.</description>
81978 <description>Unspecified</description>
81983 <description>Unspecified</description>
81990 <description>Microwire Control.</description>
81996 <description>Unspecified</description>
82001 <description>Unspecified</description>
82008 <description>Microwire Handshaking.</description>
82014 <description>Unspecified</description>
82019 <description>Unspecified</description>
82028 …<description>This register is valid only when the DWC_ssi is configured as a master device.</descr…
82036 <description>Slave Select Enable Flag.</description>
82042 <description>Unspecified</description>
82047 <description>Unspecified</description>
82056 …<description>This register is valid only when the DWC_ssi is configured as a master device.</descr…
82064 <description>SSI Clock Divider.</description>
82072 …<description>This register controls the threshold value for the transmit FIFO memory..</descriptio…
82080 <description>Transmit FIFO Threshold.</description>
82086 <description>Transfer start FIFO level.</description>
82094 …<description>This register controls the threshold value for the receive FIFO memory..</description>
82102 <description>Receive FIFO Threshold.</description>
82110 …<description>This register contains the number of valid data entries in the transmit FIFO memory.<…
82118 <description>Transmit FIFO Level.</description>
82127 …<description>This register contains the number of valid data entries in the receive FIFO memory.</…
82135 <description>Receive FIFO Level.</description>
82144 …description>This is a read-only register used to indicate the current transfer status, FIFO status…
82152 <description>SSI Busy Flag.</description>
82159 <description>Unspecified</description>
82164 <description>Unspecified</description>
82171 <description>Transmit FIFO Not Full.</description>
82178 <description>Unspecified</description>
82183 <description>Unspecified</description>
82190 <description>Transmit FIFO Empty.</description>
82197 <description>Unspecified</description>
82202 <description>Unspecified</description>
82209 <description>Receive FIFO Not Empty.</description>
82216 <description>Unspecified</description>
82221 <description>Unspecified</description>
82228 <description>Receive FIFO Full.</description>
82235 <description>Unspecified</description>
82240 <description>Unspecified</description>
82247 <description>Transmission Error.</description>
82254 <description>Unspecified</description>
82259 <description>Unspecified</description>
82266 <description>Data Collision Error.</description>
82273 <description>Unspecified</description>
82278 <description>Unspecified</description>
82287 …<description>This read/write register masks or enables all interrupts generated by the DWC_ssi.</d…
82295 <description>Transmit FIFO Empty Interrupt Mask</description>
82301 <description>Unspecified</description>
82306 <description>Unspecified</description>
82313 <description>Transmit FIFO Overflow Interrupt Mask</description>
82319 <description>Unspecified</description>
82324 <description>Unspecified</description>
82331 <description>Receive FIFO Underflow Interrupt Mask</description>
82337 <description>Unspecified</description>
82342 <description>Unspecified</description>
82349 <description>Receive FIFO Overflow Interrupt Mask</description>
82355 <description>Unspecified</description>
82360 <description>Unspecified</description>
82367 <description>Receive FIFO Full Interrupt Mask</description>
82373 <description>ssi_rxf_intr interrupt is masked</description>
82378 <description>ssi_rxf_intr interrupt is not masked</description>
82385 <description>Multi-Master Contention Interrupt Mask.</description>
82391 <description>Unspecified</description>
82396 <description>Unspecified</description>
82403 <description>XIP Receive FIFO Overflow Interrupt Mask</description>
82409 <description>Unspecified</description>
82414 <description>Unspecified</description>
82421 <description>Transmit FIFO Underflow Interrupt Mask</description>
82427 <description>Unspecified</description>
82432 <description>Unspecified</description>
82439 <description>SSI Done Interrupt Mask</description>
82446 <description>Unspecified</description>
82451 <description>Unspecified</description>
82460 …<description>This register reports the status of the DWC_ssi interrupts after they have been maske…
82468 <description>Transmit FIFO Empty Interrupt Status</description>
82475 <description>Unspecified</description>
82480 <description>Unspecified</description>
82487 <description>Transmit FIFO Overflow Interrupt Status</description>
82494 <description>Unspecified</description>
82499 <description>Unspecified</description>
82506 <description>Receive FIFO Underflow Interrupt Status</description>
82513 <description>Unspecified</description>
82518 <description>Unspecified</description>
82525 <description>Receive FIFO Overflow Interrupt Status</description>
82532 <description>Unspecified</description>
82537 <description>Unspecified</description>
82544 <description>Receive FIFO Full Interrupt Status</description>
82551 <description>Unspecified</description>
82556 <description>Unspecified</description>
82563 <description>Multi-Master Contention Interrupt Status.</description>
82570 <description>Unspecified</description>
82575 <description>Unspecified</description>
82582 <description>XIP Receive FIFO Overflow Interrupt Status</description>
82589 <description>Unspecified</description>
82594 <description>Unspecified</description>
82601 <description>Transmit FIFO Underflow Interrupt Status</description>
82608 <description>Unspecified</description>
82613 <description>Unspecified</description>
82620 <description>SSI Done Interrupt Status</description>
82627 <description>Unspecified</description>
82632 <description>Unspecified</description>
82641 <description>Raw Interrupt Status Register</description>
82649 <description>Transmit FIFO Empty Raw Interrupt Status</description>
82656 <description>Unspecified</description>
82661 <description>Unspecified</description>
82668 <description>Transmit FIFO Overflow Raw Interrupt Status</description>
82675 <description>Unspecified</description>
82680 <description>Unspecified</description>
82687 <description>Receive FIFO Underflow Raw Interrupt Status</description>
82694 <description>Unspecified</description>
82699 <description>Unspecified</description>
82706 <description>Receive FIFO Overflow Raw Interrupt Status</description>
82713 <description>Unspecified</description>
82718 <description>Unspecified</description>
82725 <description>Receive FIFO Full Raw Interrupt Status</description>
82732 <description>Unspecified</description>
82737 <description>Unspecified</description>
82744 <description>Multi-Master Contention Raw Interrupt Status.</description>
82751 <description>Unspecified</description>
82756 <description>Unspecified</description>
82763 <description>XIP Receive FIFO Overflow Raw Interrupt Status</description>
82770 <description>Unspecified</description>
82775 <description>Unspecified</description>
82782 <description>Transmit FIFO Underflow Interrupt Raw Status</description>
82789 <description>Unspecified</description>
82794 <description>Unspecified</description>
82801 <description>SSI Done Interrupt Raw Status</description>
82808 <description>Unspecified</description>
82813 <description>Unspecified</description>
82822 <description>Transmit FIFO Error Interrupt Clear Register</description>
82830 <description>Clear Transmit FIFO Overflow/Underflow Interrupt.</description>
82839 <description>Receive FIFO Overflow Interrupt Clear Register</description>
82847 <description>Clear Receive FIFO Overflow Interrupt.</description>
82856 <description>Receive FIFO Underflow Interrupt Clear Register</description>
82864 <description>Clear Receive FIFO Underflow Interrupt.</description>
82873 <description>Multi-Master Interrupt Clear Register</description>
82881 <description>Clear Multi-Master Contention Interrupt.</description>
82890 <description>Interrupt Clear Register</description>
82898 <description>Clear Interrupts.</description>
82907 …description>This register contains the peripherals identification code, which is written into the …
82915 <description>Identification code.</description>
82924 … <description>This read-only register stores the specific DWC_ssi component version.</description>
82932 … <description>Contains the hex representation of the Synopsys component version.</description>
82943 …<description>Description collection: The DWC_ssi data register is a 32-bit read/write buffer for t…
82951 <description>Data Register.</description>
82959 …<description>This register is only valid when the DWC_ssi is configured with rxd sample delay logi…
82967 <description>Receive Data (rxd) Sample Delay.</description>
82973 <description>Receive Data (rxd) Sampling Edge.</description>
82981 …<description>This register is used to control the serial data transfer in enhanced SPI mode of ope…
82989 <description>Address and instruction transfer format.</description>
82995 <description>Unspecified</description>
83000 <description>Unspecified</description>
83005 <description>Unspecified</description>
83010 <description>Unspecified</description>
83017 <description>This bit defines Length of Address to be transmitted.</description>
83023 <description>Unspecified</description>
83028 <description>Unspecified</description>
83033 <description>Unspecified</description>
83038 <description>Unspecified</description>
83043 <description>Unspecified</description>
83048 <description>Unspecified</description>
83053 <description>Unspecified</description>
83058 <description>Unspecified</description>
83063 <description>Unspecified</description>
83068 <description>Unspecified</description>
83073 <description>Unspecified</description>
83078 <description>Unspecified</description>
83083 <description>Unspecified</description>
83088 <description>Unspecified</description>
83093 <description>Unspecified</description>
83098 <description>Unspecified</description>
83105 <description>Mode bits enable in XIP mode.</description>
83112 <description>Dual/Quad/Octal mode instruction length in bits.</description>
83118 <description>Unspecified</description>
83123 <description>Unspecified</description>
83128 <description>Unspecified</description>
83133 <description>Unspecified</description>
83140 …<description>Wait cycles in Dual/Quad/Octal mode between control frames transmit and data receptio…
83146 <description>SPI DDR Enable bit.</description>
83152 <description>Instruction DDR Enable bit.</description>
83158 <description>Read data strobe enable bit.</description>
83164 <description>Fix DFS for XIP transfers.</description>
83171 <description>XIP instruction enable bit.</description>
83178 <description>Enable continuous transfer in XIP mode.</description>
83185 <description>SPI data mask enable bit.</description>
83191 …<description>Enable rxds signaling during address and command phase of Hyperbus transfer.</descrip…
83197 <description>XIP Mode bits length.</description>
83204 <description>Unspecified</description>
83209 <description>Unspecified</description>
83214 <description>Unspecified</description>
83219 <description>Unspecified</description>
83226 <description>Enables XIP pre-fetch functionality in DWC_ssi.</description>
83233 <description>Enables clock stretching capability in SPI transfers.</description>
83241 … <description>This Register is valid only when SSIC_HAS_DDR is equal to 1.</description>
83249 …<description>TXD Drive edge register which decided the driving edge of transmit data.</description>
83257 …<description>This register carries the mode bits which are sent in the XIP mode of operation after…
83265 … <description>XIP mode bits to be sent after address phase of XIP transfer.</description>
83274 <description>Unspecified</description>
83280 <description>This Register is valid only when SSIC_XIP_EN is equal to 1.</description>
83288 <description>XIP INCR transfer opcode.</description>
83296 <description>This Register is valid only when SSIC_XIP_EN is equal to 1.</description>
83304 <description>XIP WRAP transfer opcode.</description>
83312 … <description>This Register is valid only when SSIC_CONCURRENT_XIP_EN is equal to 1.</description>
83320 <description>SPI Frame Format</description>
83326 <description>Unspecified</description>
83331 <description>Unspecified</description>
83336 <description>Unspecified</description>
83341 <description>Unspecified</description>
83348 <description>Address and instruction transfer format.</description>
83354 <description>Unspecified</description>
83359 <description>Unspecified</description>
83364 <description>Unspecified</description>
83369 <description>Unspecified</description>
83376 <description>This bit defines Length of Address to be transmitted.</description>
83382 <description>Unspecified</description>
83387 <description>Unspecified</description>
83392 <description>Unspecified</description>
83397 <description>Unspecified</description>
83402 <description>Unspecified</description>
83407 <description>Unspecified</description>
83412 <description>Unspecified</description>
83417 <description>Unspecified</description>
83422 <description>Unspecified</description>
83427 <description>Unspecified</description>
83432 <description>Unspecified</description>
83437 <description>Unspecified</description>
83442 <description>Unspecified</description>
83447 <description>Unspecified</description>
83452 <description>Unspecified</description>
83457 <description>Unspecified</description>
83464 <description>Dual/Quad/Octal mode instruction length in bits.</description>
83470 <description>Unspecified</description>
83475 <description>Unspecified</description>
83480 <description>Unspecified</description>
83485 <description>Unspecified</description>
83492 <description>Mode bits enable in XIP mode.</description>
83498 …<description>Wait cycles in Dual/Quad/Octal mode between control frames transmit and data receptio…
83504 <description>Fix DFS for XIP transfers.</description>
83510 <description>SPI DDR Enable bit.</description>
83516 <description>Instruction DDR Enable bit.</description>
83522 <description>Read data strobe enable bit.</description>
83528 <description>XIP instruction enable bit.</description>
83534 <description>Enable continuous transfer in XIP mode.</description>
83541 <description>SPI Hyperbus Frame format enable for XIP transfers.</description>
83547 …<description>Enable rxds signaling during address and command phase of Hyperbus transfer.</descrip…
83553 <description>XIP Mode bits length.</description>
83559 <description>Unspecified</description>
83564 <description>Unspecified</description>
83569 <description>Unspecified</description>
83574 <description>Unspecified</description>
83581 <description>Enables XIP pre-fetch functionality in DWC_ssi.</description>
83589 <description>XIP Receive FIFO Overflow Interrupt Clear Register</description>
83597 <description>Clear XIP Receive FIFO Overflow Interrupt.</description>
83606 …<description>This Register is valid only when both SSIC_XIP_WRITE_REG_EN is set to 1.</description>
83614 <description>XIP Write INCR transfer opcode.</description>
83620 <description>Reserved bits - Read Only</description>
83629 …<description>This Register is valid only when both SSIC_XIP_WRITE_REG_EN is set to 1.</description>
83637 <description>XIP Write WRAP transfer opcode.</description>
83643 <description>Reserved bits - Read Only</description>
83652 … <description>This Register is valid only when SSIC_XIP_WRITE_REG_EN is equal to 1.</description>
83660 <description>SPI Frame Format</description>
83666 <description>Unspecified</description>
83671 <description>Unspecified</description>
83676 <description>Unspecified</description>
83681 <description>Unspecified</description>
83688 <description>Address and instruction transfer format.</description>
83694 <description>Unspecified</description>
83699 <description>Unspecified</description>
83704 <description>Unspecified</description>
83709 <description>Unspecified</description>
83716 <description>This bit defines Length of Address to be transmitted.</description>
83722 <description>Unspecified</description>
83727 <description>Unspecified</description>
83732 <description>Unspecified</description>
83737 <description>Unspecified</description>
83742 <description>Unspecified</description>
83747 <description>Unspecified</description>
83752 <description>Unspecified</description>
83757 <description>Unspecified</description>
83762 <description>Unspecified</description>
83769 <description>Dual/Quad/Octal mode instruction length in bits.</description>
83775 <description>Unspecified</description>
83780 <description>Unspecified</description>
83785 <description>Unspecified</description>
83790 <description>Unspecified</description>
83797 <description>SPI DDR Enable bit.</description>
83803 <description>Instruction DDR Enable bit.</description>
83809 … <description>SPI Hyperbus Frame format enable for XIP Write transfers.</description>
83815 …<description>Enable rxds signaling during address and command phase of Hyperbus transfer.</descrip…
83821 <description>Reserved bits - Read Only</description>
83828 …<description>Wait cycles in Dual/Quad/Octal mode between control frames transmit and data receptio…
83834 <description>Reserved bits - Read Only</description>
83847 <description>BELLBOARD public registers</description>
83865 <description>Description collection: Task TRIGGER[n]</description>
83873 <description>Task TRIGGER[n]</description>
83879 <description>Trigger task</description>
83890 <description>AUXPLL</description>
83905 <description>Start the AUXPLL</description>
83913 <description>Start the AUXPLL</description>
83919 <description>Trigger task</description>
83928 <description>Stop the AUXPLL</description>
83936 <description>Stop the AUXPLL</description>
83942 <description>Trigger task</description>
83951 <description>Change fine frequency</description>
83959 <description>Change fine frequency</description>
83965 <description>Trigger task</description>
83974 <description>Change base frequency</description>
83982 <description>Change base frequency</description>
83988 <description>Trigger task</description>
83997 <description>Start automated frequency increment</description>
84005 <description>Start automated frequency increment</description>
84011 <description>Trigger task</description>
84020 <description>Stop automated frequency increment</description>
84028 <description>Stop automated frequency increment</description>
84034 <description>Trigger task</description>
84043 <description>AUXPLL started</description>
84051 <description>AUXPLL started</description>
84057 <description>Event not generated</description>
84062 <description>Event generated</description>
84071 <description>AUXPLL stopped</description>
84079 <description>AUXPLL stopped</description>
84085 <description>Event not generated</description>
84090 <description>Event generated</description>
84099 <description>AUXPLL locked</description>
84107 <description>AUXPLL locked</description>
84113 <description>Event not generated</description>
84118 <description>Event generated</description>
84127 <description>Enable or disable interrupt</description>
84135 <description>Enable or disable interrupt for event STARTED</description>
84141 <description>Disable</description>
84146 <description>Enable</description>
84153 <description>Enable or disable interrupt for event STOPPED</description>
84159 <description>Disable</description>
84164 <description>Enable</description>
84171 <description>Enable or disable interrupt for event LOCKED</description>
84177 <description>Disable</description>
84182 <description>Enable</description>
84191 <description>Enable interrupt</description>
84199 <description>Write '1' to enable interrupt for event STARTED</description>
84206 <description>Read: Disabled</description>
84211 <description>Read: Enabled</description>
84219 <description>Enable</description>
84226 <description>Write '1' to enable interrupt for event STOPPED</description>
84233 <description>Read: Disabled</description>
84238 <description>Read: Enabled</description>
84246 <description>Enable</description>
84253 <description>Write '1' to enable interrupt for event LOCKED</description>
84260 <description>Read: Disabled</description>
84265 <description>Read: Enabled</description>
84273 <description>Enable</description>
84282 <description>Disable interrupt</description>
84290 <description>Write '1' to disable interrupt for event STARTED</description>
84297 <description>Read: Disabled</description>
84302 <description>Read: Enabled</description>
84310 <description>Disable</description>
84317 <description>Write '1' to disable interrupt for event STOPPED</description>
84324 <description>Read: Disabled</description>
84329 <description>Read: Enabled</description>
84337 <description>Disable</description>
84344 <description>Write '1' to disable interrupt for event LOCKED</description>
84351 <description>Read: Disabled</description>
84356 <description>Read: Enabled</description>
84364 <description>Disable</description>
84373 <description>Pending interrupts</description>
84381 <description>Read pending status of interrupt for event STARTED</description>
84388 <description>Read: Not pending</description>
84393 <description>Read: Pending</description>
84400 <description>Read pending status of interrupt for event STOPPED</description>
84407 <description>Read: Not pending</description>
84412 <description>Read: Pending</description>
84419 <description>Read pending status of interrupt for event LOCKED</description>
84426 <description>Read: Not pending</description>
84431 <description>Read: Pending</description>
84440 <description>Status of AUXPLL</description>
84448 <description>AUXPLL mode</description>
84454 <description>Freerunning mode</description>
84459 <description>Locked mode</description>
84466 <description>AUXPLL running status</description>
84472 <description>PLL not running</description>
84477 <description>PLL running</description>
84484 <description>Actual fractional PLL divider ratio</description>
84492 <description>Unspecified</description>
84498 <description>AUXPLL configuration</description>
84506 <description>Output buffer drive strength selection</description>
84512 <description>Lowest drive strength</description>
84517 <description>Highest drive strength</description>
84524 <description>Constant current tune for ring oscillator</description>
84530 <description>Minimum current</description>
84535 <description>Default current for audio and USB</description>
84540 <description>Maximum current</description>
84547 <description>Turn off sigma delta modulation</description>
84553 <description>Sigma Delta Modulator enabled</description>
84558 <description>Sigma Delta Modulator disabled</description>
84565 <description>Turn off dither in sigma delta modulator</description>
84571 <description>Dither enabled</description>
84576 <description>Dither disabled</description>
84583 <description>Loop divider base settings</description>
84589 <description>Low range divider setting</description>
84594 <description>Mid range divider setting</description>
84599 <description>High range divider setting</description>
84604 <description>Maximum static divider setting</description>
84614 <description>Unspecified</description>
84620 <description>Ring oscillator core process corner tuning</description>
84628 <description>Tuning value</description>
84634 <description>Highest frequency</description>
84639 <description>Default center frequency for audio and USB</description>
84644 <description>Lowest frequency</description>
84654 <description>Unspecified</description>
84660 <description>AUXPLL frequency selection</description>
84668 <description>Set fractional PLL divider ratio</description>
84674 <description>Division ratio of 4</description>
84679 <description>Division ratio for audio 44.1kHz frequency family</description>
84684 <description>Division ratio for USB PHY 24MHz clock</description>
84689 <description>Division ratio for audio 48kHz frequency family</description>
84694 <description>Division ratio of 5</description>
84703 <description>Frequency increment</description>
84711 <description>Signed 8-bit frequency increment, applied to FREQUENCY</description>
84719 <description>Frequency increment period in 1 us steps</description>
84727 <description>Frequency increment period</description>
84735 <description>AUXPLL output prescaler</description>
84743 <description>Prescaler ratio</description>
84749 … <description>Divider disabled. Bypassed external clock still supported</description>
84754 <description>Divide by 1</description>
84759 <description>Divide by 2</description>
84764 <description>Divide by 3</description>
84769 <description>Divide by 4</description>
84774 <description>Divide by 6</description>
84779 <description>Divide by 8</description>
84784 <description>Divide by 12</description>
84789 <description>Divide by 16</description>
84798 <description>Freerunning mode control</description>
84806 <description>Freerunning mode control</description>
84812 <description>Automatically handled by the AUXPLL peripheral</description>
84817 <description>Keep AUXPLL in freerunning mode</description>
84822 <description>Keep AUXPLL in locked mode</description>
84832 <description>Enable LOCK for mirrored registers</description>
84840 <description>Lock for mirrored registers</description>
84846 <description>Lock disabled</description>
84851 <description>Lock enabled</description>
84862 <description>VPR peripheral registers</description>
84879 <description>Description collection: VPR task [n] register</description>
84887 <description>VPR task [n] register</description>
84893 <description>Trigger task</description>
84904 <description>IPCT APB registers 0</description>
84926 …<description>Description collection: Trigger event on IPCT source channel n if there are no active…
84934 …<description>Trigger event on IPCT source channel n if there are no active signals present on that…
84940 <description>Trigger task</description>
84951 …<description>Description collection: Flush IPCT sink channel n. Any pending IPCT signal on that ch…
84953 configuring the SHORTS register accordingly.</description>
84961 <description>Flush IPCT sink channel n. Any pending IPCT signal on that channel will
84963 configuring the SHORTS register accordingly.</description>
84969 <description>Trigger task</description>
84980 … <description>Description collection: Subscribe configuration for task SEND[n]</description>
84988 <description>DPPI channel that task SEND[n] will subscribe to</description>
84999 <description>Disable subscription</description>
85004 <description>Enable subscription</description>
85015 … <description>Description collection: Subscribe configuration for task FLUSH[n]</description>
85023 <description>DPPI channel that task FLUSH[n] will subscribe to</description>
85034 <description>Disable subscription</description>
85039 <description>Enable subscription</description>
85050 <description>Description collection: Event received on IPCT sink channel n</description>
85058 <description>Event received on IPCT sink channel n</description>
85064 <description>Event not generated</description>
85069 <description>Event generated</description>
85080 … <description>Description collection: Event received when hardware handshake of SEND task for IPCT
85082 on that channel.</description>
85090 <description>Event received when hardware handshake of SEND task for IPCT
85092 on that channel.</description>
85098 <description>Event not generated</description>
85103 <description>Event generated</description>
85114 … <description>Description collection: Publish configuration for event RECEIVE[n]</description>
85122 <description>DPPI channel that event RECEIVE[n] will publish to</description>
85133 <description>Disable publishing</description>
85138 <description>Enable publishing</description>
85149 … <description>Description collection: Publish configuration for event READY[n]</description>
85157 <description>DPPI channel that event READY[n] will publish to</description>
85168 <description>Disable publishing</description>
85173 <description>Enable publishing</description>
85182 <description>Shortcuts between local events and tasks</description>
85190 <description>Shortcut between event RECEIVE[0] and task FLUSH[0]</description>
85196 <description>Disable shortcut</description>
85201 <description>Enable shortcut</description>
85208 <description>Shortcut between event RECEIVE[1] and task FLUSH[1]</description>
85214 <description>Disable shortcut</description>
85219 <description>Enable shortcut</description>
85226 <description>Shortcut between event RECEIVE[2] and task FLUSH[2]</description>
85232 <description>Disable shortcut</description>
85237 <description>Enable shortcut</description>
85244 <description>Shortcut between event RECEIVE[3] and task FLUSH[3]</description>
85250 <description>Disable shortcut</description>
85255 <description>Enable shortcut</description>
85262 <description>Shortcut between event RECEIVE[4] and task FLUSH[4]</description>
85268 <description>Disable shortcut</description>
85273 <description>Enable shortcut</description>
85280 <description>Shortcut between event RECEIVE[5] and task FLUSH[5]</description>
85286 <description>Disable shortcut</description>
85291 <description>Enable shortcut</description>
85298 <description>Shortcut between event RECEIVE[6] and task FLUSH[6]</description>
85304 <description>Disable shortcut</description>
85309 <description>Enable shortcut</description>
85316 <description>Shortcut between event RECEIVE[7] and task FLUSH[7]</description>
85322 <description>Disable shortcut</description>
85327 <description>Enable shortcut</description>
85336 <description>Enable or disable interrupt</description>
85344 <description>Enable or disable interrupt for event RECEIVE[0]</description>
85350 <description>Disable</description>
85355 <description>Enable</description>
85362 <description>Enable or disable interrupt for event RECEIVE[1]</description>
85368 <description>Disable</description>
85373 <description>Enable</description>
85380 <description>Enable or disable interrupt for event RECEIVE[2]</description>
85386 <description>Disable</description>
85391 <description>Enable</description>
85398 <description>Enable or disable interrupt for event RECEIVE[3]</description>
85404 <description>Disable</description>
85409 <description>Enable</description>
85416 <description>Enable or disable interrupt for event RECEIVE[4]</description>
85422 <description>Disable</description>
85427 <description>Enable</description>
85434 <description>Enable or disable interrupt for event RECEIVE[5]</description>
85440 <description>Disable</description>
85445 <description>Enable</description>
85452 <description>Enable or disable interrupt for event RECEIVE[6]</description>
85458 <description>Disable</description>
85463 <description>Enable</description>
85470 <description>Enable or disable interrupt for event RECEIVE[7]</description>
85476 <description>Disable</description>
85481 <description>Enable</description>
85488 <description>Enable or disable interrupt for event READY[0]</description>
85494 <description>Disable</description>
85499 <description>Enable</description>
85506 <description>Enable or disable interrupt for event READY[1]</description>
85512 <description>Disable</description>
85517 <description>Enable</description>
85524 <description>Enable or disable interrupt for event READY[2]</description>
85530 <description>Disable</description>
85535 <description>Enable</description>
85542 <description>Enable or disable interrupt for event READY[3]</description>
85548 <description>Disable</description>
85553 <description>Enable</description>
85560 <description>Enable or disable interrupt for event READY[4]</description>
85566 <description>Disable</description>
85571 <description>Enable</description>
85578 <description>Enable or disable interrupt for event READY[5]</description>
85584 <description>Disable</description>
85589 <description>Enable</description>
85596 <description>Enable or disable interrupt for event READY[6]</description>
85602 <description>Disable</description>
85607 <description>Enable</description>
85614 <description>Enable or disable interrupt for event READY[7]</description>
85620 <description>Disable</description>
85625 <description>Enable</description>
85634 <description>Enable interrupt</description>
85642 <description>Write '1' to enable interrupt for event RECEIVE[0]</description>
85649 <description>Read: Disabled</description>
85654 <description>Read: Enabled</description>
85662 <description>Enable</description>
85669 <description>Write '1' to enable interrupt for event RECEIVE[1]</description>
85676 <description>Read: Disabled</description>
85681 <description>Read: Enabled</description>
85689 <description>Enable</description>
85696 <description>Write '1' to enable interrupt for event RECEIVE[2]</description>
85703 <description>Read: Disabled</description>
85708 <description>Read: Enabled</description>
85716 <description>Enable</description>
85723 <description>Write '1' to enable interrupt for event RECEIVE[3]</description>
85730 <description>Read: Disabled</description>
85735 <description>Read: Enabled</description>
85743 <description>Enable</description>
85750 <description>Write '1' to enable interrupt for event RECEIVE[4]</description>
85757 <description>Read: Disabled</description>
85762 <description>Read: Enabled</description>
85770 <description>Enable</description>
85777 <description>Write '1' to enable interrupt for event RECEIVE[5]</description>
85784 <description>Read: Disabled</description>
85789 <description>Read: Enabled</description>
85797 <description>Enable</description>
85804 <description>Write '1' to enable interrupt for event RECEIVE[6]</description>
85811 <description>Read: Disabled</description>
85816 <description>Read: Enabled</description>
85824 <description>Enable</description>
85831 <description>Write '1' to enable interrupt for event RECEIVE[7]</description>
85838 <description>Read: Disabled</description>
85843 <description>Read: Enabled</description>
85851 <description>Enable</description>
85858 <description>Write '1' to enable interrupt for event READY[0]</description>
85865 <description>Read: Disabled</description>
85870 <description>Read: Enabled</description>
85878 <description>Enable</description>
85885 <description>Write '1' to enable interrupt for event READY[1]</description>
85892 <description>Read: Disabled</description>
85897 <description>Read: Enabled</description>
85905 <description>Enable</description>
85912 <description>Write '1' to enable interrupt for event READY[2]</description>
85919 <description>Read: Disabled</description>
85924 <description>Read: Enabled</description>
85932 <description>Enable</description>
85939 <description>Write '1' to enable interrupt for event READY[3]</description>
85946 <description>Read: Disabled</description>
85951 <description>Read: Enabled</description>
85959 <description>Enable</description>
85966 <description>Write '1' to enable interrupt for event READY[4]</description>
85973 <description>Read: Disabled</description>
85978 <description>Read: Enabled</description>
85986 <description>Enable</description>
85993 <description>Write '1' to enable interrupt for event READY[5]</description>
86000 <description>Read: Disabled</description>
86005 <description>Read: Enabled</description>
86013 <description>Enable</description>
86020 <description>Write '1' to enable interrupt for event READY[6]</description>
86027 <description>Read: Disabled</description>
86032 <description>Read: Enabled</description>
86040 <description>Enable</description>
86047 <description>Write '1' to enable interrupt for event READY[7]</description>
86054 <description>Read: Disabled</description>
86059 <description>Read: Enabled</description>
86067 <description>Enable</description>
86076 <description>Disable interrupt</description>
86084 <description>Write '1' to disable interrupt for event RECEIVE[0]</description>
86091 <description>Read: Disabled</description>
86096 <description>Read: Enabled</description>
86104 <description>Disable</description>
86111 <description>Write '1' to disable interrupt for event RECEIVE[1]</description>
86118 <description>Read: Disabled</description>
86123 <description>Read: Enabled</description>
86131 <description>Disable</description>
86138 <description>Write '1' to disable interrupt for event RECEIVE[2]</description>
86145 <description>Read: Disabled</description>
86150 <description>Read: Enabled</description>
86158 <description>Disable</description>
86165 <description>Write '1' to disable interrupt for event RECEIVE[3]</description>
86172 <description>Read: Disabled</description>
86177 <description>Read: Enabled</description>
86185 <description>Disable</description>
86192 <description>Write '1' to disable interrupt for event RECEIVE[4]</description>
86199 <description>Read: Disabled</description>
86204 <description>Read: Enabled</description>
86212 <description>Disable</description>
86219 <description>Write '1' to disable interrupt for event RECEIVE[5]</description>
86226 <description>Read: Disabled</description>
86231 <description>Read: Enabled</description>
86239 <description>Disable</description>
86246 <description>Write '1' to disable interrupt for event RECEIVE[6]</description>
86253 <description>Read: Disabled</description>
86258 <description>Read: Enabled</description>
86266 <description>Disable</description>
86273 <description>Write '1' to disable interrupt for event RECEIVE[7]</description>
86280 <description>Read: Disabled</description>
86285 <description>Read: Enabled</description>
86293 <description>Disable</description>
86300 <description>Write '1' to disable interrupt for event READY[0]</description>
86307 <description>Read: Disabled</description>
86312 <description>Read: Enabled</description>
86320 <description>Disable</description>
86327 <description>Write '1' to disable interrupt for event READY[1]</description>
86334 <description>Read: Disabled</description>
86339 <description>Read: Enabled</description>
86347 <description>Disable</description>
86354 <description>Write '1' to disable interrupt for event READY[2]</description>
86361 <description>Read: Disabled</description>
86366 <description>Read: Enabled</description>
86374 <description>Disable</description>
86381 <description>Write '1' to disable interrupt for event READY[3]</description>
86388 <description>Read: Disabled</description>
86393 <description>Read: Enabled</description>
86401 <description>Disable</description>
86408 <description>Write '1' to disable interrupt for event READY[4]</description>
86415 <description>Read: Disabled</description>
86420 <description>Read: Enabled</description>
86428 <description>Disable</description>
86435 <description>Write '1' to disable interrupt for event READY[5]</description>
86442 <description>Read: Disabled</description>
86447 <description>Read: Enabled</description>
86455 <description>Disable</description>
86462 <description>Write '1' to disable interrupt for event READY[6]</description>
86469 <description>Read: Disabled</description>
86474 <description>Read: Enabled</description>
86482 <description>Disable</description>
86489 <description>Write '1' to disable interrupt for event READY[7]</description>
86496 <description>Read: Disabled</description>
86501 <description>Read: Enabled</description>
86509 <description>Disable</description>
86518 <description>Pending interrupts</description>
86526 <description>Read pending status of interrupt for event RECEIVE[0]</description>
86533 <description>Read: Not pending</description>
86538 <description>Read: Pending</description>
86545 <description>Read pending status of interrupt for event RECEIVE[1]</description>
86552 <description>Read: Not pending</description>
86557 <description>Read: Pending</description>
86564 <description>Read pending status of interrupt for event RECEIVE[2]</description>
86571 <description>Read: Not pending</description>
86576 <description>Read: Pending</description>
86583 <description>Read pending status of interrupt for event RECEIVE[3]</description>
86590 <description>Read: Not pending</description>
86595 <description>Read: Pending</description>
86602 <description>Read pending status of interrupt for event RECEIVE[4]</description>
86609 <description>Read: Not pending</description>
86614 <description>Read: Pending</description>
86621 <description>Read pending status of interrupt for event RECEIVE[5]</description>
86628 <description>Read: Not pending</description>
86633 <description>Read: Pending</description>
86640 <description>Read pending status of interrupt for event RECEIVE[6]</description>
86647 <description>Read: Not pending</description>
86652 <description>Read: Pending</description>
86659 <description>Read pending status of interrupt for event RECEIVE[7]</description>
86666 <description>Read: Not pending</description>
86671 <description>Read: Pending</description>
86678 <description>Read pending status of interrupt for event READY[0]</description>
86685 <description>Read: Not pending</description>
86690 <description>Read: Pending</description>
86697 <description>Read pending status of interrupt for event READY[1]</description>
86704 <description>Read: Not pending</description>
86709 <description>Read: Pending</description>
86716 <description>Read pending status of interrupt for event READY[2]</description>
86723 <description>Read: Not pending</description>
86728 <description>Read: Pending</description>
86735 <description>Read pending status of interrupt for event READY[3]</description>
86742 <description>Read: Not pending</description>
86747 <description>Read: Pending</description>
86754 <description>Read pending status of interrupt for event READY[4]</description>
86761 <description>Read: Not pending</description>
86766 <description>Read: Pending</description>
86773 <description>Read pending status of interrupt for event READY[5]</description>
86780 <description>Read: Not pending</description>
86785 <description>Read: Pending</description>
86792 <description>Read pending status of interrupt for event READY[6]</description>
86799 <description>Read: Not pending</description>
86804 <description>Read: Pending</description>
86811 <description>Read pending status of interrupt for event READY[7]</description>
86818 <description>Read: Not pending</description>
86823 <description>Read: Pending</description>
86832 <description>Unspecified</description>
86838 <description>Overflow status for SEND tasks Write 0 to clear</description>
86846 <description>Overflow status for SEND[0] task</description>
86852 <description>Task overflow has happened</description>
86857 <description>Task overflow has not happened</description>
86864 <description>Overflow status for SEND[1] task</description>
86870 <description>Task overflow has happened</description>
86875 <description>Task overflow has not happened</description>
86882 <description>Overflow status for SEND[2] task</description>
86888 <description>Task overflow has happened</description>
86893 <description>Task overflow has not happened</description>
86900 <description>Overflow status for SEND[3] task</description>
86906 <description>Task overflow has happened</description>
86911 <description>Task overflow has not happened</description>
86918 <description>Overflow status for SEND[4] task</description>
86924 <description>Task overflow has happened</description>
86929 <description>Task overflow has not happened</description>
86936 <description>Overflow status for SEND[5] task</description>
86942 <description>Task overflow has happened</description>
86947 <description>Task overflow has not happened</description>
86954 <description>Overflow status for SEND[6] task</description>
86960 <description>Task overflow has happened</description>
86965 <description>Task overflow has not happened</description>
86972 <description>Overflow status for SEND[7] task</description>
86978 <description>Task overflow has happened</description>
86983 <description>Task overflow has not happened</description>
86995 <description>MUTEX 0</description>
87012 <description>Description collection: Mutex register</description>
87020 <description>Mutex register n</description>
87026 <description>Mutex n is in unlocked state</description>
87031 <description>Mutex n is in locked state</description>
87042 <description>I3C 0</description>
87061 <description>Event indicating that interrupt triggered at I3C core</description>
87069 <description>Event indicating that interrupt triggered at I3C core</description>
87075 <description>Event not generated</description>
87080 <description>Event generated</description>
87089 <description>Event indicating that interrupt triggered at I3C DMA</description>
87097 <description>Event indicating that interrupt triggered at I3C DMA</description>
87103 <description>Event not generated</description>
87108 <description>Event generated</description>
87117 <description>Enable or disable interrupt</description>
87125 <description>Enable or disable interrupt for event CORE</description>
87131 <description>Disable</description>
87136 <description>Enable</description>
87143 <description>Enable or disable interrupt for event DMA</description>
87149 <description>Disable</description>
87154 <description>Enable</description>
87163 <description>Enable interrupt</description>
87171 <description>Write '1' to enable interrupt for event CORE</description>
87178 <description>Read: Disabled</description>
87183 <description>Read: Enabled</description>
87191 <description>Enable</description>
87198 <description>Write '1' to enable interrupt for event DMA</description>
87205 <description>Read: Disabled</description>
87210 <description>Read: Enabled</description>
87218 <description>Enable</description>
87227 <description>Disable interrupt</description>
87235 <description>Write '1' to disable interrupt for event CORE</description>
87242 <description>Read: Disabled</description>
87247 <description>Read: Enabled</description>
87255 <description>Disable</description>
87262 <description>Write '1' to disable interrupt for event DMA</description>
87269 <description>Read: Disabled</description>
87274 <description>Read: Enabled</description>
87282 <description>Disable</description>
87291 <description>Pending interrupts</description>
87299 <description>Read pending status of interrupt for event CORE</description>
87306 <description>Read: Not pending</description>
87311 <description>Read: Pending</description>
87318 <description>Read pending status of interrupt for event DMA</description>
87325 <description>Read: Not pending</description>
87330 <description>Read: Pending</description>
87339 <description>Enable I3C peripheral.</description>
87347 <description>Enable</description>
87353 <description>I3C peripheral disabled.</description>
87358 <description>I3C peripheral enabled.</description>
87367 <description>Unspecified</description>
87373 <description>Start offset of recovered clock</description>
87381 <description>Value</description>
87389 …<description>Maximum cycle ratio between SDA/SCL and CDR (clock and data recovery) clock</descript…
87397 <description>Value</description>
87405 <description>Maximum skew between SCL and SCL in CDR clock cycles</description>
87413 <description>Value</description>
87422 <description>I3C slave interface 0</description>
87430 <description>I2C or I3C mode select signal</description>
87436 <description>Unspecified</description>
87441 <description>Unspecified</description>
87448 <description>Slave activity mode for GETSTATUS CCC</description>
87454 <description>Pending interrupt information for GETSTATUS CCC</description>
87460 <description>Slave static address valid</description>
87466 <description>Unspecified</description>
87471 <description>Unspecified</description>
87478 <description>Slave static address</description>
87484 <description>Slave maximum read data rate</description>
87490 <description>Slave maximum write write rate</description>
87496 <description>Slave maximum clock data turnaround time</description>
87502 <description>Device Characteristic Register value</description>
87510 <description>I3C slave interface 1</description>
87518 <description>Slave wakeup signal</description>
87525 <description>Unspecified</description>
87530 <description>Unspecified</description>
87539 <description>Slave Device Provisioned ID 0</description>
87547 <description>Additional Meaning</description>
87553 <description>Instance ID</description>
87559 <description>Part ID</description>
87567 <description>Slave Device Provisioned ID 1</description>
87575 <description>Provisional ID Type Selector</description>
87581 <description>MIPI Manufacturer ID</description>
87589 …<description>Enable or disable the SDA high-keeper used for Master-to-Slave and Slave-to-Master bu…
87597 <description>Enable or disable the SDA high-keeper</description>
87603 <description>High-keeper disabled.</description>
87608 <description>High-keeper enabled.</description>
87617 …<description>Enable or disable the SCL high-keeper used for Master-to-Slave and Slave-to-Master bu…
87625 <description>Enable or disable the SCL high-keeper</description>
87631 <description>High-keeper disabled.</description>
87636 <description>High-keeper enabled.</description>
87647 <description>VPR peripheral registers 0</description>
87668 <description>Description collection: VPR task [n] register</description>
87676 <description>VPR task [n] register</description>
87682 <description>Trigger task</description>
87693 …<description>Description collection: Subscribe configuration for task TASKS_TRIGGER[n]</descriptio…
87701 <description>Subscription enable bit</description>
87707 <description>Disable subscription</description>
87712 <description>Enable subscription</description>
87723 <description>Description collection: VPR event [n] register</description>
87731 <description>VPR event [n] register</description>
87737 <description>Event not generated</description>
87742 <description>Event generated</description>
87753 …<description>Description collection: Publish configuration for event EVENTS_TRIGGERED[n]</descript…
87761 <description>Publication enable bit</description>
87767 <description>Disable publishing</description>
87772 <description>Enable publishing</description>
87781 <description>Enable or disable interrupt</description>
87789 <description>Enable or disable interrupt for event TRIGGERED[0]</description>
87795 <description>Disable</description>
87800 <description>Enable</description>
87807 <description>Enable or disable interrupt for event TRIGGERED[1]</description>
87813 <description>Disable</description>
87818 <description>Enable</description>
87825 <description>Enable or disable interrupt for event TRIGGERED[2]</description>
87831 <description>Disable</description>
87836 <description>Enable</description>
87843 <description>Enable or disable interrupt for event TRIGGERED[3]</description>
87849 <description>Disable</description>
87854 <description>Enable</description>
87861 <description>Enable or disable interrupt for event TRIGGERED[4]</description>
87867 <description>Disable</description>
87872 <description>Enable</description>
87879 <description>Enable or disable interrupt for event TRIGGERED[5]</description>
87885 <description>Disable</description>
87890 <description>Enable</description>
87897 <description>Enable or disable interrupt for event TRIGGERED[6]</description>
87903 <description>Disable</description>
87908 <description>Enable</description>
87915 <description>Enable or disable interrupt for event TRIGGERED[7]</description>
87921 <description>Disable</description>
87926 <description>Enable</description>
87933 <description>Enable or disable interrupt for event TRIGGERED[8]</description>
87939 <description>Disable</description>
87944 <description>Enable</description>
87951 <description>Enable or disable interrupt for event TRIGGERED[9]</description>
87957 <description>Disable</description>
87962 <description>Enable</description>
87969 <description>Enable or disable interrupt for event TRIGGERED[10]</description>
87975 <description>Disable</description>
87980 <description>Enable</description>
87987 <description>Enable or disable interrupt for event TRIGGERED[11]</description>
87993 <description>Disable</description>
87998 <description>Enable</description>
88005 <description>Enable or disable interrupt for event TRIGGERED[12]</description>
88011 <description>Disable</description>
88016 <description>Enable</description>
88023 <description>Enable or disable interrupt for event TRIGGERED[13]</description>
88029 <description>Disable</description>
88034 <description>Enable</description>
88041 <description>Enable or disable interrupt for event TRIGGERED[14]</description>
88047 <description>Disable</description>
88052 <description>Enable</description>
88059 <description>Enable or disable interrupt for event TRIGGERED[15]</description>
88065 <description>Disable</description>
88070 <description>Enable</description>
88077 <description>Enable or disable interrupt for event TRIGGERED[16]</description>
88083 <description>Disable</description>
88088 <description>Enable</description>
88095 <description>Enable or disable interrupt for event TRIGGERED[17]</description>
88101 <description>Disable</description>
88106 <description>Enable</description>
88113 <description>Enable or disable interrupt for event TRIGGERED[18]</description>
88119 <description>Disable</description>
88124 <description>Enable</description>
88131 <description>Enable or disable interrupt for event TRIGGERED[19]</description>
88137 <description>Disable</description>
88142 <description>Enable</description>
88149 <description>Enable or disable interrupt for event TRIGGERED[20]</description>
88155 <description>Disable</description>
88160 <description>Enable</description>
88167 <description>Enable or disable interrupt for event TRIGGERED[21]</description>
88173 <description>Disable</description>
88178 <description>Enable</description>
88185 <description>Enable or disable interrupt for event TRIGGERED[22]</description>
88191 <description>Disable</description>
88196 <description>Enable</description>
88203 <description>Enable or disable interrupt for event TRIGGERED[23]</description>
88209 <description>Disable</description>
88214 <description>Enable</description>
88221 <description>Enable or disable interrupt for event TRIGGERED[24]</description>
88227 <description>Disable</description>
88232 <description>Enable</description>
88239 <description>Enable or disable interrupt for event TRIGGERED[25]</description>
88245 <description>Disable</description>
88250 <description>Enable</description>
88257 <description>Enable or disable interrupt for event TRIGGERED[26]</description>
88263 <description>Disable</description>
88268 <description>Enable</description>
88275 <description>Enable or disable interrupt for event TRIGGERED[27]</description>
88281 <description>Disable</description>
88286 <description>Enable</description>
88293 <description>Enable or disable interrupt for event TRIGGERED[28]</description>
88299 <description>Disable</description>
88304 <description>Enable</description>
88311 <description>Enable or disable interrupt for event TRIGGERED[29]</description>
88317 <description>Disable</description>
88322 <description>Enable</description>
88329 <description>Enable or disable interrupt for event TRIGGERED[30]</description>
88335 <description>Disable</description>
88340 <description>Enable</description>
88347 <description>Enable or disable interrupt for event TRIGGERED[31]</description>
88353 <description>Disable</description>
88358 <description>Enable</description>
88367 <description>Enable interrupt</description>
88375 <description>Write '1' to enable interrupt for event TRIGGERED[0]</description>
88382 <description>Read: Disabled</description>
88387 <description>Read: Enabled</description>
88395 <description>Enable</description>
88402 <description>Write '1' to enable interrupt for event TRIGGERED[1]</description>
88409 <description>Read: Disabled</description>
88414 <description>Read: Enabled</description>
88422 <description>Enable</description>
88429 <description>Write '1' to enable interrupt for event TRIGGERED[2]</description>
88436 <description>Read: Disabled</description>
88441 <description>Read: Enabled</description>
88449 <description>Enable</description>
88456 <description>Write '1' to enable interrupt for event TRIGGERED[3]</description>
88463 <description>Read: Disabled</description>
88468 <description>Read: Enabled</description>
88476 <description>Enable</description>
88483 <description>Write '1' to enable interrupt for event TRIGGERED[4]</description>
88490 <description>Read: Disabled</description>
88495 <description>Read: Enabled</description>
88503 <description>Enable</description>
88510 <description>Write '1' to enable interrupt for event TRIGGERED[5]</description>
88517 <description>Read: Disabled</description>
88522 <description>Read: Enabled</description>
88530 <description>Enable</description>
88537 <description>Write '1' to enable interrupt for event TRIGGERED[6]</description>
88544 <description>Read: Disabled</description>
88549 <description>Read: Enabled</description>
88557 <description>Enable</description>
88564 <description>Write '1' to enable interrupt for event TRIGGERED[7]</description>
88571 <description>Read: Disabled</description>
88576 <description>Read: Enabled</description>
88584 <description>Enable</description>
88591 <description>Write '1' to enable interrupt for event TRIGGERED[8]</description>
88598 <description>Read: Disabled</description>
88603 <description>Read: Enabled</description>
88611 <description>Enable</description>
88618 <description>Write '1' to enable interrupt for event TRIGGERED[9]</description>
88625 <description>Read: Disabled</description>
88630 <description>Read: Enabled</description>
88638 <description>Enable</description>
88645 <description>Write '1' to enable interrupt for event TRIGGERED[10]</description>
88652 <description>Read: Disabled</description>
88657 <description>Read: Enabled</description>
88665 <description>Enable</description>
88672 <description>Write '1' to enable interrupt for event TRIGGERED[11]</description>
88679 <description>Read: Disabled</description>
88684 <description>Read: Enabled</description>
88692 <description>Enable</description>
88699 <description>Write '1' to enable interrupt for event TRIGGERED[12]</description>
88706 <description>Read: Disabled</description>
88711 <description>Read: Enabled</description>
88719 <description>Enable</description>
88726 <description>Write '1' to enable interrupt for event TRIGGERED[13]</description>
88733 <description>Read: Disabled</description>
88738 <description>Read: Enabled</description>
88746 <description>Enable</description>
88753 <description>Write '1' to enable interrupt for event TRIGGERED[14]</description>
88760 <description>Read: Disabled</description>
88765 <description>Read: Enabled</description>
88773 <description>Enable</description>
88780 <description>Write '1' to enable interrupt for event TRIGGERED[15]</description>
88787 <description>Read: Disabled</description>
88792 <description>Read: Enabled</description>
88800 <description>Enable</description>
88807 <description>Write '1' to enable interrupt for event TRIGGERED[16]</description>
88814 <description>Read: Disabled</description>
88819 <description>Read: Enabled</description>
88827 <description>Enable</description>
88834 <description>Write '1' to enable interrupt for event TRIGGERED[17]</description>
88841 <description>Read: Disabled</description>
88846 <description>Read: Enabled</description>
88854 <description>Enable</description>
88861 <description>Write '1' to enable interrupt for event TRIGGERED[18]</description>
88868 <description>Read: Disabled</description>
88873 <description>Read: Enabled</description>
88881 <description>Enable</description>
88888 <description>Write '1' to enable interrupt for event TRIGGERED[19]</description>
88895 <description>Read: Disabled</description>
88900 <description>Read: Enabled</description>
88908 <description>Enable</description>
88915 <description>Write '1' to enable interrupt for event TRIGGERED[20]</description>
88922 <description>Read: Disabled</description>
88927 <description>Read: Enabled</description>
88935 <description>Enable</description>
88942 <description>Write '1' to enable interrupt for event TRIGGERED[21]</description>
88949 <description>Read: Disabled</description>
88954 <description>Read: Enabled</description>
88962 <description>Enable</description>
88969 <description>Write '1' to enable interrupt for event TRIGGERED[22]</description>
88976 <description>Read: Disabled</description>
88981 <description>Read: Enabled</description>
88989 <description>Enable</description>
88996 <description>Write '1' to enable interrupt for event TRIGGERED[23]</description>
89003 <description>Read: Disabled</description>
89008 <description>Read: Enabled</description>
89016 <description>Enable</description>
89023 <description>Write '1' to enable interrupt for event TRIGGERED[24]</description>
89030 <description>Read: Disabled</description>
89035 <description>Read: Enabled</description>
89043 <description>Enable</description>
89050 <description>Write '1' to enable interrupt for event TRIGGERED[25]</description>
89057 <description>Read: Disabled</description>
89062 <description>Read: Enabled</description>
89070 <description>Enable</description>
89077 <description>Write '1' to enable interrupt for event TRIGGERED[26]</description>
89084 <description>Read: Disabled</description>
89089 <description>Read: Enabled</description>
89097 <description>Enable</description>
89104 <description>Write '1' to enable interrupt for event TRIGGERED[27]</description>
89111 <description>Read: Disabled</description>
89116 <description>Read: Enabled</description>
89124 <description>Enable</description>
89131 <description>Write '1' to enable interrupt for event TRIGGERED[28]</description>
89138 <description>Read: Disabled</description>
89143 <description>Read: Enabled</description>
89151 <description>Enable</description>
89158 <description>Write '1' to enable interrupt for event TRIGGERED[29]</description>
89165 <description>Read: Disabled</description>
89170 <description>Read: Enabled</description>
89178 <description>Enable</description>
89185 <description>Write '1' to enable interrupt for event TRIGGERED[30]</description>
89192 <description>Read: Disabled</description>
89197 <description>Read: Enabled</description>
89205 <description>Enable</description>
89212 <description>Write '1' to enable interrupt for event TRIGGERED[31]</description>
89219 <description>Read: Disabled</description>
89224 <description>Read: Enabled</description>
89232 <description>Enable</description>
89241 <description>Disable interrupt</description>
89249 <description>Write '1' to disable interrupt for event TRIGGERED[0]</description>
89256 <description>Read: Disabled</description>
89261 <description>Read: Enabled</description>
89269 <description>Disable</description>
89276 <description>Write '1' to disable interrupt for event TRIGGERED[1]</description>
89283 <description>Read: Disabled</description>
89288 <description>Read: Enabled</description>
89296 <description>Disable</description>
89303 <description>Write '1' to disable interrupt for event TRIGGERED[2]</description>
89310 <description>Read: Disabled</description>
89315 <description>Read: Enabled</description>
89323 <description>Disable</description>
89330 <description>Write '1' to disable interrupt for event TRIGGERED[3]</description>
89337 <description>Read: Disabled</description>
89342 <description>Read: Enabled</description>
89350 <description>Disable</description>
89357 <description>Write '1' to disable interrupt for event TRIGGERED[4]</description>
89364 <description>Read: Disabled</description>
89369 <description>Read: Enabled</description>
89377 <description>Disable</description>
89384 <description>Write '1' to disable interrupt for event TRIGGERED[5]</description>
89391 <description>Read: Disabled</description>
89396 <description>Read: Enabled</description>
89404 <description>Disable</description>
89411 <description>Write '1' to disable interrupt for event TRIGGERED[6]</description>
89418 <description>Read: Disabled</description>
89423 <description>Read: Enabled</description>
89431 <description>Disable</description>
89438 <description>Write '1' to disable interrupt for event TRIGGERED[7]</description>
89445 <description>Read: Disabled</description>
89450 <description>Read: Enabled</description>
89458 <description>Disable</description>
89465 <description>Write '1' to disable interrupt for event TRIGGERED[8]</description>
89472 <description>Read: Disabled</description>
89477 <description>Read: Enabled</description>
89485 <description>Disable</description>
89492 <description>Write '1' to disable interrupt for event TRIGGERED[9]</description>
89499 <description>Read: Disabled</description>
89504 <description>Read: Enabled</description>
89512 <description>Disable</description>
89519 <description>Write '1' to disable interrupt for event TRIGGERED[10]</description>
89526 <description>Read: Disabled</description>
89531 <description>Read: Enabled</description>
89539 <description>Disable</description>
89546 <description>Write '1' to disable interrupt for event TRIGGERED[11]</description>
89553 <description>Read: Disabled</description>
89558 <description>Read: Enabled</description>
89566 <description>Disable</description>
89573 <description>Write '1' to disable interrupt for event TRIGGERED[12]</description>
89580 <description>Read: Disabled</description>
89585 <description>Read: Enabled</description>
89593 <description>Disable</description>
89600 <description>Write '1' to disable interrupt for event TRIGGERED[13]</description>
89607 <description>Read: Disabled</description>
89612 <description>Read: Enabled</description>
89620 <description>Disable</description>
89627 <description>Write '1' to disable interrupt for event TRIGGERED[14]</description>
89634 <description>Read: Disabled</description>
89639 <description>Read: Enabled</description>
89647 <description>Disable</description>
89654 <description>Write '1' to disable interrupt for event TRIGGERED[15]</description>
89661 <description>Read: Disabled</description>
89666 <description>Read: Enabled</description>
89674 <description>Disable</description>
89681 <description>Write '1' to disable interrupt for event TRIGGERED[16]</description>
89688 <description>Read: Disabled</description>
89693 <description>Read: Enabled</description>
89701 <description>Disable</description>
89708 <description>Write '1' to disable interrupt for event TRIGGERED[17]</description>
89715 <description>Read: Disabled</description>
89720 <description>Read: Enabled</description>
89728 <description>Disable</description>
89735 <description>Write '1' to disable interrupt for event TRIGGERED[18]</description>
89742 <description>Read: Disabled</description>
89747 <description>Read: Enabled</description>
89755 <description>Disable</description>
89762 <description>Write '1' to disable interrupt for event TRIGGERED[19]</description>
89769 <description>Read: Disabled</description>
89774 <description>Read: Enabled</description>
89782 <description>Disable</description>
89789 <description>Write '1' to disable interrupt for event TRIGGERED[20]</description>
89796 <description>Read: Disabled</description>
89801 <description>Read: Enabled</description>
89809 <description>Disable</description>
89816 <description>Write '1' to disable interrupt for event TRIGGERED[21]</description>
89823 <description>Read: Disabled</description>
89828 <description>Read: Enabled</description>
89836 <description>Disable</description>
89843 <description>Write '1' to disable interrupt for event TRIGGERED[22]</description>
89850 <description>Read: Disabled</description>
89855 <description>Read: Enabled</description>
89863 <description>Disable</description>
89870 <description>Write '1' to disable interrupt for event TRIGGERED[23]</description>
89877 <description>Read: Disabled</description>
89882 <description>Read: Enabled</description>
89890 <description>Disable</description>
89897 <description>Write '1' to disable interrupt for event TRIGGERED[24]</description>
89904 <description>Read: Disabled</description>
89909 <description>Read: Enabled</description>
89917 <description>Disable</description>
89924 <description>Write '1' to disable interrupt for event TRIGGERED[25]</description>
89931 <description>Read: Disabled</description>
89936 <description>Read: Enabled</description>
89944 <description>Disable</description>
89951 <description>Write '1' to disable interrupt for event TRIGGERED[26]</description>
89958 <description>Read: Disabled</description>
89963 <description>Read: Enabled</description>
89971 <description>Disable</description>
89978 <description>Write '1' to disable interrupt for event TRIGGERED[27]</description>
89985 <description>Read: Disabled</description>
89990 <description>Read: Enabled</description>
89998 <description>Disable</description>
90005 <description>Write '1' to disable interrupt for event TRIGGERED[28]</description>
90012 <description>Read: Disabled</description>
90017 <description>Read: Enabled</description>
90025 <description>Disable</description>
90032 <description>Write '1' to disable interrupt for event TRIGGERED[29]</description>
90039 <description>Read: Disabled</description>
90044 <description>Read: Enabled</description>
90052 <description>Disable</description>
90059 <description>Write '1' to disable interrupt for event TRIGGERED[30]</description>
90066 <description>Read: Disabled</description>
90071 <description>Read: Enabled</description>
90079 <description>Disable</description>
90086 <description>Write '1' to disable interrupt for event TRIGGERED[31]</description>
90093 <description>Read: Disabled</description>
90098 <description>Read: Enabled</description>
90106 <description>Disable</description>
90115 <description>Pending interrupts</description>
90123 <description>Read pending status of interrupt for event TRIGGERED[0]</description>
90130 <description>Read: Not pending</description>
90135 <description>Read: Pending</description>
90142 <description>Read pending status of interrupt for event TRIGGERED[1]</description>
90149 <description>Read: Not pending</description>
90154 <description>Read: Pending</description>
90161 <description>Read pending status of interrupt for event TRIGGERED[2]</description>
90168 <description>Read: Not pending</description>
90173 <description>Read: Pending</description>
90180 <description>Read pending status of interrupt for event TRIGGERED[3]</description>
90187 <description>Read: Not pending</description>
90192 <description>Read: Pending</description>
90199 <description>Read pending status of interrupt for event TRIGGERED[4]</description>
90206 <description>Read: Not pending</description>
90211 <description>Read: Pending</description>
90218 <description>Read pending status of interrupt for event TRIGGERED[5]</description>
90225 <description>Read: Not pending</description>
90230 <description>Read: Pending</description>
90237 <description>Read pending status of interrupt for event TRIGGERED[6]</description>
90244 <description>Read: Not pending</description>
90249 <description>Read: Pending</description>
90256 <description>Read pending status of interrupt for event TRIGGERED[7]</description>
90263 <description>Read: Not pending</description>
90268 <description>Read: Pending</description>
90275 <description>Read pending status of interrupt for event TRIGGERED[8]</description>
90282 <description>Read: Not pending</description>
90287 <description>Read: Pending</description>
90294 <description>Read pending status of interrupt for event TRIGGERED[9]</description>
90301 <description>Read: Not pending</description>
90306 <description>Read: Pending</description>
90313 <description>Read pending status of interrupt for event TRIGGERED[10]</description>
90320 <description>Read: Not pending</description>
90325 <description>Read: Pending</description>
90332 <description>Read pending status of interrupt for event TRIGGERED[11]</description>
90339 <description>Read: Not pending</description>
90344 <description>Read: Pending</description>
90351 <description>Read pending status of interrupt for event TRIGGERED[12]</description>
90358 <description>Read: Not pending</description>
90363 <description>Read: Pending</description>
90370 <description>Read pending status of interrupt for event TRIGGERED[13]</description>
90377 <description>Read: Not pending</description>
90382 <description>Read: Pending</description>
90389 <description>Read pending status of interrupt for event TRIGGERED[14]</description>
90396 <description>Read: Not pending</description>
90401 <description>Read: Pending</description>
90408 <description>Read pending status of interrupt for event TRIGGERED[15]</description>
90415 <description>Read: Not pending</description>
90420 <description>Read: Pending</description>
90427 <description>Read pending status of interrupt for event TRIGGERED[16]</description>
90434 <description>Read: Not pending</description>
90439 <description>Read: Pending</description>
90446 <description>Read pending status of interrupt for event TRIGGERED[17]</description>
90453 <description>Read: Not pending</description>
90458 <description>Read: Pending</description>
90465 <description>Read pending status of interrupt for event TRIGGERED[18]</description>
90472 <description>Read: Not pending</description>
90477 <description>Read: Pending</description>
90484 <description>Read pending status of interrupt for event TRIGGERED[19]</description>
90491 <description>Read: Not pending</description>
90496 <description>Read: Pending</description>
90503 <description>Read pending status of interrupt for event TRIGGERED[20]</description>
90510 <description>Read: Not pending</description>
90515 <description>Read: Pending</description>
90522 <description>Read pending status of interrupt for event TRIGGERED[21]</description>
90529 <description>Read: Not pending</description>
90534 <description>Read: Pending</description>
90541 <description>Read pending status of interrupt for event TRIGGERED[22]</description>
90548 <description>Read: Not pending</description>
90553 <description>Read: Pending</description>
90560 <description>Read pending status of interrupt for event TRIGGERED[23]</description>
90567 <description>Read: Not pending</description>
90572 <description>Read: Pending</description>
90579 <description>Read pending status of interrupt for event TRIGGERED[24]</description>
90586 <description>Read: Not pending</description>
90591 <description>Read: Pending</description>
90598 <description>Read pending status of interrupt for event TRIGGERED[25]</description>
90605 <description>Read: Not pending</description>
90610 <description>Read: Pending</description>
90617 <description>Read pending status of interrupt for event TRIGGERED[26]</description>
90624 <description>Read: Not pending</description>
90629 <description>Read: Pending</description>
90636 <description>Read pending status of interrupt for event TRIGGERED[27]</description>
90643 <description>Read: Not pending</description>
90648 <description>Read: Pending</description>
90655 <description>Read pending status of interrupt for event TRIGGERED[28]</description>
90662 <description>Read: Not pending</description>
90667 <description>Read: Pending</description>
90674 <description>Read pending status of interrupt for event TRIGGERED[29]</description>
90681 <description>Read: Not pending</description>
90686 <description>Read: Pending</description>
90693 <description>Read pending status of interrupt for event TRIGGERED[30]</description>
90700 <description>Read: Not pending</description>
90705 <description>Read: Pending</description>
90712 <description>Read pending status of interrupt for event TRIGGERED[31]</description>
90719 <description>Read: Not pending</description>
90724 <description>Read: Pending</description>
90733 <description>Unspecified</description>
90739 <description>Abstract Data 0. Read/write data for argument 0</description>
90747 <description>Abstract Data 0</description>
90755 <description>Abstract Data 1. Read/write data for argument 1</description>
90763 <description>Abstract Data 1</description>
90771 <description>Debug Module Control</description>
90779 <description>Reset signal for the debug module.</description>
90785 <description>Reset the debug module itself</description>
90790 <description>Normal operation</description>
90797 <description>Reset signal output from the debug module to the system.</description>
90803 <description>Reset inactive</description>
90808 <description>Reset active</description>
90815 <description>Clear the halt on reset request.</description>
90822 <description>No operation when written 0.</description>
90827 <description>Clears the halt on reset request</description>
90834 <description>Set the halt on reset request.</description>
90841 <description>No operation when written 0.</description>
90846 <description>Sets the halt on reset request</description>
90853 <description>The high 10 bits of hartsel.</description>
90860 <description>The low 10 bits of hartsel.</description>
90867 <description>Definition of currently selected harts.</description>
90874 <description>Single hart selected.</description>
90879 <description>Multiple harts selected</description>
90886 <description>Clear the havereset.</description>
90893 <description>No operation when written 0.</description>
90898 <description>Clears the havereset for selected harts.</description>
90905 <description>Reset harts.</description>
90911 <description>Reset de-asserted.</description>
90916 <description>Reset asserted.</description>
90923 <description>Resume currently selected harts.</description>
90930 <description>No operation when written 0.</description>
90935 <description>Currently selected harts resumed.</description>
90942 <description>Halt currently selected harts.</description>
90949 … <description>Clears halt request bit for all currently selected harts.</description>
90954 <description>Currently selected harts halted.</description>
90963 <description>Debug Module Status</description>
90971 <description>Version of the debug module.</description>
90977 <description>Debug module not present.</description>
90982 …<description>There is a Debug Module and it conforms to version 0.11 of this specifcation.</descri…
90987 …<description>There is a Debug Module and it conforms to version 0.13 of this specifcation.</descri…
90992 …<description>There is a Debug Module but it does not conform to any available version of the spec.…
90999 <description>Configuration string.</description>
91005 …<description>The confstrptr0..confstrptr3 holds information which is not relevant to the configura…
91010 …<description>The confstrptr0..confstrptr3 holds the address of the configuration string.</descript…
91017 <description>Halt-on-reset support status.</description>
91023 <description>Halt-on-reset is supported.</description>
91028 <description>Halt-on-reset is not supported.</description>
91035 <description>Authentication busy status.</description>
91041 <description>The authentication module is ready.</description>
91046 <description>The authentication module is busy.</description>
91053 <description>Authentication status.</description>
91059 … <description>Authentication required before using the debug module.</description>
91064 <description>Authentication passed.</description>
91071 <description>Any currently selected harts halted status.</description>
91077 <description>None of the currently selected harts halted.</description>
91082 <description>Any of the currently selected harts halted.</description>
91089 <description>All currently selected harts halted status.</description>
91095 <description>Not all of the currently selected harts halted.</description>
91100 <description>All of the currently selected harts halted.</description>
91107 <description>Any currently selected harts running status.</description>
91113 <description>None of the currently selected harts running.</description>
91118 <description>Any of the currently selected harts running.</description>
91125 <description>All currently selected harts running status.</description>
91131 <description>Not all of the currently selected harts running.</description>
91136 <description>All of the currently selected harts running.</description>
91143 <description>Any currently selected harts unavailable status.</description>
91149 <description>None of the currently selected harts unavailable.</description>
91154 <description>Any of the currently selected harts unavailable.</description>
91161 <description>All currently selected harts unavailable status.</description>
91167 <description>Not all of the currently selected harts unavailable.</description>
91172 <description>All of the currently selected harts unavailable.</description>
91179 <description>Any currently selected harts nonexistent status.</description>
91185 <description>None of the currently selected harts nonexistent.</description>
91190 <description>Any of the currently selected harts nonexistent.</description>
91197 <description>All currently selected harts nonexistent status.</description>
91203 <description>Not all of the currently selected harts nonexistent.</description>
91208 <description>All of the currently selected harts nonexistent.</description>
91215 … <description>Any currently selected harts acknowledged last resume request.</description>
91221 … <description>None of the currently selected harts acknowledged last resume request.</description>
91226 … <description>Any of the currently selected harts acknowledged last resume request.</description>
91233 <description>All currently selected harts acknowledged last resume</description>
91239 …<description>Not all of the currently selected harts acknowledged last resume request.</descriptio…
91244 … <description>All of the currently selected harts acknowledged last resume request.</description>
91251 …<description>Any currently selected harts have been reset and reset is not acknowledged.</descript…
91257 …<description>None of the currently selected harts have been reset and reset is not acknowledget.</…
91262 …<description>Any of the currently selected harts have been reset and reset is not acknowledge.</de…
91269 …<description>All currently selected harts have been reset and reset is not acknowledge</descriptio…
91275 …<description>Not all of the currently selected harts have been reset and reset is not acknowledge.…
91280 …<description>All of the currently selected harts have been reset and reset is not acknowledge.</de…
91287 …<description>Implicit ebreak instruction at the non-existent word immediately after the Program Bu…
91293 <description>No implicit ebreak instruction.</description>
91298 <description>Implicit ebreak instruction.</description>
91307 <description>Hart Information</description>
91315 <description>Data Address</description>
91322 <description>Data Size</description>
91329 <description>Data Access</description>
91336 <description>The data registers are shadowed in the hart
91338 corresponds to a single argument.</description>
91343 <description>The data registers are shadowed in the hart's
91345 the memory map.</description>
91352 <description>Number of dscratch registers</description>
91361 <description>Halt Summary 1</description>
91369 <description>Halt Summary 1</description>
91378 <description>Hart Array Window Select</description>
91386 …<description>The high bits of this field may be tied to 0, depending on how large the array mask r…
91387 … E.g. on a system with 48 harts only bit 0 of this field may actually be writable.</description>
91396 <description>Hart Array Window</description>
91404 <description>Mask data.</description>
91412 <description>Abstract Control and Status</description>
91420 …<description>Number of data registers that are implemented as part of the abstract command interfa…
91427 <description>Command error when the abstract command fails.</description>
91433 <description>No error.</description>
91438 <description>An abstract command was executing while command,
91440 or written. This status is only written if cmderr contains 0</description>
91445 <description>The requested command is notsupported,
91446 regardless of whether the hart is running or not.</description>
91451 <description>An exception occurred while executing the
91452 command (e.g. while executing theProgram Buffer).</description>
91457 <description>The abstract command couldn't execute
91458 … because the hart wasn't in the required state (running/halted). or unavailable.</description>
91463 <description>The abstract command failed due to abus
91464 error (e.g. alignment, access size, or timeout).</description>
91469 <description>The command failed for another reason.</description>
91476 <description>Abstract command execution status.</description>
91483 <description>Not busy.</description>
91488 <description>An abstract command is currently being executed.
91489 …t as soon as command is written, and is not cleared until that command has completed.</description>
91496 … <description>Size of the Program Buffer, in 32-bit words. Valid sizes are 0 - 1.</description>
91505 <description>Abstract command</description>
91513 …<description>This Field is interpreted in a command specific manner, described for each abstract c…
91519 … <description>The type determines the overall functionality of this abstract command.</description>
91525 <description>Register Access Command</description>
91530 <description>Quick Access Command</description>
91535 <description>Memory Access Command</description>
91544 <description>Abstract Command Autoexec</description>
91552 …<description>When a bit in this field is 1, read or write accesses to the corresponding data word …
91553 command in command to be executed again.</description>
91560 …<description>When a bit in this field is 1, read or write accesses to the corresponding progbuf wo…
91561 the command in command to be executed again.</description>
91572 <description>Description collection: Configuration String Pointer [n]</description>
91580 <description>Address</description>
91589 <description>Next Debug Module</description>
91597 <description>Address</description>
91608 <description>Description collection: Program Buffer [n]</description>
91616 <description>Data</description>
91625 <description>Authentication Data</description>
91633 <description>Data</description>
91642 <description>Halt Summary 2</description>
91650 <description>Halt Summary 2</description>
91659 <description>Halt Summary 3</description>
91667 <description>Halt Summary 3</description>
91676 <description>System Bus Addres 127:96</description>
91684 <description>Accesses bits 127:96 of the physical address in
91686 wide).</description>
91695 <description>System Bus Access Control and Status</description>
91709 <description>8-bit system bus accesses are supported.</description>
91722 <description>16-bit system bus accesses are supported.</description>
91735 <description>32-bit system bus accesses are supported.</description>
91748 <description>64-bit system bus accesses are supported.</description>
91761 <description>128-bit system bus accesses are supported.</description>
91768 …<description>Width of system bus addresses in bits. (0 indicates there is no bus access support.)<…
91781 <description>There was no bus error.</description>
91786 <description>There was a timeout.</description>
91791 <description>A bad address was accessed.</description>
91796 <description>There was an alignment error.</description>
91801 <description>An access of unsupported size was requested.</description>
91806 <description>Other.</description>
91819 <description>Every read from sbdata0 automatically
91820 triggers a system bus read at the (possibly autoincremented) address.</description>
91833 <description>sbaddress is incremented by the access
91834 size (in bytes) selected in sbaccess after every system bus access.</description>
91847 <description>8-bit.</description>
91852 <description>16-bit.</description>
91857 <description>32-bit.</description>
91862 <description>64-bit.</description>
91867 <description>128-bit.</description>
91880 <description>Every write to sbaddress0 automatically
91881 triggers a system bus read at the new address.</description>
91894 <description>System bus master is not busy.</description>
91899 <description>System bus master is busy.</description>
91912 <description>No error.</description>
91917 <description>Debugger access attempted while one in progress.</description>
91930 <description>The System Bus interface conforms to mainline
91931 … drafts of thia RISC-V External Debug Support spec older than 1 January, 2018.</description>
91936 …<description>The System Bus interface conforms to RISC-V External Debug Support version 0.14.0-DRA…
91937 Other values are reserved for future versions.</description>
91946 <description>System Bus Addres 31:0</description>
91954 <description>Accesses bits 31:0 of the physical address in
91955 sbaddress.</description>
91964 <description>System Bus Addres 63:32</description>
91972 <description>Accesses bits 63:32 of the physical address in
91974 wide).</description>
91983 <description>System Bus Addres 95:64</description>
91991 <description>Accesses bits 95:64 of the physical address in
91993 wide).</description>
92002 <description>System Bus Data 31:0</description>
92010 <description>Accesses bits 31:0 of sbdata</description>
92019 <description>System Bus Data 63:32</description>
92027 <description>Accesses bits 63:32 of sbdata (if the system bus
92028 is that wide).</description>
92037 <description>System Bus Data 95:64</description>
92045 <description>Accesses bits 95:64 of sbdata (if the system bus
92046 is that wide).</description>
92055 <description>System Bus Data 127:96</description>
92063 <description>Accesses bits 127:96 of sbdata (if the system bus
92064 is that wide).</description>
92073 <description>Halt summary 0</description>
92081 <description>Halt summary 0</description>
92091 <description>State of the CPU after a core reset</description>
92099 <description>Controls CPU running state after a core reset.</description>
92105 …<description>CPU stopped. If this is the CPU state after a core reset, setting this bit will chang…
92110 …description>CPU running. If this is the CPU state after a core reset, clearing this bit will chang…
92119 <description>Initial value of the PC at CPU start.</description>
92127 <description>Initial value of the PC at CPU start.</description>
92137 <description>Controller Area Network 0</description>
92156 <description>Start the CAN peripheral.</description>
92164 <description>Start the CAN peripheral.</description>
92170 <description>Trigger task</description>
92179 <description>Request to stop the CAN peripheral</description>
92187 <description>Request to stop the CAN peripheral</description>
92193 <description>Trigger task</description>
92202 <description>Stop the CAN peripheral</description>
92210 <description>Stop the CAN peripheral</description>
92216 <description>Trigger task</description>
92227 …<description>Description collection: Event indicating that interrupt n triggered at CAN core</desc…
92235 <description>Event indicating that interrupt n triggered at CAN core</description>
92241 <description>Event not generated</description>
92246 <description>Event generated</description>
92255 <description>Event indicating that interrupt triggered at CAN DMU</description>
92263 <description>Event indicating that interrupt triggered at CAN DMU</description>
92269 <description>Event not generated</description>
92274 <description>Event generated</description>
92283 <description>Event indicating that interrupt triggered at CAN DMA</description>
92291 <description>Event indicating that interrupt triggered at CAN DMA</description>
92297 <description>Event not generated</description>
92302 <description>Event generated</description>
92311 <description>Event indicating that the CAN is ready to be stopped</description>
92319 <description>Event indicating that the CAN is ready to be stopped</description>
92325 <description>Event not generated</description>
92330 <description>Event generated</description>
92339 <description>Shortcuts between local events and tasks</description>
92347 <description>Shortcut between event READYFORSTOP and task STOP</description>
92353 <description>Disable shortcut</description>
92358 <description>Enable shortcut</description>
92367 <description>Enable or disable interrupt</description>
92375 <description>Enable or disable interrupt for event CORE[0]</description>
92381 <description>Disable</description>
92386 <description>Enable</description>
92393 <description>Enable or disable interrupt for event CORE[1]</description>
92399 <description>Disable</description>
92404 <description>Enable</description>
92411 <description>Enable or disable interrupt for event DMU</description>
92417 <description>Disable</description>
92422 <description>Enable</description>
92429 <description>Enable or disable interrupt for event DMA</description>
92435 <description>Disable</description>
92440 <description>Enable</description>
92447 <description>Enable or disable interrupt for event READYFORSTOP</description>
92453 <description>Disable</description>
92458 <description>Enable</description>
92467 <description>Enable interrupt</description>
92475 <description>Write '1' to enable interrupt for event CORE[0]</description>
92482 <description>Read: Disabled</description>
92487 <description>Read: Enabled</description>
92495 <description>Enable</description>
92502 <description>Write '1' to enable interrupt for event CORE[1]</description>
92509 <description>Read: Disabled</description>
92514 <description>Read: Enabled</description>
92522 <description>Enable</description>
92529 <description>Write '1' to enable interrupt for event DMU</description>
92536 <description>Read: Disabled</description>
92541 <description>Read: Enabled</description>
92549 <description>Enable</description>
92556 <description>Write '1' to enable interrupt for event DMA</description>
92563 <description>Read: Disabled</description>
92568 <description>Read: Enabled</description>
92576 <description>Enable</description>
92583 <description>Write '1' to enable interrupt for event READYFORSTOP</description>
92590 <description>Read: Disabled</description>
92595 <description>Read: Enabled</description>
92603 <description>Enable</description>
92612 <description>Disable interrupt</description>
92620 <description>Write '1' to disable interrupt for event CORE[0]</description>
92627 <description>Read: Disabled</description>
92632 <description>Read: Enabled</description>
92640 <description>Disable</description>
92647 <description>Write '1' to disable interrupt for event CORE[1]</description>
92654 <description>Read: Disabled</description>
92659 <description>Read: Enabled</description>
92667 <description>Disable</description>
92674 <description>Write '1' to disable interrupt for event DMU</description>
92681 <description>Read: Disabled</description>
92686 <description>Read: Enabled</description>
92694 <description>Disable</description>
92701 <description>Write '1' to disable interrupt for event DMA</description>
92708 <description>Read: Disabled</description>
92713 <description>Read: Enabled</description>
92721 <description>Disable</description>
92728 <description>Write '1' to disable interrupt for event READYFORSTOP</description>
92735 <description>Read: Disabled</description>
92740 <description>Read: Enabled</description>
92748 <description>Disable</description>
92757 <description>Pending interrupts</description>
92765 <description>Read pending status of interrupt for event CORE[0]</description>
92772 <description>Read: Not pending</description>
92777 <description>Read: Pending</description>
92784 <description>Read pending status of interrupt for event CORE[1]</description>
92791 <description>Read: Not pending</description>
92796 <description>Read: Pending</description>
92803 <description>Read pending status of interrupt for event DMU</description>
92810 <description>Read: Not pending</description>
92815 <description>Read: Pending</description>
92822 <description>Read pending status of interrupt for event DMA</description>
92829 <description>Read: Not pending</description>
92834 <description>Read: Pending</description>
92841 <description>Read pending status of interrupt for event READYFORSTOP</description>
92848 <description>Read: Not pending</description>
92853 <description>Read: Pending</description>
92864 …description>MVDMA performs direct-memory-accesses between memories. Data is transferred according …
92883 <description>Pause operation.</description>
92891 <description>Pause operation.</description>
92897 <description>Trigger task</description>
92906 <description>Reset operation.</description>
92914 <description>Reset operation.</description>
92920 <description>Trigger task</description>
92931 …<description>Description collection: Start operation of job list n. Base address for successive TA…
92939 …<description>Start operation of job list n. Base address for successive TASKS_STARTs.</description>
92945 <description>Trigger task</description>
92956 … <description>Description collection: Subscribe configuration for task START[n]</description>
92964 <description>DPPI channel that task START[n] will subscribe to</description>
92975 <description>Disable subscription</description>
92980 <description>Enable subscription</description>
92989 … <description>Event indicating that Sink data descriptor list has been completed.</description>
92997 … <description>Event indicating that Sink data descriptor list has been completed.</description>
93003 <description>Event not generated</description>
93008 <description>Event generated</description>
93017 <description>Event indicating that the source list processing has started.</description>
93025 … <description>Event indicating that the source list processing has started.</description>
93031 <description>Event not generated</description>
93036 <description>Event generated</description>
93045 <description>Event indicating that the data transfer has been paused.</description>
93053 <description>Event indicating that the data transfer has been paused.</description>
93059 <description>Event not generated</description>
93064 <description>Event generated</description>
93073 <description>Event indicating that the peripheral has been reset.</description>
93081 <description>Event indicating that the peripheral has been reset.</description>
93087 <description>Event not generated</description>
93092 <description>Event generated</description>
93101 <description>Peripheral events.</description>
93107 …<description>Event indicating that a bus error has been received on the Source channel.</descripti…
93115 …<description>Event indicating that a bus error has been received on the Source channel.</descripti…
93121 <description>Event not generated</description>
93126 <description>Event generated</description>
93135 …<description>Event indicating that a job on the Source channel with EVENT_ENABLE active has been p…
93143 …<description>Event indicating that a job on the Source channel with EVENT_ENABLE active has been p…
93149 <description>Event not generated</description>
93154 <description>Event generated</description>
93164 <description>Peripheral events.</description>
93170 …<description>Event indicating that a bus error has been received on the Sink channel.</description>
93178 …<description>Event indicating that a bus error has been received on the Sink channel.</description>
93184 <description>Event not generated</description>
93189 <description>Event generated</description>
93198 …<description>Event indicating that a job on the Sink channel with EVENT_ENABLE active has been pro…
93206 …<description>Event indicating that a job on the Sink channel with EVENT_ENABLE active has been pro…
93212 <description>Event not generated</description>
93217 <description>Event generated</description>
93229 …description>Description collection: Event indicating that the operation started by the task START[…
93237 …description>Event indicating that the operation started by the task START[n] has been completed. B…
93243 <description>Event not generated</description>
93248 <description>Event generated</description>
93257 <description>Publish configuration for event END</description>
93265 <description>DPPI channel that event END will publish to</description>
93276 <description>Disable publishing</description>
93281 <description>Enable publishing</description>
93290 <description>Publish configuration for events</description>
93296 <description>Publish configuration for event SOURCE.SELECTJOBDONE</description>
93304 … <description>DPPI channel that event SOURCE.SELECTJOBDONE will publish to</description>
93315 <description>Disable publishing</description>
93320 <description>Enable publishing</description>
93330 <description>Publish configuration for events</description>
93336 <description>Publish configuration for event SINK.SELECTJOBDONE</description>
93344 … <description>DPPI channel that event SINK.SELECTJOBDONE will publish to</description>
93355 <description>Disable publishing</description>
93360 <description>Enable publishing</description>
93372 … <description>Description collection: Publish configuration for event COMPLETED[n]</description>
93380 <description>DPPI channel that event COMPLETED[n] will publish to</description>
93391 <description>Disable publishing</description>
93396 <description>Enable publishing</description>
93405 <description>Enable or disable interrupt</description>
93413 <description>Enable or disable interrupt for event END</description>
93419 <description>Disable</description>
93424 <description>Enable</description>
93431 <description>Enable or disable interrupt for event STARTED</description>
93437 <description>Disable</description>
93442 <description>Enable</description>
93449 <description>Enable or disable interrupt for event PAUSED</description>
93455 <description>Disable</description>
93460 <description>Enable</description>
93467 <description>Enable or disable interrupt for event RESET</description>
93473 <description>Disable</description>
93478 <description>Enable</description>
93485 <description>Enable or disable interrupt for event SOURCEBUSERROR</description>
93491 <description>Disable</description>
93496 <description>Enable</description>
93503 <description>Enable or disable interrupt for event SOURCESELECTJOBDONE</description>
93509 <description>Disable</description>
93514 <description>Enable</description>
93521 <description>Enable or disable interrupt for event SINKBUSERROR</description>
93527 <description>Disable</description>
93532 <description>Enable</description>
93539 <description>Enable or disable interrupt for event SINKSELECTJOBDONE</description>
93545 <description>Disable</description>
93550 <description>Enable</description>
93557 <description>Enable or disable interrupt for event COMPLETED[0]</description>
93563 <description>Disable</description>
93568 <description>Enable</description>
93575 <description>Enable or disable interrupt for event COMPLETED[1]</description>
93581 <description>Disable</description>
93586 <description>Enable</description>
93593 <description>Enable or disable interrupt for event COMPLETED[2]</description>
93599 <description>Disable</description>
93604 <description>Enable</description>
93611 <description>Enable or disable interrupt for event COMPLETED[3]</description>
93617 <description>Disable</description>
93622 <description>Enable</description>
93629 <description>Enable or disable interrupt for event COMPLETED[4]</description>
93635 <description>Disable</description>
93640 <description>Enable</description>
93647 <description>Enable or disable interrupt for event COMPLETED[5]</description>
93653 <description>Disable</description>
93658 <description>Enable</description>
93665 <description>Enable or disable interrupt for event COMPLETED[6]</description>
93671 <description>Disable</description>
93676 <description>Enable</description>
93683 <description>Enable or disable interrupt for event COMPLETED[7]</description>
93689 <description>Disable</description>
93694 <description>Enable</description>
93703 <description>Enable interrupt</description>
93711 <description>Write '1' to enable interrupt for event END</description>
93718 <description>Read: Disabled</description>
93723 <description>Read: Enabled</description>
93731 <description>Enable</description>
93738 <description>Write '1' to enable interrupt for event STARTED</description>
93745 <description>Read: Disabled</description>
93750 <description>Read: Enabled</description>
93758 <description>Enable</description>
93765 <description>Write '1' to enable interrupt for event PAUSED</description>
93772 <description>Read: Disabled</description>
93777 <description>Read: Enabled</description>
93785 <description>Enable</description>
93792 <description>Write '1' to enable interrupt for event RESET</description>
93799 <description>Read: Disabled</description>
93804 <description>Read: Enabled</description>
93812 <description>Enable</description>
93819 <description>Write '1' to enable interrupt for event SOURCEBUSERROR</description>
93826 <description>Read: Disabled</description>
93831 <description>Read: Enabled</description>
93839 <description>Enable</description>
93846 <description>Write '1' to enable interrupt for event SOURCESELECTJOBDONE</description>
93853 <description>Read: Disabled</description>
93858 <description>Read: Enabled</description>
93866 <description>Enable</description>
93873 <description>Write '1' to enable interrupt for event SINKBUSERROR</description>
93880 <description>Read: Disabled</description>
93885 <description>Read: Enabled</description>
93893 <description>Enable</description>
93900 <description>Write '1' to enable interrupt for event SINKSELECTJOBDONE</description>
93907 <description>Read: Disabled</description>
93912 <description>Read: Enabled</description>
93920 <description>Enable</description>
93927 <description>Write '1' to enable interrupt for event COMPLETED[0]</description>
93934 <description>Read: Disabled</description>
93939 <description>Read: Enabled</description>
93947 <description>Enable</description>
93954 <description>Write '1' to enable interrupt for event COMPLETED[1]</description>
93961 <description>Read: Disabled</description>
93966 <description>Read: Enabled</description>
93974 <description>Enable</description>
93981 <description>Write '1' to enable interrupt for event COMPLETED[2]</description>
93988 <description>Read: Disabled</description>
93993 <description>Read: Enabled</description>
94001 <description>Enable</description>
94008 <description>Write '1' to enable interrupt for event COMPLETED[3]</description>
94015 <description>Read: Disabled</description>
94020 <description>Read: Enabled</description>
94028 <description>Enable</description>
94035 <description>Write '1' to enable interrupt for event COMPLETED[4]</description>
94042 <description>Read: Disabled</description>
94047 <description>Read: Enabled</description>
94055 <description>Enable</description>
94062 <description>Write '1' to enable interrupt for event COMPLETED[5]</description>
94069 <description>Read: Disabled</description>
94074 <description>Read: Enabled</description>
94082 <description>Enable</description>
94089 <description>Write '1' to enable interrupt for event COMPLETED[6]</description>
94096 <description>Read: Disabled</description>
94101 <description>Read: Enabled</description>
94109 <description>Enable</description>
94116 <description>Write '1' to enable interrupt for event COMPLETED[7]</description>
94123 <description>Read: Disabled</description>
94128 <description>Read: Enabled</description>
94136 <description>Enable</description>
94145 <description>Disable interrupt</description>
94153 <description>Write '1' to disable interrupt for event END</description>
94160 <description>Read: Disabled</description>
94165 <description>Read: Enabled</description>
94173 <description>Disable</description>
94180 <description>Write '1' to disable interrupt for event STARTED</description>
94187 <description>Read: Disabled</description>
94192 <description>Read: Enabled</description>
94200 <description>Disable</description>
94207 <description>Write '1' to disable interrupt for event PAUSED</description>
94214 <description>Read: Disabled</description>
94219 <description>Read: Enabled</description>
94227 <description>Disable</description>
94234 <description>Write '1' to disable interrupt for event RESET</description>
94241 <description>Read: Disabled</description>
94246 <description>Read: Enabled</description>
94254 <description>Disable</description>
94261 <description>Write '1' to disable interrupt for event SOURCEBUSERROR</description>
94268 <description>Read: Disabled</description>
94273 <description>Read: Enabled</description>
94281 <description>Disable</description>
94288 … <description>Write '1' to disable interrupt for event SOURCESELECTJOBDONE</description>
94295 <description>Read: Disabled</description>
94300 <description>Read: Enabled</description>
94308 <description>Disable</description>
94315 <description>Write '1' to disable interrupt for event SINKBUSERROR</description>
94322 <description>Read: Disabled</description>
94327 <description>Read: Enabled</description>
94335 <description>Disable</description>
94342 <description>Write '1' to disable interrupt for event SINKSELECTJOBDONE</description>
94349 <description>Read: Disabled</description>
94354 <description>Read: Enabled</description>
94362 <description>Disable</description>
94369 <description>Write '1' to disable interrupt for event COMPLETED[0]</description>
94376 <description>Read: Disabled</description>
94381 <description>Read: Enabled</description>
94389 <description>Disable</description>
94396 <description>Write '1' to disable interrupt for event COMPLETED[1]</description>
94403 <description>Read: Disabled</description>
94408 <description>Read: Enabled</description>
94416 <description>Disable</description>
94423 <description>Write '1' to disable interrupt for event COMPLETED[2]</description>
94430 <description>Read: Disabled</description>
94435 <description>Read: Enabled</description>
94443 <description>Disable</description>
94450 <description>Write '1' to disable interrupt for event COMPLETED[3]</description>
94457 <description>Read: Disabled</description>
94462 <description>Read: Enabled</description>
94470 <description>Disable</description>
94477 <description>Write '1' to disable interrupt for event COMPLETED[4]</description>
94484 <description>Read: Disabled</description>
94489 <description>Read: Enabled</description>
94497 <description>Disable</description>
94504 <description>Write '1' to disable interrupt for event COMPLETED[5]</description>
94511 <description>Read: Disabled</description>
94516 <description>Read: Enabled</description>
94524 <description>Disable</description>
94531 <description>Write '1' to disable interrupt for event COMPLETED[6]</description>
94538 <description>Read: Disabled</description>
94543 <description>Read: Enabled</description>
94551 <description>Disable</description>
94558 <description>Write '1' to disable interrupt for event COMPLETED[7]</description>
94565 <description>Read: Disabled</description>
94570 <description>Read: Enabled</description>
94578 <description>Disable</description>
94587 <description>Pending interrupts</description>
94595 <description>Read pending status of interrupt for event END</description>
94602 <description>Read: Not pending</description>
94607 <description>Read: Pending</description>
94614 <description>Read pending status of interrupt for event STARTED</description>
94621 <description>Read: Not pending</description>
94626 <description>Read: Pending</description>
94633 <description>Read pending status of interrupt for event PAUSED</description>
94640 <description>Read: Not pending</description>
94645 <description>Read: Pending</description>
94652 <description>Read pending status of interrupt for event RESET</description>
94659 <description>Read: Not pending</description>
94664 <description>Read: Pending</description>
94671 <description>Read pending status of interrupt for event SOURCEBUSERROR</description>
94678 <description>Read: Not pending</description>
94683 <description>Read: Pending</description>
94690 … <description>Read pending status of interrupt for event SOURCESELECTJOBDONE</description>
94697 <description>Read: Not pending</description>
94702 <description>Read: Pending</description>
94709 <description>Read pending status of interrupt for event SINKBUSERROR</description>
94716 <description>Read: Not pending</description>
94721 <description>Read: Pending</description>
94728 … <description>Read pending status of interrupt for event SINKSELECTJOBDONE</description>
94735 <description>Read: Not pending</description>
94740 <description>Read: Pending</description>
94747 <description>Read pending status of interrupt for event COMPLETED[0]</description>
94754 <description>Read: Not pending</description>
94759 <description>Read: Pending</description>
94766 <description>Read pending status of interrupt for event COMPLETED[1]</description>
94773 <description>Read: Not pending</description>
94778 <description>Read: Pending</description>
94785 <description>Read pending status of interrupt for event COMPLETED[2]</description>
94792 <description>Read: Not pending</description>
94797 <description>Read: Pending</description>
94804 <description>Read pending status of interrupt for event COMPLETED[3]</description>
94811 <description>Read: Not pending</description>
94816 <description>Read: Pending</description>
94823 <description>Read pending status of interrupt for event COMPLETED[4]</description>
94830 <description>Read: Not pending</description>
94835 <description>Read: Pending</description>
94842 <description>Read pending status of interrupt for event COMPLETED[5]</description>
94849 <description>Read: Not pending</description>
94854 <description>Read: Pending</description>
94861 <description>Read pending status of interrupt for event COMPLETED[6]</description>
94868 <description>Read: Not pending</description>
94873 <description>Read: Pending</description>
94880 <description>Read pending status of interrupt for event COMPLETED[7]</description>
94887 <description>Read: Not pending</description>
94892 <description>Read: Pending</description>
94901 <description>MVDMA status registers.</description>
94907 <description>CRC checksum calculation result</description>
94915 <description>Result</description>
94923 …<description>Status of intermediate fifo: empty, not empty and full information available.</descri…
94931 <description>Result</description>
94937 <description>Fifo is empty.</description>
94942 <description>Fifo contains data.</description>
94947 <description>Fifo is full.</description>
94956 <description>Status of DMA transfer.</description>
94964 <description>DMA activity</description>
94970 <description>DMA is in IDLE state.</description>
94975 <description>Data being transferred.</description>
94985 <description>MVDMA configuration registers.</description>
94991 <description>Configure MVDMA mode of operation.</description>
95004 …<description>Registers SOURCE.LISTPTR and SINK.LISTPTR contain start address of a single job list.…
95009 …<description>Registers SOURCE.LISTPTR and SINK.LISTPTR contain start address of a list of job list…
95019 <description>Source channel configuration and status.</description>
95025 …<description>Start address of Source job list or list of job list pointers, depending on value of …
95033 <description>Source job descriptor list address.</description>
95041 <description>Source bus error status.</description>
95049 <description>Bus error type</description>
95055 <description>There are no errors.</description>
95060 …<description>Error related to memory when reading joblist, or error related to memory/register whe…
95065 …<description>Error related to the joblist address when reading joblist, or error related to addres…
95074 …description>Latest address being accessed on the Source channel.If a bus error occurs, these regis…
95082 <description>Source address</description>
95090 …<description>Number of completed jobs in the current Source descriptor list. This resets to 0 when…
95098 <description>Source job count</description>
95107 <description>Sink channel configuration and status.</description>
95113 …<description>Start address of Sink job list or list of job list pointers, depending on value of CO…
95121 <description>Sink descriptor list address.</description>
95129 <description>Sink bus error status.</description>
95137 <description>Bus error type</description>
95143 <description>There are no errors.</description>
95148 <description>Error related to memory when reading joblist.</description>
95153 … <description>Error related to the joblist address when reading joblist.</description>
95158 <description>Error related to memory/register when writing data.</description>
95163 … <description>Error related to the memory/register address when writing data.</description>
95172 …description>Latest address being accessed on the Sink channel. If a bus error occurs, these regist…
95180 <description>Sink address</description>
95188 …<description>Number of completed jobs in the current Sink descriptor list. This resets to 0 when a…
95196 <description>Sink job count</description>
95207 <description>RAM Controller 0</description>
95222 <description>Waitstates for read operations.</description>
95230 <description>Number of waitstates for a read from the RAM.</description>
95240 <description>Controller Area Network 1</description>
95251 …description>MVDMA performs direct-memory-accesses between memories. Data is transferred according …
95262 <description>RAM Controller 1</description>
95269 <description>I3C 1</description>
95280 <description>Distributed programmable peripheral interconnect controller 0</description>
95298 <description>Channel group tasks</description>
95304 <description>Description cluster: Enable channel group n</description>
95312 <description>Enable channel group n</description>
95318 <description>Trigger task</description>
95327 <description>Description cluster: Disable channel group n</description>
95335 <description>Disable channel group n</description>
95341 <description>Trigger task</description>
95353 <description>Subscribe configuration for tasks</description>
95359 … <description>Description cluster: Subscribe configuration for task CHG[n].EN</description>
95367 <description>DPPI channel that task CHG[n].EN will subscribe to</description>
95378 <description>Disable subscription</description>
95383 <description>Enable subscription</description>
95392 … <description>Description cluster: Subscribe configuration for task CHG[n].DIS</description>
95400 <description>DPPI channel that task CHG[n].DIS will subscribe to</description>
95411 <description>Disable subscription</description>
95416 <description>Enable subscription</description>
95426 <description>Channel enable register</description>
95434 <description>Enable or disable channel 0</description>
95440 <description>Disable channel</description>
95445 <description>Enable channel</description>
95452 <description>Enable or disable channel 1</description>
95458 <description>Disable channel</description>
95463 <description>Enable channel</description>
95470 <description>Enable or disable channel 2</description>
95476 <description>Disable channel</description>
95481 <description>Enable channel</description>
95488 <description>Enable or disable channel 3</description>
95494 <description>Disable channel</description>
95499 <description>Enable channel</description>
95506 <description>Enable or disable channel 4</description>
95512 <description>Disable channel</description>
95517 <description>Enable channel</description>
95524 <description>Enable or disable channel 5</description>
95530 <description>Disable channel</description>
95535 <description>Enable channel</description>
95542 <description>Enable or disable channel 6</description>
95548 <description>Disable channel</description>
95553 <description>Enable channel</description>
95560 <description>Enable or disable channel 7</description>
95566 <description>Disable channel</description>
95571 <description>Enable channel</description>
95578 <description>Enable or disable channel 8</description>
95584 <description>Disable channel</description>
95589 <description>Enable channel</description>
95596 <description>Enable or disable channel 9</description>
95602 <description>Disable channel</description>
95607 <description>Enable channel</description>
95614 <description>Enable or disable channel 10</description>
95620 <description>Disable channel</description>
95625 <description>Enable channel</description>
95632 <description>Enable or disable channel 11</description>
95638 <description>Disable channel</description>
95643 <description>Enable channel</description>
95650 <description>Enable or disable channel 12</description>
95656 <description>Disable channel</description>
95661 <description>Enable channel</description>
95668 <description>Enable or disable channel 13</description>
95674 <description>Disable channel</description>
95679 <description>Enable channel</description>
95686 <description>Enable or disable channel 14</description>
95692 <description>Disable channel</description>
95697 <description>Enable channel</description>
95704 <description>Enable or disable channel 15</description>
95710 <description>Disable channel</description>
95715 <description>Enable channel</description>
95722 <description>Enable or disable channel 16</description>
95728 <description>Disable channel</description>
95733 <description>Enable channel</description>
95740 <description>Enable or disable channel 17</description>
95746 <description>Disable channel</description>
95751 <description>Enable channel</description>
95758 <description>Enable or disable channel 18</description>
95764 <description>Disable channel</description>
95769 <description>Enable channel</description>
95776 <description>Enable or disable channel 19</description>
95782 <description>Disable channel</description>
95787 <description>Enable channel</description>
95794 <description>Enable or disable channel 20</description>
95800 <description>Disable channel</description>
95805 <description>Enable channel</description>
95812 <description>Enable or disable channel 21</description>
95818 <description>Disable channel</description>
95823 <description>Enable channel</description>
95830 <description>Enable or disable channel 22</description>
95836 <description>Disable channel</description>
95841 <description>Enable channel</description>
95848 <description>Enable or disable channel 23</description>
95854 <description>Disable channel</description>
95859 <description>Enable channel</description>
95868 <description>Channel enable set register</description>
95877 <description>Channel 0 enable set register. Writing 0 has no effect.</description>
95884 <description>Read: Channel disabled</description>
95889 <description>Read: Channel enabled</description>
95897 <description>Write: Enable channel</description>
95904 <description>Channel 1 enable set register. Writing 0 has no effect.</description>
95911 <description>Read: Channel disabled</description>
95916 <description>Read: Channel enabled</description>
95924 <description>Write: Enable channel</description>
95931 <description>Channel 2 enable set register. Writing 0 has no effect.</description>
95938 <description>Read: Channel disabled</description>
95943 <description>Read: Channel enabled</description>
95951 <description>Write: Enable channel</description>
95958 <description>Channel 3 enable set register. Writing 0 has no effect.</description>
95965 <description>Read: Channel disabled</description>
95970 <description>Read: Channel enabled</description>
95978 <description>Write: Enable channel</description>
95985 <description>Channel 4 enable set register. Writing 0 has no effect.</description>
95992 <description>Read: Channel disabled</description>
95997 <description>Read: Channel enabled</description>
96005 <description>Write: Enable channel</description>
96012 <description>Channel 5 enable set register. Writing 0 has no effect.</description>
96019 <description>Read: Channel disabled</description>
96024 <description>Read: Channel enabled</description>
96032 <description>Write: Enable channel</description>
96039 <description>Channel 6 enable set register. Writing 0 has no effect.</description>
96046 <description>Read: Channel disabled</description>
96051 <description>Read: Channel enabled</description>
96059 <description>Write: Enable channel</description>
96066 <description>Channel 7 enable set register. Writing 0 has no effect.</description>
96073 <description>Read: Channel disabled</description>
96078 <description>Read: Channel enabled</description>
96086 <description>Write: Enable channel</description>
96093 <description>Channel 8 enable set register. Writing 0 has no effect.</description>
96100 <description>Read: Channel disabled</description>
96105 <description>Read: Channel enabled</description>
96113 <description>Write: Enable channel</description>
96120 <description>Channel 9 enable set register. Writing 0 has no effect.</description>
96127 <description>Read: Channel disabled</description>
96132 <description>Read: Channel enabled</description>
96140 <description>Write: Enable channel</description>
96147 <description>Channel 10 enable set register. Writing 0 has no effect.</description>
96154 <description>Read: Channel disabled</description>
96159 <description>Read: Channel enabled</description>
96167 <description>Write: Enable channel</description>
96174 <description>Channel 11 enable set register. Writing 0 has no effect.</description>
96181 <description>Read: Channel disabled</description>
96186 <description>Read: Channel enabled</description>
96194 <description>Write: Enable channel</description>
96201 <description>Channel 12 enable set register. Writing 0 has no effect.</description>
96208 <description>Read: Channel disabled</description>
96213 <description>Read: Channel enabled</description>
96221 <description>Write: Enable channel</description>
96228 <description>Channel 13 enable set register. Writing 0 has no effect.</description>
96235 <description>Read: Channel disabled</description>
96240 <description>Read: Channel enabled</description>
96248 <description>Write: Enable channel</description>
96255 <description>Channel 14 enable set register. Writing 0 has no effect.</description>
96262 <description>Read: Channel disabled</description>
96267 <description>Read: Channel enabled</description>
96275 <description>Write: Enable channel</description>
96282 <description>Channel 15 enable set register. Writing 0 has no effect.</description>
96289 <description>Read: Channel disabled</description>
96294 <description>Read: Channel enabled</description>
96302 <description>Write: Enable channel</description>
96309 <description>Channel 16 enable set register. Writing 0 has no effect.</description>
96316 <description>Read: Channel disabled</description>
96321 <description>Read: Channel enabled</description>
96329 <description>Write: Enable channel</description>
96336 <description>Channel 17 enable set register. Writing 0 has no effect.</description>
96343 <description>Read: Channel disabled</description>
96348 <description>Read: Channel enabled</description>
96356 <description>Write: Enable channel</description>
96363 <description>Channel 18 enable set register. Writing 0 has no effect.</description>
96370 <description>Read: Channel disabled</description>
96375 <description>Read: Channel enabled</description>
96383 <description>Write: Enable channel</description>
96390 <description>Channel 19 enable set register. Writing 0 has no effect.</description>
96397 <description>Read: Channel disabled</description>
96402 <description>Read: Channel enabled</description>
96410 <description>Write: Enable channel</description>
96417 <description>Channel 20 enable set register. Writing 0 has no effect.</description>
96424 <description>Read: Channel disabled</description>
96429 <description>Read: Channel enabled</description>
96437 <description>Write: Enable channel</description>
96444 <description>Channel 21 enable set register. Writing 0 has no effect.</description>
96451 <description>Read: Channel disabled</description>
96456 <description>Read: Channel enabled</description>
96464 <description>Write: Enable channel</description>
96471 <description>Channel 22 enable set register. Writing 0 has no effect.</description>
96478 <description>Read: Channel disabled</description>
96483 <description>Read: Channel enabled</description>
96491 <description>Write: Enable channel</description>
96498 <description>Channel 23 enable set register. Writing 0 has no effect.</description>
96505 <description>Read: Channel disabled</description>
96510 <description>Read: Channel enabled</description>
96518 <description>Write: Enable channel</description>
96527 <description>Channel enable clear register</description>
96536 <description>Channel 0 enable clear register. Writing 0 has no effect.</description>
96543 <description>Read: Channel disabled</description>
96548 <description>Read: Channel enabled</description>
96556 <description>Write: Disable channel</description>
96563 <description>Channel 1 enable clear register. Writing 0 has no effect.</description>
96570 <description>Read: Channel disabled</description>
96575 <description>Read: Channel enabled</description>
96583 <description>Write: Disable channel</description>
96590 <description>Channel 2 enable clear register. Writing 0 has no effect.</description>
96597 <description>Read: Channel disabled</description>
96602 <description>Read: Channel enabled</description>
96610 <description>Write: Disable channel</description>
96617 <description>Channel 3 enable clear register. Writing 0 has no effect.</description>
96624 <description>Read: Channel disabled</description>
96629 <description>Read: Channel enabled</description>
96637 <description>Write: Disable channel</description>
96644 <description>Channel 4 enable clear register. Writing 0 has no effect.</description>
96651 <description>Read: Channel disabled</description>
96656 <description>Read: Channel enabled</description>
96664 <description>Write: Disable channel</description>
96671 <description>Channel 5 enable clear register. Writing 0 has no effect.</description>
96678 <description>Read: Channel disabled</description>
96683 <description>Read: Channel enabled</description>
96691 <description>Write: Disable channel</description>
96698 <description>Channel 6 enable clear register. Writing 0 has no effect.</description>
96705 <description>Read: Channel disabled</description>
96710 <description>Read: Channel enabled</description>
96718 <description>Write: Disable channel</description>
96725 <description>Channel 7 enable clear register. Writing 0 has no effect.</description>
96732 <description>Read: Channel disabled</description>
96737 <description>Read: Channel enabled</description>
96745 <description>Write: Disable channel</description>
96752 <description>Channel 8 enable clear register. Writing 0 has no effect.</description>
96759 <description>Read: Channel disabled</description>
96764 <description>Read: Channel enabled</description>
96772 <description>Write: Disable channel</description>
96779 <description>Channel 9 enable clear register. Writing 0 has no effect.</description>
96786 <description>Read: Channel disabled</description>
96791 <description>Read: Channel enabled</description>
96799 <description>Write: Disable channel</description>
96806 <description>Channel 10 enable clear register. Writing 0 has no effect.</description>
96813 <description>Read: Channel disabled</description>
96818 <description>Read: Channel enabled</description>
96826 <description>Write: Disable channel</description>
96833 <description>Channel 11 enable clear register. Writing 0 has no effect.</description>
96840 <description>Read: Channel disabled</description>
96845 <description>Read: Channel enabled</description>
96853 <description>Write: Disable channel</description>
96860 <description>Channel 12 enable clear register. Writing 0 has no effect.</description>
96867 <description>Read: Channel disabled</description>
96872 <description>Read: Channel enabled</description>
96880 <description>Write: Disable channel</description>
96887 <description>Channel 13 enable clear register. Writing 0 has no effect.</description>
96894 <description>Read: Channel disabled</description>
96899 <description>Read: Channel enabled</description>
96907 <description>Write: Disable channel</description>
96914 <description>Channel 14 enable clear register. Writing 0 has no effect.</description>
96921 <description>Read: Channel disabled</description>
96926 <description>Read: Channel enabled</description>
96934 <description>Write: Disable channel</description>
96941 <description>Channel 15 enable clear register. Writing 0 has no effect.</description>
96948 <description>Read: Channel disabled</description>
96953 <description>Read: Channel enabled</description>
96961 <description>Write: Disable channel</description>
96968 <description>Channel 16 enable clear register. Writing 0 has no effect.</description>
96975 <description>Read: Channel disabled</description>
96980 <description>Read: Channel enabled</description>
96988 <description>Write: Disable channel</description>
96995 <description>Channel 17 enable clear register. Writing 0 has no effect.</description>
97002 <description>Read: Channel disabled</description>
97007 <description>Read: Channel enabled</description>
97015 <description>Write: Disable channel</description>
97022 <description>Channel 18 enable clear register. Writing 0 has no effect.</description>
97029 <description>Read: Channel disabled</description>
97034 <description>Read: Channel enabled</description>
97042 <description>Write: Disable channel</description>
97049 <description>Channel 19 enable clear register. Writing 0 has no effect.</description>
97056 <description>Read: Channel disabled</description>
97061 <description>Read: Channel enabled</description>
97069 <description>Write: Disable channel</description>
97076 <description>Channel 20 enable clear register. Writing 0 has no effect.</description>
97083 <description>Read: Channel disabled</description>
97088 <description>Read: Channel enabled</description>
97096 <description>Write: Disable channel</description>
97103 <description>Channel 21 enable clear register. Writing 0 has no effect.</description>
97110 <description>Read: Channel disabled</description>
97115 <description>Read: Channel enabled</description>
97123 <description>Write: Disable channel</description>
97130 <description>Channel 22 enable clear register. Writing 0 has no effect.</description>
97137 <description>Read: Channel disabled</description>
97142 <description>Read: Channel enabled</description>
97150 <description>Write: Disable channel</description>
97157 <description>Channel 23 enable clear register. Writing 0 has no effect.</description>
97164 <description>Read: Channel disabled</description>
97169 <description>Read: Channel enabled</description>
97177 <description>Write: Disable channel</description>
97188 …description>Description collection: Channel group n Note: Writes to this register are ignored if e…
97196 <description>Include or exclude channel 0</description>
97202 <description>Exclude</description>
97207 <description>Include</description>
97214 <description>Include or exclude channel 1</description>
97220 <description>Exclude</description>
97225 <description>Include</description>
97232 <description>Include or exclude channel 2</description>
97238 <description>Exclude</description>
97243 <description>Include</description>
97250 <description>Include or exclude channel 3</description>
97256 <description>Exclude</description>
97261 <description>Include</description>
97268 <description>Include or exclude channel 4</description>
97274 <description>Exclude</description>
97279 <description>Include</description>
97286 <description>Include or exclude channel 5</description>
97292 <description>Exclude</description>
97297 <description>Include</description>
97304 <description>Include or exclude channel 6</description>
97310 <description>Exclude</description>
97315 <description>Include</description>
97322 <description>Include or exclude channel 7</description>
97328 <description>Exclude</description>
97333 <description>Include</description>
97340 <description>Include or exclude channel 8</description>
97346 <description>Exclude</description>
97351 <description>Include</description>
97358 <description>Include or exclude channel 9</description>
97364 <description>Exclude</description>
97369 <description>Include</description>
97376 <description>Include or exclude channel 10</description>
97382 <description>Exclude</description>
97387 <description>Include</description>
97394 <description>Include or exclude channel 11</description>
97400 <description>Exclude</description>
97405 <description>Include</description>
97412 <description>Include or exclude channel 12</description>
97418 <description>Exclude</description>
97423 <description>Include</description>
97430 <description>Include or exclude channel 13</description>
97436 <description>Exclude</description>
97441 <description>Include</description>
97448 <description>Include or exclude channel 14</description>
97454 <description>Exclude</description>
97459 <description>Include</description>
97466 <description>Include or exclude channel 15</description>
97472 <description>Exclude</description>
97477 <description>Include</description>
97484 <description>Include or exclude channel 16</description>
97490 <description>Exclude</description>
97495 <description>Include</description>
97502 <description>Include or exclude channel 17</description>
97508 <description>Exclude</description>
97513 <description>Include</description>
97520 <description>Include or exclude channel 18</description>
97526 <description>Exclude</description>
97531 <description>Include</description>
97538 <description>Include or exclude channel 19</description>
97544 <description>Exclude</description>
97549 <description>Include</description>
97556 <description>Include or exclude channel 20</description>
97562 <description>Exclude</description>
97567 <description>Include</description>
97574 <description>Include or exclude channel 21</description>
97580 <description>Exclude</description>
97585 <description>Include</description>
97592 <description>Include or exclude channel 22</description>
97598 <description>Exclude</description>
97603 <description>Include</description>
97610 <description>Include or exclude channel 23</description>
97616 <description>Exclude</description>
97621 <description>Include</description>
97632 <description>Timer/Counter 0</description>
97651 <description>Start Timer</description>
97659 <description>Start Timer</description>
97665 <description>Trigger task</description>
97674 <description>Stop Timer</description>
97682 <description>Stop Timer</description>
97688 <description>Trigger task</description>
97697 <description>Increment Timer (Counter mode only)</description>
97705 <description>Increment Timer (Counter mode only)</description>
97711 <description>Trigger task</description>
97720 <description>Clear time</description>
97728 <description>Clear time</description>
97734 <description>Trigger task</description>
97743 <description>Deprecated register - Shut down timer</description>
97751 <description>Deprecated field - Shut down timer</description>
97757 <description>Trigger task</description>
97768 <description>Description collection: Capture Timer value to CC[n] register</description>
97776 <description>Capture Timer value to CC[n] register</description>
97782 <description>Trigger task</description>
97791 <description>Subscribe configuration for task START</description>
97799 <description>DPPI channel that task START will subscribe to</description>
97810 <description>Disable subscription</description>
97815 <description>Enable subscription</description>
97824 <description>Subscribe configuration for task STOP</description>
97832 <description>DPPI channel that task STOP will subscribe to</description>
97843 <description>Disable subscription</description>
97848 <description>Enable subscription</description>
97857 <description>Subscribe configuration for task COUNT</description>
97865 <description>DPPI channel that task COUNT will subscribe to</description>
97876 <description>Disable subscription</description>
97881 <description>Enable subscription</description>
97890 <description>Subscribe configuration for task CLEAR</description>
97898 <description>DPPI channel that task CLEAR will subscribe to</description>
97909 <description>Disable subscription</description>
97914 <description>Enable subscription</description>
97923 <description>Deprecated register - Subscribe configuration for task SHUTDOWN</description>
97931 <description>DPPI channel that task SHUTDOWN will subscribe to</description>
97942 <description>Disable subscription</description>
97947 <description>Enable subscription</description>
97958 … <description>Description collection: Subscribe configuration for task CAPTURE[n]</description>
97966 <description>DPPI channel that task CAPTURE[n] will subscribe to</description>
97977 <description>Disable subscription</description>
97982 <description>Enable subscription</description>
97993 <description>Description collection: Compare event on CC[n] match</description>
98001 <description>Compare event on CC[n] match</description>
98007 <description>Event not generated</description>
98012 <description>Event generated</description>
98023 … <description>Description collection: Publish configuration for event COMPARE[n]</description>
98031 <description>DPPI channel that event COMPARE[n] will publish to</description>
98042 <description>Disable publishing</description>
98047 <description>Enable publishing</description>
98056 <description>Shortcuts between local events and tasks</description>
98064 <description>Shortcut between event COMPARE[0] and task CLEAR</description>
98070 <description>Disable shortcut</description>
98075 <description>Enable shortcut</description>
98082 <description>Shortcut between event COMPARE[1] and task CLEAR</description>
98088 <description>Disable shortcut</description>
98093 <description>Enable shortcut</description>
98100 <description>Shortcut between event COMPARE[2] and task CLEAR</description>
98106 <description>Disable shortcut</description>
98111 <description>Enable shortcut</description>
98118 <description>Shortcut between event COMPARE[3] and task CLEAR</description>
98124 <description>Disable shortcut</description>
98129 <description>Enable shortcut</description>
98136 <description>Shortcut between event COMPARE[4] and task CLEAR</description>
98142 <description>Disable shortcut</description>
98147 <description>Enable shortcut</description>
98154 <description>Shortcut between event COMPARE[5] and task CLEAR</description>
98160 <description>Disable shortcut</description>
98165 <description>Enable shortcut</description>
98172 <description>Shortcut between event COMPARE[6] and task CLEAR</description>
98178 <description>Disable shortcut</description>
98183 <description>Enable shortcut</description>
98190 <description>Shortcut between event COMPARE[7] and task CLEAR</description>
98196 <description>Disable shortcut</description>
98201 <description>Enable shortcut</description>
98208 <description>Shortcut between event COMPARE[0] and task STOP</description>
98214 <description>Disable shortcut</description>
98219 <description>Enable shortcut</description>
98226 <description>Shortcut between event COMPARE[1] and task STOP</description>
98232 <description>Disable shortcut</description>
98237 <description>Enable shortcut</description>
98244 <description>Shortcut between event COMPARE[2] and task STOP</description>
98250 <description>Disable shortcut</description>
98255 <description>Enable shortcut</description>
98262 <description>Shortcut between event COMPARE[3] and task STOP</description>
98268 <description>Disable shortcut</description>
98273 <description>Enable shortcut</description>
98280 <description>Shortcut between event COMPARE[4] and task STOP</description>
98286 <description>Disable shortcut</description>
98291 <description>Enable shortcut</description>
98298 <description>Shortcut between event COMPARE[5] and task STOP</description>
98304 <description>Disable shortcut</description>
98309 <description>Enable shortcut</description>
98316 <description>Shortcut between event COMPARE[6] and task STOP</description>
98322 <description>Disable shortcut</description>
98327 <description>Enable shortcut</description>
98334 <description>Shortcut between event COMPARE[7] and task STOP</description>
98340 <description>Disable shortcut</description>
98345 <description>Enable shortcut</description>
98354 <description>Enable or disable interrupt</description>
98362 <description>Enable or disable interrupt for event COMPARE[0]</description>
98368 <description>Disable</description>
98373 <description>Enable</description>
98380 <description>Enable or disable interrupt for event COMPARE[1]</description>
98386 <description>Disable</description>
98391 <description>Enable</description>
98398 <description>Enable or disable interrupt for event COMPARE[2]</description>
98404 <description>Disable</description>
98409 <description>Enable</description>
98416 <description>Enable or disable interrupt for event COMPARE[3]</description>
98422 <description>Disable</description>
98427 <description>Enable</description>
98434 <description>Enable or disable interrupt for event COMPARE[4]</description>
98440 <description>Disable</description>
98445 <description>Enable</description>
98452 <description>Enable or disable interrupt for event COMPARE[5]</description>
98458 <description>Disable</description>
98463 <description>Enable</description>
98470 <description>Enable or disable interrupt for event COMPARE[6]</description>
98476 <description>Disable</description>
98481 <description>Enable</description>
98488 <description>Enable or disable interrupt for event COMPARE[7]</description>
98494 <description>Disable</description>
98499 <description>Enable</description>
98508 <description>Enable interrupt</description>
98516 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
98523 <description>Read: Disabled</description>
98528 <description>Read: Enabled</description>
98536 <description>Enable</description>
98543 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
98550 <description>Read: Disabled</description>
98555 <description>Read: Enabled</description>
98563 <description>Enable</description>
98570 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
98577 <description>Read: Disabled</description>
98582 <description>Read: Enabled</description>
98590 <description>Enable</description>
98597 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
98604 <description>Read: Disabled</description>
98609 <description>Read: Enabled</description>
98617 <description>Enable</description>
98624 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
98631 <description>Read: Disabled</description>
98636 <description>Read: Enabled</description>
98644 <description>Enable</description>
98651 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
98658 <description>Read: Disabled</description>
98663 <description>Read: Enabled</description>
98671 <description>Enable</description>
98678 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
98685 <description>Read: Disabled</description>
98690 <description>Read: Enabled</description>
98698 <description>Enable</description>
98705 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
98712 <description>Read: Disabled</description>
98717 <description>Read: Enabled</description>
98725 <description>Enable</description>
98734 <description>Disable interrupt</description>
98742 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
98749 <description>Read: Disabled</description>
98754 <description>Read: Enabled</description>
98762 <description>Disable</description>
98769 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
98776 <description>Read: Disabled</description>
98781 <description>Read: Enabled</description>
98789 <description>Disable</description>
98796 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
98803 <description>Read: Disabled</description>
98808 <description>Read: Enabled</description>
98816 <description>Disable</description>
98823 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
98830 <description>Read: Disabled</description>
98835 <description>Read: Enabled</description>
98843 <description>Disable</description>
98850 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
98857 <description>Read: Disabled</description>
98862 <description>Read: Enabled</description>
98870 <description>Disable</description>
98877 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
98884 <description>Read: Disabled</description>
98889 <description>Read: Enabled</description>
98897 <description>Disable</description>
98904 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
98911 <description>Read: Disabled</description>
98916 <description>Read: Enabled</description>
98924 <description>Disable</description>
98931 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
98938 <description>Read: Disabled</description>
98943 <description>Read: Enabled</description>
98951 <description>Disable</description>
98960 <description>Timer mode selection</description>
98968 <description>Timer mode</description>
98974 <description>Select Timer mode</description>
98979 <description>Deprecated enumerator - Select Counter mode</description>
98984 <description>Select Low Power Counter mode</description>
98993 <description>Configure the number of bits used by the TIMER</description>
99001 <description>Timer bit width</description>
99007 <description>16 bit timer bit width</description>
99012 <description>8 bit timer bit width</description>
99017 <description>24 bit timer bit width</description>
99022 <description>32 bit timer bit width</description>
99031 <description>Timer prescaler register</description>
99039 <description>Prescaler value</description>
99049 <description>Description collection: Capture/Compare register n</description>
99057 <description>Capture/Compare value</description>
99067 …<description>Description collection: Enable one-shot operation for Capture/Compare channel n</desc…
99075 <description>Enable one-shot operation</description>
99081 <description>Disable one-shot operation</description>
99086 <description>Enable one-shot operation</description>
99097 <description>Timer/Counter 1</description>
99108 <description>Pulse width modulation unit 0</description>
99127 …<description>Stops PWM pulse generation on all channels at the end of current PWM period, and stop…
99135 …<description>Stops PWM pulse generation on all channels at the end of current PWM period, and stop…
99141 <description>Trigger task</description>
99150 …description>Steps by one value in the current sequence on all enabled channels if DECODER.MODE=Nex…
99158 …description>Steps by one value in the current sequence on all enabled channels if DECODER.MODE=Nex…
99164 <description>Trigger task</description>
99173 <description>Peripheral tasks.</description>
99181 <description>Peripheral tasks.</description>
99187 …description>Description cluster: Starts operation using easyDMA to load the values. See peripheral…
99195 …<description>Starts operation using easyDMA to load the values. See peripheral description for ope…
99201 <description>Trigger task</description>
99210 …<description>Description cluster: Stops operation using easyDMA. This does not trigger an END even…
99218 … <description>Stops operation using easyDMA. This does not trigger an END event.</description>
99224 <description>Trigger task</description>
99235 <description>Subscribe configuration for task STOP</description>
99243 <description>DPPI channel that task STOP will subscribe to</description>
99254 <description>Disable subscription</description>
99259 <description>Enable subscription</description>
99268 <description>Subscribe configuration for task NEXTSTEP</description>
99276 <description>DPPI channel that task NEXTSTEP will subscribe to</description>
99287 <description>Disable subscription</description>
99292 <description>Enable subscription</description>
99301 <description>Subscribe configuration for tasks</description>
99309 <description>Subscribe configuration for tasks</description>
99315 <description>Description cluster: Subscribe configuration for task START</description>
99323 <description>DPPI channel that task START will subscribe to</description>
99334 <description>Disable subscription</description>
99339 <description>Enable subscription</description>
99348 <description>Description cluster: Subscribe configuration for task STOP</description>
99356 <description>DPPI channel that task STOP will subscribe to</description>
99367 <description>Disable subscription</description>
99372 <description>Enable subscription</description>
99383 … <description>Response to STOP task, emitted when PWM pulses are no longer generated</description>
99391 … <description>Response to STOP task, emitted when PWM pulses are no longer generated</description>
99397 <description>Event not generated</description>
99402 <description>Event generated</description>
99413 <description>Description collection: First PWM period started on sequence n</description>
99421 <description>First PWM period started on sequence n</description>
99427 <description>Event not generated</description>
99432 <description>Event generated</description>
99443 …<description>Description collection: Emitted at end of every sequence n, when last value from RAM …
99451 …<description>Emitted at end of every sequence n, when last value from RAM has been applied to wave…
99457 <description>Event not generated</description>
99462 <description>Event generated</description>
99471 <description>Emitted at the end of each PWM period</description>
99479 <description>Emitted at the end of each PWM period</description>
99485 <description>Event not generated</description>
99490 <description>Event generated</description>
99499 …<description>Concatenated sequences have been played the amount of times defined in LOOP.CNT</desc…
99507 …<description>Concatenated sequences have been played the amount of times defined in LOOP.CNT</desc…
99513 <description>Event not generated</description>
99518 <description>Event generated</description>
99527 …<description>Emitted when retrieving from RAM does not complete in time for the PWM module</descri…
99535 …<description>Emitted when retrieving from RAM does not complete in time for the PWM module</descri…
99541 <description>Event not generated</description>
99546 <description>Event generated</description>
99555 <description>Peripheral events.</description>
99563 <description>Peripheral events.</description>
99569 …<description>Description cluster: Generated after all MAXCNT bytes have been transferred</descript…
99577 <description>Generated after all MAXCNT bytes have been transferred</description>
99583 <description>Event not generated</description>
99588 <description>Event generated</description>
99597 …description>Description cluster: Generated when EasyDMA has buffered the .PTR and .MAXCNT register…
99605 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
99611 <description>Event not generated</description>
99616 <description>Event generated</description>
99625 … <description>Description cluster: An error occured during the bus transfer.</description>
99633 <description>An error occured during the bus transfer.</description>
99639 <description>Event not generated</description>
99644 <description>Event generated</description>
99657 …<description>Description collection: This event is generated when the compare matches for the comp…
99665 …<description>This event is generated when the compare matches for the compare channel [n].</descri…
99671 <description>Event not generated</description>
99676 <description>Event generated</description>
99685 <description>Publish configuration for event STOPPED</description>
99693 <description>DPPI channel that event STOPPED will publish to</description>
99704 <description>Disable publishing</description>
99709 <description>Enable publishing</description>
99720 … <description>Description collection: Publish configuration for event SEQSTARTED[n]</description>
99728 <description>DPPI channel that event SEQSTARTED[n] will publish to</description>
99739 <description>Disable publishing</description>
99744 <description>Enable publishing</description>
99755 … <description>Description collection: Publish configuration for event SEQEND[n]</description>
99763 <description>DPPI channel that event SEQEND[n] will publish to</description>
99774 <description>Disable publishing</description>
99779 <description>Enable publishing</description>
99788 <description>Publish configuration for event PWMPERIODEND</description>
99796 <description>DPPI channel that event PWMPERIODEND will publish to</description>
99807 <description>Disable publishing</description>
99812 <description>Enable publishing</description>
99821 <description>Publish configuration for event LOOPSDONE</description>
99829 <description>DPPI channel that event LOOPSDONE will publish to</description>
99840 <description>Disable publishing</description>
99845 <description>Enable publishing</description>
99854 <description>Publish configuration for event RAMUNDERFLOW</description>
99862 <description>DPPI channel that event RAMUNDERFLOW will publish to</description>
99873 <description>Disable publishing</description>
99878 <description>Enable publishing</description>
99887 <description>Publish configuration for events</description>
99895 <description>Publish configuration for events</description>
99901 <description>Description cluster: Publish configuration for event END</description>
99909 <description>DPPI channel that event END will publish to</description>
99920 <description>Disable publishing</description>
99925 <description>Enable publishing</description>
99934 <description>Description cluster: Publish configuration for event READY</description>
99942 <description>DPPI channel that event READY will publish to</description>
99953 <description>Disable publishing</description>
99958 <description>Enable publishing</description>
99967 … <description>Description cluster: Publish configuration for event BUSERROR</description>
99975 <description>DPPI channel that event BUSERROR will publish to</description>
99986 <description>Disable publishing</description>
99991 <description>Enable publishing</description>
100004 … <description>Description collection: Publish configuration for event COMPAREMATCH[n]</description>
100012 <description>DPPI channel that event COMPAREMATCH[n] will publish to</description>
100023 <description>Disable publishing</description>
100028 <description>Enable publishing</description>
100037 <description>Shortcuts between local events and tasks</description>
100045 <description>Shortcut between event SEQEND[n] and task STOP</description>
100051 <description>Disable shortcut</description>
100056 <description>Enable shortcut</description>
100063 <description>Shortcut between event SEQEND[n] and task STOP</description>
100069 <description>Disable shortcut</description>
100074 <description>Enable shortcut</description>
100081 <description>Shortcut between event LOOPSDONE and task DMA.SEQ[n].START</description>
100087 <description>Disable shortcut</description>
100092 <description>Enable shortcut</description>
100099 <description>Shortcut between event LOOPSDONE and task DMA.SEQ[n].START</description>
100105 <description>Disable shortcut</description>
100110 <description>Enable shortcut</description>
100117 <description>Shortcut between event LOOPSDONE and task STOP</description>
100123 <description>Disable shortcut</description>
100128 <description>Enable shortcut</description>
100135 <description>Shortcut between event RAMUNDERFLOW and task STOP</description>
100141 <description>Disable shortcut</description>
100146 <description>Enable shortcut</description>
100153 <description>Shortcut between event DMA.SEQ[n].BUSERROR and task STOP</description>
100159 <description>Disable shortcut</description>
100164 <description>Enable shortcut</description>
100171 <description>Shortcut between event DMA.SEQ[n].BUSERROR and task STOP</description>
100177 <description>Disable shortcut</description>
100182 <description>Enable shortcut</description>
100191 <description>Enable or disable interrupt</description>
100199 <description>Enable or disable interrupt for event STOPPED</description>
100205 <description>Disable</description>
100210 <description>Enable</description>
100217 <description>Enable or disable interrupt for event SEQSTARTED[0]</description>
100223 <description>Disable</description>
100228 <description>Enable</description>
100235 <description>Enable or disable interrupt for event SEQSTARTED[1]</description>
100241 <description>Disable</description>
100246 <description>Enable</description>
100253 <description>Enable or disable interrupt for event SEQEND[0]</description>
100259 <description>Disable</description>
100264 <description>Enable</description>
100271 <description>Enable or disable interrupt for event SEQEND[1]</description>
100277 <description>Disable</description>
100282 <description>Enable</description>
100289 <description>Enable or disable interrupt for event PWMPERIODEND</description>
100295 <description>Disable</description>
100300 <description>Enable</description>
100307 <description>Enable or disable interrupt for event LOOPSDONE</description>
100313 <description>Disable</description>
100318 <description>Enable</description>
100325 <description>Enable or disable interrupt for event RAMUNDERFLOW</description>
100331 <description>Disable</description>
100336 <description>Enable</description>
100343 <description>Enable or disable interrupt for event DMASEQ0END</description>
100349 <description>Disable</description>
100354 <description>Enable</description>
100361 <description>Enable or disable interrupt for event DMASEQ0READY</description>
100367 <description>Disable</description>
100372 <description>Enable</description>
100379 <description>Enable or disable interrupt for event DMASEQ0BUSERROR</description>
100385 <description>Disable</description>
100390 <description>Enable</description>
100397 <description>Enable or disable interrupt for event DMASEQ1END</description>
100403 <description>Disable</description>
100408 <description>Enable</description>
100415 <description>Enable or disable interrupt for event DMASEQ1READY</description>
100421 <description>Disable</description>
100426 <description>Enable</description>
100433 <description>Enable or disable interrupt for event DMASEQ1BUSERROR</description>
100439 <description>Disable</description>
100444 <description>Enable</description>
100451 <description>Enable or disable interrupt for event COMPAREMATCH[0]</description>
100457 <description>Disable</description>
100462 <description>Enable</description>
100469 <description>Enable or disable interrupt for event COMPAREMATCH[1]</description>
100475 <description>Disable</description>
100480 <description>Enable</description>
100487 <description>Enable or disable interrupt for event COMPAREMATCH[2]</description>
100493 <description>Disable</description>
100498 <description>Enable</description>
100505 <description>Enable or disable interrupt for event COMPAREMATCH[3]</description>
100511 <description>Disable</description>
100516 <description>Enable</description>
100525 <description>Enable interrupt</description>
100533 <description>Write '1' to enable interrupt for event STOPPED</description>
100540 <description>Read: Disabled</description>
100545 <description>Read: Enabled</description>
100553 <description>Enable</description>
100560 <description>Write '1' to enable interrupt for event SEQSTARTED[0]</description>
100567 <description>Read: Disabled</description>
100572 <description>Read: Enabled</description>
100580 <description>Enable</description>
100587 <description>Write '1' to enable interrupt for event SEQSTARTED[1]</description>
100594 <description>Read: Disabled</description>
100599 <description>Read: Enabled</description>
100607 <description>Enable</description>
100614 <description>Write '1' to enable interrupt for event SEQEND[0]</description>
100621 <description>Read: Disabled</description>
100626 <description>Read: Enabled</description>
100634 <description>Enable</description>
100641 <description>Write '1' to enable interrupt for event SEQEND[1]</description>
100648 <description>Read: Disabled</description>
100653 <description>Read: Enabled</description>
100661 <description>Enable</description>
100668 <description>Write '1' to enable interrupt for event PWMPERIODEND</description>
100675 <description>Read: Disabled</description>
100680 <description>Read: Enabled</description>
100688 <description>Enable</description>
100695 <description>Write '1' to enable interrupt for event LOOPSDONE</description>
100702 <description>Read: Disabled</description>
100707 <description>Read: Enabled</description>
100715 <description>Enable</description>
100722 <description>Write '1' to enable interrupt for event RAMUNDERFLOW</description>
100729 <description>Read: Disabled</description>
100734 <description>Read: Enabled</description>
100742 <description>Enable</description>
100749 <description>Write '1' to enable interrupt for event DMASEQ0END</description>
100756 <description>Read: Disabled</description>
100761 <description>Read: Enabled</description>
100769 <description>Enable</description>
100776 <description>Write '1' to enable interrupt for event DMASEQ0READY</description>
100783 <description>Read: Disabled</description>
100788 <description>Read: Enabled</description>
100796 <description>Enable</description>
100803 <description>Write '1' to enable interrupt for event DMASEQ0BUSERROR</description>
100810 <description>Read: Disabled</description>
100815 <description>Read: Enabled</description>
100823 <description>Enable</description>
100830 <description>Write '1' to enable interrupt for event DMASEQ1END</description>
100837 <description>Read: Disabled</description>
100842 <description>Read: Enabled</description>
100850 <description>Enable</description>
100857 <description>Write '1' to enable interrupt for event DMASEQ1READY</description>
100864 <description>Read: Disabled</description>
100869 <description>Read: Enabled</description>
100877 <description>Enable</description>
100884 <description>Write '1' to enable interrupt for event DMASEQ1BUSERROR</description>
100891 <description>Read: Disabled</description>
100896 <description>Read: Enabled</description>
100904 <description>Enable</description>
100911 <description>Write '1' to enable interrupt for event COMPAREMATCH[0]</description>
100918 <description>Read: Disabled</description>
100923 <description>Read: Enabled</description>
100931 <description>Enable</description>
100938 <description>Write '1' to enable interrupt for event COMPAREMATCH[1]</description>
100945 <description>Read: Disabled</description>
100950 <description>Read: Enabled</description>
100958 <description>Enable</description>
100965 <description>Write '1' to enable interrupt for event COMPAREMATCH[2]</description>
100972 <description>Read: Disabled</description>
100977 <description>Read: Enabled</description>
100985 <description>Enable</description>
100992 <description>Write '1' to enable interrupt for event COMPAREMATCH[3]</description>
100999 <description>Read: Disabled</description>
101004 <description>Read: Enabled</description>
101012 <description>Enable</description>
101021 <description>Disable interrupt</description>
101029 <description>Write '1' to disable interrupt for event STOPPED</description>
101036 <description>Read: Disabled</description>
101041 <description>Read: Enabled</description>
101049 <description>Disable</description>
101056 <description>Write '1' to disable interrupt for event SEQSTARTED[0]</description>
101063 <description>Read: Disabled</description>
101068 <description>Read: Enabled</description>
101076 <description>Disable</description>
101083 <description>Write '1' to disable interrupt for event SEQSTARTED[1]</description>
101090 <description>Read: Disabled</description>
101095 <description>Read: Enabled</description>
101103 <description>Disable</description>
101110 <description>Write '1' to disable interrupt for event SEQEND[0]</description>
101117 <description>Read: Disabled</description>
101122 <description>Read: Enabled</description>
101130 <description>Disable</description>
101137 <description>Write '1' to disable interrupt for event SEQEND[1]</description>
101144 <description>Read: Disabled</description>
101149 <description>Read: Enabled</description>
101157 <description>Disable</description>
101164 <description>Write '1' to disable interrupt for event PWMPERIODEND</description>
101171 <description>Read: Disabled</description>
101176 <description>Read: Enabled</description>
101184 <description>Disable</description>
101191 <description>Write '1' to disable interrupt for event LOOPSDONE</description>
101198 <description>Read: Disabled</description>
101203 <description>Read: Enabled</description>
101211 <description>Disable</description>
101218 <description>Write '1' to disable interrupt for event RAMUNDERFLOW</description>
101225 <description>Read: Disabled</description>
101230 <description>Read: Enabled</description>
101238 <description>Disable</description>
101245 <description>Write '1' to disable interrupt for event DMASEQ0END</description>
101252 <description>Read: Disabled</description>
101257 <description>Read: Enabled</description>
101265 <description>Disable</description>
101272 <description>Write '1' to disable interrupt for event DMASEQ0READY</description>
101279 <description>Read: Disabled</description>
101284 <description>Read: Enabled</description>
101292 <description>Disable</description>
101299 <description>Write '1' to disable interrupt for event DMASEQ0BUSERROR</description>
101306 <description>Read: Disabled</description>
101311 <description>Read: Enabled</description>
101319 <description>Disable</description>
101326 <description>Write '1' to disable interrupt for event DMASEQ1END</description>
101333 <description>Read: Disabled</description>
101338 <description>Read: Enabled</description>
101346 <description>Disable</description>
101353 <description>Write '1' to disable interrupt for event DMASEQ1READY</description>
101360 <description>Read: Disabled</description>
101365 <description>Read: Enabled</description>
101373 <description>Disable</description>
101380 <description>Write '1' to disable interrupt for event DMASEQ1BUSERROR</description>
101387 <description>Read: Disabled</description>
101392 <description>Read: Enabled</description>
101400 <description>Disable</description>
101407 <description>Write '1' to disable interrupt for event COMPAREMATCH[0]</description>
101414 <description>Read: Disabled</description>
101419 <description>Read: Enabled</description>
101427 <description>Disable</description>
101434 <description>Write '1' to disable interrupt for event COMPAREMATCH[1]</description>
101441 <description>Read: Disabled</description>
101446 <description>Read: Enabled</description>
101454 <description>Disable</description>
101461 <description>Write '1' to disable interrupt for event COMPAREMATCH[2]</description>
101468 <description>Read: Disabled</description>
101473 <description>Read: Enabled</description>
101481 <description>Disable</description>
101488 <description>Write '1' to disable interrupt for event COMPAREMATCH[3]</description>
101495 <description>Read: Disabled</description>
101500 <description>Read: Enabled</description>
101508 <description>Disable</description>
101517 <description>Pending interrupts</description>
101525 <description>Read pending status of interrupt for event STOPPED</description>
101532 <description>Read: Not pending</description>
101537 <description>Read: Pending</description>
101544 <description>Read pending status of interrupt for event SEQSTARTED[0]</description>
101551 <description>Read: Not pending</description>
101556 <description>Read: Pending</description>
101563 <description>Read pending status of interrupt for event SEQSTARTED[1]</description>
101570 <description>Read: Not pending</description>
101575 <description>Read: Pending</description>
101582 <description>Read pending status of interrupt for event SEQEND[0]</description>
101589 <description>Read: Not pending</description>
101594 <description>Read: Pending</description>
101601 <description>Read pending status of interrupt for event SEQEND[1]</description>
101608 <description>Read: Not pending</description>
101613 <description>Read: Pending</description>
101620 <description>Read pending status of interrupt for event PWMPERIODEND</description>
101627 <description>Read: Not pending</description>
101632 <description>Read: Pending</description>
101639 <description>Read pending status of interrupt for event LOOPSDONE</description>
101646 <description>Read: Not pending</description>
101651 <description>Read: Pending</description>
101658 <description>Read pending status of interrupt for event RAMUNDERFLOW</description>
101665 <description>Read: Not pending</description>
101670 <description>Read: Pending</description>
101677 <description>Read pending status of interrupt for event DMASEQ0END</description>
101684 <description>Read: Not pending</description>
101689 <description>Read: Pending</description>
101696 <description>Read pending status of interrupt for event DMASEQ0READY</description>
101703 <description>Read: Not pending</description>
101708 <description>Read: Pending</description>
101715 <description>Read pending status of interrupt for event DMASEQ0BUSERROR</description>
101722 <description>Read: Not pending</description>
101727 <description>Read: Pending</description>
101734 <description>Read pending status of interrupt for event DMASEQ1END</description>
101741 <description>Read: Not pending</description>
101746 <description>Read: Pending</description>
101753 <description>Read pending status of interrupt for event DMASEQ1READY</description>
101760 <description>Read: Not pending</description>
101765 <description>Read: Pending</description>
101772 <description>Read pending status of interrupt for event DMASEQ1BUSERROR</description>
101779 <description>Read: Not pending</description>
101784 <description>Read: Pending</description>
101791 <description>Read pending status of interrupt for event COMPAREMATCH[0]</description>
101798 <description>Read: Not pending</description>
101803 <description>Read: Pending</description>
101810 <description>Read pending status of interrupt for event COMPAREMATCH[1]</description>
101817 <description>Read: Not pending</description>
101822 <description>Read: Pending</description>
101829 <description>Read pending status of interrupt for event COMPAREMATCH[2]</description>
101836 <description>Read: Not pending</description>
101841 <description>Read: Pending</description>
101848 <description>Read pending status of interrupt for event COMPAREMATCH[3]</description>
101855 <description>Read: Not pending</description>
101860 <description>Read: Pending</description>
101869 <description>PWM module enable register</description>
101877 <description>Enable or disable PWM module</description>
101883 <description>Disabled</description>
101888 <description>Enable</description>
101897 <description>Selects operating mode of the wave counter</description>
101905 <description>Selects up mode or up-and-down mode for the counter</description>
101911 <description>Up counter, edge-aligned PWM duty cycle</description>
101916 <description>Up and down counter, center-aligned PWM duty cycle</description>
101925 <description>Value up to which the pulse generator counter counts</description>
101933 …description>Value up to which the pulse generator counter counts. This register is ignored when DE…
101941 <description>Configuration for PWM_CLK</description>
101949 <description>Prescaler of PWM_CLK</description>
101955 <description>Divide by 1 (16 MHz)</description>
101960 <description>Divide by 2 (8 MHz)</description>
101965 <description>Divide by 4 (4 MHz)</description>
101970 <description>Divide by 8 (2 MHz)</description>
101975 <description>Divide by 16 (1 MHz)</description>
101980 <description>Divide by 32 (500 kHz)</description>
101985 <description>Divide by 64 (250 kHz)</description>
101990 <description>Divide by 128 (125 kHz)</description>
101999 <description>Configuration of the decoder</description>
102007 … <description>How a sequence is read from RAM and spread to the compare register</description>
102013 <description>1st half word (16-bit) used in all PWM channels 0..3</description>
102018 … <description>1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3</description>
102023 … <description>1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3</description>
102028 … <description>1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP</description>
102035 <description>Selects source for advancing the active sequence</description>
102041 … <description>SEQ[n].REFRESH is used to determine loading internal compare registers</description>
102046 …<description>NEXTSTEP task causes a new value to be loaded to internal compare registers</descript…
102055 <description>Number of playbacks of a loop</description>
102063 <description>Number of playbacks of pattern cycles</description>
102069 <description>Looping disabled (stop at the end of the sequence)</description>
102078 <description>Configure the output value on the PWM channel during idle</description>
102086 <description>Idle output value for PWM channel [0]</description>
102092 <description>Idle output value for PWM channel [1]</description>
102098 <description>Idle output value for PWM channel [2]</description>
102104 <description>Idle output value for PWM channel [3]</description>
102114 <description>Unspecified</description>
102120 …<description>Description cluster: Number of additional PWM periods between samples loaded into com…
102128 …<description>Number of additional PWM periods between samples loaded into compare register (load e…
102134 <description>Update every PWM period</description>
102143 <description>Description cluster: Time added after the sequence</description>
102151 <description>Time added after the sequence in PWM periods</description>
102160 <description>Unspecified</description>
102168 <description>Description collection: Output pin select for PWM channel n</description>
102176 <description>Pin number</description>
102182 <description>Port number</description>
102188 <description>Connection</description>
102194 <description>Disconnect</description>
102199 <description>Connect</description>
102209 <description>Unspecified</description>
102217 <description>Unspecified</description>
102223 <description>Description cluster: RAM buffer start address</description>
102231 …<description>RAM buffer start address for this EasyDMA channel. This address is a word aligned Dat…
102239 … <description>Description cluster: Maximum number of bytes in channel buffer</description>
102247 <description>Maximum number of bytes in channel buffer</description>
102255 …<description>Description cluster: Number of bytes transferred in the last transaction, updated aft…
102263 …<description>Number of bytes transferred in the last transaction. In case of NACK error, includes …
102271 …<description>Description cluster: Number of bytes transferred in the current transaction</descript…
102279 …<description>Number of bytes transferred in the current transaction. Continuously updated.</descri…
102287 …<description>Description cluster: Terminate the transaction if a BUSERROR event is detected.</desc…
102300 <description>Disable</description>
102305 <description>Enable</description>
102314 …<description>Description cluster: Address of transaction that generated the last BUSERROR event.</…
102333 <description>SPI Slave 0</description>
102352 <description>Acquire SPI semaphore</description>
102360 <description>Acquire SPI semaphore</description>
102366 <description>Trigger task</description>
102375 <description>Release SPI semaphore, enabling the SPI slave to acquire it</description>
102383 <description>Release SPI semaphore, enabling the SPI slave to acquire it</description>
102389 <description>Trigger task</description>
102398 <description>Peripheral tasks.</description>
102404 <description>Peripheral tasks.</description>
102412 …<description>Description collection: Enables the MATCH[n] event by setting the ENABLE[n] bit in th…
102420 …<description>Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register.</desc…
102426 <description>Trigger task</description>
102437 …<description>Description collection: Disables the MATCH[n] event by clearing the ENABLE[n] bit in …
102445 …<description>Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register.</de…
102451 <description>Trigger task</description>
102462 <description>Subscribe configuration for task ACQUIRE</description>
102470 <description>DPPI channel that task ACQUIRE will subscribe to</description>
102481 <description>Disable subscription</description>
102486 <description>Enable subscription</description>
102495 <description>Subscribe configuration for task RELEASE</description>
102503 <description>DPPI channel that task RELEASE will subscribe to</description>
102514 <description>Disable subscription</description>
102519 <description>Enable subscription</description>
102528 <description>Subscribe configuration for tasks</description>
102534 <description>Subscribe configuration for tasks</description>
102542 … <description>Description collection: Subscribe configuration for task ENABLEMATCH[n]</description>
102550 <description>DPPI channel that task ENABLEMATCH[n] will subscribe to</description>
102561 <description>Disable subscription</description>
102566 <description>Enable subscription</description>
102577 …<description>Description collection: Subscribe configuration for task DISABLEMATCH[n]</description>
102585 … <description>DPPI channel that task DISABLEMATCH[n] will subscribe to</description>
102596 <description>Disable subscription</description>
102601 <description>Enable subscription</description>
102612 <description>Granted transaction completed</description>
102620 <description>Granted transaction completed</description>
102626 <description>Event not generated</description>
102631 <description>Event generated</description>
102640 <description>Semaphore acquired</description>
102648 <description>Semaphore acquired</description>
102654 <description>Event not generated</description>
102659 <description>Event generated</description>
102668 <description>Peripheral events.</description>
102674 <description>Peripheral events.</description>
102680 <description>Generated after all MAXCNT bytes have been transferred</description>
102688 <description>Generated after all MAXCNT bytes have been transferred</description>
102694 <description>Event not generated</description>
102699 <description>Event generated</description>
102708 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
102716 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
102722 <description>Event not generated</description>
102727 <description>Event generated</description>
102736 <description>An error occured during the bus transfer.</description>
102744 <description>An error occured during the bus transfer.</description>
102750 <description>Event not generated</description>
102755 <description>Event generated</description>
102766 … <description>Description collection: Pattern match is detected on the DMA data bus.</description>
102774 <description>Pattern match is detected on the DMA data bus.</description>
102780 <description>Event not generated</description>
102785 <description>Event generated</description>
102795 <description>Peripheral events.</description>
102801 <description>Generated after all MAXCNT bytes have been transferred</description>
102809 <description>Generated after all MAXCNT bytes have been transferred</description>
102815 <description>Event not generated</description>
102820 <description>Event generated</description>
102829 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
102837 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
102843 <description>Event not generated</description>
102848 <description>Event generated</description>
102857 <description>An error occured during the bus transfer.</description>
102865 <description>An error occured during the bus transfer.</description>
102871 <description>Event not generated</description>
102876 <description>Event generated</description>
102887 <description>Publish configuration for event END</description>
102895 <description>DPPI channel that event END will publish to</description>
102906 <description>Disable publishing</description>
102911 <description>Enable publishing</description>
102920 <description>Publish configuration for event ACQUIRED</description>
102928 <description>DPPI channel that event ACQUIRED will publish to</description>
102939 <description>Disable publishing</description>
102944 <description>Enable publishing</description>
102953 <description>Publish configuration for events</description>
102959 <description>Publish configuration for events</description>
102965 <description>Publish configuration for event END</description>
102973 <description>DPPI channel that event END will publish to</description>
102984 <description>Disable publishing</description>
102989 <description>Enable publishing</description>
102998 <description>Publish configuration for event READY</description>
103006 <description>DPPI channel that event READY will publish to</description>
103017 <description>Disable publishing</description>
103022 <description>Enable publishing</description>
103031 <description>Publish configuration for event BUSERROR</description>
103039 <description>DPPI channel that event BUSERROR will publish to</description>
103050 <description>Disable publishing</description>
103055 <description>Enable publishing</description>
103066 … <description>Description collection: Publish configuration for event MATCH[n]</description>
103074 <description>DPPI channel that event MATCH[n] will publish to</description>
103085 <description>Disable publishing</description>
103090 <description>Enable publishing</description>
103100 <description>Publish configuration for events</description>
103106 <description>Publish configuration for event END</description>
103114 <description>DPPI channel that event END will publish to</description>
103125 <description>Disable publishing</description>
103130 <description>Enable publishing</description>
103139 <description>Publish configuration for event READY</description>
103147 <description>DPPI channel that event READY will publish to</description>
103158 <description>Disable publishing</description>
103163 <description>Enable publishing</description>
103172 <description>Publish configuration for event BUSERROR</description>
103180 <description>DPPI channel that event BUSERROR will publish to</description>
103191 <description>Disable publishing</description>
103196 <description>Enable publishing</description>
103207 <description>Shortcuts between local events and tasks</description>
103215 <description>Shortcut between event END and task ACQUIRE</description>
103221 <description>Disable shortcut</description>
103226 <description>Enable shortcut</description>
103233 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows daisy-ch…
103239 <description>Disable shortcut</description>
103244 <description>Enable shortcut</description>
103251 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows daisy-ch…
103257 <description>Disable shortcut</description>
103262 <description>Enable shortcut</description>
103269 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows daisy-ch…
103275 <description>Disable shortcut</description>
103280 <description>Enable shortcut</description>
103287 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows daisy-ch…
103293 <description>Disable shortcut</description>
103298 <description>Enable shortcut</description>
103305 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
103311 <description>Disable shortcut</description>
103316 <description>Enable shortcut</description>
103323 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
103329 <description>Disable shortcut</description>
103334 <description>Enable shortcut</description>
103341 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
103347 <description>Disable shortcut</description>
103352 <description>Enable shortcut</description>
103359 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
103365 <description>Disable shortcut</description>
103370 <description>Enable shortcut</description>
103379 <description>Enable interrupt</description>
103387 <description>Write '1' to enable interrupt for event END</description>
103394 <description>Read: Disabled</description>
103399 <description>Read: Enabled</description>
103407 <description>Enable</description>
103414 <description>Write '1' to enable interrupt for event ACQUIRED</description>
103421 <description>Read: Disabled</description>
103426 <description>Read: Enabled</description>
103434 <description>Enable</description>
103441 <description>Write '1' to enable interrupt for event DMARXEND</description>
103448 <description>Read: Disabled</description>
103453 <description>Read: Enabled</description>
103461 <description>Enable</description>
103468 <description>Write '1' to enable interrupt for event DMARXREADY</description>
103475 <description>Read: Disabled</description>
103480 <description>Read: Enabled</description>
103488 <description>Enable</description>
103495 <description>Write '1' to enable interrupt for event DMARXBUSERROR</description>
103502 <description>Read: Disabled</description>
103507 <description>Read: Enabled</description>
103515 <description>Enable</description>
103522 <description>Write '1' to enable interrupt for event DMARXMATCH[0]</description>
103529 <description>Read: Disabled</description>
103534 <description>Read: Enabled</description>
103542 <description>Enable</description>
103549 <description>Write '1' to enable interrupt for event DMARXMATCH[1]</description>
103556 <description>Read: Disabled</description>
103561 <description>Read: Enabled</description>
103569 <description>Enable</description>
103576 <description>Write '1' to enable interrupt for event DMARXMATCH[2]</description>
103583 <description>Read: Disabled</description>
103588 <description>Read: Enabled</description>
103596 <description>Enable</description>
103603 <description>Write '1' to enable interrupt for event DMARXMATCH[3]</description>
103610 <description>Read: Disabled</description>
103615 <description>Read: Enabled</description>
103623 <description>Enable</description>
103630 <description>Write '1' to enable interrupt for event DMATXEND</description>
103637 <description>Read: Disabled</description>
103642 <description>Read: Enabled</description>
103650 <description>Enable</description>
103657 <description>Write '1' to enable interrupt for event DMATXREADY</description>
103664 <description>Read: Disabled</description>
103669 <description>Read: Enabled</description>
103677 <description>Enable</description>
103684 <description>Write '1' to enable interrupt for event DMATXBUSERROR</description>
103691 <description>Read: Disabled</description>
103696 <description>Read: Enabled</description>
103704 <description>Enable</description>
103713 <description>Disable interrupt</description>
103721 <description>Write '1' to disable interrupt for event END</description>
103728 <description>Read: Disabled</description>
103733 <description>Read: Enabled</description>
103741 <description>Disable</description>
103748 <description>Write '1' to disable interrupt for event ACQUIRED</description>
103755 <description>Read: Disabled</description>
103760 <description>Read: Enabled</description>
103768 <description>Disable</description>
103775 <description>Write '1' to disable interrupt for event DMARXEND</description>
103782 <description>Read: Disabled</description>
103787 <description>Read: Enabled</description>
103795 <description>Disable</description>
103802 <description>Write '1' to disable interrupt for event DMARXREADY</description>
103809 <description>Read: Disabled</description>
103814 <description>Read: Enabled</description>
103822 <description>Disable</description>
103829 <description>Write '1' to disable interrupt for event DMARXBUSERROR</description>
103836 <description>Read: Disabled</description>
103841 <description>Read: Enabled</description>
103849 <description>Disable</description>
103856 <description>Write '1' to disable interrupt for event DMARXMATCH[0]</description>
103863 <description>Read: Disabled</description>
103868 <description>Read: Enabled</description>
103876 <description>Disable</description>
103883 <description>Write '1' to disable interrupt for event DMARXMATCH[1]</description>
103890 <description>Read: Disabled</description>
103895 <description>Read: Enabled</description>
103903 <description>Disable</description>
103910 <description>Write '1' to disable interrupt for event DMARXMATCH[2]</description>
103917 <description>Read: Disabled</description>
103922 <description>Read: Enabled</description>
103930 <description>Disable</description>
103937 <description>Write '1' to disable interrupt for event DMARXMATCH[3]</description>
103944 <description>Read: Disabled</description>
103949 <description>Read: Enabled</description>
103957 <description>Disable</description>
103964 <description>Write '1' to disable interrupt for event DMATXEND</description>
103971 <description>Read: Disabled</description>
103976 <description>Read: Enabled</description>
103984 <description>Disable</description>
103991 <description>Write '1' to disable interrupt for event DMATXREADY</description>
103998 <description>Read: Disabled</description>
104003 <description>Read: Enabled</description>
104011 <description>Disable</description>
104018 <description>Write '1' to disable interrupt for event DMATXBUSERROR</description>
104025 <description>Read: Disabled</description>
104030 <description>Read: Enabled</description>
104038 <description>Disable</description>
104047 <description>Semaphore status register</description>
104055 <description>Semaphore status</description>
104061 <description>Semaphore is free</description>
104066 <description>Semaphore is assigned to CPU</description>
104071 <description>Semaphore is assigned to SPI slave</description>
104076 … <description>Semaphore is assigned to SPI but a handover to the CPU is pending</description>
104085 <description>Status from last transaction</description>
104093 <description>TX buffer over-read detected, and prevented</description>
104100 <description>Read: error not present</description>
104105 <description>Read: error present</description>
104113 <description>Write: clear error on writing '1'</description>
104120 <description>RX buffer overflow detected, and prevented</description>
104127 <description>Read: error not present</description>
104132 <description>Read: error present</description>
104140 <description>Write: clear error on writing '1'</description>
104149 <description>Enable SPI slave</description>
104157 <description>Enable or disable SPI slave</description>
104163 <description>Disable SPI slave</description>
104168 <description>Enable SPI slave</description>
104177 <description>Configuration register</description>
104185 <description>Bit order</description>
104191 <description>Most significant bit shifted out first</description>
104196 <description>Least significant bit shifted out first</description>
104203 <description>Serial clock (SCK) phase</description>
104209 … <description>Sample on leading edge of clock, shift serial data on trailing edge</description>
104214 … <description>Sample on trailing edge of clock, shift serial data on leading edge</description>
104221 <description>Serial clock (SCK) polarity</description>
104227 <description>Active high</description>
104232 <description>Active low</description>
104241 …<description>Default character. Character clocked out in case of an ignored transaction.</descript…
104249 …<description>Default character. Character clocked out in case of an ignored transaction.</descript…
104257 <description>Over-read character</description>
104265 …<description>Over-read character. Character clocked out after an over-read of the transmit buffer.…
104273 <description>Unspecified</description>
104279 <description>Pin select for SCK</description>
104287 <description>Pin number</description>
104293 <description>Port number</description>
104299 <description>Connection</description>
104305 <description>Disconnect</description>
104310 <description>Connect</description>
104319 <description>Pin select for MISO signal</description>
104327 <description>Pin number</description>
104333 <description>Port number</description>
104339 <description>Connection</description>
104345 <description>Disconnect</description>
104350 <description>Connect</description>
104359 <description>Pin select for MOSI signal</description>
104367 <description>Pin number</description>
104373 <description>Port number</description>
104379 <description>Connection</description>
104385 <description>Disconnect</description>
104390 <description>Connect</description>
104399 <description>Pin select for CSN signal</description>
104407 <description>Pin number</description>
104413 <description>Port number</description>
104419 <description>Connection</description>
104425 <description>Disconnect</description>
104430 <description>Connect</description>
104440 <description>Unspecified</description>
104446 <description>Unspecified</description>
104452 <description>RAM buffer start address</description>
104460 …<description>RAM buffer start address for this EasyDMA channel. This address is a word aligned Dat…
104468 <description>Maximum number of bytes in channel buffer</description>
104476 <description>Maximum number of bytes in channel buffer</description>
104484 …<description>Number of bytes transferred in the last transaction, updated after the END event. Als…
104492 …<description>Number of bytes transferred in the last transaction. In case of NACK error, includes …
104500 <description>Number of bytes transferred in the current transaction</description>
104508 …<description>Number of bytes transferred in the current transaction. Continuously updated.</descri…
104516 <description>EasyDMA list type</description>
104524 <description>List type</description>
104530 <description>Disable EasyDMA list</description>
104535 <description>Use array list</description>
104544 <description>Terminate the transaction if a BUSERROR event is detected.</description>
104557 <description>Disable</description>
104562 <description>Enable</description>
104571 … <description>Address of transaction that generated the last BUSERROR event.</description>
104586 … <description>Registers to control the behavior of the pattern matcher engine</description>
104592 <description>Configure individual match events</description>
104600 <description>Enable match filter 0</description>
104606 <description>Match filter disabled</description>
104611 <description>Match filter enabled</description>
104618 <description>Enable match filter 1</description>
104624 <description>Match filter disabled</description>
104629 <description>Match filter enabled</description>
104636 <description>Enable match filter 2</description>
104642 <description>Match filter disabled</description>
104647 <description>Match filter enabled</description>
104654 <description>Enable match filter 3</description>
104660 <description>Match filter disabled</description>
104665 <description>Match filter enabled</description>
104672 <description>Configure match filter 0 as one-shot or sticky</description>
104678 <description>Match filter stays enabled until disabled by task</description>
104683 … <description>Match filter stays enabled until next data word is received</description>
104690 <description>Configure match filter 1 as one-shot or sticky</description>
104696 <description>Match filter stays enabled until disabled by task</description>
104701 … <description>Match filter stays enabled until next data word is received</description>
104708 <description>Configure match filter 2 as one-shot or sticky</description>
104714 <description>Match filter stays enabled until disabled by task</description>
104719 … <description>Match filter stays enabled until next data word is received</description>
104726 <description>Configure match filter 3 as one-shot or sticky</description>
104732 <description>Match filter stays enabled until disabled by task</description>
104737 … <description>Match filter stays enabled until next data word is received</description>
104748 …<description>Description collection: The data to look for - any match will trigger the MATCH[n] ev…
104756 <description>Data to look for</description>
104766 <description>Unspecified</description>
104772 <description>RAM buffer start address</description>
104780 …<description>RAM buffer start address for this EasyDMA channel. This address is a word aligned Dat…
104788 <description>Maximum number of bytes in channel buffer</description>
104796 <description>Maximum number of bytes in channel buffer</description>
104804 …<description>Number of bytes transferred in the last transaction, updated after the END event. Als…
104812 …<description>Number of bytes transferred in the last transaction. In case of NACK error, includes …
104820 <description>Number of bytes transferred in the current transaction</description>
104828 …<description>Number of bytes transferred in the current transaction. Continuously updated.</descri…
104836 <description>EasyDMA list type</description>
104844 <description>List type</description>
104850 <description>Disable EasyDMA list</description>
104855 <description>Use array list</description>
104864 <description>Terminate the transaction if a BUSERROR event is detected.</description>
104877 <description>Disable</description>
104882 <description>Enable</description>
104891 … <description>Address of transaction that generated the last BUSERROR event.</description>
104910 <description>Serial Peripheral Interface Master with EasyDMA 0</description>
104929 <description>Start SPI transaction</description>
104937 <description>Start SPI transaction</description>
104943 <description>Trigger task</description>
104952 <description>Stop SPI transaction</description>
104960 <description>Stop SPI transaction</description>
104966 <description>Trigger task</description>
104975 <description>Suspend SPI transaction</description>
104983 <description>Suspend SPI transaction</description>
104989 <description>Trigger task</description>
104998 <description>Resume SPI transaction</description>
105006 <description>Resume SPI transaction</description>
105012 <description>Trigger task</description>
105021 <description>Peripheral tasks.</description>
105027 <description>Peripheral tasks.</description>
105035 …<description>Description collection: Enables the MATCH[n] event by setting the ENABLE[n] bit in th…
105043 …<description>Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register.</desc…
105049 <description>Trigger task</description>
105060 …<description>Description collection: Disables the MATCH[n] event by clearing the ENABLE[n] bit in …
105068 …<description>Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register.</de…
105074 <description>Trigger task</description>
105085 <description>Subscribe configuration for task START</description>
105093 <description>DPPI channel that task START will subscribe to</description>
105104 <description>Disable subscription</description>
105109 <description>Enable subscription</description>
105118 <description>Subscribe configuration for task STOP</description>
105126 <description>DPPI channel that task STOP will subscribe to</description>
105137 <description>Disable subscription</description>
105142 <description>Enable subscription</description>
105151 <description>Subscribe configuration for task SUSPEND</description>
105159 <description>DPPI channel that task SUSPEND will subscribe to</description>
105170 <description>Disable subscription</description>
105175 <description>Enable subscription</description>
105184 <description>Subscribe configuration for task RESUME</description>
105192 <description>DPPI channel that task RESUME will subscribe to</description>
105203 <description>Disable subscription</description>
105208 <description>Enable subscription</description>
105217 <description>Subscribe configuration for tasks</description>
105223 <description>Subscribe configuration for tasks</description>
105231 … <description>Description collection: Subscribe configuration for task ENABLEMATCH[n]</description>
105239 <description>DPPI channel that task ENABLEMATCH[n] will subscribe to</description>
105250 <description>Disable subscription</description>
105255 <description>Enable subscription</description>
105266 …<description>Description collection: Subscribe configuration for task DISABLEMATCH[n]</description>
105274 … <description>DPPI channel that task DISABLEMATCH[n] will subscribe to</description>
105285 <description>Disable subscription</description>
105290 <description>Enable subscription</description>
105301 <description>SPI transaction has started</description>
105309 <description>SPI transaction has started</description>
105315 <description>Event not generated</description>
105320 <description>Event generated</description>
105329 <description>SPI transaction has stopped</description>
105337 <description>SPI transaction has stopped</description>
105343 <description>Event not generated</description>
105348 <description>Event generated</description>
105357 <description>End of RXD buffer and TXD buffer reached</description>
105365 <description>End of RXD buffer and TXD buffer reached</description>
105371 <description>Event not generated</description>
105376 <description>Event generated</description>
105385 <description>Peripheral events.</description>
105391 <description>Peripheral events.</description>
105397 <description>Generated after all MAXCNT bytes have been transferred</description>
105405 <description>Generated after all MAXCNT bytes have been transferred</description>
105411 <description>Event not generated</description>
105416 <description>Event generated</description>
105425 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
105433 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
105439 <description>Event not generated</description>
105444 <description>Event generated</description>
105453 <description>An error occured during the bus transfer.</description>
105461 <description>An error occured during the bus transfer.</description>
105467 <description>Event not generated</description>
105472 <description>Event generated</description>
105483 … <description>Description collection: Pattern match is detected on the DMA data bus.</description>
105491 <description>Pattern match is detected on the DMA data bus.</description>
105497 <description>Event not generated</description>
105502 <description>Event generated</description>
105512 <description>Peripheral events.</description>
105518 <description>Generated after all MAXCNT bytes have been transferred</description>
105526 <description>Generated after all MAXCNT bytes have been transferred</description>
105532 <description>Event not generated</description>
105537 <description>Event generated</description>
105546 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
105554 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
105560 <description>Event not generated</description>
105565 <description>Event generated</description>
105574 <description>An error occured during the bus transfer.</description>
105582 <description>An error occured during the bus transfer.</description>
105588 <description>Event not generated</description>
105593 <description>Event generated</description>
105604 <description>Publish configuration for event STARTED</description>
105612 <description>DPPI channel that event STARTED will publish to</description>
105623 <description>Disable publishing</description>
105628 <description>Enable publishing</description>
105637 <description>Publish configuration for event STOPPED</description>
105645 <description>DPPI channel that event STOPPED will publish to</description>
105656 <description>Disable publishing</description>
105661 <description>Enable publishing</description>
105670 <description>Publish configuration for event END</description>
105678 <description>DPPI channel that event END will publish to</description>
105689 <description>Disable publishing</description>
105694 <description>Enable publishing</description>
105703 <description>Publish configuration for events</description>
105709 <description>Publish configuration for events</description>
105715 <description>Publish configuration for event END</description>
105723 <description>DPPI channel that event END will publish to</description>
105734 <description>Disable publishing</description>
105739 <description>Enable publishing</description>
105748 <description>Publish configuration for event READY</description>
105756 <description>DPPI channel that event READY will publish to</description>
105767 <description>Disable publishing</description>
105772 <description>Enable publishing</description>
105781 <description>Publish configuration for event BUSERROR</description>
105789 <description>DPPI channel that event BUSERROR will publish to</description>
105800 <description>Disable publishing</description>
105805 <description>Enable publishing</description>
105816 … <description>Description collection: Publish configuration for event MATCH[n]</description>
105824 <description>DPPI channel that event MATCH[n] will publish to</description>
105835 <description>Disable publishing</description>
105840 <description>Enable publishing</description>
105850 <description>Publish configuration for events</description>
105856 <description>Publish configuration for event END</description>
105864 <description>DPPI channel that event END will publish to</description>
105875 <description>Disable publishing</description>
105880 <description>Enable publishing</description>
105889 <description>Publish configuration for event READY</description>
105897 <description>DPPI channel that event READY will publish to</description>
105908 <description>Disable publishing</description>
105913 <description>Enable publishing</description>
105922 <description>Publish configuration for event BUSERROR</description>
105930 <description>DPPI channel that event BUSERROR will publish to</description>
105941 <description>Disable publishing</description>
105946 <description>Enable publishing</description>
105957 <description>Shortcuts between local events and tasks</description>
105965 <description>Shortcut between event END and task START</description>
105971 <description>Disable shortcut</description>
105976 <description>Enable shortcut</description>
105983 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows daisy-ch…
105989 <description>Disable shortcut</description>
105994 <description>Enable shortcut</description>
106001 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows daisy-ch…
106007 <description>Disable shortcut</description>
106012 <description>Enable shortcut</description>
106019 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows daisy-ch…
106025 <description>Disable shortcut</description>
106030 <description>Enable shortcut</description>
106037 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows daisy-ch…
106043 <description>Disable shortcut</description>
106048 <description>Enable shortcut</description>
106055 … <description>Shortcut between event DMA.RX.MATCH[0] and task DMA.RX.DISABLEMATCH[0]</description>
106061 <description>Disable shortcut</description>
106066 <description>Enable shortcut</description>
106073 … <description>Shortcut between event DMA.RX.MATCH[1] and task DMA.RX.DISABLEMATCH[1]</description>
106079 <description>Disable shortcut</description>
106084 <description>Enable shortcut</description>
106091 … <description>Shortcut between event DMA.RX.MATCH[2] and task DMA.RX.DISABLEMATCH[2]</description>
106097 <description>Disable shortcut</description>
106102 <description>Enable shortcut</description>
106109 … <description>Shortcut between event DMA.RX.MATCH[3] and task DMA.RX.DISABLEMATCH[3]</description>
106115 <description>Disable shortcut</description>
106120 <description>Enable shortcut</description>
106129 <description>Enable interrupt</description>
106137 <description>Write '1' to enable interrupt for event STARTED</description>
106144 <description>Read: Disabled</description>
106149 <description>Read: Enabled</description>
106157 <description>Enable</description>
106164 <description>Write '1' to enable interrupt for event STOPPED</description>
106171 <description>Read: Disabled</description>
106176 <description>Read: Enabled</description>
106184 <description>Enable</description>
106191 <description>Write '1' to enable interrupt for event END</description>
106198 <description>Read: Disabled</description>
106203 <description>Read: Enabled</description>
106211 <description>Enable</description>
106218 <description>Write '1' to enable interrupt for event DMARXEND</description>
106225 <description>Read: Disabled</description>
106230 <description>Read: Enabled</description>
106238 <description>Enable</description>
106245 <description>Write '1' to enable interrupt for event DMARXREADY</description>
106252 <description>Read: Disabled</description>
106257 <description>Read: Enabled</description>
106265 <description>Enable</description>
106272 <description>Write '1' to enable interrupt for event DMARXBUSERROR</description>
106279 <description>Read: Disabled</description>
106284 <description>Read: Enabled</description>
106292 <description>Enable</description>
106299 <description>Write '1' to enable interrupt for event DMARXMATCH[0]</description>
106306 <description>Read: Disabled</description>
106311 <description>Read: Enabled</description>
106319 <description>Enable</description>
106326 <description>Write '1' to enable interrupt for event DMARXMATCH[1]</description>
106333 <description>Read: Disabled</description>
106338 <description>Read: Enabled</description>
106346 <description>Enable</description>
106353 <description>Write '1' to enable interrupt for event DMARXMATCH[2]</description>
106360 <description>Read: Disabled</description>
106365 <description>Read: Enabled</description>
106373 <description>Enable</description>
106380 <description>Write '1' to enable interrupt for event DMARXMATCH[3]</description>
106387 <description>Read: Disabled</description>
106392 <description>Read: Enabled</description>
106400 <description>Enable</description>
106407 <description>Write '1' to enable interrupt for event DMATXEND</description>
106414 <description>Read: Disabled</description>
106419 <description>Read: Enabled</description>
106427 <description>Enable</description>
106434 <description>Write '1' to enable interrupt for event DMATXREADY</description>
106441 <description>Read: Disabled</description>
106446 <description>Read: Enabled</description>
106454 <description>Enable</description>
106461 <description>Write '1' to enable interrupt for event DMATXBUSERROR</description>
106468 <description>Read: Disabled</description>
106473 <description>Read: Enabled</description>
106481 <description>Enable</description>
106490 <description>Disable interrupt</description>
106498 <description>Write '1' to disable interrupt for event STARTED</description>
106505 <description>Read: Disabled</description>
106510 <description>Read: Enabled</description>
106518 <description>Disable</description>
106525 <description>Write '1' to disable interrupt for event STOPPED</description>
106532 <description>Read: Disabled</description>
106537 <description>Read: Enabled</description>
106545 <description>Disable</description>
106552 <description>Write '1' to disable interrupt for event END</description>
106559 <description>Read: Disabled</description>
106564 <description>Read: Enabled</description>
106572 <description>Disable</description>
106579 <description>Write '1' to disable interrupt for event DMARXEND</description>
106586 <description>Read: Disabled</description>
106591 <description>Read: Enabled</description>
106599 <description>Disable</description>
106606 <description>Write '1' to disable interrupt for event DMARXREADY</description>
106613 <description>Read: Disabled</description>
106618 <description>Read: Enabled</description>
106626 <description>Disable</description>
106633 <description>Write '1' to disable interrupt for event DMARXBUSERROR</description>
106640 <description>Read: Disabled</description>
106645 <description>Read: Enabled</description>
106653 <description>Disable</description>
106660 <description>Write '1' to disable interrupt for event DMARXMATCH[0]</description>
106667 <description>Read: Disabled</description>
106672 <description>Read: Enabled</description>
106680 <description>Disable</description>
106687 <description>Write '1' to disable interrupt for event DMARXMATCH[1]</description>
106694 <description>Read: Disabled</description>
106699 <description>Read: Enabled</description>
106707 <description>Disable</description>
106714 <description>Write '1' to disable interrupt for event DMARXMATCH[2]</description>
106721 <description>Read: Disabled</description>
106726 <description>Read: Enabled</description>
106734 <description>Disable</description>
106741 <description>Write '1' to disable interrupt for event DMARXMATCH[3]</description>
106748 <description>Read: Disabled</description>
106753 <description>Read: Enabled</description>
106761 <description>Disable</description>
106768 <description>Write '1' to disable interrupt for event DMATXEND</description>
106775 <description>Read: Disabled</description>
106780 <description>Read: Enabled</description>
106788 <description>Disable</description>
106795 <description>Write '1' to disable interrupt for event DMATXREADY</description>
106802 <description>Read: Disabled</description>
106807 <description>Read: Enabled</description>
106815 <description>Disable</description>
106822 <description>Write '1' to disable interrupt for event DMATXBUSERROR</description>
106829 <description>Read: Disabled</description>
106834 <description>Read: Enabled</description>
106842 <description>Disable</description>
106851 <description>Enable SPIM</description>
106859 <description>Enable or disable SPIM</description>
106865 <description>Disable SPIM</description>
106870 <description>Enable SPIM</description>
106879 <description>The prescaler is used to set the SPI frequency.</description>
106887 <description>Core clock to SCK divisor</description>
106895 <description>Configuration register</description>
106903 <description>Bit order</description>
106909 <description>Most significant bit shifted out first</description>
106914 <description>Least significant bit shifted out first</description>
106921 <description>Serial clock (SCK) phase</description>
106927 … <description>Sample on leading edge of clock, shift serial data on trailing edge</description>
106932 … <description>Sample on trailing edge of clock, shift serial data on leading edge</description>
106939 <description>Serial clock (SCK) polarity</description>
106945 <description>Active high</description>
106950 <description>Active low</description>
106959 <description>Unspecified</description>
106965 <description>Sample delay for input serial data on MISO</description>
106973 …description>Sample delay for input serial data on MISO. The value specifies the number of SPIM cor…
106981 …description>Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, t…
106989 …description>Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, t…
106998 <description>DCX configuration</description>
107006 …description>This register specifies the number of command bytes preceding the data bytes. The PSEL…
107014 <description>Polarity of CSN output</description>
107022 <description>Polarity of CSN output</description>
107028 <description>Active low (idle state high)</description>
107033 <description>Active high (idle state low)</description>
107042 …description>Selects which CSN is used, only one CSN can be active at one time. This register can b…
107050 <description>CSN Number.</description>
107058 …<description>Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MA…
107066 …<description>Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MA…
107074 <description>Unspecified</description>
107080 <description>Pin select for SCK</description>
107088 <description>Pin number</description>
107094 <description>Port number</description>
107100 <description>Connection</description>
107106 <description>Disconnect</description>
107111 <description>Connect</description>
107120 <description>Pin select for MOSI signal</description>
107128 <description>Pin number</description>
107134 <description>Port number</description>
107140 <description>Connection</description>
107146 <description>Disconnect</description>
107151 <description>Connect</description>
107160 <description>Pin select for MISO signal</description>
107168 <description>Pin number</description>
107174 <description>Port number</description>
107180 <description>Connection</description>
107186 <description>Disconnect</description>
107191 <description>Connect</description>
107200 <description>Pin select for DCX signal</description>
107208 <description>Pin number</description>
107214 <description>Port number</description>
107220 <description>Connection</description>
107226 <description>Disconnect</description>
107231 <description>Connect</description>
107242 <description>Description collection: Pin select for CSN</description>
107250 <description>Pin number</description>
107256 <description>Port number</description>
107262 <description>Connection</description>
107268 <description>Disconnect</description>
107273 <description>Connect</description>
107283 <description>Unspecified</description>
107289 <description>Unspecified</description>
107295 <description>RAM buffer start address</description>
107303 …<description>RAM buffer start address for this EasyDMA channel. This address is a word aligned Dat…
107311 <description>Maximum number of bytes in channel buffer</description>
107319 <description>Maximum number of bytes in channel buffer</description>
107327 …<description>Number of bytes transferred in the last transaction, updated after the END event. Als…
107335 …<description>Number of bytes transferred in the last transaction. In case of NACK error, includes …
107343 <description>Number of bytes transferred in the current transaction</description>
107351 …<description>Number of bytes transferred in the current transaction. Continuously updated.</descri…
107359 <description>EasyDMA list type</description>
107367 <description>List type</description>
107373 <description>Disable EasyDMA list</description>
107378 <description>Use array list</description>
107387 <description>Terminate the transaction if a BUSERROR event is detected.</description>
107400 <description>Disable</description>
107405 <description>Enable</description>
107414 … <description>Address of transaction that generated the last BUSERROR event.</description>
107429 … <description>Registers to control the behavior of the pattern matcher engine</description>
107435 <description>Configure individual match events</description>
107443 <description>Enable match filter 0</description>
107449 <description>Match filter disabled</description>
107454 <description>Match filter enabled</description>
107461 <description>Enable match filter 1</description>
107467 <description>Match filter disabled</description>
107472 <description>Match filter enabled</description>
107479 <description>Enable match filter 2</description>
107485 <description>Match filter disabled</description>
107490 <description>Match filter enabled</description>
107497 <description>Enable match filter 3</description>
107503 <description>Match filter disabled</description>
107508 <description>Match filter enabled</description>
107515 <description>Configure match filter 0 as one-shot or sticky</description>
107521 <description>Match filter stays enabled until disabled by task</description>
107526 … <description>Match filter stays enabled until next data word is received</description>
107533 <description>Configure match filter 1 as one-shot or sticky</description>
107539 <description>Match filter stays enabled until disabled by task</description>
107544 … <description>Match filter stays enabled until next data word is received</description>
107551 <description>Configure match filter 2 as one-shot or sticky</description>
107557 <description>Match filter stays enabled until disabled by task</description>
107562 … <description>Match filter stays enabled until next data word is received</description>
107569 <description>Configure match filter 3 as one-shot or sticky</description>
107575 <description>Match filter stays enabled until disabled by task</description>
107580 … <description>Match filter stays enabled until next data word is received</description>
107591 …<description>Description collection: The data to look for - any match will trigger the MATCH[n] ev…
107599 <description>Data to look for</description>
107609 <description>Unspecified</description>
107615 <description>RAM buffer start address</description>
107623 …<description>RAM buffer start address for this EasyDMA channel. This address is a word aligned Dat…
107631 <description>Maximum number of bytes in channel buffer</description>
107639 <description>Maximum number of bytes in channel buffer</description>
107647 …<description>Number of bytes transferred in the last transaction, updated after the END event. Als…
107655 …<description>Number of bytes transferred in the last transaction. In case of NACK error, includes …
107663 <description>Number of bytes transferred in the current transaction</description>
107671 …<description>Number of bytes transferred in the current transaction. Continuously updated.</descri…
107679 <description>EasyDMA list type</description>
107687 <description>List type</description>
107693 <description>Disable EasyDMA list</description>
107698 <description>Use array list</description>
107707 <description>Terminate the transaction if a BUSERROR event is detected.</description>
107720 <description>Disable</description>
107725 <description>Enable</description>
107734 … <description>Address of transaction that generated the last BUSERROR event.</description>
107753 <description>UART with EasyDMA 0</description>
107773 <description>Flush RX FIFO into RX buffer</description>
107781 <description>Flush RX FIFO into RX buffer</description>
107787 <description>Trigger task</description>
107796 <description>Peripheral tasks.</description>
107802 <description>Peripheral tasks.</description>
107808 …<description>Starts operation using easyDMA to load the values. See peripheral description for ope…
107816 …<description>Starts operation using easyDMA to load the values. See peripheral description for ope…
107822 <description>Trigger task</description>
107831 … <description>Stops operation using easyDMA. This does not trigger an END event.</description>
107839 … <description>Stops operation using easyDMA. This does not trigger an END event.</description>
107845 <description>Trigger task</description>
107856 …<description>Description collection: Enables the MATCH[n] event by setting the ENABLE[n] bit in th…
107864 …<description>Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register.</desc…
107870 <description>Trigger task</description>
107881 …<description>Description collection: Disables the MATCH[n] event by clearing the ENABLE[n] bit in …
107889 …<description>Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register.</de…
107895 <description>Trigger task</description>
107905 <description>Peripheral tasks.</description>
107911 …<description>Starts operation using easyDMA to load the values. See peripheral description for ope…
107919 …<description>Starts operation using easyDMA to load the values. See peripheral description for ope…
107925 <description>Trigger task</description>
107934 … <description>Stops operation using easyDMA. This does not trigger an END event.</description>
107942 … <description>Stops operation using easyDMA. This does not trigger an END event.</description>
107948 <description>Trigger task</description>
107959 <description>Subscribe configuration for task FLUSHRX</description>
107967 <description>DPPI channel that task FLUSHRX will subscribe to</description>
107978 <description>Disable subscription</description>
107983 <description>Enable subscription</description>
107992 <description>Subscribe configuration for tasks</description>
107998 <description>Subscribe configuration for tasks</description>
108004 <description>Subscribe configuration for task START</description>
108012 <description>DPPI channel that task START will subscribe to</description>
108023 <description>Disable subscription</description>
108028 <description>Enable subscription</description>
108037 <description>Subscribe configuration for task STOP</description>
108045 <description>DPPI channel that task STOP will subscribe to</description>
108056 <description>Disable subscription</description>
108061 <description>Enable subscription</description>
108072 … <description>Description collection: Subscribe configuration for task ENABLEMATCH[n]</description>
108080 <description>DPPI channel that task ENABLEMATCH[n] will subscribe to</description>
108091 <description>Disable subscription</description>
108096 <description>Enable subscription</description>
108107 …<description>Description collection: Subscribe configuration for task DISABLEMATCH[n]</description>
108115 … <description>DPPI channel that task DISABLEMATCH[n] will subscribe to</description>
108126 <description>Disable subscription</description>
108131 <description>Enable subscription</description>
108141 <description>Subscribe configuration for tasks</description>
108147 <description>Subscribe configuration for task START</description>
108155 <description>DPPI channel that task START will subscribe to</description>
108166 <description>Disable subscription</description>
108171 <description>Enable subscription</description>
108180 <description>Subscribe configuration for task STOP</description>
108188 <description>DPPI channel that task STOP will subscribe to</description>
108199 <description>Disable subscription</description>
108204 <description>Enable subscription</description>
108215 <description>CTS is activated (set low). Clear To Send.</description>
108223 <description>CTS is activated (set low). Clear To Send.</description>
108229 <description>Event not generated</description>
108234 <description>Event generated</description>
108243 <description>CTS is deactivated (set high). Not Clear To Send.</description>
108251 <description>CTS is deactivated (set high). Not Clear To Send.</description>
108257 <description>Event not generated</description>
108262 <description>Event generated</description>
108271 <description>Data sent from TXD</description>
108279 <description>Data sent from TXD</description>
108285 <description>Event not generated</description>
108290 <description>Event generated</description>
108299 … <description>Data received in RXD (but potentially not yet transferred to Data RAM)</description>
108307 … <description>Data received in RXD (but potentially not yet transferred to Data RAM)</description>
108313 <description>Event not generated</description>
108318 <description>Event generated</description>
108327 <description>Error detected</description>
108335 <description>Error detected</description>
108341 <description>Event not generated</description>
108346 <description>Event generated</description>
108355 <description>Receiver timeout</description>
108363 <description>Receiver timeout</description>
108369 <description>Event not generated</description>
108374 <description>Event generated</description>
108383 <description>Transmitter stopped</description>
108391 <description>Transmitter stopped</description>
108397 <description>Event not generated</description>
108402 <description>Event generated</description>
108411 <description>Peripheral events.</description>
108417 <description>Peripheral events.</description>
108423 <description>Generated after all MAXCNT bytes have been transferred</description>
108431 <description>Generated after all MAXCNT bytes have been transferred</description>
108437 <description>Event not generated</description>
108442 <description>Event generated</description>
108451 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
108459 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
108465 <description>Event not generated</description>
108470 <description>Event generated</description>
108479 <description>An error occured during the bus transfer.</description>
108487 <description>An error occured during the bus transfer.</description>
108493 <description>Event not generated</description>
108498 <description>Event generated</description>
108509 … <description>Description collection: Pattern match is detected on the DMA data bus.</description>
108517 <description>Pattern match is detected on the DMA data bus.</description>
108523 <description>Event not generated</description>
108528 <description>Event generated</description>
108538 <description>Peripheral events.</description>
108544 <description>Generated after all MAXCNT bytes have been transferred</description>
108552 <description>Generated after all MAXCNT bytes have been transferred</description>
108558 <description>Event not generated</description>
108563 <description>Event generated</description>
108572 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
108580 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
108586 <description>Event not generated</description>
108591 <description>Event generated</description>
108600 <description>An error occured during the bus transfer.</description>
108608 <description>An error occured during the bus transfer.</description>
108614 <description>Event not generated</description>
108619 <description>Event generated</description>
108630 <description>Timed out due to bus being idle while receiving data.</description>
108638 <description>Timed out due to bus being idle while receiving data.</description>
108644 <description>Event not generated</description>
108649 <description>Event generated</description>
108658 <description>Publish configuration for event CTS</description>
108666 <description>DPPI channel that event CTS will publish to</description>
108677 <description>Disable publishing</description>
108682 <description>Enable publishing</description>
108691 <description>Publish configuration for event NCTS</description>
108699 <description>DPPI channel that event NCTS will publish to</description>
108710 <description>Disable publishing</description>
108715 <description>Enable publishing</description>
108724 <description>Publish configuration for event TXDRDY</description>
108732 <description>DPPI channel that event TXDRDY will publish to</description>
108743 <description>Disable publishing</description>
108748 <description>Enable publishing</description>
108757 <description>Publish configuration for event RXDRDY</description>
108765 <description>DPPI channel that event RXDRDY will publish to</description>
108776 <description>Disable publishing</description>
108781 <description>Enable publishing</description>
108790 <description>Publish configuration for event ERROR</description>
108798 <description>DPPI channel that event ERROR will publish to</description>
108809 <description>Disable publishing</description>
108814 <description>Enable publishing</description>
108823 <description>Publish configuration for event RXTO</description>
108831 <description>DPPI channel that event RXTO will publish to</description>
108842 <description>Disable publishing</description>
108847 <description>Enable publishing</description>
108856 <description>Publish configuration for event TXSTOPPED</description>
108864 <description>DPPI channel that event TXSTOPPED will publish to</description>
108875 <description>Disable publishing</description>
108880 <description>Enable publishing</description>
108889 <description>Publish configuration for events</description>
108895 <description>Publish configuration for events</description>
108901 <description>Publish configuration for event END</description>
108909 <description>DPPI channel that event END will publish to</description>
108920 <description>Disable publishing</description>
108925 <description>Enable publishing</description>
108934 <description>Publish configuration for event READY</description>
108942 <description>DPPI channel that event READY will publish to</description>
108953 <description>Disable publishing</description>
108958 <description>Enable publishing</description>
108967 <description>Publish configuration for event BUSERROR</description>
108975 <description>DPPI channel that event BUSERROR will publish to</description>
108986 <description>Disable publishing</description>
108991 <description>Enable publishing</description>
109002 … <description>Description collection: Publish configuration for event MATCH[n]</description>
109010 <description>DPPI channel that event MATCH[n] will publish to</description>
109021 <description>Disable publishing</description>
109026 <description>Enable publishing</description>
109036 <description>Publish configuration for events</description>
109042 <description>Publish configuration for event END</description>
109050 <description>DPPI channel that event END will publish to</description>
109061 <description>Disable publishing</description>
109066 <description>Enable publishing</description>
109075 <description>Publish configuration for event READY</description>
109083 <description>DPPI channel that event READY will publish to</description>
109094 <description>Disable publishing</description>
109099 <description>Enable publishing</description>
109108 <description>Publish configuration for event BUSERROR</description>
109116 <description>DPPI channel that event BUSERROR will publish to</description>
109127 <description>Disable publishing</description>
109132 <description>Enable publishing</description>
109143 <description>Publish configuration for event FRAMETIMEOUT</description>
109151 <description>DPPI channel that event FRAMETIMEOUT will publish to</description>
109162 <description>Disable publishing</description>
109167 <description>Enable publishing</description>
109176 <description>Shortcuts between local events and tasks</description>
109184 <description>Shortcut between event DMA.RX.END and task DMA.RX.START</description>
109190 <description>Disable shortcut</description>
109195 <description>Enable shortcut</description>
109202 <description>Shortcut between event DMA.RX.END and task DMA.RX.STOP</description>
109208 <description>Disable shortcut</description>
109213 <description>Enable shortcut</description>
109220 <description>Shortcut between event DMA.TX.END and task DMA.TX.STOP</description>
109226 <description>Disable shortcut</description>
109231 <description>Enable shortcut</description>
109238 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows daisy-ch…
109244 <description>Disable shortcut</description>
109249 <description>Enable shortcut</description>
109256 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows daisy-ch…
109262 <description>Disable shortcut</description>
109267 <description>Enable shortcut</description>
109274 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows daisy-ch…
109280 <description>Disable shortcut</description>
109285 <description>Enable shortcut</description>
109292 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows daisy-ch…
109298 <description>Disable shortcut</description>
109303 <description>Enable shortcut</description>
109310 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
109316 <description>Disable shortcut</description>
109321 <description>Enable shortcut</description>
109328 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
109334 <description>Disable shortcut</description>
109339 <description>Enable shortcut</description>
109346 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
109352 <description>Disable shortcut</description>
109357 <description>Enable shortcut</description>
109364 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
109370 <description>Disable shortcut</description>
109375 <description>Enable shortcut</description>
109382 <description>Shortcut between event FRAMETIMEOUT and task DMA.RX.STOP</description>
109388 <description>Disable shortcut</description>
109393 <description>Enable shortcut</description>
109402 <description>Enable or disable interrupt</description>
109410 <description>Enable or disable interrupt for event CTS</description>
109416 <description>Disable</description>
109421 <description>Enable</description>
109428 <description>Enable or disable interrupt for event NCTS</description>
109434 <description>Disable</description>
109439 <description>Enable</description>
109446 <description>Enable or disable interrupt for event TXDRDY</description>
109452 <description>Disable</description>
109457 <description>Enable</description>
109464 <description>Enable or disable interrupt for event RXDRDY</description>
109470 <description>Disable</description>
109475 <description>Enable</description>
109482 <description>Enable or disable interrupt for event ERROR</description>
109488 <description>Disable</description>
109493 <description>Enable</description>
109500 <description>Enable or disable interrupt for event RXTO</description>
109506 <description>Disable</description>
109511 <description>Enable</description>
109518 <description>Enable or disable interrupt for event TXSTOPPED</description>
109524 <description>Disable</description>
109529 <description>Enable</description>
109536 <description>Enable or disable interrupt for event DMARXEND</description>
109542 <description>Disable</description>
109547 <description>Enable</description>
109554 <description>Enable or disable interrupt for event DMARXREADY</description>
109560 <description>Disable</description>
109565 <description>Enable</description>
109572 <description>Enable or disable interrupt for event DMARXBUSERROR</description>
109578 <description>Disable</description>
109583 <description>Enable</description>
109590 <description>Enable or disable interrupt for event DMARXMATCH[0]</description>
109596 <description>Disable</description>
109601 <description>Enable</description>
109608 <description>Enable or disable interrupt for event DMARXMATCH[1]</description>
109614 <description>Disable</description>
109619 <description>Enable</description>
109626 <description>Enable or disable interrupt for event DMARXMATCH[2]</description>
109632 <description>Disable</description>
109637 <description>Enable</description>
109644 <description>Enable or disable interrupt for event DMARXMATCH[3]</description>
109650 <description>Disable</description>
109655 <description>Enable</description>
109662 <description>Enable or disable interrupt for event DMATXEND</description>
109668 <description>Disable</description>
109673 <description>Enable</description>
109680 <description>Enable or disable interrupt for event DMATXREADY</description>
109686 <description>Disable</description>
109691 <description>Enable</description>
109698 <description>Enable or disable interrupt for event DMATXBUSERROR</description>
109704 <description>Disable</description>
109709 <description>Enable</description>
109716 <description>Enable or disable interrupt for event FRAMETIMEOUT</description>
109722 <description>Disable</description>
109727 <description>Enable</description>
109736 <description>Enable interrupt</description>
109744 <description>Write '1' to enable interrupt for event CTS</description>
109751 <description>Read: Disabled</description>
109756 <description>Read: Enabled</description>
109764 <description>Enable</description>
109771 <description>Write '1' to enable interrupt for event NCTS</description>
109778 <description>Read: Disabled</description>
109783 <description>Read: Enabled</description>
109791 <description>Enable</description>
109798 <description>Write '1' to enable interrupt for event TXDRDY</description>
109805 <description>Read: Disabled</description>
109810 <description>Read: Enabled</description>
109818 <description>Enable</description>
109825 <description>Write '1' to enable interrupt for event RXDRDY</description>
109832 <description>Read: Disabled</description>
109837 <description>Read: Enabled</description>
109845 <description>Enable</description>
109852 <description>Write '1' to enable interrupt for event ERROR</description>
109859 <description>Read: Disabled</description>
109864 <description>Read: Enabled</description>
109872 <description>Enable</description>
109879 <description>Write '1' to enable interrupt for event RXTO</description>
109886 <description>Read: Disabled</description>
109891 <description>Read: Enabled</description>
109899 <description>Enable</description>
109906 <description>Write '1' to enable interrupt for event TXSTOPPED</description>
109913 <description>Read: Disabled</description>
109918 <description>Read: Enabled</description>
109926 <description>Enable</description>
109933 <description>Write '1' to enable interrupt for event DMARXEND</description>
109940 <description>Read: Disabled</description>
109945 <description>Read: Enabled</description>
109953 <description>Enable</description>
109960 <description>Write '1' to enable interrupt for event DMARXREADY</description>
109967 <description>Read: Disabled</description>
109972 <description>Read: Enabled</description>
109980 <description>Enable</description>
109987 <description>Write '1' to enable interrupt for event DMARXBUSERROR</description>
109994 <description>Read: Disabled</description>
109999 <description>Read: Enabled</description>
110007 <description>Enable</description>
110014 <description>Write '1' to enable interrupt for event DMARXMATCH[0]</description>
110021 <description>Read: Disabled</description>
110026 <description>Read: Enabled</description>
110034 <description>Enable</description>
110041 <description>Write '1' to enable interrupt for event DMARXMATCH[1]</description>
110048 <description>Read: Disabled</description>
110053 <description>Read: Enabled</description>
110061 <description>Enable</description>
110068 <description>Write '1' to enable interrupt for event DMARXMATCH[2]</description>
110075 <description>Read: Disabled</description>
110080 <description>Read: Enabled</description>
110088 <description>Enable</description>
110095 <description>Write '1' to enable interrupt for event DMARXMATCH[3]</description>
110102 <description>Read: Disabled</description>
110107 <description>Read: Enabled</description>
110115 <description>Enable</description>
110122 <description>Write '1' to enable interrupt for event DMATXEND</description>
110129 <description>Read: Disabled</description>
110134 <description>Read: Enabled</description>
110142 <description>Enable</description>
110149 <description>Write '1' to enable interrupt for event DMATXREADY</description>
110156 <description>Read: Disabled</description>
110161 <description>Read: Enabled</description>
110169 <description>Enable</description>
110176 <description>Write '1' to enable interrupt for event DMATXBUSERROR</description>
110183 <description>Read: Disabled</description>
110188 <description>Read: Enabled</description>
110196 <description>Enable</description>
110203 <description>Write '1' to enable interrupt for event FRAMETIMEOUT</description>
110210 <description>Read: Disabled</description>
110215 <description>Read: Enabled</description>
110223 <description>Enable</description>
110232 <description>Disable interrupt</description>
110240 <description>Write '1' to disable interrupt for event CTS</description>
110247 <description>Read: Disabled</description>
110252 <description>Read: Enabled</description>
110260 <description>Disable</description>
110267 <description>Write '1' to disable interrupt for event NCTS</description>
110274 <description>Read: Disabled</description>
110279 <description>Read: Enabled</description>
110287 <description>Disable</description>
110294 <description>Write '1' to disable interrupt for event TXDRDY</description>
110301 <description>Read: Disabled</description>
110306 <description>Read: Enabled</description>
110314 <description>Disable</description>
110321 <description>Write '1' to disable interrupt for event RXDRDY</description>
110328 <description>Read: Disabled</description>
110333 <description>Read: Enabled</description>
110341 <description>Disable</description>
110348 <description>Write '1' to disable interrupt for event ERROR</description>
110355 <description>Read: Disabled</description>
110360 <description>Read: Enabled</description>
110368 <description>Disable</description>
110375 <description>Write '1' to disable interrupt for event RXTO</description>
110382 <description>Read: Disabled</description>
110387 <description>Read: Enabled</description>
110395 <description>Disable</description>
110402 <description>Write '1' to disable interrupt for event TXSTOPPED</description>
110409 <description>Read: Disabled</description>
110414 <description>Read: Enabled</description>
110422 <description>Disable</description>
110429 <description>Write '1' to disable interrupt for event DMARXEND</description>
110436 <description>Read: Disabled</description>
110441 <description>Read: Enabled</description>
110449 <description>Disable</description>
110456 <description>Write '1' to disable interrupt for event DMARXREADY</description>
110463 <description>Read: Disabled</description>
110468 <description>Read: Enabled</description>
110476 <description>Disable</description>
110483 <description>Write '1' to disable interrupt for event DMARXBUSERROR</description>
110490 <description>Read: Disabled</description>
110495 <description>Read: Enabled</description>
110503 <description>Disable</description>
110510 <description>Write '1' to disable interrupt for event DMARXMATCH[0]</description>
110517 <description>Read: Disabled</description>
110522 <description>Read: Enabled</description>
110530 <description>Disable</description>
110537 <description>Write '1' to disable interrupt for event DMARXMATCH[1]</description>
110544 <description>Read: Disabled</description>
110549 <description>Read: Enabled</description>
110557 <description>Disable</description>
110564 <description>Write '1' to disable interrupt for event DMARXMATCH[2]</description>
110571 <description>Read: Disabled</description>
110576 <description>Read: Enabled</description>
110584 <description>Disable</description>
110591 <description>Write '1' to disable interrupt for event DMARXMATCH[3]</description>
110598 <description>Read: Disabled</description>
110603 <description>Read: Enabled</description>
110611 <description>Disable</description>
110618 <description>Write '1' to disable interrupt for event DMATXEND</description>
110625 <description>Read: Disabled</description>
110630 <description>Read: Enabled</description>
110638 <description>Disable</description>
110645 <description>Write '1' to disable interrupt for event DMATXREADY</description>
110652 <description>Read: Disabled</description>
110657 <description>Read: Enabled</description>
110665 <description>Disable</description>
110672 <description>Write '1' to disable interrupt for event DMATXBUSERROR</description>
110679 <description>Read: Disabled</description>
110684 <description>Read: Enabled</description>
110692 <description>Disable</description>
110699 <description>Write '1' to disable interrupt for event FRAMETIMEOUT</description>
110706 <description>Read: Disabled</description>
110711 <description>Read: Enabled</description>
110719 <description>Disable</description>
110728 <description>Error source</description>
110737 <description>Overrun error</description>
110744 <description>Read: error not present</description>
110749 <description>Read: error present</description>
110756 <description>Parity error</description>
110763 <description>Read: error not present</description>
110768 <description>Read: error present</description>
110775 <description>Framing error occurred</description>
110782 <description>Read: error not present</description>
110787 <description>Read: error present</description>
110794 <description>Break condition</description>
110801 <description>Read: error not present</description>
110806 <description>Read: error present</description>
110815 <description>Enable UART</description>
110823 <description>Enable or disable UARTE</description>
110829 <description>Disable UARTE</description>
110834 <description>Enable UARTE</description>
110843 <description>Baud rate. Accuracy depends on the HFCLK source selected.</description>
110851 <description>Baud rate</description>
110857 <description>1200 baud (actual rate: 1205)</description>
110862 <description>2400 baud (actual rate: 2396)</description>
110867 <description>4800 baud (actual rate: 4808)</description>
110872 <description>9600 baud (actual rate: 9598)</description>
110877 <description>14400 baud (actual rate: 14401)</description>
110882 <description>19200 baud (actual rate: 19208)</description>
110887 <description>28800 baud (actual rate: 28777)</description>
110892 <description>31250 baud</description>
110897 <description>38400 baud (actual rate: 38369)</description>
110902 <description>56000 baud (actual rate: 55944)</description>
110907 <description>57600 baud (actual rate: 57554)</description>
110912 <description>76800 baud (actual rate: 76923)</description>
110917 <description>115200 baud (actual rate: 115108)</description>
110922 <description>230400 baud (actual rate: 231884)</description>
110927 <description>250000 baud</description>
110932 <description>460800 baud (actual rate: 457143)</description>
110937 <description>921600 baud (actual rate: 941176)</description>
110942 <description>1 megabaud</description>
110951 …<description>Configuration of parity, hardware flow control, framesize, and packet timeout.</descr…
110959 <description>Hardware flow control</description>
110965 <description>Disabled</description>
110970 <description>Enabled</description>
110977 <description>Parity</description>
110983 <description>Exclude parity bit</description>
110988 <description>Include even parity bit</description>
110995 <description>Stop bits</description>
111001 <description>One stop bit</description>
111006 <description>Two stop bits</description>
111013 <description>Even or odd parity type</description>
111019 <description>Even parity</description>
111024 <description>Odd parity</description>
111031 <description>Set the data frame size</description>
111037 … <description>9 bit data frame size. 9th bit is treated as address bit.</description>
111042 <description>8 bit data frame size.</description>
111047 <description>7 bit data frame size.</description>
111052 <description>6 bit data frame size.</description>
111057 <description>5 bit data frame size.</description>
111062 <description>4 bit data frame size.</description>
111069 …<description>Select if data is trimmed from MSB or LSB end when the data frame size is less than 8…
111075 <description>Data is trimmed from MSB end.</description>
111080 <description>Data is trimmed from LSB end.</description>
111087 <description>Enable packet timeout.</description>
111093 <description>Packet timeout is disabled.</description>
111098 <description>Packet timeout is enabled.</description>
111107 … <description>Set the address of the UARTE for RX when used in 9 bit data frame mode.</description>
111115 <description>Set address</description>
111123 … <description>Set the number of UARTE bits to count before triggering packet timeout.</description>
111131 <description>Number of UARTE bits before timeout.</description>
111139 <description>Unspecified</description>
111145 <description>Pin select for TXD signal</description>
111153 <description>Pin number</description>
111159 <description>Port number</description>
111165 <description>Connection</description>
111171 <description>Disconnect</description>
111176 <description>Connect</description>
111185 <description>Pin select for CTS signal</description>
111193 <description>Pin number</description>
111199 <description>Port number</description>
111205 <description>Connection</description>
111211 <description>Disconnect</description>
111216 <description>Connect</description>
111225 <description>Pin select for RXD signal</description>
111233 <description>Pin number</description>
111239 <description>Port number</description>
111245 <description>Connection</description>
111251 <description>Disconnect</description>
111256 <description>Connect</description>
111265 <description>Pin select for RTS signal</description>
111273 <description>Pin number</description>
111279 <description>Port number</description>
111285 <description>Connection</description>
111291 <description>Disconnect</description>
111296 <description>Connect</description>
111306 <description>Unspecified</description>
111312 <description>Unspecified</description>
111318 <description>RAM buffer start address</description>
111326 …<description>RAM buffer start address for this EasyDMA channel. This address is a word aligned Dat…
111334 <description>Maximum number of bytes in channel buffer</description>
111342 <description>Maximum number of bytes in channel buffer</description>
111350 …<description>Number of bytes transferred in the last transaction, updated after the END event. Als…
111358 …<description>Number of bytes transferred in the last transaction. In case of NACK error, includes …
111366 <description>Number of bytes transferred in the current transaction</description>
111374 …<description>Number of bytes transferred in the current transaction. Continuously updated.</descri…
111382 <description>EasyDMA list type</description>
111390 <description>List type</description>
111396 <description>Disable EasyDMA list</description>
111401 <description>Use array list</description>
111410 <description>Terminate the transaction if a BUSERROR event is detected.</description>
111423 <description>Disable</description>
111428 <description>Enable</description>
111437 … <description>Address of transaction that generated the last BUSERROR event.</description>
111452 … <description>Registers to control the behavior of the pattern matcher engine</description>
111458 <description>Configure individual match events</description>
111466 <description>Enable match filter 0</description>
111472 <description>Match filter disabled</description>
111477 <description>Match filter enabled</description>
111484 <description>Enable match filter 1</description>
111490 <description>Match filter disabled</description>
111495 <description>Match filter enabled</description>
111502 <description>Enable match filter 2</description>
111508 <description>Match filter disabled</description>
111513 <description>Match filter enabled</description>
111520 <description>Enable match filter 3</description>
111526 <description>Match filter disabled</description>
111531 <description>Match filter enabled</description>
111538 <description>Configure match filter 0 as one-shot or sticky</description>
111544 <description>Match filter stays enabled until disabled by task</description>
111549 … <description>Match filter stays enabled until next data word is received</description>
111556 <description>Configure match filter 1 as one-shot or sticky</description>
111562 <description>Match filter stays enabled until disabled by task</description>
111567 … <description>Match filter stays enabled until next data word is received</description>
111574 <description>Configure match filter 2 as one-shot or sticky</description>
111580 <description>Match filter stays enabled until disabled by task</description>
111585 … <description>Match filter stays enabled until next data word is received</description>
111592 <description>Configure match filter 3 as one-shot or sticky</description>
111598 <description>Match filter stays enabled until disabled by task</description>
111603 … <description>Match filter stays enabled until next data word is received</description>
111614 …<description>Description collection: The data to look for - any match will trigger the MATCH[n] ev…
111622 <description>Data to look for</description>
111632 <description>Unspecified</description>
111638 <description>RAM buffer start address</description>
111646 …<description>RAM buffer start address for this EasyDMA channel. This address is a word aligned Dat…
111654 <description>Maximum number of bytes in channel buffer</description>
111662 <description>Maximum number of bytes in channel buffer</description>
111670 …<description>Number of bytes transferred in the last transaction, updated after the END event. Als…
111678 …<description>Number of bytes transferred in the last transaction. In case of NACK error, includes …
111686 <description>Number of bytes transferred in the current transaction</description>
111694 …<description>Number of bytes transferred in the current transaction. Continuously updated.</descri…
111702 <description>EasyDMA list type</description>
111710 <description>List type</description>
111716 <description>Disable EasyDMA list</description>
111721 <description>Use array list</description>
111730 <description>Terminate the transaction if a BUSERROR event is detected.</description>
111743 <description>Disable</description>
111748 <description>Enable</description>
111757 … <description>Address of transaction that generated the last BUSERROR event.</description>
111776 <description>Serial Peripheral Interface Master with EasyDMA 1</description>
111787 <description>VPR peripheral registers 1</description>
111798 <description>IPCT APB registers 1</description>
111810 <description>Distributed programmable peripheral interconnect controller 1</description>
111818 <description>MUTEX 1</description>
111825 <description>Real-time counter 0</description>
111844 <description>Start RTC counter</description>
111852 <description>Start RTC counter</description>
111858 <description>Trigger task</description>
111867 <description>Stop RTC counter</description>
111875 <description>Stop RTC counter</description>
111881 <description>Trigger task</description>
111890 <description>Clear RTC counter</description>
111898 <description>Clear RTC counter</description>
111904 <description>Trigger task</description>
111913 <description>Set counter to 0xFFFFF0</description>
111921 <description>Set counter to 0xFFFFF0</description>
111927 <description>Trigger task</description>
111938 <description>Description collection: Capture RTC counter to CC[n] register</description>
111946 <description>Capture RTC counter to CC[n] register</description>
111952 <description>Trigger task</description>
111961 <description>Subscribe configuration for task START</description>
111969 <description>DPPI channel that task START will subscribe to</description>
111980 <description>Disable subscription</description>
111985 <description>Enable subscription</description>
111994 <description>Subscribe configuration for task STOP</description>
112002 <description>DPPI channel that task STOP will subscribe to</description>
112013 <description>Disable subscription</description>
112018 <description>Enable subscription</description>
112027 <description>Subscribe configuration for task CLEAR</description>
112035 <description>DPPI channel that task CLEAR will subscribe to</description>
112046 <description>Disable subscription</description>
112051 <description>Enable subscription</description>
112060 <description>Subscribe configuration for task TRIGOVRFLW</description>
112068 <description>DPPI channel that task TRIGOVRFLW will subscribe to</description>
112079 <description>Disable subscription</description>
112084 <description>Enable subscription</description>
112095 … <description>Description collection: Subscribe configuration for task CAPTURE[n]</description>
112103 <description>DPPI channel that task CAPTURE[n] will subscribe to</description>
112114 <description>Disable subscription</description>
112119 <description>Enable subscription</description>
112128 <description>Event on counter increment</description>
112136 <description>Event on counter increment</description>
112142 <description>Event not generated</description>
112147 <description>Event generated</description>
112156 <description>Event on counter overflow</description>
112164 <description>Event on counter overflow</description>
112170 <description>Event not generated</description>
112175 <description>Event generated</description>
112186 <description>Description collection: Compare event on CC[n] match</description>
112194 <description>Compare event on CC[n] match</description>
112200 <description>Event not generated</description>
112205 <description>Event generated</description>
112214 <description>Publish configuration for event TICK</description>
112222 <description>DPPI channel that event TICK will publish to</description>
112233 <description>Disable publishing</description>
112238 <description>Enable publishing</description>
112247 <description>Publish configuration for event OVRFLW</description>
112255 <description>DPPI channel that event OVRFLW will publish to</description>
112266 <description>Disable publishing</description>
112271 <description>Enable publishing</description>
112282 … <description>Description collection: Publish configuration for event COMPARE[n]</description>
112290 <description>DPPI channel that event COMPARE[n] will publish to</description>
112301 <description>Disable publishing</description>
112306 <description>Enable publishing</description>
112315 <description>Shortcuts between local events and tasks</description>
112323 <description>Shortcut between event COMPARE[0] and task CLEAR</description>
112329 <description>Disable shortcut</description>
112334 <description>Enable shortcut</description>
112341 <description>Shortcut between event COMPARE[1] and task CLEAR</description>
112347 <description>Disable shortcut</description>
112352 <description>Enable shortcut</description>
112359 <description>Shortcut between event COMPARE[2] and task CLEAR</description>
112365 <description>Disable shortcut</description>
112370 <description>Enable shortcut</description>
112377 <description>Shortcut between event COMPARE[3] and task CLEAR</description>
112383 <description>Disable shortcut</description>
112388 <description>Enable shortcut</description>
112395 <description>Shortcut between event COMPARE[4] and task CLEAR</description>
112401 <description>Disable shortcut</description>
112406 <description>Enable shortcut</description>
112413 <description>Shortcut between event COMPARE[5] and task CLEAR</description>
112419 <description>Disable shortcut</description>
112424 <description>Enable shortcut</description>
112431 <description>Shortcut between event COMPARE[6] and task CLEAR</description>
112437 <description>Disable shortcut</description>
112442 <description>Enable shortcut</description>
112449 <description>Shortcut between event COMPARE[7] and task CLEAR</description>
112455 <description>Disable shortcut</description>
112460 <description>Enable shortcut</description>
112469 <description>Enable interrupt</description>
112477 <description>Write '1' to enable interrupt for event TICK</description>
112484 <description>Read: Disabled</description>
112489 <description>Read: Enabled</description>
112497 <description>Enable</description>
112504 <description>Write '1' to enable interrupt for event OVRFLW</description>
112511 <description>Read: Disabled</description>
112516 <description>Read: Enabled</description>
112524 <description>Enable</description>
112531 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
112538 <description>Read: Disabled</description>
112543 <description>Read: Enabled</description>
112551 <description>Enable</description>
112558 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
112565 <description>Read: Disabled</description>
112570 <description>Read: Enabled</description>
112578 <description>Enable</description>
112585 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
112592 <description>Read: Disabled</description>
112597 <description>Read: Enabled</description>
112605 <description>Enable</description>
112612 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
112619 <description>Read: Disabled</description>
112624 <description>Read: Enabled</description>
112632 <description>Enable</description>
112639 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
112646 <description>Read: Disabled</description>
112651 <description>Read: Enabled</description>
112659 <description>Enable</description>
112666 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
112673 <description>Read: Disabled</description>
112678 <description>Read: Enabled</description>
112686 <description>Enable</description>
112693 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
112700 <description>Read: Disabled</description>
112705 <description>Read: Enabled</description>
112713 <description>Enable</description>
112720 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
112727 <description>Read: Disabled</description>
112732 <description>Read: Enabled</description>
112740 <description>Enable</description>
112749 <description>Disable interrupt</description>
112757 <description>Write '1' to disable interrupt for event TICK</description>
112764 <description>Read: Disabled</description>
112769 <description>Read: Enabled</description>
112777 <description>Disable</description>
112784 <description>Write '1' to disable interrupt for event OVRFLW</description>
112791 <description>Read: Disabled</description>
112796 <description>Read: Enabled</description>
112804 <description>Disable</description>
112811 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
112818 <description>Read: Disabled</description>
112823 <description>Read: Enabled</description>
112831 <description>Disable</description>
112838 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
112845 <description>Read: Disabled</description>
112850 <description>Read: Enabled</description>
112858 <description>Disable</description>
112865 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
112872 <description>Read: Disabled</description>
112877 <description>Read: Enabled</description>
112885 <description>Disable</description>
112892 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
112899 <description>Read: Disabled</description>
112904 <description>Read: Enabled</description>
112912 <description>Disable</description>
112919 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
112926 <description>Read: Disabled</description>
112931 <description>Read: Enabled</description>
112939 <description>Disable</description>
112946 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
112953 <description>Read: Disabled</description>
112958 <description>Read: Enabled</description>
112966 <description>Disable</description>
112973 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
112980 <description>Read: Disabled</description>
112985 <description>Read: Enabled</description>
112993 <description>Disable</description>
113000 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
113007 <description>Read: Disabled</description>
113012 <description>Read: Enabled</description>
113020 <description>Disable</description>
113029 <description>Enable or disable event routing</description>
113037 <description>Enable or disable event routing for event TICK</description>
113043 <description>Disable</description>
113048 <description>Enable</description>
113055 <description>Enable or disable event routing for event OVRFLW</description>
113061 <description>Disable</description>
113066 <description>Enable</description>
113073 <description>Enable or disable event routing for event COMPARE[0]</description>
113079 <description>Disable</description>
113084 <description>Enable</description>
113091 <description>Enable or disable event routing for event COMPARE[1]</description>
113097 <description>Disable</description>
113102 <description>Enable</description>
113109 <description>Enable or disable event routing for event COMPARE[2]</description>
113115 <description>Disable</description>
113120 <description>Enable</description>
113127 <description>Enable or disable event routing for event COMPARE[3]</description>
113133 <description>Disable</description>
113138 <description>Enable</description>
113145 <description>Enable or disable event routing for event COMPARE[4]</description>
113151 <description>Disable</description>
113156 <description>Enable</description>
113163 <description>Enable or disable event routing for event COMPARE[5]</description>
113169 <description>Disable</description>
113174 <description>Enable</description>
113181 <description>Enable or disable event routing for event COMPARE[6]</description>
113187 <description>Disable</description>
113192 <description>Enable</description>
113199 <description>Enable or disable event routing for event COMPARE[7]</description>
113205 <description>Disable</description>
113210 <description>Enable</description>
113219 <description>Enable event routing</description>
113227 <description>Write '1' to enable event routing for event TICK</description>
113234 <description>Read: Disabled</description>
113239 <description>Read: Enabled</description>
113247 <description>Enable</description>
113254 <description>Write '1' to enable event routing for event OVRFLW</description>
113261 <description>Read: Disabled</description>
113266 <description>Read: Enabled</description>
113274 <description>Enable</description>
113281 <description>Write '1' to enable event routing for event COMPARE[0]</description>
113288 <description>Read: Disabled</description>
113293 <description>Read: Enabled</description>
113301 <description>Enable</description>
113308 <description>Write '1' to enable event routing for event COMPARE[1]</description>
113315 <description>Read: Disabled</description>
113320 <description>Read: Enabled</description>
113328 <description>Enable</description>
113335 <description>Write '1' to enable event routing for event COMPARE[2]</description>
113342 <description>Read: Disabled</description>
113347 <description>Read: Enabled</description>
113355 <description>Enable</description>
113362 <description>Write '1' to enable event routing for event COMPARE[3]</description>
113369 <description>Read: Disabled</description>
113374 <description>Read: Enabled</description>
113382 <description>Enable</description>
113389 <description>Write '1' to enable event routing for event COMPARE[4]</description>
113396 <description>Read: Disabled</description>
113401 <description>Read: Enabled</description>
113409 <description>Enable</description>
113416 <description>Write '1' to enable event routing for event COMPARE[5]</description>
113423 <description>Read: Disabled</description>
113428 <description>Read: Enabled</description>
113436 <description>Enable</description>
113443 <description>Write '1' to enable event routing for event COMPARE[6]</description>
113450 <description>Read: Disabled</description>
113455 <description>Read: Enabled</description>
113463 <description>Enable</description>
113470 <description>Write '1' to enable event routing for event COMPARE[7]</description>
113477 <description>Read: Disabled</description>
113482 <description>Read: Enabled</description>
113490 <description>Enable</description>
113499 <description>Disable event routing</description>
113507 <description>Write '1' to disable event routing for event TICK</description>
113514 <description>Read: Disabled</description>
113519 <description>Read: Enabled</description>
113527 <description>Disable</description>
113534 <description>Write '1' to disable event routing for event OVRFLW</description>
113541 <description>Read: Disabled</description>
113546 <description>Read: Enabled</description>
113554 <description>Disable</description>
113561 <description>Write '1' to disable event routing for event COMPARE[0]</description>
113568 <description>Read: Disabled</description>
113573 <description>Read: Enabled</description>
113581 <description>Disable</description>
113588 <description>Write '1' to disable event routing for event COMPARE[1]</description>
113595 <description>Read: Disabled</description>
113600 <description>Read: Enabled</description>
113608 <description>Disable</description>
113615 <description>Write '1' to disable event routing for event COMPARE[2]</description>
113622 <description>Read: Disabled</description>
113627 <description>Read: Enabled</description>
113635 <description>Disable</description>
113642 <description>Write '1' to disable event routing for event COMPARE[3]</description>
113649 <description>Read: Disabled</description>
113654 <description>Read: Enabled</description>
113662 <description>Disable</description>
113669 <description>Write '1' to disable event routing for event COMPARE[4]</description>
113676 <description>Read: Disabled</description>
113681 <description>Read: Enabled</description>
113689 <description>Disable</description>
113696 <description>Write '1' to disable event routing for event COMPARE[5]</description>
113703 <description>Read: Disabled</description>
113708 <description>Read: Enabled</description>
113716 <description>Disable</description>
113723 <description>Write '1' to disable event routing for event COMPARE[6]</description>
113730 <description>Read: Disabled</description>
113735 <description>Read: Enabled</description>
113743 <description>Disable</description>
113750 <description>Write '1' to disable event routing for event COMPARE[7]</description>
113757 <description>Read: Disabled</description>
113762 <description>Read: Enabled</description>
113770 <description>Disable</description>
113779 <description>Current counter value</description>
113787 <description>Counter value</description>
113795 …<description>12-bit prescaler for counter frequency (32768 / (PRESCALER + 1)). Must be written whe…
113803 <description>Prescaler value</description>
113813 <description>Description collection: Compare register n</description>
113821 <description>Compare value</description>
113831 <description>Real-time counter 1</description>
113842 <description>Watchdog Timer 0</description>
113861 <description>Start WDT</description>
113869 <description>Start WDT</description>
113875 <description>Trigger task</description>
113884 <description>Stop WDT</description>
113892 <description>Stop WDT</description>
113898 <description>Trigger task</description>
113907 <description>Subscribe configuration for task START</description>
113915 <description>DPPI channel that task START will subscribe to</description>
113926 <description>Disable subscription</description>
113931 <description>Enable subscription</description>
113940 <description>Subscribe configuration for task STOP</description>
113948 <description>DPPI channel that task STOP will subscribe to</description>
113959 <description>Disable subscription</description>
113964 <description>Enable subscription</description>
113973 <description>Watchdog timeout</description>
113981 <description>Watchdog timeout</description>
113987 <description>Event not generated</description>
113992 <description>Event generated</description>
114001 <description>Watchdog stopped</description>
114009 <description>Watchdog stopped</description>
114015 <description>Event not generated</description>
114020 <description>Event generated</description>
114029 <description>Publish configuration for event TIMEOUT</description>
114037 <description>DPPI channel that event TIMEOUT will publish to</description>
114048 <description>Disable publishing</description>
114053 <description>Enable publishing</description>
114062 <description>Publish configuration for event STOPPED</description>
114070 <description>DPPI channel that event STOPPED will publish to</description>
114081 <description>Disable publishing</description>
114086 <description>Enable publishing</description>
114095 <description>Enable interrupt</description>
114103 <description>Write '1' to enable interrupt for event TIMEOUT</description>
114110 <description>Read: Disabled</description>
114115 <description>Read: Enabled</description>
114123 <description>Enable</description>
114130 <description>Write '1' to enable interrupt for event STOPPED</description>
114137 <description>Read: Disabled</description>
114142 <description>Read: Enabled</description>
114150 <description>Enable</description>
114159 <description>Disable interrupt</description>
114167 <description>Write '1' to disable interrupt for event TIMEOUT</description>
114174 <description>Read: Disabled</description>
114179 <description>Read: Enabled</description>
114187 <description>Disable</description>
114194 <description>Write '1' to disable interrupt for event STOPPED</description>
114201 <description>Read: Disabled</description>
114206 <description>Read: Enabled</description>
114214 <description>Disable</description>
114223 <description>Enable interrupt</description>
114231 <description>Write '1' to enable interrupt for event TIMEOUT</description>
114238 <description>Read: Disabled</description>
114243 <description>Read: Enabled</description>
114251 <description>Enable</description>
114258 <description>Write '1' to enable interrupt for event STOPPED</description>
114265 <description>Read: Disabled</description>
114270 <description>Read: Enabled</description>
114278 <description>Enable</description>
114287 <description>Disable interrupt</description>
114295 <description>Write '1' to disable interrupt for event TIMEOUT</description>
114302 <description>Read: Disabled</description>
114307 <description>Read: Enabled</description>
114315 <description>Disable</description>
114322 <description>Write '1' to disable interrupt for event STOPPED</description>
114329 <description>Read: Disabled</description>
114334 <description>Read: Enabled</description>
114342 <description>Disable</description>
114351 <description>Run status</description>
114359 <description>Indicates whether or not WDT is running</description>
114365 <description>Watchdog is not running</description>
114370 <description>Watchdog is running</description>
114379 <description>Request status</description>
114387 <description>Request status for RR[0] register</description>
114393 … <description>RR[0] register is not enabled, or are already requesting reload</description>
114398 … <description>RR[0] register is enabled, and are not yet requesting reload</description>
114405 <description>Request status for RR[1] register</description>
114411 … <description>RR[1] register is not enabled, or are already requesting reload</description>
114416 … <description>RR[1] register is enabled, and are not yet requesting reload</description>
114423 <description>Request status for RR[2] register</description>
114429 … <description>RR[2] register is not enabled, or are already requesting reload</description>
114434 … <description>RR[2] register is enabled, and are not yet requesting reload</description>
114441 <description>Request status for RR[3] register</description>
114447 … <description>RR[3] register is not enabled, or are already requesting reload</description>
114452 … <description>RR[3] register is enabled, and are not yet requesting reload</description>
114459 <description>Request status for RR[4] register</description>
114465 … <description>RR[4] register is not enabled, or are already requesting reload</description>
114470 … <description>RR[4] register is enabled, and are not yet requesting reload</description>
114477 <description>Request status for RR[5] register</description>
114483 … <description>RR[5] register is not enabled, or are already requesting reload</description>
114488 … <description>RR[5] register is enabled, and are not yet requesting reload</description>
114495 <description>Request status for RR[6] register</description>
114501 … <description>RR[6] register is not enabled, or are already requesting reload</description>
114506 … <description>RR[6] register is enabled, and are not yet requesting reload</description>
114513 <description>Request status for RR[7] register</description>
114519 … <description>RR[7] register is not enabled, or are already requesting reload</description>
114524 … <description>RR[7] register is enabled, and are not yet requesting reload</description>
114533 <description>Counter reload value</description>
114541 … <description>Counter reload value in number of cycles of the 32.768 kHz clock</description>
114549 <description>Enable register for reload request registers</description>
114557 <description>Enable or disable RR[0] register</description>
114563 <description>Disable RR[0] register</description>
114568 <description>Enable RR[0] register</description>
114575 <description>Enable or disable RR[1] register</description>
114581 <description>Disable RR[1] register</description>
114586 <description>Enable RR[1] register</description>
114593 <description>Enable or disable RR[2] register</description>
114599 <description>Disable RR[2] register</description>
114604 <description>Enable RR[2] register</description>
114611 <description>Enable or disable RR[3] register</description>
114617 <description>Disable RR[3] register</description>
114622 <description>Enable RR[3] register</description>
114629 <description>Enable or disable RR[4] register</description>
114635 <description>Disable RR[4] register</description>
114640 <description>Enable RR[4] register</description>
114647 <description>Enable or disable RR[5] register</description>
114653 <description>Disable RR[5] register</description>
114658 <description>Enable RR[5] register</description>
114665 <description>Enable or disable RR[6] register</description>
114671 <description>Disable RR[6] register</description>
114676 <description>Enable RR[6] register</description>
114683 <description>Enable or disable RR[7] register</description>
114689 <description>Disable RR[7] register</description>
114694 <description>Enable RR[7] register</description>
114703 <description>Configuration register</description>
114711 …<description>Configure WDT to either be paused, or kept running, while the CPU is sleeping</descri…
114717 <description>Pause WDT while the CPU is sleeping</description>
114722 <description>Keep WDT running while the CPU is sleeping</description>
114729 …<description>Configure WDT to either be paused, or kept running, while the CPU is halted by the de…
114735 <description>Pause WDT while the CPU is halted by the debugger</description>
114740 … <description>Keep WDT running while the CPU is halted by the debugger</description>
114747 <description>Allow stopping WDT</description>
114753 <description>Do not allow stopping WDT</description>
114758 <description>Allow stopping WDT</description>
114767 <description>Task stop enable</description>
114775 <description>Allow stopping WDT</description>
114781 <description>Value to allow stopping WDT</description>
114792 <description>Description collection: Reload request n</description>
114800 <description>Reload request register</description>
114806 <description>Value to request a reload of the watchdog timer</description>
114817 <description>Watchdog Timer 1</description>
114828 <description>Event generator unit</description>
114849 …<description>Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event…
114857 … <description>Trigger n for triggering the corresponding TRIGGERED[n] event</description>
114863 <description>Trigger task</description>
114874 … <description>Description collection: Subscribe configuration for task TRIGGER[n]</description>
114882 <description>DPPI channel that task TRIGGER[n] will subscribe to</description>
114893 <description>Disable subscription</description>
114898 <description>Enable subscription</description>
114909 …<description>Description collection: Event number n generated by triggering the corresponding TRIG…
114917 …<description>Event number n generated by triggering the corresponding TRIGGER[n] task</description>
114923 <description>Event not generated</description>
114928 <description>Event generated</description>
114939 … <description>Description collection: Publish configuration for event TRIGGERED[n]</description>
114947 <description>DPPI channel that event TRIGGERED[n] will publish to</description>
114958 <description>Disable publishing</description>
114963 <description>Enable publishing</description>
114972 <description>Enable or disable interrupt</description>
114980 <description>Enable or disable interrupt for event TRIGGERED[0]</description>
114986 <description>Disable</description>
114991 <description>Enable</description>
114998 <description>Enable or disable interrupt for event TRIGGERED[1]</description>
115004 <description>Disable</description>
115009 <description>Enable</description>
115016 <description>Enable or disable interrupt for event TRIGGERED[2]</description>
115022 <description>Disable</description>
115027 <description>Enable</description>
115034 <description>Enable or disable interrupt for event TRIGGERED[3]</description>
115040 <description>Disable</description>
115045 <description>Enable</description>
115052 <description>Enable or disable interrupt for event TRIGGERED[4]</description>
115058 <description>Disable</description>
115063 <description>Enable</description>
115070 <description>Enable or disable interrupt for event TRIGGERED[5]</description>
115076 <description>Disable</description>
115081 <description>Enable</description>
115088 <description>Enable or disable interrupt for event TRIGGERED[6]</description>
115094 <description>Disable</description>
115099 <description>Enable</description>
115106 <description>Enable or disable interrupt for event TRIGGERED[7]</description>
115112 <description>Disable</description>
115117 <description>Enable</description>
115124 <description>Enable or disable interrupt for event TRIGGERED[8]</description>
115130 <description>Disable</description>
115135 <description>Enable</description>
115142 <description>Enable or disable interrupt for event TRIGGERED[9]</description>
115148 <description>Disable</description>
115153 <description>Enable</description>
115160 <description>Enable or disable interrupt for event TRIGGERED[10]</description>
115166 <description>Disable</description>
115171 <description>Enable</description>
115178 <description>Enable or disable interrupt for event TRIGGERED[11]</description>
115184 <description>Disable</description>
115189 <description>Enable</description>
115196 <description>Enable or disable interrupt for event TRIGGERED[12]</description>
115202 <description>Disable</description>
115207 <description>Enable</description>
115214 <description>Enable or disable interrupt for event TRIGGERED[13]</description>
115220 <description>Disable</description>
115225 <description>Enable</description>
115232 <description>Enable or disable interrupt for event TRIGGERED[14]</description>
115238 <description>Disable</description>
115243 <description>Enable</description>
115250 <description>Enable or disable interrupt for event TRIGGERED[15]</description>
115256 <description>Disable</description>
115261 <description>Enable</description>
115270 <description>Enable interrupt</description>
115278 <description>Write '1' to enable interrupt for event TRIGGERED[0]</description>
115285 <description>Read: Disabled</description>
115290 <description>Read: Enabled</description>
115298 <description>Enable</description>
115305 <description>Write '1' to enable interrupt for event TRIGGERED[1]</description>
115312 <description>Read: Disabled</description>
115317 <description>Read: Enabled</description>
115325 <description>Enable</description>
115332 <description>Write '1' to enable interrupt for event TRIGGERED[2]</description>
115339 <description>Read: Disabled</description>
115344 <description>Read: Enabled</description>
115352 <description>Enable</description>
115359 <description>Write '1' to enable interrupt for event TRIGGERED[3]</description>
115366 <description>Read: Disabled</description>
115371 <description>Read: Enabled</description>
115379 <description>Enable</description>
115386 <description>Write '1' to enable interrupt for event TRIGGERED[4]</description>
115393 <description>Read: Disabled</description>
115398 <description>Read: Enabled</description>
115406 <description>Enable</description>
115413 <description>Write '1' to enable interrupt for event TRIGGERED[5]</description>
115420 <description>Read: Disabled</description>
115425 <description>Read: Enabled</description>
115433 <description>Enable</description>
115440 <description>Write '1' to enable interrupt for event TRIGGERED[6]</description>
115447 <description>Read: Disabled</description>
115452 <description>Read: Enabled</description>
115460 <description>Enable</description>
115467 <description>Write '1' to enable interrupt for event TRIGGERED[7]</description>
115474 <description>Read: Disabled</description>
115479 <description>Read: Enabled</description>
115487 <description>Enable</description>
115494 <description>Write '1' to enable interrupt for event TRIGGERED[8]</description>
115501 <description>Read: Disabled</description>
115506 <description>Read: Enabled</description>
115514 <description>Enable</description>
115521 <description>Write '1' to enable interrupt for event TRIGGERED[9]</description>
115528 <description>Read: Disabled</description>
115533 <description>Read: Enabled</description>
115541 <description>Enable</description>
115548 <description>Write '1' to enable interrupt for event TRIGGERED[10]</description>
115555 <description>Read: Disabled</description>
115560 <description>Read: Enabled</description>
115568 <description>Enable</description>
115575 <description>Write '1' to enable interrupt for event TRIGGERED[11]</description>
115582 <description>Read: Disabled</description>
115587 <description>Read: Enabled</description>
115595 <description>Enable</description>
115602 <description>Write '1' to enable interrupt for event TRIGGERED[12]</description>
115609 <description>Read: Disabled</description>
115614 <description>Read: Enabled</description>
115622 <description>Enable</description>
115629 <description>Write '1' to enable interrupt for event TRIGGERED[13]</description>
115636 <description>Read: Disabled</description>
115641 <description>Read: Enabled</description>
115649 <description>Enable</description>
115656 <description>Write '1' to enable interrupt for event TRIGGERED[14]</description>
115663 <description>Read: Disabled</description>
115668 <description>Read: Enabled</description>
115676 <description>Enable</description>
115683 <description>Write '1' to enable interrupt for event TRIGGERED[15]</description>
115690 <description>Read: Disabled</description>
115695 <description>Read: Enabled</description>
115703 <description>Enable</description>
115712 <description>Disable interrupt</description>
115720 <description>Write '1' to disable interrupt for event TRIGGERED[0]</description>
115727 <description>Read: Disabled</description>
115732 <description>Read: Enabled</description>
115740 <description>Disable</description>
115747 <description>Write '1' to disable interrupt for event TRIGGERED[1]</description>
115754 <description>Read: Disabled</description>
115759 <description>Read: Enabled</description>
115767 <description>Disable</description>
115774 <description>Write '1' to disable interrupt for event TRIGGERED[2]</description>
115781 <description>Read: Disabled</description>
115786 <description>Read: Enabled</description>
115794 <description>Disable</description>
115801 <description>Write '1' to disable interrupt for event TRIGGERED[3]</description>
115808 <description>Read: Disabled</description>
115813 <description>Read: Enabled</description>
115821 <description>Disable</description>
115828 <description>Write '1' to disable interrupt for event TRIGGERED[4]</description>
115835 <description>Read: Disabled</description>
115840 <description>Read: Enabled</description>
115848 <description>Disable</description>
115855 <description>Write '1' to disable interrupt for event TRIGGERED[5]</description>
115862 <description>Read: Disabled</description>
115867 <description>Read: Enabled</description>
115875 <description>Disable</description>
115882 <description>Write '1' to disable interrupt for event TRIGGERED[6]</description>
115889 <description>Read: Disabled</description>
115894 <description>Read: Enabled</description>
115902 <description>Disable</description>
115909 <description>Write '1' to disable interrupt for event TRIGGERED[7]</description>
115916 <description>Read: Disabled</description>
115921 <description>Read: Enabled</description>
115929 <description>Disable</description>
115936 <description>Write '1' to disable interrupt for event TRIGGERED[8]</description>
115943 <description>Read: Disabled</description>
115948 <description>Read: Enabled</description>
115956 <description>Disable</description>
115963 <description>Write '1' to disable interrupt for event TRIGGERED[9]</description>
115970 <description>Read: Disabled</description>
115975 <description>Read: Enabled</description>
115983 <description>Disable</description>
115990 <description>Write '1' to disable interrupt for event TRIGGERED[10]</description>
115997 <description>Read: Disabled</description>
116002 <description>Read: Enabled</description>
116010 <description>Disable</description>
116017 <description>Write '1' to disable interrupt for event TRIGGERED[11]</description>
116024 <description>Read: Disabled</description>
116029 <description>Read: Enabled</description>
116037 <description>Disable</description>
116044 <description>Write '1' to disable interrupt for event TRIGGERED[12]</description>
116051 <description>Read: Disabled</description>
116056 <description>Read: Enabled</description>
116064 <description>Disable</description>
116071 <description>Write '1' to disable interrupt for event TRIGGERED[13]</description>
116078 <description>Read: Disabled</description>
116083 <description>Read: Enabled</description>
116091 <description>Disable</description>
116098 <description>Write '1' to disable interrupt for event TRIGGERED[14]</description>
116105 <description>Read: Disabled</description>
116110 <description>Read: Enabled</description>
116118 <description>Disable</description>
116125 <description>Write '1' to disable interrupt for event TRIGGERED[15]</description>
116132 <description>Read: Disabled</description>
116137 <description>Read: Enabled</description>
116145 <description>Disable</description>
116154 <description>Pending interrupts</description>
116162 <description>Read pending status of interrupt for event TRIGGERED[0]</description>
116169 <description>Read: Not pending</description>
116174 <description>Read: Pending</description>
116181 <description>Read pending status of interrupt for event TRIGGERED[1]</description>
116188 <description>Read: Not pending</description>
116193 <description>Read: Pending</description>
116200 <description>Read pending status of interrupt for event TRIGGERED[2]</description>
116207 <description>Read: Not pending</description>
116212 <description>Read: Pending</description>
116219 <description>Read pending status of interrupt for event TRIGGERED[3]</description>
116226 <description>Read: Not pending</description>
116231 <description>Read: Pending</description>
116238 <description>Read pending status of interrupt for event TRIGGERED[4]</description>
116245 <description>Read: Not pending</description>
116250 <description>Read: Pending</description>
116257 <description>Read pending status of interrupt for event TRIGGERED[5]</description>
116264 <description>Read: Not pending</description>
116269 <description>Read: Pending</description>
116276 <description>Read pending status of interrupt for event TRIGGERED[6]</description>
116283 <description>Read: Not pending</description>
116288 <description>Read: Pending</description>
116295 <description>Read pending status of interrupt for event TRIGGERED[7]</description>
116302 <description>Read: Not pending</description>
116307 <description>Read: Pending</description>
116314 <description>Read pending status of interrupt for event TRIGGERED[8]</description>
116321 <description>Read: Not pending</description>
116326 <description>Read: Pending</description>
116333 <description>Read pending status of interrupt for event TRIGGERED[9]</description>
116340 <description>Read: Not pending</description>
116345 <description>Read: Pending</description>
116352 <description>Read pending status of interrupt for event TRIGGERED[10]</description>
116359 <description>Read: Not pending</description>
116364 <description>Read: Pending</description>
116371 <description>Read pending status of interrupt for event TRIGGERED[11]</description>
116378 <description>Read: Not pending</description>
116383 <description>Read: Pending</description>
116390 <description>Read pending status of interrupt for event TRIGGERED[12]</description>
116397 <description>Read: Not pending</description>
116402 <description>Read: Pending</description>
116409 <description>Read pending status of interrupt for event TRIGGERED[13]</description>
116416 <description>Read: Not pending</description>
116421 <description>Read: Pending</description>
116428 <description>Read pending status of interrupt for event TRIGGERED[14]</description>
116435 <description>Read: Not pending</description>
116440 <description>Read: Pending</description>
116447 <description>Read pending status of interrupt for event TRIGGERED[15]</description>
116454 <description>Read: Not pending</description>
116459 <description>Read: Pending</description>
116470 <description>GPIO Port 0</description>
116486 <description>Write GPIO port</description>
116494 <description>Pin 0</description>
116500 <description>Pin driver is low</description>
116505 <description>Pin driver is high</description>
116512 <description>Pin 1</description>
116518 <description>Pin driver is low</description>
116523 <description>Pin driver is high</description>
116530 <description>Pin 2</description>
116536 <description>Pin driver is low</description>
116541 <description>Pin driver is high</description>
116548 <description>Pin 3</description>
116554 <description>Pin driver is low</description>
116559 <description>Pin driver is high</description>
116566 <description>Pin 4</description>
116572 <description>Pin driver is low</description>
116577 <description>Pin driver is high</description>
116584 <description>Pin 5</description>
116590 <description>Pin driver is low</description>
116595 <description>Pin driver is high</description>
116602 <description>Pin 6</description>
116608 <description>Pin driver is low</description>
116613 <description>Pin driver is high</description>
116620 <description>Pin 7</description>
116626 <description>Pin driver is low</description>
116631 <description>Pin driver is high</description>
116638 <description>Pin 8</description>
116644 <description>Pin driver is low</description>
116649 <description>Pin driver is high</description>
116656 <description>Pin 9</description>
116662 <description>Pin driver is low</description>
116667 <description>Pin driver is high</description>
116674 <description>Pin 10</description>
116680 <description>Pin driver is low</description>
116685 <description>Pin driver is high</description>
116692 <description>Pin 11</description>
116698 <description>Pin driver is low</description>
116703 <description>Pin driver is high</description>
116710 <description>Pin 12</description>
116716 <description>Pin driver is low</description>
116721 <description>Pin driver is high</description>
116728 <description>Pin 13</description>
116734 <description>Pin driver is low</description>
116739 <description>Pin driver is high</description>
116746 <description>Pin 14</description>
116752 <description>Pin driver is low</description>
116757 <description>Pin driver is high</description>
116764 <description>Pin 15</description>
116770 <description>Pin driver is low</description>
116775 <description>Pin driver is high</description>
116782 <description>Pin 16</description>
116788 <description>Pin driver is low</description>
116793 <description>Pin driver is high</description>
116800 <description>Pin 17</description>
116806 <description>Pin driver is low</description>
116811 <description>Pin driver is high</description>
116818 <description>Pin 18</description>
116824 <description>Pin driver is low</description>
116829 <description>Pin driver is high</description>
116836 <description>Pin 19</description>
116842 <description>Pin driver is low</description>
116847 <description>Pin driver is high</description>
116854 <description>Pin 20</description>
116860 <description>Pin driver is low</description>
116865 <description>Pin driver is high</description>
116872 <description>Pin 21</description>
116878 <description>Pin driver is low</description>
116883 <description>Pin driver is high</description>
116890 <description>Pin 22</description>
116896 <description>Pin driver is low</description>
116901 <description>Pin driver is high</description>
116908 <description>Pin 23</description>
116914 <description>Pin driver is low</description>
116919 <description>Pin driver is high</description>
116926 <description>Pin 24</description>
116932 <description>Pin driver is low</description>
116937 <description>Pin driver is high</description>
116944 <description>Pin 25</description>
116950 <description>Pin driver is low</description>
116955 <description>Pin driver is high</description>
116962 <description>Pin 26</description>
116968 <description>Pin driver is low</description>
116973 <description>Pin driver is high</description>
116980 <description>Pin 27</description>
116986 <description>Pin driver is low</description>
116991 <description>Pin driver is high</description>
116998 <description>Pin 28</description>
117004 <description>Pin driver is low</description>
117009 <description>Pin driver is high</description>
117016 <description>Pin 29</description>
117022 <description>Pin driver is low</description>
117027 <description>Pin driver is high</description>
117034 <description>Pin 30</description>
117040 <description>Pin driver is low</description>
117045 <description>Pin driver is high</description>
117052 <description>Pin 31</description>
117058 <description>Pin driver is low</description>
117063 <description>Pin driver is high</description>
117072 <description>Set individual bits in GPIO port</description>
117081 <description>Pin 0</description>
117088 <description>Read: pin driver is low</description>
117093 <description>Read: pin driver is high</description>
117101 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
117108 <description>Pin 1</description>
117115 <description>Read: pin driver is low</description>
117120 <description>Read: pin driver is high</description>
117128 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
117135 <description>Pin 2</description>
117142 <description>Read: pin driver is low</description>
117147 <description>Read: pin driver is high</description>
117155 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
117162 <description>Pin 3</description>
117169 <description>Read: pin driver is low</description>
117174 <description>Read: pin driver is high</description>
117182 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
117189 <description>Pin 4</description>
117196 <description>Read: pin driver is low</description>
117201 <description>Read: pin driver is high</description>
117209 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
117216 <description>Pin 5</description>
117223 <description>Read: pin driver is low</description>
117228 <description>Read: pin driver is high</description>
117236 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
117243 <description>Pin 6</description>
117250 <description>Read: pin driver is low</description>
117255 <description>Read: pin driver is high</description>
117263 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
117270 <description>Pin 7</description>
117277 <description>Read: pin driver is low</description>
117282 <description>Read: pin driver is high</description>
117290 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
117297 <description>Pin 8</description>
117304 <description>Read: pin driver is low</description>
117309 <description>Read: pin driver is high</description>
117317 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
117324 <description>Pin 9</description>
117331 <description>Read: pin driver is low</description>
117336 <description>Read: pin driver is high</description>
117344 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
117351 <description>Pin 10</description>
117358 <description>Read: pin driver is low</description>
117363 <description>Read: pin driver is high</description>
117371 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
117378 <description>Pin 11</description>
117385 <description>Read: pin driver is low</description>
117390 <description>Read: pin driver is high</description>
117398 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
117405 <description>Pin 12</description>
117412 <description>Read: pin driver is low</description>
117417 <description>Read: pin driver is high</description>
117425 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
117432 <description>Pin 13</description>
117439 <description>Read: pin driver is low</description>
117444 <description>Read: pin driver is high</description>
117452 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
117459 <description>Pin 14</description>
117466 <description>Read: pin driver is low</description>
117471 <description>Read: pin driver is high</description>
117479 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
117486 <description>Pin 15</description>
117493 <description>Read: pin driver is low</description>
117498 <description>Read: pin driver is high</description>
117506 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
117513 <description>Pin 16</description>
117520 <description>Read: pin driver is low</description>
117525 <description>Read: pin driver is high</description>
117533 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
117540 <description>Pin 17</description>
117547 <description>Read: pin driver is low</description>
117552 <description>Read: pin driver is high</description>
117560 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
117567 <description>Pin 18</description>
117574 <description>Read: pin driver is low</description>
117579 <description>Read: pin driver is high</description>
117587 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
117594 <description>Pin 19</description>
117601 <description>Read: pin driver is low</description>
117606 <description>Read: pin driver is high</description>
117614 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
117621 <description>Pin 20</description>
117628 <description>Read: pin driver is low</description>
117633 <description>Read: pin driver is high</description>
117641 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
117648 <description>Pin 21</description>
117655 <description>Read: pin driver is low</description>
117660 <description>Read: pin driver is high</description>
117668 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
117675 <description>Pin 22</description>
117682 <description>Read: pin driver is low</description>
117687 <description>Read: pin driver is high</description>
117695 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
117702 <description>Pin 23</description>
117709 <description>Read: pin driver is low</description>
117714 <description>Read: pin driver is high</description>
117722 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
117729 <description>Pin 24</description>
117736 <description>Read: pin driver is low</description>
117741 <description>Read: pin driver is high</description>
117749 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
117756 <description>Pin 25</description>
117763 <description>Read: pin driver is low</description>
117768 <description>Read: pin driver is high</description>
117776 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
117783 <description>Pin 26</description>
117790 <description>Read: pin driver is low</description>
117795 <description>Read: pin driver is high</description>
117803 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
117810 <description>Pin 27</description>
117817 <description>Read: pin driver is low</description>
117822 <description>Read: pin driver is high</description>
117830 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
117837 <description>Pin 28</description>
117844 <description>Read: pin driver is low</description>
117849 <description>Read: pin driver is high</description>
117857 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
117864 <description>Pin 29</description>
117871 <description>Read: pin driver is low</description>
117876 <description>Read: pin driver is high</description>
117884 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
117891 <description>Pin 30</description>
117898 <description>Read: pin driver is low</description>
117903 <description>Read: pin driver is high</description>
117911 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
117918 <description>Pin 31</description>
117925 <description>Read: pin driver is low</description>
117930 <description>Read: pin driver is high</description>
117938 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
117947 <description>Clear individual bits in GPIO port</description>
117956 <description>Pin 0</description>
117963 <description>Read: pin driver is low</description>
117968 <description>Read: pin driver is high</description>
117976 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
117983 <description>Pin 1</description>
117990 <description>Read: pin driver is low</description>
117995 <description>Read: pin driver is high</description>
118003 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
118010 <description>Pin 2</description>
118017 <description>Read: pin driver is low</description>
118022 <description>Read: pin driver is high</description>
118030 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
118037 <description>Pin 3</description>
118044 <description>Read: pin driver is low</description>
118049 <description>Read: pin driver is high</description>
118057 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
118064 <description>Pin 4</description>
118071 <description>Read: pin driver is low</description>
118076 <description>Read: pin driver is high</description>
118084 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
118091 <description>Pin 5</description>
118098 <description>Read: pin driver is low</description>
118103 <description>Read: pin driver is high</description>
118111 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
118118 <description>Pin 6</description>
118125 <description>Read: pin driver is low</description>
118130 <description>Read: pin driver is high</description>
118138 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
118145 <description>Pin 7</description>
118152 <description>Read: pin driver is low</description>
118157 <description>Read: pin driver is high</description>
118165 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
118172 <description>Pin 8</description>
118179 <description>Read: pin driver is low</description>
118184 <description>Read: pin driver is high</description>
118192 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
118199 <description>Pin 9</description>
118206 <description>Read: pin driver is low</description>
118211 <description>Read: pin driver is high</description>
118219 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
118226 <description>Pin 10</description>
118233 <description>Read: pin driver is low</description>
118238 <description>Read: pin driver is high</description>
118246 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
118253 <description>Pin 11</description>
118260 <description>Read: pin driver is low</description>
118265 <description>Read: pin driver is high</description>
118273 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
118280 <description>Pin 12</description>
118287 <description>Read: pin driver is low</description>
118292 <description>Read: pin driver is high</description>
118300 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
118307 <description>Pin 13</description>
118314 <description>Read: pin driver is low</description>
118319 <description>Read: pin driver is high</description>
118327 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
118334 <description>Pin 14</description>
118341 <description>Read: pin driver is low</description>
118346 <description>Read: pin driver is high</description>
118354 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
118361 <description>Pin 15</description>
118368 <description>Read: pin driver is low</description>
118373 <description>Read: pin driver is high</description>
118381 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
118388 <description>Pin 16</description>
118395 <description>Read: pin driver is low</description>
118400 <description>Read: pin driver is high</description>
118408 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
118415 <description>Pin 17</description>
118422 <description>Read: pin driver is low</description>
118427 <description>Read: pin driver is high</description>
118435 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
118442 <description>Pin 18</description>
118449 <description>Read: pin driver is low</description>
118454 <description>Read: pin driver is high</description>
118462 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
118469 <description>Pin 19</description>
118476 <description>Read: pin driver is low</description>
118481 <description>Read: pin driver is high</description>
118489 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
118496 <description>Pin 20</description>
118503 <description>Read: pin driver is low</description>
118508 <description>Read: pin driver is high</description>
118516 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
118523 <description>Pin 21</description>
118530 <description>Read: pin driver is low</description>
118535 <description>Read: pin driver is high</description>
118543 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
118550 <description>Pin 22</description>
118557 <description>Read: pin driver is low</description>
118562 <description>Read: pin driver is high</description>
118570 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
118577 <description>Pin 23</description>
118584 <description>Read: pin driver is low</description>
118589 <description>Read: pin driver is high</description>
118597 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
118604 <description>Pin 24</description>
118611 <description>Read: pin driver is low</description>
118616 <description>Read: pin driver is high</description>
118624 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
118631 <description>Pin 25</description>
118638 <description>Read: pin driver is low</description>
118643 <description>Read: pin driver is high</description>
118651 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
118658 <description>Pin 26</description>
118665 <description>Read: pin driver is low</description>
118670 <description>Read: pin driver is high</description>
118678 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
118685 <description>Pin 27</description>
118692 <description>Read: pin driver is low</description>
118697 <description>Read: pin driver is high</description>
118705 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
118712 <description>Pin 28</description>
118719 <description>Read: pin driver is low</description>
118724 <description>Read: pin driver is high</description>
118732 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
118739 <description>Pin 29</description>
118746 <description>Read: pin driver is low</description>
118751 <description>Read: pin driver is high</description>
118759 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
118766 <description>Pin 30</description>
118773 <description>Read: pin driver is low</description>
118778 <description>Read: pin driver is high</description>
118786 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
118793 <description>Pin 31</description>
118800 <description>Read: pin driver is low</description>
118805 <description>Read: pin driver is high</description>
118813 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
118822 <description>Read GPIO port</description>
118830 <description>Pin 0</description>
118836 <description>Pin input is low</description>
118841 <description>Pin input is high</description>
118848 <description>Pin 1</description>
118854 <description>Pin input is low</description>
118859 <description>Pin input is high</description>
118866 <description>Pin 2</description>
118872 <description>Pin input is low</description>
118877 <description>Pin input is high</description>
118884 <description>Pin 3</description>
118890 <description>Pin input is low</description>
118895 <description>Pin input is high</description>
118902 <description>Pin 4</description>
118908 <description>Pin input is low</description>
118913 <description>Pin input is high</description>
118920 <description>Pin 5</description>
118926 <description>Pin input is low</description>
118931 <description>Pin input is high</description>
118938 <description>Pin 6</description>
118944 <description>Pin input is low</description>
118949 <description>Pin input is high</description>
118956 <description>Pin 7</description>
118962 <description>Pin input is low</description>
118967 <description>Pin input is high</description>
118974 <description>Pin 8</description>
118980 <description>Pin input is low</description>
118985 <description>Pin input is high</description>
118992 <description>Pin 9</description>
118998 <description>Pin input is low</description>
119003 <description>Pin input is high</description>
119010 <description>Pin 10</description>
119016 <description>Pin input is low</description>
119021 <description>Pin input is high</description>
119028 <description>Pin 11</description>
119034 <description>Pin input is low</description>
119039 <description>Pin input is high</description>
119046 <description>Pin 12</description>
119052 <description>Pin input is low</description>
119057 <description>Pin input is high</description>
119064 <description>Pin 13</description>
119070 <description>Pin input is low</description>
119075 <description>Pin input is high</description>
119082 <description>Pin 14</description>
119088 <description>Pin input is low</description>
119093 <description>Pin input is high</description>
119100 <description>Pin 15</description>
119106 <description>Pin input is low</description>
119111 <description>Pin input is high</description>
119118 <description>Pin 16</description>
119124 <description>Pin input is low</description>
119129 <description>Pin input is high</description>
119136 <description>Pin 17</description>
119142 <description>Pin input is low</description>
119147 <description>Pin input is high</description>
119154 <description>Pin 18</description>
119160 <description>Pin input is low</description>
119165 <description>Pin input is high</description>
119172 <description>Pin 19</description>
119178 <description>Pin input is low</description>
119183 <description>Pin input is high</description>
119190 <description>Pin 20</description>
119196 <description>Pin input is low</description>
119201 <description>Pin input is high</description>
119208 <description>Pin 21</description>
119214 <description>Pin input is low</description>
119219 <description>Pin input is high</description>
119226 <description>Pin 22</description>
119232 <description>Pin input is low</description>
119237 <description>Pin input is high</description>
119244 <description>Pin 23</description>
119250 <description>Pin input is low</description>
119255 <description>Pin input is high</description>
119262 <description>Pin 24</description>
119268 <description>Pin input is low</description>
119273 <description>Pin input is high</description>
119280 <description>Pin 25</description>
119286 <description>Pin input is low</description>
119291 <description>Pin input is high</description>
119298 <description>Pin 26</description>
119304 <description>Pin input is low</description>
119309 <description>Pin input is high</description>
119316 <description>Pin 27</description>
119322 <description>Pin input is low</description>
119327 <description>Pin input is high</description>
119334 <description>Pin 28</description>
119340 <description>Pin input is low</description>
119345 <description>Pin input is high</description>
119352 <description>Pin 29</description>
119358 <description>Pin input is low</description>
119363 <description>Pin input is high</description>
119370 <description>Pin 30</description>
119376 <description>Pin input is low</description>
119381 <description>Pin input is high</description>
119388 <description>Pin 31</description>
119394 <description>Pin input is low</description>
119399 <description>Pin input is high</description>
119408 <description>Direction of GPIO pins</description>
119416 <description>Pin 0</description>
119422 <description>Pin set as input</description>
119427 <description>Pin set as output</description>
119434 <description>Pin 1</description>
119440 <description>Pin set as input</description>
119445 <description>Pin set as output</description>
119452 <description>Pin 2</description>
119458 <description>Pin set as input</description>
119463 <description>Pin set as output</description>
119470 <description>Pin 3</description>
119476 <description>Pin set as input</description>
119481 <description>Pin set as output</description>
119488 <description>Pin 4</description>
119494 <description>Pin set as input</description>
119499 <description>Pin set as output</description>
119506 <description>Pin 5</description>
119512 <description>Pin set as input</description>
119517 <description>Pin set as output</description>
119524 <description>Pin 6</description>
119530 <description>Pin set as input</description>
119535 <description>Pin set as output</description>
119542 <description>Pin 7</description>
119548 <description>Pin set as input</description>
119553 <description>Pin set as output</description>
119560 <description>Pin 8</description>
119566 <description>Pin set as input</description>
119571 <description>Pin set as output</description>
119578 <description>Pin 9</description>
119584 <description>Pin set as input</description>
119589 <description>Pin set as output</description>
119596 <description>Pin 10</description>
119602 <description>Pin set as input</description>
119607 <description>Pin set as output</description>
119614 <description>Pin 11</description>
119620 <description>Pin set as input</description>
119625 <description>Pin set as output</description>
119632 <description>Pin 12</description>
119638 <description>Pin set as input</description>
119643 <description>Pin set as output</description>
119650 <description>Pin 13</description>
119656 <description>Pin set as input</description>
119661 <description>Pin set as output</description>
119668 <description>Pin 14</description>
119674 <description>Pin set as input</description>
119679 <description>Pin set as output</description>
119686 <description>Pin 15</description>
119692 <description>Pin set as input</description>
119697 <description>Pin set as output</description>
119704 <description>Pin 16</description>
119710 <description>Pin set as input</description>
119715 <description>Pin set as output</description>
119722 <description>Pin 17</description>
119728 <description>Pin set as input</description>
119733 <description>Pin set as output</description>
119740 <description>Pin 18</description>
119746 <description>Pin set as input</description>
119751 <description>Pin set as output</description>
119758 <description>Pin 19</description>
119764 <description>Pin set as input</description>
119769 <description>Pin set as output</description>
119776 <description>Pin 20</description>
119782 <description>Pin set as input</description>
119787 <description>Pin set as output</description>
119794 <description>Pin 21</description>
119800 <description>Pin set as input</description>
119805 <description>Pin set as output</description>
119812 <description>Pin 22</description>
119818 <description>Pin set as input</description>
119823 <description>Pin set as output</description>
119830 <description>Pin 23</description>
119836 <description>Pin set as input</description>
119841 <description>Pin set as output</description>
119848 <description>Pin 24</description>
119854 <description>Pin set as input</description>
119859 <description>Pin set as output</description>
119866 <description>Pin 25</description>
119872 <description>Pin set as input</description>
119877 <description>Pin set as output</description>
119884 <description>Pin 26</description>
119890 <description>Pin set as input</description>
119895 <description>Pin set as output</description>
119902 <description>Pin 27</description>
119908 <description>Pin set as input</description>
119913 <description>Pin set as output</description>
119920 <description>Pin 28</description>
119926 <description>Pin set as input</description>
119931 <description>Pin set as output</description>
119938 <description>Pin 29</description>
119944 <description>Pin set as input</description>
119949 <description>Pin set as output</description>
119956 <description>Pin 30</description>
119962 <description>Pin set as input</description>
119967 <description>Pin set as output</description>
119974 <description>Pin 31</description>
119980 <description>Pin set as input</description>
119985 <description>Pin set as output</description>
119994 <description>DIR set register</description>
120003 <description>Set as output pin 0</description>
120010 <description>Read: pin set as input</description>
120015 <description>Read: pin set as output</description>
120023 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
120030 <description>Set as output pin 1</description>
120037 <description>Read: pin set as input</description>
120042 <description>Read: pin set as output</description>
120050 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
120057 <description>Set as output pin 2</description>
120064 <description>Read: pin set as input</description>
120069 <description>Read: pin set as output</description>
120077 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
120084 <description>Set as output pin 3</description>
120091 <description>Read: pin set as input</description>
120096 <description>Read: pin set as output</description>
120104 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
120111 <description>Set as output pin 4</description>
120118 <description>Read: pin set as input</description>
120123 <description>Read: pin set as output</description>
120131 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
120138 <description>Set as output pin 5</description>
120145 <description>Read: pin set as input</description>
120150 <description>Read: pin set as output</description>
120158 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
120165 <description>Set as output pin 6</description>
120172 <description>Read: pin set as input</description>
120177 <description>Read: pin set as output</description>
120185 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
120192 <description>Set as output pin 7</description>
120199 <description>Read: pin set as input</description>
120204 <description>Read: pin set as output</description>
120212 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
120219 <description>Set as output pin 8</description>
120226 <description>Read: pin set as input</description>
120231 <description>Read: pin set as output</description>
120239 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
120246 <description>Set as output pin 9</description>
120253 <description>Read: pin set as input</description>
120258 <description>Read: pin set as output</description>
120266 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
120273 <description>Set as output pin 10</description>
120280 <description>Read: pin set as input</description>
120285 <description>Read: pin set as output</description>
120293 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
120300 <description>Set as output pin 11</description>
120307 <description>Read: pin set as input</description>
120312 <description>Read: pin set as output</description>
120320 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
120327 <description>Set as output pin 12</description>
120334 <description>Read: pin set as input</description>
120339 <description>Read: pin set as output</description>
120347 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
120354 <description>Set as output pin 13</description>
120361 <description>Read: pin set as input</description>
120366 <description>Read: pin set as output</description>
120374 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
120381 <description>Set as output pin 14</description>
120388 <description>Read: pin set as input</description>
120393 <description>Read: pin set as output</description>
120401 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
120408 <description>Set as output pin 15</description>
120415 <description>Read: pin set as input</description>
120420 <description>Read: pin set as output</description>
120428 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
120435 <description>Set as output pin 16</description>
120442 <description>Read: pin set as input</description>
120447 <description>Read: pin set as output</description>
120455 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
120462 <description>Set as output pin 17</description>
120469 <description>Read: pin set as input</description>
120474 <description>Read: pin set as output</description>
120482 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
120489 <description>Set as output pin 18</description>
120496 <description>Read: pin set as input</description>
120501 <description>Read: pin set as output</description>
120509 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
120516 <description>Set as output pin 19</description>
120523 <description>Read: pin set as input</description>
120528 <description>Read: pin set as output</description>
120536 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
120543 <description>Set as output pin 20</description>
120550 <description>Read: pin set as input</description>
120555 <description>Read: pin set as output</description>
120563 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
120570 <description>Set as output pin 21</description>
120577 <description>Read: pin set as input</description>
120582 <description>Read: pin set as output</description>
120590 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
120597 <description>Set as output pin 22</description>
120604 <description>Read: pin set as input</description>
120609 <description>Read: pin set as output</description>
120617 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
120624 <description>Set as output pin 23</description>
120631 <description>Read: pin set as input</description>
120636 <description>Read: pin set as output</description>
120644 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
120651 <description>Set as output pin 24</description>
120658 <description>Read: pin set as input</description>
120663 <description>Read: pin set as output</description>
120671 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
120678 <description>Set as output pin 25</description>
120685 <description>Read: pin set as input</description>
120690 <description>Read: pin set as output</description>
120698 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
120705 <description>Set as output pin 26</description>
120712 <description>Read: pin set as input</description>
120717 <description>Read: pin set as output</description>
120725 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
120732 <description>Set as output pin 27</description>
120739 <description>Read: pin set as input</description>
120744 <description>Read: pin set as output</description>
120752 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
120759 <description>Set as output pin 28</description>
120766 <description>Read: pin set as input</description>
120771 <description>Read: pin set as output</description>
120779 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
120786 <description>Set as output pin 29</description>
120793 <description>Read: pin set as input</description>
120798 <description>Read: pin set as output</description>
120806 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
120813 <description>Set as output pin 30</description>
120820 <description>Read: pin set as input</description>
120825 <description>Read: pin set as output</description>
120833 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
120840 <description>Set as output pin 31</description>
120847 <description>Read: pin set as input</description>
120852 <description>Read: pin set as output</description>
120860 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
120869 <description>DIR clear register</description>
120878 <description>Set as input pin 0</description>
120885 <description>Read: pin set as input</description>
120890 <description>Read: pin set as output</description>
120898 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
120905 <description>Set as input pin 1</description>
120912 <description>Read: pin set as input</description>
120917 <description>Read: pin set as output</description>
120925 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
120932 <description>Set as input pin 2</description>
120939 <description>Read: pin set as input</description>
120944 <description>Read: pin set as output</description>
120952 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
120959 <description>Set as input pin 3</description>
120966 <description>Read: pin set as input</description>
120971 <description>Read: pin set as output</description>
120979 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
120986 <description>Set as input pin 4</description>
120993 <description>Read: pin set as input</description>
120998 <description>Read: pin set as output</description>
121006 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
121013 <description>Set as input pin 5</description>
121020 <description>Read: pin set as input</description>
121025 <description>Read: pin set as output</description>
121033 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
121040 <description>Set as input pin 6</description>
121047 <description>Read: pin set as input</description>
121052 <description>Read: pin set as output</description>
121060 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
121067 <description>Set as input pin 7</description>
121074 <description>Read: pin set as input</description>
121079 <description>Read: pin set as output</description>
121087 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
121094 <description>Set as input pin 8</description>
121101 <description>Read: pin set as input</description>
121106 <description>Read: pin set as output</description>
121114 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
121121 <description>Set as input pin 9</description>
121128 <description>Read: pin set as input</description>
121133 <description>Read: pin set as output</description>
121141 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
121148 <description>Set as input pin 10</description>
121155 <description>Read: pin set as input</description>
121160 <description>Read: pin set as output</description>
121168 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
121175 <description>Set as input pin 11</description>
121182 <description>Read: pin set as input</description>
121187 <description>Read: pin set as output</description>
121195 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
121202 <description>Set as input pin 12</description>
121209 <description>Read: pin set as input</description>
121214 <description>Read: pin set as output</description>
121222 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
121229 <description>Set as input pin 13</description>
121236 <description>Read: pin set as input</description>
121241 <description>Read: pin set as output</description>
121249 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
121256 <description>Set as input pin 14</description>
121263 <description>Read: pin set as input</description>
121268 <description>Read: pin set as output</description>
121276 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
121283 <description>Set as input pin 15</description>
121290 <description>Read: pin set as input</description>
121295 <description>Read: pin set as output</description>
121303 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
121310 <description>Set as input pin 16</description>
121317 <description>Read: pin set as input</description>
121322 <description>Read: pin set as output</description>
121330 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
121337 <description>Set as input pin 17</description>
121344 <description>Read: pin set as input</description>
121349 <description>Read: pin set as output</description>
121357 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
121364 <description>Set as input pin 18</description>
121371 <description>Read: pin set as input</description>
121376 <description>Read: pin set as output</description>
121384 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
121391 <description>Set as input pin 19</description>
121398 <description>Read: pin set as input</description>
121403 <description>Read: pin set as output</description>
121411 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
121418 <description>Set as input pin 20</description>
121425 <description>Read: pin set as input</description>
121430 <description>Read: pin set as output</description>
121438 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
121445 <description>Set as input pin 21</description>
121452 <description>Read: pin set as input</description>
121457 <description>Read: pin set as output</description>
121465 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
121472 <description>Set as input pin 22</description>
121479 <description>Read: pin set as input</description>
121484 <description>Read: pin set as output</description>
121492 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
121499 <description>Set as input pin 23</description>
121506 <description>Read: pin set as input</description>
121511 <description>Read: pin set as output</description>
121519 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
121526 <description>Set as input pin 24</description>
121533 <description>Read: pin set as input</description>
121538 <description>Read: pin set as output</description>
121546 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
121553 <description>Set as input pin 25</description>
121560 <description>Read: pin set as input</description>
121565 <description>Read: pin set as output</description>
121573 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
121580 <description>Set as input pin 26</description>
121587 <description>Read: pin set as input</description>
121592 <description>Read: pin set as output</description>
121600 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
121607 <description>Set as input pin 27</description>
121614 <description>Read: pin set as input</description>
121619 <description>Read: pin set as output</description>
121627 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
121634 <description>Set as input pin 28</description>
121641 <description>Read: pin set as input</description>
121646 <description>Read: pin set as output</description>
121654 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
121661 <description>Set as input pin 29</description>
121668 <description>Read: pin set as input</description>
121673 <description>Read: pin set as output</description>
121681 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
121688 <description>Set as input pin 30</description>
121695 <description>Read: pin set as input</description>
121700 <description>Read: pin set as output</description>
121708 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
121715 <description>Set as input pin 31</description>
121722 <description>Read: pin set as input</description>
121727 <description>Read: pin set as output</description>
121735 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
121744 …<description>Latch register indicating what GPIO pins that have met the criteria set in the PIN_CN…
121752 …<description>Status on whether PIN0 has met criteria set in PIN_CNF[0].SENSE register. Write '1' t…
121758 <description>Criteria has not been met</description>
121763 <description>Criteria has been met</description>
121770 …<description>Status on whether PIN1 has met criteria set in PIN_CNF[1].SENSE register. Write '1' t…
121776 <description>Criteria has not been met</description>
121781 <description>Criteria has been met</description>
121788 …<description>Status on whether PIN2 has met criteria set in PIN_CNF[2].SENSE register. Write '1' t…
121794 <description>Criteria has not been met</description>
121799 <description>Criteria has been met</description>
121806 …<description>Status on whether PIN3 has met criteria set in PIN_CNF[3].SENSE register. Write '1' t…
121812 <description>Criteria has not been met</description>
121817 <description>Criteria has been met</description>
121824 …<description>Status on whether PIN4 has met criteria set in PIN_CNF[4].SENSE register. Write '1' t…
121830 <description>Criteria has not been met</description>
121835 <description>Criteria has been met</description>
121842 …<description>Status on whether PIN5 has met criteria set in PIN_CNF[5].SENSE register. Write '1' t…
121848 <description>Criteria has not been met</description>
121853 <description>Criteria has been met</description>
121860 …<description>Status on whether PIN6 has met criteria set in PIN_CNF[6].SENSE register. Write '1' t…
121866 <description>Criteria has not been met</description>
121871 <description>Criteria has been met</description>
121878 …<description>Status on whether PIN7 has met criteria set in PIN_CNF[7].SENSE register. Write '1' t…
121884 <description>Criteria has not been met</description>
121889 <description>Criteria has been met</description>
121896 …<description>Status on whether PIN8 has met criteria set in PIN_CNF[8].SENSE register. Write '1' t…
121902 <description>Criteria has not been met</description>
121907 <description>Criteria has been met</description>
121914 …<description>Status on whether PIN9 has met criteria set in PIN_CNF[9].SENSE register. Write '1' t…
121920 <description>Criteria has not been met</description>
121925 <description>Criteria has been met</description>
121932 …<description>Status on whether PIN10 has met criteria set in PIN_CNF[10].SENSE register. Write '1'…
121938 <description>Criteria has not been met</description>
121943 <description>Criteria has been met</description>
121950 …<description>Status on whether PIN11 has met criteria set in PIN_CNF[11].SENSE register. Write '1'…
121956 <description>Criteria has not been met</description>
121961 <description>Criteria has been met</description>
121968 …<description>Status on whether PIN12 has met criteria set in PIN_CNF[12].SENSE register. Write '1'…
121974 <description>Criteria has not been met</description>
121979 <description>Criteria has been met</description>
121986 …<description>Status on whether PIN13 has met criteria set in PIN_CNF[13].SENSE register. Write '1'…
121992 <description>Criteria has not been met</description>
121997 <description>Criteria has been met</description>
122004 …<description>Status on whether PIN14 has met criteria set in PIN_CNF[14].SENSE register. Write '1'…
122010 <description>Criteria has not been met</description>
122015 <description>Criteria has been met</description>
122022 …<description>Status on whether PIN15 has met criteria set in PIN_CNF[15].SENSE register. Write '1'…
122028 <description>Criteria has not been met</description>
122033 <description>Criteria has been met</description>
122040 …<description>Status on whether PIN16 has met criteria set in PIN_CNF[16].SENSE register. Write '1'…
122046 <description>Criteria has not been met</description>
122051 <description>Criteria has been met</description>
122058 …<description>Status on whether PIN17 has met criteria set in PIN_CNF[17].SENSE register. Write '1'…
122064 <description>Criteria has not been met</description>
122069 <description>Criteria has been met</description>
122076 …<description>Status on whether PIN18 has met criteria set in PIN_CNF[18].SENSE register. Write '1'…
122082 <description>Criteria has not been met</description>
122087 <description>Criteria has been met</description>
122094 …<description>Status on whether PIN19 has met criteria set in PIN_CNF[19].SENSE register. Write '1'…
122100 <description>Criteria has not been met</description>
122105 <description>Criteria has been met</description>
122112 …<description>Status on whether PIN20 has met criteria set in PIN_CNF[20].SENSE register. Write '1'…
122118 <description>Criteria has not been met</description>
122123 <description>Criteria has been met</description>
122130 …<description>Status on whether PIN21 has met criteria set in PIN_CNF[21].SENSE register. Write '1'…
122136 <description>Criteria has not been met</description>
122141 <description>Criteria has been met</description>
122148 …<description>Status on whether PIN22 has met criteria set in PIN_CNF[22].SENSE register. Write '1'…
122154 <description>Criteria has not been met</description>
122159 <description>Criteria has been met</description>
122166 …<description>Status on whether PIN23 has met criteria set in PIN_CNF[23].SENSE register. Write '1'…
122172 <description>Criteria has not been met</description>
122177 <description>Criteria has been met</description>
122184 …<description>Status on whether PIN24 has met criteria set in PIN_CNF[24].SENSE register. Write '1'…
122190 <description>Criteria has not been met</description>
122195 <description>Criteria has been met</description>
122202 …<description>Status on whether PIN25 has met criteria set in PIN_CNF[25].SENSE register. Write '1'…
122208 <description>Criteria has not been met</description>
122213 <description>Criteria has been met</description>
122220 …<description>Status on whether PIN26 has met criteria set in PIN_CNF[26].SENSE register. Write '1'…
122226 <description>Criteria has not been met</description>
122231 <description>Criteria has been met</description>
122238 …<description>Status on whether PIN27 has met criteria set in PIN_CNF[27].SENSE register. Write '1'…
122244 <description>Criteria has not been met</description>
122249 <description>Criteria has been met</description>
122256 …<description>Status on whether PIN28 has met criteria set in PIN_CNF[28].SENSE register. Write '1'…
122262 <description>Criteria has not been met</description>
122267 <description>Criteria has been met</description>
122274 …<description>Status on whether PIN29 has met criteria set in PIN_CNF[29].SENSE register. Write '1'…
122280 <description>Criteria has not been met</description>
122285 <description>Criteria has been met</description>
122292 …<description>Status on whether PIN30 has met criteria set in PIN_CNF[30].SENSE register. Write '1'…
122298 <description>Criteria has not been met</description>
122303 <description>Criteria has been met</description>
122310 …<description>Status on whether PIN31 has met criteria set in PIN_CNF[31].SENSE register. Write '1'…
122316 <description>Criteria has not been met</description>
122321 <description>Criteria has been met</description>
122330 <description>Select between default DETECT signal behavior and LDETECT mode</description>
122339 … <description>Select between default DETECT signal behavior and LDETECT mode</description>
122345 <description>DETECT directly connected to PIN DETECT signals</description>
122350 <description>Use the latched LDETECT behavior</description>
122359 <description>Enable retention for those GPIO registers marked as retained</description>
122367 <description>Enable retention for GPIO registers for Application domain</description>
122373 <description>Retention disabled</description>
122378 <description>Retention enabled</description>
122385 <description>Enable retention for GPIO registers for Radio core</description>
122391 <description>Retention disabled</description>
122396 <description>Retention enabled</description>
122405 <description>Unspecified</description>
122411 <description>Drive control for impedance matching of the pins in this port</description>
122420 <description>Enable 50 ohms impedance to the pins in this port</description>
122426 <description>Disabled</description>
122431 <description>Enable</description>
122438 <description>Enable 100 ohms impedance to the pins in this port</description>
122444 <description>Disabled</description>
122449 <description>Enable</description>
122456 <description>Enable 200 ohms impedance to the pins in this port</description>
122462 <description>Disabled</description>
122467 <description>Enable</description>
122474 <description>Enable 400 ohms impedance to the pins in this port</description>
122480 <description>Disabled</description>
122485 <description>Enable</description>
122492 <description>Enable 800 ohms impedance to the pins in this port</description>
122498 <description>Disabled</description>
122503 <description>Enable</description>
122510 <description>Enable 1600 ohms impedance to the pins in this port</description>
122516 <description>Disabled</description>
122521 <description>Enable</description>
122533 <description>Description collection: Pin n configuration of GPIO pin</description>
122541 <description>Pin direction. Same physical register as DIR register</description>
122547 <description>Configure pin as an input pin</description>
122552 <description>Configure pin as an output pin</description>
122559 <description>Connect or disconnect input buffer</description>
122565 <description>Connect input buffer</description>
122570 <description>Disconnect input buffer</description>
122577 <description>Pull configuration</description>
122583 <description>No pull</description>
122588 <description>Pull down on pin</description>
122593 <description>Pull up on pin</description>
122600 <description>Drive configuration for '0'</description>
122606 <description>Standard '0'</description>
122611 <description>High drive '0'</description>
122616 <description>Disconnect '0'(normally used for wired-or connections)</description>
122621 <description>Extra high drive '0'</description>
122628 <description>Drive configuration for '1'</description>
122634 <description>Standard '1'</description>
122639 <description>High drive '1'</description>
122644 <description>Disconnect '1'(normally used for wired-or connections)</description>
122649 <description>Extra high drive '1'</description>
122656 <description>Pin sensing mechanism</description>
122662 <description>Disabled</description>
122667 <description>Sense for high level</description>
122672 <description>Sense for low level</description>
122679 <description>Enable clock on the pin.</description>
122685 <description>Clock disabled</description>
122690 <description>Clock enabled</description>
122701 <description>GPIO Port 1</description>
122709 <description>GPIO Port 2</description>
122717 <description>GPIO Port 3</description>
122725 <description>GPIO Port 4</description>
122733 <description>GPIO Port 5</description>
122741 <description>GPIO Port 6</description>
122749 <description>GPIO Port 7</description>
122757 <description>GPIO Port 8</description>
122765 <description>GPIO Port 9</description>
122773 <description>Distributed programmable peripheral interconnect controller 2</description>
122781 <description>Analog to Digital Converter</description>
122799 <description>Start the ADC and prepare the result buffer in RAM</description>
122807 <description>Start the ADC and prepare the result buffer in RAM</description>
122813 <description>Trigger task</description>
122822 … <description>Take one ADC sample, if scan is enabled all channels are sampled</description>
122830 … <description>Take one ADC sample, if scan is enabled all channels are sampled</description>
122836 <description>Trigger task</description>
122845 <description>Stop the ADC and terminate any on-going conversion</description>
122853 <description>Stop the ADC and terminate any on-going conversion</description>
122859 <description>Trigger task</description>
122868 <description>Starts offset auto-calibration</description>
122876 <description>Starts offset auto-calibration</description>
122882 <description>Trigger task</description>
122891 <description>Subscribe configuration for task START</description>
122899 <description>DPPI channel that task START will subscribe to</description>
122910 <description>Disable subscription</description>
122915 <description>Enable subscription</description>
122924 <description>Subscribe configuration for task SAMPLE</description>
122932 <description>DPPI channel that task SAMPLE will subscribe to</description>
122943 <description>Disable subscription</description>
122948 <description>Enable subscription</description>
122957 <description>Subscribe configuration for task STOP</description>
122965 <description>DPPI channel that task STOP will subscribe to</description>
122976 <description>Disable subscription</description>
122981 <description>Enable subscription</description>
122990 <description>Subscribe configuration for task CALIBRATEOFFSET</description>
122998 <description>DPPI channel that task CALIBRATEOFFSET will subscribe to</description>
123009 <description>Disable subscription</description>
123014 <description>Enable subscription</description>
123023 <description>The ADC has started</description>
123031 <description>The ADC has started</description>
123037 <description>Event not generated</description>
123042 <description>Event generated</description>
123051 <description>The ADC has filled up the Result buffer</description>
123059 <description>The ADC has filled up the Result buffer</description>
123065 <description>Event not generated</description>
123070 <description>Event generated</description>
123079 …description>A conversion task has been completed. Depending on the mode, multiple conversions migh…
123087 …description>A conversion task has been completed. Depending on the mode, multiple conversions migh…
123093 <description>Event not generated</description>
123098 <description>Event generated</description>
123107 <description>A result is ready to get transferred to RAM.</description>
123115 <description>A result is ready to get transferred to RAM.</description>
123121 <description>Event not generated</description>
123126 <description>Event generated</description>
123135 <description>Calibration is complete</description>
123143 <description>Calibration is complete</description>
123149 <description>Event not generated</description>
123154 <description>Event generated</description>
123163 <description>The ADC has stopped</description>
123171 <description>The ADC has stopped</description>
123177 <description>Event not generated</description>
123182 <description>Event generated</description>
123193 <description>Peripheral events.</description>
123199 … <description>Description cluster: Last results is equal or above CH[n].LIMIT.HIGH</description>
123207 <description>Last results is equal or above CH[n].LIMIT.HIGH</description>
123213 <description>Event not generated</description>
123218 <description>Event generated</description>
123227 … <description>Description cluster: Last results is equal or below CH[n].LIMIT.LOW</description>
123235 <description>Last results is equal or below CH[n].LIMIT.LOW</description>
123241 <description>Event not generated</description>
123246 <description>Event generated</description>
123256 <description>Publish configuration for event STARTED</description>
123264 <description>DPPI channel that event STARTED will publish to</description>
123275 <description>Disable publishing</description>
123280 <description>Enable publishing</description>
123289 <description>Publish configuration for event END</description>
123297 <description>DPPI channel that event END will publish to</description>
123308 <description>Disable publishing</description>
123313 <description>Enable publishing</description>
123322 <description>Publish configuration for event DONE</description>
123330 <description>DPPI channel that event DONE will publish to</description>
123341 <description>Disable publishing</description>
123346 <description>Enable publishing</description>
123355 <description>Publish configuration for event RESULTDONE</description>
123363 <description>DPPI channel that event RESULTDONE will publish to</description>
123374 <description>Disable publishing</description>
123379 <description>Enable publishing</description>
123388 <description>Publish configuration for event CALIBRATEDONE</description>
123396 <description>DPPI channel that event CALIBRATEDONE will publish to</description>
123407 <description>Disable publishing</description>
123412 <description>Enable publishing</description>
123421 <description>Publish configuration for event STOPPED</description>
123429 <description>DPPI channel that event STOPPED will publish to</description>
123440 <description>Disable publishing</description>
123445 <description>Enable publishing</description>
123456 <description>Publish configuration for events</description>
123462 … <description>Description cluster: Publish configuration for event CH[n].LIMITH</description>
123470 <description>DPPI channel that event CH[n].LIMITH will publish to</description>
123481 <description>Disable publishing</description>
123486 <description>Enable publishing</description>
123495 … <description>Description cluster: Publish configuration for event CH[n].LIMITL</description>
123503 <description>DPPI channel that event CH[n].LIMITL will publish to</description>
123514 <description>Disable publishing</description>
123519 <description>Enable publishing</description>
123529 <description>Enable or disable interrupt</description>
123537 <description>Enable or disable interrupt for event STARTED</description>
123543 <description>Disable</description>
123548 <description>Enable</description>
123555 <description>Enable or disable interrupt for event END</description>
123561 <description>Disable</description>
123566 <description>Enable</description>
123573 <description>Enable or disable interrupt for event DONE</description>
123579 <description>Disable</description>
123584 <description>Enable</description>
123591 <description>Enable or disable interrupt for event RESULTDONE</description>
123597 <description>Disable</description>
123602 <description>Enable</description>
123609 <description>Enable or disable interrupt for event CALIBRATEDONE</description>
123615 <description>Disable</description>
123620 <description>Enable</description>
123627 <description>Enable or disable interrupt for event STOPPED</description>
123633 <description>Disable</description>
123638 <description>Enable</description>
123645 <description>Enable or disable interrupt for event CH0LIMITH</description>
123651 <description>Disable</description>
123656 <description>Enable</description>
123663 <description>Enable or disable interrupt for event CH0LIMITL</description>
123669 <description>Disable</description>
123674 <description>Enable</description>
123681 <description>Enable or disable interrupt for event CH1LIMITH</description>
123687 <description>Disable</description>
123692 <description>Enable</description>
123699 <description>Enable or disable interrupt for event CH1LIMITL</description>
123705 <description>Disable</description>
123710 <description>Enable</description>
123717 <description>Enable or disable interrupt for event CH2LIMITH</description>
123723 <description>Disable</description>
123728 <description>Enable</description>
123735 <description>Enable or disable interrupt for event CH2LIMITL</description>
123741 <description>Disable</description>
123746 <description>Enable</description>
123753 <description>Enable or disable interrupt for event CH3LIMITH</description>
123759 <description>Disable</description>
123764 <description>Enable</description>
123771 <description>Enable or disable interrupt for event CH3LIMITL</description>
123777 <description>Disable</description>
123782 <description>Enable</description>
123789 <description>Enable or disable interrupt for event CH4LIMITH</description>
123795 <description>Disable</description>
123800 <description>Enable</description>
123807 <description>Enable or disable interrupt for event CH4LIMITL</description>
123813 <description>Disable</description>
123818 <description>Enable</description>
123825 <description>Enable or disable interrupt for event CH5LIMITH</description>
123831 <description>Disable</description>
123836 <description>Enable</description>
123843 <description>Enable or disable interrupt for event CH5LIMITL</description>
123849 <description>Disable</description>
123854 <description>Enable</description>
123861 <description>Enable or disable interrupt for event CH6LIMITH</description>
123867 <description>Disable</description>
123872 <description>Enable</description>
123879 <description>Enable or disable interrupt for event CH6LIMITL</description>
123885 <description>Disable</description>
123890 <description>Enable</description>
123897 <description>Enable or disable interrupt for event CH7LIMITH</description>
123903 <description>Disable</description>
123908 <description>Enable</description>
123915 <description>Enable or disable interrupt for event CH7LIMITL</description>
123921 <description>Disable</description>
123926 <description>Enable</description>
123935 <description>Enable interrupt</description>
123943 <description>Write '1' to enable interrupt for event STARTED</description>
123950 <description>Read: Disabled</description>
123955 <description>Read: Enabled</description>
123963 <description>Enable</description>
123970 <description>Write '1' to enable interrupt for event END</description>
123977 <description>Read: Disabled</description>
123982 <description>Read: Enabled</description>
123990 <description>Enable</description>
123997 <description>Write '1' to enable interrupt for event DONE</description>
124004 <description>Read: Disabled</description>
124009 <description>Read: Enabled</description>
124017 <description>Enable</description>
124024 <description>Write '1' to enable interrupt for event RESULTDONE</description>
124031 <description>Read: Disabled</description>
124036 <description>Read: Enabled</description>
124044 <description>Enable</description>
124051 <description>Write '1' to enable interrupt for event CALIBRATEDONE</description>
124058 <description>Read: Disabled</description>
124063 <description>Read: Enabled</description>
124071 <description>Enable</description>
124078 <description>Write '1' to enable interrupt for event STOPPED</description>
124085 <description>Read: Disabled</description>
124090 <description>Read: Enabled</description>
124098 <description>Enable</description>
124105 <description>Write '1' to enable interrupt for event CH0LIMITH</description>
124112 <description>Read: Disabled</description>
124117 <description>Read: Enabled</description>
124125 <description>Enable</description>
124132 <description>Write '1' to enable interrupt for event CH0LIMITL</description>
124139 <description>Read: Disabled</description>
124144 <description>Read: Enabled</description>
124152 <description>Enable</description>
124159 <description>Write '1' to enable interrupt for event CH1LIMITH</description>
124166 <description>Read: Disabled</description>
124171 <description>Read: Enabled</description>
124179 <description>Enable</description>
124186 <description>Write '1' to enable interrupt for event CH1LIMITL</description>
124193 <description>Read: Disabled</description>
124198 <description>Read: Enabled</description>
124206 <description>Enable</description>
124213 <description>Write '1' to enable interrupt for event CH2LIMITH</description>
124220 <description>Read: Disabled</description>
124225 <description>Read: Enabled</description>
124233 <description>Enable</description>
124240 <description>Write '1' to enable interrupt for event CH2LIMITL</description>
124247 <description>Read: Disabled</description>
124252 <description>Read: Enabled</description>
124260 <description>Enable</description>
124267 <description>Write '1' to enable interrupt for event CH3LIMITH</description>
124274 <description>Read: Disabled</description>
124279 <description>Read: Enabled</description>
124287 <description>Enable</description>
124294 <description>Write '1' to enable interrupt for event CH3LIMITL</description>
124301 <description>Read: Disabled</description>
124306 <description>Read: Enabled</description>
124314 <description>Enable</description>
124321 <description>Write '1' to enable interrupt for event CH4LIMITH</description>
124328 <description>Read: Disabled</description>
124333 <description>Read: Enabled</description>
124341 <description>Enable</description>
124348 <description>Write '1' to enable interrupt for event CH4LIMITL</description>
124355 <description>Read: Disabled</description>
124360 <description>Read: Enabled</description>
124368 <description>Enable</description>
124375 <description>Write '1' to enable interrupt for event CH5LIMITH</description>
124382 <description>Read: Disabled</description>
124387 <description>Read: Enabled</description>
124395 <description>Enable</description>
124402 <description>Write '1' to enable interrupt for event CH5LIMITL</description>
124409 <description>Read: Disabled</description>
124414 <description>Read: Enabled</description>
124422 <description>Enable</description>
124429 <description>Write '1' to enable interrupt for event CH6LIMITH</description>
124436 <description>Read: Disabled</description>
124441 <description>Read: Enabled</description>
124449 <description>Enable</description>
124456 <description>Write '1' to enable interrupt for event CH6LIMITL</description>
124463 <description>Read: Disabled</description>
124468 <description>Read: Enabled</description>
124476 <description>Enable</description>
124483 <description>Write '1' to enable interrupt for event CH7LIMITH</description>
124490 <description>Read: Disabled</description>
124495 <description>Read: Enabled</description>
124503 <description>Enable</description>
124510 <description>Write '1' to enable interrupt for event CH7LIMITL</description>
124517 <description>Read: Disabled</description>
124522 <description>Read: Enabled</description>
124530 <description>Enable</description>
124539 <description>Disable interrupt</description>
124547 <description>Write '1' to disable interrupt for event STARTED</description>
124554 <description>Read: Disabled</description>
124559 <description>Read: Enabled</description>
124567 <description>Disable</description>
124574 <description>Write '1' to disable interrupt for event END</description>
124581 <description>Read: Disabled</description>
124586 <description>Read: Enabled</description>
124594 <description>Disable</description>
124601 <description>Write '1' to disable interrupt for event DONE</description>
124608 <description>Read: Disabled</description>
124613 <description>Read: Enabled</description>
124621 <description>Disable</description>
124628 <description>Write '1' to disable interrupt for event RESULTDONE</description>
124635 <description>Read: Disabled</description>
124640 <description>Read: Enabled</description>
124648 <description>Disable</description>
124655 <description>Write '1' to disable interrupt for event CALIBRATEDONE</description>
124662 <description>Read: Disabled</description>
124667 <description>Read: Enabled</description>
124675 <description>Disable</description>
124682 <description>Write '1' to disable interrupt for event STOPPED</description>
124689 <description>Read: Disabled</description>
124694 <description>Read: Enabled</description>
124702 <description>Disable</description>
124709 <description>Write '1' to disable interrupt for event CH0LIMITH</description>
124716 <description>Read: Disabled</description>
124721 <description>Read: Enabled</description>
124729 <description>Disable</description>
124736 <description>Write '1' to disable interrupt for event CH0LIMITL</description>
124743 <description>Read: Disabled</description>
124748 <description>Read: Enabled</description>
124756 <description>Disable</description>
124763 <description>Write '1' to disable interrupt for event CH1LIMITH</description>
124770 <description>Read: Disabled</description>
124775 <description>Read: Enabled</description>
124783 <description>Disable</description>
124790 <description>Write '1' to disable interrupt for event CH1LIMITL</description>
124797 <description>Read: Disabled</description>
124802 <description>Read: Enabled</description>
124810 <description>Disable</description>
124817 <description>Write '1' to disable interrupt for event CH2LIMITH</description>
124824 <description>Read: Disabled</description>
124829 <description>Read: Enabled</description>
124837 <description>Disable</description>
124844 <description>Write '1' to disable interrupt for event CH2LIMITL</description>
124851 <description>Read: Disabled</description>
124856 <description>Read: Enabled</description>
124864 <description>Disable</description>
124871 <description>Write '1' to disable interrupt for event CH3LIMITH</description>
124878 <description>Read: Disabled</description>
124883 <description>Read: Enabled</description>
124891 <description>Disable</description>
124898 <description>Write '1' to disable interrupt for event CH3LIMITL</description>
124905 <description>Read: Disabled</description>
124910 <description>Read: Enabled</description>
124918 <description>Disable</description>
124925 <description>Write '1' to disable interrupt for event CH4LIMITH</description>
124932 <description>Read: Disabled</description>
124937 <description>Read: Enabled</description>
124945 <description>Disable</description>
124952 <description>Write '1' to disable interrupt for event CH4LIMITL</description>
124959 <description>Read: Disabled</description>
124964 <description>Read: Enabled</description>
124972 <description>Disable</description>
124979 <description>Write '1' to disable interrupt for event CH5LIMITH</description>
124986 <description>Read: Disabled</description>
124991 <description>Read: Enabled</description>
124999 <description>Disable</description>
125006 <description>Write '1' to disable interrupt for event CH5LIMITL</description>
125013 <description>Read: Disabled</description>
125018 <description>Read: Enabled</description>
125026 <description>Disable</description>
125033 <description>Write '1' to disable interrupt for event CH6LIMITH</description>
125040 <description>Read: Disabled</description>
125045 <description>Read: Enabled</description>
125053 <description>Disable</description>
125060 <description>Write '1' to disable interrupt for event CH6LIMITL</description>
125067 <description>Read: Disabled</description>
125072 <description>Read: Enabled</description>
125080 <description>Disable</description>
125087 <description>Write '1' to disable interrupt for event CH7LIMITH</description>
125094 <description>Read: Disabled</description>
125099 <description>Read: Enabled</description>
125107 <description>Disable</description>
125114 <description>Write '1' to disable interrupt for event CH7LIMITL</description>
125121 <description>Read: Disabled</description>
125126 <description>Read: Enabled</description>
125134 <description>Disable</description>
125143 <description>Status</description>
125151 <description>Status</description>
125157 <description>ADC is ready. No on-going conversion.</description>
125162 <description>ADC is busy. Single conversion in progress.</description>
125171 <description>Unspecified</description>
125179 <description>Description collection: Linearity calibration coefficient</description>
125187 <description>value</description>
125196 <description>Enable or disable ADC</description>
125204 <description>Enable or disable ADC</description>
125210 <description>Disable ADC</description>
125215 <description>Enable ADC</description>
125226 <description>Unspecified</description>
125232 <description>Description cluster: Input positive pin selection for CH[n]</description>
125240 <description>Analog positive input pin select</description>
125246 <description>GPIO Port selection</description>
125252 <description>Connection</description>
125258 <description>Not connected</description>
125263 <description>Select analog input</description>
125272 <description>Description cluster: Input negative pin selection for CH[n]</description>
125280 <description>Analog negative input pin select</description>
125286 <description>GPIO Port selection</description>
125292 <description>Connection</description>
125298 <description>Not connected</description>
125303 <description>Select analog input</description>
125312 <description>Description cluster: Input configuration for CH[n]</description>
125320 <description>Positive channel resistor control</description>
125326 <description>Bypass resistor ladder</description>
125331 <description>Pull-down to GND</description>
125336 <description>Pull-up to VDD_AO_1V8</description>
125341 <description>Set input at VDD_AO_1V8/2</description>
125348 <description>Negative channel resistor control</description>
125354 <description>Bypass resistor ladder</description>
125359 <description>Pull-down to GND</description>
125364 <description>Pull-up to VDD_AO_1V8</description>
125369 <description>Set input at VDD_AO_1V8/2</description>
125376 <description>Gain control</description>
125382 <description>2/3</description>
125387 <description>1</description>
125392 <description>2</description>
125397 <description>4</description>
125404 <description>Enable burst mode</description>
125410 <description>Burst mode is disabled (normal operation)</description>
125415 …<description>Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, …
125422 <description>Reference control</description>
125428 <description>Internal reference (1.024 V)</description>
125433 <description>External reference given at PADC_EXT_REF_1V2</description>
125440 <description>Enable differential mode</description>
125446 …<description>Single ended, PSELN will be ignored, negative input to ADC shorted to GND</descriptio…
125451 <description>Differential</description>
125458 …<description>Acquisition time, the time the ADC uses to sample the input voltage. Resulting acquis…
125464 … <description>Conversion time. Resulting conversion time is ((TCONV+1) x 250 ns)</description>
125472 … <description>Description cluster: High/low limits for event monitoring a channel</description>
125480 <description>Low level limit</description>
125486 <description>High level limit</description>
125495 <description>Resolution configuration</description>
125503 <description>Set the resolution</description>
125509 <description>8 bit</description>
125514 <description>10 bit</description>
125519 <description>12 bit</description>
125524 <description>14 bit</description>
125533 …description>Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTIO…
125541 <description>Oversample control</description>
125547 <description>Bypass oversampling</description>
125552 <description>Oversample 2x</description>
125557 <description>Oversample 4x</description>
125562 <description>Oversample 8x</description>
125567 <description>Oversample 16x</description>
125572 <description>Oversample 32x</description>
125577 <description>Oversample 64x</description>
125582 <description>Oversample 128x</description>
125587 <description>Oversample 256x</description>
125596 <description>Controls normal or continuous sample rate</description>
125604 <description>Capture and compare value. Sample rate is 16 MHz/CC</description>
125610 <description>Select mode for sample rate control</description>
125616 <description>Rate is controlled from SAMPLE task</description>
125621 … <description>Rate is controlled from local timer (use CC to control the rate)</description>
125630 <description>RESULT EasyDMA channel</description>
125636 <description>Data pointer</description>
125644 <description>Data pointer</description>
125652 <description>Maximum number of buffer bytes to transfer</description>
125660 <description>Maximum number of buffer bytes to transfer</description>
125668 <description>Number of buffer bytes transferred since last START</description>
125676 …<description>Number of buffer bytes transferred since last START. This register can be read after …
125687 <description>Comparator</description>
125705 <description>Start comparator</description>
125713 <description>Start comparator</description>
125719 <description>Trigger task</description>
125728 <description>Stop comparator</description>
125736 <description>Stop comparator</description>
125742 <description>Trigger task</description>
125751 <description>Sample comparator value</description>
125759 <description>Sample comparator value</description>
125765 <description>Trigger task</description>
125774 <description>Subscribe configuration for task START</description>
125782 <description>DPPI channel that task START will subscribe to</description>
125793 <description>Disable subscription</description>
125798 <description>Enable subscription</description>
125807 <description>Subscribe configuration for task STOP</description>
125815 <description>DPPI channel that task STOP will subscribe to</description>
125826 <description>Disable subscription</description>
125831 <description>Enable subscription</description>
125840 <description>Subscribe configuration for task SAMPLE</description>
125848 <description>DPPI channel that task SAMPLE will subscribe to</description>
125859 <description>Disable subscription</description>
125864 <description>Enable subscription</description>
125873 <description>COMP is ready and output is valid</description>
125881 <description>COMP is ready and output is valid</description>
125887 <description>Event not generated</description>
125892 <description>Event generated</description>
125901 <description>Downward crossing</description>
125909 <description>Downward crossing</description>
125915 <description>Event not generated</description>
125920 <description>Event generated</description>
125929 <description>Upward crossing</description>
125937 <description>Upward crossing</description>
125943 <description>Event not generated</description>
125948 <description>Event generated</description>
125957 <description>Downward or upward crossing</description>
125965 <description>Downward or upward crossing</description>
125971 <description>Event not generated</description>
125976 <description>Event generated</description>
125985 <description>Publish configuration for event READY</description>
125993 <description>DPPI channel that event READY will publish to</description>
126004 <description>Disable publishing</description>
126009 <description>Enable publishing</description>
126018 <description>Publish configuration for event DOWN</description>
126026 <description>DPPI channel that event DOWN will publish to</description>
126037 <description>Disable publishing</description>
126042 <description>Enable publishing</description>
126051 <description>Publish configuration for event UP</description>
126059 <description>DPPI channel that event UP will publish to</description>
126070 <description>Disable publishing</description>
126075 <description>Enable publishing</description>
126084 <description>Publish configuration for event CROSS</description>
126092 <description>DPPI channel that event CROSS will publish to</description>
126103 <description>Disable publishing</description>
126108 <description>Enable publishing</description>
126117 <description>Shortcuts between local events and tasks</description>
126125 <description>Shortcut between event READY and task SAMPLE</description>
126131 <description>Disable shortcut</description>
126136 <description>Enable shortcut</description>
126143 <description>Shortcut between event READY and task STOP</description>
126149 <description>Disable shortcut</description>
126154 <description>Enable shortcut</description>
126161 <description>Shortcut between event DOWN and task STOP</description>
126167 <description>Disable shortcut</description>
126172 <description>Enable shortcut</description>
126179 <description>Shortcut between event UP and task STOP</description>
126185 <description>Disable shortcut</description>
126190 <description>Enable shortcut</description>
126197 <description>Shortcut between event CROSS and task STOP</description>
126203 <description>Disable shortcut</description>
126208 <description>Enable shortcut</description>
126217 <description>Enable or disable interrupt</description>
126225 <description>Enable or disable interrupt for event READY</description>
126231 <description>Disable</description>
126236 <description>Enable</description>
126243 <description>Enable or disable interrupt for event DOWN</description>
126249 <description>Disable</description>
126254 <description>Enable</description>
126261 <description>Enable or disable interrupt for event UP</description>
126267 <description>Disable</description>
126272 <description>Enable</description>
126279 <description>Enable or disable interrupt for event CROSS</description>
126285 <description>Disable</description>
126290 <description>Enable</description>
126299 <description>Enable interrupt</description>
126307 <description>Write '1' to enable interrupt for event READY</description>
126314 <description>Read: Disabled</description>
126319 <description>Read: Enabled</description>
126327 <description>Enable</description>
126334 <description>Write '1' to enable interrupt for event DOWN</description>
126341 <description>Read: Disabled</description>
126346 <description>Read: Enabled</description>
126354 <description>Enable</description>
126361 <description>Write '1' to enable interrupt for event UP</description>
126368 <description>Read: Disabled</description>
126373 <description>Read: Enabled</description>
126381 <description>Enable</description>
126388 <description>Write '1' to enable interrupt for event CROSS</description>
126395 <description>Read: Disabled</description>
126400 <description>Read: Enabled</description>
126408 <description>Enable</description>
126417 <description>Disable interrupt</description>
126425 <description>Write '1' to disable interrupt for event READY</description>
126432 <description>Read: Disabled</description>
126437 <description>Read: Enabled</description>
126445 <description>Disable</description>
126452 <description>Write '1' to disable interrupt for event DOWN</description>
126459 <description>Read: Disabled</description>
126464 <description>Read: Enabled</description>
126472 <description>Disable</description>
126479 <description>Write '1' to disable interrupt for event UP</description>
126486 <description>Read: Disabled</description>
126491 <description>Read: Enabled</description>
126499 <description>Disable</description>
126506 <description>Write '1' to disable interrupt for event CROSS</description>
126513 <description>Read: Disabled</description>
126518 <description>Read: Enabled</description>
126526 <description>Disable</description>
126535 <description>Pending interrupts</description>
126543 <description>Read pending status of interrupt for event READY</description>
126550 <description>Read: Not pending</description>
126555 <description>Read: Pending</description>
126562 <description>Read pending status of interrupt for event DOWN</description>
126569 <description>Read: Not pending</description>
126574 <description>Read: Pending</description>
126581 <description>Read pending status of interrupt for event UP</description>
126588 <description>Read: Not pending</description>
126593 <description>Read: Pending</description>
126600 <description>Read pending status of interrupt for event CROSS</description>
126607 <description>Read: Not pending</description>
126612 <description>Read: Pending</description>
126621 <description>Compare result</description>
126629 <description>Result of last compare. Decision point SAMPLE task.</description>
126635 … <description>Input voltage is below the threshold (VIN+ &lt; VIN-)</description>
126640 … <description>Input voltage is above the threshold (VIN+ &gt; VIN-)</description>
126649 <description>COMP enable</description>
126657 <description>Enable or disable COMP</description>
126663 <description>Disable</description>
126668 <description>Enable</description>
126677 <description>Pin select</description>
126685 <description>Analog pin select</description>
126691 <description>GPIO Port selection</description>
126699 <description>Reference source select for single-ended mode</description>
126707 <description>Reference select</description>
126713 … <description>VREF = internal 1.2 V reference (AVDD_AO_1V8 &gt;= 1.7 V)</description>
126718 <description>VREF = AVDD_AO_1V8</description>
126723 <description>VREF = AREF</description>
126732 <description>External reference select</description>
126740 <description>External analog reference pin select</description>
126746 <description>GPIO Port selection</description>
126754 <description>Threshold configuration for hysteresis unit</description>
126762 <description>VDOWN = (THDOWN+1)/64*VREF</description>
126768 <description>VUP = (THUP+1)/64*VREF</description>
126776 <description>Mode configuration</description>
126784 <description>Speed and power modes</description>
126790 <description>Low-power mode</description>
126795 <description>High-speed mode</description>
126802 <description>Main operation modes</description>
126808 <description>Single-ended mode</description>
126813 <description>Differential mode</description>
126822 <description>Comparator hysteresis enable</description>
126830 <description>Comparator hysteresis</description>
126836 <description>Comparator hysteresis disabled</description>
126841 <description>Comparator hysteresis enabled</description>
126850 <description>Current source select on analog input</description>
126858 <description>Current source select on analog input</description>
126864 <description>Current source disabled</description>
126869 <description>Current source enabled (+/- 2.5 uA)</description>
126874 <description>Current source enabled (+/- 5 uA)</description>
126879 <description>Current source enabled (+/- 10 uA)</description>
126890 <description>Low-power comparator</description>
126909 <description>Start comparator</description>
126917 <description>Start comparator</description>
126923 <description>Trigger task</description>
126932 <description>Stop comparator</description>
126940 <description>Stop comparator</description>
126946 <description>Trigger task</description>
126955 <description>Sample comparator value</description>
126963 <description>Sample comparator value</description>
126969 <description>Trigger task</description>
126978 <description>Subscribe configuration for task START</description>
126986 <description>DPPI channel that task START will subscribe to</description>
126997 <description>Disable subscription</description>
127002 <description>Enable subscription</description>
127011 <description>Subscribe configuration for task STOP</description>
127019 <description>DPPI channel that task STOP will subscribe to</description>
127030 <description>Disable subscription</description>
127035 <description>Enable subscription</description>
127044 <description>Subscribe configuration for task SAMPLE</description>
127052 <description>DPPI channel that task SAMPLE will subscribe to</description>
127063 <description>Disable subscription</description>
127068 <description>Enable subscription</description>
127077 <description>LPCOMP is ready and output is valid</description>
127085 <description>LPCOMP is ready and output is valid</description>
127091 <description>Event not generated</description>
127096 <description>Event generated</description>
127105 <description>Downward crossing</description>
127113 <description>Downward crossing</description>
127119 <description>Event not generated</description>
127124 <description>Event generated</description>
127133 <description>Upward crossing</description>
127141 <description>Upward crossing</description>
127147 <description>Event not generated</description>
127152 <description>Event generated</description>
127161 <description>Downward or upward crossing</description>
127169 <description>Downward or upward crossing</description>
127175 <description>Event not generated</description>
127180 <description>Event generated</description>
127189 <description>Publish configuration for event READY</description>
127197 <description>DPPI channel that event READY will publish to</description>
127208 <description>Disable publishing</description>
127213 <description>Enable publishing</description>
127222 <description>Publish configuration for event DOWN</description>
127230 <description>DPPI channel that event DOWN will publish to</description>
127241 <description>Disable publishing</description>
127246 <description>Enable publishing</description>
127255 <description>Publish configuration for event UP</description>
127263 <description>DPPI channel that event UP will publish to</description>
127274 <description>Disable publishing</description>
127279 <description>Enable publishing</description>
127288 <description>Publish configuration for event CROSS</description>
127296 <description>DPPI channel that event CROSS will publish to</description>
127307 <description>Disable publishing</description>
127312 <description>Enable publishing</description>
127321 <description>Shortcuts between local events and tasks</description>
127329 <description>Shortcut between event READY and task SAMPLE</description>
127335 <description>Disable shortcut</description>
127340 <description>Enable shortcut</description>
127347 <description>Shortcut between event READY and task STOP</description>
127353 <description>Disable shortcut</description>
127358 <description>Enable shortcut</description>
127365 <description>Shortcut between event DOWN and task STOP</description>
127371 <description>Disable shortcut</description>
127376 <description>Enable shortcut</description>
127383 <description>Shortcut between event UP and task STOP</description>
127389 <description>Disable shortcut</description>
127394 <description>Enable shortcut</description>
127401 <description>Shortcut between event CROSS and task STOP</description>
127407 <description>Disable shortcut</description>
127412 <description>Enable shortcut</description>
127421 <description>Enable or disable interrupt</description>
127429 <description>Enable or disable interrupt for event READY</description>
127435 <description>Disable</description>
127440 <description>Enable</description>
127447 <description>Enable or disable interrupt for event DOWN</description>
127453 <description>Disable</description>
127458 <description>Enable</description>
127465 <description>Enable or disable interrupt for event UP</description>
127471 <description>Disable</description>
127476 <description>Enable</description>
127483 <description>Enable or disable interrupt for event CROSS</description>
127489 <description>Disable</description>
127494 <description>Enable</description>
127503 <description>Enable interrupt</description>
127511 <description>Write '1' to enable interrupt for event READY</description>
127518 <description>Read: Disabled</description>
127523 <description>Read: Enabled</description>
127531 <description>Enable</description>
127538 <description>Write '1' to enable interrupt for event DOWN</description>
127545 <description>Read: Disabled</description>
127550 <description>Read: Enabled</description>
127558 <description>Enable</description>
127565 <description>Write '1' to enable interrupt for event UP</description>
127572 <description>Read: Disabled</description>
127577 <description>Read: Enabled</description>
127585 <description>Enable</description>
127592 <description>Write '1' to enable interrupt for event CROSS</description>
127599 <description>Read: Disabled</description>
127604 <description>Read: Enabled</description>
127612 <description>Enable</description>
127621 <description>Disable interrupt</description>
127629 <description>Write '1' to disable interrupt for event READY</description>
127636 <description>Read: Disabled</description>
127641 <description>Read: Enabled</description>
127649 <description>Disable</description>
127656 <description>Write '1' to disable interrupt for event DOWN</description>
127663 <description>Read: Disabled</description>
127668 <description>Read: Enabled</description>
127676 <description>Disable</description>
127683 <description>Write '1' to disable interrupt for event UP</description>
127690 <description>Read: Disabled</description>
127695 <description>Read: Enabled</description>
127703 <description>Disable</description>
127710 <description>Write '1' to disable interrupt for event CROSS</description>
127717 <description>Read: Disabled</description>
127722 <description>Read: Enabled</description>
127730 <description>Disable</description>
127739 <description>Pending interrupts</description>
127747 <description>Read pending status of interrupt for event READY</description>
127754 <description>Read: Not pending</description>
127759 <description>Read: Pending</description>
127766 <description>Read pending status of interrupt for event DOWN</description>
127773 <description>Read: Not pending</description>
127778 <description>Read: Pending</description>
127785 <description>Read pending status of interrupt for event UP</description>
127792 <description>Read: Not pending</description>
127797 <description>Read: Pending</description>
127804 <description>Read pending status of interrupt for event CROSS</description>
127811 <description>Read: Not pending</description>
127816 <description>Read: Pending</description>
127825 <description>Compare result</description>
127833 <description>Result of last compare. Decision point SAMPLE task.</description>
127839 … <description>Input voltage is below the reference threshold (VIN+ &lt; VIN-)</description>
127844 … <description>Input voltage is above the reference threshold (VIN+ &gt; VIN-)</description>
127853 <description>Enable LPCOMP</description>
127861 <description>Enable or disable LPCOMP</description>
127867 <description>Disable</description>
127872 <description>Enable</description>
127881 <description>Input pin select</description>
127889 <description>Analog pin select</description>
127895 <description>GPIO Port selection</description>
127903 <description>Reference select</description>
127911 <description>Reference select</description>
127917 <description>VDD * 1/8 selected as reference</description>
127922 <description>VDD * 2/8 selected as reference</description>
127927 <description>VDD * 3/8 selected as reference</description>
127932 <description>VDD * 4/8 selected as reference</description>
127937 <description>VDD * 5/8 selected as reference</description>
127942 <description>VDD * 6/8 selected as reference</description>
127947 <description>VDD * 7/8 selected as reference</description>
127952 <description>External analog reference selected</description>
127957 <description>VDD * 1/16 selected as reference</description>
127962 <description>VDD * 3/16 selected as reference</description>
127967 <description>VDD * 5/16 selected as reference</description>
127972 <description>VDD * 7/16 selected as reference</description>
127977 <description>VDD * 9/16 selected as reference</description>
127982 <description>VDD * 11/16 selected as reference</description>
127987 <description>VDD * 13/16 selected as reference</description>
127992 <description>VDD * 15/16 selected as reference</description>
128001 <description>External reference select</description>
128009 <description>External analog reference pin select</description>
128015 <description>GPIO Port selection</description>
128023 <description>Analog detect configuration</description>
128031 <description>Analog detect configuration</description>
128037 …<description>Generate ANADETECT on crossing, both upward crossing and downward crossing</descripti…
128042 <description>Generate ANADETECT on upward crossing only</description>
128047 <description>Generate ANADETECT on downward crossing only</description>
128056 <description>Comparator hysteresis enable</description>
128064 <description>Comparator hysteresis enable</description>
128070 <description>Comparator hysteresis disabled</description>
128075 <description>Comparator hysteresis enabled</description>
128086 <description>Temperature Sensor</description>
128104 <description>Start temperature measurement</description>
128112 <description>Start temperature measurement</description>
128118 <description>Trigger task</description>
128127 <description>Stop temperature measurement</description>
128135 <description>Stop temperature measurement</description>
128141 <description>Trigger task</description>
128150 <description>Subscribe configuration for task START</description>
128158 <description>DPPI channel that task START will subscribe to</description>
128169 <description>Disable subscription</description>
128174 <description>Enable subscription</description>
128183 <description>Subscribe configuration for task STOP</description>
128191 <description>DPPI channel that task STOP will subscribe to</description>
128202 <description>Disable subscription</description>
128207 <description>Enable subscription</description>
128216 <description>Temperature measurement complete, data ready</description>
128224 <description>Temperature measurement complete, data ready</description>
128230 <description>Event not generated</description>
128235 <description>Event generated</description>
128244 <description>Publish configuration for event DATARDY</description>
128252 <description>DPPI channel that event DATARDY will publish to</description>
128263 <description>Disable publishing</description>
128268 <description>Enable publishing</description>
128277 <description>Enable interrupt</description>
128285 <description>Write '1' to enable interrupt for event DATARDY</description>
128292 <description>Read: Disabled</description>
128297 <description>Read: Enabled</description>
128305 <description>Enable</description>
128314 <description>Disable interrupt</description>
128322 <description>Write '1' to disable interrupt for event DATARDY</description>
128329 <description>Read: Disabled</description>
128334 <description>Read: Enabled</description>
128342 <description>Disable</description>
128351 <description>Temperature in degC (0.25deg steps)</description>
128360 <description>Temperature in degC (0.25deg steps)</description>
128368 <description>Slope of 1st piece wise linear function</description>
128376 <description>Slope of 1st piece wise linear function</description>
128384 <description>Slope of 2nd piece wise linear function</description>
128392 <description>Slope of 2nd piece wise linear function</description>
128400 <description>Slope of 3rd piece wise linear function</description>
128408 <description>Slope of 3rd piece wise linear function</description>
128416 <description>Slope of 4th piece wise linear function</description>
128424 <description>Slope of 4th piece wise linear function</description>
128432 <description>Slope of 5th piece wise linear function</description>
128440 <description>Slope of 5th piece wise linear function</description>
128448 <description>Slope of 6th piece wise linear function</description>
128456 <description>Slope of 6th piece wise linear function</description>
128464 <description>Slope of 7th piece wise linear function</description>
128472 <description>Slope of 7th piece wise linear function</description>
128480 <description>y-intercept of 1st piece wise linear function</description>
128488 <description>y-intercept of 1st piece wise linear function</description>
128496 <description>y-intercept of 2nd piece wise linear function</description>
128504 <description>y-intercept of 2nd piece wise linear function</description>
128512 <description>y-intercept of 3rd piece wise linear function</description>
128520 <description>y-intercept of 3rd piece wise linear function</description>
128528 <description>y-intercept of 4th piece wise linear function</description>
128536 <description>y-intercept of 4th piece wise linear function</description>
128544 <description>y-intercept of 5th piece wise linear function</description>
128552 <description>y-intercept of 5th piece wise linear function</description>
128560 <description>y-intercept of 6th piece wise linear function</description>
128568 <description>y-intercept of 6th piece wise linear function</description>
128576 <description>y-intercept of 7th piece wise linear function</description>
128584 <description>y-intercept of 7th piece wise linear function</description>
128592 <description>End point of 1st piece wise linear function</description>
128600 <description>End point of 1st piece wise linear function</description>
128608 <description>End point of 2nd piece wise linear function</description>
128616 <description>End point of 2nd piece wise linear function</description>
128624 <description>End point of 3rd piece wise linear function</description>
128632 <description>End point of 3rd piece wise linear function</description>
128640 <description>End point of 4th piece wise linear function</description>
128648 <description>End point of 4th piece wise linear function</description>
128656 <description>End point of 5th piece wise linear function</description>
128664 <description>End point of 5th piece wise linear function</description>
128672 <description>End point of 6th piece wise linear function</description>
128680 <description>End point of 6th piece wise linear function</description>
128690 <description>Distributed programmable peripheral interconnect controller 3</description>
128698 <description>Inter-IC Sound 0</description>
128717 …<description>Starts continuous I2S transfer. Also starts MCK generator when this is enabled</descr…
128725 …<description>Starts continuous I2S transfer. Also starts MCK generator when this is enabled</descr…
128731 <description>Trigger task</description>
128740 …<description>Stops I2S transfer and MCK generator. Triggering this task will cause the event STOPP…
128748 …<description>Stops I2S transfer and MCK generator. Triggering this task will cause the event STOPP…
128754 <description>Trigger task</description>
128763 <description>Subscribe configuration for task START</description>
128771 <description>DPPI channel that task START will subscribe to</description>
128782 <description>Disable subscription</description>
128787 <description>Enable subscription</description>
128796 <description>Subscribe configuration for task STOP</description>
128804 <description>DPPI channel that task STOP will subscribe to</description>
128815 <description>Disable subscription</description>
128820 <description>Enable subscription</description>
128829 <description>The RXD.PTR register has been copied to internal double-buffers.
128830 …, this event will be generated for every RXTXD.MAXCNT words received on the SDIN pin.</description>
128838 <description>The RXD.PTR register has been copied to internal double-buffers.
128839 …, this event will be generated for every RXTXD.MAXCNT words received on the SDIN pin.</description>
128845 <description>Event not generated</description>
128850 <description>Event generated</description>
128859 <description>I2S transfer stopped.</description>
128867 <description>I2S transfer stopped.</description>
128873 <description>Event not generated</description>
128878 <description>Event generated</description>
128887 <description>The TDX.PTR register has been copied to internal double-buffers.
128888 … event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin.</description>
128896 <description>The TDX.PTR register has been copied to internal double-buffers.
128897 … event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin.</description>
128903 <description>Event not generated</description>
128908 <description>Event generated</description>
128917 <description>Frame start event, generated on the active edge of LRCK</description>
128925 <description>Frame start event, generated on the active edge of LRCK</description>
128931 <description>Event not generated</description>
128936 <description>Event generated</description>
128945 <description>Publish configuration for event RXPTRUPD</description>
128953 <description>DPPI channel that event RXPTRUPD will publish to</description>
128964 <description>Disable publishing</description>
128969 <description>Enable publishing</description>
128978 <description>Publish configuration for event STOPPED</description>
128986 <description>DPPI channel that event STOPPED will publish to</description>
128997 <description>Disable publishing</description>
129002 <description>Enable publishing</description>
129011 <description>Publish configuration for event TXPTRUPD</description>
129019 <description>DPPI channel that event TXPTRUPD will publish to</description>
129030 <description>Disable publishing</description>
129035 <description>Enable publishing</description>
129044 <description>Publish configuration for event FRAMESTART</description>
129052 <description>DPPI channel that event FRAMESTART will publish to</description>
129063 <description>Disable publishing</description>
129068 <description>Enable publishing</description>
129077 <description>Enable or disable interrupt</description>
129085 <description>Enable or disable interrupt for event RXPTRUPD</description>
129091 <description>Disable</description>
129096 <description>Enable</description>
129103 <description>Enable or disable interrupt for event STOPPED</description>
129109 <description>Disable</description>
129114 <description>Enable</description>
129121 <description>Enable or disable interrupt for event TXPTRUPD</description>
129127 <description>Disable</description>
129132 <description>Enable</description>
129139 <description>Enable or disable interrupt for event FRAMESTART</description>
129145 <description>Disable</description>
129150 <description>Enable</description>
129159 <description>Enable interrupt</description>
129167 <description>Write '1' to enable interrupt for event RXPTRUPD</description>
129174 <description>Read: Disabled</description>
129179 <description>Read: Enabled</description>
129187 <description>Enable</description>
129194 <description>Write '1' to enable interrupt for event STOPPED</description>
129201 <description>Read: Disabled</description>
129206 <description>Read: Enabled</description>
129214 <description>Enable</description>
129221 <description>Write '1' to enable interrupt for event TXPTRUPD</description>
129228 <description>Read: Disabled</description>
129233 <description>Read: Enabled</description>
129241 <description>Enable</description>
129248 <description>Write '1' to enable interrupt for event FRAMESTART</description>
129255 <description>Read: Disabled</description>
129260 <description>Read: Enabled</description>
129268 <description>Enable</description>
129277 <description>Disable interrupt</description>
129285 <description>Write '1' to disable interrupt for event RXPTRUPD</description>
129292 <description>Read: Disabled</description>
129297 <description>Read: Enabled</description>
129305 <description>Disable</description>
129312 <description>Write '1' to disable interrupt for event STOPPED</description>
129319 <description>Read: Disabled</description>
129324 <description>Read: Enabled</description>
129332 <description>Disable</description>
129339 <description>Write '1' to disable interrupt for event TXPTRUPD</description>
129346 <description>Read: Disabled</description>
129351 <description>Read: Enabled</description>
129359 <description>Disable</description>
129366 <description>Write '1' to disable interrupt for event FRAMESTART</description>
129373 <description>Read: Disabled</description>
129378 <description>Read: Enabled</description>
129386 <description>Disable</description>
129395 <description>Enable I2S module</description>
129403 <description>Enable I2S module</description>
129409 <description>Disable</description>
129414 <description>Enable</description>
129423 <description>Unspecified</description>
129429 <description>I2S mode</description>
129437 <description>I2S mode</description>
129443 …<description>Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pi…
129448 …<description>Slave mode. SCK and LRCK generated by external master and received on pins defined by…
129457 <description>Reception (RX) enable</description>
129465 <description>Reception (RX) enable</description>
129471 … <description>Reception disabled and now data will be written to the RXD.PTR address.</description>
129476 <description>Reception enabled.</description>
129485 <description>Transmission (TX) enable</description>
129493 <description>Transmission (TX) enable</description>
129499 …<description>Transmission disabled and now data will be read from the RXD.TXD address.</descriptio…
129504 <description>Transmission enabled.</description>
129513 <description>Master clock generator enable</description>
129521 <description>Master clock generator enable</description>
129527 …<description>Master clock generator disabled and PSEL.MCK not connected(available as GPIO).</descr…
129532 … <description>Master clock generator running and MCK output on PSEL.MCK.</description>
129541 <description>I2S clock generator control</description>
129549 …description>I2S MCK frequency configuration NOTE: Enumerations are deprecated, use MCKFREQ equatio…
129555 … <description>32 MHz / 2 = 16.0 MHz Deprecated, use MCKFREQ equation.</description>
129560 … <description>32 MHz / 3 = 10.6666667 MHz Deprecated, use MCKFREQ equation.</description>
129565 … <description>32 MHz / 4 = 8.0 MHz Deprecated, use MCKFREQ equation.</description>
129570 … <description>32 MHz / 5 = 6.4 MHz Deprecated, use MCKFREQ equation.</description>
129575 … <description>32 MHz / 6 = 5.3333333 MHz Deprecated, use MCKFREQ equation.</description>
129580 … <description>32 MHz / 8 = 4.0 MHz Deprecated, use MCKFREQ equation.</description>
129585 … <description>32 MHz / 10 = 3.2 MHz Deprecated, use MCKFREQ equation.</description>
129590 … <description>32 MHz / 11 = 2.9090909 MHz Deprecated, use MCKFREQ equation.</description>
129595 … <description>32 MHz / 15 = 2.1333333 MHz Deprecated, use MCKFREQ equation.</description>
129600 … <description>32 MHz / 16 = 2.0 MHz Deprecated, use MCKFREQ equation.</description>
129605 … <description>32 MHz / 21 = 1.5238095 MHz Deprecated, use MCKFREQ equation.</description>
129610 … <description>32 MHz / 23 = 1.3913043 MHz Deprecated, use MCKFREQ equation.</description>
129615 … <description>32 MHz / 30 = 1.0666667 MHz Deprecated, use MCKFREQ equation.</description>
129620 … <description>32 MHz / 31 = 1.0322581 MHz Deprecated, use MCKFREQ equation.</description>
129625 … <description>32 MHz / 32 = 1.0 MHz Deprecated, use MCKFREQ equation.</description>
129630 … <description>32 MHz / 42 = 0.7619048 MHz Deprecated, use MCKFREQ equation.</description>
129635 … <description>32 MHz / 63 = 0.5079365 MHz Deprecated, use MCKFREQ equation.</description>
129640 … <description>32 MHz / 125 = 0.256 MHz Deprecated, use MCKFREQ equation.</description>
129649 <description>MCK / LRCK ratio</description>
129657 <description>MCK / LRCK ratio</description>
129663 <description>LRCK = MCK / 32</description>
129668 <description>LRCK = MCK / 48</description>
129673 <description>LRCK = MCK / 64</description>
129678 <description>LRCK = MCK / 96</description>
129683 <description>LRCK = MCK / 128</description>
129688 <description>LRCK = MCK / 192</description>
129693 <description>LRCK = MCK / 256</description>
129698 <description>LRCK = MCK / 384</description>
129703 <description>LRCK = MCK / 512</description>
129712 <description>Sample width</description>
129720 <description>Sample and half-frame width</description>
129726 <description>8 bit sample.</description>
129731 <description>16 bit sample.</description>
129736 <description>24 bit sample.</description>
129741 <description>32 bit sample.</description>
129746 <description>8 bit sample in a 16-bit half-frame.</description>
129751 <description>8 bit sample in a 32-bit half-frame.</description>
129756 <description>16 bit sample in a 32-bit half-frame.</description>
129761 <description>24 bit sample in a 32-bit half-frame.</description>
129770 <description>Alignment of sample within a frame</description>
129778 <description>Alignment of sample within a frame</description>
129784 <description>Left-aligned.</description>
129789 <description>Right-aligned.</description>
129798 <description>Frame format</description>
129806 <description>Frame format</description>
129812 <description>Original I2S format.</description>
129817 <description>Alternate (left- or right-aligned) format.</description>
129826 <description>Enable channels</description>
129834 <description>Enable channels</description>
129840 <description>Stereo.</description>
129845 <description>Left only.</description>
129850 <description>Right only.</description>
129859 <description>Clock source selection for the I2S module</description>
129867 <description>Clock source selection</description>
129873 <description>32MHz peripheral clock</description>
129878 <description>Audio PLL clock</description>
129885 …<description>Bypass clock generator. MCK will be equal to source input. If bypass is enabled the M…
129891 <description>Disable bypass</description>
129896 <description>Enable bypass</description>
129906 <description>Unspecified</description>
129912 <description>Receive buffer RAM start address.</description>
129920 …description>Receive buffer Data RAM start address. When receiving, words containing samples will b…
129929 <description>Unspecified</description>
129935 <description>Transmit buffer RAM start address</description>
129943 …description>Transmit buffer Data RAM start address. When transmitting, words containing samples wi…
129952 <description>Unspecified</description>
129958 <description>Size of RXD and TXD buffers</description>
129966 <description>Size of RXD and TXD buffers in number of 32 bit words</description>
129975 <description>Unspecified</description>
129981 <description>Pin select for MCK signal</description>
129989 <description>Pin number</description>
129995 <description>Port number</description>
130001 <description>Connection</description>
130007 <description>Disconnect</description>
130012 <description>Connect</description>
130021 <description>Pin select for SCK signal</description>
130029 <description>Pin number</description>
130035 <description>Port number</description>
130041 <description>Connection</description>
130047 <description>Disconnect</description>
130052 <description>Connect</description>
130061 <description>Pin select for LRCK signal</description>
130069 <description>Pin number</description>
130075 <description>Port number</description>
130081 <description>Connection</description>
130087 <description>Disconnect</description>
130092 <description>Connect</description>
130101 <description>Pin select for SDIN signal</description>
130109 <description>Pin number</description>
130115 <description>Port number</description>
130121 <description>Connection</description>
130127 <description>Disconnect</description>
130132 <description>Connect</description>
130141 <description>Pin select for SDOUT signal</description>
130149 <description>Pin number</description>
130155 <description>Port number</description>
130161 <description>Connection</description>
130167 <description>Disconnect</description>
130172 <description>Connect</description>
130184 <description>Pulse Density Modulation (Digital Microphone) Interface</description>
130202 <description>Starts continuous PDM transfer</description>
130210 <description>Starts continuous PDM transfer</description>
130216 <description>Trigger task</description>
130225 <description>Stops PDM transfer</description>
130233 <description>Stops PDM transfer</description>
130239 <description>Trigger task</description>
130248 <description>Subscribe configuration for task START</description>
130256 <description>DPPI channel that task START will subscribe to</description>
130267 <description>Disable subscription</description>
130272 <description>Enable subscription</description>
130281 <description>Subscribe configuration for task STOP</description>
130289 <description>DPPI channel that task STOP will subscribe to</description>
130300 <description>Disable subscription</description>
130305 <description>Enable subscription</description>
130314 <description>PDM transfer has started</description>
130322 <description>PDM transfer has started</description>
130328 <description>Event not generated</description>
130333 <description>Event generated</description>
130342 <description>PDM transfer has finished</description>
130350 <description>PDM transfer has finished</description>
130356 <description>Event not generated</description>
130361 <description>Event generated</description>
130370 …description>The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample aft…
130378 …description>The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample aft…
130384 <description>Event not generated</description>
130389 <description>Event generated</description>
130398 <description>Publish configuration for event STARTED</description>
130406 <description>DPPI channel that event STARTED will publish to</description>
130417 <description>Disable publishing</description>
130422 <description>Enable publishing</description>
130431 <description>Publish configuration for event STOPPED</description>
130439 <description>DPPI channel that event STOPPED will publish to</description>
130450 <description>Disable publishing</description>
130455 <description>Enable publishing</description>
130464 <description>Publish configuration for event END</description>
130472 <description>DPPI channel that event END will publish to</description>
130483 <description>Disable publishing</description>
130488 <description>Enable publishing</description>
130497 <description>Enable or disable interrupt</description>
130505 <description>Enable or disable interrupt for event STARTED</description>
130511 <description>Disable</description>
130516 <description>Enable</description>
130523 <description>Enable or disable interrupt for event STOPPED</description>
130529 <description>Disable</description>
130534 <description>Enable</description>
130541 <description>Enable or disable interrupt for event END</description>
130547 <description>Disable</description>
130552 <description>Enable</description>
130561 <description>Enable interrupt</description>
130569 <description>Write '1' to enable interrupt for event STARTED</description>
130576 <description>Read: Disabled</description>
130581 <description>Read: Enabled</description>
130589 <description>Enable</description>
130596 <description>Write '1' to enable interrupt for event STOPPED</description>
130603 <description>Read: Disabled</description>
130608 <description>Read: Enabled</description>
130616 <description>Enable</description>
130623 <description>Write '1' to enable interrupt for event END</description>
130630 <description>Read: Disabled</description>
130635 <description>Read: Enabled</description>
130643 <description>Enable</description>
130652 <description>Disable interrupt</description>
130660 <description>Write '1' to disable interrupt for event STARTED</description>
130667 <description>Read: Disabled</description>
130672 <description>Read: Enabled</description>
130680 <description>Disable</description>
130687 <description>Write '1' to disable interrupt for event STOPPED</description>
130694 <description>Read: Disabled</description>
130699 <description>Read: Enabled</description>
130707 <description>Disable</description>
130714 <description>Write '1' to disable interrupt for event END</description>
130721 <description>Read: Disabled</description>
130726 <description>Read: Enabled</description>
130734 <description>Disable</description>
130743 <description>Pending interrupts</description>
130751 <description>Read pending status of interrupt for event STARTED</description>
130758 <description>Read: Not pending</description>
130763 <description>Read: Pending</description>
130770 <description>Read pending status of interrupt for event STOPPED</description>
130777 <description>Read: Not pending</description>
130782 <description>Read: Pending</description>
130789 <description>Read pending status of interrupt for event END</description>
130796 <description>Read: Not pending</description>
130801 <description>Read: Pending</description>
130810 <description>PDM module enable register</description>
130818 <description>Enable or disable PDM module</description>
130824 <description>Disable</description>
130829 <description>Enable</description>
130838 <description>PDM clock generator control</description>
130846 <description>PDM_CLK frequency configuration. Enumerations are deprecated, use
130848 register are ignored and shall be set to zero.</description>
130854 <description>PDM_CLK = 32 MHz / 32 = 1.000 MHz</description>
130859 … <description>PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64.</description>
130864 <description>PDM_CLK = 32 MHz / 30 = 1.067 MHz</description>
130869 <description>PDM_CLK = 32 MHz / 26 = 1.231 MHz</description>
130874 … <description>PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80.</description>
130879 <description>PDM_CLK = 32 MHz / 24 = 1.333 MHz</description>
130888 <description>Defines the routing of the connected PDM microphones' signals</description>
130896 <description>Mono or stereo operation</description>
130902 …<description>Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=…
130907 …<description>Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; …
130914 <description>Defines on which PDM_CLK edge left (or mono) is sampled.</description>
130920 <description>Left (or mono) is sampled on falling edge of PDM_CLK</description>
130925 <description>Left (or mono) is sampled on rising edge of PDM_CLK</description>
130934 <description>Left output gain adjustment</description>
130942 …description>Left output gain adjustment, in 0.5 dB steps, around the default module gain (see elec…
130948 <description>-20 dB gain adjustment (minimum)</description>
130953 <description>0 dB gain adjustment</description>
130958 <description>+20 dB gain adjustment (maximum)</description>
130967 <description>Right output gain adjustment</description>
130975 …<description>Right output gain adjustment, in 0.5 dB steps, around the default module gain (see el…
130981 <description>-20 dB gain adjustment (minimum)</description>
130986 <description>0 dB gain adjustment</description>
130991 <description>+20 dB gain adjustment (maximum)</description>
131000 …<description>Selects the decimation ratio between PDM_CLK and output sample rate. Change PDMCLKCTR…
131008 … <description>Selects the decimation ratio between PDM_CLK and output sample rate</description>
131014 <description>Ratio of 64</description>
131019 <description>Ratio of 80</description>
131028 <description>Unspecified</description>
131034 <description>Pin number configuration for PDM CLK signal</description>
131042 <description>Pin number</description>
131048 <description>Port number</description>
131054 <description>Connection</description>
131060 <description>Disconnect</description>
131065 <description>Connect</description>
131074 <description>Pin number configuration for PDM DIN signal</description>
131082 <description>Pin number</description>
131088 <description>Port number</description>
131094 <description>Connection</description>
131100 <description>Disconnect</description>
131105 <description>Connect</description>
131115 <description>Master clock generator configuration</description>
131123 <description>Master clock source selection</description>
131129 <description>32 MHz peripheral clock</description>
131134 <description>Audio PLL clock</description>
131143 <description>Unspecified</description>
131149 <description>RAM address pointer to write samples to with EasyDMA</description>
131157 <description>Address to write PDM samples to over DMA</description>
131165 <description>Number of samples to allocate memory for in EasyDMA mode</description>
131173 <description>Length of DMA RAM allocation in number of samples</description>
131182 <description>Unspecified</description>
131188 <description>Terminate the transaction if a BUSERROR event is detected.</description>
131201 <description>Disable</description>
131206 <description>Enable</description>
131215 … <description>Address of transaction that generated the last BUSERROR event.</description>
131233 <description>Quadrature Decoder 0</description>
131252 <description>Task starting the quadrature decoder</description>
131260 <description>Task starting the quadrature decoder</description>
131266 <description>Trigger task</description>
131275 <description>Task stopping the quadrature decoder</description>
131283 <description>Task stopping the quadrature decoder</description>
131289 <description>Trigger task</description>
131298 <description>Read and clear ACC and ACCDBL</description>
131306 <description>Read and clear ACC and ACCDBL</description>
131312 <description>Trigger task</description>
131321 <description>Read and clear ACC</description>
131329 <description>Read and clear ACC</description>
131335 <description>Trigger task</description>
131344 <description>Read and clear ACCDBL</description>
131352 <description>Read and clear ACCDBL</description>
131358 <description>Trigger task</description>
131367 <description>Subscribe configuration for task START</description>
131375 <description>DPPI channel that task START will subscribe to</description>
131386 <description>Disable subscription</description>
131391 <description>Enable subscription</description>
131400 <description>Subscribe configuration for task STOP</description>
131408 <description>DPPI channel that task STOP will subscribe to</description>
131419 <description>Disable subscription</description>
131424 <description>Enable subscription</description>
131433 <description>Subscribe configuration for task READCLRACC</description>
131441 <description>DPPI channel that task READCLRACC will subscribe to</description>
131452 <description>Disable subscription</description>
131457 <description>Enable subscription</description>
131466 <description>Subscribe configuration for task RDCLRACC</description>
131474 <description>DPPI channel that task RDCLRACC will subscribe to</description>
131485 <description>Disable subscription</description>
131490 <description>Enable subscription</description>
131499 <description>Subscribe configuration for task RDCLRDBL</description>
131507 <description>DPPI channel that task RDCLRDBL will subscribe to</description>
131518 <description>Disable subscription</description>
131523 <description>Enable subscription</description>
131532 …<description>Event being generated for every new sample value written to the SAMPLE register</desc…
131540 …<description>Event being generated for every new sample value written to the SAMPLE register</desc…
131546 <description>Event not generated</description>
131551 <description>Event generated</description>
131560 <description>Non-null report ready</description>
131568 <description>Non-null report ready</description>
131574 <description>Event not generated</description>
131579 <description>Event generated</description>
131588 <description>ACC or ACCDBL register overflow</description>
131596 <description>ACC or ACCDBL register overflow</description>
131602 <description>Event not generated</description>
131607 <description>Event generated</description>
131616 <description>Double displacement(s) detected</description>
131624 <description>Double displacement(s) detected</description>
131630 <description>Event not generated</description>
131635 <description>Event generated</description>
131644 <description>QDEC has been stopped</description>
131652 <description>QDEC has been stopped</description>
131658 <description>Event not generated</description>
131663 <description>Event generated</description>
131672 <description>Publish configuration for event SAMPLERDY</description>
131680 <description>DPPI channel that event SAMPLERDY will publish to</description>
131691 <description>Disable publishing</description>
131696 <description>Enable publishing</description>
131705 <description>Publish configuration for event REPORTRDY</description>
131713 <description>DPPI channel that event REPORTRDY will publish to</description>
131724 <description>Disable publishing</description>
131729 <description>Enable publishing</description>
131738 <description>Publish configuration for event ACCOF</description>
131746 <description>DPPI channel that event ACCOF will publish to</description>
131757 <description>Disable publishing</description>
131762 <description>Enable publishing</description>
131771 <description>Publish configuration for event DBLRDY</description>
131779 <description>DPPI channel that event DBLRDY will publish to</description>
131790 <description>Disable publishing</description>
131795 <description>Enable publishing</description>
131804 <description>Publish configuration for event STOPPED</description>
131812 <description>DPPI channel that event STOPPED will publish to</description>
131823 <description>Disable publishing</description>
131828 <description>Enable publishing</description>
131837 <description>Shortcuts between local events and tasks</description>
131845 <description>Shortcut between event REPORTRDY and task READCLRACC</description>
131851 <description>Disable shortcut</description>
131856 <description>Enable shortcut</description>
131863 <description>Shortcut between event SAMPLERDY and task STOP</description>
131869 <description>Disable shortcut</description>
131874 <description>Enable shortcut</description>
131881 <description>Shortcut between event REPORTRDY and task RDCLRACC</description>
131887 <description>Disable shortcut</description>
131892 <description>Enable shortcut</description>
131899 <description>Shortcut between event REPORTRDY and task STOP</description>
131905 <description>Disable shortcut</description>
131910 <description>Enable shortcut</description>
131917 <description>Shortcut between event DBLRDY and task RDCLRDBL</description>
131923 <description>Disable shortcut</description>
131928 <description>Enable shortcut</description>
131935 <description>Shortcut between event DBLRDY and task STOP</description>
131941 <description>Disable shortcut</description>
131946 <description>Enable shortcut</description>
131953 <description>Shortcut between event SAMPLERDY and task READCLRACC</description>
131959 <description>Disable shortcut</description>
131964 <description>Enable shortcut</description>
131973 <description>Enable interrupt</description>
131981 <description>Write '1' to enable interrupt for event SAMPLERDY</description>
131988 <description>Read: Disabled</description>
131993 <description>Read: Enabled</description>
132001 <description>Enable</description>
132008 <description>Write '1' to enable interrupt for event REPORTRDY</description>
132015 <description>Read: Disabled</description>
132020 <description>Read: Enabled</description>
132028 <description>Enable</description>
132035 <description>Write '1' to enable interrupt for event ACCOF</description>
132042 <description>Read: Disabled</description>
132047 <description>Read: Enabled</description>
132055 <description>Enable</description>
132062 <description>Write '1' to enable interrupt for event DBLRDY</description>
132069 <description>Read: Disabled</description>
132074 <description>Read: Enabled</description>
132082 <description>Enable</description>
132089 <description>Write '1' to enable interrupt for event STOPPED</description>
132096 <description>Read: Disabled</description>
132101 <description>Read: Enabled</description>
132109 <description>Enable</description>
132118 <description>Disable interrupt</description>
132126 <description>Write '1' to disable interrupt for event SAMPLERDY</description>
132133 <description>Read: Disabled</description>
132138 <description>Read: Enabled</description>
132146 <description>Disable</description>
132153 <description>Write '1' to disable interrupt for event REPORTRDY</description>
132160 <description>Read: Disabled</description>
132165 <description>Read: Enabled</description>
132173 <description>Disable</description>
132180 <description>Write '1' to disable interrupt for event ACCOF</description>
132187 <description>Read: Disabled</description>
132192 <description>Read: Enabled</description>
132200 <description>Disable</description>
132207 <description>Write '1' to disable interrupt for event DBLRDY</description>
132214 <description>Read: Disabled</description>
132219 <description>Read: Enabled</description>
132227 <description>Disable</description>
132234 <description>Write '1' to disable interrupt for event STOPPED</description>
132241 <description>Read: Disabled</description>
132246 <description>Read: Enabled</description>
132254 <description>Disable</description>
132263 <description>Enable the quadrature decoder</description>
132271 <description>Enable or disable the quadrature decoder</description>
132277 <description>Disable</description>
132282 <description>Enable</description>
132291 <description>LED output pin polarity</description>
132299 <description>LED output pin polarity</description>
132305 <description>Led active on output pin low</description>
132310 <description>Led active on output pin high</description>
132319 <description>Sample period</description>
132327 … <description>Sample period. The SAMPLE register will be updated for every new sample</description>
132333 <description>128 us</description>
132338 <description>256 us</description>
132343 <description>512 us</description>
132348 <description>1024 us</description>
132353 <description>2048 us</description>
132358 <description>4096 us</description>
132363 <description>8192 us</description>
132368 <description>16384 us</description>
132373 <description>32768 us</description>
132378 <description>65536 us</description>
132383 <description>131072 us</description>
132392 <description>Motion sample value</description>
132401 <description>Last motion sample</description>
132409 …<description>Number of samples to be taken before REPORTRDY and DBLRDY events can be generated</de…
132417 …<description>Specifies the number of samples to be accumulated in the ACC register before the REPO…
132423 <description>10 samples/report</description>
132428 <description>40 samples/report</description>
132433 <description>80 samples/report</description>
132438 <description>120 samples/report</description>
132443 <description>160 samples/report</description>
132448 <description>200 samples/report</description>
132453 <description>240 samples/report</description>
132458 <description>280 samples/report</description>
132463 <description>1 sample/report</description>
132472 <description>Register accumulating the valid transitions</description>
132481 …<description>Register accumulating all valid samples (not double transition) read from the SAMPLE …
132489 …<description>Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task</description>
132498 <description>Snapshot of the ACC register.</description>
132506 <description>Unspecified</description>
132512 <description>Pin select for LED signal</description>
132520 <description>Pin number</description>
132526 <description>Port number</description>
132532 <description>Connection</description>
132538 <description>Disconnect</description>
132543 <description>Connect</description>
132552 <description>Pin select for A signal</description>
132560 <description>Pin number</description>
132566 <description>Port number</description>
132572 <description>Connection</description>
132578 <description>Disconnect</description>
132583 <description>Connect</description>
132592 <description>Pin select for B signal</description>
132600 <description>Pin number</description>
132606 <description>Port number</description>
132612 <description>Connection</description>
132618 <description>Disconnect</description>
132623 <description>Connect</description>
132633 <description>Enable input debounce filters</description>
132641 <description>Enable input debounce filters</description>
132647 <description>Debounce input filters disabled</description>
132652 <description>Debounce input filters enabled</description>
132661 <description>Time period the LED is switched ON prior to sampling</description>
132669 <description>Period in us the LED is switched on prior to sampling</description>
132677 <description>Register accumulating the number of detected double transitions</description>
132685 …<description>Register accumulating the number of detected double or illegal transitions. ( SAMPLE …
132693 … <description>Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task</description>
132701 …<description>Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDB…
132711 <description>Quadrature Decoder 1</description>
132722 <description>Inter-IC Sound 1</description>
132733 <description>Distributed programmable peripheral interconnect controller 4</description>
132741 <description>Timer/Counter 2</description>
132752 <description>Timer/Counter 3</description>
132763 <description>Pulse width modulation unit 1</description>
132774 <description>Serial Peripheral Interface Master with EasyDMA 2</description>
132785 <description>SPI Slave 1</description>
132797 <description>I2C compatible Two-Wire Master Interface with EasyDMA 0</description>
132817 …<description>Stop TWI transaction. Must be issued while the TWI master is not suspended.</descript…
132825 …<description>Stop TWI transaction. Must be issued while the TWI master is not suspended.</descript…
132831 <description>Trigger task</description>
132840 <description>Suspend TWI transaction</description>
132848 <description>Suspend TWI transaction</description>
132854 <description>Trigger task</description>
132863 <description>Resume TWI transaction</description>
132871 <description>Resume TWI transaction</description>
132877 <description>Trigger task</description>
132886 <description>Peripheral tasks.</description>
132892 <description>Peripheral tasks.</description>
132898 …<description>Starts operation using easyDMA to load the values. See peripheral description for ope…
132906 …<description>Starts operation using easyDMA to load the values. See peripheral description for ope…
132912 <description>Trigger task</description>
132921 … <description>Stops operation using easyDMA. This does not trigger an END event.</description>
132929 … <description>Stops operation using easyDMA. This does not trigger an END event.</description>
132935 <description>Trigger task</description>
132946 …<description>Description collection: Enables the MATCH[n] event by setting the ENABLE[n] bit in th…
132954 …<description>Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register.</desc…
132960 <description>Trigger task</description>
132971 …<description>Description collection: Disables the MATCH[n] event by clearing the ENABLE[n] bit in …
132979 …<description>Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register.</de…
132985 <description>Trigger task</description>
132995 <description>Peripheral tasks.</description>
133001 …<description>Starts operation using easyDMA to load the values. See peripheral description for ope…
133009 …<description>Starts operation using easyDMA to load the values. See peripheral description for ope…
133015 <description>Trigger task</description>
133024 … <description>Stops operation using easyDMA. This does not trigger an END event.</description>
133032 … <description>Stops operation using easyDMA. This does not trigger an END event.</description>
133038 <description>Trigger task</description>
133049 <description>Subscribe configuration for task STOP</description>
133057 <description>DPPI channel that task STOP will subscribe to</description>
133068 <description>Disable subscription</description>
133073 <description>Enable subscription</description>
133082 <description>Subscribe configuration for task SUSPEND</description>
133090 <description>DPPI channel that task SUSPEND will subscribe to</description>
133101 <description>Disable subscription</description>
133106 <description>Enable subscription</description>
133115 <description>Subscribe configuration for task RESUME</description>
133123 <description>DPPI channel that task RESUME will subscribe to</description>
133134 <description>Disable subscription</description>
133139 <description>Enable subscription</description>
133148 <description>Subscribe configuration for tasks</description>
133154 <description>Subscribe configuration for tasks</description>
133160 <description>Subscribe configuration for task START</description>
133168 <description>DPPI channel that task START will subscribe to</description>
133179 <description>Disable subscription</description>
133184 <description>Enable subscription</description>
133193 <description>Subscribe configuration for task STOP</description>
133201 <description>DPPI channel that task STOP will subscribe to</description>
133212 <description>Disable subscription</description>
133217 <description>Enable subscription</description>
133228 … <description>Description collection: Subscribe configuration for task ENABLEMATCH[n]</description>
133236 <description>DPPI channel that task ENABLEMATCH[n] will subscribe to</description>
133247 <description>Disable subscription</description>
133252 <description>Enable subscription</description>
133263 …<description>Description collection: Subscribe configuration for task DISABLEMATCH[n]</description>
133271 … <description>DPPI channel that task DISABLEMATCH[n] will subscribe to</description>
133282 <description>Disable subscription</description>
133287 <description>Enable subscription</description>
133297 <description>Subscribe configuration for tasks</description>
133303 <description>Subscribe configuration for task START</description>
133311 <description>DPPI channel that task START will subscribe to</description>
133322 <description>Disable subscription</description>
133327 <description>Enable subscription</description>
133336 <description>Subscribe configuration for task STOP</description>
133344 <description>DPPI channel that task STOP will subscribe to</description>
133355 <description>Disable subscription</description>
133360 <description>Enable subscription</description>
133371 <description>TWI stopped</description>
133379 <description>TWI stopped</description>
133385 <description>Event not generated</description>
133390 <description>Event generated</description>
133399 <description>TWI error</description>
133407 <description>TWI error</description>
133413 <description>Event not generated</description>
133418 <description>Event generated</description>
133427 <description>SUSPEND task has been issued, TWI traffic is now suspended.</description>
133435 <description>SUSPEND task has been issued, TWI traffic is now suspended.</description>
133441 <description>Event not generated</description>
133446 <description>Event generated</description>
133455 <description>Byte boundary, starting to receive the last byte</description>
133463 <description>Byte boundary, starting to receive the last byte</description>
133469 <description>Event not generated</description>
133474 <description>Event generated</description>
133483 <description>Byte boundary, starting to transmit the last byte</description>
133491 <description>Byte boundary, starting to transmit the last byte</description>
133497 <description>Event not generated</description>
133502 <description>Event generated</description>
133511 <description>Peripheral events.</description>
133517 <description>Peripheral events.</description>
133523 <description>Generated after all MAXCNT bytes have been transferred</description>
133531 <description>Generated after all MAXCNT bytes have been transferred</description>
133537 <description>Event not generated</description>
133542 <description>Event generated</description>
133551 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
133559 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
133565 <description>Event not generated</description>
133570 <description>Event generated</description>
133579 <description>An error occured during the bus transfer.</description>
133587 <description>An error occured during the bus transfer.</description>
133593 <description>Event not generated</description>
133598 <description>Event generated</description>
133609 … <description>Description collection: Pattern match is detected on the DMA data bus.</description>
133617 <description>Pattern match is detected on the DMA data bus.</description>
133623 <description>Event not generated</description>
133628 <description>Event generated</description>
133638 <description>Peripheral events.</description>
133644 <description>Generated after all MAXCNT bytes have been transferred</description>
133652 <description>Generated after all MAXCNT bytes have been transferred</description>
133658 <description>Event not generated</description>
133663 <description>Event generated</description>
133672 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
133680 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
133686 <description>Event not generated</description>
133691 <description>Event generated</description>
133700 <description>An error occured during the bus transfer.</description>
133708 <description>An error occured during the bus transfer.</description>
133714 <description>Event not generated</description>
133719 <description>Event generated</description>
133730 <description>Publish configuration for event STOPPED</description>
133738 <description>DPPI channel that event STOPPED will publish to</description>
133749 <description>Disable publishing</description>
133754 <description>Enable publishing</description>
133763 <description>Publish configuration for event ERROR</description>
133771 <description>DPPI channel that event ERROR will publish to</description>
133782 <description>Disable publishing</description>
133787 <description>Enable publishing</description>
133796 <description>Publish configuration for event SUSPENDED</description>
133804 <description>DPPI channel that event SUSPENDED will publish to</description>
133815 <description>Disable publishing</description>
133820 <description>Enable publishing</description>
133829 <description>Publish configuration for event LASTRX</description>
133837 <description>DPPI channel that event LASTRX will publish to</description>
133848 <description>Disable publishing</description>
133853 <description>Enable publishing</description>
133862 <description>Publish configuration for event LASTTX</description>
133870 <description>DPPI channel that event LASTTX will publish to</description>
133881 <description>Disable publishing</description>
133886 <description>Enable publishing</description>
133895 <description>Publish configuration for events</description>
133901 <description>Publish configuration for events</description>
133907 <description>Publish configuration for event END</description>
133915 <description>DPPI channel that event END will publish to</description>
133926 <description>Disable publishing</description>
133931 <description>Enable publishing</description>
133940 <description>Publish configuration for event READY</description>
133948 <description>DPPI channel that event READY will publish to</description>
133959 <description>Disable publishing</description>
133964 <description>Enable publishing</description>
133973 <description>Publish configuration for event BUSERROR</description>
133981 <description>DPPI channel that event BUSERROR will publish to</description>
133992 <description>Disable publishing</description>
133997 <description>Enable publishing</description>
134008 … <description>Description collection: Publish configuration for event MATCH[n]</description>
134016 <description>DPPI channel that event MATCH[n] will publish to</description>
134027 <description>Disable publishing</description>
134032 <description>Enable publishing</description>
134042 <description>Publish configuration for events</description>
134048 <description>Publish configuration for event END</description>
134056 <description>DPPI channel that event END will publish to</description>
134067 <description>Disable publishing</description>
134072 <description>Enable publishing</description>
134081 <description>Publish configuration for event READY</description>
134089 <description>DPPI channel that event READY will publish to</description>
134100 <description>Disable publishing</description>
134105 <description>Enable publishing</description>
134114 <description>Publish configuration for event BUSERROR</description>
134122 <description>DPPI channel that event BUSERROR will publish to</description>
134133 <description>Disable publishing</description>
134138 <description>Enable publishing</description>
134149 <description>Shortcuts between local events and tasks</description>
134157 <description>Shortcut between event LASTTX and task DMA.RX.START</description>
134163 <description>Disable shortcut</description>
134168 <description>Enable shortcut</description>
134175 <description>Shortcut between event LASTTX and task SUSPEND</description>
134181 <description>Disable shortcut</description>
134186 <description>Enable shortcut</description>
134193 <description>Shortcut between event LASTTX and task STOP</description>
134199 <description>Disable shortcut</description>
134204 <description>Enable shortcut</description>
134211 <description>Shortcut between event LASTRX and task DMA.TX.START</description>
134217 <description>Disable shortcut</description>
134222 <description>Enable shortcut</description>
134229 <description>Shortcut between event LASTRX and task STOP</description>
134235 <description>Disable shortcut</description>
134240 <description>Enable shortcut</description>
134247 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows daisy-ch…
134253 <description>Disable shortcut</description>
134258 <description>Enable shortcut</description>
134265 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows daisy-ch…
134271 <description>Disable shortcut</description>
134276 <description>Enable shortcut</description>
134283 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows daisy-ch…
134289 <description>Disable shortcut</description>
134294 <description>Enable shortcut</description>
134301 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows daisy-ch…
134307 <description>Disable shortcut</description>
134312 <description>Enable shortcut</description>
134319 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
134325 <description>Disable shortcut</description>
134330 <description>Enable shortcut</description>
134337 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
134343 <description>Disable shortcut</description>
134348 <description>Enable shortcut</description>
134355 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
134361 <description>Disable shortcut</description>
134366 <description>Enable shortcut</description>
134373 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
134379 <description>Disable shortcut</description>
134384 <description>Enable shortcut</description>
134393 <description>Enable or disable interrupt</description>
134401 <description>Enable or disable interrupt for event STOPPED</description>
134407 <description>Disable</description>
134412 <description>Enable</description>
134419 <description>Enable or disable interrupt for event ERROR</description>
134425 <description>Disable</description>
134430 <description>Enable</description>
134437 <description>Enable or disable interrupt for event SUSPENDED</description>
134443 <description>Disable</description>
134448 <description>Enable</description>
134455 <description>Enable or disable interrupt for event LASTRX</description>
134461 <description>Disable</description>
134466 <description>Enable</description>
134473 <description>Enable or disable interrupt for event LASTTX</description>
134479 <description>Disable</description>
134484 <description>Enable</description>
134491 <description>Enable or disable interrupt for event DMARXEND</description>
134497 <description>Disable</description>
134502 <description>Enable</description>
134509 <description>Enable or disable interrupt for event DMARXREADY</description>
134515 <description>Disable</description>
134520 <description>Enable</description>
134527 <description>Enable or disable interrupt for event DMARXBUSERROR</description>
134533 <description>Disable</description>
134538 <description>Enable</description>
134545 <description>Enable or disable interrupt for event DMARXMATCH[0]</description>
134551 <description>Disable</description>
134556 <description>Enable</description>
134563 <description>Enable or disable interrupt for event DMARXMATCH[1]</description>
134569 <description>Disable</description>
134574 <description>Enable</description>
134581 <description>Enable or disable interrupt for event DMARXMATCH[2]</description>
134587 <description>Disable</description>
134592 <description>Enable</description>
134599 <description>Enable or disable interrupt for event DMARXMATCH[3]</description>
134605 <description>Disable</description>
134610 <description>Enable</description>
134617 <description>Enable or disable interrupt for event DMATXEND</description>
134623 <description>Disable</description>
134628 <description>Enable</description>
134635 <description>Enable or disable interrupt for event DMATXREADY</description>
134641 <description>Disable</description>
134646 <description>Enable</description>
134653 <description>Enable or disable interrupt for event DMATXBUSERROR</description>
134659 <description>Disable</description>
134664 <description>Enable</description>
134673 <description>Enable interrupt</description>
134681 <description>Write '1' to enable interrupt for event STOPPED</description>
134688 <description>Read: Disabled</description>
134693 <description>Read: Enabled</description>
134701 <description>Enable</description>
134708 <description>Write '1' to enable interrupt for event ERROR</description>
134715 <description>Read: Disabled</description>
134720 <description>Read: Enabled</description>
134728 <description>Enable</description>
134735 <description>Write '1' to enable interrupt for event SUSPENDED</description>
134742 <description>Read: Disabled</description>
134747 <description>Read: Enabled</description>
134755 <description>Enable</description>
134762 <description>Write '1' to enable interrupt for event LASTRX</description>
134769 <description>Read: Disabled</description>
134774 <description>Read: Enabled</description>
134782 <description>Enable</description>
134789 <description>Write '1' to enable interrupt for event LASTTX</description>
134796 <description>Read: Disabled</description>
134801 <description>Read: Enabled</description>
134809 <description>Enable</description>
134816 <description>Write '1' to enable interrupt for event DMARXEND</description>
134823 <description>Read: Disabled</description>
134828 <description>Read: Enabled</description>
134836 <description>Enable</description>
134843 <description>Write '1' to enable interrupt for event DMARXREADY</description>
134850 <description>Read: Disabled</description>
134855 <description>Read: Enabled</description>
134863 <description>Enable</description>
134870 <description>Write '1' to enable interrupt for event DMARXBUSERROR</description>
134877 <description>Read: Disabled</description>
134882 <description>Read: Enabled</description>
134890 <description>Enable</description>
134897 <description>Write '1' to enable interrupt for event DMARXMATCH[0]</description>
134904 <description>Read: Disabled</description>
134909 <description>Read: Enabled</description>
134917 <description>Enable</description>
134924 <description>Write '1' to enable interrupt for event DMARXMATCH[1]</description>
134931 <description>Read: Disabled</description>
134936 <description>Read: Enabled</description>
134944 <description>Enable</description>
134951 <description>Write '1' to enable interrupt for event DMARXMATCH[2]</description>
134958 <description>Read: Disabled</description>
134963 <description>Read: Enabled</description>
134971 <description>Enable</description>
134978 <description>Write '1' to enable interrupt for event DMARXMATCH[3]</description>
134985 <description>Read: Disabled</description>
134990 <description>Read: Enabled</description>
134998 <description>Enable</description>
135005 <description>Write '1' to enable interrupt for event DMATXEND</description>
135012 <description>Read: Disabled</description>
135017 <description>Read: Enabled</description>
135025 <description>Enable</description>
135032 <description>Write '1' to enable interrupt for event DMATXREADY</description>
135039 <description>Read: Disabled</description>
135044 <description>Read: Enabled</description>
135052 <description>Enable</description>
135059 <description>Write '1' to enable interrupt for event DMATXBUSERROR</description>
135066 <description>Read: Disabled</description>
135071 <description>Read: Enabled</description>
135079 <description>Enable</description>
135088 <description>Disable interrupt</description>
135096 <description>Write '1' to disable interrupt for event STOPPED</description>
135103 <description>Read: Disabled</description>
135108 <description>Read: Enabled</description>
135116 <description>Disable</description>
135123 <description>Write '1' to disable interrupt for event ERROR</description>
135130 <description>Read: Disabled</description>
135135 <description>Read: Enabled</description>
135143 <description>Disable</description>
135150 <description>Write '1' to disable interrupt for event SUSPENDED</description>
135157 <description>Read: Disabled</description>
135162 <description>Read: Enabled</description>
135170 <description>Disable</description>
135177 <description>Write '1' to disable interrupt for event LASTRX</description>
135184 <description>Read: Disabled</description>
135189 <description>Read: Enabled</description>
135197 <description>Disable</description>
135204 <description>Write '1' to disable interrupt for event LASTTX</description>
135211 <description>Read: Disabled</description>
135216 <description>Read: Enabled</description>
135224 <description>Disable</description>
135231 <description>Write '1' to disable interrupt for event DMARXEND</description>
135238 <description>Read: Disabled</description>
135243 <description>Read: Enabled</description>
135251 <description>Disable</description>
135258 <description>Write '1' to disable interrupt for event DMARXREADY</description>
135265 <description>Read: Disabled</description>
135270 <description>Read: Enabled</description>
135278 <description>Disable</description>
135285 <description>Write '1' to disable interrupt for event DMARXBUSERROR</description>
135292 <description>Read: Disabled</description>
135297 <description>Read: Enabled</description>
135305 <description>Disable</description>
135312 <description>Write '1' to disable interrupt for event DMARXMATCH[0]</description>
135319 <description>Read: Disabled</description>
135324 <description>Read: Enabled</description>
135332 <description>Disable</description>
135339 <description>Write '1' to disable interrupt for event DMARXMATCH[1]</description>
135346 <description>Read: Disabled</description>
135351 <description>Read: Enabled</description>
135359 <description>Disable</description>
135366 <description>Write '1' to disable interrupt for event DMARXMATCH[2]</description>
135373 <description>Read: Disabled</description>
135378 <description>Read: Enabled</description>
135386 <description>Disable</description>
135393 <description>Write '1' to disable interrupt for event DMARXMATCH[3]</description>
135400 <description>Read: Disabled</description>
135405 <description>Read: Enabled</description>
135413 <description>Disable</description>
135420 <description>Write '1' to disable interrupt for event DMATXEND</description>
135427 <description>Read: Disabled</description>
135432 <description>Read: Enabled</description>
135440 <description>Disable</description>
135447 <description>Write '1' to disable interrupt for event DMATXREADY</description>
135454 <description>Read: Disabled</description>
135459 <description>Read: Enabled</description>
135467 <description>Disable</description>
135474 <description>Write '1' to disable interrupt for event DMATXBUSERROR</description>
135481 <description>Read: Disabled</description>
135486 <description>Read: Enabled</description>
135494 <description>Disable</description>
135503 <description>Error source</description>
135512 <description>Overrun error</description>
135518 <description>Error did not occur</description>
135523 <description>Error occurred</description>
135530 … <description>NACK received after sending the address (write '1' to clear)</description>
135536 <description>Error did not occur</description>
135541 <description>Error occurred</description>
135548 … <description>NACK received after sending a data byte (write '1' to clear)</description>
135554 <description>Error did not occur</description>
135559 <description>Error occurred</description>
135568 <description>Enable TWIM</description>
135576 <description>Enable or disable TWIM</description>
135582 <description>Disable TWIM</description>
135587 <description>Enable TWIM</description>
135596 <description>TWI frequency. Accuracy depends on the HFCLK source selected.</description>
135604 <description>TWI master clock frequency</description>
135610 <description>100 kbps</description>
135615 <description>250 kbps</description>
135620 <description>400 kbps</description>
135625 <description>1000 kbps</description>
135634 <description>Address used in the TWI transfer</description>
135642 <description>Address used in the TWI transfer</description>
135650 <description>Unspecified</description>
135656 <description>Pin select for SCL signal</description>
135664 <description>Pin number</description>
135670 <description>Port number</description>
135676 <description>Connection</description>
135682 <description>Disconnect</description>
135687 <description>Connect</description>
135696 <description>Pin select for SDA signal</description>
135704 <description>Pin number</description>
135710 <description>Port number</description>
135716 <description>Connection</description>
135722 <description>Disconnect</description>
135727 <description>Connect</description>
135737 <description>Unspecified</description>
135743 <description>Unspecified</description>
135749 <description>RAM buffer start address</description>
135757 …<description>RAM buffer start address for this EasyDMA channel. This address is a word aligned Dat…
135765 <description>Maximum number of bytes in channel buffer</description>
135773 <description>Maximum number of bytes in channel buffer</description>
135781 …<description>Number of bytes transferred in the last transaction, updated after the END event. Als…
135789 …<description>Number of bytes transferred in the last transaction. In case of NACK error, includes …
135797 <description>Number of bytes transferred in the current transaction</description>
135805 …<description>Number of bytes transferred in the current transaction. Continuously updated.</descri…
135813 <description>EasyDMA list type</description>
135821 <description>List type</description>
135827 <description>Disable EasyDMA list</description>
135832 <description>Use array list</description>
135841 <description>Terminate the transaction if a BUSERROR event is detected.</description>
135854 <description>Disable</description>
135859 <description>Enable</description>
135868 … <description>Address of transaction that generated the last BUSERROR event.</description>
135883 … <description>Registers to control the behavior of the pattern matcher engine</description>
135889 <description>Configure individual match events</description>
135897 <description>Enable match filter 0</description>
135903 <description>Match filter disabled</description>
135908 <description>Match filter enabled</description>
135915 <description>Enable match filter 1</description>
135921 <description>Match filter disabled</description>
135926 <description>Match filter enabled</description>
135933 <description>Enable match filter 2</description>
135939 <description>Match filter disabled</description>
135944 <description>Match filter enabled</description>
135951 <description>Enable match filter 3</description>
135957 <description>Match filter disabled</description>
135962 <description>Match filter enabled</description>
135969 <description>Configure match filter 0 as one-shot or sticky</description>
135975 <description>Match filter stays enabled until disabled by task</description>
135980 … <description>Match filter stays enabled until next data word is received</description>
135987 <description>Configure match filter 1 as one-shot or sticky</description>
135993 <description>Match filter stays enabled until disabled by task</description>
135998 … <description>Match filter stays enabled until next data word is received</description>
136005 <description>Configure match filter 2 as one-shot or sticky</description>
136011 <description>Match filter stays enabled until disabled by task</description>
136016 … <description>Match filter stays enabled until next data word is received</description>
136023 <description>Configure match filter 3 as one-shot or sticky</description>
136029 <description>Match filter stays enabled until disabled by task</description>
136034 … <description>Match filter stays enabled until next data word is received</description>
136045 …<description>Description collection: The data to look for - any match will trigger the MATCH[n] ev…
136053 <description>Data to look for</description>
136063 <description>Unspecified</description>
136069 <description>RAM buffer start address</description>
136077 …<description>RAM buffer start address for this EasyDMA channel. This address is a word aligned Dat…
136085 <description>Maximum number of bytes in channel buffer</description>
136093 <description>Maximum number of bytes in channel buffer</description>
136101 …<description>Number of bytes transferred in the last transaction, updated after the END event. Als…
136109 …<description>Number of bytes transferred in the last transaction. In case of NACK error, includes …
136117 <description>Number of bytes transferred in the current transaction</description>
136125 …<description>Number of bytes transferred in the current transaction. Continuously updated.</descri…
136133 <description>EasyDMA list type</description>
136141 <description>List type</description>
136147 <description>Disable EasyDMA list</description>
136152 <description>Use array list</description>
136161 <description>Terminate the transaction if a BUSERROR event is detected.</description>
136174 <description>Disable</description>
136179 <description>Enable</description>
136188 … <description>Address of transaction that generated the last BUSERROR event.</description>
136207 <description>I2C compatible Two-Wire Slave Interface with EasyDMA 0</description>
136227 <description>Stop TWI transaction</description>
136235 <description>Stop TWI transaction</description>
136241 <description>Trigger task</description>
136250 <description>Suspend TWI transaction</description>
136258 <description>Suspend TWI transaction</description>
136264 <description>Trigger task</description>
136273 <description>Resume TWI transaction</description>
136281 <description>Resume TWI transaction</description>
136287 <description>Trigger task</description>
136296 <description>Prepare the TWI slave to respond to a write command</description>
136304 <description>Prepare the TWI slave to respond to a write command</description>
136310 <description>Trigger task</description>
136319 <description>Prepare the TWI slave to respond to a read command</description>
136327 <description>Prepare the TWI slave to respond to a read command</description>
136333 <description>Trigger task</description>
136342 <description>Peripheral tasks.</description>
136348 <description>Peripheral tasks.</description>
136356 …<description>Description collection: Enables the MATCH[n] event by setting the ENABLE[n] bit in th…
136364 …<description>Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register.</desc…
136370 <description>Trigger task</description>
136381 …<description>Description collection: Disables the MATCH[n] event by clearing the ENABLE[n] bit in …
136389 …<description>Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register.</de…
136395 <description>Trigger task</description>
136406 <description>Subscribe configuration for task STOP</description>
136414 <description>DPPI channel that task STOP will subscribe to</description>
136425 <description>Disable subscription</description>
136430 <description>Enable subscription</description>
136439 <description>Subscribe configuration for task SUSPEND</description>
136447 <description>DPPI channel that task SUSPEND will subscribe to</description>
136458 <description>Disable subscription</description>
136463 <description>Enable subscription</description>
136472 <description>Subscribe configuration for task RESUME</description>
136480 <description>DPPI channel that task RESUME will subscribe to</description>
136491 <description>Disable subscription</description>
136496 <description>Enable subscription</description>
136505 <description>Subscribe configuration for task PREPARERX</description>
136513 <description>DPPI channel that task PREPARERX will subscribe to</description>
136524 <description>Disable subscription</description>
136529 <description>Enable subscription</description>
136538 <description>Subscribe configuration for task PREPARETX</description>
136546 <description>DPPI channel that task PREPARETX will subscribe to</description>
136557 <description>Disable subscription</description>
136562 <description>Enable subscription</description>
136571 <description>Subscribe configuration for tasks</description>
136577 <description>Subscribe configuration for tasks</description>
136585 … <description>Description collection: Subscribe configuration for task ENABLEMATCH[n]</description>
136593 <description>DPPI channel that task ENABLEMATCH[n] will subscribe to</description>
136604 <description>Disable subscription</description>
136609 <description>Enable subscription</description>
136620 …<description>Description collection: Subscribe configuration for task DISABLEMATCH[n]</description>
136628 … <description>DPPI channel that task DISABLEMATCH[n] will subscribe to</description>
136639 <description>Disable subscription</description>
136644 <description>Enable subscription</description>
136655 <description>TWI stopped</description>
136663 <description>TWI stopped</description>
136669 <description>Event not generated</description>
136674 <description>Event generated</description>
136683 <description>TWI error</description>
136691 <description>TWI error</description>
136697 <description>Event not generated</description>
136702 <description>Event generated</description>
136711 <description>Write command received</description>
136719 <description>Write command received</description>
136725 <description>Event not generated</description>
136730 <description>Event generated</description>
136739 <description>Read command received</description>
136747 <description>Read command received</description>
136753 <description>Event not generated</description>
136758 <description>Event generated</description>
136767 <description>Peripheral events.</description>
136773 <description>Peripheral events.</description>
136779 <description>Generated after all MAXCNT bytes have been transferred</description>
136787 <description>Generated after all MAXCNT bytes have been transferred</description>
136793 <description>Event not generated</description>
136798 <description>Event generated</description>
136807 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
136815 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
136821 <description>Event not generated</description>
136826 <description>Event generated</description>
136835 <description>An error occured during the bus transfer.</description>
136843 <description>An error occured during the bus transfer.</description>
136849 <description>Event not generated</description>
136854 <description>Event generated</description>
136865 … <description>Description collection: Pattern match is detected on the DMA data bus.</description>
136873 <description>Pattern match is detected on the DMA data bus.</description>
136879 <description>Event not generated</description>
136884 <description>Event generated</description>
136894 <description>Peripheral events.</description>
136900 <description>Generated after all MAXCNT bytes have been transferred</description>
136908 <description>Generated after all MAXCNT bytes have been transferred</description>
136914 <description>Event not generated</description>
136919 <description>Event generated</description>
136928 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
136936 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
136942 <description>Event not generated</description>
136947 <description>Event generated</description>
136956 <description>An error occured during the bus transfer.</description>
136964 <description>An error occured during the bus transfer.</description>
136970 <description>Event not generated</description>
136975 <description>Event generated</description>
136986 <description>Publish configuration for event STOPPED</description>
136994 <description>DPPI channel that event STOPPED will publish to</description>
137005 <description>Disable publishing</description>
137010 <description>Enable publishing</description>
137019 <description>Publish configuration for event ERROR</description>
137027 <description>DPPI channel that event ERROR will publish to</description>
137038 <description>Disable publishing</description>
137043 <description>Enable publishing</description>
137052 <description>Publish configuration for event WRITE</description>
137060 <description>DPPI channel that event WRITE will publish to</description>
137071 <description>Disable publishing</description>
137076 <description>Enable publishing</description>
137085 <description>Publish configuration for event READ</description>
137093 <description>DPPI channel that event READ will publish to</description>
137104 <description>Disable publishing</description>
137109 <description>Enable publishing</description>
137118 <description>Publish configuration for events</description>
137124 <description>Publish configuration for events</description>
137130 <description>Publish configuration for event END</description>
137138 <description>DPPI channel that event END will publish to</description>
137149 <description>Disable publishing</description>
137154 <description>Enable publishing</description>
137163 <description>Publish configuration for event READY</description>
137171 <description>DPPI channel that event READY will publish to</description>
137182 <description>Disable publishing</description>
137187 <description>Enable publishing</description>
137196 <description>Publish configuration for event BUSERROR</description>
137204 <description>DPPI channel that event BUSERROR will publish to</description>
137215 <description>Disable publishing</description>
137220 <description>Enable publishing</description>
137231 … <description>Description collection: Publish configuration for event MATCH[n]</description>
137239 <description>DPPI channel that event MATCH[n] will publish to</description>
137250 <description>Disable publishing</description>
137255 <description>Enable publishing</description>
137265 <description>Publish configuration for events</description>
137271 <description>Publish configuration for event END</description>
137279 <description>DPPI channel that event END will publish to</description>
137290 <description>Disable publishing</description>
137295 <description>Enable publishing</description>
137304 <description>Publish configuration for event READY</description>
137312 <description>DPPI channel that event READY will publish to</description>
137323 <description>Disable publishing</description>
137328 <description>Enable publishing</description>
137337 <description>Publish configuration for event BUSERROR</description>
137345 <description>DPPI channel that event BUSERROR will publish to</description>
137356 <description>Disable publishing</description>
137361 <description>Enable publishing</description>
137372 <description>Shortcuts between local events and tasks</description>
137380 <description>Shortcut between event WRITE and task SUSPEND</description>
137386 <description>Disable shortcut</description>
137391 <description>Enable shortcut</description>
137398 <description>Shortcut between event READ and task SUSPEND</description>
137404 <description>Disable shortcut</description>
137409 <description>Enable shortcut</description>
137416 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows daisy-ch…
137422 <description>Disable shortcut</description>
137427 <description>Enable shortcut</description>
137434 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows daisy-ch…
137440 <description>Disable shortcut</description>
137445 <description>Enable shortcut</description>
137452 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows daisy-ch…
137458 <description>Disable shortcut</description>
137463 <description>Enable shortcut</description>
137470 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows daisy-ch…
137476 <description>Disable shortcut</description>
137481 <description>Enable shortcut</description>
137488 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
137494 <description>Disable shortcut</description>
137499 <description>Enable shortcut</description>
137506 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
137512 <description>Disable shortcut</description>
137517 <description>Enable shortcut</description>
137524 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
137530 <description>Disable shortcut</description>
137535 <description>Enable shortcut</description>
137542 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
137548 <description>Disable shortcut</description>
137553 <description>Enable shortcut</description>
137562 <description>Enable or disable interrupt</description>
137570 <description>Enable or disable interrupt for event STOPPED</description>
137576 <description>Disable</description>
137581 <description>Enable</description>
137588 <description>Enable or disable interrupt for event ERROR</description>
137594 <description>Disable</description>
137599 <description>Enable</description>
137606 <description>Enable or disable interrupt for event WRITE</description>
137612 <description>Disable</description>
137617 <description>Enable</description>
137624 <description>Enable or disable interrupt for event READ</description>
137630 <description>Disable</description>
137635 <description>Enable</description>
137642 <description>Enable or disable interrupt for event DMARXEND</description>
137648 <description>Disable</description>
137653 <description>Enable</description>
137660 <description>Enable or disable interrupt for event DMARXREADY</description>
137666 <description>Disable</description>
137671 <description>Enable</description>
137678 <description>Enable or disable interrupt for event DMARXBUSERROR</description>
137684 <description>Disable</description>
137689 <description>Enable</description>
137696 <description>Enable or disable interrupt for event DMARXMATCH[0]</description>
137702 <description>Disable</description>
137707 <description>Enable</description>
137714 <description>Enable or disable interrupt for event DMARXMATCH[1]</description>
137720 <description>Disable</description>
137725 <description>Enable</description>
137732 <description>Enable or disable interrupt for event DMARXMATCH[2]</description>
137738 <description>Disable</description>
137743 <description>Enable</description>
137750 <description>Enable or disable interrupt for event DMARXMATCH[3]</description>
137756 <description>Disable</description>
137761 <description>Enable</description>
137768 <description>Enable or disable interrupt for event DMATXEND</description>
137774 <description>Disable</description>
137779 <description>Enable</description>
137786 <description>Enable or disable interrupt for event DMATXREADY</description>
137792 <description>Disable</description>
137797 <description>Enable</description>
137804 <description>Enable or disable interrupt for event DMATXBUSERROR</description>
137810 <description>Disable</description>
137815 <description>Enable</description>
137824 <description>Enable interrupt</description>
137832 <description>Write '1' to enable interrupt for event STOPPED</description>
137839 <description>Read: Disabled</description>
137844 <description>Read: Enabled</description>
137852 <description>Enable</description>
137859 <description>Write '1' to enable interrupt for event ERROR</description>
137866 <description>Read: Disabled</description>
137871 <description>Read: Enabled</description>
137879 <description>Enable</description>
137886 <description>Write '1' to enable interrupt for event WRITE</description>
137893 <description>Read: Disabled</description>
137898 <description>Read: Enabled</description>
137906 <description>Enable</description>
137913 <description>Write '1' to enable interrupt for event READ</description>
137920 <description>Read: Disabled</description>
137925 <description>Read: Enabled</description>
137933 <description>Enable</description>
137940 <description>Write '1' to enable interrupt for event DMARXEND</description>
137947 <description>Read: Disabled</description>
137952 <description>Read: Enabled</description>
137960 <description>Enable</description>
137967 <description>Write '1' to enable interrupt for event DMARXREADY</description>
137974 <description>Read: Disabled</description>
137979 <description>Read: Enabled</description>
137987 <description>Enable</description>
137994 <description>Write '1' to enable interrupt for event DMARXBUSERROR</description>
138001 <description>Read: Disabled</description>
138006 <description>Read: Enabled</description>
138014 <description>Enable</description>
138021 <description>Write '1' to enable interrupt for event DMARXMATCH[0]</description>
138028 <description>Read: Disabled</description>
138033 <description>Read: Enabled</description>
138041 <description>Enable</description>
138048 <description>Write '1' to enable interrupt for event DMARXMATCH[1]</description>
138055 <description>Read: Disabled</description>
138060 <description>Read: Enabled</description>
138068 <description>Enable</description>
138075 <description>Write '1' to enable interrupt for event DMARXMATCH[2]</description>
138082 <description>Read: Disabled</description>
138087 <description>Read: Enabled</description>
138095 <description>Enable</description>
138102 <description>Write '1' to enable interrupt for event DMARXMATCH[3]</description>
138109 <description>Read: Disabled</description>
138114 <description>Read: Enabled</description>
138122 <description>Enable</description>
138129 <description>Write '1' to enable interrupt for event DMATXEND</description>
138136 <description>Read: Disabled</description>
138141 <description>Read: Enabled</description>
138149 <description>Enable</description>
138156 <description>Write '1' to enable interrupt for event DMATXREADY</description>
138163 <description>Read: Disabled</description>
138168 <description>Read: Enabled</description>
138176 <description>Enable</description>
138183 <description>Write '1' to enable interrupt for event DMATXBUSERROR</description>
138190 <description>Read: Disabled</description>
138195 <description>Read: Enabled</description>
138203 <description>Enable</description>
138212 <description>Disable interrupt</description>
138220 <description>Write '1' to disable interrupt for event STOPPED</description>
138227 <description>Read: Disabled</description>
138232 <description>Read: Enabled</description>
138240 <description>Disable</description>
138247 <description>Write '1' to disable interrupt for event ERROR</description>
138254 <description>Read: Disabled</description>
138259 <description>Read: Enabled</description>
138267 <description>Disable</description>
138274 <description>Write '1' to disable interrupt for event WRITE</description>
138281 <description>Read: Disabled</description>
138286 <description>Read: Enabled</description>
138294 <description>Disable</description>
138301 <description>Write '1' to disable interrupt for event READ</description>
138308 <description>Read: Disabled</description>
138313 <description>Read: Enabled</description>
138321 <description>Disable</description>
138328 <description>Write '1' to disable interrupt for event DMARXEND</description>
138335 <description>Read: Disabled</description>
138340 <description>Read: Enabled</description>
138348 <description>Disable</description>
138355 <description>Write '1' to disable interrupt for event DMARXREADY</description>
138362 <description>Read: Disabled</description>
138367 <description>Read: Enabled</description>
138375 <description>Disable</description>
138382 <description>Write '1' to disable interrupt for event DMARXBUSERROR</description>
138389 <description>Read: Disabled</description>
138394 <description>Read: Enabled</description>
138402 <description>Disable</description>
138409 <description>Write '1' to disable interrupt for event DMARXMATCH[0]</description>
138416 <description>Read: Disabled</description>
138421 <description>Read: Enabled</description>
138429 <description>Disable</description>
138436 <description>Write '1' to disable interrupt for event DMARXMATCH[1]</description>
138443 <description>Read: Disabled</description>
138448 <description>Read: Enabled</description>
138456 <description>Disable</description>
138463 <description>Write '1' to disable interrupt for event DMARXMATCH[2]</description>
138470 <description>Read: Disabled</description>
138475 <description>Read: Enabled</description>
138483 <description>Disable</description>
138490 <description>Write '1' to disable interrupt for event DMARXMATCH[3]</description>
138497 <description>Read: Disabled</description>
138502 <description>Read: Enabled</description>
138510 <description>Disable</description>
138517 <description>Write '1' to disable interrupt for event DMATXEND</description>
138524 <description>Read: Disabled</description>
138529 <description>Read: Enabled</description>
138537 <description>Disable</description>
138544 <description>Write '1' to disable interrupt for event DMATXREADY</description>
138551 <description>Read: Disabled</description>
138556 <description>Read: Enabled</description>
138564 <description>Disable</description>
138571 <description>Write '1' to disable interrupt for event DMATXBUSERROR</description>
138578 <description>Read: Disabled</description>
138583 <description>Read: Enabled</description>
138591 <description>Disable</description>
138600 <description>Error source</description>
138609 <description>RX buffer overflow detected, and prevented</description>
138615 <description>Error did not occur</description>
138620 <description>Error occurred</description>
138627 <description>NACK sent after receiving a data byte</description>
138633 <description>Error did not occur</description>
138638 <description>Error occurred</description>
138645 <description>TX buffer over-read detected, and prevented</description>
138651 <description>Error did not occur</description>
138656 <description>Error occurred</description>
138665 <description>Status register indicating which address had a match</description>
138673 …<description>Indication of which address in ADDRESS that matched the incoming address</description>
138681 <description>Enable TWIS</description>
138689 <description>Enable or disable TWIS</description>
138695 <description>Disable TWIS</description>
138700 <description>Enable TWIS</description>
138711 <description>Description collection: TWI slave address n</description>
138719 <description>TWI slave address</description>
138727 <description>Configuration register for the address match mechanism</description>
138735 <description>Enable or disable address matching on ADDRESS[0]</description>
138741 <description>Disabled</description>
138746 <description>Enabled</description>
138753 <description>Enable or disable address matching on ADDRESS[1]</description>
138759 <description>Disabled</description>
138764 <description>Enabled</description>
138773 …<description>Over-read character. Character sent out in case of an over-read of the transmit buffe…
138781 …<description>Over-read character. Character sent out in case of an over-read of the transmit buffe…
138789 <description>Unspecified</description>
138795 <description>Pin select for SCL signal</description>
138803 <description>Pin number</description>
138809 <description>Port number</description>
138815 <description>Connection</description>
138821 <description>Disconnect</description>
138826 <description>Connect</description>
138835 <description>Pin select for SDA signal</description>
138843 <description>Pin number</description>
138849 <description>Port number</description>
138855 <description>Connection</description>
138861 <description>Disconnect</description>
138866 <description>Connect</description>
138876 <description>Unspecified</description>
138882 <description>Unspecified</description>
138888 <description>RAM buffer start address</description>
138896 …<description>RAM buffer start address for this EasyDMA channel. This address is a word aligned Dat…
138904 <description>Maximum number of bytes in channel buffer</description>
138912 <description>Maximum number of bytes in channel buffer</description>
138920 …<description>Number of bytes transferred in the last transaction, updated after the END event. Als…
138928 …<description>Number of bytes transferred in the last transaction. In case of NACK error, includes …
138936 <description>Number of bytes transferred in the current transaction</description>
138944 …<description>Number of bytes transferred in the current transaction. Continuously updated.</descri…
138952 <description>EasyDMA list type</description>
138960 <description>List type</description>
138966 <description>Disable EasyDMA list</description>
138971 <description>Use array list</description>
138980 <description>Terminate the transaction if a BUSERROR event is detected.</description>
138993 <description>Disable</description>
138998 <description>Enable</description>
139007 … <description>Address of transaction that generated the last BUSERROR event.</description>
139022 … <description>Registers to control the behavior of the pattern matcher engine</description>
139028 <description>Configure individual match events</description>
139036 <description>Enable match filter 0</description>
139042 <description>Match filter disabled</description>
139047 <description>Match filter enabled</description>
139054 <description>Enable match filter 1</description>
139060 <description>Match filter disabled</description>
139065 <description>Match filter enabled</description>
139072 <description>Enable match filter 2</description>
139078 <description>Match filter disabled</description>
139083 <description>Match filter enabled</description>
139090 <description>Enable match filter 3</description>
139096 <description>Match filter disabled</description>
139101 <description>Match filter enabled</description>
139108 <description>Configure match filter 0 as one-shot or sticky</description>
139114 <description>Match filter stays enabled until disabled by task</description>
139119 … <description>Match filter stays enabled until next data word is received</description>
139126 <description>Configure match filter 1 as one-shot or sticky</description>
139132 <description>Match filter stays enabled until disabled by task</description>
139137 … <description>Match filter stays enabled until next data word is received</description>
139144 <description>Configure match filter 2 as one-shot or sticky</description>
139150 <description>Match filter stays enabled until disabled by task</description>
139155 … <description>Match filter stays enabled until next data word is received</description>
139162 <description>Configure match filter 3 as one-shot or sticky</description>
139168 <description>Match filter stays enabled until disabled by task</description>
139173 … <description>Match filter stays enabled until next data word is received</description>
139184 …<description>Description collection: The data to look for - any match will trigger the MATCH[n] ev…
139192 <description>Data to look for</description>
139202 <description>Unspecified</description>
139208 <description>RAM buffer start address</description>
139216 …<description>RAM buffer start address for this EasyDMA channel. This address is a word aligned Dat…
139224 <description>Maximum number of bytes in channel buffer</description>
139232 <description>Maximum number of bytes in channel buffer</description>
139240 …<description>Number of bytes transferred in the last transaction, updated after the END event. Als…
139248 …<description>Number of bytes transferred in the last transaction. In case of NACK error, includes …
139256 <description>Number of bytes transferred in the current transaction</description>
139264 …<description>Number of bytes transferred in the current transaction. Continuously updated.</descri…
139272 <description>EasyDMA list type</description>
139280 <description>List type</description>
139286 <description>Disable EasyDMA list</description>
139291 <description>Use array list</description>
139300 <description>Terminate the transaction if a BUSERROR event is detected.</description>
139313 <description>Disable</description>
139318 <description>Enable</description>
139327 … <description>Address of transaction that generated the last BUSERROR event.</description>
139346 <description>UART with EasyDMA 1</description>
139358 <description>Serial Peripheral Interface Master with EasyDMA 3</description>
139369 <description>SPI Slave 2</description>
139381 <description>I2C compatible Two-Wire Master Interface with EasyDMA 1</description>
139393 <description>I2C compatible Two-Wire Slave Interface with EasyDMA 1</description>
139405 <description>UART with EasyDMA 2</description>
139417 <description>Distributed programmable peripheral interconnect controller 5</description>
139425 <description>Timer/Counter 4</description>
139436 <description>Timer/Counter 5</description>
139447 <description>Pulse width modulation unit 2</description>
139458 <description>Serial Peripheral Interface Master with EasyDMA 4</description>
139469 <description>SPI Slave 3</description>
139481 <description>I2C compatible Two-Wire Master Interface with EasyDMA 2</description>
139493 <description>I2C compatible Two-Wire Slave Interface with EasyDMA 2</description>
139505 <description>UART with EasyDMA 3</description>
139517 <description>Serial Peripheral Interface Master with EasyDMA 5</description>
139528 <description>SPI Slave 4</description>
139540 <description>I2C compatible Two-Wire Master Interface with EasyDMA 3</description>
139552 <description>I2C compatible Two-Wire Slave Interface with EasyDMA 3</description>
139564 <description>UART with EasyDMA 4</description>
139576 <description>Distributed programmable peripheral interconnect controller 6</description>
139584 <description>Timer/Counter 6</description>
139595 <description>Timer/Counter 7</description>
139606 <description>Pulse width modulation unit 3</description>
139617 <description>Serial Peripheral Interface Master with EasyDMA 6</description>
139628 <description>SPI Slave 5</description>
139640 <description>I2C compatible Two-Wire Master Interface with EasyDMA 4</description>
139652 <description>I2C compatible Two-Wire Slave Interface with EasyDMA 4</description>
139664 <description>UART with EasyDMA 5</description>
139676 <description>Serial Peripheral Interface Master with EasyDMA 7</description>
139687 <description>SPI Slave 6</description>
139699 <description>I2C compatible Two-Wire Master Interface with EasyDMA 5</description>
139711 <description>I2C compatible Two-Wire Slave Interface with EasyDMA 5</description>
139723 <description>UART with EasyDMA 6</description>
139735 <description>Distributed programmable peripheral interconnect controller 7</description>
139743 <description>Timer/Counter 8</description>
139754 <description>Timer/Counter 9</description>
139765 <description>Pulse width modulation unit 4</description>
139776 <description>Serial Peripheral Interface Master with EasyDMA 8</description>
139787 <description>SPI Slave 7</description>
139799 <description>I2C compatible Two-Wire Master Interface with EasyDMA 6</description>
139811 <description>I2C compatible Two-Wire Slave Interface with EasyDMA 6</description>
139823 <description>UART with EasyDMA 7</description>
139835 <description>Serial Peripheral Interface Master with EasyDMA 9</description>
139846 <description>SPI Slave 8</description>
139858 <description>I2C compatible Two-Wire Master Interface with EasyDMA 7</description>
139870 <description>I2C compatible Two-Wire Slave Interface with EasyDMA 7</description>
139882 <description>UART with EasyDMA 8</description>