Lines Matching refs:__OM
147 #ifndef __OM /*!< Fallback for older CMSIS versions …
148 #define __OM __O macro
599 …__OM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Enable chan…
600 …__OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Disable cha…
718 …__OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster: RAMn power …
719 …__OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAMn power …
1021 …__OM uint32_t ITMISCOP0; /*!< (@ 0x00000EE0) Integration Test Miscellaneous O…
1023 …__OM uint32_t ITTRFLINACK; /*!< (@ 0x00000EE4) Integration Test Trigger In and …
1027 …__OM uint32_t ITATBCTR2; /*!< (@ 0x00000EF0) Integration Test ATB Control Reg…
1036 …__OM uint32_t LAR; /*!< (@ 0x00000FB0) Lock Access Register …
1371 …__OM uint32_t TASKS_CLOCKSTART; /*!< (@ 0x00000000) Start all trace and debug clocks…
1372 …__OM uint32_t TASKS_CLOCKSTOP; /*!< (@ 0x00000004) Stop all trace and debug clocks.…
1440 …__OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register …
1459 …__OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK source …
1460 …__OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK source …
1461 …__OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK source …
1462 …__OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK source …
1512 …__OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode. …
1513 …__OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable …
1573 …__OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction …
1574 …__OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction …
1576 …__OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction …
1577 …__OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction …
1638 …__OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore …
1639 …__OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling …
1692 …__OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence …
1694 …__OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence …
1696 …__OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be is…
1699 …__OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction …
1700 …__OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction …
1769 …__OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction …
1771 …__OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction …
1772 …__OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction …
1774 …__OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond…
1775 …__OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond…
1843 …__OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver …
1844 …__OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver …
1845 …__OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter …
1846 …__OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter …
1848 …__OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer …
1927 …__OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection: Task for…
1931 …__OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection: Task for…
1935 …__OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection: Task for…
1975 …__OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the ADC and prepare the re…
1977 …__OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Take one ADC sample, if scan is …
1979 …__OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop the ADC and terminate any o…
1980 …__OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration …
2039 …__OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer …
2040 …__OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer …
2041 …__OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode on…
2042 …__OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time …
2043 …__OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down …
2045 …__OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection: Capture …
2092 …__OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC counter …
2093 …__OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC counter …
2094 …__OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC counter …
2095 …__OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set counter to 0xFFFFF0 …
2140 …__OM DPPIC_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks …
2166 …__OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog …
2184 …__OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection: Reload r…
2199 …__OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection: Trigger …
2230 …__OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on al…
2233 …__OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection: Loads th…
2238 …__OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the curren…
2297 …__OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous PDM transfer …
2298 …__OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PDM transfer …
2344 …__OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous I2S transfer. …
2346 …__OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops I2S transfer. Also stops M…
2399 …__OM uint32_t TASKS_SEND[8]; /*!< (@ 0x00000000) Description collection: Trigger …
2452 …__OM uint32_t TASKS_PUSH_KEYSLOT; /*!< (@ 0x00000000) Push a key slot over secure APB …
2491 …__OM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-vol…
2501 …__OM uint32_t WRITEUICRNS; /*!< (@ 0x00000588) Non-secure APPROTECT enable regi…
2549 …__OM uint32_t AES_KEY_0[8]; /*!< (@ 0x00000400) Description collection: AES key …
2565 …__OM uint32_t AES_SK; /*!< (@ 0x00000478) Writing to this address trigger …
2567 …__OM uint32_t AES_CMAC_INIT; /*!< (@ 0x0000047C) Writing to this address triggers…
2582 …__OM uint32_t AES_SW_RESET; /*!< (@ 0x000004F4) Reset the AES engine. …
2584 …__OM uint32_t AES_CMAC_SIZE0_KICK; /*!< (@ 0x00000524) Writing to this address triggers…
2625 …__OM uint32_t CHACHA_KEY[8]; /*!< (@ 0x00000388) Description collection: CHACHA k…
2639 …__OM uint32_t CHACHA_SW_RESET; /*!< (@ 0x000003C0) Reset the CHACHA engine. …
2662 …__OM uint32_t CRYPTO_CTL; /*!< (@ 0x00000900) Defines the cryptographic flow. …
2685 …__OM uint32_t DIN_BUFFER; /*!< (@ 0x00000C00) Used by CPU to write data direct…
2692 …__OM uint32_t SRC_MEM_ADDR; /*!< (@ 0x00000C28) Data source address in memory. …
2693 …__OM uint32_t SRC_MEM_SIZE; /*!< (@ 0x00000C2C) The number of bytes to be read f…
2696 …__OM uint32_t SRC_SRAM_SIZE; /*!< (@ 0x00000C34) The number of bytes to be read f…
2704 …__OM uint32_t DIN_SW_RESET; /*!< (@ 0x00000C44) Reset the DIN DMA engine. …
2705 …__OM uint32_t DIN_CPU_DATA; /*!< (@ 0x00000C48) Specifies the number of bytes th…
2708 …__OM uint32_t DIN_WRITE_ALIGN; /*!< (@ 0x00000C4C) Indicates that the next CPU writ…
2715 …__OM uint32_t DIN_FIFO_RESET; /*!< (@ 0x00000C58) Reset the DIN FIFO, effectively …
2738 …__OM uint32_t DST_MEM_ADDR; /*!< (@ 0x00000D28) Data destination address in memo…
2739 …__OM uint32_t DST_MEM_SIZE; /*!< (@ 0x00000D2C) The number of bytes to be writte…
2741 …__OM uint32_t DST_SRAM_SIZE; /*!< (@ 0x00000D34) The number of bytes to be writte…
2747 …__OM uint32_t DOUT_READ_ALIGN; /*!< (@ 0x00000D44) Indication that the next CPU rea…
2755 …__OM uint32_t DOUT_SW_RESET; /*!< (@ 0x00000D58) Reset the DOUT DMA engine. …
2775 …__OM uint32_t HASH_PAD_AUTO; /*!< (@ 0x00000684) Configure the HASH engine to aut…
2779 …__OM uint32_t HASH_INIT_STATE; /*!< (@ 0x00000694) Configure HASH engine initial st…
2796 …__OM uint32_t HASH_SW_RESET; /*!< (@ 0x000007E4) Reset the HASH engine. …
2820 …__OM uint32_t ICR; /*!< (@ 0x00000A08) Interrupt clear register. Writin…
2843 …__OM uint32_t HOST_IOT_KDR1; /*!< (@ 0x00000A54) This register holds bits 63:32 o…
2846 …__OM uint32_t HOST_IOT_KDR2; /*!< (@ 0x00000A58) This register holds bits 95:64 o…
2849 …__OM uint32_t HOST_IOT_KDR3; /*!< (@ 0x00000A5C) This register holds bits 127:96 …
2869 …__OM uint32_t AES_CLK; /*!< (@ 0x00000810) Clock control for the AES engine…
2871 …__OM uint32_t HASH_CLK; /*!< (@ 0x00000818) Clock control for the HASH engin…
2872 …__OM uint32_t PKA_CLK; /*!< (@ 0x0000081C) Clock control for the PKA engine…
2873 …__OM uint32_t DMA_CLK; /*!< (@ 0x00000820) Clock control for the DMA engine…
2876 …__OM uint32_t CHACHA_CLK; /*!< (@ 0x00000858) Clock control for the CHACHA eng…
2900 …__OM uint32_t PKA_SW_RESET; /*!< (@ 0x0000008C) Reset the PKA engine. …
2911 …__OM uint32_t PKA_SRAM_WADDR; /*!< (@ 0x000000D4) Start address in PKA SRAM for su…
2913 …__OM uint32_t PKA_SRAM_WDATA; /*!< (@ 0x000000D8) Write data to PKA SRAM. Writing …
2921 …__OM uint32_t PKA_SRAM_WCLEAR; /*!< (@ 0x000000E0) Register for clearing PKA SRAM w…
2922 …__OM uint32_t PKA_SRAM_RADDR; /*!< (@ 0x000000E4) Start address in PKA SRAM for su…
2945 …__OM uint32_t RNG_ICR; /*!< (@ 0x00000108) Interrupt clear register. Writin…
2967 …__OM uint32_t RNG_SW_RESET; /*!< (@ 0x00000140) Reset the RNG engine. …
2970 …__OM uint32_t TRNG_RESET; /*!< (@ 0x000001BC) Reset the TRNG, including intern…
2975 …__OM uint32_t RNG_CLK; /*!< (@ 0x000001C4) Control clock for the RNG engine…
3009 …__OM uint32_t SRAM_ADDR; /*!< (@ 0x00000F04) First address given to RNG SRAM …