Lines Matching full:description
9 …<description>nRF54H20 reference description for system-on-chip with many ARM 32-bit Cortex-M33 mic…
54 <description>Factory Information Configuration Registers</description>
68 <description>Unspecified</description>
74 <description>Device address type.</description>
82 <description>Device address type.</description>
88 <description>Public address.</description>
93 <description>Random address.</description>
104 <description>Description collection: 48 bit device address.</description>
112 <description>Device address [n].</description>
122 <description>Description collection: Encryption Root.</description>
130 <description>Encryption root word [n].</description>
140 <description>Description collection: Identity Root.</description>
148 <description>Identity root word [n].</description>
157 <description>Unspecified</description>
165 <description>Description collection: Default header for NFC Tag.</description>
173 <description>Unique identifier byte 0</description>
179 <description>Unique identifier byte 1</description>
185 <description>Unique identifier byte 2</description>
191 <description>Unique identifier byte 3</description>
200 <description>Device info</description>
206 <description>Configuration identifier</description>
214 <description>Identification number for the HW</description>
222 <description>Part code</description>
230 <description>Part code</description>
236 <description>Unspecified</description>
245 <description>Part Variant, Hardware version and Production configuration</description>
253 …<description>Part Variant, Hardware version and Production configuration, encoded as ASCII</descri…
259 <description>Unspecified</description>
268 <description>Package option</description>
276 <description>Package option</description>
282 <description>Unspecified</description>
291 <description>RAM variant</description>
299 <description>RAM variant</description>
305 <description>Unspecified</description>
314 <description>MRAM variant</description>
322 <description>MRAM variant</description>
328 <description>Unspecified</description>
337 <description>Code memory page size in bytes</description>
345 <description>Code memory page size in bytes</description>
351 <description>Unspecified</description>
360 <description>Code memory size</description>
368 <description>Code memory size in number of pages</description>
374 <description>Unspecified</description>
383 <description>Device type</description>
391 <description>Device type</description>
397 <description>Device is an physical DIE</description>
402 <description>Device is an FPGA</description>
412 <description>Unspecified</description>
418 <description>Unspecified</description>
424 <description>Unspecified</description>
432 <description>Description collection: Trim value for GLOBAL.SAADC.CAL</description>
440 <description>Trim value</description>
448 <description>Trim value for GLOBAL.SAADC.CALREF</description>
456 <description>Trim value</description>
466 … <description>Description collection: Trim value for GLOBAL.SAADC.TRIM.LINCALCOEFF</description>
474 <description>Trim value</description>
483 <description>Unspecified</description>
489 <description>Trim value for NFCT.BIASCFG</description>
497 <description>Trim value</description>
506 <description>Unspecified</description>
512 <description>Unspecified</description>
518 <description>Trim value for GLOBAL.CANPLL.TRIM.CTUNE</description>
526 <description>Trim value</description>
536 <description>Unspecified</description>
542 <description>Trim value for GLOBAL.COMP.REFTRIM</description>
550 <description>Trim value</description>
560 <description>Unspecified</description>
566 <description>Unspecified</description>
572 <description>Unspecified</description>
578 <description>Trim value for APPLICATION.HSFLL.TRIM.VSUP</description>
586 <description>Trim value</description>
596 … <description>Description collection: Trim value for APPLICATION.HSFLL.TRIM.COARSE</description>
604 <description>Trim value</description>
614 … <description>Description collection: Trim value for APPLICATION.HSFLL.TRIM.FINE</description>
622 <description>Trim value</description>
630 <description>Trim value for APPLICATION.HSFLL.TRIM.TCOEF</description>
638 <description>Trim value</description>
648 <description>Unspecified</description>
656 <description>Unspecified</description>
662 …<description>Description cluster: Trim value for APPLICATION.MEMCONF.BLOCKTYPE[n].TRIM</descriptio…
670 <description>Trim value</description>
681 <description>Unspecified</description>
687 <description>Unspecified</description>
693 <description>Unspecified</description>
699 <description>Trim value for RADIOCORE.HSFLL.TRIM.VSUP</description>
707 <description>Trim value</description>
717 … <description>Description collection: Trim value for RADIOCORE.HSFLL.TRIM.COARSE</description>
725 <description>Trim value</description>
735 … <description>Description collection: Trim value for RADIOCORE.HSFLL.TRIM.FINE</description>
743 <description>Trim value</description>
751 <description>Trim value for RADIOCORE.HSFLL.TRIM.TCOEF</description>
759 <description>Trim value</description>
769 <description>Unspecified</description>
777 <description>Unspecified</description>
783 … <description>Description cluster: Trim value for RADIOCORE.MEMCONF.BLOCKTYPE[n].TRIM</description>
791 <description>Trim value</description>
805 <description>USBHSCORE</description>
820 <description>Control and Status Register</description>
828 <description>Mode: Host only. VBUS Valid Override Enable (VbvalidOvEn)</description>
834 …<description>Override is disabled and bvalid signal from the respective PHY selected is used inter…
839 …<description>The vbus-valid signal received from the PHY is overridden with GOTGCTL.VbvalidOvVal</…
846 <description>Mode: Host only. VBUS Valid OverrideValue (VbvalidOvVal)</description>
852 <description>vbusvalid value when GOTGCTL.VbvalidOvEn = 1</description>
857 <description>vbusvalid value when GOTGCTL.VbvalidOvEn is 1</description>
864 …<description>Mode: Host only. A-Peripheral Session Valid Override Enable (AvalidOvEn)</description>
870 <description>Derive AValid from PHY</description>
875 <description>Derive Avalid from GOTGCTL.AvalidOvVal</description>
882 … <description>Mode: Host only. A-Peripheral Session Valid OverrideValue (AvalidOvVal)</description>
888 <description>Avalid value is 1'b0 when GOTGCTL.AvalidOvEn =1</description>
893 <description>Avalid value is 1'b1 when GOTGCTL.AvalidOvEn =1</description>
900 …<description>Mode: Device only. B-Peripheral Session Valid Override Value (BvalidOvEn)</descriptio…
906 …<description>Override is disabled and bvalid signal from the respective PHY selected is used inter…
911 …<description>Internally Bvalid received from the PHY is overridden with GOTGCTL.BvalidOvVal</descr…
918 …<description>Mode: Device only. B-Peripheral Session Valid OverrideValue (BvalidOvVal)</descriptio…
924 <description>Bvalid value when GOTGCTL.BvalidOvEn =1</description>
929 <description>Bvalid value when GOTGCTL.BvalidOvEn =1</description>
936 <description>Mode: Host and Device. Debounce Filter Bypass</description>
942 <description>Debounce Filter Bypass is disabled.</description>
947 <description>Debounce Filter Bypass is enabled.</description>
954 <description>Mode: Host and Device. Connector ID Status (ConIDSts)</description>
961 <description>The core is in A-Device mode.</description>
966 <description>The core is in B-Device mode.</description>
973 <description>Mode: Host only. Long/Short Debounce Time (DbncTime)</description>
980 …<description>Long debounce time, used for physical connections (100 ms + 2.5 micro-sec)</descripti…
985 … <description>Short debounce time, used for soft connections (2.5 micro-sec)</description>
992 <description>Mode: Host only. A-Session Valid (ASesVld)</description>
999 <description>A-session is not valid.</description>
1004 <description>A-session is valid.</description>
1011 <description>Mode: Device only. B-Session Valid (BSesVld)</description>
1018 <description>B-session is not valid.</description>
1023 <description>B-session is valid.</description>
1030 <description>OTG Version (OTGVer)</description>
1036 <description>Supports OTG Version 1.3</description>
1041 <description>Supports OTG Version 2.0</description>
1048 <description>Current Mode of Operation (CurMod)</description>
1055 <description>Current mode is device mode.</description>
1060 <description>Current mode is host mode.</description>
1067 <description>Mode: Host and Device. Multi Valued ID pin (MultValIdBC)</description>
1074 <description>B-Device connected to ACA. VBUS is on.</description>
1079 <description>B-Device connected to ACA. VBUS is off.</description>
1084 <description>A-Device connected to ACA</description>
1089 <description>A-Device not connected to ACA</description>
1094 <description>B-Device not connected to ACA</description>
1101 …description>Mode: Device Only. This bit when programmed to 1'b1 results in the core asserting chir…
1107 …<description>The controller does not assert chirp_on before sending an actual Chirp 'K' signal on …
1112 …<description>The controller asserts chirp_on before sending an actual Chirp 'K' signal on USB.</de…
1121 <description>Interrupt Register</description>
1129 <description>Mode: Host and Device. Session End Detected (SesEndDet)</description>
1135 <description>Session is Active</description>
1140 <description>SessionEnd utmiotg_bvalid signal is deasserted</description>
1147 …<description>Mode: Host and Device. Session Request Success Status Change (SesReqSucStsChng)</desc…
1153 <description>No Change in Session Request Status</description>
1158 <description>Session Request Status has changed</description>
1165 …<description>Mode: Host and Device. Host Negotiation Success Status Change (HstNegSucStsChng)</des…
1171 <description>No Change</description>
1176 <description>Host Negotiation Status Change</description>
1183 <description>Mode:Host and Device. Host Negotiation Detected (HstNegDet)</description>
1189 <description>No Active HNP Request</description>
1194 <description>Active HNP request detected</description>
1201 … <description>Mode: Host and Device. A-Device Timeout Change (ADevTOUTChg)</description>
1207 <description>No A-Device Timeout</description>
1212 <description>A-Device Timeout</description>
1219 <description>Mode: Host only. Debounce Done (DbnceDone)</description>
1225 <description>After Connect waiting for Debounce to complete</description>
1230 <description>Debounce completed</description>
1237 …<description>This bit when set indicates that there is a change in the value of at least one ACA p…
1243 <description>Indicates there is no change in ACA pin value</description>
1248 <description>Indicates there is a change in ACA pin value</description>
1257 <description>AHB Configuration Register</description>
1265 <description>Mode: Host and device. Global Interrupt Mask (GlblIntrMsk)</description>
1271 <description>Mask the interrupt assertion to the application</description>
1276 <description>Unmask the interrupt assertion to the application.</description>
1283 <description>Mode: Host and device. Burst Length/Type (HBstLen)</description>
1289 <description>1 word or single</description>
1294 <description>4 words or INCR</description>
1299 <description>8 words</description>
1304 <description>16 words or INCR4</description>
1309 <description>32 words</description>
1314 <description>64 words or INCR8</description>
1319 <description>128 words</description>
1324 <description>256 words or INCR16</description>
1329 <description>Others reserved</description>
1336 <description>Mode: Host and device. DMA Enable (DMAEn)</description>
1342 <description>Core operates in Slave mode</description>
1347 <description>Core operates in a DMA mode</description>
1354 … <description>Mode: Host and device. Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)</description>
1360 …<description>DIEPINTn.TxFEmp interrupt indicates that the Non-Periodic TxFIFO is half empty or tha…
1365 …description>GINTSTS.NPTxFEmp interrupt indicates that the Non-Periodic TxFIFO is completely empty …
1372 <description>Mode: Host and Device. Remote Memory Support (RemMemSupp)</description>
1378 <description>Remote Memory Support Feature disabled</description>
1383 <description>Remote Memory Support Feature enabled</description>
1390 …<description>Mode: Host and Device. Notify All DMA Write Transactions (NotiAllDmaWrit)</descriptio…
1396 <description>Unspecified</description>
1401 …description>The core asserts int_dma_req for all the DMA write transactions on the AHB interface a…
1408 <description>Mode: Host and Device. AHB Single Support (AHBSingle)</description>
1414 … <description>The remaining data in the transfer is sent using INCR burst size</description>
1419 … <description>The remaining data in the transfer is sent using Single burst size</description>
1428 <description>USB Configuration Register</description>
1436 <description>Mode: Host and Device. HS/FS Timeout Calibration (TOutCal)</description>
1442 <description>Add 0 PHY clocks</description>
1447 <description>Add 1 PHY clocks</description>
1452 <description>Add 2 PHY clocks</description>
1457 <description>Add 3 PHY clocks</description>
1462 <description>Add 4 PHY clocks</description>
1467 <description>Add 5 PHY clocks</description>
1472 <description>Add 6 PHY clocks</description>
1477 <description>Add 7 PHY clocks</description>
1484 <description>Mode: Host and Device. PHY Interface (PHYIf)</description>
1490 <description>PHY 8bit Mode</description>
1495 <description>PHY 16bit Mode</description>
1502 <description>Mode: Host and Device. ULPI or UTMI+ Select (ULPI_UTMI_Sel)</description>
1509 <description>UTMI+ Interface</description>
1514 <description>ULPI Interface</description>
1521 … <description>Mode: Host and Device. Full-Speed Serial Interface Select (FSIntf)</description>
1528 <description>6-pin unidirectional full-speed serial interface</description>
1533 <description>3-pin bidirectional full-speed serial interface</description>
1540 <description>PHYSel</description>
1547 <description>USB 2.0 high-speed UTMI+ or ULPI PHY is selected</description>
1552 <description>USB 1.1 full-speed serial transceiver is selected</description>
1559 <description>Mode: Device only. USB Turnaround Time (USBTrdTim)</description>
1565 <description>MAC interface is 16-bit UTMI+.</description>
1570 <description>MAC interface is 8-bit UTMI+.</description>
1577 <description>PHY Low-Power Clock Select (PhyLPwrClkSel)</description>
1583 <description>480-MHz Internal PLL clock</description>
1588 <description>48-MHz External Clock</description>
1595 … <description>Mode: Device only. TermSel DLine Pulsing Selection (TermSelDLPulse)</description>
1601 <description>Data line pulsing using utmi_txvalid</description>
1606 <description>Data line pulsing using utmi_termsel</description>
1613 <description>Mode: Host and Device. IC_USB-Capable (IC_USBCap)</description>
1620 <description>IC_USB PHY Interface is not selected</description>
1625 <description>IC_USB PHY Interface is selected</description>
1632 <description>Mode: Device only. Tx End Delay (TxEndDelay)</description>
1638 <description>Normal Mode</description>
1643 <description>Tx End delay</description>
1650 <description>Mode: Host and device. Force Host Mode (ForceHstMode)</description>
1656 <description>Normal Mode</description>
1661 <description>Force Host Mode</description>
1668 <description>Mode:Host and device. Force Device Mode (ForceDevMode)</description>
1674 <description>Normal Mode</description>
1679 <description>Force Device Mode</description>
1686 <description>Mode: Host and device. Corrupt Tx packet (CorruptTxPkt)</description>
1693 <description>Normal Mode</description>
1698 <description>Debug Mode</description>
1707 <description>Reset Register</description>
1715 <description>Mode: Host and Device. Core Soft Reset (CSftRst)</description>
1721 <description>No reset</description>
1726 <description>Resets hclk and phy_clock domains</description>
1733 …<description>Mode: Host and Device. PIU FS Dedicated Controller Soft Reset (PIUFSSftRst)</descript…
1739 <description>No Reset</description>
1744 <description>PIU FS Dedicated Controller Soft Reset</description>
1751 <description>Mode: Host only. Host Frame Counter Reset (FrmCntrRst)</description>
1757 <description>No reset</description>
1762 <description>Host Frame Counter Reset</description>
1769 <description>Mode: Host and Device. RxFIFO Flush (RxFFlsh)</description>
1775 <description>Does not flush the entire RxFIFO</description>
1780 <description>Flushes the entire RxFIFO</description>
1787 <description>Mode: Host and Device. TxFIFO Flush (TxFFlsh)</description>
1793 <description>No Flush</description>
1798 <description>Selectively flushes a single or all transmit FIFOs</description>
1805 <description>Mode: Host and Device. TxFIFO Number (TxFNum)</description>
1811 …description>-Periodic TxFIFO flush in host mode -Periodic TxFIFO 0 flush in device mode when in sh…
1816 …description>-Periodic TxFIFO flush in host mode -Periodic TxFIFO 1 flush in device mode when in sh…
1821 …description>-Periodic TxFIFO 2 flush in device mode when in shared FIFO operation -TXFIFO 2 flush …
1826 …description>-Periodic TxFIFO 3 flush in device mode when in shared FIFO operation -TXFIFO 3 flush …
1831 …description>-Periodic TxFIFO 4 flush in device mode when in shared FIFO operation -TXFIFO 4 flush …
1836 …description>-Periodic TxFIFO 5 flush in device mode when in shared FIFO operation -TXFIFO 5 flush …
1841 …description>-Periodic TxFIFO 6 flush in device mode when in shared FIFO operation -TXFIFO 6 flush …
1846 …description>-Periodic TxFIFO 7 flush in device mode when in shared FIFO operation -TXFIFO 7 flush …
1851 …description>-Periodic TxFIFO 8 flush in device mode when in shared FIFO operation -TXFIFO 8 flush …
1856 …description>-Periodic TxFIFO 9 flush in device mode when in shared FIFO operation -TXFIFO 9 flush …
1861 …description>-Periodic TxFIFO 10 flush in device mode when in shared FIFO operation -TXFIFO 10 flus…
1866 …description>-Periodic TxFIFO 11 flush in device mode when in shared FIFO operation -TXFIFO 11 flus…
1871 …description>-Periodic TxFIFO 12 flush in device mode when in shared FIFO operation -TXFIFO 12 flus…
1876 …description>-Periodic TxFIFO 13 flush in Device mode when in shared FIFO operation -TXFIFO 13 flus…
1881 …description>-Periodic TxFIFO 14 flush in Device mode when in shared FIFO operation -TXFIFO 14 flus…
1886 …description>-Periodic TxFIFO 15 flush in Device mode when in shared FIFO operation - TXFIFO 15 flu…
1891 <description>Flush all the transmit FIFOs in device or host mode</description>
1898 <description>Mode: Host and Device. Core Soft Reset Done (CSftRstDone)</description>
1904 <description>No reset</description>
1909 <description>Core Soft Reset is done</description>
1916 <description>Mode: Host and Device. DMA Request Signal (DMAReq)</description>
1923 <description>No DMA request</description>
1928 <description>DMA request is in progress</description>
1935 <description>Mode: Host and Device. AHB Master Idle (AHBIdle)</description>
1942 <description>Not Idle</description>
1947 <description>AHB Master Idle</description>
1956 <description>Interrupt Register</description>
1964 <description>Mode: Host and Device. Current Mode of Operation (CurMod)</description>
1971 <description>Device mode</description>
1976 <description>Host mode</description>
1983 <description>Mode: Host and Device. Mode Mismatch Interrupt (ModeMis)</description>
1989 <description>No Mode Mismatch Interrupt</description>
1994 <description>Mode Mismatch Interrupt</description>
2001 <description>Mode: Host and Device. OTG Interrupt (OTGInt)</description>
2008 <description>No Interrupt</description>
2013 <description>OTG Interrupt</description>
2020 <description>Mode: Host and Device. Start of (micro)Frame (Sof)</description>
2026 <description>No Start of Frame</description>
2031 <description>Start of Frame</description>
2038 <description>Mode: Host and Device. RxFIFO Non-Empty (RxFLvl)</description>
2045 <description>Rx Fifo is empty</description>
2050 <description>Rx Fifo is not empty</description>
2057 <description>Mode: Host and Device. Non-periodic TxFIFO Empty (NPTxFEmp)</description>
2064 <description>Non-periodic TxFIFO is not empty</description>
2069 <description>Non-periodic TxFIFO is empty</description>
2076 … <description>Mode: Device only. Global IN Non-periodic NAK Effective (GINNakEff)</description>
2083 <description>Global Non-periodic IN NAK not active</description>
2088 <description>Set Global Non-periodic IN NAK bit</description>
2095 <description>Mode: Device only. Global OUT NAK Effective (GOUTNakEff)</description>
2102 <description>Not Active</description>
2107 <description>Global OUT NAK Effective</description>
2114 <description>Mode: Device only. Early Suspend (ErlySusp)</description>
2120 <description>No Idle state detected</description>
2125 <description>3ms of Idle state detected</description>
2132 <description>Mode: Device only. USB Suspend (USBSusp)</description>
2138 <description>Not Active</description>
2143 <description>USB Suspend</description>
2150 <description>Mode: Device only. USB Reset (USBRst)</description>
2156 <description>Not active</description>
2161 <description>USB Reset</description>
2168 <description>Mode: Device only. Enumeration Done (EnumDone)</description>
2174 <description>Not active</description>
2179 <description>Enumeration Done</description>
2186 …<description>Mode: Device only. Isochronous OUT Packet Dropped Interrupt (ISOOutDrop)</description>
2192 <description>Not active</description>
2197 <description>Isochronous OUT Packet Dropped Interrupt</description>
2204 <description>Mode: Device only. End of Periodic Frame Interrupt (EOPF)</description>
2210 <description>Not active</description>
2215 <description>End of Periodic Frame Interrupt</description>
2222 <description>Mode: Device only. Restore Done Interrupt (RstrDoneInt)</description>
2228 <description>Not active</description>
2233 <description>Restore Done Interrupt</description>
2240 <description>Mode: Device only. Endpoint Mismatch Interrupt (EPMis)</description>
2246 <description>Not active</description>
2251 <description>Endpoint Mismatch Interrupt</description>
2258 <description>Mode: Device only. IN Endpoints Interrupt (IEPInt)</description>
2265 <description>Not active</description>
2270 <description>IN Endpoints Interrupt</description>
2277 <description>Mode: Device only. OUT Endpoints Interrupt (OEPInt)</description>
2284 <description>Not active</description>
2289 <description>OUT Endpoints Interrupt</description>
2296 … <description>Mode: Device only. Incomplete Isochronous IN Transfer (incompISOIN)</description>
2302 <description>Not active</description>
2307 <description>Incomplete Isochronous IN Transfer</description>
2314 <description>Incomplete Periodic Transfer (incomplP)</description>
2320 <description>Not active</description>
2325 <description>Incomplete Periodic Transfer</description>
2332 <description>Mode: Device only. Data Fetch Suspended (FetSusp)</description>
2338 <description>Not active</description>
2343 <description>Data Fetch Suspended</description>
2350 <description>Mode: Device only. Reset detected Interrupt (ResetDet)</description>
2356 <description>Not active</description>
2361 <description>Reset detected Interrupt</description>
2368 <description>Mode: Host only. Host Port Interrupt (PrtInt)</description>
2375 <description>Not active</description>
2380 <description>Host Port Interrupt</description>
2387 <description>Mode: Host only. Host Channels Interrupt (HChInt)</description>
2394 <description>Not active</description>
2399 <description>Host Channels Interrupt</description>
2406 … <description>Mode: Host and Device. LPM Transaction Received Interrupt (LPM_Int).</description>
2412 <description>Not Active</description>
2417 <description>LPM Transaction Received Interrupt</description>
2424 … <description>Mode: Host and Device. Connector ID Status Change (ConIDStsChng)</description>
2430 <description>Not Active</description>
2435 <description>Connector ID Status Change</description>
2442 <description>Mode: Host only. Disconnect Detected Interrupt (DisconnInt)</description>
2448 <description>Not active</description>
2453 <description>Disconnect Detected Interrupt</description>
2460 …<description>Mode: Host and Device. Session Request/New Session Detected Interrupt (SessReqInt)</d…
2466 <description>Not active</description>
2471 <description>Session Request New Session Detected Interrupt</description>
2478 …<description>Mode: Host and Device. Resume/Remote Wakeup Detected Interrupt (WkUpInt)</description>
2484 <description>Not active</description>
2489 <description>Resume or Remote Wakeup Detected Interrupt</description>
2498 <description>Interrupt Mask Register</description>
2506 … <description>Mode: Host and Device. Mode Mismatch Interrupt Mask (ModeMisMsk)</description>
2512 <description>Mode Mismatch Interrupt Mask</description>
2517 <description>No Mode Mismatch Interrupt Mask</description>
2524 <description>Mode: Host and Device. OTG Interrupt Mask (OTGIntMsk)</description>
2530 <description>OTG Interrupt Mask</description>
2535 <description>No OTG Interrupt Mask</description>
2542 <description>Mode: Host and Device. Start of (micro)Frame Mask (SofMsk)</description>
2548 <description>Start of Frame Mask</description>
2553 <description>No Start of Frame Mask</description>
2560 … <description>Mode: Host and Device. Receive FIFO Non-Empty Mask (RxFLvlMsk)</description>
2566 <description>Receive FIFO Non-Empty Mask</description>
2571 <description>No Receive FIFO Non-Empty Mask</description>
2578 … <description>Mode: Host and Device. Non-periodic TxFIFO Empty Mask (NPTxFEmpMsk)</description>
2584 <description>Non-periodic TxFIFO Empty Mask</description>
2589 <description>No Non-periodic TxFIFO Empty Mask</description>
2596 …<description>Mode: Device only,. Global Non-periodic IN NAK Effective Mask (GINNakEffMsk)</descrip…
2602 <description>Global Non-periodic IN NAK Effective Mask</description>
2607 <description>No Global Non-periodic IN NAK Effective Mask</description>
2614 … <description>Mode: Device only. Global OUT NAK Effective Mask (GOUTNakEffMsk)</description>
2620 <description>Global OUT NAK Effective Mask</description>
2625 <description>No Global OUT NAK Effective Mask</description>
2632 <description>Mode: Device only. Early Suspend Mask (ErlySuspMsk)</description>
2638 <description>Early Suspend Mask</description>
2643 <description>No Early Suspend Mask</description>
2650 <description>Mode: Device only. USB Suspend Mask (USBSuspMsk)</description>
2656 <description>USB Suspend Mask</description>
2661 <description>No USB Suspend Mask</description>
2668 <description>Mode: Device only. USB Reset Mask (USBRstMsk)</description>
2674 <description>USB Reset Mask</description>
2679 <description>No USB Reset Mask</description>
2686 <description>Mode: Device only. Enumeration Done Mask (EnumDoneMsk)</description>
2692 <description>Enumeration Done Mask</description>
2697 <description>No Enumeration Done Mask</description>
2704 …<description>Mode: Device only. Isochronous OUT Packet Dropped Interrupt Mask (ISOOutDropMsk)</des…
2710 <description>Isochronous OUT Packet Dropped Interrupt Mask</description>
2715 <description>No Isochronous OUT Packet Dropped Interrupt Mask</description>
2722 … <description>Mode: Device only. End of Periodic Frame Interrupt Mask (EOPFMsk)</description>
2728 <description>End of Periodic Frame Interrupt Mask</description>
2733 <description>No End of Periodic Frame Interrupt Mask</description>
2740 … <description>Mode: Host and Device. Restore Done Interrupt Mask (RstrDoneIntMsk)</description>
2746 <description>Restore Done Interrupt Mask</description>
2751 <description>No Restore Done Interrupt Mask</description>
2758 … <description>Mode: Device only. Endpoint Mismatch Interrupt Mask (EPMisMsk)</description>
2764 <description>Endpoint Mismatch Interrupt Mask</description>
2769 <description>No Endpoint Mismatch Interrupt Mask</description>
2776 <description>Mode: Device only. IN Endpoints Interrupt Mask (IEPIntMsk)</description>
2782 <description>IN Endpoints Interrupt Mask</description>
2787 <description>No IN Endpoints Interrupt Mask</description>
2794 <description>Mode: Device only. OUT Endpoints Interrupt Mask (OEPIntMsk)</description>
2800 <description>OUT Endpoints Interrupt Mask</description>
2805 <description>No OUT Endpoints Interrupt Mask</description>
2812 <description>Incomplete Periodic Transfer Mask (incomplPMsk)</description>
2818 …<description>Host mode: Incomplete Periodic Transfer MaskDevice mode: Incomplete Isochronous OUT T…
2823 …<description>Host mode: No Incomplete Periodic Transfer MaskDevice mode: No Incomplete Isochronous…
2830 <description>Mode: Device only. Data Fetch Suspended Mask (FetSuspMsk)</description>
2836 <description>Data Fetch Suspended Mask</description>
2841 <description>No Data Fetch Suspended Mask</description>
2848 … <description>Mode: Device only. Reset detected Interrupt Mask (ResetDetMsk)</description>
2854 <description>Reset detected Interrupt Mask</description>
2859 <description>No Reset detected Interrupt Mask</description>
2866 <description>Mode: Host only. Host Port Interrupt Mask (PrtIntMsk)</description>
2872 <description>Host Port Interrupt Mask</description>
2877 <description>No Host Port Interrupt Mask</description>
2884 <description>Mode: Host only. Host Channels Interrupt Mask (HChIntMsk)</description>
2890 <description>Host Channels Interrupt Mask</description>
2895 <description>No Host Channels Interrupt Mask</description>
2902 … <description>Mode: Host and Device. LPM Transaction Received Interrupt (LPM_Int)</description>
2908 <description>LPM Transaction received interrupt Mask</description>
2913 <description>No LPM Transaction received interrupt Mask</description>
2920 …<description>Mode: Host and Device. Connector ID Status Change Mask (ConIDStsChngMsk)</description>
2926 <description>Connector ID Status Change Mask</description>
2931 <description>No Connector ID Status Change Mask</description>
2938 …<description>Mode: Host and Device. Disconnect Detected Interrupt Mask (DisconnIntMsk)</descriptio…
2944 <description>Disconnect Detected Interrupt Mask</description>
2949 <description>No Disconnect Detected Interrupt Mask</description>
2956 …<description>Mode: Host and Device. Session Request/New Session Detected Interrupt Mask (SessReqIn…
2962 <description>Session Request or New Session Detected Interrupt Mask</description>
2967 … <description>No Session Request or New Session Detected Interrupt Mask</description>
2974 …<description>Mode: Host and Device. Resume/Remote Wakeup Detected Interrupt Mask (WkUpIntMsk)</des…
2980 <description>Resume or Remote Wakeup Detected Interrupt Mask</description>
2985 <description>Unmask Resume Remote Wakeup Detected Interrupt</description>
2994 <description>Receive Status Debug Read Register</description>
3002 <description>Channel Number (ChNum)</description>
3009 <description>Channel or EndPoint 0</description>
3014 <description>Channel or EndPoint 1</description>
3019 <description>Channel or EndPoint 2</description>
3024 <description>Channel or EndPoint 3</description>
3029 <description>Channel or EndPoint 4</description>
3034 <description>Channel or EndPoint 5</description>
3039 <description>Channel or EndPoint 6</description>
3044 <description>Channel or EndPoint 7</description>
3049 <description>Channel or EndPoint 8</description>
3054 <description>Channel or EndPoint 9</description>
3059 <description>Channel or EndPoint 10</description>
3064 <description>Channel or EndPoint 11</description>
3069 <description>Channel or EndPoint 12</description>
3074 <description>Channel or EndPoint 13</description>
3079 <description>Channel or EndPoint 14</description>
3084 <description>Channel or EndPoint 15</description>
3091 <description>Byte Count (BCnt)</description>
3098 <description>Data PID (DPID)</description>
3105 <description>DATA0</description>
3110 <description>DATA2</description>
3115 <description>DATA1</description>
3120 <description>MDATA</description>
3127 … <description>Packet Status (PktSts) indicates the status of the received packet.</description>
3134 <description>Global OUT NAK in device mode (triggers an interrupt)</description>
3139 …<description>IN data packet received in host mode and OUT data packet received in device mode</des…
3144 …<description>IN or OUT transfer completed in both host and device mode (triggers an interrupt)</de…
3149 … <description>SETUP transaction completed in device mode (triggers an interrupt)</description>
3154 <description>Data toggle error (triggers an interrupt) in host mode</description>
3159 <description>SETUP data packet received in device mode</description>
3164 <description>Channel halted in host mode (triggers an interrupt)</description>
3171 <description>Mode: Device only. Frame Number (FN)</description>
3180 <description>Receive Status Read/Pop Register</description>
3188 <description>Channel Number (ChNum)</description>
3195 <description>Channel or EndPoint 0</description>
3200 <description>Channel or EndPoint 1</description>
3205 <description>Channel or EndPoint 2</description>
3210 <description>Channel or EndPoint 3</description>
3215 <description>Channel or EndPoint 4</description>
3220 <description>Channel or EndPoint 5</description>
3225 <description>Channel or EndPoint 6</description>
3230 <description>Channel or EndPoint 7</description>
3235 <description>Channel or EndPoint 8</description>
3240 <description>Channel or EndPoint 9</description>
3245 <description>Channel or EndPoint 10</description>
3250 <description>Channel or EndPoint 11</description>
3255 <description>Channel or EndPoint 12</description>
3260 <description>Channel or EndPoint 13</description>
3265 <description>Channel or EndPoint 14</description>
3270 <description>Channel or EndPoint 15</description>
3277 <description>Byte Count (BCnt)</description>
3284 <description>Data PID (DPID)</description>
3291 <description>DATA0</description>
3296 <description>DATA2</description>
3301 <description>DATA1</description>
3306 <description>MDATA</description>
3313 … <description>Packet Status (PktSts) indicates the status of the received packet.</description>
3320 <description>Global OUT NAK in device mode (triggers an interrupt)</description>
3325 …<description>IN data packet received in host mode and OUT data packet received in device mode</des…
3330 …<description>IN or OUT transfer completed in both host and device mode (triggers an interrupt)</de…
3335 … <description>SETUP transaction completed in device mode (triggers an interrupt)</description>
3340 <description>Data toggle error (triggers an interrupt) in host mode</description>
3347 <description>Mode: Device only. Frame Number (FN)</description>
3356 <description>Receive FIFO Size Register</description>
3364 <description>Mode: Host and Device. RxFIFO Depth (RxFDep)</description>
3372 <description>Non-periodic Transmit FIFO Size Register</description>
3380 <description>Non-periodic Transmit RAM Start Address (NPTxFStAddr)</description>
3386 <description>Mode: Host only. Non-periodic TxFIFO Depth (NPTxFDep)</description>
3394 <description>Non-periodic Transmit FIFO/Queue Status Register</description>
3402 <description>Non-periodic TxFIFO Space Avail (NPTxFSpcAvail)</description>
3409 … <description>Non-periodic Transmit Request Queue Space Available (NPTxQSpcAvail)</description>
3416 <description>Non-periodic Transmit Request Queue is full</description>
3421 <description>1 location available</description>
3426 <description>2 locations available</description>
3431 <description>3 locations available</description>
3436 <description>4 locations available</description>
3441 <description>5 locations available</description>
3446 <description>6 locations available</description>
3451 <description>7 locations available</description>
3456 <description>8 locations available</description>
3463 <description>Top of the Non-periodic Transmit Request Queue (NPTxQTop)</description>
3470 <description>IN/OUT token</description>
3475 <description>Zero-length transmit packet (device IN/host OUT)</description>
3480 <description>PING/CSPLIT token</description>
3485 <description>Channel halt command</description>
3494 <description>General Purpose Input/Output Register</description>
3515 <description>User ID Register</description>
3523 <description>User ID (UserID) Application-programmable ID field.</description>
3531 <description>Synopsys ID Register</description>
3539 <description>Release number of the controller being used currently.</description>
3548 <description>User Hardware Configuration 1 Register</description>
3556 <description>This 32-bit field uses two bits per</description>
3565 <description>User Hardware Configuration 2 Register</description>
3573 <description>Mode of Operation (OtgMode)</description>
3580 <description>HNP- and SRP-Capable OTG (Host and Device)</description>
3585 <description>SRP-Capable OTG (Host and Device)</description>
3590 <description>Non-HNP and Non-SRP Capable OTG (Host and Device)</description>
3595 <description>SRP-Capable Device</description>
3600 <description>Non-OTG Device</description>
3605 <description>SRP-Capable Host</description>
3610 <description>Non-OTG Host</description>
3617 <description>Architecture (OtgArch)</description>
3624 <description>Slave Mode</description>
3629 <description>External DMA Mode</description>
3634 <description>Internal DMA Mode</description>
3641 <description>Point-to-Point (SingPnt)</description>
3648 <description>Multi-point application (hub and split support)</description>
3653 <description>Single-point application (no hub and split support)</description>
3660 <description>High-Speed PHY Interface Type (HSPhyType)</description>
3667 <description>High-Speed interface not supported</description>
3672 <description>High Speed Interface UTMI+ is supported</description>
3677 <description>High Speed Interface ULPI is supported</description>
3682 <description>High Speed Interfaces UTMI+ and ULPI is supported</description>
3689 <description>Full-Speed PHY Interface Type (FSPhyType)</description>
3696 <description>Full-speed interface not supported</description>
3701 <description>Dedicated full-speed interface is supported</description>
3706 <description>FS pins shared with UTMI+ pins is supported</description>
3711 <description>FS pins shared with ULPI pins is supported</description>
3718 <description>Number of Device Endpoints (NumDevEps)</description>
3725 <description>End point 0</description>
3730 <description>End point 1</description>
3735 <description>End point 2</description>
3740 <description>End point 3</description>
3745 <description>End point 4</description>
3750 <description>End point 5</description>
3755 <description>End point 6</description>
3760 <description>End point 7</description>
3765 <description>End point 8</description>
3770 <description>End point 9</description>
3775 <description>End point 10</description>
3780 <description>End point 11</description>
3785 <description>End point 12</description>
3790 <description>End point 13</description>
3795 <description>End point 14</description>
3800 <description>End point 15</description>
3807 <description>Number of Host Channels (NumHstChnl)</description>
3814 <description>Host Channel 1</description>
3819 <description>Host Channel 2</description>
3824 <description>Host Channel 3</description>
3829 <description>Host Channel 4</description>
3834 <description>Host Channel 5</description>
3839 <description>Host Channel 6</description>
3844 <description>Host Channel 7</description>
3849 <description>Host Channel 8</description>
3854 <description>Host Channel 9</description>
3859 <description>Host Channel 10</description>
3864 <description>Host Channel 11</description>
3869 <description>Host Channel 12</description>
3874 <description>Host Channel 13</description>
3879 <description>Host Channel 14</description>
3884 <description>Host Channel 15</description>
3889 <description>Host Channel 16</description>
3896 <description>Periodic OUT Channels Supported in Host Mode (PerioSupport)</description>
3903 <description>Periodic OUT Channels is not supported in Host Mode</description>
3908 <description>Periodic OUT Channels Supported in Host Mode Supported</description>
3915 <description>Dynamic FIFO Sizing Enabled (DynFifoSizing)</description>
3922 <description>Dynamic FIFO Sizing Disabled</description>
3927 <description>Dynamic FIFO Sizing Enabled</description>
3934 <description>Multi Processor Interrupt Enabled (MultiProcIntrpt)</description>
3941 <description>No Multi Processor Interrupt Enabled</description>
3946 <description>Multi Processor Interrupt Enabled</description>
3953 <description>Non-periodic Request Queue Depth (NPTxQDepth)</description>
3960 <description>Queue size 2</description>
3965 <description>Queue size 4</description>
3970 <description>Queue size 8</description>
3977 <description>Host Mode Periodic Request Queue Depth (PTxQDepth)</description>
3984 <description>Queue Depth 2</description>
3989 <description>Queue Depth 4</description>
3994 <description>Queue Depth 8</description>
3999 <description>Queue Depth 16</description>
4006 … <description>Device Mode IN Token Sequence Learning Queue Depth (TknQDepth)</description>
4015 <description>User Hardware Configuration 3 Register</description>
4023 <description>Width of Transfer Size Counters (XferSizeWidth)</description>
4030 <description>Width of Transfer Size Counter 11 bits</description>
4035 <description>Width of Transfer Size Counter 12 bits</description>
4040 <description>Width of Transfer Size Counter 13 bits</description>
4045 <description>Width of Transfer Size Counter 14 bits</description>
4050 <description>Width of Transfer Size Counter 15 bits</description>
4055 <description>Width of Transfer Size Counter 16 bits</description>
4060 <description>Width of Transfer Size Counter 17 bits</description>
4065 <description>Width of Transfer Size Counter 18 bits</description>
4070 <description>Width of Transfer Size Counter 19 bits</description>
4077 <description>Width of Packet Size Counters (PktSizeWidth)</description>
4084 <description>Width of Packet Size Counter 4</description>
4089 <description>Width of Packet Size Counter 5</description>
4094 <description>Width of Packet Size Counter 6</description>
4099 <description>Width of Packet Size Counter 7</description>
4104 <description>Width of Packet Size Counter 8</description>
4109 <description>Width of Packet Size Counter 9</description>
4114 <description>Width of Packet Size Counter 10</description>
4121 <description>OTG Function Enabled (OtgEn)</description>
4128 <description>Not OTG Capable</description>
4133 <description>OTG Capable</description>
4140 <description>I2C Selection (I2CIntSel)</description>
4147 <description>I2C Interface is not available</description>
4152 <description>I2C Interface is available</description>
4159 <description>Vendor Control Interface Support (VndctlSupt)</description>
4166 <description>Vendor Control Interface is not available.</description>
4171 <description>Vendor Control Interface is available.</description>
4178 <description>Optional Features Removed (OptFeature)</description>
4185 <description>Optional features were not Removed</description>
4190 <description>Optional Features have been Removed</description>
4197 <description>Reset Style for Clocked always Blocks in RTL (RstType)</description>
4204 <description>Asynchronous reset is used in the core</description>
4209 <description>Synchronous reset is used in the core</description>
4216 …<description>This bit indicates whether ADP logic is present within or external to the controller<…
4223 <description>ADP logic is not present along with the controller</description>
4228 <description>ADP logic is present along with the controller</description>
4235 <description>HSIC mode specified for Mode of Operation</description>
4242 <description>No HSIC capability</description>
4247 <description>HSIC-capable with shared UTMI PHY interface</description>
4254 … <description>This bit indicates the controller support for Battery Charger.</description>
4261 <description>No Battery Charger Support</description>
4266 <description>Battery Charger Support present</description>
4273 <description>LPM mode specified for Mode of Operation.</description>
4280 <description>LPM disabled</description>
4285 <description>LPM enabled</description>
4292 <description>DFIFO Depth (DfifoDepth - EP_LOC_CNT)</description>
4301 <description>User Hardware Configuration 4 Register</description>
4309 … <description>Number of Device Mode Periodic IN Endpoints (NumDevPerioEps)</description>
4316 <description>Number of Periodic IN EPs is 0</description>
4321 <description>Number of Periodic IN EPs is 1</description>
4326 <description>Number of Periodic IN EPs is 2</description>
4331 <description>Number of Periodic IN EPs is 3</description>
4336 <description>Number of Periodic IN EPs is 4</description>
4341 <description>Number of Periodic IN EPs is 5</description>
4346 <description>Number of Periodic IN EPs is 6</description>
4351 <description>Number of Periodic IN EPs is 7</description>
4356 <description>Number of Periodic IN EPs is 8</description>
4361 <description>Number of Periodic IN EPs is 9</description>
4366 <description>Number of Periodic IN EPs is 10</description>
4371 <description>Number of Periodic IN EPs is 11</description>
4376 <description>Number of Periodic IN EPs is 12</description>
4381 <description>Number of Periodic IN EPs is 13</description>
4386 <description>Number of Periodic IN EPs is 14</description>
4391 <description>Number of Periodic IN EPs is 15</description>
4398 <description>Enable Partial Power Down (PartialPwrDn)</description>
4405 <description>Partial Power Down disabled</description>
4410 <description>Partial Power Down enabled</description>
4417 <description>Minimum AHB Frequency Less Than 60 MHz (AhbFreq)</description>
4424 <description>Minimum AHB Frequency More Than 60 MHz</description>
4429 <description>Minimum AHB Frequency Less Than 60 MHz</description>
4436 <description>Enable Hibernation (Hibernation)</description>
4443 <description>Hibernation feature disabled</description>
4448 <description>Hibernation feature enabled</description>
4455 <description>Enable Hibernation</description>
4462 <description>Extended Hibernation feature not enabled</description>
4467 <description>Extended Hibernation feature enabled</description>
4474 <description>Enhanced LPM Support1 (EnhancedLPMSupt1)</description>
4481 …<description>Reject L1 Request even if Non-Periodic (Bulk/Interrupt) TxFIFO is not empty.</descrip…
4486 …<description>Accept L1 Request even if Non-Periodic (Bulk/Interrupt) TxFIFO is not empty</descript…
4493 <description>Service Interval Flow</description>
4500 <description>Service Interval Flow not supported</description>
4505 <description>Service Interval Flow supported</description>
4512 <description>Interpacket Gap ISOC OUT Worst-case Support (ipgisocSupt)</description>
4519 <description>Interpacket Gap ISOC OUT Worst-case Support is Disabled</description>
4524 … <description>Interpacket Gap ISOC OUT Worst-case Support is Enabled (Default)</description>
4531 <description>Active Clock Gating Support</description>
4538 <description>Unspecified</description>
4543 <description>Active Clock Gating Support</description>
4550 <description>Enhanced LPM Support (EnhancedLPMSupt)</description>
4557 <description>Enhanced LPM Support is enabled</description>
4564 <description>UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width</description>
4571 <description>8 bits</description>
4576 <description>16 bits</description>
4581 <description>8/16 bits, software selectable</description>
4588 <description>Number of Device Mode Control Endpoints in Addition to</description>
4595 <description>End point 0</description>
4600 <description>End point 1</description>
4605 <description>End point 2</description>
4610 <description>End point 3</description>
4615 <description>End point 4</description>
4620 <description>End point 5</description>
4625 <description>End point 6</description>
4630 <description>End point 7</description>
4635 <description>End point 8</description>
4640 <description>End point 9</description>
4645 <description>End point 10</description>
4650 <description>End point 11</description>
4655 <description>End point 12</description>
4660 <description>End point 13</description>
4665 <description>End point 14</description>
4670 <description>End point 15</description>
4677 <description>IDDIG Filter Enable (IddgFltr)</description>
4684 <description>Iddig Filter Disabled</description>
4689 <description>Iddig Filter Enabled</description>
4696 <description>VBUS Valid Filter Enabled (VBusValidFltr)</description>
4703 <description>Vbus Valid Filter Disabled</description>
4708 <description>Vbus Valid Filter Enabled</description>
4715 <description>a_valid Filter Enabled (AValidFltr)</description>
4722 <description>No filter</description>
4727 <description>Filter</description>
4734 <description>b_valid Filter Enabled (BValidFltr)</description>
4741 <description>No Filter</description>
4746 <description>Filter</description>
4753 <description>session_end Filter Enabled (SessEndFltr)</description>
4760 <description>No filter</description>
4765 <description>Filter</description>
4772 <description>Enable Dedicated Transmit FIFO for device IN Endpoints</description>
4779 <description>Dedicated Transmit FIFO Operation not enabled</description>
4784 <description>Dedicated Transmit FIFO Operation enabled</description>
4791 … <description>Number of Device Mode IN Endpoints Including Control Endpoints (INEps)</description>
4798 <description>1 IN Endpoint</description>
4803 <description>2 IN Endpoints</description>
4808 <description>3 IN Endpoints</description>
4813 <description>4 IN Endpoints</description>
4818 <description>5 IN Endpoints</description>
4823 <description>6 IN Endpoints</description>
4828 <description>7 IN Endpoints</description>
4833 <description>8 IN Endpoints</description>
4838 <description>9 IN Endpoints</description>
4843 <description>10 IN Endpoints</description>
4848 <description>11 IN Endpoints</description>
4853 <description>12 IN Endpoints</description>
4858 <description>13 IN Endpoints</description>
4863 <description>14 IN Endpoints</description>
4868 <description>15 IN Endpoints</description>
4873 <description>16 IN Endpoints</description>
4880 <description>Scatter/Gather DMA configuration</description>
4887 <description>Non-Scatter/Gather DMA configuration</description>
4892 <description>Scatter/Gather DMA configuration</description>
4899 <description>Scatter/Gather DMA configuration</description>
4906 <description>Non Dynamic configuration</description>
4911 <description>Dynamic configuration</description>
4920 <description>LPM Config Register</description>
4928 <description>LPM-Capable (LPMCap)</description>
4934 <description>LPM capability is not enabled</description>
4939 <description>LPM capability is enabled</description>
4946 … <description>Mode: Device only. LPM response programmed by application (AppL1Res)</description>
4952 …<description>The core responds with a NYET when an error is detected in either of the LPM token pa…
4957 … <description>The core responds with an ACK only on a successful LPM transaction</description>
4964 <description>Host-Initiated Resume Duration (HIRD)</description>
4970 <description>RemoteWakeEnable (bRemoteWake)</description>
4976 <description>Remote Wakeup is disabled</description>
4981 … <description>In Host or device mode, this field takes the value of remote wake up</description>
4988 <description>Enable utmi_sleep_n (EnblSlpM)</description>
4994 …<description>utmi_sleep_n assertion from the core is not transferred to the external PHY</descript…
4999 …<description>utmi_sleep_n assertion from the core is transferred to the external PHY when utmi_l1_…
5006 <description>BESL/HIRD Threshold (HIRD_Thres)</description>
5012 <description>LPM Response (CoreL1Res)</description>
5019 <description>ERROR : No handshake response</description>
5024 <description>STALL response</description>
5029 <description>NYET response</description>
5034 <description>ACK response</description>
5041 <description>Port Sleep Status (SlpSts)</description>
5048 … <description>In Host or Device mode, this bit indicates core is not in L1</description>
5053 …description>In Host mode, this bit indicates the core transitions to Sleep state as a successful L…
5060 <description>Sleep State Resume OK (L1ResumeOK)</description>
5067 … <description>The application/core cannot start Resume from Sleep state</description>
5072 <description>The application/core can start Resume from Sleep state</description>
5079 <description>LPM Channel Index</description>
5085 <description>Channel 0</description>
5090 <description>Channel 1</description>
5095 <description>Channel 2</description>
5100 <description>Channel 3</description>
5105 <description>Channel 4</description>
5110 <description>Channel 5</description>
5115 <description>Channel 6</description>
5120 <description>Channel 7</description>
5125 <description>Channel 8</description>
5130 <description>Channel 9</description>
5135 <description>Channel 10</description>
5140 <description>Channel 11</description>
5145 <description>Channel 12</description>
5150 <description>Channel 13</description>
5155 <description>Channel 14</description>
5160 <description>Channel15</description>
5167 <description>LPM Retry Count (LPM_Retry_Cnt)</description>
5173 <description>Zero LPM retries</description>
5178 <description>One LPM retry</description>
5183 <description>Two LPM retries</description>
5188 <description>Three LPM retries</description>
5193 <description>Four LPM retries</description>
5198 <description>Five LPM retries</description>
5203 <description>Six LPM retries</description>
5208 <description>Seven LPM retries</description>
5215 <description>Send LPM Transaction (SndLPM)</description>
5221 …<description>In host-only mode: Received the response from the device for the LPM transaction</des…
5226 …<description>In host-only mode: Sending LPM transaction containing EXT and LPM tokens</description>
5233 <description>LPM Retry Count Status (LPM_RetryCnt_Sts)</description>
5240 <description>Zero LPM retries remaining</description>
5245 <description>One LPM retry remaining</description>
5250 <description>Two LPM retries remaining</description>
5255 <description>Three LPM retries remaining</description>
5260 <description>Four LPM retries remaining</description>
5265 <description>Five LPM retries remaining</description>
5270 <description>Six LPM retries remaining</description>
5275 <description>Seven LPM retries remaining</description>
5282 <description>LPM Enable BESL (LPM_EnBESL)</description>
5288 <description>BESL is disabled</description>
5293 <description>BESL is enabled as defined in LPM Errata</description>
5300 <description>LPM Restore Sleep Status (LPM_RestoreSlpSts)</description>
5306 …<description>Puts the core in Shallow Sleep mode based on the BESL value from the Host</descriptio…
5311 … <description>Puts the core in Deep Sleep mode based on the BESL value from the Host</description>
5320 <description>Global Power Down Register</description>
5328 <description>PMU Interrupt Select (PMUIntSel)</description>
5334 <description>Internal DWC_otg_core interrupt is selected</description>
5339 <description>External DWC_otg_pmu interrupt is selected</description>
5346 <description>PMU Active (PMUActv)</description>
5352 <description>Disable PMU module</description>
5357 <description>Enable PMU module</description>
5364 <description>Restore</description>
5370 <description>The controller in normal mode of operation</description>
5375 <description>The controller in Restore mode</description>
5382 <description>Power Down Clamp (PwrDnClmp)</description>
5388 <description>Disable PMU power clamp</description>
5393 <description>Enable PMU power clamp</description>
5400 <description>Power Down ResetN (PwrDnRst_n)</description>
5406 <description>Reset the controller</description>
5411 <description>The controller is in normal operation</description>
5418 <description>Power Down Switch (PwrDnSwtch)</description>
5424 <description>The controller is in ON state</description>
5429 <description>The controller is in OFF state</description>
5436 <description>DisableVBUS</description>
5442 …<description>Host mode:HPRT0.PrtPwr was not programmed to 0, and in Device mode:Session Valid</des…
5447 …<description>Host mode:HPRT0.PrtPwr was programmed to 0 and in Device mode:Session End</descriptio…
5454 <description>Line State Change (LnStsChng)</description>
5460 <description>No LineState change on USB</description>
5465 <description>LineState change on USB</description>
5472 <description>LineStageChangeMsk</description>
5478 <description>No LineStateChange Interrupt Mask</description>
5483 <description>Mask for LineStateChange Interrupt</description>
5490 <description>ResetDetected</description>
5496 <description>Reset not detected</description>
5501 <description>Reset detected</description>
5508 <description>ResetDetMsk</description>
5514 <description>No ResetDetect Interrupt Mask</description>
5519 <description>Mask for ResetDetect Interrupt</description>
5526 <description>DisconnectDetect</description>
5532 <description>Disconnect not detected</description>
5537 <description>Disconnect detected</description>
5544 <description>DisconnectDetectMsk</description>
5550 <description>No DisconnectDetect Interrupt Mask</description>
5555 <description>Mask for DisconnectDetect Interrupt</description>
5562 <description>ConnectDet</description>
5568 <description>Connect not detected</description>
5573 <description>Connect detected</description>
5580 <description>ConnDetMsk</description>
5586 <description>No ConnectDet Interrupt Mask</description>
5591 <description>Mask for ConnectDet Interrupt</description>
5598 <description>SRPDetect</description>
5604 <description>SRP not detected</description>
5609 <description>SRP detected</description>
5616 <description>SRPDetectMsk</description>
5622 <description>No SRPDetect Interrupt Mask</description>
5627 <description>Mask for SRPDetect Interrupt</description>
5634 <description>Status Change Interrupt (StsChngInt)</description>
5640 <description>No Status change</description>
5645 <description>Status change detected</description>
5652 <description>StsChngIntMsk</description>
5658 <description>No Status Change Interrupt Mask</description>
5663 <description>Mask for Status Change Interrupt</description>
5670 <description>LineState</description>
5677 <description>Linestate on USB: DM = 0, DP = 0</description>
5682 <description>Linestate on USB: DM = 0, DP = 1</description>
5687 <description>Linestate on USB: DM = 1, DP = 0</description>
5692 <description>Linestate on USB: Not-defined</description>
5699 …description>This bit indicates the status of the signal IDDIG. The application must read this bit …
5706 <description>Host Mode</description>
5711 <description>Device Mode</description>
5718 <description>B Session Valid (BSessVld)</description>
5725 <description>B_Valid is 0</description>
5730 <description>B_Valid is 1</description>
5737 <description>MultValIdBC</description>
5744 <description>OTG device as B-device</description>
5749 <description>OTG device as B-device, can connect</description>
5754 <description>OTG device as B-device, cannot connect</description>
5759 <description>OTG device as A-device</description>
5764 <description>ID_OTG pin is grounded</description>
5769 <description>OTG device as A-device, RID_A=1 and RID_GND=1</description>
5774 <description>ID pull down when ID_OTG is floating</description>
5779 … <description>OTG device as B-device, can connect, RID_C=1 and RID_FLOAT=1</description>
5784 … <description>OTG device as B-device, cannot connect, RID_B=1 and RID_FLOAT=1</description>
5789 <description>OTG device as A-device</description>
5798 <description>Global DFIFO Configuration Register</description>
5806 <description>GDFIFOCfg</description>
5812 … <description>This field provides the start address of the EP info controller.</description>
5820 <description>Interrupt Mask Register 2</description>
5835 <description>Interrupt Register 2</description>
5850 <description>Host Periodic Transmit FIFO Size Register</description>
5858 <description>Host Periodic TxFIFO Start Address (PTxFStAddr)</description>
5864 <description>Host Periodic TxFIFO Depth (PTxFSize)</description>
5874 … <description>Description collection: Device IN Endpoint Transmit FIFO Size Register</description>
5882 … <description>IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr)</description>
5888 <description>IN Endpoint TxFIFO Depth (INEPnTxFDep)</description>
5896 <description>Host Configuration Register</description>
5904 <description>FS/LS PHY Clock Select (FSLSPclkSel)</description>
5910 <description>PHY clock is running at 30/60 MHz</description>
5915 <description>PHY clock is running at 48 MHz</description>
5920 <description>PHY clock is running at 6 MHz</description>
5927 <description>FS- and LS-Only Support (FSLSSupp)</description>
5933 … <description>HS/FS/LS, based on the maximum speed supported by the connected device</description>
5938 <description>FS/LS-only, even if the connected device can support HS</description>
5945 <description>Enable 32 KHz Suspend mode (Ena32KHzS)</description>
5951 <description>32 KHz Suspend mode disabled</description>
5956 <description>32 KHz Suspend mode enabled</description>
5963 <description>Resume Validation Period (ResValid)</description>
5969 <description>Mode Change Ready Timer Enable (ModeChTimEn)</description>
5975 …description>The Host core waits for either 200 PHY clock cycles or a linestate of SE0 at the end o…
5980 …<description>The Host core waits only for a linestate of SE0 at the end of resume to change the op…
5989 <description>Host Frame Interval Register</description>
5997 <description>Frame Interval (FrInt)</description>
6003 <description>Reload Control (HFIRRldCtrl)</description>
6009 <description>The HFIR cannot be reloaded dynamically</description>
6014 <description>The HFIR can be dynamically reloaded during runtime</description>
6023 <description>Host Frame Number/Frame Time Remaining Register</description>
6031 <description>Frame Number (FrNum)</description>
6038 <description>No SOF is transmitted</description>
6043 <description>SOF is transmitted</description>
6050 <description>Frame Time Remaining (FrRem)</description>
6059 <description>Host All Channels Interrupt Register</description>
6073 <description>Not active</description>
6078 <description>Host Channel Interrupt</description>
6087 <description>Host All Channels Interrupt Mask Register</description>
6095 <description>Channel Interrupt Mask (HAINTMsk)</description>
6101 <description>Unmask Channel interrupt</description>
6106 <description>Mask Channel interrupt</description>
6115 <description>Host Port Control and Status Register</description>
6123 <description>Port Connect Status (PrtConnSts)</description>
6130 <description>No device is attached to the port</description>
6135 <description>A device is attached to the port</description>
6142 <description>Port Connect Detected (PrtConnDet)</description>
6148 <description>No device connection detected</description>
6153 <description>Device connection detected</description>
6160 <description>Port Enable (PrtEna)</description>
6166 <description>Port disabled</description>
6171 <description>Port enabled</description>
6178 <description>Port Enable/Disable Change (PrtEnChng)</description>
6184 <description>Port Enable bit 2 has not changed</description>
6189 <description>Port Enable bit 2 changed</description>
6196 <description>Port Overcurrent Active (PrtOvrCurrAct)</description>
6203 <description>No overcurrent condition</description>
6208 <description>Overcurrent condition</description>
6215 <description>Port Overcurrent Change (PrtOvrCurrChng)</description>
6221 <description>Status of port overcurrent status is not changed</description>
6226 <description>Status of port overcurrent changed</description>
6233 <description>Port Resume (PrtRes)</description>
6239 <description>No resume driven</description>
6244 <description>Resume driven</description>
6251 <description>Port Suspend (PrtSusp)</description>
6257 <description>Port not in Suspend mode</description>
6262 <description>Port in Suspend mode</description>
6269 <description>Port Reset (PrtRst)</description>
6275 <description>Port not in reset</description>
6280 <description>Port in reset</description>
6287 <description>Port Line Status (PrtLnSts)</description>
6294 <description>Logic level of D+</description>
6299 <description>Logic level of D-</description>
6306 <description>Port Power (PrtPwr)</description>
6312 <description>Power off</description>
6317 <description>Power on</description>
6324 <description>Port Test Control (PrtTstCtl)</description>
6330 <description>Test mode disabled</description>
6335 <description>Test_J mode</description>
6340 <description>Test_K mode</description>
6345 <description>Test_SE0_NAK mode</description>
6350 <description>Test_Packet mode</description>
6355 <description>Test_force_Enable</description>
6362 <description>Port Speed (PrtSpd)</description>
6369 <description>High speed</description>
6374 <description>Full speed</description>
6379 <description>Low speed</description>
6390 <description>Unspecified</description>
6396 <description>Description cluster: Host Channel Characteristics Register</description>
6404 <description>Maximum Packet Size (MPS)</description>
6410 <description>Endpoint Number (EPNum)</description>
6416 <description>End point 0</description>
6421 <description>End point 1</description>
6426 <description>End point 2</description>
6431 <description>End point 3</description>
6436 <description>End point 4</description>
6441 <description>End point 5</description>
6446 <description>End point 6</description>
6451 <description>End point 7</description>
6456 <description>End point 8</description>
6461 <description>End point 9</description>
6466 <description>End point 10</description>
6471 <description>End point 11</description>
6476 <description>End point 12</description>
6481 <description>End point 13</description>
6486 <description>End point 14</description>
6491 <description>End point 15</description>
6498 <description>Endpoint Direction (EPDir)</description>
6504 <description>OUT Direction</description>
6509 <description>IN Direction</description>
6516 <description>Low-Speed Device (LSpdDev)</description>
6522 <description>Not Communicating with low speed device</description>
6527 <description>Communicating with low speed device</description>
6534 <description>Endpoint Type (EPType)</description>
6540 <description>Control</description>
6545 <description>Isochronous</description>
6550 <description>Bulk</description>
6555 <description>Interrupt</description>
6562 <description>Multi Count (MC) / Error Count (EC)</description>
6568 <description>1 transaction</description>
6573 … <description>2 transactions to be issued for this endpoint per microframe</description>
6578 … <description>3 transactions to be issued for this endpoint per microframe</description>
6585 <description>Device Address (DevAddr)</description>
6591 <description>Odd Frame (OddFrm)</description>
6597 <description>Even Frame Transfer</description>
6602 <description>Odd Frame Transfer</description>
6609 <description>Channel Disable (ChDis)</description>
6615 <description>Transmit/Recieve normal</description>
6620 <description>Stop transmitting/receiving data on channel</description>
6627 <description>Channel Enable (ChEna)</description>
6633 …description>If Scatter/Gather mode is enabled, indicates that the descriptor structure is not yet …
6638 …description>If Scatter/Gather mode is enabled, indicates that the descriptor structure and data bu…
6647 <description>Description cluster: Host Channel Interrupt Register</description>
6655 <description>Transfer Completed (XferCompl)</description>
6661 <description>Transfer in progress or No Active Transfer</description>
6666 <description>Transfer completed normally without any errors</description>
6673 <description>Channel Halted (ChHltd)</description>
6679 <description>Channel not halted</description>
6684 <description>Channel Halted</description>
6691 <description>AHB Error (AHBErr)</description>
6697 <description>No AHB error</description>
6702 <description>AHB error during AHB read/write</description>
6709 <description>STALL Response Received Interrupt (STALL)</description>
6715 <description>No Stall Response Received Interrupt</description>
6720 <description>Stall Response Received Interrupt</description>
6727 <description>NAK Response Received Interrupt (NAK)</description>
6733 <description>No NAK Response Received Interrupt</description>
6738 <description>NAK Response Received Interrupt</description>
6745 <description>ACK Response Received/Transmitted Interrupt (ACK)</description>
6751 <description>No ACK Response Received or Transmitted Interrupt</description>
6756 <description>ACK Response Received or Transmitted Interrup</description>
6763 <description>NYET Response Received Interrupt (NYET)</description>
6769 <description>No NYET Response Received Interrupt</description>
6774 <description>NYET Response Received Interrupt</description>
6781 <description>Transaction Error (XactErr)</description>
6787 <description>No Transaction Error</description>
6792 <description>Transaction Error</description>
6799 <description>Babble Error (BblErr)</description>
6805 <description>No Babble Error</description>
6810 <description>Babble Error</description>
6817 <description>Frame Overrun (FrmOvrun).</description>
6823 <description>No Frame Overrun</description>
6828 <description>Frame Overrun</description>
6840 <description>No Data Toggle Error</description>
6845 <description>Data Toggle Error</description>
6854 <description>Description cluster: Host Channel Interrupt Mask Register</description>
6867 <description>Transfer Completed Mask</description>
6872 <description>No Transfer Completed Mask</description>
6884 <description>Channel Halted Mask</description>
6889 <description>No Channel Halted Mask</description>
6901 <description>AHB Error Mask</description>
6906 <description>No AHB Error Mask</description>
6918 <description>Mask STALL Response Received Interrupt</description>
6923 <description>No STALL Response Received Interrupt Mask</description>
6935 <description>Mask NAK Response Received Interrupt</description>
6940 <description>No NAK Response Received Interrupt Mask</description>
6952 <description>Mask ACK Response Received/Transmitted Interrupt</description>
6957 <description>No ACK Response Received/Transmitted Interrupt Mask</description>
6969 <description>Mask NYET Response Received Interrupt</description>
6974 <description>No NYET Response Received Interrupt Mask</description>
6986 <description>Mask Transaction Error</description>
6991 <description>No Transaction Error Mask</description>
7003 <description>Mask Babble Error</description>
7008 <description>No Babble Error Mask</description>
7020 <description>Mask Overrun Mask</description>
7025 <description>No Frame Overrun Mask</description>
7037 <description>Mask Data Toggle Error</description>
7042 <description>No Data Toggle Error Mask</description>
7051 <description>Description cluster: Host Channel Transfer Size Register</description>
7059 <description>Non-Scatter/Gather DMA Mode:</description>
7065 <description>Non-Scatter/Gather DMA Mode:</description>
7071 <description>PID (Pid)</description>
7077 <description>DATA0</description>
7082 <description>DATA2</description>
7087 <description>DATA1</description>
7092 <description>MDATA (non-control)/SETUP (control)</description>
7099 <description>Do Ping (DoPng)</description>
7105 <description>No ping protocol</description>
7110 <description>Ping protocol</description>
7119 <description>Description cluster: Host Channel DMA Address Register</description>
7127 <description>In Buffer DMA Mode:</description>
7136 <description>Device Configuration Register</description>
7144 <description>Device Speed (DevSpd)</description>
7150 <description>High speed USB 2.0 PHY clock is 30 MHz or 60 MHz</description>
7155 <description>Full speed USB 2.0 PHY clock is 30 MHz or 60 MHz</description>
7160 <description>Low speed USB 1.1 transceiver clock is 6 MHz</description>
7165 <description>Full speed USB 1.1 transceiver clock is 48 MHz</description>
7172 <description>Non-Zero-Length Status OUT Handshake (NZStsOUTHShk)</description>
7178 …description>Send the received OUT packet to the application (zero-length or non-zero length) and s…
7183 …<description>Send a STALL handshake on a nonzero-length status OUT transaction and do not send the…
7190 <description>Enable 32 KHz Suspend mode (Ena32KHzSusp)</description>
7196 <description>USB 1.1 Full-Speed Serial Transceiver not selected</description>
7201 … <description>USB 1.1 Full-Speed Serial Transceiver Interface selected</description>
7208 <description>Device Address (DevAddr)</description>
7214 <description>Periodic Frame Interval (PerFrInt)</description>
7220 <description>80 percent of the (micro)Frame interval</description>
7225 <description>85 percent of the (micro)Frame interval</description>
7230 <description>90 percent of the (micro)Frame interval</description>
7235 <description>95 percent of the (micro)Frame interval</description>
7242 <description>XCVRDLY</description>
7248 … <description>No delay between xcvr_sel and txvalid during Device chirp</description>
7253 … <description>Enable delay between xcvr_sel and txvalid during Device chirp</description>
7260 <description>Erratic Error Interrupt Mask</description>
7266 <description>Early suspend interrupt is generated on erratic error</description>
7271 <description>Mask early suspend interrupt on erratic error</description>
7278 <description>Worst-Case Inter-Packet Gap ISOC OUT Support (ipgisocSupt)</description>
7284 … <description>Worst-Case Inter-Packet Gap ISOC OUT Support is disabled</description>
7289 <description>Worst-Case Inter-Packet Gap ISOC OUT Support is enabled</description>
7296 <description>Periodic Scheduling Interval (PerSchIntvl)</description>
7302 <description>25 percent of (micro)Frame</description>
7307 <description>50 percent of (micro)Frame</description>
7312 <description>75 percent of (micro)Frame</description>
7319 <description>Resume Validation Period (ResValid)</description>
7327 <description>Device Control Register</description>
7335 <description>Remote Wakeup Signaling (RmtWkUpSig)</description>
7341 <description>Core does not send Remote Wakeup Signaling</description>
7346 <description>Core sends Remote Wakeup Signaling</description>
7353 <description>Soft Disconnect (SftDiscon)</description>
7359 …<description>The core drives the phy_opmode_o signal on the UTMI+ to 2'b00, which generates a devi…
7364 …<description>The core drives the phy_opmode_o signal on the UTMI+ to 2'b01, which generates a devi…
7371 <description>Global Non-periodic IN NAK Status (GNPINNakSts)</description>
7378 …<description>A handshake is sent out based on the data availability in the transmit FIFO</descript…
7383 …<description>A NAK handshake is sent out on all non-periodic IN endpoints, irrespective of the dat…
7390 <description>Global OUT NAK Status (GOUTNakSts)</description>
7397 …<description>A handshake is sent based on the FIFO Status and the NAK and STALL bit settings.</des…
7402 …description>No data is written to the RxFIFO, irrespective of space availability. Sends a NAK hand…
7409 <description>Test Control (TstCtl)</description>
7415 <description>Test mode disabled</description>
7420 <description>Test_J mode</description>
7425 <description>Test_K mode</description>
7430 <description>Test_SE0_NAK mode</description>
7435 <description>Test_Packet mode</description>
7440 <description>Test_force_Enable</description>
7447 <description>Set Global Non-periodic IN NAK (SGNPInNak)</description>
7454 <description>Disable Global Non-periodic IN NAK</description>
7459 <description>Set Global Non-periodic IN NAK</description>
7466 <description>Clear Global Non-periodic IN NAK (CGNPInNak)</description>
7473 <description>Disable Global Non-periodic IN NAK</description>
7478 <description>Clear Global Non-periodic IN NAK</description>
7485 <description>Set Global OUT NAK (SGOUTNak)</description>
7492 <description>Disable Global OUT NAK</description>
7497 <description>Set Global OUT NAK</description>
7504 <description>Clear Global OUT NAK (CGOUTNak)</description>
7511 <description>Disable Clear Global OUT NAK</description>
7516 <description>Clear Global OUT NAK</description>
7523 <description>Power-On Programming Done (PWROnPrgDone)</description>
7529 <description>Power-On Programming not done</description>
7534 <description>Power-On Programming Done</description>
7541 … <description>Ignore Frame Number Feature for Isochronous Endpoints (IgnrFrmNum)</description>
7547 …description>Scatter/Gather DMA Mode: The core transmits the packets only in the frame number in wh…
7552 …description>Scatter/Gather DMA Mode: The core ignores the frame number, sending packets immediatel…
7559 <description>NAK on Babble Error (NakOnBble)</description>
7565 <description>Disable NAK on Babble Error</description>
7570 <description>NAK on Babble Error</description>
7577 <description>DeepSleepBESLReject</description>
7583 <description>Deep Sleep BESL Reject feature is disabled</description>
7588 <description>Deep Sleep BESL Reject feature is enabled</description>
7595 … <description>Service Interval based scheduling for Isochronous IN Endpoints</description>
7601 … <description>The controller behavior depends on DCTL.IgnrFrmNum field.</description>
7606 …<description>Scatter/Gather DMA Mode: The controller can transmit the packets in any frame of the …
7613 … <description>Disable the correction to OpMode/XcvrSel/TermSel on UTMI Interface.</description>
7619 …<description>Opmode, XcvrSel, TermSel are changed by the Device Controller after TxValid goes LOW …
7624 …<description>Opmode, XcvrSel, TermSel are changed by the Device Controller immediately on soft dis…
7631 <description>Disable the correction of TermSel on UTMI Interface.</description>
7637 …<description>Valid Combination of XcvrSel and TermSel is driven by the Device Controller.</descrip…
7642 …<description>Invalid Combination of XcvrSel and TermSel is driven by the Device Controller.</descr…
7651 <description>Device Status Register</description>
7659 <description>Suspend Status (SuspSts)</description>
7666 <description>No suspend state</description>
7671 <description>Suspend state</description>
7678 <description>Enumerated Speed (EnumSpd)</description>
7685 <description>High speed (PHY clock is running at 30 or 60 MHz)</description>
7690 <description>Full speed (PHY clock is running at 30 or 60 MHz)</description>
7695 <description>Low speed (PHY clock is running at 6 MHz)</description>
7700 <description>Full speed (PHY clock is running at 48 MHz)</description>
7707 <description>Erratic Error (ErrticErr)</description>
7714 <description>No Erratic Error</description>
7719 <description>Erratic Error</description>
7726 <description>Frame or Microframe Number of the Received SOF (SOFFN)</description>
7733 <description>Device Line Status (DevLnSts)</description>
7742 <description>Device IN Endpoint Common Interrupt Mask Register</description>
7750 <description>Transfer Completed Interrupt Mask (XferComplMsk)</description>
7756 <description>Mask Transfer Completed Interrupt</description>
7761 <description>No Transfer Completed Interrupt Mask</description>
7768 <description>Endpoint Disabled Interrupt Mask (EPDisbldMsk)</description>
7774 <description>Mask Endpoint Disabled Interrupt</description>
7779 <description>No Endpoint Disabled Interrupt Mask</description>
7786 <description>AHB Error Mask (AHBErrMsk)</description>
7792 <description>Mask AHB Error Interrupt</description>
7797 <description>No AHB Error Interrupt Mask</description>
7804 … <description>Timeout Condition Mask (TimeOUTMsk) (Non-isochronous endpoints)</description>
7810 <description>Mask Timeout Condition Interrupt</description>
7815 <description>No Timeout Condition Interrupt Mask</description>
7822 <description>IN Token Received When TxFIFO Empty Mask (INTknTXFEmpMsk)</description>
7828 <description>Mask IN Token Received When TxFIFO Empty Interrupt</description>
7833 <description>No IN Token Received When TxFIFO Empty Interrupt</description>
7840 <description>IN Token received with EP Mismatch Mask (INTknEPMisMsk)</description>
7846 <description>Mask IN Token received with EP Mismatch Interrupt</description>
7851 <description>No Mask IN Token received with EP Mismatch Interrupt</description>
7858 <description>IN Endpoint NAK Effective Mask (INEPNakEffMsk)</description>
7864 <description>Mask IN Endpoint NAK Effective Interrupt</description>
7869 <description>No IN Endpoint NAK Effective Interrupt Mask</description>
7876 <description>Fifo Underrun Mask (TxfifoUndrnMsk)</description>
7882 <description>Mask Fifo Underrun Interrupt</description>
7887 <description>No Fifo Underrun Interrupt Mask</description>
7894 <description>NAK interrupt Mask (NAKMsk)</description>
7900 <description>Mask NAK Interrupt</description>
7905 <description>No Mask NAK Interrupt</description>
7914 <description>Device OUT Endpoint Common Interrupt Mask Register</description>
7922 <description>Transfer Completed Interrupt Mask (XferComplMsk)</description>
7928 <description>Mask Transfer Completed Interrupt</description>
7933 <description>No Transfer Completed Interrupt Mask</description>
7940 <description>Endpoint Disabled Interrupt Mask (EPDisbldMsk)</description>
7946 <description>Mask Endpoint Disabled Interrupt</description>
7951 <description>No Endpoint Disabled Interrupt Mask</description>
7958 <description>AHB Error (AHBErrMsk)</description>
7964 <description>Mask AHB Error Interrupt</description>
7969 <description>No AHB Error Interrupt Mask</description>
7976 <description>SETUP Phase Done Mask (SetUPMsk)</description>
7982 <description>Mask SETUP Phase Done Interrupt</description>
7987 <description>No SETUP Phase Done Interrupt Mask</description>
7994 … <description>OUT Token Received when Endpoint Disabled Mask (OUTTknEPdisMsk)</description>
8000 … <description>Mask OUT Token Received when Endpoint Disabled Interrupt</description>
8005 … <description>No OUT Token Received when Endpoint Disabled Interrupt Mask</description>
8012 <description>Status Phase Received Mask (StsPhseRcvdMsk)</description>
8018 <description>Status Phase Received Mask</description>
8023 <description>No Status Phase Received Mask</description>
8030 <description>Back-to-Back SETUP Packets Received Mask (Back2BackSETup)</description>
8036 <description>Mask Back-to-Back SETUP Packets Received Interrupt</description>
8041 <description>No Back-to-Back SETUP Packets Received Interrupt Mask</description>
8048 <description>OUT Packet Error Mask (OutPktErrMsk)</description>
8054 <description>Mask OUT Packet Error Interrupt</description>
8059 <description>No OUT Packet Error Interrupt Mask</description>
8066 <description>Babble Error interrupt Mask (BbleErrMsk)</description>
8072 <description>Mask Babble Error Interrupt</description>
8077 <description>No Babble Error Interrupt Mask</description>
8084 <description>NAK interrupt Mask (NAKMsk)</description>
8090 <description>Mask NAK Interrupt</description>
8095 <description>No NAK Interrupt Mask</description>
8102 <description>NYET interrupt Mask (NYETMsk)</description>
8108 <description>Mask NYET Interrupt</description>
8113 <description>No NYET Interrupt Mask</description>
8122 <description>Device All Endpoints Interrupt Register</description>
8130 <description>IN Endpoint 0 Interrupt Bit</description>
8137 <description>No Interrupt</description>
8142 <description>Interrupt is active for IN EP0</description>
8149 <description>IN Endpoint 1 Interrupt Bit</description>
8156 <description>No Interrupt</description>
8161 <description>Interrupt is active for the IN EP</description>
8168 <description>IN Endpoint 2 Interrupt Bit</description>
8175 <description>No Interrupt</description>
8180 <description>Interrupt is active for the IN EP</description>
8187 <description>IN Endpoint 3 Interrupt Bit</description>
8194 <description>No Interrupt</description>
8199 <description>Interrupt is active for the IN EP</description>
8206 <description>IN Endpoint 4 Interrupt Bit</description>
8213 <description>No Interrupt</description>
8218 <description>Interrupt is active for the IN EP</description>
8225 <description>IN Endpoint 5 Interrupt Bit</description>
8232 <description>No Interrupt</description>
8237 <description>Interrupt is active for the IN EP</description>
8244 <description>IN Endpoint 6 Interrupt Bit</description>
8251 <description>No Interrupt</description>
8256 <description>Interrupt is active for the IN EP</description>
8263 <description>IN Endpoint 7 Interrupt Bit</description>
8270 <description>No Interrupt</description>
8275 <description>Interrupt is active for the IN EP</description>
8282 <description>IN Endpoint 8 Interrupt Bit</description>
8289 <description>No Interrupt</description>
8294 <description>Interrupt is active for the IN EP</description>
8301 <description>IN Endpoint 9 Interrupt Bit</description>
8308 <description>No Interrupt</description>
8313 <description>Interrupt is active for the IN EP</description>
8320 <description>IN Endpoint 10 Interrupt Bit</description>
8327 <description>No Interrupt</description>
8332 <description>Interrupt is active for the IN EP</description>
8339 <description>IN Endpoint 11 Interrupt Bit</description>
8346 <description>No Interrupt</description>
8351 <description>Interrupt is active for the IN EP</description>
8358 <description>OUT Endpoint 0 Interrupt Bit</description>
8365 <description>No Interrupt</description>
8370 <description>Interrupt is active for OUT EP0</description>
8377 <description>OUT Endpoint 1 Interrupt Bit</description>
8384 <description>No Interrupt</description>
8389 <description>Interrupt is active for the OUT EP</description>
8396 <description>OUT Endpoint 2 Interrupt Bit</description>
8403 <description>No Interrupt</description>
8408 <description>Interrupt is active for the OUT EP</description>
8415 <description>OUT Endpoint 3 Interrupt Bit</description>
8422 <description>No Interrupt</description>
8427 <description>Interrupt is active for the OUT EP</description>
8434 <description>OUT Endpoint 4 Interrupt Bit</description>
8441 <description>No Interrupt</description>
8446 <description>Interrupt is active for the OUT EP</description>
8453 <description>OUT Endpoint 5 Interrupt Bit</description>
8460 <description>No Interrupt</description>
8465 <description>Interrupt is active for the OUT EP</description>
8472 <description>OUT Endpoint 12 Interrupt Bit</description>
8479 <description>No Interrupt</description>
8484 <description>Interrupt is active for the OUT EP</description>
8491 <description>OUT Endpoint 13 Interrupt Bit</description>
8498 <description>No Interrupt</description>
8503 <description>Interrupt is active for the OUT EP</description>
8510 <description>OUT Endpoint 14 Interrupt Bit</description>
8517 <description>No Interrupt</description>
8522 <description>Interrupt is active for the OUT EP</description>
8529 <description>OUT Endpoint 15 Interrupt Bit</description>
8536 <description>No Interrupt</description>
8541 <description>Interrupt is active for the OUT EP</description>
8550 <description>Device All Endpoints Interrupt Mask Register</description>
8558 <description>IN Endpoint 0 Interrupt mask Bit</description>
8564 <description>Mask IN Endpoint 0 Interrupt</description>
8569 <description>No Interrupt mask</description>
8576 <description>IN Endpoint 1 Interrupt mask Bit</description>
8582 <description>Mask IN Endpoint Interrupt</description>
8587 <description>No Interrupt mask</description>
8594 <description>IN Endpoint 2 Interrupt mask Bit</description>
8600 <description>Mask IN Endpoint Interrupt</description>
8605 <description>No Interrupt mask</description>
8612 <description>IN Endpoint 3 Interrupt mask Bit</description>
8618 <description>Mask IN Endpoint Interrupt</description>
8623 <description>No Interrupt mask</description>
8630 <description>IN Endpoint 4 Interrupt mask Bit</description>
8636 <description>Mask IN Endpoint Interrupt</description>
8641 <description>No Interrupt mask</description>
8648 <description>IN Endpoint 5 Interrupt mask Bit</description>
8654 <description>Mask IN Endpoint Interrupt</description>
8659 <description>No Interrupt mask</description>
8666 <description>IN Endpoint 6 Interrupt mask Bit</description>
8672 <description>Mask IN Endpoint Interrupt</description>
8677 <description>No Interrupt mask</description>
8684 <description>IN Endpoint 7 Interrupt mask Bit</description>
8690 <description>Mask IN Endpoint Interrupt</description>
8695 <description>No Interrupt mask</description>
8702 <description>IN Endpoint 8 Interrupt mask Bit</description>
8708 <description>Mask IN Endpoint Interrupt</description>
8713 <description>No Interrupt mask</description>
8720 <description>IN Endpoint 9 Interrupt mask Bit</description>
8726 <description>Mask IN Endpoint Interrupt</description>
8731 <description>No Interrupt mask</description>
8738 <description>IN Endpoint 10 Interrupt mask Bit</description>
8744 <description>Mask IN Endpoint Interrupt</description>
8749 <description>No Interrupt mask</description>
8756 <description>IN Endpoint 11 Interrupt mask Bit</description>
8762 <description>Mask IN Endpoint Interrupt</description>
8767 <description>No Interrupt mask</description>
8774 <description>OUT Endpoint 0 Interrupt mask Bit</description>
8780 <description>Mask OUT Endpoint 0 Interrupt</description>
8785 <description>No Interrupt mask</description>
8792 <description>OUT Endpoint 1 Interrupt mask Bit</description>
8798 <description>Mask OUT Endpoint Interrupt</description>
8803 <description>No Interrupt mask</description>
8810 <description>OUT Endpoint 2 Interrupt mask Bit</description>
8816 <description>Mask OUT Endpoint Interrupt</description>
8821 <description>No Interrupt mask</description>
8828 <description>OUT Endpoint 3 Interrupt mask Bit</description>
8834 <description>Mask OUT Endpoint Interrupt</description>
8839 <description>No Interrupt mask</description>
8846 <description>OUT Endpoint 4 Interrupt mask Bit</description>
8852 <description>Mask OUT Endpoint Interrupt</description>
8857 <description>No Interrupt mask</description>
8864 <description>OUT Endpoint 5 Interrupt mask Bit</description>
8870 <description>Mask OUT Endpoint Interrupt</description>
8875 <description>No Interrupt mask</description>
8882 <description>OUT Endpoint 12 Interrupt mask Bit</description>
8888 <description>Mask OUT Endpoint Interrupt</description>
8893 <description>No Interrupt mask</description>
8900 <description>OUT Endpoint 13 Interrupt mask Bit</description>
8906 <description>Mask OUT Endpoint Interrupt</description>
8911 <description>No Interrupt mask</description>
8918 <description>OUT Endpoint 14 Interrupt mask Bit</description>
8924 <description>Mask OUT Endpoint Interrupt</description>
8929 <description>No Interrupt mask</description>
8936 <description>OUT Endpoint 15 Interrupt mask Bit</description>
8942 <description>Mask OUT Endpoint Interrupt</description>
8947 <description>No Interrupt mask</description>
8956 <description>Device VBUS Discharge Time Register</description>
8964 <description>Device VBUS Discharge Time (DVBUSDis)</description>
8972 <description>Device VBUS Pulsing Time Register</description>
8980 <description>Device VBUS Pulsing Time (DVBUSPulse)</description>
8988 <description>Device Threshold Control Register</description>
8996 <description>Non-ISO IN Endpoints Threshold Enable. (NonISOThrEn)</description>
9002 <description>No thresholding</description>
9007 <description>Enable thresholding for non-isochronous IN endpoints</description>
9019 <description>No thresholding</description>
9024 <description>Enables thresholding for isochronous IN endpoints</description>
9031 <description>Transmit Threshold Length (TxThrLen)</description>
9037 <description>AHB Threshold Ratio (AHBThrRatio)</description>
9043 <description>AHB threshold = MAC threshold</description>
9048 <description>AHB threshold = MAC threshold /2</description>
9053 <description>AHB threshold = MAC threshold /4</description>
9058 <description>AHB threshold = MAC threshold /8</description>
9065 <description>Receive Threshold Enable (RxThrEn)</description>
9071 <description>Disable thresholding</description>
9076 <description>Enable thresholding in the receive direction</description>
9083 <description>Receive Threshold Length (RxThrLen)</description>
9089 <description>Arbiter Parking Enable (ArbPrkEn)</description>
9095 <description>Disable DMA arbiter parking</description>
9100 <description>Enable DMA arbiter parking for IN endpoints</description>
9109 <description>Device IN Endpoint FIFO Empty Interrupt Mask Register</description>
9117 <description>IN EP Tx FIFO Empty Interrupt Mask Bits (InEpTxfEmpMsk)</description>
9123 <description>Mask IN EP0 Tx FIFO Empty Interrupt</description>
9128 <description>Mask IN EP1 Tx FIFO Empty Interrupt</description>
9133 <description>Mask IN EP2 Tx FIFO Empty Interrupt</description>
9138 <description>Mask IN EP3 Tx FIFO Empty Interrupt</description>
9143 <description>Mask IN EP4 Tx FIFO Empty Interrupt</description>
9148 <description>Mask IN EP5 Tx FIFO Empty Interrupt</description>
9153 <description>Mask IN EP6 Tx FIFO Empty Interrupt</description>
9158 <description>Mask IN EP7 Tx FIFO Empty Interrupt</description>
9163 <description>Mask IN EP8 Tx FIFO Empty Interrupt</description>
9168 <description>Mask IN EP9 Tx FIFO Empty Interrupt</description>
9173 <description>Mask IN EP10 Tx FIFO Empty Interrupt</description>
9178 <description>Mask IN EP11 Tx FIFO Empty Interrupt</description>
9183 <description>Mask IN EP12 Tx FIFO Empty Interrupt</description>
9188 <description>Mask IN EP13 Tx FIFO Empty Interrupt</description>
9193 <description>Mask IN EP14 Tx FIFO Empty Interrupt</description>
9198 <description>Mask IN EP15 Tx FIFO Empty Interrupt</description>
9207 <description>Device Control IN Endpoint 0 Control Register</description>
9215 <description>Maximum Packet Size (MPS)</description>
9221 <description>64 bytes</description>
9226 <description>32 bytes</description>
9231 <description>16 bytes</description>
9236 <description>8 bytes</description>
9243 <description>USB Active Endpoint (USBActEP)</description>
9250 <description>Control endpoint is always active</description>
9257 <description>NAK Status (NAKSts)</description>
9264 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
9269 … <description>The core is transmitting NAK handshakes on this endpoint</description>
9276 <description>Endpoint Type (EPType)</description>
9283 <description>Endpoint Control 0</description>
9290 <description>STALL Handshake (Stall)</description>
9296 <description>No Stall</description>
9301 <description>Stall Handshake</description>
9308 <description>TxFIFO Number (TxFNum)</description>
9314 <description>Tx FIFO 0</description>
9319 <description>Tx FIFO 1</description>
9324 <description>Tx FIFO 2</description>
9329 <description>Tx FIFO 3</description>
9334 <description>Tx FIFO 4</description>
9339 <description>Tx FIFO 5</description>
9344 <description>Tx FIFO 6</description>
9349 <description>Tx FIFO 7</description>
9354 <description>Tx FIFO 8</description>
9359 <description>Tx FIFO 9</description>
9364 <description>Tx FIFO 10</description>
9369 <description>Tx FIFO 11</description>
9374 <description>Tx FIFO 12</description>
9379 <description>Tx FIFO 13</description>
9384 <description>Tx FIFO 14</description>
9389 <description>Tx FIFO 15</description>
9402 <description>No action</description>
9407 <description>Clear NAK</description>
9420 <description>No action</description>
9425 <description>Set NAK</description>
9432 <description>Endpoint Disable (EPDis)</description>
9438 <description>No action</description>
9443 <description>Disabled Endpoint</description>
9450 <description>Endpoint Enable (EPEna)</description>
9456 <description>No action</description>
9461 <description>Enable Endpoint</description>
9470 <description>Device IN Endpoint 0 Interrupt Register</description>
9478 <description>Transfer Completed Interrupt (XferCompl)</description>
9484 <description>No Transfer Complete Interrupt</description>
9489 <description>Transfer Completed Interrupt</description>
9496 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
9502 <description>No Endpoint Disabled Interrupt</description>
9507 <description>Endpoint Disabled Interrupt</description>
9514 <description>AHB Error (AHBErr)</description>
9520 <description>No AHB Error Interrupt</description>
9525 <description>AHB Error interrupt</description>
9532 <description>Timeout Condition (TimeOUT)</description>
9538 <description>No Timeout interrupt</description>
9543 <description>Timeout interrupt</description>
9550 <description>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</description>
9556 <description>No IN Token Received when TxFIFO Empty interrupt</description>
9561 <description>IN Token Received when TxFIFO Empty Interrupt</description>
9568 <description>IN Token Received with EP Mismatch (INTknEPMis)</description>
9574 <description>No IN Token Received with EP Mismatch interrupt</description>
9579 <description>IN Token Received with EP Mismatch interrupt</description>
9586 <description>IN Endpoint NAK Effective (INEPNakEff)</description>
9592 <description>No IN Endpoint NAK Effective interrupt</description>
9597 <description>IN Endpoint NAK Effective interrupt</description>
9604 <description>Transmit FIFO Empty (TxFEmp)</description>
9611 <description>No Transmit FIFO Empty interrupt</description>
9616 <description>Transmit FIFO Empty interrupt</description>
9623 <description>Fifo Underrun (TxfifoUndrn)</description>
9629 <description>No Fifo Underrun interrupt</description>
9634 <description>Fifo Underrun interrupt</description>
9641 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
9647 <description>No BNA interrupt</description>
9652 <description>BNA interrupt</description>
9659 <description>Packet Drop Status (PktDrpSts)</description>
9665 <description>No interrupt</description>
9670 <description>Packet Drop Status</description>
9677 <description>NAK Interrupt (BbleErr)</description>
9683 <description>No interrupt</description>
9688 <description>BbleErr interrupt</description>
9695 <description>NAK Interrupt (NAKInterrupt)</description>
9701 <description>No interrupt</description>
9706 <description>NAK Interrupt</description>
9713 <description>NYET Interrupt (NYETIntrpt)</description>
9719 <description>No interrupt</description>
9724 <description>NYET Interrupt</description>
9733 <description>Device IN Endpoint 0 Transfer Size Register</description>
9741 <description>Transfer Size (XferSize)</description>
9747 <description>Packet Count (PktCnt)</description>
9755 <description>Device IN Endpoint 0 DMA Address Register</description>
9763 <description>DMAAddr</description>
9771 <description>Device IN Endpoint Transmit FIFO Status Register 0</description>
9779 <description>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</description>
9788 <description>Device Control IN Endpoint Control Register</description>
9796 <description>Maximum Packet Size (MPS)</description>
9802 <description>USB Active Endpoint (USBActEP)</description>
9808 <description>Not Active</description>
9813 <description>USB Active Endpoint</description>
9826 <description>DATA0 or Even Frame</description>
9831 <description>DATA1 or Odd Frame</description>
9838 <description>NAK Status (NAKSts)</description>
9845 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
9850 … <description>The core is transmitting NAK handshakes on this endpoint</description>
9857 <description>Endpoint Type (EPType)</description>
9863 <description>Control</description>
9868 <description>Isochronous</description>
9873 <description>Bulk</description>
9878 <description>Interrupt</description>
9885 <description>STALL Handshake (Stall)</description>
9891 <description>STALL All non-active tokens</description>
9896 <description>STALL All Active Tokens</description>
9903 <description>TxFIFO Number (TxFNum)</description>
9909 <description>Tx FIFO 0</description>
9914 <description>Tx FIFO 1</description>
9919 <description>Tx FIFO 2</description>
9924 <description>Tx FIFO 3</description>
9929 <description>Tx FIFO 4</description>
9934 <description>Tx FIFO 5</description>
9939 <description>Tx FIFO 6</description>
9944 <description>Tx FIFO 7</description>
9949 <description>Tx FIFO 8</description>
9954 <description>Tx FIFO 9</description>
9959 <description>Tx FIFO 10</description>
9964 <description>Tx FIFO 11</description>
9969 <description>Tx FIFO 12</description>
9974 <description>Tx FIFO 13</description>
9979 <description>Tx FIFO 14</description>
9984 <description>Tx FIFO 15</description>
9991 <description>Clear NAK (CNAK)</description>
9998 <description>No Clear NAK</description>
10003 <description>Clear NAK</description>
10010 <description>Set NAK (SNAK)</description>
10017 <description>No Set NAK</description>
10022 <description>Set NAK</description>
10029 <description>Set DATA0 PID (SetD0PID)</description>
10036 … <description>Disables Set DATA0 PID or Do not force Even (micro)Frame</description>
10041 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame</descript…
10048 <description>Set DATA1 PID (SetD1PID)</description>
10055 … <description>Disables Set DATA1 PID or Do not force Odd (micro)Frame</description>
10060 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame</descripti…
10067 <description>Endpoint Disable (EPDis)</description>
10073 <description>No Action</description>
10078 <description>Disable Endpoint</description>
10085 <description>Endpoint Enable (EPEna)</description>
10091 <description>No Action</description>
10096 <description>Enable Endpoint</description>
10105 <description>Device IN Endpoint Interrupt Register</description>
10113 <description>Transfer Completed Interrupt (XferCompl)</description>
10119 <description>No Transfer Complete Interrupt</description>
10124 <description>Transfer Complete Interrupt</description>
10131 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
10137 <description>No Endpoint Disabled Interrupt</description>
10142 <description>Endpoint Disabled Interrupt</description>
10149 <description>AHB Error (AHBErr)</description>
10155 <description>No AHB Error Interrupt</description>
10160 <description>AHB Error interrupt</description>
10167 <description>Timeout Condition (TimeOUT)</description>
10173 <description>No Timeout interrupt</description>
10178 <description>Timeout interrupt</description>
10185 <description>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</description>
10191 <description>No IN Token Received interrupt</description>
10196 <description>IN Token Received Interrupt</description>
10203 <description>IN Token Received with EP Mismatch (INTknEPMis)</description>
10209 <description>No IN Token Received with EP Mismatch interrupt</description>
10214 <description>IN Token Received with EP Mismatch interrupt</description>
10221 <description>IN Endpoint NAK Effective (INEPNakEff)</description>
10227 <description>No Endpoint NAK Effective interrupt</description>
10232 <description>IN Endpoint NAK Effective interrupt</description>
10239 <description>Transmit FIFO Empty (TxFEmp)</description>
10246 <description>No Transmit FIFO Empty interrupt</description>
10251 <description>Transmit FIFO Empty interrupt</description>
10258 <description>Fifo Underrun (TxfifoUndrn)</description>
10264 <description>No Tx FIFO Underrun interrupt</description>
10269 <description>TxFIFO Underrun interrupt</description>
10276 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
10282 <description>No BNA interrupt</description>
10287 <description>BNA interrupt</description>
10294 <description>Packet Drop Status (PktDrpSts)</description>
10300 <description>No interrupt</description>
10305 <description>Packet Drop Status interrupt</description>
10312 <description>NAK Interrupt (BbleErr)</description>
10318 <description>No interrupt</description>
10323 <description>BbleErr interrupt</description>
10330 <description>NAK Interrupt (NAKInterrupt)</description>
10336 <description>No NAK interrupt</description>
10341 <description>NAK Interrupt</description>
10348 <description>NYET Interrupt (NYETIntrpt)</description>
10354 <description>No NYET interrupt</description>
10359 <description>NYET Interrupt</description>
10368 <description>Device IN Endpoint Transfer Size Register</description>
10376 <description>Transfer Size (XferSize)</description>
10382 <description>Packet Count (PktCnt)</description>
10388 <description>MC</description>
10394 <description>1 packet</description>
10399 <description>2 packets</description>
10404 <description>3 packets</description>
10413 <description>Device IN Endpoint DMA Address Register</description>
10421 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
10429 <description>Device IN Endpoint Transmit FIFO Status Register</description>
10437 <description>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</description>
10446 <description>Device Control IN Endpoint Control Register</description>
10454 <description>Maximum Packet Size (MPS)</description>
10460 <description>USB Active Endpoint (USBActEP)</description>
10466 <description>Not Active</description>
10471 <description>USB Active Endpoint</description>
10484 <description>DATA0 or Even Frame</description>
10489 <description>DATA1 or Odd Frame</description>
10496 <description>NAK Status (NAKSts)</description>
10503 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
10508 … <description>The core is transmitting NAK handshakes on this endpoint</description>
10515 <description>Endpoint Type (EPType)</description>
10521 <description>Control</description>
10526 <description>Isochronous</description>
10531 <description>Bulk</description>
10536 <description>Interrupt</description>
10543 <description>STALL Handshake (Stall)</description>
10549 <description>STALL All non-active tokens</description>
10554 <description>STALL All Active Tokens</description>
10561 <description>TxFIFO Number (TxFNum)</description>
10567 <description>Tx FIFO 0</description>
10572 <description>Tx FIFO 1</description>
10577 <description>Tx FIFO 2</description>
10582 <description>Tx FIFO 3</description>
10587 <description>Tx FIFO 4</description>
10592 <description>Tx FIFO 5</description>
10597 <description>Tx FIFO 6</description>
10602 <description>Tx FIFO 7</description>
10607 <description>Tx FIFO 8</description>
10612 <description>Tx FIFO 9</description>
10617 <description>Tx FIFO 10</description>
10622 <description>Tx FIFO 11</description>
10627 <description>Tx FIFO 12</description>
10632 <description>Tx FIFO 13</description>
10637 <description>Tx FIFO 14</description>
10642 <description>Tx FIFO 15</description>
10649 <description>Clear NAK (CNAK)</description>
10656 <description>No Clear NAK</description>
10661 <description>Clear NAK</description>
10668 <description>Set NAK (SNAK)</description>
10675 <description>No Set NAK</description>
10680 <description>Set NAK</description>
10687 <description>Set DATA0 PID (SetD0PID)</description>
10694 … <description>Disables Set DATA0 PID or Do not force Even (micro)Frame</description>
10699 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame</descript…
10706 <description>Set DATA1 PID (SetD1PID)</description>
10713 … <description>Disables Set DATA1 PID or Do not force Odd (micro)Frame</description>
10718 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame</descripti…
10725 <description>Endpoint Disable (EPDis)</description>
10731 <description>No Action</description>
10736 <description>Disable Endpoint</description>
10743 <description>Endpoint Enable (EPEna)</description>
10749 <description>No Action</description>
10754 <description>Enable Endpoint</description>
10763 <description>Device IN Endpoint Interrupt Register</description>
10771 <description>Transfer Completed Interrupt (XferCompl)</description>
10777 <description>No Transfer Complete Interrupt</description>
10782 <description>Transfer Complete Interrupt</description>
10789 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
10795 <description>No Endpoint Disabled Interrupt</description>
10800 <description>Endpoint Disabled Interrupt</description>
10807 <description>AHB Error (AHBErr)</description>
10813 <description>No AHB Error Interrupt</description>
10818 <description>AHB Error interrupt</description>
10825 <description>Timeout Condition (TimeOUT)</description>
10831 <description>No Timeout interrupt</description>
10836 <description>Timeout interrupt</description>
10843 <description>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</description>
10849 <description>No IN Token Received interrupt</description>
10854 <description>IN Token Received Interrupt</description>
10861 <description>IN Token Received with EP Mismatch (INTknEPMis)</description>
10867 <description>No IN Token Received with EP Mismatch interrupt</description>
10872 <description>IN Token Received with EP Mismatch interrupt</description>
10879 <description>IN Endpoint NAK Effective (INEPNakEff)</description>
10885 <description>No Endpoint NAK Effective interrupt</description>
10890 <description>IN Endpoint NAK Effective interrupt</description>
10897 <description>Transmit FIFO Empty (TxFEmp)</description>
10904 <description>No Transmit FIFO Empty interrupt</description>
10909 <description>Transmit FIFO Empty interrupt</description>
10916 <description>Fifo Underrun (TxfifoUndrn)</description>
10922 <description>No Tx FIFO Underrun interrupt</description>
10927 <description>TxFIFO Underrun interrupt</description>
10934 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
10940 <description>No BNA interrupt</description>
10945 <description>BNA interrupt</description>
10952 <description>Packet Drop Status (PktDrpSts)</description>
10958 <description>No interrupt</description>
10963 <description>Packet Drop Status interrupt</description>
10970 <description>NAK Interrupt (BbleErr)</description>
10976 <description>No interrupt</description>
10981 <description>BbleErr interrupt</description>
10988 <description>NAK Interrupt (NAKInterrupt)</description>
10994 <description>No NAK interrupt</description>
10999 <description>NAK Interrupt</description>
11006 <description>NYET Interrupt (NYETIntrpt)</description>
11012 <description>No NYET interrupt</description>
11017 <description>NYET Interrupt</description>
11026 <description>Device IN Endpoint Transfer Size Register</description>
11034 <description>Transfer Size (XferSize)</description>
11040 <description>Packet Count (PktCnt)</description>
11046 <description>MC</description>
11052 <description>1 packet</description>
11057 <description>2 packets</description>
11062 <description>3 packets</description>
11071 <description>Device IN Endpoint DMA Address Register</description>
11079 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
11087 <description>Device IN Endpoint Transmit FIFO Status Register</description>
11095 <description>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</description>
11104 <description>Device Control IN Endpoint Control Register</description>
11112 <description>Maximum Packet Size (MPS)</description>
11118 <description>USB Active Endpoint (USBActEP)</description>
11124 <description>Not Active</description>
11129 <description>USB Active Endpoint</description>
11142 <description>DATA0 or Even Frame</description>
11147 <description>DATA1 or Odd Frame</description>
11154 <description>NAK Status (NAKSts)</description>
11161 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
11166 … <description>The core is transmitting NAK handshakes on this endpoint</description>
11173 <description>Endpoint Type (EPType)</description>
11179 <description>Control</description>
11184 <description>Isochronous</description>
11189 <description>Bulk</description>
11194 <description>Interrupt</description>
11201 <description>STALL Handshake (Stall)</description>
11207 <description>STALL All non-active tokens</description>
11212 <description>STALL All Active Tokens</description>
11219 <description>TxFIFO Number (TxFNum)</description>
11225 <description>Tx FIFO 0</description>
11230 <description>Tx FIFO 1</description>
11235 <description>Tx FIFO 2</description>
11240 <description>Tx FIFO 3</description>
11245 <description>Tx FIFO 4</description>
11250 <description>Tx FIFO 5</description>
11255 <description>Tx FIFO 6</description>
11260 <description>Tx FIFO 7</description>
11265 <description>Tx FIFO 8</description>
11270 <description>Tx FIFO 9</description>
11275 <description>Tx FIFO 10</description>
11280 <description>Tx FIFO 11</description>
11285 <description>Tx FIFO 12</description>
11290 <description>Tx FIFO 13</description>
11295 <description>Tx FIFO 14</description>
11300 <description>Tx FIFO 15</description>
11307 <description>Clear NAK (CNAK)</description>
11314 <description>No Clear NAK</description>
11319 <description>Clear NAK</description>
11326 <description>Set NAK (SNAK)</description>
11333 <description>No Set NAK</description>
11338 <description>Set NAK</description>
11345 <description>Set DATA0 PID (SetD0PID)</description>
11352 … <description>Disables Set DATA0 PID or Do not force Even (micro)Frame</description>
11357 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame</descript…
11364 <description>Set DATA1 PID (SetD1PID)</description>
11371 … <description>Disables Set DATA1 PID or Do not force Odd (micro)Frame</description>
11376 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame</descripti…
11383 <description>Endpoint Disable (EPDis)</description>
11389 <description>No Action</description>
11394 <description>Disable Endpoint</description>
11401 <description>Endpoint Enable (EPEna)</description>
11407 <description>No Action</description>
11412 <description>Enable Endpoint</description>
11421 <description>Device IN Endpoint Interrupt Register</description>
11429 <description>Transfer Completed Interrupt (XferCompl)</description>
11435 <description>No Transfer Complete Interrupt</description>
11440 <description>Transfer Complete Interrupt</description>
11447 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
11453 <description>No Endpoint Disabled Interrupt</description>
11458 <description>Endpoint Disabled Interrupt</description>
11465 <description>AHB Error (AHBErr)</description>
11471 <description>No AHB Error Interrupt</description>
11476 <description>AHB Error interrupt</description>
11483 <description>Timeout Condition (TimeOUT)</description>
11489 <description>No Timeout interrupt</description>
11494 <description>Timeout interrupt</description>
11501 <description>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</description>
11507 <description>No IN Token Received interrupt</description>
11512 <description>IN Token Received Interrupt</description>
11519 <description>IN Token Received with EP Mismatch (INTknEPMis)</description>
11525 <description>No IN Token Received with EP Mismatch interrupt</description>
11530 <description>IN Token Received with EP Mismatch interrupt</description>
11537 <description>IN Endpoint NAK Effective (INEPNakEff)</description>
11543 <description>No Endpoint NAK Effective interrupt</description>
11548 <description>IN Endpoint NAK Effective interrupt</description>
11555 <description>Transmit FIFO Empty (TxFEmp)</description>
11562 <description>No Transmit FIFO Empty interrupt</description>
11567 <description>Transmit FIFO Empty interrupt</description>
11574 <description>Fifo Underrun (TxfifoUndrn)</description>
11580 <description>No Tx FIFO Underrun interrupt</description>
11585 <description>TxFIFO Underrun interrupt</description>
11592 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
11598 <description>No BNA interrupt</description>
11603 <description>BNA interrupt</description>
11610 <description>Packet Drop Status (PktDrpSts)</description>
11616 <description>No interrupt</description>
11621 <description>Packet Drop Status interrupt</description>
11628 <description>NAK Interrupt (BbleErr)</description>
11634 <description>No interrupt</description>
11639 <description>BbleErr interrupt</description>
11646 <description>NAK Interrupt (NAKInterrupt)</description>
11652 <description>No NAK interrupt</description>
11657 <description>NAK Interrupt</description>
11664 <description>NYET Interrupt (NYETIntrpt)</description>
11670 <description>No NYET interrupt</description>
11675 <description>NYET Interrupt</description>
11684 <description>Device IN Endpoint Transfer Size Register</description>
11692 <description>Transfer Size (XferSize)</description>
11698 <description>Packet Count (PktCnt)</description>
11704 <description>MC</description>
11710 <description>1 packet</description>
11715 <description>2 packets</description>
11720 <description>3 packets</description>
11729 <description>Device IN Endpoint DMA Address Register</description>
11737 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
11745 <description>Device IN Endpoint Transmit FIFO Status Register</description>
11753 <description>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</description>
11762 <description>Device Control IN Endpoint Control Register</description>
11770 <description>Maximum Packet Size (MPS)</description>
11776 <description>USB Active Endpoint (USBActEP)</description>
11782 <description>Not Active</description>
11787 <description>USB Active Endpoint</description>
11800 <description>DATA0 or Even Frame</description>
11805 <description>DATA1 or Odd Frame</description>
11812 <description>NAK Status (NAKSts)</description>
11819 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
11824 … <description>The core is transmitting NAK handshakes on this endpoint</description>
11831 <description>Endpoint Type (EPType)</description>
11837 <description>Control</description>
11842 <description>Isochronous</description>
11847 <description>Bulk</description>
11852 <description>Interrupt</description>
11859 <description>STALL Handshake (Stall)</description>
11865 <description>STALL All non-active tokens</description>
11870 <description>STALL All Active Tokens</description>
11877 <description>TxFIFO Number (TxFNum)</description>
11883 <description>Tx FIFO 0</description>
11888 <description>Tx FIFO 1</description>
11893 <description>Tx FIFO 2</description>
11898 <description>Tx FIFO 3</description>
11903 <description>Tx FIFO 4</description>
11908 <description>Tx FIFO 5</description>
11913 <description>Tx FIFO 6</description>
11918 <description>Tx FIFO 7</description>
11923 <description>Tx FIFO 8</description>
11928 <description>Tx FIFO 9</description>
11933 <description>Tx FIFO 10</description>
11938 <description>Tx FIFO 11</description>
11943 <description>Tx FIFO 12</description>
11948 <description>Tx FIFO 13</description>
11953 <description>Tx FIFO 14</description>
11958 <description>Tx FIFO 15</description>
11965 <description>Clear NAK (CNAK)</description>
11972 <description>No Clear NAK</description>
11977 <description>Clear NAK</description>
11984 <description>Set NAK (SNAK)</description>
11991 <description>No Set NAK</description>
11996 <description>Set NAK</description>
12003 <description>Set DATA0 PID (SetD0PID)</description>
12010 … <description>Disables Set DATA0 PID or Do not force Even (micro)Frame</description>
12015 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame</descript…
12022 <description>Set DATA1 PID (SetD1PID)</description>
12029 … <description>Disables Set DATA1 PID or Do not force Odd (micro)Frame</description>
12034 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame</descripti…
12041 <description>Endpoint Disable (EPDis)</description>
12047 <description>No Action</description>
12052 <description>Disable Endpoint</description>
12059 <description>Endpoint Enable (EPEna)</description>
12065 <description>No Action</description>
12070 <description>Enable Endpoint</description>
12079 <description>Device IN Endpoint Interrupt Register</description>
12087 <description>Transfer Completed Interrupt (XferCompl)</description>
12093 <description>No Transfer Complete Interrupt</description>
12098 <description>Transfer Complete Interrupt</description>
12105 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
12111 <description>No Endpoint Disabled Interrupt</description>
12116 <description>Endpoint Disabled Interrupt</description>
12123 <description>AHB Error (AHBErr)</description>
12129 <description>No AHB Error Interrupt</description>
12134 <description>AHB Error interrupt</description>
12141 <description>Timeout Condition (TimeOUT)</description>
12147 <description>No Timeout interrupt</description>
12152 <description>Timeout interrupt</description>
12159 <description>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</description>
12165 <description>No IN Token Received interrupt</description>
12170 <description>IN Token Received Interrupt</description>
12177 <description>IN Token Received with EP Mismatch (INTknEPMis)</description>
12183 <description>No IN Token Received with EP Mismatch interrupt</description>
12188 <description>IN Token Received with EP Mismatch interrupt</description>
12195 <description>IN Endpoint NAK Effective (INEPNakEff)</description>
12201 <description>No Endpoint NAK Effective interrupt</description>
12206 <description>IN Endpoint NAK Effective interrupt</description>
12213 <description>Transmit FIFO Empty (TxFEmp)</description>
12220 <description>No Transmit FIFO Empty interrupt</description>
12225 <description>Transmit FIFO Empty interrupt</description>
12232 <description>Fifo Underrun (TxfifoUndrn)</description>
12238 <description>No Tx FIFO Underrun interrupt</description>
12243 <description>TxFIFO Underrun interrupt</description>
12250 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
12256 <description>No BNA interrupt</description>
12261 <description>BNA interrupt</description>
12268 <description>Packet Drop Status (PktDrpSts)</description>
12274 <description>No interrupt</description>
12279 <description>Packet Drop Status interrupt</description>
12286 <description>NAK Interrupt (BbleErr)</description>
12292 <description>No interrupt</description>
12297 <description>BbleErr interrupt</description>
12304 <description>NAK Interrupt (NAKInterrupt)</description>
12310 <description>No NAK interrupt</description>
12315 <description>NAK Interrupt</description>
12322 <description>NYET Interrupt (NYETIntrpt)</description>
12328 <description>No NYET interrupt</description>
12333 <description>NYET Interrupt</description>
12342 <description>Device IN Endpoint Transfer Size Register</description>
12350 <description>Transfer Size (XferSize)</description>
12356 <description>Packet Count (PktCnt)</description>
12362 <description>MC</description>
12368 <description>1 packet</description>
12373 <description>2 packets</description>
12378 <description>3 packets</description>
12387 <description>Device IN Endpoint DMA Address Register</description>
12395 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
12403 <description>Device IN Endpoint Transmit FIFO Status Register</description>
12411 <description>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</description>
12420 <description>Device Control IN Endpoint Control Register</description>
12428 <description>Maximum Packet Size (MPS)</description>
12434 <description>USB Active Endpoint (USBActEP)</description>
12440 <description>Not Active</description>
12445 <description>USB Active Endpoint</description>
12458 <description>DATA0 or Even Frame</description>
12463 <description>DATA1 or Odd Frame</description>
12470 <description>NAK Status (NAKSts)</description>
12477 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
12482 … <description>The core is transmitting NAK handshakes on this endpoint</description>
12489 <description>Endpoint Type (EPType)</description>
12495 <description>Control</description>
12500 <description>Isochronous</description>
12505 <description>Bulk</description>
12510 <description>Interrupt</description>
12517 <description>STALL Handshake (Stall)</description>
12523 <description>STALL All non-active tokens</description>
12528 <description>STALL All Active Tokens</description>
12535 <description>TxFIFO Number (TxFNum)</description>
12541 <description>Tx FIFO 0</description>
12546 <description>Tx FIFO 1</description>
12551 <description>Tx FIFO 2</description>
12556 <description>Tx FIFO 3</description>
12561 <description>Tx FIFO 4</description>
12566 <description>Tx FIFO 5</description>
12571 <description>Tx FIFO 6</description>
12576 <description>Tx FIFO 7</description>
12581 <description>Tx FIFO 8</description>
12586 <description>Tx FIFO 9</description>
12591 <description>Tx FIFO 10</description>
12596 <description>Tx FIFO 11</description>
12601 <description>Tx FIFO 12</description>
12606 <description>Tx FIFO 13</description>
12611 <description>Tx FIFO 14</description>
12616 <description>Tx FIFO 15</description>
12623 <description>Clear NAK (CNAK)</description>
12630 <description>No Clear NAK</description>
12635 <description>Clear NAK</description>
12642 <description>Set NAK (SNAK)</description>
12649 <description>No Set NAK</description>
12654 <description>Set NAK</description>
12661 <description>Set DATA0 PID (SetD0PID)</description>
12668 … <description>Disables Set DATA0 PID or Do not force Even (micro)Frame</description>
12673 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame</descript…
12680 <description>Set DATA1 PID (SetD1PID)</description>
12687 … <description>Disables Set DATA1 PID or Do not force Odd (micro)Frame</description>
12692 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame</descripti…
12699 <description>Endpoint Disable (EPDis)</description>
12705 <description>No Action</description>
12710 <description>Disable Endpoint</description>
12717 <description>Endpoint Enable (EPEna)</description>
12723 <description>No Action</description>
12728 <description>Enable Endpoint</description>
12737 <description>Device IN Endpoint Interrupt Register</description>
12745 <description>Transfer Completed Interrupt (XferCompl)</description>
12751 <description>No Transfer Complete Interrupt</description>
12756 <description>Transfer Complete Interrupt</description>
12763 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
12769 <description>No Endpoint Disabled Interrupt</description>
12774 <description>Endpoint Disabled Interrupt</description>
12781 <description>AHB Error (AHBErr)</description>
12787 <description>No AHB Error Interrupt</description>
12792 <description>AHB Error interrupt</description>
12799 <description>Timeout Condition (TimeOUT)</description>
12805 <description>No Timeout interrupt</description>
12810 <description>Timeout interrupt</description>
12817 <description>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</description>
12823 <description>No IN Token Received interrupt</description>
12828 <description>IN Token Received Interrupt</description>
12835 <description>IN Token Received with EP Mismatch (INTknEPMis)</description>
12841 <description>No IN Token Received with EP Mismatch interrupt</description>
12846 <description>IN Token Received with EP Mismatch interrupt</description>
12853 <description>IN Endpoint NAK Effective (INEPNakEff)</description>
12859 <description>No Endpoint NAK Effective interrupt</description>
12864 <description>IN Endpoint NAK Effective interrupt</description>
12871 <description>Transmit FIFO Empty (TxFEmp)</description>
12878 <description>No Transmit FIFO Empty interrupt</description>
12883 <description>Transmit FIFO Empty interrupt</description>
12890 <description>Fifo Underrun (TxfifoUndrn)</description>
12896 <description>No Tx FIFO Underrun interrupt</description>
12901 <description>TxFIFO Underrun interrupt</description>
12908 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
12914 <description>No BNA interrupt</description>
12919 <description>BNA interrupt</description>
12926 <description>Packet Drop Status (PktDrpSts)</description>
12932 <description>No interrupt</description>
12937 <description>Packet Drop Status interrupt</description>
12944 <description>NAK Interrupt (BbleErr)</description>
12950 <description>No interrupt</description>
12955 <description>BbleErr interrupt</description>
12962 <description>NAK Interrupt (NAKInterrupt)</description>
12968 <description>No NAK interrupt</description>
12973 <description>NAK Interrupt</description>
12980 <description>NYET Interrupt (NYETIntrpt)</description>
12986 <description>No NYET interrupt</description>
12991 <description>NYET Interrupt</description>
13000 <description>Device IN Endpoint Transfer Size Register</description>
13008 <description>Transfer Size (XferSize)</description>
13014 <description>Packet Count (PktCnt)</description>
13020 <description>MC</description>
13026 <description>1 packet</description>
13031 <description>2 packets</description>
13036 <description>3 packets</description>
13045 <description>Device IN Endpoint DMA Address Register</description>
13053 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
13061 <description>Device IN Endpoint Transmit FIFO Status Register</description>
13069 <description>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</description>
13078 <description>Device Control IN Endpoint Control Register</description>
13086 <description>Maximum Packet Size (MPS)</description>
13092 <description>USB Active Endpoint (USBActEP)</description>
13098 <description>Not Active</description>
13103 <description>USB Active Endpoint</description>
13116 <description>DATA0 or Even Frame</description>
13121 <description>DATA1 or Odd Frame</description>
13128 <description>NAK Status (NAKSts)</description>
13135 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
13140 … <description>The core is transmitting NAK handshakes on this endpoint</description>
13147 <description>Endpoint Type (EPType)</description>
13153 <description>Control</description>
13158 <description>Isochronous</description>
13163 <description>Bulk</description>
13168 <description>Interrupt</description>
13175 <description>STALL Handshake (Stall)</description>
13181 <description>STALL All non-active tokens</description>
13186 <description>STALL All Active Tokens</description>
13193 <description>TxFIFO Number (TxFNum)</description>
13199 <description>Tx FIFO 0</description>
13204 <description>Tx FIFO 1</description>
13209 <description>Tx FIFO 2</description>
13214 <description>Tx FIFO 3</description>
13219 <description>Tx FIFO 4</description>
13224 <description>Tx FIFO 5</description>
13229 <description>Tx FIFO 6</description>
13234 <description>Tx FIFO 7</description>
13239 <description>Tx FIFO 8</description>
13244 <description>Tx FIFO 9</description>
13249 <description>Tx FIFO 10</description>
13254 <description>Tx FIFO 11</description>
13259 <description>Tx FIFO 12</description>
13264 <description>Tx FIFO 13</description>
13269 <description>Tx FIFO 14</description>
13274 <description>Tx FIFO 15</description>
13281 <description>Clear NAK (CNAK)</description>
13288 <description>No Clear NAK</description>
13293 <description>Clear NAK</description>
13300 <description>Set NAK (SNAK)</description>
13307 <description>No Set NAK</description>
13312 <description>Set NAK</description>
13319 <description>Set DATA0 PID (SetD0PID)</description>
13326 … <description>Disables Set DATA0 PID or Do not force Even (micro)Frame</description>
13331 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame</descript…
13338 <description>Set DATA1 PID (SetD1PID)</description>
13345 … <description>Disables Set DATA1 PID or Do not force Odd (micro)Frame</description>
13350 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame</descripti…
13357 <description>Endpoint Disable (EPDis)</description>
13363 <description>No Action</description>
13368 <description>Disable Endpoint</description>
13375 <description>Endpoint Enable (EPEna)</description>
13381 <description>No Action</description>
13386 <description>Enable Endpoint</description>
13395 <description>Device IN Endpoint Interrupt Register</description>
13403 <description>Transfer Completed Interrupt (XferCompl)</description>
13409 <description>No Transfer Complete Interrupt</description>
13414 <description>Transfer Complete Interrupt</description>
13421 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
13427 <description>No Endpoint Disabled Interrupt</description>
13432 <description>Endpoint Disabled Interrupt</description>
13439 <description>AHB Error (AHBErr)</description>
13445 <description>No AHB Error Interrupt</description>
13450 <description>AHB Error interrupt</description>
13457 <description>Timeout Condition (TimeOUT)</description>
13463 <description>No Timeout interrupt</description>
13468 <description>Timeout interrupt</description>
13475 <description>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</description>
13481 <description>No IN Token Received interrupt</description>
13486 <description>IN Token Received Interrupt</description>
13493 <description>IN Token Received with EP Mismatch (INTknEPMis)</description>
13499 <description>No IN Token Received with EP Mismatch interrupt</description>
13504 <description>IN Token Received with EP Mismatch interrupt</description>
13511 <description>IN Endpoint NAK Effective (INEPNakEff)</description>
13517 <description>No Endpoint NAK Effective interrupt</description>
13522 <description>IN Endpoint NAK Effective interrupt</description>
13529 <description>Transmit FIFO Empty (TxFEmp)</description>
13536 <description>No Transmit FIFO Empty interrupt</description>
13541 <description>Transmit FIFO Empty interrupt</description>
13548 <description>Fifo Underrun (TxfifoUndrn)</description>
13554 <description>No Tx FIFO Underrun interrupt</description>
13559 <description>TxFIFO Underrun interrupt</description>
13566 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
13572 <description>No BNA interrupt</description>
13577 <description>BNA interrupt</description>
13584 <description>Packet Drop Status (PktDrpSts)</description>
13590 <description>No interrupt</description>
13595 <description>Packet Drop Status interrupt</description>
13602 <description>NAK Interrupt (BbleErr)</description>
13608 <description>No interrupt</description>
13613 <description>BbleErr interrupt</description>
13620 <description>NAK Interrupt (NAKInterrupt)</description>
13626 <description>No NAK interrupt</description>
13631 <description>NAK Interrupt</description>
13638 <description>NYET Interrupt (NYETIntrpt)</description>
13644 <description>No NYET interrupt</description>
13649 <description>NYET Interrupt</description>
13658 <description>Device IN Endpoint Transfer Size Register</description>
13666 <description>Transfer Size (XferSize)</description>
13672 <description>Packet Count (PktCnt)</description>
13678 <description>MC</description>
13684 <description>1 packet</description>
13689 <description>2 packets</description>
13694 <description>3 packets</description>
13703 <description>Device IN Endpoint DMA Address Register</description>
13711 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
13719 <description>Device IN Endpoint Transmit FIFO Status Register</description>
13727 <description>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</description>
13736 <description>Device Control IN Endpoint Control Register</description>
13744 <description>Maximum Packet Size (MPS)</description>
13750 <description>USB Active Endpoint (USBActEP)</description>
13756 <description>Not Active</description>
13761 <description>USB Active Endpoint</description>
13774 <description>DATA0 or Even Frame</description>
13779 <description>DATA1 or Odd Frame</description>
13786 <description>NAK Status (NAKSts)</description>
13793 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
13798 … <description>The core is transmitting NAK handshakes on this endpoint</description>
13805 <description>Endpoint Type (EPType)</description>
13811 <description>Control</description>
13816 <description>Isochronous</description>
13821 <description>Bulk</description>
13826 <description>Interrupt</description>
13833 <description>STALL Handshake (Stall)</description>
13839 <description>STALL All non-active tokens</description>
13844 <description>STALL All Active Tokens</description>
13851 <description>TxFIFO Number (TxFNum)</description>
13857 <description>Tx FIFO 0</description>
13862 <description>Tx FIFO 1</description>
13867 <description>Tx FIFO 2</description>
13872 <description>Tx FIFO 3</description>
13877 <description>Tx FIFO 4</description>
13882 <description>Tx FIFO 5</description>
13887 <description>Tx FIFO 6</description>
13892 <description>Tx FIFO 7</description>
13897 <description>Tx FIFO 8</description>
13902 <description>Tx FIFO 9</description>
13907 <description>Tx FIFO 10</description>
13912 <description>Tx FIFO 11</description>
13917 <description>Tx FIFO 12</description>
13922 <description>Tx FIFO 13</description>
13927 <description>Tx FIFO 14</description>
13932 <description>Tx FIFO 15</description>
13939 <description>Clear NAK (CNAK)</description>
13946 <description>No Clear NAK</description>
13951 <description>Clear NAK</description>
13958 <description>Set NAK (SNAK)</description>
13965 <description>No Set NAK</description>
13970 <description>Set NAK</description>
13977 <description>Set DATA0 PID (SetD0PID)</description>
13984 … <description>Disables Set DATA0 PID or Do not force Even (micro)Frame</description>
13989 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame</descript…
13996 <description>Set DATA1 PID (SetD1PID)</description>
14003 … <description>Disables Set DATA1 PID or Do not force Odd (micro)Frame</description>
14008 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame</descripti…
14015 <description>Endpoint Disable (EPDis)</description>
14021 <description>No Action</description>
14026 <description>Disable Endpoint</description>
14033 <description>Endpoint Enable (EPEna)</description>
14039 <description>No Action</description>
14044 <description>Enable Endpoint</description>
14053 <description>Device IN Endpoint Interrupt Register</description>
14061 <description>Transfer Completed Interrupt (XferCompl)</description>
14067 <description>No Transfer Complete Interrupt</description>
14072 <description>Transfer Complete Interrupt</description>
14079 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
14085 <description>No Endpoint Disabled Interrupt</description>
14090 <description>Endpoint Disabled Interrupt</description>
14097 <description>AHB Error (AHBErr)</description>
14103 <description>No AHB Error Interrupt</description>
14108 <description>AHB Error interrupt</description>
14115 <description>Timeout Condition (TimeOUT)</description>
14121 <description>No Timeout interrupt</description>
14126 <description>Timeout interrupt</description>
14133 <description>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</description>
14139 <description>No IN Token Received interrupt</description>
14144 <description>IN Token Received Interrupt</description>
14151 <description>IN Token Received with EP Mismatch (INTknEPMis)</description>
14157 <description>No IN Token Received with EP Mismatch interrupt</description>
14162 <description>IN Token Received with EP Mismatch interrupt</description>
14169 <description>IN Endpoint NAK Effective (INEPNakEff)</description>
14175 <description>No Endpoint NAK Effective interrupt</description>
14180 <description>IN Endpoint NAK Effective interrupt</description>
14187 <description>Transmit FIFO Empty (TxFEmp)</description>
14194 <description>No Transmit FIFO Empty interrupt</description>
14199 <description>Transmit FIFO Empty interrupt</description>
14206 <description>Fifo Underrun (TxfifoUndrn)</description>
14212 <description>No Tx FIFO Underrun interrupt</description>
14217 <description>TxFIFO Underrun interrupt</description>
14224 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
14230 <description>No BNA interrupt</description>
14235 <description>BNA interrupt</description>
14242 <description>Packet Drop Status (PktDrpSts)</description>
14248 <description>No interrupt</description>
14253 <description>Packet Drop Status interrupt</description>
14260 <description>NAK Interrupt (BbleErr)</description>
14266 <description>No interrupt</description>
14271 <description>BbleErr interrupt</description>
14278 <description>NAK Interrupt (NAKInterrupt)</description>
14284 <description>No NAK interrupt</description>
14289 <description>NAK Interrupt</description>
14296 <description>NYET Interrupt (NYETIntrpt)</description>
14302 <description>No NYET interrupt</description>
14307 <description>NYET Interrupt</description>
14316 <description>Device IN Endpoint Transfer Size Register</description>
14324 <description>Transfer Size (XferSize)</description>
14330 <description>Packet Count (PktCnt)</description>
14336 <description>MC</description>
14342 <description>1 packet</description>
14347 <description>2 packets</description>
14352 <description>3 packets</description>
14361 <description>Device IN Endpoint DMA Address Register</description>
14369 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
14377 <description>Device IN Endpoint Transmit FIFO Status Register</description>
14385 <description>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</description>
14394 <description>Device Control IN Endpoint Control Register</description>
14402 <description>Maximum Packet Size (MPS)</description>
14408 <description>USB Active Endpoint (USBActEP)</description>
14414 <description>Not Active</description>
14419 <description>USB Active Endpoint</description>
14432 <description>DATA0 or Even Frame</description>
14437 <description>DATA1 or Odd Frame</description>
14444 <description>NAK Status (NAKSts)</description>
14451 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
14456 … <description>The core is transmitting NAK handshakes on this endpoint</description>
14463 <description>Endpoint Type (EPType)</description>
14469 <description>Control</description>
14474 <description>Isochronous</description>
14479 <description>Bulk</description>
14484 <description>Interrupt</description>
14491 <description>STALL Handshake (Stall)</description>
14497 <description>STALL All non-active tokens</description>
14502 <description>STALL All Active Tokens</description>
14509 <description>TxFIFO Number (TxFNum)</description>
14515 <description>Tx FIFO 0</description>
14520 <description>Tx FIFO 1</description>
14525 <description>Tx FIFO 2</description>
14530 <description>Tx FIFO 3</description>
14535 <description>Tx FIFO 4</description>
14540 <description>Tx FIFO 5</description>
14545 <description>Tx FIFO 6</description>
14550 <description>Tx FIFO 7</description>
14555 <description>Tx FIFO 8</description>
14560 <description>Tx FIFO 9</description>
14565 <description>Tx FIFO 10</description>
14570 <description>Tx FIFO 11</description>
14575 <description>Tx FIFO 12</description>
14580 <description>Tx FIFO 13</description>
14585 <description>Tx FIFO 14</description>
14590 <description>Tx FIFO 15</description>
14597 <description>Clear NAK (CNAK)</description>
14604 <description>No Clear NAK</description>
14609 <description>Clear NAK</description>
14616 <description>Set NAK (SNAK)</description>
14623 <description>No Set NAK</description>
14628 <description>Set NAK</description>
14635 <description>Set DATA0 PID (SetD0PID)</description>
14642 … <description>Disables Set DATA0 PID or Do not force Even (micro)Frame</description>
14647 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame</descript…
14654 <description>Set DATA1 PID (SetD1PID)</description>
14661 … <description>Disables Set DATA1 PID or Do not force Odd (micro)Frame</description>
14666 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame</descripti…
14673 <description>Endpoint Disable (EPDis)</description>
14679 <description>No Action</description>
14684 <description>Disable Endpoint</description>
14691 <description>Endpoint Enable (EPEna)</description>
14697 <description>No Action</description>
14702 <description>Enable Endpoint</description>
14711 <description>Device IN Endpoint Interrupt Register</description>
14719 <description>Transfer Completed Interrupt (XferCompl)</description>
14725 <description>No Transfer Complete Interrupt</description>
14730 <description>Transfer Complete Interrupt</description>
14737 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
14743 <description>No Endpoint Disabled Interrupt</description>
14748 <description>Endpoint Disabled Interrupt</description>
14755 <description>AHB Error (AHBErr)</description>
14761 <description>No AHB Error Interrupt</description>
14766 <description>AHB Error interrupt</description>
14773 <description>Timeout Condition (TimeOUT)</description>
14779 <description>No Timeout interrupt</description>
14784 <description>Timeout interrupt</description>
14791 <description>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</description>
14797 <description>No IN Token Received interrupt</description>
14802 <description>IN Token Received Interrupt</description>
14809 <description>IN Token Received with EP Mismatch (INTknEPMis)</description>
14815 <description>No IN Token Received with EP Mismatch interrupt</description>
14820 <description>IN Token Received with EP Mismatch interrupt</description>
14827 <description>IN Endpoint NAK Effective (INEPNakEff)</description>
14833 <description>No Endpoint NAK Effective interrupt</description>
14838 <description>IN Endpoint NAK Effective interrupt</description>
14845 <description>Transmit FIFO Empty (TxFEmp)</description>
14852 <description>No Transmit FIFO Empty interrupt</description>
14857 <description>Transmit FIFO Empty interrupt</description>
14864 <description>Fifo Underrun (TxfifoUndrn)</description>
14870 <description>No Tx FIFO Underrun interrupt</description>
14875 <description>TxFIFO Underrun interrupt</description>
14882 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
14888 <description>No BNA interrupt</description>
14893 <description>BNA interrupt</description>
14900 <description>Packet Drop Status (PktDrpSts)</description>
14906 <description>No interrupt</description>
14911 <description>Packet Drop Status interrupt</description>
14918 <description>NAK Interrupt (BbleErr)</description>
14924 <description>No interrupt</description>
14929 <description>BbleErr interrupt</description>
14936 <description>NAK Interrupt (NAKInterrupt)</description>
14942 <description>No NAK interrupt</description>
14947 <description>NAK Interrupt</description>
14954 <description>NYET Interrupt (NYETIntrpt)</description>
14960 <description>No NYET interrupt</description>
14965 <description>NYET Interrupt</description>
14974 <description>Device IN Endpoint Transfer Size Register</description>
14982 <description>Transfer Size (XferSize)</description>
14988 <description>Packet Count (PktCnt)</description>
14994 <description>MC</description>
15000 <description>1 packet</description>
15005 <description>2 packets</description>
15010 <description>3 packets</description>
15019 <description>Device IN Endpoint DMA Address Register</description>
15027 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
15035 <description>Device IN Endpoint Transmit FIFO Status Register</description>
15043 <description>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</description>
15052 <description>Device Control IN Endpoint Control Register</description>
15060 <description>Maximum Packet Size (MPS)</description>
15066 <description>USB Active Endpoint (USBActEP)</description>
15072 <description>Not Active</description>
15077 <description>USB Active Endpoint</description>
15090 <description>DATA0 or Even Frame</description>
15095 <description>DATA1 or Odd Frame</description>
15102 <description>NAK Status (NAKSts)</description>
15109 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
15114 … <description>The core is transmitting NAK handshakes on this endpoint</description>
15121 <description>Endpoint Type (EPType)</description>
15127 <description>Control</description>
15132 <description>Isochronous</description>
15137 <description>Bulk</description>
15142 <description>Interrupt</description>
15149 <description>STALL Handshake (Stall)</description>
15155 <description>STALL All non-active tokens</description>
15160 <description>STALL All Active Tokens</description>
15167 <description>TxFIFO Number (TxFNum)</description>
15173 <description>Tx FIFO 0</description>
15178 <description>Tx FIFO 1</description>
15183 <description>Tx FIFO 2</description>
15188 <description>Tx FIFO 3</description>
15193 <description>Tx FIFO 4</description>
15198 <description>Tx FIFO 5</description>
15203 <description>Tx FIFO 6</description>
15208 <description>Tx FIFO 7</description>
15213 <description>Tx FIFO 8</description>
15218 <description>Tx FIFO 9</description>
15223 <description>Tx FIFO 10</description>
15228 <description>Tx FIFO 11</description>
15233 <description>Tx FIFO 12</description>
15238 <description>Tx FIFO 13</description>
15243 <description>Tx FIFO 14</description>
15248 <description>Tx FIFO 15</description>
15255 <description>Clear NAK (CNAK)</description>
15262 <description>No Clear NAK</description>
15267 <description>Clear NAK</description>
15274 <description>Set NAK (SNAK)</description>
15281 <description>No Set NAK</description>
15286 <description>Set NAK</description>
15293 <description>Set DATA0 PID (SetD0PID)</description>
15300 … <description>Disables Set DATA0 PID or Do not force Even (micro)Frame</description>
15305 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame</descript…
15312 <description>Set DATA1 PID (SetD1PID)</description>
15319 … <description>Disables Set DATA1 PID or Do not force Odd (micro)Frame</description>
15324 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame</descripti…
15331 <description>Endpoint Disable (EPDis)</description>
15337 <description>No Action</description>
15342 <description>Disable Endpoint</description>
15349 <description>Endpoint Enable (EPEna)</description>
15355 <description>No Action</description>
15360 <description>Enable Endpoint</description>
15369 <description>Device IN Endpoint Interrupt Register</description>
15377 <description>Transfer Completed Interrupt (XferCompl)</description>
15383 <description>No Transfer Complete Interrupt</description>
15388 <description>Transfer Complete Interrupt</description>
15395 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
15401 <description>No Endpoint Disabled Interrupt</description>
15406 <description>Endpoint Disabled Interrupt</description>
15413 <description>AHB Error (AHBErr)</description>
15419 <description>No AHB Error Interrupt</description>
15424 <description>AHB Error interrupt</description>
15431 <description>Timeout Condition (TimeOUT)</description>
15437 <description>No Timeout interrupt</description>
15442 <description>Timeout interrupt</description>
15449 <description>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</description>
15455 <description>No IN Token Received interrupt</description>
15460 <description>IN Token Received Interrupt</description>
15467 <description>IN Token Received with EP Mismatch (INTknEPMis)</description>
15473 <description>No IN Token Received with EP Mismatch interrupt</description>
15478 <description>IN Token Received with EP Mismatch interrupt</description>
15485 <description>IN Endpoint NAK Effective (INEPNakEff)</description>
15491 <description>No Endpoint NAK Effective interrupt</description>
15496 <description>IN Endpoint NAK Effective interrupt</description>
15503 <description>Transmit FIFO Empty (TxFEmp)</description>
15510 <description>No Transmit FIFO Empty interrupt</description>
15515 <description>Transmit FIFO Empty interrupt</description>
15522 <description>Fifo Underrun (TxfifoUndrn)</description>
15528 <description>No Tx FIFO Underrun interrupt</description>
15533 <description>TxFIFO Underrun interrupt</description>
15540 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
15546 <description>No BNA interrupt</description>
15551 <description>BNA interrupt</description>
15558 <description>Packet Drop Status (PktDrpSts)</description>
15564 <description>No interrupt</description>
15569 <description>Packet Drop Status interrupt</description>
15576 <description>NAK Interrupt (BbleErr)</description>
15582 <description>No interrupt</description>
15587 <description>BbleErr interrupt</description>
15594 <description>NAK Interrupt (NAKInterrupt)</description>
15600 <description>No NAK interrupt</description>
15605 <description>NAK Interrupt</description>
15612 <description>NYET Interrupt (NYETIntrpt)</description>
15618 <description>No NYET interrupt</description>
15623 <description>NYET Interrupt</description>
15632 <description>Device IN Endpoint Transfer Size Register</description>
15640 <description>Transfer Size (XferSize)</description>
15646 <description>Packet Count (PktCnt)</description>
15652 <description>MC</description>
15658 <description>1 packet</description>
15663 <description>2 packets</description>
15668 <description>3 packets</description>
15677 <description>Device IN Endpoint DMA Address Register</description>
15685 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
15693 <description>Device IN Endpoint Transmit FIFO Status Register</description>
15701 <description>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</description>
15710 <description>Device Control IN Endpoint Control Register</description>
15718 <description>Maximum Packet Size (MPS)</description>
15724 <description>USB Active Endpoint (USBActEP)</description>
15730 <description>Not Active</description>
15735 <description>USB Active Endpoint</description>
15748 <description>DATA0 or Even Frame</description>
15753 <description>DATA1 or Odd Frame</description>
15760 <description>NAK Status (NAKSts)</description>
15767 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
15772 … <description>The core is transmitting NAK handshakes on this endpoint</description>
15779 <description>Endpoint Type (EPType)</description>
15785 <description>Control</description>
15790 <description>Isochronous</description>
15795 <description>Bulk</description>
15800 <description>Interrupt</description>
15807 <description>STALL Handshake (Stall)</description>
15813 <description>STALL All non-active tokens</description>
15818 <description>STALL All Active Tokens</description>
15825 <description>TxFIFO Number (TxFNum)</description>
15831 <description>Tx FIFO 0</description>
15836 <description>Tx FIFO 1</description>
15841 <description>Tx FIFO 2</description>
15846 <description>Tx FIFO 3</description>
15851 <description>Tx FIFO 4</description>
15856 <description>Tx FIFO 5</description>
15861 <description>Tx FIFO 6</description>
15866 <description>Tx FIFO 7</description>
15871 <description>Tx FIFO 8</description>
15876 <description>Tx FIFO 9</description>
15881 <description>Tx FIFO 10</description>
15886 <description>Tx FIFO 11</description>
15891 <description>Tx FIFO 12</description>
15896 <description>Tx FIFO 13</description>
15901 <description>Tx FIFO 14</description>
15906 <description>Tx FIFO 15</description>
15913 <description>Clear NAK (CNAK)</description>
15920 <description>No Clear NAK</description>
15925 <description>Clear NAK</description>
15932 <description>Set NAK (SNAK)</description>
15939 <description>No Set NAK</description>
15944 <description>Set NAK</description>
15951 <description>Set DATA0 PID (SetD0PID)</description>
15958 … <description>Disables Set DATA0 PID or Do not force Even (micro)Frame</description>
15963 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame</descript…
15970 <description>Set DATA1 PID (SetD1PID)</description>
15977 … <description>Disables Set DATA1 PID or Do not force Odd (micro)Frame</description>
15982 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame</descripti…
15989 <description>Endpoint Disable (EPDis)</description>
15995 <description>No Action</description>
16000 <description>Disable Endpoint</description>
16007 <description>Endpoint Enable (EPEna)</description>
16013 <description>No Action</description>
16018 <description>Enable Endpoint</description>
16027 <description>Device IN Endpoint Interrupt Register</description>
16035 <description>Transfer Completed Interrupt (XferCompl)</description>
16041 <description>No Transfer Complete Interrupt</description>
16046 <description>Transfer Complete Interrupt</description>
16053 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
16059 <description>No Endpoint Disabled Interrupt</description>
16064 <description>Endpoint Disabled Interrupt</description>
16071 <description>AHB Error (AHBErr)</description>
16077 <description>No AHB Error Interrupt</description>
16082 <description>AHB Error interrupt</description>
16089 <description>Timeout Condition (TimeOUT)</description>
16095 <description>No Timeout interrupt</description>
16100 <description>Timeout interrupt</description>
16107 <description>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</description>
16113 <description>No IN Token Received interrupt</description>
16118 <description>IN Token Received Interrupt</description>
16125 <description>IN Token Received with EP Mismatch (INTknEPMis)</description>
16131 <description>No IN Token Received with EP Mismatch interrupt</description>
16136 <description>IN Token Received with EP Mismatch interrupt</description>
16143 <description>IN Endpoint NAK Effective (INEPNakEff)</description>
16149 <description>No Endpoint NAK Effective interrupt</description>
16154 <description>IN Endpoint NAK Effective interrupt</description>
16161 <description>Transmit FIFO Empty (TxFEmp)</description>
16168 <description>No Transmit FIFO Empty interrupt</description>
16173 <description>Transmit FIFO Empty interrupt</description>
16180 <description>Fifo Underrun (TxfifoUndrn)</description>
16186 <description>No Tx FIFO Underrun interrupt</description>
16191 <description>TxFIFO Underrun interrupt</description>
16198 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
16204 <description>No BNA interrupt</description>
16209 <description>BNA interrupt</description>
16216 <description>Packet Drop Status (PktDrpSts)</description>
16222 <description>No interrupt</description>
16227 <description>Packet Drop Status interrupt</description>
16234 <description>NAK Interrupt (BbleErr)</description>
16240 <description>No interrupt</description>
16245 <description>BbleErr interrupt</description>
16252 <description>NAK Interrupt (NAKInterrupt)</description>
16258 <description>No NAK interrupt</description>
16263 <description>NAK Interrupt</description>
16270 <description>NYET Interrupt (NYETIntrpt)</description>
16276 <description>No NYET interrupt</description>
16281 <description>NYET Interrupt</description>
16290 <description>Device IN Endpoint Transfer Size Register</description>
16298 <description>Transfer Size (XferSize)</description>
16304 <description>Packet Count (PktCnt)</description>
16310 <description>MC</description>
16316 <description>1 packet</description>
16321 <description>2 packets</description>
16326 <description>3 packets</description>
16335 <description>Device IN Endpoint DMA Address Register</description>
16343 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
16351 <description>Device IN Endpoint Transmit FIFO Status Register</description>
16359 <description>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</description>
16368 <description>Device Control IN Endpoint Control Register</description>
16376 <description>Maximum Packet Size (MPS)</description>
16382 <description>USB Active Endpoint (USBActEP)</description>
16388 <description>Not Active</description>
16393 <description>USB Active Endpoint</description>
16406 <description>DATA0 or Even Frame</description>
16411 <description>DATA1 or Odd Frame</description>
16418 <description>NAK Status (NAKSts)</description>
16425 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
16430 … <description>The core is transmitting NAK handshakes on this endpoint</description>
16437 <description>Endpoint Type (EPType)</description>
16443 <description>Control</description>
16448 <description>Isochronous</description>
16453 <description>Bulk</description>
16458 <description>Interrupt</description>
16465 <description>STALL Handshake (Stall)</description>
16471 <description>STALL All non-active tokens</description>
16476 <description>STALL All Active Tokens</description>
16483 <description>TxFIFO Number (TxFNum)</description>
16489 <description>Tx FIFO 0</description>
16494 <description>Tx FIFO 1</description>
16499 <description>Tx FIFO 2</description>
16504 <description>Tx FIFO 3</description>
16509 <description>Tx FIFO 4</description>
16514 <description>Tx FIFO 5</description>
16519 <description>Tx FIFO 6</description>
16524 <description>Tx FIFO 7</description>
16529 <description>Tx FIFO 8</description>
16534 <description>Tx FIFO 9</description>
16539 <description>Tx FIFO 10</description>
16544 <description>Tx FIFO 11</description>
16549 <description>Tx FIFO 12</description>
16554 <description>Tx FIFO 13</description>
16559 <description>Tx FIFO 14</description>
16564 <description>Tx FIFO 15</description>
16571 <description>Clear NAK (CNAK)</description>
16578 <description>No Clear NAK</description>
16583 <description>Clear NAK</description>
16590 <description>Set NAK (SNAK)</description>
16597 <description>No Set NAK</description>
16602 <description>Set NAK</description>
16609 <description>Set DATA0 PID (SetD0PID)</description>
16616 … <description>Disables Set DATA0 PID or Do not force Even (micro)Frame</description>
16621 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame</descript…
16628 <description>Set DATA1 PID (SetD1PID)</description>
16635 … <description>Disables Set DATA1 PID or Do not force Odd (micro)Frame</description>
16640 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame</descripti…
16647 <description>Endpoint Disable (EPDis)</description>
16653 <description>No Action</description>
16658 <description>Disable Endpoint</description>
16665 <description>Endpoint Enable (EPEna)</description>
16671 <description>No Action</description>
16676 <description>Enable Endpoint</description>
16685 <description>Device IN Endpoint Interrupt Register</description>
16693 <description>Transfer Completed Interrupt (XferCompl)</description>
16699 <description>No Transfer Complete Interrupt</description>
16704 <description>Transfer Complete Interrupt</description>
16711 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
16717 <description>No Endpoint Disabled Interrupt</description>
16722 <description>Endpoint Disabled Interrupt</description>
16729 <description>AHB Error (AHBErr)</description>
16735 <description>No AHB Error Interrupt</description>
16740 <description>AHB Error interrupt</description>
16747 <description>Timeout Condition (TimeOUT)</description>
16753 <description>No Timeout interrupt</description>
16758 <description>Timeout interrupt</description>
16765 <description>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</description>
16771 <description>No IN Token Received interrupt</description>
16776 <description>IN Token Received Interrupt</description>
16783 <description>IN Token Received with EP Mismatch (INTknEPMis)</description>
16789 <description>No IN Token Received with EP Mismatch interrupt</description>
16794 <description>IN Token Received with EP Mismatch interrupt</description>
16801 <description>IN Endpoint NAK Effective (INEPNakEff)</description>
16807 <description>No Endpoint NAK Effective interrupt</description>
16812 <description>IN Endpoint NAK Effective interrupt</description>
16819 <description>Transmit FIFO Empty (TxFEmp)</description>
16826 <description>No Transmit FIFO Empty interrupt</description>
16831 <description>Transmit FIFO Empty interrupt</description>
16838 <description>Fifo Underrun (TxfifoUndrn)</description>
16844 <description>No Tx FIFO Underrun interrupt</description>
16849 <description>TxFIFO Underrun interrupt</description>
16856 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
16862 <description>No BNA interrupt</description>
16867 <description>BNA interrupt</description>
16874 <description>Packet Drop Status (PktDrpSts)</description>
16880 <description>No interrupt</description>
16885 <description>Packet Drop Status interrupt</description>
16892 <description>NAK Interrupt (BbleErr)</description>
16898 <description>No interrupt</description>
16903 <description>BbleErr interrupt</description>
16910 <description>NAK Interrupt (NAKInterrupt)</description>
16916 <description>No NAK interrupt</description>
16921 <description>NAK Interrupt</description>
16928 <description>NYET Interrupt (NYETIntrpt)</description>
16934 <description>No NYET interrupt</description>
16939 <description>NYET Interrupt</description>
16948 <description>Device IN Endpoint Transfer Size Register</description>
16956 <description>Transfer Size (XferSize)</description>
16962 <description>Packet Count (PktCnt)</description>
16968 <description>MC</description>
16974 <description>1 packet</description>
16979 <description>2 packets</description>
16984 <description>3 packets</description>
16993 <description>Device IN Endpoint DMA Address Register</description>
17001 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
17009 <description>Device IN Endpoint Transmit FIFO Status Register</description>
17017 <description>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</description>
17026 <description>Device Control OUT Endpoint 0 Control Register</description>
17034 <description>Maximum Packet Size (MPS)</description>
17041 <description>64 bytes</description>
17046 <description>32 bytes</description>
17051 <description>16 bytes</description>
17056 <description>8 bytes</description>
17063 <description>USB Active Endpoint (USBActEP)</description>
17070 <description>USB Active Endpoint 0</description>
17077 <description>NAK Status (NAKSts)</description>
17084 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
17089 … <description>The core is transmitting NAK handshakes on this endpoint</description>
17096 <description>Endpoint Type (EPType)</description>
17103 <description>Endpoint Control 0</description>
17110 <description>STALL Handshake (Stall)</description>
17116 <description>No Stall</description>
17121 <description>Stall Handshake</description>
17128 <description>Clear NAK (CNAK)</description>
17135 <description>No action</description>
17140 <description>Clear NAK</description>
17147 <description>Set NAK (SNAK)</description>
17154 <description>No action</description>
17159 <description>Set NAK</description>
17166 <description>Endpoint Disable (EPDis)</description>
17173 <description>No Endpoint disable</description>
17180 <description>Endpoint Enable (EPEna)</description>
17186 <description>No action</description>
17191 <description>Enable Endpoint</description>
17200 <description>Device OUT Endpoint 0 Interrupt Register</description>
17208 <description>Transfer Completed Interrupt (XferCompl)</description>
17214 <description>No Transfer Complete Interrupt</description>
17219 <description>Transfer Complete Interrupt</description>
17226 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
17232 <description>No Endpoint Disabled Interrupt</description>
17237 <description>Endpoint Disabled Interrupt</description>
17244 <description>AHB Error (AHBErr)</description>
17250 <description>No AHB Error Interrupt</description>
17255 <description>AHB Error interrupt</description>
17262 <description>SETUP Phase Done (SetUp)</description>
17268 <description>No SETUP Phase Done</description>
17273 <description>SETUP Phase Done</description>
17280 <description>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</description>
17286 <description>No OUT Token Received When Endpoint Disabled</description>
17291 <description>OUT Token Received When Endpoint Disabled</description>
17298 <description>Status Phase Received for Control Write (StsPhseRcvd)</description>
17304 <description>No Status Phase Received for Control Write</description>
17309 <description>Status Phase Received for Control Write</description>
17316 <description>Back-to-Back SETUP Packets Received (Back2BackSETup)</description>
17322 <description>No Back-to-Back SETUP Packets Received</description>
17327 <description>Back-to-Back SETUP Packets Received</description>
17334 <description>OUT Packet Error (OutPktErr)</description>
17340 <description>No OUT Packet Error</description>
17345 <description>OUT Packet Error</description>
17352 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
17358 <description>No BNA interrupt</description>
17363 <description>BNA interrupt</description>
17370 <description>Packet Drop Status (PktDrpSts)</description>
17376 <description>No interrupt</description>
17381 <description>Packet Drop Status interrupt</description>
17388 <description>NAK Interrupt (BbleErr)</description>
17394 <description>No BbleErr interrupt</description>
17399 <description>BbleErr interrupt</description>
17406 <description>NAK Interrupt (NAKInterrupt)</description>
17412 <description>No NAK interrupt</description>
17417 <description>NAK Interrupt</description>
17424 <description>NYET Interrupt (NYETIntrpt)</description>
17430 <description>No NYET interrupt</description>
17435 <description>NYET Interrupt</description>
17442 <description>Setup Packet Received</description>
17448 <description>No Setup packet received</description>
17453 <description>Setup packet received</description>
17462 <description>Device OUT Endpoint 0 Transfer Size Register</description>
17470 <description>Transfer Size (XferSize)</description>
17476 <description>Packet Count (PktCnt)</description>
17482 <description>SETUP Packet Count (SUPCnt)</description>
17488 <description>1 packet</description>
17493 <description>2 packets</description>
17498 <description>3 packets</description>
17507 <description>Device OUT Endpoint 0 DMA Address Register</description>
17515 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
17523 <description>Device Control OUT Endpoint Control Register</description>
17531 <description>Maximum Packet Size (MPS)</description>
17537 <description>USB Active Endpoint (USBActEP)</description>
17543 <description>Not Active</description>
17548 <description>USB Active Endpoint</description>
17555 <description>Endpoint Data PID (DPID)</description>
17562 <description>Endpoint Data PID not active</description>
17567 <description>Endpoint Data PID active</description>
17574 <description>NAK Status (NAKSts)</description>
17581 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
17586 … <description>The core is transmitting NAK handshakes on this endpoint</description>
17593 <description>Endpoint Type (EPType)</description>
17599 <description>Control</description>
17604 <description>Isochronous</description>
17609 <description>Bulk</description>
17614 <description>Interrupt</description>
17621 <description>STALL Handshake (Stall)</description>
17627 <description>STALL All non-active tokens</description>
17632 <description>STALL All Active Tokens</description>
17645 <description>No Clear NAK</description>
17650 <description>Clear NAK</description>
17657 <description>Set NAK (SNAK)</description>
17664 <description>No Set NAK</description>
17669 <description>Set NAK</description>
17676 <description>Set DATA0 PID (SetD0PID)</description>
17683 <description>Disables Set DATA0 PID or Do not force Even Frame</description>
17688 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
17695 <description>Set DATA1 PID (SetD1PID)</description>
17702 <description>Disables Set DATA1 PID or Do not force Odd Frame</description>
17707 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
17714 <description>Endpoint Disable (EPDis)</description>
17720 <description>No Action</description>
17725 <description>Disable Endpoint</description>
17732 <description>Endpoint Enable (EPEna)</description>
17738 <description>No Action</description>
17743 <description>Enable Endpoint</description>
17752 <description>Device OUT Endpoint Interrupt Register</description>
17760 <description>Transfer Completed Interrupt (XferCompl)</description>
17766 <description>No Transfer Complete Interrupt</description>
17771 <description>Transfer Complete Interrupt</description>
17778 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
17784 <description>No Endpoint Disabled Interrupt</description>
17789 <description>Endpoint Disabled Interrupt</description>
17796 <description>AHB Error (AHBErr)</description>
17802 <description>No AHB Error Interrupt</description>
17807 <description>AHB Error interrupt</description>
17814 <description>SETUP Phase Done (SetUp)</description>
17820 <description>No SETUP Phase Done</description>
17825 <description>SETUP Phase Done</description>
17832 <description>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</description>
17838 <description>No OUT Token Received When Endpoint Disabled</description>
17843 <description>OUT Token Received When Endpoint Disabled</description>
17850 <description>Status Phase Received for Control Write (StsPhseRcvd)</description>
17856 <description>No Status Phase Received for Control Write</description>
17861 <description>Status Phase Received for Control Write</description>
17868 <description>Back-to-Back SETUP Packets Received (Back2BackSETup)</description>
17874 <description>No Back-to-Back SETUP Packets Received</description>
17879 <description>Back-to-Back SETUP Packets Received</description>
17886 <description>OUT Packet Error (OutPktErr)</description>
17892 <description>No OUT Packet Error</description>
17897 <description>OUT Packet Error</description>
17904 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
17910 <description>No BNA interrupt</description>
17915 <description>BNA interrupt</description>
17922 <description>Packet Drop Status (PktDrpSts)</description>
17928 <description>No interrupt</description>
17933 <description>Packet Drop Status interrupt</description>
17940 <description>NAK Interrupt (BbleErr)</description>
17946 <description>No BbleErr interrupt</description>
17951 <description>BbleErr interrupt</description>
17958 <description>NAK Interrupt (NAKInterrupt)</description>
17964 <description>No NAK interrupt</description>
17969 <description>NAK Interrupt</description>
17976 <description>NYET Interrupt (NYETIntrpt)</description>
17982 <description>No NYET interrupt</description>
17987 <description>NYET Interrupt</description>
17994 <description>Setup Packet Received</description>
18000 <description>No Setup packet received</description>
18005 <description>Setup packet received</description>
18014 <description>Device OUT Endpoint Transfer Size Register</description>
18022 <description>Transfer Size (XferSize)</description>
18028 <description>Packet Count (PktCnt)</description>
18034 <description>RxDPID</description>
18041 <description>DATA0</description>
18046 <description>DATA2 or 1 packet</description>
18051 <description>DATA1 or 2 packets</description>
18056 <description>MDATA or 3 packets</description>
18065 <description>Device OUT Endpoint DMA Address Register</description>
18073 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
18081 <description>Device Control OUT Endpoint Control Register</description>
18089 <description>Maximum Packet Size (MPS)</description>
18095 <description>USB Active Endpoint (USBActEP)</description>
18101 <description>Not Active</description>
18106 <description>USB Active Endpoint</description>
18113 <description>Endpoint Data PID (DPID)</description>
18120 <description>Endpoint Data PID not active</description>
18125 <description>Endpoint Data PID active</description>
18132 <description>NAK Status (NAKSts)</description>
18139 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
18144 … <description>The core is transmitting NAK handshakes on this endpoint</description>
18151 <description>Endpoint Type (EPType)</description>
18157 <description>Control</description>
18162 <description>Isochronous</description>
18167 <description>Bulk</description>
18172 <description>Interrupt</description>
18179 <description>STALL Handshake (Stall)</description>
18185 <description>STALL All non-active tokens</description>
18190 <description>STALL All Active Tokens</description>
18203 <description>No Clear NAK</description>
18208 <description>Clear NAK</description>
18215 <description>Set NAK (SNAK)</description>
18222 <description>No Set NAK</description>
18227 <description>Set NAK</description>
18234 <description>Set DATA0 PID (SetD0PID)</description>
18241 <description>Disables Set DATA0 PID or Do not force Even Frame</description>
18246 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
18253 <description>Set DATA1 PID (SetD1PID)</description>
18260 <description>Disables Set DATA1 PID or Do not force Odd Frame</description>
18265 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
18272 <description>Endpoint Disable (EPDis)</description>
18278 <description>No Action</description>
18283 <description>Disable Endpoint</description>
18290 <description>Endpoint Enable (EPEna)</description>
18296 <description>No Action</description>
18301 <description>Enable Endpoint</description>
18310 <description>Device OUT Endpoint Interrupt Register</description>
18318 <description>Transfer Completed Interrupt (XferCompl)</description>
18324 <description>No Transfer Complete Interrupt</description>
18329 <description>Transfer Complete Interrupt</description>
18336 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
18342 <description>No Endpoint Disabled Interrupt</description>
18347 <description>Endpoint Disabled Interrupt</description>
18354 <description>AHB Error (AHBErr)</description>
18360 <description>No AHB Error Interrupt</description>
18365 <description>AHB Error interrupt</description>
18372 <description>SETUP Phase Done (SetUp)</description>
18378 <description>No SETUP Phase Done</description>
18383 <description>SETUP Phase Done</description>
18390 <description>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</description>
18396 <description>No OUT Token Received When Endpoint Disabled</description>
18401 <description>OUT Token Received When Endpoint Disabled</description>
18408 <description>Status Phase Received for Control Write (StsPhseRcvd)</description>
18414 <description>No Status Phase Received for Control Write</description>
18419 <description>Status Phase Received for Control Write</description>
18426 <description>Back-to-Back SETUP Packets Received (Back2BackSETup)</description>
18432 <description>No Back-to-Back SETUP Packets Received</description>
18437 <description>Back-to-Back SETUP Packets Received</description>
18444 <description>OUT Packet Error (OutPktErr)</description>
18450 <description>No OUT Packet Error</description>
18455 <description>OUT Packet Error</description>
18462 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
18468 <description>No BNA interrupt</description>
18473 <description>BNA interrupt</description>
18480 <description>Packet Drop Status (PktDrpSts)</description>
18486 <description>No interrupt</description>
18491 <description>Packet Drop Status interrupt</description>
18498 <description>NAK Interrupt (BbleErr)</description>
18504 <description>No BbleErr interrupt</description>
18509 <description>BbleErr interrupt</description>
18516 <description>NAK Interrupt (NAKInterrupt)</description>
18522 <description>No NAK interrupt</description>
18527 <description>NAK Interrupt</description>
18534 <description>NYET Interrupt (NYETIntrpt)</description>
18540 <description>No NYET interrupt</description>
18545 <description>NYET Interrupt</description>
18552 <description>Setup Packet Received</description>
18558 <description>No Setup packet received</description>
18563 <description>Setup packet received</description>
18572 <description>Device OUT Endpoint Transfer Size Register</description>
18580 <description>Transfer Size (XferSize)</description>
18586 <description>Packet Count (PktCnt)</description>
18592 <description>RxDPID</description>
18599 <description>DATA0</description>
18604 <description>DATA2 or 1 packet</description>
18609 <description>DATA1 or 2 packets</description>
18614 <description>MDATA or 3 packets</description>
18623 <description>Device OUT Endpoint DMA Address Register</description>
18631 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
18639 <description>Device Control OUT Endpoint Control Register</description>
18647 <description>Maximum Packet Size (MPS)</description>
18653 <description>USB Active Endpoint (USBActEP)</description>
18659 <description>Not Active</description>
18664 <description>USB Active Endpoint</description>
18671 <description>Endpoint Data PID (DPID)</description>
18678 <description>Endpoint Data PID not active</description>
18683 <description>Endpoint Data PID active</description>
18690 <description>NAK Status (NAKSts)</description>
18697 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
18702 … <description>The core is transmitting NAK handshakes on this endpoint</description>
18709 <description>Endpoint Type (EPType)</description>
18715 <description>Control</description>
18720 <description>Isochronous</description>
18725 <description>Bulk</description>
18730 <description>Interrupt</description>
18737 <description>STALL Handshake (Stall)</description>
18743 <description>STALL All non-active tokens</description>
18748 <description>STALL All Active Tokens</description>
18761 <description>No Clear NAK</description>
18766 <description>Clear NAK</description>
18773 <description>Set NAK (SNAK)</description>
18780 <description>No Set NAK</description>
18785 <description>Set NAK</description>
18792 <description>Set DATA0 PID (SetD0PID)</description>
18799 <description>Disables Set DATA0 PID or Do not force Even Frame</description>
18804 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
18811 <description>Set DATA1 PID (SetD1PID)</description>
18818 <description>Disables Set DATA1 PID or Do not force Odd Frame</description>
18823 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
18830 <description>Endpoint Disable (EPDis)</description>
18836 <description>No Action</description>
18841 <description>Disable Endpoint</description>
18848 <description>Endpoint Enable (EPEna)</description>
18854 <description>No Action</description>
18859 <description>Enable Endpoint</description>
18868 <description>Device OUT Endpoint Interrupt Register</description>
18876 <description>Transfer Completed Interrupt (XferCompl)</description>
18882 <description>No Transfer Complete Interrupt</description>
18887 <description>Transfer Complete Interrupt</description>
18894 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
18900 <description>No Endpoint Disabled Interrupt</description>
18905 <description>Endpoint Disabled Interrupt</description>
18912 <description>AHB Error (AHBErr)</description>
18918 <description>No AHB Error Interrupt</description>
18923 <description>AHB Error interrupt</description>
18930 <description>SETUP Phase Done (SetUp)</description>
18936 <description>No SETUP Phase Done</description>
18941 <description>SETUP Phase Done</description>
18948 <description>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</description>
18954 <description>No OUT Token Received When Endpoint Disabled</description>
18959 <description>OUT Token Received When Endpoint Disabled</description>
18966 <description>Status Phase Received for Control Write (StsPhseRcvd)</description>
18972 <description>No Status Phase Received for Control Write</description>
18977 <description>Status Phase Received for Control Write</description>
18984 <description>Back-to-Back SETUP Packets Received (Back2BackSETup)</description>
18990 <description>No Back-to-Back SETUP Packets Received</description>
18995 <description>Back-to-Back SETUP Packets Received</description>
19002 <description>OUT Packet Error (OutPktErr)</description>
19008 <description>No OUT Packet Error</description>
19013 <description>OUT Packet Error</description>
19020 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
19026 <description>No BNA interrupt</description>
19031 <description>BNA interrupt</description>
19038 <description>Packet Drop Status (PktDrpSts)</description>
19044 <description>No interrupt</description>
19049 <description>Packet Drop Status interrupt</description>
19056 <description>NAK Interrupt (BbleErr)</description>
19062 <description>No BbleErr interrupt</description>
19067 <description>BbleErr interrupt</description>
19074 <description>NAK Interrupt (NAKInterrupt)</description>
19080 <description>No NAK interrupt</description>
19085 <description>NAK Interrupt</description>
19092 <description>NYET Interrupt (NYETIntrpt)</description>
19098 <description>No NYET interrupt</description>
19103 <description>NYET Interrupt</description>
19110 <description>Setup Packet Received</description>
19116 <description>No Setup packet received</description>
19121 <description>Setup packet received</description>
19130 <description>Device OUT Endpoint Transfer Size Register</description>
19138 <description>Transfer Size (XferSize)</description>
19144 <description>Packet Count (PktCnt)</description>
19150 <description>RxDPID</description>
19157 <description>DATA0</description>
19162 <description>DATA2 or 1 packet</description>
19167 <description>DATA1 or 2 packets</description>
19172 <description>MDATA or 3 packets</description>
19181 <description>Device OUT Endpoint DMA Address Register</description>
19189 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
19197 <description>Device Control OUT Endpoint Control Register</description>
19205 <description>Maximum Packet Size (MPS)</description>
19211 <description>USB Active Endpoint (USBActEP)</description>
19217 <description>Not Active</description>
19222 <description>USB Active Endpoint</description>
19229 <description>Endpoint Data PID (DPID)</description>
19236 <description>Endpoint Data PID not active</description>
19241 <description>Endpoint Data PID active</description>
19248 <description>NAK Status (NAKSts)</description>
19255 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
19260 … <description>The core is transmitting NAK handshakes on this endpoint</description>
19267 <description>Endpoint Type (EPType)</description>
19273 <description>Control</description>
19278 <description>Isochronous</description>
19283 <description>Bulk</description>
19288 <description>Interrupt</description>
19295 <description>STALL Handshake (Stall)</description>
19301 <description>STALL All non-active tokens</description>
19306 <description>STALL All Active Tokens</description>
19319 <description>No Clear NAK</description>
19324 <description>Clear NAK</description>
19331 <description>Set NAK (SNAK)</description>
19338 <description>No Set NAK</description>
19343 <description>Set NAK</description>
19350 <description>Set DATA0 PID (SetD0PID)</description>
19357 <description>Disables Set DATA0 PID or Do not force Even Frame</description>
19362 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
19369 <description>Set DATA1 PID (SetD1PID)</description>
19376 <description>Disables Set DATA1 PID or Do not force Odd Frame</description>
19381 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
19388 <description>Endpoint Disable (EPDis)</description>
19394 <description>No Action</description>
19399 <description>Disable Endpoint</description>
19406 <description>Endpoint Enable (EPEna)</description>
19412 <description>No Action</description>
19417 <description>Enable Endpoint</description>
19426 <description>Device OUT Endpoint Interrupt Register</description>
19434 <description>Transfer Completed Interrupt (XferCompl)</description>
19440 <description>No Transfer Complete Interrupt</description>
19445 <description>Transfer Complete Interrupt</description>
19452 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
19458 <description>No Endpoint Disabled Interrupt</description>
19463 <description>Endpoint Disabled Interrupt</description>
19470 <description>AHB Error (AHBErr)</description>
19476 <description>No AHB Error Interrupt</description>
19481 <description>AHB Error interrupt</description>
19488 <description>SETUP Phase Done (SetUp)</description>
19494 <description>No SETUP Phase Done</description>
19499 <description>SETUP Phase Done</description>
19506 <description>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</description>
19512 <description>No OUT Token Received When Endpoint Disabled</description>
19517 <description>OUT Token Received When Endpoint Disabled</description>
19524 <description>Status Phase Received for Control Write (StsPhseRcvd)</description>
19530 <description>No Status Phase Received for Control Write</description>
19535 <description>Status Phase Received for Control Write</description>
19542 <description>Back-to-Back SETUP Packets Received (Back2BackSETup)</description>
19548 <description>No Back-to-Back SETUP Packets Received</description>
19553 <description>Back-to-Back SETUP Packets Received</description>
19560 <description>OUT Packet Error (OutPktErr)</description>
19566 <description>No OUT Packet Error</description>
19571 <description>OUT Packet Error</description>
19578 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
19584 <description>No BNA interrupt</description>
19589 <description>BNA interrupt</description>
19596 <description>Packet Drop Status (PktDrpSts)</description>
19602 <description>No interrupt</description>
19607 <description>Packet Drop Status interrupt</description>
19614 <description>NAK Interrupt (BbleErr)</description>
19620 <description>No BbleErr interrupt</description>
19625 <description>BbleErr interrupt</description>
19632 <description>NAK Interrupt (NAKInterrupt)</description>
19638 <description>No NAK interrupt</description>
19643 <description>NAK Interrupt</description>
19650 <description>NYET Interrupt (NYETIntrpt)</description>
19656 <description>No NYET interrupt</description>
19661 <description>NYET Interrupt</description>
19668 <description>Setup Packet Received</description>
19674 <description>No Setup packet received</description>
19679 <description>Setup packet received</description>
19688 <description>Device OUT Endpoint Transfer Size Register</description>
19696 <description>Transfer Size (XferSize)</description>
19702 <description>Packet Count (PktCnt)</description>
19708 <description>RxDPID</description>
19715 <description>DATA0</description>
19720 <description>DATA2 or 1 packet</description>
19725 <description>DATA1 or 2 packets</description>
19730 <description>MDATA or 3 packets</description>
19739 <description>Device OUT Endpoint DMA Address Register</description>
19747 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
19755 <description>Device Control OUT Endpoint Control Register</description>
19763 <description>Maximum Packet Size (MPS)</description>
19769 <description>USB Active Endpoint (USBActEP)</description>
19775 <description>Not Active</description>
19780 <description>USB Active Endpoint</description>
19787 <description>Endpoint Data PID (DPID)</description>
19794 <description>Endpoint Data PID not active</description>
19799 <description>Endpoint Data PID active</description>
19806 <description>NAK Status (NAKSts)</description>
19813 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
19818 … <description>The core is transmitting NAK handshakes on this endpoint</description>
19825 <description>Endpoint Type (EPType)</description>
19831 <description>Control</description>
19836 <description>Isochronous</description>
19841 <description>Bulk</description>
19846 <description>Interrupt</description>
19853 <description>STALL Handshake (Stall)</description>
19859 <description>STALL All non-active tokens</description>
19864 <description>STALL All Active Tokens</description>
19877 <description>No Clear NAK</description>
19882 <description>Clear NAK</description>
19889 <description>Set NAK (SNAK)</description>
19896 <description>No Set NAK</description>
19901 <description>Set NAK</description>
19908 <description>Set DATA0 PID (SetD0PID)</description>
19915 <description>Disables Set DATA0 PID or Do not force Even Frame</description>
19920 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
19927 <description>Set DATA1 PID (SetD1PID)</description>
19934 <description>Disables Set DATA1 PID or Do not force Odd Frame</description>
19939 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
19946 <description>Endpoint Disable (EPDis)</description>
19952 <description>No Action</description>
19957 <description>Disable Endpoint</description>
19964 <description>Endpoint Enable (EPEna)</description>
19970 <description>No Action</description>
19975 <description>Enable Endpoint</description>
19984 <description>Device OUT Endpoint Interrupt Register</description>
19992 <description>Transfer Completed Interrupt (XferCompl)</description>
19998 <description>No Transfer Complete Interrupt</description>
20003 <description>Transfer Complete Interrupt</description>
20010 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
20016 <description>No Endpoint Disabled Interrupt</description>
20021 <description>Endpoint Disabled Interrupt</description>
20028 <description>AHB Error (AHBErr)</description>
20034 <description>No AHB Error Interrupt</description>
20039 <description>AHB Error interrupt</description>
20046 <description>SETUP Phase Done (SetUp)</description>
20052 <description>No SETUP Phase Done</description>
20057 <description>SETUP Phase Done</description>
20064 <description>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</description>
20070 <description>No OUT Token Received When Endpoint Disabled</description>
20075 <description>OUT Token Received When Endpoint Disabled</description>
20082 <description>Status Phase Received for Control Write (StsPhseRcvd)</description>
20088 <description>No Status Phase Received for Control Write</description>
20093 <description>Status Phase Received for Control Write</description>
20100 <description>Back-to-Back SETUP Packets Received (Back2BackSETup)</description>
20106 <description>No Back-to-Back SETUP Packets Received</description>
20111 <description>Back-to-Back SETUP Packets Received</description>
20118 <description>OUT Packet Error (OutPktErr)</description>
20124 <description>No OUT Packet Error</description>
20129 <description>OUT Packet Error</description>
20136 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
20142 <description>No BNA interrupt</description>
20147 <description>BNA interrupt</description>
20154 <description>Packet Drop Status (PktDrpSts)</description>
20160 <description>No interrupt</description>
20165 <description>Packet Drop Status interrupt</description>
20172 <description>NAK Interrupt (BbleErr)</description>
20178 <description>No BbleErr interrupt</description>
20183 <description>BbleErr interrupt</description>
20190 <description>NAK Interrupt (NAKInterrupt)</description>
20196 <description>No NAK interrupt</description>
20201 <description>NAK Interrupt</description>
20208 <description>NYET Interrupt (NYETIntrpt)</description>
20214 <description>No NYET interrupt</description>
20219 <description>NYET Interrupt</description>
20226 <description>Setup Packet Received</description>
20232 <description>No Setup packet received</description>
20237 <description>Setup packet received</description>
20246 <description>Device OUT Endpoint Transfer Size Register</description>
20254 <description>Transfer Size (XferSize)</description>
20260 <description>Packet Count (PktCnt)</description>
20266 <description>RxDPID</description>
20273 <description>DATA0</description>
20278 <description>DATA2 or 1 packet</description>
20283 <description>DATA1 or 2 packets</description>
20288 <description>MDATA or 3 packets</description>
20297 <description>Device OUT Endpoint DMA Address Register</description>
20305 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
20313 <description>Device Control OUT Endpoint Control Register</description>
20321 <description>Maximum Packet Size (MPS)</description>
20327 <description>USB Active Endpoint (USBActEP)</description>
20333 <description>Not Active</description>
20338 <description>USB Active Endpoint</description>
20345 <description>Endpoint Data PID (DPID)</description>
20352 <description>Endpoint Data PID not active</description>
20357 <description>Endpoint Data PID active</description>
20364 <description>NAK Status (NAKSts)</description>
20371 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
20376 … <description>The core is transmitting NAK handshakes on this endpoint</description>
20383 <description>Endpoint Type (EPType)</description>
20389 <description>Control</description>
20394 <description>Isochronous</description>
20399 <description>Bulk</description>
20404 <description>Interrupt</description>
20411 <description>STALL Handshake (Stall)</description>
20417 <description>STALL All non-active tokens</description>
20422 <description>STALL All Active Tokens</description>
20435 <description>No Clear NAK</description>
20440 <description>Clear NAK</description>
20447 <description>Set NAK (SNAK)</description>
20454 <description>No Set NAK</description>
20459 <description>Set NAK</description>
20466 <description>Set DATA0 PID (SetD0PID)</description>
20473 <description>Disables Set DATA0 PID or Do not force Even Frame</description>
20478 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
20485 <description>Set DATA1 PID (SetD1PID)</description>
20492 <description>Disables Set DATA1 PID or Do not force Odd Frame</description>
20497 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
20504 <description>Endpoint Disable (EPDis)</description>
20510 <description>No Action</description>
20515 <description>Disable Endpoint</description>
20522 <description>Endpoint Enable (EPEna)</description>
20528 <description>No Action</description>
20533 <description>Enable Endpoint</description>
20542 <description>Device OUT Endpoint Interrupt Register</description>
20550 <description>Transfer Completed Interrupt (XferCompl)</description>
20556 <description>No Transfer Complete Interrupt</description>
20561 <description>Transfer Complete Interrupt</description>
20568 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
20574 <description>No Endpoint Disabled Interrupt</description>
20579 <description>Endpoint Disabled Interrupt</description>
20586 <description>AHB Error (AHBErr)</description>
20592 <description>No AHB Error Interrupt</description>
20597 <description>AHB Error interrupt</description>
20604 <description>SETUP Phase Done (SetUp)</description>
20610 <description>No SETUP Phase Done</description>
20615 <description>SETUP Phase Done</description>
20622 <description>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</description>
20628 <description>No OUT Token Received When Endpoint Disabled</description>
20633 <description>OUT Token Received When Endpoint Disabled</description>
20640 <description>Status Phase Received for Control Write (StsPhseRcvd)</description>
20646 <description>No Status Phase Received for Control Write</description>
20651 <description>Status Phase Received for Control Write</description>
20658 <description>Back-to-Back SETUP Packets Received (Back2BackSETup)</description>
20664 <description>No Back-to-Back SETUP Packets Received</description>
20669 <description>Back-to-Back SETUP Packets Received</description>
20676 <description>OUT Packet Error (OutPktErr)</description>
20682 <description>No OUT Packet Error</description>
20687 <description>OUT Packet Error</description>
20694 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
20700 <description>No BNA interrupt</description>
20705 <description>BNA interrupt</description>
20712 <description>Packet Drop Status (PktDrpSts)</description>
20718 <description>No interrupt</description>
20723 <description>Packet Drop Status interrupt</description>
20730 <description>NAK Interrupt (BbleErr)</description>
20736 <description>No BbleErr interrupt</description>
20741 <description>BbleErr interrupt</description>
20748 <description>NAK Interrupt (NAKInterrupt)</description>
20754 <description>No NAK interrupt</description>
20759 <description>NAK Interrupt</description>
20766 <description>NYET Interrupt (NYETIntrpt)</description>
20772 <description>No NYET interrupt</description>
20777 <description>NYET Interrupt</description>
20784 <description>Setup Packet Received</description>
20790 <description>No Setup packet received</description>
20795 <description>Setup packet received</description>
20804 <description>Device OUT Endpoint Transfer Size Register</description>
20812 <description>Transfer Size (XferSize)</description>
20818 <description>Packet Count (PktCnt)</description>
20824 <description>RxDPID</description>
20831 <description>DATA0</description>
20836 <description>DATA2 or 1 packet</description>
20841 <description>DATA1 or 2 packets</description>
20846 <description>MDATA or 3 packets</description>
20855 <description>Device OUT Endpoint DMA Address Register</description>
20863 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
20871 <description>Device Control OUT Endpoint Control Register</description>
20879 <description>Maximum Packet Size (MPS)</description>
20885 <description>USB Active Endpoint (USBActEP)</description>
20891 <description>Not Active</description>
20896 <description>USB Active Endpoint</description>
20903 <description>Endpoint Data PID (DPID)</description>
20910 <description>Endpoint Data PID not active</description>
20915 <description>Endpoint Data PID active</description>
20922 <description>NAK Status (NAKSts)</description>
20929 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
20934 … <description>The core is transmitting NAK handshakes on this endpoint</description>
20941 <description>Endpoint Type (EPType)</description>
20947 <description>Control</description>
20952 <description>Isochronous</description>
20957 <description>Bulk</description>
20962 <description>Interrupt</description>
20969 <description>STALL Handshake (Stall)</description>
20975 <description>STALL All non-active tokens</description>
20980 <description>STALL All Active Tokens</description>
20993 <description>No Clear NAK</description>
20998 <description>Clear NAK</description>
21005 <description>Set NAK (SNAK)</description>
21012 <description>No Set NAK</description>
21017 <description>Set NAK</description>
21024 <description>Set DATA0 PID (SetD0PID)</description>
21031 <description>Disables Set DATA0 PID or Do not force Even Frame</description>
21036 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
21043 <description>Set DATA1 PID (SetD1PID)</description>
21050 <description>Disables Set DATA1 PID or Do not force Odd Frame</description>
21055 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
21062 <description>Endpoint Disable (EPDis)</description>
21068 <description>No Action</description>
21073 <description>Disable Endpoint</description>
21080 <description>Endpoint Enable (EPEna)</description>
21086 <description>No Action</description>
21091 <description>Enable Endpoint</description>
21100 <description>Device OUT Endpoint Interrupt Register</description>
21108 <description>Transfer Completed Interrupt (XferCompl)</description>
21114 <description>No Transfer Complete Interrupt</description>
21119 <description>Transfer Complete Interrupt</description>
21126 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
21132 <description>No Endpoint Disabled Interrupt</description>
21137 <description>Endpoint Disabled Interrupt</description>
21144 <description>AHB Error (AHBErr)</description>
21150 <description>No AHB Error Interrupt</description>
21155 <description>AHB Error interrupt</description>
21162 <description>SETUP Phase Done (SetUp)</description>
21168 <description>No SETUP Phase Done</description>
21173 <description>SETUP Phase Done</description>
21180 <description>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</description>
21186 <description>No OUT Token Received When Endpoint Disabled</description>
21191 <description>OUT Token Received When Endpoint Disabled</description>
21198 <description>Status Phase Received for Control Write (StsPhseRcvd)</description>
21204 <description>No Status Phase Received for Control Write</description>
21209 <description>Status Phase Received for Control Write</description>
21216 <description>Back-to-Back SETUP Packets Received (Back2BackSETup)</description>
21222 <description>No Back-to-Back SETUP Packets Received</description>
21227 <description>Back-to-Back SETUP Packets Received</description>
21234 <description>OUT Packet Error (OutPktErr)</description>
21240 <description>No OUT Packet Error</description>
21245 <description>OUT Packet Error</description>
21252 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
21258 <description>No BNA interrupt</description>
21263 <description>BNA interrupt</description>
21270 <description>Packet Drop Status (PktDrpSts)</description>
21276 <description>No interrupt</description>
21281 <description>Packet Drop Status interrupt</description>
21288 <description>NAK Interrupt (BbleErr)</description>
21294 <description>No BbleErr interrupt</description>
21299 <description>BbleErr interrupt</description>
21306 <description>NAK Interrupt (NAKInterrupt)</description>
21312 <description>No NAK interrupt</description>
21317 <description>NAK Interrupt</description>
21324 <description>NYET Interrupt (NYETIntrpt)</description>
21330 <description>No NYET interrupt</description>
21335 <description>NYET Interrupt</description>
21342 <description>Setup Packet Received</description>
21348 <description>No Setup packet received</description>
21353 <description>Setup packet received</description>
21362 <description>Device OUT Endpoint Transfer Size Register</description>
21370 <description>Transfer Size (XferSize)</description>
21376 <description>Packet Count (PktCnt)</description>
21382 <description>RxDPID</description>
21389 <description>DATA0</description>
21394 <description>DATA2 or 1 packet</description>
21399 <description>DATA1 or 2 packets</description>
21404 <description>MDATA or 3 packets</description>
21413 <description>Device OUT Endpoint DMA Address Register</description>
21421 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
21429 <description>Device Control OUT Endpoint Control Register</description>
21437 <description>Maximum Packet Size (MPS)</description>
21443 <description>USB Active Endpoint (USBActEP)</description>
21449 <description>Not Active</description>
21454 <description>USB Active Endpoint</description>
21461 <description>Endpoint Data PID (DPID)</description>
21468 <description>Endpoint Data PID not active</description>
21473 <description>Endpoint Data PID active</description>
21480 <description>NAK Status (NAKSts)</description>
21487 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
21492 … <description>The core is transmitting NAK handshakes on this endpoint</description>
21499 <description>Endpoint Type (EPType)</description>
21505 <description>Control</description>
21510 <description>Isochronous</description>
21515 <description>Bulk</description>
21520 <description>Interrupt</description>
21527 <description>STALL Handshake (Stall)</description>
21533 <description>STALL All non-active tokens</description>
21538 <description>STALL All Active Tokens</description>
21551 <description>No Clear NAK</description>
21556 <description>Clear NAK</description>
21563 <description>Set NAK (SNAK)</description>
21570 <description>No Set NAK</description>
21575 <description>Set NAK</description>
21582 <description>Set DATA0 PID (SetD0PID)</description>
21589 <description>Disables Set DATA0 PID or Do not force Even Frame</description>
21594 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
21601 <description>Set DATA1 PID (SetD1PID)</description>
21608 <description>Disables Set DATA1 PID or Do not force Odd Frame</description>
21613 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
21620 <description>Endpoint Disable (EPDis)</description>
21626 <description>No Action</description>
21631 <description>Disable Endpoint</description>
21638 <description>Endpoint Enable (EPEna)</description>
21644 <description>No Action</description>
21649 <description>Enable Endpoint</description>
21658 <description>Device OUT Endpoint Interrupt Register</description>
21666 <description>Transfer Completed Interrupt (XferCompl)</description>
21672 <description>No Transfer Complete Interrupt</description>
21677 <description>Transfer Complete Interrupt</description>
21684 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
21690 <description>No Endpoint Disabled Interrupt</description>
21695 <description>Endpoint Disabled Interrupt</description>
21702 <description>AHB Error (AHBErr)</description>
21708 <description>No AHB Error Interrupt</description>
21713 <description>AHB Error interrupt</description>
21720 <description>SETUP Phase Done (SetUp)</description>
21726 <description>No SETUP Phase Done</description>
21731 <description>SETUP Phase Done</description>
21738 <description>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</description>
21744 <description>No OUT Token Received When Endpoint Disabled</description>
21749 <description>OUT Token Received When Endpoint Disabled</description>
21756 <description>Status Phase Received for Control Write (StsPhseRcvd)</description>
21762 <description>No Status Phase Received for Control Write</description>
21767 <description>Status Phase Received for Control Write</description>
21774 <description>Back-to-Back SETUP Packets Received (Back2BackSETup)</description>
21780 <description>No Back-to-Back SETUP Packets Received</description>
21785 <description>Back-to-Back SETUP Packets Received</description>
21792 <description>OUT Packet Error (OutPktErr)</description>
21798 <description>No OUT Packet Error</description>
21803 <description>OUT Packet Error</description>
21810 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
21816 <description>No BNA interrupt</description>
21821 <description>BNA interrupt</description>
21828 <description>Packet Drop Status (PktDrpSts)</description>
21834 <description>No interrupt</description>
21839 <description>Packet Drop Status interrupt</description>
21846 <description>NAK Interrupt (BbleErr)</description>
21852 <description>No BbleErr interrupt</description>
21857 <description>BbleErr interrupt</description>
21864 <description>NAK Interrupt (NAKInterrupt)</description>
21870 <description>No NAK interrupt</description>
21875 <description>NAK Interrupt</description>
21882 <description>NYET Interrupt (NYETIntrpt)</description>
21888 <description>No NYET interrupt</description>
21893 <description>NYET Interrupt</description>
21900 <description>Setup Packet Received</description>
21906 <description>No Setup packet received</description>
21911 <description>Setup packet received</description>
21920 <description>Device OUT Endpoint Transfer Size Register</description>
21928 <description>Transfer Size (XferSize)</description>
21934 <description>Packet Count (PktCnt)</description>
21940 <description>RxDPID</description>
21947 <description>DATA0</description>
21952 <description>DATA2 or 1 packet</description>
21957 <description>DATA1 or 2 packets</description>
21962 <description>MDATA or 3 packets</description>
21971 <description>Device OUT Endpoint DMA Address Register</description>
21979 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
21987 <description>Device Control OUT Endpoint Control Register</description>
21995 <description>Maximum Packet Size (MPS)</description>
22001 <description>USB Active Endpoint (USBActEP)</description>
22007 <description>Not Active</description>
22012 <description>USB Active Endpoint</description>
22019 <description>Endpoint Data PID (DPID)</description>
22026 <description>Endpoint Data PID not active</description>
22031 <description>Endpoint Data PID active</description>
22038 <description>NAK Status (NAKSts)</description>
22045 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
22050 … <description>The core is transmitting NAK handshakes on this endpoint</description>
22057 <description>Endpoint Type (EPType)</description>
22063 <description>Control</description>
22068 <description>Isochronous</description>
22073 <description>Bulk</description>
22078 <description>Interrupt</description>
22085 <description>STALL Handshake (Stall)</description>
22091 <description>STALL All non-active tokens</description>
22096 <description>STALL All Active Tokens</description>
22109 <description>No Clear NAK</description>
22114 <description>Clear NAK</description>
22121 <description>Set NAK (SNAK)</description>
22128 <description>No Set NAK</description>
22133 <description>Set NAK</description>
22140 <description>Set DATA0 PID (SetD0PID)</description>
22147 <description>Disables Set DATA0 PID or Do not force Even Frame</description>
22152 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
22159 <description>Set DATA1 PID (SetD1PID)</description>
22166 <description>Disables Set DATA1 PID or Do not force Odd Frame</description>
22171 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
22178 <description>Endpoint Disable (EPDis)</description>
22184 <description>No Action</description>
22189 <description>Disable Endpoint</description>
22196 <description>Endpoint Enable (EPEna)</description>
22202 <description>No Action</description>
22207 <description>Enable Endpoint</description>
22216 <description>Device OUT Endpoint Interrupt Register</description>
22224 <description>Transfer Completed Interrupt (XferCompl)</description>
22230 <description>No Transfer Complete Interrupt</description>
22235 <description>Transfer Complete Interrupt</description>
22242 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
22248 <description>No Endpoint Disabled Interrupt</description>
22253 <description>Endpoint Disabled Interrupt</description>
22260 <description>AHB Error (AHBErr)</description>
22266 <description>No AHB Error Interrupt</description>
22271 <description>AHB Error interrupt</description>
22278 <description>SETUP Phase Done (SetUp)</description>
22284 <description>No SETUP Phase Done</description>
22289 <description>SETUP Phase Done</description>
22296 <description>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</description>
22302 <description>No OUT Token Received When Endpoint Disabled</description>
22307 <description>OUT Token Received When Endpoint Disabled</description>
22314 <description>Status Phase Received for Control Write (StsPhseRcvd)</description>
22320 <description>No Status Phase Received for Control Write</description>
22325 <description>Status Phase Received for Control Write</description>
22332 <description>Back-to-Back SETUP Packets Received (Back2BackSETup)</description>
22338 <description>No Back-to-Back SETUP Packets Received</description>
22343 <description>Back-to-Back SETUP Packets Received</description>
22350 <description>OUT Packet Error (OutPktErr)</description>
22356 <description>No OUT Packet Error</description>
22361 <description>OUT Packet Error</description>
22368 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
22374 <description>No BNA interrupt</description>
22379 <description>BNA interrupt</description>
22386 <description>Packet Drop Status (PktDrpSts)</description>
22392 <description>No interrupt</description>
22397 <description>Packet Drop Status interrupt</description>
22404 <description>NAK Interrupt (BbleErr)</description>
22410 <description>No BbleErr interrupt</description>
22415 <description>BbleErr interrupt</description>
22422 <description>NAK Interrupt (NAKInterrupt)</description>
22428 <description>No NAK interrupt</description>
22433 <description>NAK Interrupt</description>
22440 <description>NYET Interrupt (NYETIntrpt)</description>
22446 <description>No NYET interrupt</description>
22451 <description>NYET Interrupt</description>
22458 <description>Setup Packet Received</description>
22464 <description>No Setup packet received</description>
22469 <description>Setup packet received</description>
22478 <description>Device OUT Endpoint Transfer Size Register</description>
22486 <description>Transfer Size (XferSize)</description>
22492 <description>Packet Count (PktCnt)</description>
22498 <description>RxDPID</description>
22505 <description>DATA0</description>
22510 <description>DATA2 or 1 packet</description>
22515 <description>DATA1 or 2 packets</description>
22520 <description>MDATA or 3 packets</description>
22529 <description>Device OUT Endpoint DMA Address Register</description>
22537 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
22545 <description>Power and Clock Gating Control Register</description>
22553 <description>Stop Pclk (StopPclk)</description>
22559 <description>Disable Stop Pclk</description>
22564 <description>Enable Stop Pclk</description>
22571 <description>Gate Hclk (GateHclk)</description>
22577 … <description>Clears this bit when the USB is resumed or a new session starts</description>
22582 …<description>Sets this bit to gate hclk to modules when the USB is suspended or the session is not…
22589 <description>Reset Power-Down Modules (RstPdwnModule)</description>
22595 <description>Power is turned on</description>
22600 <description>Power is turned off</description>
22607 <description>Enable Sleep Clock Gating</description>
22613 <description>The PHY clock is not gated in Sleep state</description>
22618 … <description>The Core internal clock gating is enabled in Sleep state</description>
22625 <description>PHY In Sleep</description>
22632 <description>Phy not in Sleep state</description>
22637 <description>Phy in Sleep state</description>
22644 <description>L1 Deep Sleep</description>
22651 <description>Non Deep Sleep</description>
22656 <description>Deep Sleep</description>
22663 <description>Restore Mode (RestoreMode)</description>
22669 …description>In Host mode,this bit indicates Host-initiated Resume and Reset. In Device mode, this …
22674 …description>In Host mode,this bit indicates Device-initiated Remote Wakeup. In Device mode, this b…
22681 <description>Essential Register Values Restored (EssRegRestored)</description>
22688 <description>Register values of essential registers are not restored</description>
22693 … <description>Register values of essential registers have been restored</description>
22700 <description>Restore Value (RestoreValue)</description>
22708 <description>Global STAR Fix Disable Register</description>
22716 …<description>Disable the STAR fix added for Device controller to go back to low power mode when Ho…
22722 …<description>Device controller goes back into SUSPENDED state when host ignores Remote Wakeup</des…
22727 …<description>Device controller waits indefinitely without entering SUSPENDED state when host ignor…
22734 …<description>Disable the STAR fix added for Device controller to detect lineK and move to RESUMING…
22740 <description>Device controller detects line K and resumes</description>
22745 <description>Device controller does not detect line K and resume</description>
22752 …description>Disable the STAR fix added for Device controller to reject DATA0 for the first Control…
22758 <description>Transaction Error reported when host sends DATA0 PID</description>
22763 … <description>Transaction Error not reported when host sends DATA0 PID</description>
22770 …<description>Disable the STAR fix added for Host controller to flag error for SSPLIT STALL/NYET</d…
22776 … <description>Transaction Error reported when device sends STALL/NYET for SSPLIT</description>
22781 … <description>Transaction Error not reported when device sends STALL/NYET for SSPLIT</description>
22788 …<description>Disable the STAR fix added for Host controller to accept DATA1 PID from device for IS…
22794 …<description>Transaction Error not reported when device sends DATA1 PID for ISOC Split</descriptio…
22799 … <description>Transaction Error reported when device sends DATA1 PID for ISOC Split</description>
22806 …<description>Disable the STAR fix added for Host controller to handle Faulty cable scenarios</desc…
22812 <description>Fix for handling faulty cable enabled</description>
22817 <description>Fix for handling faulty cable disabled</description>
22824 …<description>Disable the STAR fix added for Host controller LS mode IPG increment from 2 LS bit ti…
22830 <description>Host LS mode IPG is 3 LS bit times</description>
22835 <description>Host LS mode IPG is 2 LS bit times</description>
22842 …<description>Disable the STAR fix added for Device controller to transition to IDLE state during F…
22848 … <description>Device controller transitions to IDLE state during FS device disconnect</description>
22853 …<description>Device controller does not transition to IDLE state during FS device disconnect</desc…
22860 …<description>Disable the STAR fix added for Device controller to not start Remote Wakeup signallin…
22866 …<description>Device controller does not start remote wakeup signalling when host resume has alread…
22871 …<description>Device controller is allowed to start remote wakeup signalling when host resume has a…
22878 …<description>Disable the STAR fix added for Device controller to not hang when Remote Wakeup signa…
22884 …<description>Device controller does not hang when remote wakeup signalling clashes with host resum…
22889 …<description>Device controller hangs when remote wakeup signalling clashes with host resume during…
22896 …description>Disable the STAR fix added for Host controller to wait for IPG duration to send next t…
22902 <description>Host controller checks IPG after NAK/STALL for IN token</description>
22907 … <description>Host controller does not check IPG after NAK/STALL for IN token</description>
22914 …description>Disable the STAR fix added for Host controller to increase the gap between utmi_xcvrse…
22920 …<description>Host controller asserts utmi_txvalid at least 2 utmi_clk cycles after utmi_xcvrselect…
22925 …<description>Host controller can assert utmi_txvalid after 1 utmi_clk cycle of utmi_xcvrselect swi…
22932 …description>Disable the STAR fix added for Host controller to increase the preamble transceiver se…
22938 …description>Host controller waits for previous functional register update to complete before switc…
22943 …description>Host controller does not wait for the previous functional register update to complete …
22950 …description>Disable the STAR fix added for Host controller to report transaction error when DATA0 …
22956 …<description>Host controller reports transaction error when DATA0 PID is received for CTRL STATUS …
22961 …<description>Host controller retries the transfer when DATA0 PID is received for CTRL STATUS IN tr…
22968 …<description>Disable the correction to OpMode/XcvrSel/TermSel on UTMI Interface in Host mode.</des…
22974 …<description>Opmode, XcvrSel, TermSel are changed by the Host Controller after TxValid goes LOW (1…
22979 …description>Opmode, XcvrSel, TermSel are changed by the Host Controller without waiting for TxVali…
22986 …<description>Disable the STAR fix added for correcting Opmode and XcvrSel on UTMI Interface when r…
22992 …<description>Valid Combination of Opmode and XcvrSel is driven when reset is detected in suspend s…
22997 …<description>Invalid Combination of Opmode and XcvrSel is driven when reset is detected in suspend…
23004 …<description>Disable the STAR fix added for correcting Txvalid deassertion on UTMI Interface when …
23010 …<description>Txvalid is deasserted during soft disconnect after receiving Txready from the PHY</de…
23015 …<description>Txvalid is deasserted during soft disconnect without waiting for Txready from the PHY…
23022 …<description>Disable the STAR fix added for correcting Host behavior when port is disabled.</descr…
23028 <description>Txvalid is not asserted when port is disabled</description>
23033 <description>Txvalid can be asserted when port is disabled</description>
23044 <description>Unspecified</description>
23052 <description>Description collection: Data FIFO Access Register Map 0</description>
23061 <description>Unspecified</description>
23069 <description>Description collection: Data FIFO Direct Access Register Map</description>
23080 <description>I3CCORE 0</description>
23095 <description>Unspecified</description>
23101 <description>DWC_mipi_i3c control Register</description>
23109 <description>I3C Broadcast Address include</description>
23115 <description>Unspecified</description>
23120 <description>Unspecified</description>
23127 <description>I2C Slave Present</description>
23133 <description>Unspecified</description>
23138 <description>Unspecified</description>
23145 <description>Hot-Join ACK/NACK Control</description>
23151 <description>Unspecified</description>
23156 <description>Unspecified</description>
23163 <description>Idle Count Multiplier</description>
23169 <description>Unspecified</description>
23174 <description>Unspecified</description>
23179 <description>Unspecified</description>
23184 <description>Unspecified</description>
23191 <description>This field is used in Slave mode of operation.</description>
23197 <description>DMA Handshake Interface Enable</description>
23203 <description>The DMA handshake control has no significance.</description>
23208 … <description>Enables the DMA handshake control to interact with external DMA.</description>
23215 <description>DWC_mipi_i3c Abort</description>
23221 <description>DWC_mipi_i3c Resume</description>
23227 <description>Controls whether or not DWC_mipi_i3c is enabled.</description>
23233 <description>Disables the DWC_mipi_i3c controller</description>
23238 <description>Enables the DWC_mipi_i3c controller.</description>
23247 …<description>In the master mode of operation this Register is used to program the Device Dynamic A…
23255 <description>Device Static Address.</description>
23261 <description>Static Address Valid.</description>
23267 <description>Unspecified</description>
23272 <description>Unspecified</description>
23279 <description>Device Dynamic Address.</description>
23285 <description>Dynamic Address Valid</description>
23291 <description>Unspecified</description>
23296 <description>Unspecified</description>
23305 <description>Hardware Capability register</description>
23313 <description>Reflects the IC_DEVICE_ROLE Configurable Parameter.</description>
23320 <description>Master Only</description>
23325 <description>Programmable Master-Slave</description>
23330 <description>Secondary Master</description>
23335 <description>Slave Only</description>
23342 <description>Reflects the IC_SPEED_HDR_DDR Configurable Parameter.</description>
23349 <description>HDR-DDR not supported</description>
23354 <description>HDR-DDR supported</description>
23361 <description>Reflects the IC_SPEED_HDR_TS Configurable Parameter.</description>
23368 <description>HDR-TS not supported</description>
23373 <description>HDR-TS supported</description>
23380 <description>Reflects the IC_CLK_PERIOD Configurable Parameter</description>
23387 <description>Reflects the IC_HDR_TX_CLK_PERIOD Configurable Parameter.</description>
23394 <description>Reflects the IC_HAS_DMA Configurable Parameter.</description>
23401 <description>Reflects the IC_SLV_HJ Configurable Parameter.</description>
23408 <description>Reflects the IC_SLV_IBI Configurable Parameter.</description>
23417 <description>Command Queue Port.</description>
23425 <description>32 bit command</description>
23434 <description>Response Queue Port</description>
23442 <description>32 bit Response</description>
23451 <description>Receive Data Port Register</description>
23459 <description>Receive Data Port.</description>
23468 <description>Transmit Data Port Register</description>
23477 <description>Transmit Data Port</description>
23486 <description>In-Band Interrupt Queue Data Register</description>
23494 <description>In-Band Interrupt Data</description>
23503 <description>In-Band Interrupt Queue Status Register</description>
23512 <description>In-Band Interrupt data length.</description>
23519 <description>IBI Identifier.</description>
23526 … <description>The acknowledge bit of the IBI Received Status (IBISTS) bitfield.</description>
23533 <description>Responded with ACK</description>
23538 <description>Responded with NACK</description>
23547 <description>Queue Threshold Control Register</description>
23555 <description>Command Buffer Empty Threshold Value.</description>
23561 <description>Response Buffer Threshold Value.</description>
23567 <description>In-Band Interrupt Status Threshold Value.</description>
23575 <description>Data Buffer Threshold Control Register</description>
23583 <description>Transmit Buffer Threshold Value</description>
23589 <description>Unspecified</description>
23594 <description>Unspecified</description>
23599 <description>Unspecified</description>
23604 <description>Unspecified</description>
23609 <description>Unspecified</description>
23614 <description>Unspecified</description>
23621 <description>Receive Buffer Threshold Value</description>
23627 <description>Unspecified</description>
23632 <description>Unspecified</description>
23637 <description>Unspecified</description>
23642 <description>Unspecified</description>
23647 <description>Unspecified</description>
23652 <description>Unspecified</description>
23659 <description>Transfer Start Threshold Value</description>
23665 <description>Unspecified</description>
23670 <description>Unspecified</description>
23675 <description>Unspecified</description>
23680 <description>Unspecified</description>
23685 <description>Unspecified</description>
23690 <description>Unspecified</description>
23697 <description>Receive Start Threshold Value</description>
23703 <description>Unspecified</description>
23708 <description>Unspecified</description>
23713 <description>Unspecified</description>
23718 <description>Unspecified</description>
23723 <description>Unspecified</description>
23728 <description>Unspecified</description>
23737 …<description>This Register is used to control whether or not to intimate the application if an IBI…
23745 <description>Notify Rejected Hot-Join Control.</description>
23751 <description>Unspecified</description>
23756 <description>Unspecified</description>
23763 <description>Notify Rejected Master Request Control.</description>
23769 …description>Suppress passing the IBI Status to the IBI FIFO (hence not notifying the application) …
23774 …description>Writes IBI Status to the IBI FIFO (hence notifying the application) when a MR Request …
23781 <description>Notify Rejected Slave Interrupt Request Control.</description>
23787 …description>Suppress passing the IBI Status to the IBI FIFO (hence not notifying the application) …
23792 …description>Writes IBI Status to the IBI FIFO (hence notifying the application) when a Slave Inter…
23801 <description>IBI Master Request Rejection Control Register.</description>
23809 <description>In-band Master Request Reject.</description>
23815 <description>ACK Master Request.</description>
23820 … <description>NACK and send Directed DISEC CCC to disable the interrupting slave.</description>
23829 <description>IBI SIR Request Rejection Control</description>
23837 <description>In-band Slave Interrupt Request Reject</description>
23843 <description>ACK the SIR Request.</description>
23848 <description>NACK and send directed auto disable CCC.</description>
23857 …<description>This Register is used for general software reset and for individual buffer reset.</de…
23865 <description>Core Software Reset.</description>
23871 <description>Command Queue Software Reset</description>
23877 <description>Response Queue Software Reset</description>
23883 <description>Transmit Buffer Software Reset</description>
23889 <description>Receive Buffer Software Reset.</description>
23895 <description>IBI Queue Software Reset.</description>
23901 <description>Bus Reset type</description>
23907 <description>Exit Pattern.</description>
23912 <description>SCL_LOW_RESET Pattern.</description>
23919 <description>Bus Reset.</description>
23927 …<description>This register indicates the status/values of some events/controls that are relavant t…
23935 <description>Slave Interrupt Request Enable.</description>
23942 <description>Master Request Enable.</description>
23949 <description>Hot-Join Interrupt Enable</description>
23955 <description>Activity State Status.</description>
23962 <description>Unspecified</description>
23967 <description>Unspecified</description>
23972 <description>Unspecified</description>
23977 <description>Unspecified</description>
23984 <description>MRL Updated Status.</description>
23990 <description>MWL Updated Status.</description>
23998 <description>Interrupt Status Register</description>
24006 <description>Transmit Buffer Threshold Status</description>
24013 <description>Receive Buffer Threshold Status.</description>
24020 <description>IBI Buffer Threshold Status.</description>
24027 <description>Command Queue Ready.</description>
24034 <description>Response Queue Ready Status.</description>
24041 <description>Transfer Abort Status.</description>
24047 <description>CCC Table Updated Status.</description>
24053 <description>Dynamic Address Assigned Status.</description>
24059 <description>Transfer Error Status.</description>
24065 <description>Define Slave CCC Received Status.</description>
24071 <description>Read Request Received.</description>
24077 <description>IBI status is updated.</description>
24083 …<description>This interrupt is set when the role of the controller changes from being a Master to …
24089 <description>Bus Reset Pattern Generation Done Status.</description>
24097 <description>Interrupt Status Enable Register.</description>
24105 <description>Transmit Buffer Threshold Status Enable.</description>
24111 <description>Receive Buffer Threshold Status Enable</description>
24117 <description>IBI Buffer Threshold Status Enable.</description>
24123 <description>Command Queue Ready Status Enable</description>
24129 <description>Response Queue Ready Status Enable</description>
24135 <description>Transfer Abort Status Enable.</description>
24141 <description>CCC Table Updated Status Enable.</description>
24147 <description>Dynamic Address Assigned Status Enable</description>
24153 <description>Transfer Error Status Enable</description>
24159 <description>Define Slave CCC Received Status Enable</description>
24165 <description>Read Request Received Status Enable</description>
24171 <description>IBI Updated Status Enable</description>
24177 <description>Bus owner Updated Status Enable</description>
24183 <description>Bus Reset Pattern Generation Done Status Enable.</description>
24191 <description>Interrupt Signal Enable Register</description>
24199 <description>Transmit Buffer Threshold Signal Enable</description>
24205 <description>Receive Buffer Threshold Signal Enable</description>
24211 <description>IBI Buffer Threshold Signal Enable</description>
24217 <description>Command Queue Ready Signal Enable</description>
24223 <description>Response Queue Ready Signal Enable</description>
24229 <description>Transfer Abort Signal Enable</description>
24235 <description>CCC Table Updated Signal Enable</description>
24241 <description>Dynamic Address Assigned Signal Enable</description>
24247 <description>Transfer Error Signal Enable</description>
24253 <description>Define Slave CCC Received Signal Enable</description>
24259 <description>Read Request Received Signal Enable</description>
24265 <description>IBI Updated Signal Enable</description>
24271 <description>Bus owner Updated Signal Enable</description>
24277 <description>Bus Reset Pattern Generation Done Signal Enable.</description>
24285 <description>Interrupt Force Enable Register</description>
24293 <description>Transmit Buffer Threshold Force Enable</description>
24300 <description>Receive Buffer Threshold Force Enable</description>
24307 <description>IBI Buffer Threshold Force Enable</description>
24314 <description>Command Queue Ready Force Enable</description>
24321 <description>Response Queue Ready Force Enable</description>
24328 <description>Transfer Abort Force Enable</description>
24335 <description>CCC Table Updated Force Enable</description>
24342 <description>Dynamic Address Assigned Force Enable</description>
24349 <description>Transfer Error Force Enable</description>
24356 <description>Define Slave CCC Received Force Enable</description>
24363 <description>Read Request Received Force Enable</description>
24370 <description>IBI Updated Force Enable</description>
24377 <description>Bus owner Updated Force Enable</description>
24384 <description>Bus Reset Pattern Generation Done Force Enable.</description>
24393 <description>Queue Status Level Register.</description>
24401 <description>Command Queue Empty Locations.</description>
24408 <description>Response Buffer Level Value.</description>
24415 <description>IBI Buffer Level Value.</description>
24422 <description>IBI Buffer Status Count.</description>
24431 <description>Data Buffer Status Level Register.</description>
24439 <description>Transmit Buffer Empty Level Value.</description>
24446 <description>Receive Buffer Level Value.</description>
24455 …<description>The user can get status of the DWC_mipi_i3c Controller from this 32-bit read only reg…
24463 …<description>This bit is used to check the SCL line level to recover from errors and for debugging…
24470 …<description>This bit is used to check the SDA line level to recover from errors and for debugging…
24477 … <description>This Bit is used to check whether the Master is Current Master or not.</description>
24484 <description>Master is not Current Master</description>
24489 <description>Master is Current Master</description>
24496 <description>Transfer Type Status</description>
24503 …<description>Controller is in Idle state, waiting for commands from application or Slave initated …
24508 <description>Broadcast CCC Write Transfer.</description>
24513 <description>Directed CCC Write Transfer.</description>
24518 <description>Directed CCC Read Transfer.</description>
24523 <description>ENTDAA Address Assignment Transfer.</description>
24528 <description>SETDASA Address Assignment Transfer.</description>
24533 <description>Private I3C SDR Write Transfer.</description>
24538 <description>Private I3C SDR Read Transfer.</description>
24543 <description>Private I2C SDR Write Transfer.</description>
24548 <description>Private I2C SDR Read Transfer.</description>
24553 <description>Private HDR Ternary Symbol(TS) Write Transfer.</description>
24558 <description>Private HDR Ternary Symbol(TS) Read Transfer.</description>
24563 <description>Private HDR Double-Data Rate(DDR) Write Transfer.</description>
24568 <description>Private HDR Double-Data Rate(DDR) Read Transfer.</description>
24573 <description>Servicing In-Band Interrupt Transfer.</description>
24578 …<description>Halt state. Controller is in Halt State, waiting for the application to resume throug…
24585 <description>Current Master Transfer State Status.</description>
24592 …<description>Controller is Idle state, waiting for commands from application or Slave initated In-…
24597 <description>START Generation State.</description>
24602 <description>RESTART Generation State.</description>
24607 <description>STOP Genration State.</description>
24612 … <description>START Hold Generation for the Slave Initiated START State.</description>
24617 … <description>Broadcast Write Address Header(7h7E,W) Generation State.</description>
24622 … <description>Broadcast Read Address Header(7h7E,R) Generation State.</description>
24627 <description>Dynamic Address Assignment State.</description>
24632 <description>Slave Address Generation State.</description>
24637 <description>CCC Byte Generation State.</description>
24642 <description>HDR Command Generation State.</description>
24647 <description>Write Data Transfer State.</description>
24652 <description>Read Data Transfer State.</description>
24657 <description>In-Band Interrupt(SIR) Read Data State.</description>
24662 <description>In-Band Interrupt Auto-Disable State</description>
24667 <description>HDR-DDR CRC Data Generation/Receive State.</description>
24672 <description>Clock Extension State.</description>
24677 <description>Halt State.</description>
24684 …<description>This field reflects the Transaction-ID of the current executing command.</description>
24691 …<description>This field reflects whether the Master Controller is in Idle state or not.</descripti…
24698 <description>Unspecified</description>
24703 <description>Unspecified</description>
24712 …<description>The user can get status of the DWC_mipi_i3c Controller from this 32-bit read only reg…
24721 …<description>This bit is used to check the SCL line level to recover from errors and for debugging…
24728 …<description>This bit is used to check the SDA line level to recover from errors and for debugging…
24735 … <description>This Bit is used to check whether the Master is Current Master or not.</description>
24742 <description>Master is not Current Master</description>
24747 <description>Master is Current Master</description>
24754 <description>Transfer Type Status</description>
24761 <description>Controller is in Idle state.</description>
24766 <description>Hot-Join transfer state.</description>
24771 <description>IBI transfer state.</description>
24776 <description>Master write transfer ongoing.</description>
24781 <description>Read data prefetch state.</description>
24786 <description>Master read transfer ongoing.</description>
24791 … <description>Slave controller in Halt State waiting for resume from application.</description>
24798 <description>Current Master Transfer State Status.</description>
24805 …<description>This field reflects the Transaction-ID of the current executing command.</description>
24812 …<description>This field reflects whether the Master Controller is in Idle state or not.</descripti…
24819 <description>Unspecified</description>
24824 <description>Unspecified</description>
24833 <description>Device Operating Status Register.</description>
24841 <description>Pending Interrupt</description>
24848 <description>Protocol Error</description>
24855 <description>Activity Mode</description>
24862 <description>Underflow error</description>
24869 <description>Slave Busy</description>
24876 <description>Overflow Error</description>
24883 <description>Data not ready</description>
24890 <description>Buffer not available</description>
24897 <description>Frame Error</description>
24906 <description>Pointer for Device Address Table</description>
24914 <description>Start Address of Device Address Table.</description>
24921 <description>Depth of Device Address Table</description>
24930 <description>Pointer for Device Characteristics Table</description>
24938 <description>Start Address of Device Characteristics Table.</description>
24945 <description>Depth of Device Characteristics Table</description>
24952 <description>Current index of Device Characteristics Table.</description>
24960 <description>Pointer for Vendor Specific Registers.</description>
24968 <description>Start Address of Vendor specific registers.</description>
24977 <description>I3C MIPI Manufacturer ID Register.</description>
24985 <description>Specifies the Provisional ID Type Selector (PID[32]).</description>
24991 <description>Specifies the MIPI Manufacturer ID.</description>
24999 <description>I3C Normal Provisional ID Register.</description>
25007 … <description>Specifies the additional 12-bit ID of DWC_mipi_i3c device (PID[11:0]).</description>
25013 … <description>This field is used to program the instance ID of the Slave.</description>
25019 <description>Specifies the Part ID of DWC_mipi_i3c device (PID[31:16])</description>
25027 <description>I3C Slave Characteristic Register.</description>
25035 …<description>Max Data Speed Limitation field in Bus Characteristic Register (BCR[0]).</description>
25041 … <description>IBI Request Capable field in Bus Characteristic Register (BCR[1]).</description>
25048 … <description>IBI Payload field in Bus Characteristic Register (BCR[2]).</description>
25055 … <description>Offline Capable field in Bus Characteristic Register (BCR[3]).</description>
25062 … <description>Bridge Identifier field in Bus Characteristic Register (BCR[4]).</description>
25069 …<description>SDR Only or SDR and HDR Capable field in Bus Characteristic Register (BCR[5]).</descr…
25075 … <description>Device Role field in Bus Characteristic Register (BCR[7:6]).</description>
25081 <description>I3C Device Characteristic Value.</description>
25087 <description>I3C Device HDR Capability Register Value.</description>
25096 <description>I3C Max Write/Read Length Register.</description>
25104 <description>I3C Device Max Write Length</description>
25111 <description>I3C Device Max Read Length.</description>
25120 <description>MXDS Maximum Read Turnaround Time.</description>
25128 …<description>Specifies the maximum read turnaround time (in microseconds (us)) of DWC_mipi_i3c Sla…
25137 …<description>The values in this register are returned by the slave as GETACCMST CCC data.</descrip…
25145 …<description>Specifies the Maximum Sustained Data Rate for non-CCC messages sent by Master Device …
25151 <description>12.5MHz</description>
25156 <description>8MHZ</description>
25161 <description>6MHz</description>
25166 <description>4MHz</description>
25171 <description>2MHz</description>
25178 …<description>Specifies the Maximum Sustained Data Rate for non-CCC messages sent by DWC_mipi_i3c S…
25184 <description>12.5MHz</description>
25189 <description>8MHZ</description>
25194 <description>6MHz</description>
25199 <description>4MHz</description>
25204 <description>2MHz</description>
25211 …<description>Specifies the clock to data turnaround time (Tsco parameter) of DWC_mipi_i3c Slave de…
25217 <description>8ns</description>
25222 <description>9ns</description>
25227 <description>10ns</description>
25232 <description>11ns</description>
25237 <description>12ns</description>
25246 <description>This register is used in slave mode of operation.</description>
25254 <description>Slave Interrupt Request</description>
25260 <description>Slave Interrupt Request Control</description>
25266 <description>Send the Assigned Dynamic Address</description>
25273 <description>Master Request</description>
25279 <description>IBI Completion Status</description>
25286 <description>IBI accepted by the Master (ACK response received)</description>
25291 <description>IBI Not Attempted</description>
25300 <description>TSP/TSL Symbol Timing Register</description>
25308 <description>TSP/TSL Symbol Count Value.</description>
25316 <description>Device Control Extended register.</description>
25324 …<description>This bit is used to select the Device Operation Mode before the controller is enabled…
25330 <description>Unspecified</description>
25335 <description>Unspecified</description>
25342 …<description>In Slave mode of operation, this bit serves as a control to ACK/NACK GETACCMST CCC fr…
25348 <description>ACK GETACCMST CCC</description>
25353 <description>NACK GETACCMST CCC</description>
25362 <description>SCL I3C Open Drain Timing Register</description>
25370 <description>I3C Open Drain Low Count.</description>
25376 <description>I3C Open Drain High Count.</description>
25384 <description>SCL I3C Push Pull Timing Register</description>
25392 <description>I3C Push Pull Low Count.</description>
25398 <description>I3C Push Pull High Count.</description>
25406 <description>SCL I2C Fast Mode Timing Register</description>
25414 <description>I2C Fast Mode Low Count</description>
25420 <description>I2C Fast Mode High Count</description>
25428 <description>SCL I2C Fast Mode Plus Timing Register</description>
25436 <description>I2C Fast Mode Plus Low Count</description>
25442 <description>I2C Fast Mode Plus High Count</description>
25450 <description>SCL Extended Low Count Timing Register.</description>
25458 <description>I3C Extended Low Count Register 1</description>
25464 <description>I3C Extended Low Count Register 2</description>
25470 <description>I3C Extended Low Count Register 3</description>
25476 <description>I3C Extended Low Count Register 4</description>
25484 <description>SCL Termination Bit Low Count Timing Register</description>
25492 <description>I3C Read Termination Bit Low count.</description>
25498 <description>I3C HDR Ternary Skew Count.</description>
25506 <description>SDA Hold and Mode Switch Delay Timing Register</description>
25514 …<description>This field controls the hold time (in term of the core clock period) of the transmit …
25522 <description>Bus Free and Available Timing Register</description>
25530 … <description>This register field is used only in Master mode of operation</description>
25536 … <description>This register field is used only in Slave mode of operation</description>
25544 <description>Bus Idle Timing Register</description>
25552 <description>Bus Idle Count Value.</description>
25560 …<description>The SCL Low Master Extended Timeout register is used to define the duration of the SC…
25568 …<description>This count defines the number of core clock periods to count for generation of the SC…
25576 … <description>This register reflects the current release number of DWC_mipi_i3c</description>
25584 <description>Current release number</description>
25593 … <description>This register reflects the current release type of DWC_mipi_i3c.</description>
25601 <description>Current release type</description>
25610 …<description>This register reflects the configured size of the Data Buffer and Queues in DWC_mipi_…
25618 <description>Transmit Data Buffer Size</description>
25625 <description>2 DWORDS</description>
25630 <description>4 DWORDS</description>
25635 <description>8 DWORDS</description>
25640 <description>16 DWORDS</description>
25645 <description>32 DWORDS</description>
25650 <description>64 DWORDS</description>
25657 <description>Receive Data Buffer Size</description>
25664 <description>2 DWORDS</description>
25669 <description>4 DWORDS</description>
25674 <description>8 DWORDS</description>
25679 <description>16 DWORDS</description>
25684 <description>32 DWORDS</description>
25689 <description>64 DWORDS</description>
25696 <description>Command Queue Size</description>
25703 <description>2 DWORDS</description>
25708 <description>4 DWORDS</description>
25713 <description>8 DWORDS</description>
25718 <description>16 DWORDS</description>
25725 <description>Response Queue Size</description>
25732 <description>2 DWORDS</description>
25737 <description>4 DWORDS</description>
25742 <description>8 DWORDS</description>
25747 <description>16 DWORDS</description>
25754 <description>IBI Queue Size</description>
25761 <description>2 DWORDS</description>
25766 <description>4 DWORDS</description>
25771 <description>8 DWORDS</description>
25776 <description>16 DWORDS</description>
25787 <description>Unspecified</description>
25793 …<description>Description cluster: Device Characteristic Table Location-1 of Device [n]</descriptio…
25801 <description>The LSB 32-bit value of Provisional-ID</description>
25810 …<description>Description cluster: Device Characteristic Table Location-2 of Device [n]</descriptio…
25818 <description>The MSB 16-bit value of Provisional-ID</description>
25827 …<description>Description cluster: Device Characteristic Table Location-3 of Device [n]</descriptio…
25835 <description>Device Characteristic Value</description>
25842 <description>Bus Characteristic Value</description>
25851 …<description>Description cluster: Device Characteristic Table Location-4 of Device [n]</descriptio…
25859 <description>Device Dynamic Address assigned.</description>
25871 …<description>Description collection: Secondary Master Device Characteristic Table Location of Devi…
25879 <description>The Dynamic Addr of Device [n]</description>
25886 <description>The DCR TYPE of Device [n]</description>
25893 <description>The BCR TYPE of Device [n]</description>
25900 <description>The Static Addr of Device [n]</description>
25911 <description>Description collection: Device Address Table of Device [n]</description>
25919 <description>Device Static Address.</description>
25925 <description>Device Dynamic Address with parity.</description>
25931 …<description>This field is used to set the Device NACK Retry count for the particular device.</des…
25937 <description>Legacy I2C device or not.</description>
25946 <description>Unspecified</description>
25952 <description>Unspecified</description>
25958 … <description>This register contains the source address of the DMA transfer.</description>
25966 <description>Current Source Address of DMA transfer.</description>
25974 … <description>This register contains the destination address of the DMA transfer.</description>
25982 <description>Current Destination address of DMA transfer.</description>
25990 … <description>This register contains fields that control the DMA transfer.</description>
25998 <description>Interrupt Enable Bit.</description>
26004 <description>Unspecified</description>
26009 <description>Unspecified</description>
26016 <description>Destination Transfer Width.</description>
26022 <description>Unspecified</description>
26027 <description>Unspecified</description>
26032 <description>Unspecified</description>
26037 <description>Unspecified</description>
26042 <description>Unspecified</description>
26047 <description>Unspecified</description>
26052 <description>Unspecified</description>
26057 <description>Unspecified</description>
26064 <description>Reserved field - read-only</description>
26071 <description>Destination Address Increment.</description>
26077 <description>Unspecified</description>
26082 <description>Unspecified</description>
26087 <description>Unspecified</description>
26092 <description>Unspecified</description>
26099 <description>Source Address Increment.</description>
26105 <description>Unspecified</description>
26110 <description>Unspecified</description>
26115 <description>Unspecified</description>
26120 <description>Unspecified</description>
26127 <description>Destination Burst Transaction Length.</description>
26133 <description>Unspecified</description>
26138 <description>Unspecified</description>
26143 <description>Unspecified</description>
26148 <description>Unspecified</description>
26153 <description>Unspecified</description>
26158 <description>Unspecified</description>
26163 <description>Unspecified</description>
26168 <description>Unspecified</description>
26175 <description>Source Burst Transaction Length.</description>
26181 <description>Unspecified</description>
26186 <description>Unspecified</description>
26191 <description>Unspecified</description>
26196 <description>Unspecified</description>
26201 <description>Unspecified</description>
26206 <description>Unspecified</description>
26211 <description>Unspecified</description>
26216 <description>Unspecified</description>
26223 <description>Reserved field - read-only</description>
26230 <description>Destination scatter enable.</description>
26236 <description>Unspecified</description>
26241 <description>Unspecified</description>
26248 <description>Reserved field - read-only</description>
26255 <description>Transfer Type and Flow Control.</description>
26261 <description>Unspecified</description>
26266 <description>Unspecified</description>
26271 <description>Unspecified</description>
26276 <description>Unspecified</description>
26281 <description>Unspecified</description>
26286 <description>Unspecified</description>
26291 <description>Unspecified</description>
26296 <description>Unspecified</description>
26303 <description>Reserved field - read-only</description>
26310 <description>Reserved field - read-only</description>
26317 <description>Reserved field - read-only</description>
26324 <description>Reserved field - read-only</description>
26331 <description>Reserved field - read-only</description>
26340 … <description>This register contains fields that control the DMA transfer.</description>
26348 <description>Block Transfer Size.</description>
26354 <description>Reserved field - read-only</description>
26361 <description>Done bit.</description>
26367 <description>Unspecified</description>
26372 <description>Unspecified</description>
26381 … <description>This register contains fields that configure the DMA transfer.</description>
26389 <description>Reserved field - read-only</description>
26396 <description>Channel Priority.</description>
26402 <description>Unspecified</description>
26407 <description>Unspecified</description>
26412 <description>Unspecified</description>
26417 <description>Unspecified</description>
26422 <description>Unspecified</description>
26427 <description>Unspecified</description>
26432 <description>Unspecified</description>
26437 <description>Unspecified</description>
26444 <description>Channel Suspend.</description>
26450 <description>Unspecified</description>
26455 <description>Unspecified</description>
26462 <description>Channel FIFO status.</description>
26469 <description>Unspecified</description>
26474 <description>Unspecified</description>
26481 <description>Destination Software or Hardware Handshaking Select.</description>
26487 <description>Unspecified</description>
26492 <description>Unspecified</description>
26499 <description>Source Software or Hardware Handshaking Select.</description>
26505 <description>Unspecified</description>
26510 <description>Unspecified</description>
26517 <description>Reserved field - read-only</description>
26524 <description>Reserved field - read-only</description>
26531 <description>Reserved field - read-only</description>
26538 <description>Reserved field - read-only</description>
26545 <description>Destination Handshaking Interface Polarity.</description>
26551 <description>Unspecified</description>
26556 <description>Unspecified</description>
26563 <description>Source Handshaking Interface Polarity.</description>
26569 <description>Unspecified</description>
26574 <description>Unspecified</description>
26581 <description>Maximum AMBA Burst Length.</description>
26587 <description>Reserved field - read-only</description>
26594 <description>Reserved field- read-only</description>
26603 … <description>This register contains fields that configure the DMA transfer.</description>
26611 <description>Flow Control Mode.</description>
26617 <description>Unspecified</description>
26622 <description>Unspecified</description>
26629 <description>FIFO Mode Select.</description>
26635 <description>Unspecified</description>
26640 <description>Unspecified</description>
26647 … <description>Protection Control bits used to drive the AHB HPROT[3:1] bus.</description>
26653 <description>Reserved field- read-only</description>
26660 <description>Reserved field- read-only</description>
26667 <description>Source Hardware Interface.</description>
26673 <description>Reserved field - read-only</description>
26680 <description>Destination hardware interface.</description>
26686 <description>Reserved field - read-only</description>
26693 <description>Reserved field - read-only</description>
26702 <description>Destination Scatter register.</description>
26710 <description>Destination Scatter Interval.</description>
26716 <description>Destination Scatter Count.</description>
26725 <description>Unspecified</description>
26731 … <description>This register contains the source address of the DMA transfer.</description>
26739 <description>Current Source Address of DMA transfer.</description>
26747 … <description>This register contains the destination address of the DMA transfer.</description>
26755 <description>Current Destination address of DMA transfer.</description>
26763 … <description>This register contains fields that control the DMA transfer.</description>
26771 <description>Interrupt Enable Bit.</description>
26777 <description>Unspecified</description>
26782 <description>Unspecified</description>
26789 <description>Reserved field - read-only</description>
26796 <description>Source Transfer Width.</description>
26802 <description>Unspecified</description>
26807 <description>Unspecified</description>
26812 <description>Unspecified</description>
26817 <description>Unspecified</description>
26822 <description>Unspecified</description>
26827 <description>Unspecified</description>
26832 <description>Unspecified</description>
26837 <description>Unspecified</description>
26844 <description>Destination Address Increment.</description>
26850 <description>Unspecified</description>
26855 <description>Unspecified</description>
26860 <description>Unspecified</description>
26865 <description>Unspecified</description>
26872 <description>Source Address Increment.</description>
26878 <description>Unspecified</description>
26883 <description>Unspecified</description>
26888 <description>Unspecified</description>
26893 <description>Unspecified</description>
26900 <description>Destination Burst Transaction Length.</description>
26906 <description>Unspecified</description>
26911 <description>Unspecified</description>
26916 <description>Unspecified</description>
26921 <description>Unspecified</description>
26926 <description>Unspecified</description>
26931 <description>Unspecified</description>
26936 <description>Unspecified</description>
26941 <description>Unspecified</description>
26948 <description>Source Burst Transaction Length.</description>
26954 <description>Unspecified</description>
26959 <description>Unspecified</description>
26964 <description>Unspecified</description>
26969 <description>Unspecified</description>
26974 <description>Unspecified</description>
26979 <description>Unspecified</description>
26984 <description>Unspecified</description>
26989 <description>Unspecified</description>
26996 <description>Source gather enable.</description>
27002 <description>Unspecified</description>
27007 <description>Unspecified</description>
27014 <description>Reserved field - read-only</description>
27021 <description>Reserved field - read-only</description>
27028 <description>Transfer Type and Flow Control.</description>
27034 <description>Unspecified</description>
27039 <description>Unspecified</description>
27044 <description>Unspecified</description>
27049 <description>Unspecified</description>
27054 <description>Unspecified</description>
27059 <description>Unspecified</description>
27064 <description>Unspecified</description>
27069 <description>Unspecified</description>
27076 <description>Reserved field - read-only</description>
27083 <description>Reserved field - read-only</description>
27090 <description>Reserved field - read-only</description>
27097 <description>Reserved field - read-only</description>
27104 <description>Reserved field - read-only</description>
27113 … <description>This register contains fields that control the DMA transfer.</description>
27121 <description>Block Transfer Size.</description>
27127 <description>Reserved field - read-only</description>
27134 <description>Done bit.</description>
27140 <description>Unspecified</description>
27145 <description>Unspecified</description>
27154 … <description>This register contains fields that configure the DMA transfer.</description>
27162 <description>Reserved field - read-only</description>
27169 <description>Channel Priority.</description>
27175 <description>Unspecified</description>
27180 <description>Unspecified</description>
27185 <description>Unspecified</description>
27190 <description>Unspecified</description>
27195 <description>Unspecified</description>
27200 <description>Unspecified</description>
27205 <description>Unspecified</description>
27210 <description>Unspecified</description>
27217 <description>Channel Suspend.</description>
27223 <description>Unspecified</description>
27228 <description>Unspecified</description>
27235 <description>Channel FIFO status.</description>
27242 <description>Unspecified</description>
27247 <description>Unspecified</description>
27254 <description>Destination Software or Hardware Handshaking Select.</description>
27260 <description>Unspecified</description>
27265 <description>Unspecified</description>
27272 <description>Source Software or Hardware Handshaking Select.</description>
27278 <description>Unspecified</description>
27283 <description>Unspecified</description>
27290 <description>Reserved field - read-only</description>
27297 <description>Reserved field - read-only</description>
27304 <description>Reserved field - read-only</description>
27311 <description>Reserved field - read-only</description>
27318 <description>Destination Handshaking Interface Polarity.</description>
27324 <description>Unspecified</description>
27329 <description>Unspecified</description>
27336 <description>Source Handshaking Interface Polarity.</description>
27342 <description>Unspecified</description>
27347 <description>Unspecified</description>
27354 <description>Maximum AMBA Burst Length.</description>
27360 <description>Reserved field - read-only</description>
27367 <description>Reserved field- read-only</description>
27376 … <description>This register contains fields that configure the DMA transfer.</description>
27384 <description>Flow Control Mode.</description>
27390 <description>Unspecified</description>
27395 <description>Unspecified</description>
27402 <description>FIFO Mode Select.</description>
27408 <description>Unspecified</description>
27413 <description>Unspecified</description>
27420 … <description>Protection Control bits used to drive the AHB HPROT[3:1] bus.</description>
27426 <description>Reserved field- read-only</description>
27433 <description>Reserved field- read-only</description>
27440 <description>Source Hardware Interface.</description>
27446 <description>Reserved field - read-only</description>
27453 <description>Destination hardware interface.</description>
27461 <description>Source Gather register</description>
27469 <description>Source Gather Interval.</description>
27475 <description>Source Gather Count.</description>
27484 <description>Unspecified</description>
27490 …<description>Interrupt events are stored in this Raw Interrupt Status register before masking.</de…
27498 <description>Raw Status for IntTfr Interrupt</description>
27504 <description>Unspecified</description>
27509 <description>Unspecified</description>
27518 …<description>Interrupt events are stored in this Raw Interrupt Status register before masking.</de…
27526 <description>Raw Status for IntBlock Interrupt</description>
27532 <description>Unspecified</description>
27537 <description>Unspecified</description>
27546 …<description>Interrupt events are stored in this Raw Interrupt Status register before masking.</de…
27554 <description>Raw Status for IntSrcTran Interrupt</description>
27560 <description>Unspecified</description>
27565 <description>Unspecified</description>
27574 …<description>Interrupt events are stored in this Raw Interrupt Status register before masking.</de…
27582 <description>Raw Status for IntDstTran Interrupt</description>
27588 <description>Unspecified</description>
27593 <description>Unspecified</description>
27602 …<description>Interrupt events are stored in this Raw Interrupt Status register before masking.</de…
27610 <description>Raw Status for IntErr Interrupt</description>
27616 <description>Unspecified</description>
27621 <description>Unspecified</description>
27630 …<description>Channel DMA Transfer complete interrupt event from all channels is stored in this Int…
27638 <description>Status for IntTfr Interrupt</description>
27645 <description>Unspecified</description>
27650 <description>Unspecified</description>
27659 …<description>Channel Block complete interrupt event from all channels is stored in this Interrupt …
27667 <description>Status for IntBlock Interrupt</description>
27674 <description>Unspecified</description>
27679 <description>Unspecified</description>
27688 …description>Channel Source Transaction complete interrupt event from all channels is stored in thi…
27696 <description>Status for IntSrcTran Interrupt</description>
27703 <description>Unspecified</description>
27708 <description>Unspecified</description>
27717 …description>Channel destination transaction complete interrupt event from all channels is stored i…
27725 <description>Status for IntDstTran Interrupt</description>
27732 <description>Unspecified</description>
27737 <description>Unspecified</description>
27746 …<description>Channel Error interrupt event from all channels is stored in this Interrupt Status re…
27754 <description>Status for IntErr Interrupt</description>
27761 <description>Unspecified</description>
27766 <description>Unspecified</description>
27775 …<description>The contents of the Raw Status register RawTfr is masked with the contents of the Mas…
27783 <description>Mask for IntTfr Interrupt</description>
27789 <description>Unspecified</description>
27794 <description>Unspecified</description>
27801 <description>Reserved field - read-only</description>
27808 <description>Interrupt Mask Write Enable</description>
27815 <description>Unspecified</description>
27820 <description>Unspecified</description>
27829 …<description>The contents of the Raw Status register RawBlock is masked with the contents of the M…
27837 <description>Mask for IntBlock Interrupt</description>
27843 <description>Unspecified</description>
27848 <description>Unspecified</description>
27855 <description>Reserved field- read-only</description>
27862 <description>Interrupt Mask Write Enable</description>
27869 <description>Unspecified</description>
27874 <description>Unspecified</description>
27883 …<description>The contents of the Raw Status register RawSrcTran is masked with the contents of the…
27891 <description>Mask for IntSrcTran Interrupt</description>
27897 <description>Unspecified</description>
27902 <description>Unspecified</description>
27909 <description>Reserved field- read-only</description>
27916 <description>Interrupt Mask Write Enable</description>
27923 <description>Unspecified</description>
27928 <description>Unspecified</description>
27937 …<description>The contents of the Raw Status register RawDstTran is masked with the contents of the…
27945 <description>Mask for IntDstTran Interrupt</description>
27951 <description>Unspecified</description>
27956 <description>Unspecified</description>
27963 <description>Reserved field - read-only</description>
27970 <description>Interrupt Mask Write Enable</description>
27977 <description>Unspecified</description>
27982 <description>Unspecified</description>
27991 …<description>The contents of the Raw Status register RawErr is masked with the contents of the Mas…
27999 <description>Mask for IntErr Interrupt</description>
28005 <description>Unspecified</description>
28010 <description>Unspecified</description>
28017 <description>Reserved field- read-only</description>
28024 <description>Interrupt Mask Write Enable</description>
28031 <description>Unspecified</description>
28036 <description>Unspecified</description>
28045 …description>Each bit in the RawTfr and StatusTfr is cleared on the same cycle by writing a 1 to th…
28053 <description>Clear for IntTfr Interrupt</description>
28060 <description>Unspecified</description>
28065 <description>Unspecified</description>
28074 …description>Each bit in the RawBlock and StatusBlock is cleared on the same cycle by writing a 1 t…
28082 <description>Clear for IntBlock Interrupt</description>
28091 …description>Each bit in the RawSrcTran and StatusSrcTran is cleared on the same cycle by writing a…
28099 <description>Clear for IntSrcTran Interrupt</description>
28106 <description>Unspecified</description>
28111 <description>Unspecified</description>
28120 …description>Each bit in the RawDstTran and StatusDstTran is cleared on the same cycle by writing a…
28128 <description>Clear for IntDstTran Interrupt</description>
28135 <description>Unspecified</description>
28140 <description>Unspecified</description>
28149 …description>Each bit in the RawErr and StatusErr is cleared on the same cycle by writing a 1 to th…
28157 <description>Clear for IntErr Interrupt</description>
28164 <description>Unspecified</description>
28169 <description>Unspecified</description>
28178 …description>The contents of each of the five Status registers StatusTfr, StatusBlock, StatusSrcTr…
28186 <description>OR of the contents of StatusTfr register</description>
28193 <description>Unspecified</description>
28198 <description>Unspecified</description>
28205 <description>OR of the contents of StatusBlock register</description>
28212 <description>Unspecified</description>
28217 <description>Unspecified</description>
28224 <description>OR of the contents of StatusSrcTran</description>
28231 <description>Unspecified</description>
28236 <description>Unspecified</description>
28243 <description>OR of the contents of StatusDstTran</description>
28250 <description>Unspecified</description>
28255 <description>Unspecified</description>
28262 <description>OR of the contents of StatusErr</description>
28269 <description>Unspecified</description>
28274 <description>Unspecified</description>
28284 <description>Unspecified</description>
28290 <description>A bit is assigned for each channel in this register.</description>
28298 <description>Source Software Transaction Request</description>
28304 <description>Unspecified</description>
28309 <description>Unspecified</description>
28316 <description>Reserved field - read-only</description>
28323 <description>Source Software Transaction Request write enable</description>
28330 <description>Unspecified</description>
28335 <description>Unspecified</description>
28344 <description>A bit is assigned for each channel in this register.</description>
28352 <description>Destination Software Transaction Request</description>
28358 <description>Unspecified</description>
28363 <description>Unspecified</description>
28370 <description>Reserved field - read-only</description>
28377 <description>Destination Software Transaction Request write enable</description>
28384 <description>Unspecified</description>
28389 <description>Unspecified</description>
28398 <description>A bit is assigned for each channel in this register.</description>
28406 <description>Source Single Transaction Request</description>
28412 <description>Unspecified</description>
28417 <description>Unspecified</description>
28424 <description>Reserved field - read-only</description>
28431 <description>Source Single Transaction Request write enable</description>
28438 <description>Unspecified</description>
28443 <description>Unspecified</description>
28452 <description>A bit is assigned for each channel in this register.</description>
28460 <description>Destination Single Transaction Request</description>
28466 <description>Unspecified</description>
28471 <description>Unspecified</description>
28478 <description>Reserved field - read-only</description>
28485 <description>Destination Single Transaction Request write enable</description>
28492 <description>Unspecified</description>
28497 <description>Unspecified</description>
28506 <description>A bit is assigned for each channel in this register.</description>
28514 <description>Source Last Transaction Request register</description>
28520 <description>Unspecified</description>
28525 <description>Unspecified</description>
28532 <description>Reserved field- read-only</description>
28539 <description>Source Last Transaction Request write enable</description>
28546 <description>Unspecified</description>
28551 <description>Unspecified</description>
28560 <description>A bit is assigned for each channel in this register.</description>
28568 <description>Destination Last Transaction Request</description>
28574 <description>Unspecified</description>
28579 <description>Unspecified</description>
28586 <description>Reserved field - read-only</description>
28593 <description>Source Last Transaction Request write enable</description>
28600 <description>Unspecified</description>
28605 <description>Unspecified</description>
28615 <description>Unspecified</description>
28621 …<description>This register is used to enable the DW_ahb_dmac, which must be done before any channe…
28629 <description>DW_ahb_dmac Enable bit.</description>
28635 <description>Unspecified</description>
28640 <description>Unspecified</description>
28649 <description>This is the DW_ahb_dmac Channel Enable Register.</description>
28657 <description>Channel Enable.</description>
28663 <description>Unspecified</description>
28668 <description>Unspecified</description>
28675 <description>Reserved field - read-only</description>
28682 <description>Channel enable register</description>
28691 …description>This is the DW_ahb_dmac ID register, which is a read-only register that reads back the…
28699 <description>Hardcoded DW_ahb_dmac peripheral ID.</description>
28708 …description>This register is used to put the AHB slave interface into test mode, during which the …
28716 <description>DMA Test register</description>
28722 <description>Unspecified</description>
28727 <description>Unspecified</description>
28736 <description>This register holds the timeout value of Low Power Counter.</description>
28744 … <description>This field holds timeout value of low power counter register.</description>
28752 …description>DMA_COMP_PARAMS_6L is a constant read-only register that contains encoded information …
28760 …<description>The value of this register is derived from the DMAH_CH7_DTW coreConsultant parameter.…
28767 <description>Unspecified</description>
28772 <description>Unspecified</description>
28777 <description>Unspecified</description>
28782 <description>Unspecified</description>
28787 <description>Unspecified</description>
28792 <description>Unspecified</description>
28797 <description>Unspecified</description>
28804 …<description>The value of this register is derived from the DMAH_CH7_STW coreConsultant parameter.…
28811 <description>Unspecified</description>
28816 <description>Unspecified</description>
28821 <description>Unspecified</description>
28826 <description>Unspecified</description>
28831 <description>Unspecified</description>
28836 <description>Unspecified</description>
28841 <description>Unspecified</description>
28848 …<description>The value of this register is derived from the DMAH_CH7_STAT_DST coreConsultant param…
28855 <description>Unspecified</description>
28860 <description>Unspecified</description>
28867 …<description>The value of this register is derived from the DMAH_CH7_STAT_SRC coreConsultant param…
28874 <description>Unspecified</description>
28879 <description>Unspecified</description>
28886 …<description>The value of this register is derived from the DMAH_CH7_DST_SCA_EN coreConsultant par…
28893 <description>Unspecified</description>
28898 <description>Unspecified</description>
28905 …<description>The value of this register is derived from the DMAH_CH7_SRC_GAT_EN coreConsultant par…
28912 <description>Unspecified</description>
28917 <description>Unspecified</description>
28924 …<description>The value of this register is derived from the DMAH_CH7_LOCK_EN coreConsultant parame…
28931 <description>Unspecified</description>
28936 <description>Unspecified</description>
28943 …<description>The value of this register is derived from the DMAH_CH7_MULTI_BLK_EN coreConsultant p…
28950 <description>Unspecified</description>
28955 <description>Unspecified</description>
28962 …<description>The value of this register is derived from the DMAH_CH7_CTL_WB_EN coreConsultant para…
28969 <description>Unspecified</description>
28974 <description>Unspecified</description>
28981 …<description>The value of this register is derived from the DMAH_CH7_HC_LLP coreConsultant paramet…
28988 <description>Unspecified</description>
28993 <description>Unspecified</description>
29000 …<description>The value of this register is derived from the DMAH_CH7_FC coreConsultant parameter.<…
29007 <description>Unspecified</description>
29012 <description>Unspecified</description>
29017 <description>Unspecified</description>
29022 <description>Unspecified</description>
29029 …<description>The value of this register is derived from the DMAH_CH7_MULT_SIZE coreConsultant para…
29036 <description>Unspecified</description>
29041 <description>Unspecified</description>
29046 <description>Unspecified</description>
29051 <description>Unspecified</description>
29056 <description>Unspecified</description>
29061 <description>Unspecified</description>
29066 <description>Unspecified</description>
29073 …<description>The value of this register is derived from the DMAH_CH7_DMS coreConsultant parameter.…
29080 <description>Unspecified</description>
29085 <description>Unspecified</description>
29090 <description>Unspecified</description>
29095 <description>Unspecified</description>
29100 <description>Unspecified</description>
29107 …<description>The value of this register is derived from the DMAH_CH7_LMS coreConsultant parameter.…
29114 <description>Unspecified</description>
29119 <description>Unspecified</description>
29124 <description>Unspecified</description>
29129 <description>Unspecified</description>
29134 <description>Unspecified</description>
29141 …<description>The value of this register is derived from the DMAH_CH7_SMS coreConsultant parameter.…
29148 <description>Unspecified</description>
29153 <description>Unspecified</description>
29158 <description>Unspecified</description>
29163 <description>Unspecified</description>
29168 <description>Unspecified</description>
29175 …<description>The value of this register is derived from the DMAH_CH7_FIFO_DEPTH coreConsultant par…
29182 <description>Unspecified</description>
29187 <description>Unspecified</description>
29192 <description>Unspecified</description>
29197 <description>Unspecified</description>
29202 <description>Unspecified</description>
29207 <description>Unspecified</description>
29216 …description>DMA_COMP_PARAMS_5 is a constant read-only register that contains encoded information a…
29224 …<description>The value of this register is derived from the DMAH_CH6_DTW coreConsultant parameter.…
29231 <description>Unspecified</description>
29236 <description>Unspecified</description>
29241 <description>Unspecified</description>
29246 <description>Unspecified</description>
29251 <description>Unspecified</description>
29256 <description>Unspecified</description>
29261 <description>Unspecified</description>
29268 …<description>The value of this register is derived from the DMAH_CH6_STW coreConsultant parameter.…
29275 <description>Unspecified</description>
29280 <description>Unspecified</description>
29285 <description>Unspecified</description>
29290 <description>Unspecified</description>
29295 <description>Unspecified</description>
29300 <description>Unspecified</description>
29305 <description>Unspecified</description>
29312 …<description>The value of this register is derived from the DMAH_CH6_STAT_DST coreConsultant param…
29319 <description>Unspecified</description>
29324 <description>Unspecified</description>
29331 …<description>The value of this register is derived from the DMAH_CH6_STAT_SRC coreConsultant param…
29338 <description>Unspecified</description>
29343 <description>Unspecified</description>
29350 …<description>The value of this register is derived from the DMAH_CH6_DST_SCA_EN coreConsultant par…
29357 <description>Unspecified</description>
29362 <description>Unspecified</description>
29369 …<description>The value of this register is derived from the CH6_SRC_GAT_EN coreConsultant paramete…
29376 <description>Unspecified</description>
29381 <description>Unspecified</description>
29388 …<description>The value of this register is derived from the DMAH_CH6_LOCK_EN coreConsultant parame…
29395 <description>Unspecified</description>
29400 <description>Unspecified</description>
29407 …<description>The value of this register is derived from the DMAH_CH6_MULTI_BLK_EN coreConsultant p…
29414 <description>Unspecified</description>
29419 <description>Unspecified</description>
29426 …<description>The value of this register is derived from the DMAH_CH6_CTL_WB_EN coreConsultant para…
29433 <description>Unspecified</description>
29438 <description>Unspecified</description>
29445 …<description>The value of this register is derived from the DMAH_CH6_HC_LLP coreConsultant paramet…
29452 <description>Unspecified</description>
29457 <description>Unspecified</description>
29464 …<description>The value of this register is derived from the DMAH_CH6_FC coreConsultant parameter.<…
29471 <description>Unspecified</description>
29476 <description>Unspecified</description>
29481 <description>Unspecified</description>
29486 <description>Unspecified</description>
29493 …<description>The value of this register is derived from the DMAH_CH6_MULT_SIZE coreConsultant para…
29500 <description>Unspecified</description>
29505 <description>Unspecified</description>
29510 <description>Unspecified</description>
29515 <description>Unspecified</description>
29520 <description>Unspecified</description>
29525 <description>Unspecified</description>
29530 <description>Unspecified</description>
29537 …<description>The value of this register is derived from the DMAH_CH6_DMS coreConsultant parameter.…
29544 <description>Unspecified</description>
29549 <description>Unspecified</description>
29554 <description>Unspecified</description>
29559 <description>Unspecified</description>
29564 <description>Unspecified</description>
29571 …<description>The value of this register is derived from the DMAH_CH6_LMS coreConsultant parameter.…
29578 <description>Unspecified</description>
29583 <description>Unspecified</description>
29588 <description>Unspecified</description>
29593 <description>Unspecified</description>
29598 <description>Unspecified</description>
29605 …<description>The value of this register is derived from the DMAH_CH6_SMS coreConsultant parameter.…
29612 <description>Unspecified</description>
29617 <description>Unspecified</description>
29622 <description>Unspecified</description>
29627 <description>Unspecified</description>
29632 <description>Unspecified</description>
29639 …<description>The value of this register is derived from the DMAH_CH6_FIFO_DEPTH coreConsultant par…
29646 <description>Unspecified</description>
29651 <description>Unspecified</description>
29656 <description>Unspecified</description>
29661 <description>Unspecified</description>
29666 <description>Unspecified</description>
29671 <description>Unspecified</description>
29680 …description>DMA_COMP_PARAMS_5 is a constant read-only register that contains encoded information a…
29688 …<description>The value of this register is derived from the DMAH_CH5_DTW coreConsultant parameter.…
29695 <description>Unspecified</description>
29700 <description>Unspecified</description>
29705 <description>Unspecified</description>
29710 <description>Unspecified</description>
29715 <description>Unspecified</description>
29720 <description>Unspecified</description>
29725 <description>Unspecified</description>
29732 …<description>The value of this register is derived from the DMAH_CH5_STW coreConsultant parameter.…
29739 <description>Unspecified</description>
29744 <description>Unspecified</description>
29749 <description>Unspecified</description>
29754 <description>Unspecified</description>
29759 <description>Unspecified</description>
29764 <description>Unspecified</description>
29769 <description>Unspecified</description>
29776 …<description>The value of this register is derived from the DMAH_CH5_STAT_DST coreConsultant param…
29783 <description>Unspecified</description>
29788 <description>Unspecified</description>
29795 …<description>The value of this register is derived from the DMAH_CH5_STAT_SRC coreConsultant param…
29802 <description>Unspecified</description>
29807 <description>Unspecified</description>
29814 …<description>The value of this register is derived from the DMAH_CH5_DST_SCA_EN coreConsultant par…
29821 <description>Unspecified</description>
29826 <description>Unspecified</description>
29833 …<description>The value of this register is derived from the DMAH_CH5_SRC_GAT_EN coreConsultant par…
29840 <description>Unspecified</description>
29845 <description>Unspecified</description>
29852 …<description>The value of this register is derived from the DMAH_CH5_LOCK_EN coreConsultant parame…
29859 <description>Unspecified</description>
29864 <description>Unspecified</description>
29871 …<description>The value of this register is derived from the DMAH_CH5_MULTI_BLK_EN coreConsultant p…
29878 <description>Unspecified</description>
29883 <description>Unspecified</description>
29890 …<description>The value of this register is derived from the DMAH_CH5_CTL_WB_EN coreConsultant para…
29897 <description>Unspecified</description>
29902 <description>Unspecified</description>
29909 …<description>The value of this register is derived from the DMAH_CH5_HC_LLP coreConsultant paramet…
29916 <description>Unspecified</description>
29921 <description>Unspecified</description>
29928 …<description>The value of this register is derived from the DMAH_CH5_FC coreConsultant parameter.<…
29935 <description>Unspecified</description>
29940 <description>Unspecified</description>
29945 <description>Unspecified</description>
29950 <description>Unspecified</description>
29957 …<description>The value of this register is derived from the DMAH_CH5_MULT_SIZE coreConsultant para…
29964 <description>Unspecified</description>
29969 <description>Unspecified</description>
29974 <description>Unspecified</description>
29979 <description>Unspecified</description>
29984 <description>Unspecified</description>
29989 <description>Unspecified</description>
29994 <description>Unspecified</description>
30001 …<description>The value of this register is derived from the DMAH_CH5_DMS coreConsultant parameter.…
30008 <description>Unspecified</description>
30013 <description>Unspecified</description>
30018 <description>Unspecified</description>
30023 <description>Unspecified</description>
30028 <description>Unspecified</description>
30035 …<description>The value of this register is derived from the DMAH_CH5_LMS coreConsultant parameter.…
30042 <description>Unspecified</description>
30047 <description>Unspecified</description>
30052 <description>Unspecified</description>
30057 <description>Unspecified</description>
30062 <description>Unspecified</description>
30069 …<description>The value of this register is derived from the DMAH_CH5_SMS coreConsultant parameter.…
30076 <description>Unspecified</description>
30081 <description>Unspecified</description>
30086 <description>Unspecified</description>
30091 <description>Unspecified</description>
30096 <description>Unspecified</description>
30103 …<description>The value of this register is derived from the DMAH_CH5_FIFO_DEPTH coreConsultant par…
30110 <description>Unspecified</description>
30115 <description>Unspecified</description>
30120 <description>Unspecified</description>
30125 <description>Unspecified</description>
30130 <description>Unspecified</description>
30135 <description>Unspecified</description>
30144 …description>DMA_COMP_PARAMS_4 is a constant read-only register that contains encoded information a…
30152 …<description>The value of this register is derived from the DMAH_CH4_DTW coreConsultant parameter.…
30159 <description>Unspecified</description>
30164 <description>Unspecified</description>
30169 <description>Unspecified</description>
30174 <description>Unspecified</description>
30179 <description>Unspecified</description>
30184 <description>Unspecified</description>
30189 <description>Unspecified</description>
30196 …<description>The value of this register is derived from the DMAH_CH4_STW coreConsultant parameter.…
30203 <description>Unspecified</description>
30208 <description>Unspecified</description>
30213 <description>Unspecified</description>
30218 <description>Unspecified</description>
30223 <description>Unspecified</description>
30228 <description>Unspecified</description>
30233 <description>Unspecified</description>
30240 …<description>The value of this register is derived from the DMAH_CH4_STAT_DST coreConsultant param…
30247 <description>Unspecified</description>
30252 <description>Unspecified</description>
30259 …<description>The value of this register is derived from the DMAH_CH4_STAT_SRC coreConsultant param…
30266 <description>Unspecified</description>
30271 <description>Unspecified</description>
30278 …<description>The value of this register is derived from the DMAH_CH4_DST_SCA_EN coreConsultant par…
30285 <description>Unspecified</description>
30290 <description>Unspecified</description>
30297 …<description>The value of this register is derived from the DMAH_CH4_SRC_GAT_EN coreConsultant par…
30304 <description>Unspecified</description>
30309 <description>Unspecified</description>
30316 …<description>The value of this register is derived from the DMAH_CH4_LOCK_EN coreConsultant parame…
30323 <description>Unspecified</description>
30328 <description>Unspecified</description>
30335 …<description>The value of this register is derived from the DMAH_CH4_MULTI_BLK_EN coreConsultant p…
30342 <description>Unspecified</description>
30347 <description>Unspecified</description>
30354 …<description>The value of this register is derived from the DMAH_CH4_CTL_WB_EN coreConsultant para…
30361 <description>Unspecified</description>
30366 <description>Unspecified</description>
30373 …<description>The value of this register is derived from the DMAH_CH4_HC_LLP coreConsultant paramet…
30380 <description>Unspecified</description>
30385 <description>Unspecified</description>
30392 …<description>The value of this register is derived from the DMAH_CH4_FC coreConsultant parameter.<…
30399 <description>Unspecified</description>
30404 <description>Unspecified</description>
30409 <description>Unspecified</description>
30414 <description>Unspecified</description>
30421 …<description>The value of this register is derived from the DMAH_CH4_MULT_SIZE coreConsultant para…
30428 <description>Unspecified</description>
30433 <description>Unspecified</description>
30438 <description>Unspecified</description>
30443 <description>Unspecified</description>
30448 <description>Unspecified</description>
30453 <description>Unspecified</description>
30458 <description>Unspecified</description>
30465 …<description>The value of this register is derived from the DMAH_CH4_DMS coreConsultant parameter.…
30472 <description>Unspecified</description>
30477 <description>Unspecified</description>
30482 <description>Unspecified</description>
30487 <description>Unspecified</description>
30492 <description>Unspecified</description>
30499 …<description>The value of this register is derived from the DMAH_CH4_LMS coreConsultant parameter.…
30506 <description>Unspecified</description>
30511 <description>Unspecified</description>
30516 <description>Unspecified</description>
30521 <description>Unspecified</description>
30526 <description>Unspecified</description>
30533 …<description>The value of this register is derived from the DMAH_CH4_SMS coreConsultant parameter.…
30540 <description>Unspecified</description>
30545 <description>Unspecified</description>
30550 <description>Unspecified</description>
30555 <description>Unspecified</description>
30560 <description>Unspecified</description>
30567 …<description>The value of this register is derived from the DMAH_CH4_FIFO_DEPTH coreConsultant par…
30574 <description>Unspecified</description>
30579 <description>Unspecified</description>
30584 <description>Unspecified</description>
30589 <description>Unspecified</description>
30594 <description>Unspecified</description>
30599 <description>Unspecified</description>
30608 …description>DMA_COMP_PARAMS_4 is a constant read-only register that contains encoded information a…
30616 …<description>The value of this register is derived from the DMAH_CH3_DTW coreConsultant parameter.…
30623 <description>Unspecified</description>
30628 <description>Unspecified</description>
30633 <description>Unspecified</description>
30638 <description>Unspecified</description>
30643 <description>Unspecified</description>
30648 <description>Unspecified</description>
30653 <description>Unspecified</description>
30660 …<description>The value of this register is derived from the DMAH_CH3_STW coreConsultant parameter.…
30667 <description>Unspecified</description>
30672 <description>Unspecified</description>
30677 <description>Unspecified</description>
30682 <description>Unspecified</description>
30687 <description>Unspecified</description>
30692 <description>Unspecified</description>
30697 <description>Unspecified</description>
30704 …<description>The value of this register is derived from the DMAH_CH3_STAT_DST coreConsultant param…
30711 <description>Unspecified</description>
30716 <description>Unspecified</description>
30723 …<description>The value of this register is derived from the DMAH_CH3_STAT_SRC coreConsultant param…
30730 <description>Unspecified</description>
30735 <description>Unspecified</description>
30742 …<description>The value of this register is derived from the DMAH_CH3_DST_SCA_EN coreConsultant par…
30749 <description>Unspecified</description>
30754 <description>Unspecified</description>
30761 …<description>The value of this register is derived from the DMAH_CH3_SRC_GAT_EN coreConsultant par…
30768 <description>Unspecified</description>
30773 <description>Unspecified</description>
30780 …<description>The value of this register is derived from the DMAH_CH3_LOCK_EN coreConsultant parame…
30787 <description>Unspecified</description>
30792 <description>Unspecified</description>
30799 …<description>The value of this register is derived from the DMAH_CH3_MULTI_BLK_EN coreConsultant p…
30806 <description>Unspecified</description>
30811 <description>Unspecified</description>
30818 …<description>The value of this register is derived from the DMAH_CH3_CTL_WB_EN coreConsultant para…
30825 <description>Unspecified</description>
30830 <description>Unspecified</description>
30837 …<description>The value of this register is derived from the DMAH_CH3_HC_LLP coreConsultant paramet…
30844 <description>Unspecified</description>
30849 <description>Unspecified</description>
30856 …<description>The value of this register is derived from the DMAH_CH3_FC coreConsultant parameter.<…
30863 <description>Unspecified</description>
30868 <description>Unspecified</description>
30873 <description>Unspecified</description>
30878 <description>Unspecified</description>
30885 …<description>The value of this register is derived from the DMAH_CH3_MULT_SIZE coreConsultant para…
30892 <description>Unspecified</description>
30897 <description>Unspecified</description>
30902 <description>Unspecified</description>
30907 <description>Unspecified</description>
30912 <description>Unspecified</description>
30917 <description>Unspecified</description>
30922 <description>Unspecified</description>
30929 …<description>The value of this register is derived from the DMAH_CH3_DMS coreConsultant parameter.…
30936 <description>Unspecified</description>
30941 <description>Unspecified</description>
30946 <description>Unspecified</description>
30951 <description>Unspecified</description>
30956 <description>Unspecified</description>
30963 …<description>The value of this register is derived from the DMAH_CH3_LMS coreConsultant parameter.…
30970 <description>Unspecified</description>
30975 <description>Unspecified</description>
30980 <description>Unspecified</description>
30985 <description>Unspecified</description>
30990 <description>Unspecified</description>
30997 …<description>The value of this register is derived from the DMAH_CH3_SMS coreConsultant parameter.…
31004 <description>Unspecified</description>
31009 <description>Unspecified</description>
31014 <description>Unspecified</description>
31019 <description>Unspecified</description>
31024 <description>Unspecified</description>
31031 …<description>The value of this register is derived from the DMAH_CH3_FIFO_DEPTH coreConsultant par…
31038 <description>Unspecified</description>
31043 <description>Unspecified</description>
31048 <description>Unspecified</description>
31053 <description>Unspecified</description>
31058 <description>Unspecified</description>
31063 <description>Unspecified</description>
31072 …description>DMA_COMP_PARAMS_3 is a constant read-only register that contains encoded information a…
31080 …<description>The value of this register is derived from the DMAH_CH2_DTW coreConsultant parameter.…
31087 <description>Unspecified</description>
31092 <description>Unspecified</description>
31097 <description>Unspecified</description>
31102 <description>Unspecified</description>
31107 <description>Unspecified</description>
31112 <description>Unspecified</description>
31117 <description>Unspecified</description>
31124 …<description>The value of this register is derived from the DMAH_CH2_STW coreConsultant parameter.…
31131 <description>Unspecified</description>
31136 <description>Unspecified</description>
31141 <description>Unspecified</description>
31146 <description>Unspecified</description>
31151 <description>Unspecified</description>
31156 <description>Unspecified</description>
31161 <description>Unspecified</description>
31168 …<description>The value of this register is derived from the DMAH_CH2_STAT_DST coreConsultant param…
31175 <description>Unspecified</description>
31180 <description>Unspecified</description>
31187 …<description>The value of this register is derived from the DMAH_CH2_STAT_SRC coreConsultant param…
31194 <description>Unspecified</description>
31199 <description>Unspecified</description>
31206 …<description>The value of this register is derived from the DMAH_CH2_DST_SCA_EN coreConsultant par…
31213 <description>Unspecified</description>
31218 <description>Unspecified</description>
31225 …<description>The value of this register is derived from the DMAH_CH2_SRC_GAT_EN coreConsultant par…
31232 <description>Unspecified</description>
31237 <description>Unspecified</description>
31244 …<description>The value of this register is derived from the DMAH_CH2_LOCK_EN coreConsultant parame…
31251 <description>Unspecified</description>
31256 <description>Unspecified</description>
31263 …<description>The value of this register is derived from the DMAH_CH2_MULTI_BLK_EN coreConsultant p…
31270 <description>Unspecified</description>
31275 <description>Unspecified</description>
31282 …<description>The value of this register is derived from the DMAH_CH2_CTL_WB_EN coreConsultant para…
31289 <description>Unspecified</description>
31294 <description>Unspecified</description>
31301 …<description>The value of this register is derived from the DMAH_CH2_HC_LLP coreConsultant paramet…
31308 <description>Unspecified</description>
31313 <description>Unspecified</description>
31320 …<description>The value of this register is derived from the DMAH_CH2_FC coreConsultant parameter.<…
31327 <description>Unspecified</description>
31332 <description>Unspecified</description>
31337 <description>Unspecified</description>
31342 <description>Unspecified</description>
31349 …<description>The value of this register is derived from the DMAH_CH2_MULT_SIZE coreConsultant para…
31356 <description>Unspecified</description>
31361 <description>Unspecified</description>
31366 <description>Unspecified</description>
31371 <description>Unspecified</description>
31376 <description>Unspecified</description>
31381 <description>Unspecified</description>
31386 <description>Unspecified</description>
31393 …<description>The value of this register is derived from the DMAH_CH2_DMS coreConsultant parameter.…
31400 <description>Unspecified</description>
31405 <description>Unspecified</description>
31410 <description>Unspecified</description>
31415 <description>Unspecified</description>
31420 <description>Unspecified</description>
31427 …<description>The value of this register is derived from the DMAH_CH2_LMS coreConsultant parameter.…
31434 <description>Unspecified</description>
31439 <description>Unspecified</description>
31444 <description>Unspecified</description>
31449 <description>Unspecified</description>
31454 <description>Unspecified</description>
31461 …<description>The value of this register is derived from the DMAH_CH2_SMS coreConsultant parameter.…
31468 <description>Unspecified</description>
31473 <description>Unspecified</description>
31478 <description>Unspecified</description>
31483 <description>Unspecified</description>
31488 <description>Unspecified</description>
31495 …<description>The value of this register is derived from the DMAH_CH2_FIFO_DEPTH coreConsultant par…
31502 <description>Unspecified</description>
31507 <description>Unspecified</description>
31512 <description>Unspecified</description>
31517 <description>Unspecified</description>
31522 <description>Unspecified</description>
31527 <description>Unspecified</description>
31536 …description>DMA_COMP_PARAMS_3 is a constant read-only register that contains encoded information a…
31544 …<description>The value of this register is derived from the DMAH_CH1_DTW coreConsultant parameter.…
31551 <description>Unspecified</description>
31556 <description>Unspecified</description>
31561 <description>Unspecified</description>
31566 <description>Unspecified</description>
31571 <description>Unspecified</description>
31576 <description>Unspecified</description>
31581 <description>Unspecified</description>
31588 …<description>The value of this register is derived from the DMAH_CH1_STW coreConsultant parameter.…
31595 <description>Unspecified</description>
31600 <description>Unspecified</description>
31605 <description>Unspecified</description>
31610 <description>Unspecified</description>
31615 <description>Unspecified</description>
31620 <description>Unspecified</description>
31625 <description>Unspecified</description>
31632 …<description>The value of this register is derived from the DMAH_CH1_STAT_DST coreConsultant param…
31639 <description>Unspecified</description>
31644 <description>Unspecified</description>
31651 …<description>The value of this register is derived from the DMAH_CH1_STAT_SRC coreConsultant param…
31658 <description>Unspecified</description>
31663 <description>Unspecified</description>
31670 …<description>The value of this register is derived from the DMAH_CH1_DST_SCA_EN coreConsultant par…
31677 <description>Unspecified</description>
31682 <description>Unspecified</description>
31689 …<description>The value of this register is derived from the DMAH_CH1_SRC_GAT_EN coreConsultant par…
31696 <description>Unspecified</description>
31701 <description>Unspecified</description>
31708 …<description>The value of this register is derived from the DMAH_CH1_LOCK_EN coreConsultant parame…
31715 <description>Unspecified</description>
31720 <description>Unspecified</description>
31727 …<description>The value of this register is derived from the DMAH_CH1_MULTI_BLK_EN coreConsultant p…
31734 <description>Unspecified</description>
31739 <description>Unspecified</description>
31746 …<description>The value of this register is derived from the DMAH_CH1_CTL_WB_EN coreConsultant para…
31753 <description>Unspecified</description>
31758 <description>Unspecified</description>
31765 …<description>The value of this register is derived from the DMAH_CH1_HC_LLP coreConsultant paramet…
31772 <description>Unspecified</description>
31777 <description>Unspecified</description>
31784 …<description>The value of this register is derived from the DMAH_CH1_FC coreConsultant parameter.<…
31791 <description>Unspecified</description>
31796 <description>Unspecified</description>
31801 <description>Unspecified</description>
31806 <description>Unspecified</description>
31813 …<description>The value of this register is derived from the DMAH_CH1_MULT_SIZE coreConsultant para…
31820 <description>Unspecified</description>
31825 <description>Unspecified</description>
31830 <description>Unspecified</description>
31835 <description>Unspecified</description>
31840 <description>Unspecified</description>
31845 <description>Unspecified</description>
31850 <description>Unspecified</description>
31857 …<description>The value of this register is derived from the DMAH_CH1_DMS coreConsultant parameter.…
31864 <description>Unspecified</description>
31869 <description>Unspecified</description>
31874 <description>Unspecified</description>
31879 <description>Unspecified</description>
31884 <description>Unspecified</description>
31891 …<description>The value of this register is derived from the DMAH_CH1_LMS coreConsultant parameter.…
31898 <description>Unspecified</description>
31903 <description>Unspecified</description>
31908 <description>Unspecified</description>
31913 <description>Unspecified</description>
31918 <description>Unspecified</description>
31925 …<description>The value of this register is derived from the DMAH_CH1_SMS coreConsultant parameter.…
31932 <description>Unspecified</description>
31937 <description>Unspecified</description>
31942 <description>Unspecified</description>
31947 <description>Unspecified</description>
31952 <description>Unspecified</description>
31959 …<description>The value of this register is derived from the DMAH_CH1_FIFO_DEPTH coreConsultant par…
31966 <description>Unspecified</description>
31971 <description>Unspecified</description>
31976 <description>Unspecified</description>
31981 <description>Unspecified</description>
31986 <description>Unspecified</description>
31991 <description>Unspecified</description>
32000 …<description>DMA_COMP_PARAMS_2 is a constant read-only register that contains encoded information …
32008 …<description>The value of this register is derived from the DMAH_CH0_DTW coreConsultant parameter.…
32015 <description>Unspecified</description>
32020 <description>Unspecified</description>
32025 <description>Unspecified</description>
32030 <description>Unspecified</description>
32035 <description>Unspecified</description>
32040 <description>Unspecified</description>
32045 <description>Unspecified</description>
32052 …<description>The value of this register is derived from the DMAH_CH0_STW coreConsultant parameter.…
32059 <description>Unspecified</description>
32064 <description>Unspecified</description>
32069 <description>Unspecified</description>
32074 <description>Unspecified</description>
32079 <description>Unspecified</description>
32084 <description>Unspecified</description>
32089 <description>Unspecified</description>
32096 …<description>The value of this register is derived from the DMAH_CH0_STAT_DST coreConsultant param…
32103 <description>Unspecified</description>
32108 <description>Unspecified</description>
32115 …<description>The value of this register is derived from the DMAH_CH0_STAT_SRC coreConsultant param…
32122 <description>Unspecified</description>
32127 <description>Unspecified</description>
32134 …<description>The value of this register is derived from the DMAH_CH0_DST_SCA_EN coreConsultant par…
32141 <description>Unspecified</description>
32146 <description>Unspecified</description>
32153 …<description>The value of this register is derived from the DMAH_CH0_SRC_GAT_EN coreConsultant par…
32160 <description>Unspecified</description>
32165 <description>Unspecified</description>
32172 …<description>The value of this register is derived from the DMAH_CH0_LOCK_EN coreConsultant parame…
32179 <description>Unspecified</description>
32184 <description>Unspecified</description>
32191 …<description>The value of this register is derived from the DMAH_CH0_MULTI_BLK_EN coreConsultant p…
32198 <description>Unspecified</description>
32203 <description>Unspecified</description>
32210 …<description>The value of this register is derived from the DMAH_CH0_CTL_WB_EN coreConsultant para…
32217 <description>Unspecified</description>
32222 <description>Unspecified</description>
32229 …<description>The value of this register is derived from the DMAH_CH0_HC_LLP coreConsultant paramet…
32236 <description>Unspecified</description>
32241 <description>Unspecified</description>
32248 …<description>The value of this register is derived from the DMAH_CH0_FC coreConsultant parameter.<…
32255 <description>Unspecified</description>
32260 <description>Unspecified</description>
32265 <description>Unspecified</description>
32270 <description>Unspecified</description>
32277 …<description>The value of this register is derived from the DMAH_CH0_MULT_SIZE coreConsultant para…
32284 <description>Unspecified</description>
32289 <description>Unspecified</description>
32294 <description>Unspecified</description>
32299 <description>Unspecified</description>
32304 <description>Unspecified</description>
32309 <description>Unspecified</description>
32314 <description>Unspecified</description>
32321 …<description>The value of this register is derived from the DMAH_CH0_DMS coreConsultant parameter.…
32328 <description>Unspecified</description>
32333 <description>Unspecified</description>
32338 <description>Unspecified</description>
32343 <description>Unspecified</description>
32348 <description>Unspecified</description>
32355 …<description>The value of this register is derived from the DMAH_CH0_LMS coreConsultant parameter.…
32362 <description>Unspecified</description>
32367 <description>Unspecified</description>
32372 <description>Unspecified</description>
32377 <description>Unspecified</description>
32382 <description>Unspecified</description>
32389 …<description>The value of this register is derived from the DMAH_CH0_SMS coreConsultant parameter.…
32396 <description>Unspecified</description>
32401 <description>Unspecified</description>
32406 <description>Unspecified</description>
32411 <description>Unspecified</description>
32416 <description>Unspecified</description>
32423 …<description>The value of this register is derived from the DMAH_CH0_FIFO_DEPTH coreConsultant par…
32430 <description>Unspecified</description>
32435 <description>Unspecified</description>
32440 <description>Unspecified</description>
32445 <description>Unspecified</description>
32450 <description>Unspecified</description>
32455 <description>Unspecified</description>
32464 …<description>DMA_COMP_PARAMS_2 is a constant read-only register that contains encoded information …
32472 …<description>The values of these bit fields are derived from the DMAH_CH0_MULTI_BLK_TYPE coreConsu…
32479 <description>Unspecified</description>
32484 <description>Unspecified</description>
32489 <description>Unspecified</description>
32494 <description>Unspecified</description>
32499 <description>Unspecified</description>
32504 <description>Unspecified</description>
32509 <description>Unspecified</description>
32514 <description>Unspecified</description>
32519 <description>Unspecified</description>
32526 …<description>The values of these bit fields are derived from the DMAH_CH1_MULTI_BLK_TYPE coreConsu…
32533 <description>Unspecified</description>
32538 <description>Unspecified</description>
32543 <description>Unspecified</description>
32548 <description>Unspecified</description>
32553 <description>Unspecified</description>
32558 <description>Unspecified</description>
32563 <description>Unspecified</description>
32568 <description>Unspecified</description>
32573 <description>Unspecified</description>
32580 …<description>The values of these bit fields are derived from the DMAH_CH2_MULTI_BLK_TYPE coreConsu…
32587 <description>Unspecified</description>
32592 <description>Unspecified</description>
32597 <description>Unspecified</description>
32602 <description>Unspecified</description>
32607 <description>Unspecified</description>
32612 <description>Unspecified</description>
32617 <description>Unspecified</description>
32622 <description>Unspecified</description>
32627 <description>Unspecified</description>
32634 …<description>The values of these bit fields are derived from the DMAH_CH3_MULTI_BLK_TYPE coreConsu…
32641 <description>Unspecified</description>
32646 <description>Unspecified</description>
32651 <description>Unspecified</description>
32656 <description>Unspecified</description>
32661 <description>Unspecified</description>
32666 <description>Unspecified</description>
32671 <description>Unspecified</description>
32676 <description>Unspecified</description>
32681 <description>Unspecified</description>
32688 …<description>The values of these bit fields are derived from the DMAH_CH4_MULTI_BLK_TYPE coreConsu…
32695 <description>Unspecified</description>
32700 <description>Unspecified</description>
32705 <description>Unspecified</description>
32710 <description>Unspecified</description>
32715 <description>Unspecified</description>
32720 <description>Unspecified</description>
32725 <description>Unspecified</description>
32730 <description>Unspecified</description>
32735 <description>Unspecified</description>
32742 …<description>The values of these bit fields are derived from the DMAH_CH5_MULTI_BLK_TYPE coreConsu…
32749 <description>Unspecified</description>
32754 <description>Unspecified</description>
32759 <description>Unspecified</description>
32764 <description>Unspecified</description>
32769 <description>Unspecified</description>
32774 <description>Unspecified</description>
32779 <description>Unspecified</description>
32784 <description>Unspecified</description>
32789 <description>Unspecified</description>
32796 …<description>The values of these bit fields are derived from the DMAH_CH6_MULTI_BLK_TYPE coreConsu…
32803 <description>Unspecified</description>
32808 <description>Unspecified</description>
32813 <description>Unspecified</description>
32818 <description>Unspecified</description>
32823 <description>Unspecified</description>
32828 <description>Unspecified</description>
32833 <description>Unspecified</description>
32838 <description>Unspecified</description>
32843 <description>Unspecified</description>
32850 …<description>The values of these bit fields are derived from the DMAH_CH7_MULTI_BLK_TYPE coreConsu…
32857 <description>Unspecified</description>
32862 <description>Unspecified</description>
32867 <description>Unspecified</description>
32872 <description>Unspecified</description>
32877 <description>Unspecified</description>
32882 <description>Unspecified</description>
32887 <description>Unspecified</description>
32892 <description>Unspecified</description>
32897 <description>Unspecified</description>
32906 …<description>DMA_COMP_PARAMS_1 is a constant read-only register that contains encoded information …
32914 …<description>The values of these bit fields are derived from the DMAH_CH0_MAX_BLK_SIZE coreConsult…
32921 <description>Unspecified</description>
32926 <description>Unspecified</description>
32931 <description>Unspecified</description>
32936 <description>Unspecified</description>
32941 <description>Unspecified</description>
32946 <description>Unspecified</description>
32951 <description>Unspecified</description>
32956 <description>Unspecified</description>
32961 <description>Unspecified</description>
32966 <description>Unspecified</description>
32971 <description>Unspecified</description>
32978 …<description>The values of these bit fields are derived from the DMAH_CH1_MAX_BLK_SIZE coreConsult…
32985 <description>Unspecified</description>
32990 <description>Unspecified</description>
32995 <description>Unspecified</description>
33000 <description>Unspecified</description>
33005 <description>Unspecified</description>
33010 <description>Unspecified</description>
33015 <description>Unspecified</description>
33020 <description>Unspecified</description>
33025 <description>Unspecified</description>
33030 <description>Unspecified</description>
33035 <description>Unspecified</description>
33042 …<description>The values of these bit fields are derived from the DMAH_CH2_MAX_BLK_SIZE coreConsult…
33049 <description>Unspecified</description>
33054 <description>Unspecified</description>
33059 <description>Unspecified</description>
33064 <description>Unspecified</description>
33069 <description>Unspecified</description>
33074 <description>Unspecified</description>
33079 <description>Unspecified</description>
33084 <description>Unspecified</description>
33089 <description>Unspecified</description>
33094 <description>Unspecified</description>
33099 <description>Unspecified</description>
33106 …<description>The values of these bit fields are derived from the DMAH_CH3_MAX_BLK_SIZE coreConsult…
33113 <description>Unspecified</description>
33118 <description>Unspecified</description>
33123 <description>Unspecified</description>
33128 <description>Unspecified</description>
33133 <description>Unspecified</description>
33138 <description>Unspecified</description>
33143 <description>Unspecified</description>
33148 <description>Unspecified</description>
33153 <description>Unspecified</description>
33158 <description>Unspecified</description>
33163 <description>Unspecified</description>
33170 …<description>The values of these bit fields are derived from the DMAH_CH4_MAX_BLK_SIZE coreConsult…
33177 <description>Unspecified</description>
33182 <description>Unspecified</description>
33187 <description>Unspecified</description>
33192 <description>Unspecified</description>
33197 <description>Unspecified</description>
33202 <description>Unspecified</description>
33207 <description>Unspecified</description>
33212 <description>Unspecified</description>
33217 <description>Unspecified</description>
33222 <description>Unspecified</description>
33227 <description>Unspecified</description>
33234 …<description>The values of these bit fields are derived from the DMAH_CH5_MAX_BLK_SIZE coreConsult…
33241 <description>Unspecified</description>
33246 <description>Unspecified</description>
33251 <description>Unspecified</description>
33256 <description>Unspecified</description>
33261 <description>Unspecified</description>
33266 <description>Unspecified</description>
33271 <description>Unspecified</description>
33276 <description>Unspecified</description>
33281 <description>Unspecified</description>
33286 <description>Unspecified</description>
33291 <description>Unspecified</description>
33298 …<description>The values of these bit fields are derived from the DMAH_CH6_MAX_BLK_SIZE coreConsult…
33305 <description>Unspecified</description>
33310 <description>Unspecified</description>
33315 <description>Unspecified</description>
33320 <description>Unspecified</description>
33325 <description>Unspecified</description>
33330 <description>Unspecified</description>
33335 <description>Unspecified</description>
33340 <description>Unspecified</description>
33345 <description>Unspecified</description>
33350 <description>Unspecified</description>
33355 <description>Unspecified</description>
33362 …<description>The values of these bit fields are derived from the DMAH_CH7_MAX_BLK_SIZE coreConsult…
33369 <description>Unspecified</description>
33374 <description>Unspecified</description>
33379 <description>Unspecified</description>
33384 <description>Unspecified</description>
33389 <description>Unspecified</description>
33394 <description>Unspecified</description>
33399 <description>Unspecified</description>
33404 <description>Unspecified</description>
33409 <description>Unspecified</description>
33414 <description>Unspecified</description>
33419 <description>Unspecified</description>
33428 …<description>DMA_COMP_PARAMS_1 is a constant read-only register that contains encoded information …
33436 …<description>The value of this register is derived from the DMAH_BIG_ENDIAN coreConsultant paramet…
33443 <description>Unspecified</description>
33448 <description>Unspecified</description>
33455 …<description>The value of this register is derived from the DMAH_INTR_IO coreConsultant parameter.…
33462 <description>Unspecified</description>
33467 <description>Unspecified</description>
33472 <description>Unspecified</description>
33479 …<description>The value of this register is derived from the DMAH_MABRST coreConsultant parameter.<…
33486 <description>Unspecified</description>
33491 <description>Unspecified</description>
33498 <description>Reserved field- read-only</description>
33505 …<description>The value of this register is derived from the DMAH_NUM_CHANNELS coreConsultant param…
33512 <description>Unspecified</description>
33517 <description>Unspecified</description>
33522 <description>Unspecified</description>
33527 <description>Unspecified</description>
33532 <description>Unspecified</description>
33537 <description>Unspecified</description>
33542 <description>Unspecified</description>
33547 <description>Unspecified</description>
33554 …<description>The value of this register is derived from the DMAH_NUM_MASTER_INT coreConsultant par…
33561 <description>Unspecified</description>
33566 <description>Unspecified</description>
33571 <description>Unspecified</description>
33576 <description>Unspecified</description>
33583 …<description>The value of this register is derived from the DMAH_S_HDATA_WIDTH coreConsultant para…
33590 <description>Unspecified</description>
33595 <description>Unspecified</description>
33600 <description>Unspecified</description>
33605 <description>Unspecified</description>
33612 …<description>The value of this register is derived from the DMAH_M4_HDATA_WIDTH coreConsultant par…
33619 <description>Unspecified</description>
33624 <description>Unspecified</description>
33629 <description>Unspecified</description>
33634 <description>Unspecified</description>
33641 …<description>The value of this register is derived from the DMAH_M3_HDATA_WIDTH coreConsultant par…
33648 <description>Unspecified</description>
33653 <description>Unspecified</description>
33658 <description>Unspecified</description>
33663 <description>Unspecified</description>
33670 …<description>The value of this register is derived from the DMAH_M2_HDATA_WIDTH coreConsultant par…
33677 <description>Unspecified</description>
33682 <description>Unspecified</description>
33687 <description>Unspecified</description>
33692 <description>Unspecified</description>
33699 …<description>The value of this register is derived from the DMAH_M1_HDATA_WIDTH coreConsultant par…
33706 <description>Unspecified</description>
33711 <description>Unspecified</description>
33716 <description>Unspecified</description>
33721 <description>Unspecified</description>
33728 …<description>The value of this register is derived from the DMAH_NUM_HS_INT coreConsultant paramet…
33735 <description>Unspecified</description>
33740 <description>Unspecified</description>
33745 <description>Unspecified</description>
33750 <description>Unspecified</description>
33755 <description>Unspecified</description>
33760 <description>Unspecified</description>
33765 <description>Unspecified</description>
33770 <description>Unspecified</description>
33775 <description>Unspecified</description>
33780 <description>Unspecified</description>
33785 <description>Unspecified</description>
33790 <description>Unspecified</description>
33795 <description>Unspecified</description>
33800 <description>Unspecified</description>
33805 <description>Unspecified</description>
33810 <description>Unspecified</description>
33815 <description>Unspecified</description>
33822 …<description>The value of this register is derived from the DMAH_ADD_ENCODED_PARAMS coreConsultant…
33829 <description>Unspecified</description>
33834 <description>Unspecified</description>
33841 …<description>The value of this register is derived from the DMAH_STATIC_ENDIAN_SELECT coreConsulta…
33850 …<description>This is the DW_ahb_dmac Component Version register, which is a read-only register tha…
33858 <description>DMA Component Type Number = `h44571110.</description>
33867 …description>This is the DW_ahb_dmac Component Version register, which is a read-only register that…
33875 <description>DMA Component Version.</description>
33888 <description>I3CCORE 1</description>
33895 <description>MCAN</description>
33910 <description>Endian Register</description>
33918 <description>Endianness Test Value</description>
33926 <description>Data Bit Timing and Prescaler Register</description>
33934 <description>Data (Re)Synchronization Jump Width</description>
33940 <description>Data time segment after sample point</description>
33946 <description>Data time segment before sample point</description>
33952 <description>Data Bit Rate Prescaler</description>
33958 <description>Transmitter Delay Compensation</description>
33964 <description>Unspecified</description>
33969 <description>Unspecified</description>
33978 <description>Test Register</description>
33986 <description>Loop Back Mode</description>
33992 <description>Loop Back Mode is disabled</description>
33997 <description>Loop Back Mode is enabled</description>
34004 <description>Control of Transmit Pin</description>
34010 … <description>controlled by the CAN Core, updated at the end of the CAN bit time</description>
34015 <description>Sample Point can be monitored at pin m_can_tx</description>
34020 <description>Dominant (0) level at pin m_can_tx</description>
34025 <description>Recessive (1) at pin m_can_tx</description>
34032 <description>Receive Pin</description>
34038 <description>The CAN bus is dominant (m_can_rx = 0)</description>
34043 <description>The CAN bus is recessive (m_can_rx = '1')</description>
34050 <description>Tx Buffer Number Prepared</description>
34056 <description>Prepared Valid</description>
34062 <description>Value of TXBNP not valid</description>
34067 <description>Value of TXBNP valid</description>
34074 <description>Tx Buffer Number Started</description>
34080 <description>Started Valid</description>
34086 <description>Value of TXBNP not valid</description>
34091 <description>Value of TXBNP valid</description>
34100 <description>RAM Watchdog</description>
34108 …<description>Start value of the Message RAM Watchdog Counter. With the reset value of '00' the cou…
34109 disabled.</description>
34115 <description>Actual Message RAM Watchdog Counter Value.</description>
34123 <description>CC Control Register</description>
34131 <description>Initialization</description>
34137 <description>Normal Operation</description>
34142 <description>Initialization is started</description>
34149 <description>Configuration Change Enable</description>
34155 … <description>The CPU has no write access to the protected configuration registers</description>
34160 …<description>The CPU has write access to the protected configuration registers (while CCCR.INIT = …
34167 <description>Restricted Operation Mode</description>
34173 <description>Normal CAN operation</description>
34178 <description>Restricted Operation Mode active</description>
34185 <description>Clock Stop Acknowledge</description>
34191 <description>No clock stop acknowledged</description>
34196 … <description>MCAN may be set in power down by stopping m_can_hclk and m_can_cclk</description>
34203 <description>Clock Stop Request</description>
34209 <description>No clock stop is requested</description>
34214 <description>Clock stop requested.</description>
34221 <description>Bus Monitoring Mode</description>
34227 <description>Bus Monitoring Mode is disabled</description>
34232 <description>Bus Monitoring Mode is enabled</description>
34239 <description>Disable Automatic Retransmission</description>
34245 …<description>Automatic retransmission of messages not transmitted successfully enabled</descriptio…
34250 <description>Automatic retransmission disabled</description>
34257 <description>Test Mode Enable</description>
34263 <description>Normal operation, register TEST holds reset values</description>
34268 <description>Test Mode, write access to register TEST enabled</description>
34275 <description>FD Operation Enable</description>
34281 <description>FD operation disabled</description>
34286 <description>FD operation enabled</description>
34293 <description>Bit Rate Switch Enable</description>
34299 <description>Bit rate switching for transmissions disabled</description>
34304 <description>Bit rate switching for transmissions enabled</description>
34311 <description>Wide Message Marker</description>
34317 <description>8-bit Message Marker used</description>
34322 …<description>16-bit Message Marker used, replacing 16-bit timestamps in Tx Event FIFO</description>
34329 <description>Protocol Exception Handling Disable</description>
34335 <description>Protocol exception handling enabled</description>
34340 <description>Protocol exception handling disabled</description>
34347 <description>Edge Filtering during Bus Integration</description>
34353 <description>Edge filtering disabled</description>
34358 …<description>Two consecutive dominant tq required to detect an edge for hard synchronization</desc…
34365 <description>Transmit Pause</description>
34371 <description>Transmit pause disabled</description>
34376 <description>Transmit pause enabled</description>
34383 <description>Non ISO Operation</description>
34389 <description>CAN FD frame format according to ISO 11898-1:2015</description>
34394 … <description>CAN FD frame format according to Bosch CAN FD Specification V1.0</description>
34403 <description>Nominal Bit Timing and Prescaler Register</description>
34411 <description>Nominal Time segment after sample point</description>
34417 <description>Nominal Time segment before sample point</description>
34423 <description>Nominal Bit Rate Prescaler</description>
34429 <description>Nominal (Re)Synchronization Jump Width</description>
34437 <description>Timestamp Counter Configuration</description>
34445 <description>Timestamp Select</description>
34451 <description>Timestamp counter value always 0x0000</description>
34456 <description>Timestamp counter value incremented according to TCP</description>
34461 <description>External timestamp counter value used</description>
34466 <description>Same as Zero</description>
34473 <description>Timestamp Counter Prescaler</description>
34481 <description>Timestamp Counter Value</description>
34489 <description>Timestamp Counter</description>
34497 <description>Timeout Counter Configuration</description>
34505 <description>Enable Timeout Counter</description>
34511 <description>Timeout Counter disabled</description>
34516 <description>Timeout Counter enabled</description>
34523 <description>Timeout Select</description>
34529 <description>Continuous operation</description>
34534 <description>Timeout controlled by Tx Event FIFO</description>
34539 <description>Timeout controlled by Rx FIFO 0</description>
34544 <description>Timeout controlled by Rx FIFO 1</description>
34551 <description>Timeout Period</description>
34559 <description>Timeout Counter Value</description>
34567 <description>Timeout Counter</description>
34575 <description>Error Counter Register</description>
34583 <description>Transmit Error Counter</description>
34589 <description>Receive Error Counter</description>
34595 <description>Receive Error Passive</description>
34601 … <description>The Receive Error Counter is below the error passive level of 128</description>
34606 … <description>The Receive Error Counter has reached the error passive level of 128</description>
34613 <description>CAN Error Logging</description>
34621 <description>Protocol Status Register</description>
34629 <description>Last Error Code</description>
34635 …<description>No error occurred since LEC has been reset by successful reception or transmission.</…
34640 … <description>More than 5 equal bits in a sequence have occurred in a part of a received message
34641 where this is not allowed.</description>
34646 … <description>A fixed format part of a received frame has the wrong format.</description>
34651 …<description>The message transmitted by the MCAN was not acknowledged by another node.</descriptio…
34656 … <description>During the transmission of a message (with the exception of the arbitration field),
34658 value was dominant.</description>
34663 … <description>During the transmission of a message (or acknowledge bit, or active error flag, or
34668 dominant or continuously disturbed).</description>
34673 … <description>The CRC check sum of a received message was incorrect. The CRC of an incoming
34674 message does not match with the CRC calculated from the received data.</description>
34679 … <description>Any read access to the Protocol Status Register re-initializes the LEC to '7'.
34681 access to the Protocol Status Register.</description>
34688 <description>Activity</description>
34694 <description>Node is synchronizing on CAN communication</description>
34699 <description>Node is neither receiver nor tr ansmitter</description>
34704 <description>Node is operating as receiver</description>
34709 <description>Node is operating as transmitter</description>
34716 <description>Error Passive</description>
34722 …<description>The MCAN is in the Error_Active state. It normally takes part in bus communication and
34723 sends an active error flag when an error has been detected</description>
34728 <description>The MCAN is in the Error_Passive state</description>
34735 <description>Warning Status</description>
34741 … <description>Both error counters are below the Error_Warning limit of 96</description>
34746 … <description>At least one of error counter has reached the Error_Warning limit of 96</description>
34753 <description>Bus_Off Status</description>
34759 <description>The MCAN is not Bus_Off</description>
34764 <description>The MCAN is in Bus_Off state</description>
34771 <description>Data Phase Last Error Code</description>
34777 <description>ESI flag of last received CAN FD Message</description>
34783 … <description>Last received CAN FD message did not ha ve its ESI flag set</description>
34788 <description>Last received CAN FD message had its ESI flag set</description>
34795 <description>BRS flag of last received CAN FD Message</description>
34801 … <description>Last received CAN FD message did not ha ve its BRS flag set</description>
34806 <description>Last received CAN FD message had its BRS flag set</description>
34813 <description>Received a CAN FD Message</description>
34819 …<description>Since this bit was reset by the CPU, no CAN FD message has been received</description>
34824 … <description>Message in CAN FD format with FDF flag set has been received</description>
34831 <description>Protocol Exception Event</description>
34837 … <description>No protocol exception event occurred since last read access</description>
34842 <description>Protocol exception event occurred</description>
34849 <description>Transmitter Delay Compensation Value</description>
34857 <description>Transmitter Delay Compensation Register</description>
34865 <description>Transmitter Delay Compensation Filter Window Length</description>
34871 <description>Transmitter Delay Compensation SSP Offset</description>
34879 <description>Interrupt Register</description>
34887 <description>Rx FIFO 0 New Message</description>
34893 <description>Write '1' to clear interrupt flag</description>
34898 <description>No new message written to Rx FIFO 0</description>
34903 <description>New message written to Rx FIFO 0</description>
34910 <description>Rx FIFO 0 Watermark Reached</description>
34916 <description>Write '1' to clear interrupt flag</description>
34921 <description>Rx FIFO 0 fill level below watermark</description>
34926 <description>Rx FIFO 0 fill level reached watermark</description>
34933 <description>Rx FIFO 0 Full</description>
34939 <description>Write '1' to clear interrupt flag</description>
34944 <description>Rx FIFO 0 not full</description>
34949 <description>Rx FIFO 0 full</description>
34956 <description>Rx FIFO 0 Message Lost</description>
34962 <description>Write '1' to clear interrupt flag</description>
34967 <description>No Rx FIFO 0 message lost</description>
34972 …<description>Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero</descr…
34979 <description>Rx FIFO 1 New Message</description>
34985 <description>Write '1' to clear interrupt flag</description>
34990 <description>No new message written to Rx FIFO 1</description>
34995 <description>New message written to Rx FIFO 1</description>
35002 <description>Rx FIFO 1 Watermark Reached</description>
35008 <description>Write '1' to clear interrupt flag</description>
35013 <description>Rx FIFO 1 fill level below watermark</description>
35018 <description>Rx FIFO 1 fill level reached watermark</description>
35025 <description>Rx FIFO 1 Full</description>
35031 <description>Write '1' to clear interrupt flag</description>
35036 <description>Rx FIFO 1 not full</description>
35041 <description>Rx FIFO 1 full</description>
35048 <description>Rx FIFO 1 Message Lost</description>
35054 <description>Write '1' to clear interrupt flag</description>
35059 <description>No Rx FIFO 1 message lost</description>
35064 …<description>Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero</descr…
35071 <description>High Priority Message</description>
35077 <description>Write '1' to clear interrupt flag</description>
35082 <description>No high priority message received</description>
35087 <description>High priority message received</description>
35094 <description>Transmission Completed</description>
35100 <description>Write '1' to clear interrupt flag</description>
35105 <description>No transmission completed</description>
35110 <description>Transmission completed</description>
35117 <description>Transmission Cancellation Finished</description>
35123 <description>Write '1' to clear interrupt flag</description>
35128 <description>No transmission cancellation finished</description>
35133 <description>Transmission cancellation finished</description>
35140 <description>Tx FIFO Empty</description>
35146 <description>Write '1' to clear interrupt flag</description>
35151 <description>Tx FIFO non-empty</description>
35156 <description>Tx FIFO empty</description>
35163 <description>Tx Event FIFO New Entry</description>
35169 <description>Write '1' to clear interrupt flag</description>
35174 <description>Tx Event FIFO unchanged</description>
35179 <description>Tx Handler wrote Tx Event FIFO element</description>
35186 <description>Tx Event FIFO Watermark Reached</description>
35192 <description>Write '1' to clear interrupt flag</description>
35197 <description>Tx Event FIFO fill level below watermark</description>
35202 <description>Tx Event FIFO fill level reached watermark</description>
35209 <description>Tx Event FIFO Full</description>
35215 <description>Write '1' to clear interrupt flag</description>
35220 <description>Tx Event FIFO not full</description>
35225 <description>Tx Event FIFO full</description>
35232 <description>Tx Event FIFO Element Lost</description>
35238 <description>Write '1' to clear interrupt flag</description>
35243 <description>No Tx Event FIFO element lost</description>
35248 …<description>Tx Event FIFO element lost, also set after wr ite attempt to Tx Event FIFO of siz e z…
35255 <description>Timestamp Wraparound</description>
35261 <description>Write '1' to clear interrupt flag</description>
35266 <description>No timestamp counter wrap-around</description>
35271 <description>Timestamp counter wrapped around</description>
35278 <description>Message RAM Access Failure</description>
35284 <description>Write '1' to clear interrupt flag</description>
35289 <description>No Message RAM access failure occurred</description>
35294 <description>Message RAM access failure occurred</description>
35301 <description>Timeout Occurred</description>
35307 <description>Write '1' to clear interrupt flag</description>
35312 <description>No timeout</description>
35317 <description>Timeout reached</description>
35324 <description>Message stored to Dedicated Rx Buffer</description>
35330 <description>Write '1' to clear interrupt flag</description>
35335 <description>No Rx Buffer updated</description>
35340 <description>At least one received message stored into an Rx Buff er</description>
35347 <description>Bus Error Uncorrected</description>
35353 <description>Write '1' to clear interrupt flag</description>
35358 … <description>No read slave error detected when reading from Message RAM</description>
35363 <description>Read slave error detected</description>
35370 <description>Error Logging Overflow</description>
35376 <description>Write '1' to clear interrupt flag</description>
35381 <description>CAN Error Logging Counter did not overflow</description>
35386 <description>Overflow of CAN Error Logging Counter occurred</description>
35393 <description>Error Passive</description>
35399 <description>Write '1' to clear interrupt flag</description>
35404 <description>Error_Passive status unchanged</description>
35409 <description>Error_Passive status changed</description>
35416 <description>Warning Status</description>
35422 <description>Write '1' to clear interrupt flag</description>
35427 <description>Error_Warning status unchanged</description>
35432 <description>Error_Warning status changed</description>
35439 <description>Bus_Off Status</description>
35445 <description>Write '1' to clear interrupt flag</description>
35450 <description>Bus_Off status unchanged</description>
35455 <description>Bus_Off status changed</description>
35462 <description>Watchdog Interrupt</description>
35468 <description>Write '1' to clear interrupt flag</description>
35473 <description>No Message RAM Watchdog event occurred</description>
35478 <description>Message RAM Watchdog event due to missing READY</description>
35485 … <description>Protocol Error in Arbitration Phase (Nominal Bit Time is used)</description>
35491 <description>Write '1' to clear interrupt flag</description>
35496 <description>No protocol error in arbitration phase</description>
35501 … <description>Protocol error in arbitration phase detected (PSR.LEC ≠ 0,7)</description>
35508 <description>Protocol Error in Data Phase (Data Bit Time is used)</description>
35514 <description>Write '1' to clear interrupt flag</description>
35519 <description>No protocol error in data phase</description>
35524 <description>Protocol error in data phase detected (PSR.DLEC ≠ 0,7)</description>
35531 <description>Access to Reserved Address</description>
35537 <description>Write '1' to clear interrupt flag</description>
35542 <description>No access to reserved address occurred</description>
35547 <description>Access to reserved address occurred</description>
35556 <description>Interrupt Enable</description>
35564 <description>Rx FIFO 0 New Message Interrupt Enable</description>
35570 <description>Interrupt disabled.</description>
35575 <description>Interrupt enabled.</description>
35582 <description>Rx FIFO 0 Watermark Reached Interrupt Enable</description>
35588 <description>Interrupt disabled.</description>
35593 <description>Interrupt enabled.</description>
35600 <description>Rx FIFO 0 Full Interrupt Enable</description>
35606 <description>Interrupt disabled.</description>
35611 <description>Interrupt enabled.</description>
35618 <description>Rx FIFO 0 Message Lost Interrupt Enable</description>
35624 <description>Interrupt disabled.</description>
35629 <description>Interrupt enabled.</description>
35636 <description>Rx FIFO 1 New Message Interrupt Enable</description>
35642 <description>Interrupt disabled.</description>
35647 <description>Interrupt enabled.</description>
35654 <description>Rx FIFO 1 Watermark Reached Interrupt Enable</description>
35660 <description>Interrupt disabled.</description>
35665 <description>Interrupt enabled.</description>
35672 <description>Rx FIFO 1 Full Interrupt Enable</description>
35678 <description>Interrupt disabled.</description>
35683 <description>Interrupt enabled.</description>
35690 <description>Rx FIFO 1 Message Lost Interrupt Enable</description>
35696 <description>Interrupt disabled.</description>
35701 <description>Interrupt enabled.</description>
35708 <description>High Priority Message Interrupt Enable</description>
35714 <description>Interrupt disabled.</description>
35719 <description>Interrupt enabled.</description>
35726 <description>Transmission Completed Interrupt Enable</description>
35732 <description>Interrupt disabled.</description>
35737 <description>Interrupt enabled.</description>
35744 <description>Transmission Cancellation Finished Interrupt Enable</description>
35750 <description>Interrupt disabled.</description>
35755 <description>Interrupt enabled.</description>
35762 <description>Tx FIFO Empty Interrupt Enable</description>
35768 <description>Interrupt disabled.</description>
35773 <description>Interrupt enabled.</description>
35780 <description>Tx Event FIFO New Entry Interrupt Enable</description>
35786 <description>Interrupt disabled.</description>
35791 <description>Interrupt enabled.</description>
35798 <description>Tx Event FIFO Watermark Reached Interrupt Enable</description>
35804 <description>Interrupt disabled.</description>
35809 <description>Interrupt enabled.</description>
35816 <description>Tx Event FIFO Full Interrupt Enable</description>
35822 <description>Interrupt disabled.</description>
35827 <description>Interrupt enabled.</description>
35834 <description>Tx Event FIFO Event Lost Interrupt Enable</description>
35840 <description>Interrupt disabled.</description>
35845 <description>Interrupt enabled.</description>
35852 <description>Timestamp Wraparound Interrupt Enable</description>
35858 <description>Interrupt disabled.</description>
35863 <description>Interrupt enabled.</description>
35870 <description>Message RAM Access Failure Interrupt Enable</description>
35876 <description>Interrupt disabled.</description>
35881 <description>Interrupt enabled.</description>
35888 <description>Timeout Occurred Interrupt Enable</description>
35894 <description>Interrupt disabled.</description>
35899 <description>Interrupt enabled.</description>
35906 <description>Message stored to Dedicated Rx Buffer Interrupt Enable</description>
35912 <description>Interrupt disabled.</description>
35917 <description>Interrupt enabled.</description>
35924 <description>Bus Error Uncorrected Interrupt Enable</description>
35930 <description>Interrupt disabled.</description>
35935 <description>Interrupt enabled.</description>
35942 <description>Error Logging Overflow Interrupt Enable</description>
35948 <description>Interrupt disabled.</description>
35953 <description>Interrupt enabled.</description>
35960 <description>Error Passive Interrupt Enable</description>
35966 <description>Interrupt disabled.</description>
35971 <description>Interrupt enabled.</description>
35978 <description>Warning Status Interrupt Enable</description>
35984 <description>Interrupt disabled.</description>
35989 <description>Interrupt enabled.</description>
35996 <description>Bus_Off Status Interrupt Enable</description>
36002 <description>Interrupt disabled.</description>
36007 <description>Interrupt enabled.</description>
36014 <description>Watchdog Interrupt Enable</description>
36020 <description>Interrupt disabled.</description>
36025 <description>Interrupt enabled.</description>
36032 <description>Protocol Error in Arbitration Phase Enable</description>
36038 <description>Interrupt disabled.</description>
36043 <description>Interrupt enabled.</description>
36050 <description>Protocol Error in Data Phase Enable</description>
36056 <description>Interrupt disabled.</description>
36061 <description>Interrupt enabled.</description>
36068 <description>Access to Reserved Address Enable</description>
36074 <description>Interrupt disabled.</description>
36079 <description>Interrupt enabled.</description>
36088 <description>Interrupt Line Select</description>
36096 <description>Rx FIFO 0 New Message Interrupt Line</description>
36102 <description>Interrupt assigned to interrupt line CORE0.</description>
36107 <description>Interrupt assigned to interrupt line CORE1.</description>
36114 <description>Rx FIFO 0 Watermark Reached Interrupt Line</description>
36120 <description>Interrupt assigned to interrupt line CORE0.</description>
36125 <description>Interrupt assigned to interrupt line CORE1.</description>
36132 <description>Rx FIFO 0 Full Interrupt Line</description>
36138 <description>Interrupt assigned to interrupt line CORE0.</description>
36143 <description>Interrupt assigned to interrupt line CORE1.</description>
36150 <description>Rx FIFO 0 Message Lost Interrupt Line</description>
36156 <description>Interrupt assigned to interrupt line CORE0.</description>
36161 <description>Interrupt assigned to interrupt line CORE1.</description>
36168 <description>Rx FIFO 1 New Message Interrupt Line</description>
36174 <description>Interrupt assigned to interrupt line CORE0.</description>
36179 <description>Interrupt assigned to interrupt line CORE1.</description>
36186 <description>Rx FIFO 1 Watermark Reached Interrupt Line</description>
36192 <description>Interrupt assigned to interrupt line CORE0.</description>
36197 <description>Interrupt assigned to interrupt line CORE1.</description>
36204 <description>Rx FIFO 1 Full Interrupt Line</description>
36210 <description>Interrupt assigned to interrupt line CORE0.</description>
36215 <description>Interrupt assigned to interrupt line CORE1.</description>
36222 <description>Rx FIFO 1 Message Lost Interrupt Line</description>
36228 <description>Interrupt assigned to interrupt line CORE0.</description>
36233 <description>Interrupt assigned to interrupt line CORE1.</description>
36240 <description>High Priority Message Interrupt Line</description>
36246 <description>Interrupt assigned to interrupt line CORE0.</description>
36251 <description>Interrupt assigned to interrupt line CORE1.</description>
36258 <description>Transmission Completed Interrupt Line</description>
36264 <description>Interrupt assigned to interrupt line CORE0.</description>
36269 <description>Interrupt assigned to interrupt line CORE1.</description>
36276 <description>Transmission Cancellation Finished Interrupt Line</description>
36282 <description>Interrupt assigned to interrupt line CORE0.</description>
36287 <description>Interrupt assigned to interrupt line CORE1.</description>
36294 <description>Tx FIFO Empty Interrupt Line</description>
36300 <description>Interrupt assigned to interrupt line CORE0.</description>
36305 <description>Interrupt assigned to interrupt line CORE1.</description>
36312 <description>Tx Event FIFO New Entry Interrupt Line</description>
36318 <description>Interrupt assigned to interrupt line CORE0.</description>
36323 <description>Interrupt assigned to interrupt line CORE1.</description>
36330 <description>Tx Event FIFO Watermark Reached Interrupt Line</description>
36336 <description>Interrupt assigned to interrupt line CORE0.</description>
36341 <description>Interrupt assigned to interrupt line CORE1.</description>
36348 <description>Tx Event FIFO Full Interrupt Line</description>
36354 <description>Interrupt assigned to interrupt line CORE0.</description>
36359 <description>Interrupt assigned to interrupt line CORE1.</description>
36366 <description>Tx Event FIFO Event Lost Interrupt Line</description>
36372 <description>Interrupt assigned to interrupt line CORE0.</description>
36377 <description>Interrupt assigned to interrupt line CORE1.</description>
36384 <description>Timestamp Wraparound Interrupt Line</description>
36390 <description>Interrupt assigned to interrupt line CORE0.</description>
36395 <description>Interrupt assigned to interrupt line CORE1.</description>
36402 <description>Message RAM Access Failure Interrupt Line</description>
36408 <description>Interrupt assigned to interrupt line CORE0.</description>
36413 <description>Interrupt assigned to interrupt line CORE1.</description>
36420 <description>Timeout Occurred Interrupt Line</description>
36426 <description>Interrupt assigned to interrupt line CORE0.</description>
36431 <description>Interrupt assigned to interrupt line CORE1.</description>
36438 <description>Message stored to Dedicated Rx Buffer Interrupt Line</description>
36444 <description>Interrupt assigned to interrupt line CORE0.</description>
36449 <description>Interrupt assigned to interrupt line CORE1.</description>
36456 <description>Bus Error Uncorrected Interrupt Line</description>
36462 <description>Interrupt assigned to interrupt line CORE0.</description>
36467 <description>Interrupt assigned to interrupt line CORE1.</description>
36474 <description>Error Logging Overflow Interrupt Line</description>
36480 <description>Interrupt assigned to interrupt line CORE0.</description>
36485 <description>Interrupt assigned to interrupt line CORE1.</description>
36492 <description>Error Passive Interrupt Line</description>
36498 <description>Interrupt assigned to interrupt line CORE0.</description>
36503 <description>Interrupt assigned to interrupt line CORE1.</description>
36510 <description>Warning Status Interrupt Line</description>
36516 <description>Interrupt assigned to interrupt line CORE0.</description>
36521 <description>Interrupt assigned to interrupt line CORE1.</description>
36528 <description>Bus_Off Status Interrupt Line</description>
36534 <description>Interrupt assigned to interrupt line CORE0.</description>
36539 <description>Interrupt assigned to interrupt line CORE1.</description>
36546 <description>Watchdog Interrupt Line</description>
36552 <description>Interrupt assigned to interrupt line CORE0.</description>
36557 <description>Interrupt assigned to interrupt line CORE1.</description>
36564 <description>Protocol Error in Arbitration Phase Line</description>
36570 <description>Interrupt assigned to interrupt line CORE0.</description>
36575 <description>Interrupt assigned to interrupt line CORE1.</description>
36582 <description>Protocol Error in Data Phase Line</description>
36588 <description>Interrupt assigned to interrupt line CORE0.</description>
36593 <description>Interrupt assigned to interrupt line CORE1.</description>
36600 <description>Access to Reserved Address Line</description>
36606 <description>Interrupt assigned to interrupt line CORE0.</description>
36611 <description>Interrupt assigned to interrupt line CORE1.</description>
36620 <description>Interrupt Line Enable</description>
36628 <description>Enable Interrupt Line 0</description>
36634 <description>Interrupt line CORE0 disabled.</description>
36639 <description>Interrupt line CORE0 enabled.</description>
36646 <description>Enable Interrupt Line 1</description>
36652 <description>Interrupt line CORE1 disabled.</description>
36657 <description>Interrupt line CORE1 enabled.</description>
36666 <description>Global Filter Configuration</description>
36674 <description>Reject Remote Frames Extended</description>
36680 <description>Filter remote frames with 29-bit extended IDs.</description>
36685 <description>Reject all remote frames with 29-bit extended IDs.</description>
36692 <description>Reject Remote Frames Standard</description>
36698 <description>Filter remote frames with 11-bit standard IDs.</description>
36703 <description>Reject all remote frames with 11-bit standard IDs.</description>
36710 <description>Accept Non-matching Frames Extended</description>
36716 <description>Accept in Rx FIFO 0.</description>
36721 <description>Accept in Rx FIFO 1.</description>
36726 <description>Reject in both Rx FIFOs.</description>
36731 <description>Reject in both Rx FIFOs.</description>
36743 <description>Accept in Rx FIFO 0.</description>
36748 <description>Accept in Rx FIFO 1.</description>
36753 <description>Reject in both Rx FIFOs.</description>
36758 <description>Reject in both Rx FIFOs.</description>
36767 <description>Standard ID Filter Configuration</description>
36775 <description>Filter List Standard Start Address</description>
36781 <description>List Size Standard</description>
36789 <description>Extended ID Filter Configuration</description>
36797 <description>Filter List Extended Start Address</description>
36803 <description>List Size Extended</description>
36811 <description>Extended ID AND Mask</description>
36819 <description>Extended ID Mask</description>
36827 <description>High Priority Message Status</description>
36835 <description>Buffer Index</description>
36841 <description>Message Storage Indicator</description>
36847 <description>No FIFO selected.</description>
36852 <description>FIFO message lost.</description>
36857 <description>Message stored in FIFO 0.</description>
36862 <description>Message stored in FIFO 1.</description>
36869 <description>Filter Index</description>
36875 <description>Filter List</description>
36881 <description>Standard Filter List.</description>
36886 <description>Extended Filter List.</description>
36895 <description>New Data 1</description>
36903 <description>New Data</description>
36909 <description>Rx Buffer not updated.</description>
36914 <description>Rx Buffer updated from new message.</description>
36923 <description>New Data 2</description>
36931 <description>New Data</description>
36937 <description>Rx Buffer not updated.</description>
36942 <description>Rx Buffer updated from new message.</description>
36951 <description>Rx FIFO 0 Configuration</description>
36959 <description>Rx FIFO 0 Start Address</description>
36965 <description>Rx FIFO 0 Size</description>
36971 <description>Rx FIFO 0 Watermark</description>
36977 <description>FIFO 0 Operation Mode</description>
36983 <description>FIFO 0 blocking mode.</description>
36988 <description>FIFO 0 overwrite mode.</description>
36997 <description>Rx FIFO 0 Status</description>
37005 <description>Rx FIFO 0 Fill Leve</description>
37011 <description>Rx FIFO 0 Get Index</description>
37017 <description>Rx FIFO 0 Put Index</description>
37023 <description>Rx FIFO 0 Full</description>
37029 <description>Rx FIFO 0 not full.</description>
37034 <description>Rx FIFO 0 full.</description>
37041 <description>Rx FIFO 0 Message Lost</description>
37047 <description>No Rx FIFO 0 message lost.</description>
37052 …<description>Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero.</desc…
37061 <description>Rx FIFO 0 Acknowledge</description>
37069 <description>Rx FIFO 0 Acknowledge Index</description>
37077 <description>Rx Buffer Configuration</description>
37085 <description>Rx Buffer Start Address</description>
37093 <description>Rx FIFO 1 Configuration</description>
37101 <description>Rx FIFO 1 Start Address</description>
37107 <description>Rx FIFO 1 Size</description>
37113 <description>Rx FIFO 1 Watermark</description>
37119 <description>FIFO 1 Operation Mode</description>
37125 <description>FIFO 1 blocking mode</description>
37130 <description>FIFO 1 overwrite mode</description>
37139 <description>Rx FIFO 1 Status</description>
37147 <description>Rx FIFO 1 Fill Level</description>
37153 <description>Rx FIFO 1 Get Index</description>
37159 <description>Rx FIFO 1 Put Index</description>
37165 <description>Rx FIFO 1 Full</description>
37171 <description>Rx FIFO 1 not full</description>
37176 <description>Rx FIFO 1 full</description>
37183 <description>Rx FIFO 1 Message Lost</description>
37189 <description>No Rx FIFO 1 message lost</description>
37194 …<description>Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero</descr…
37201 <description>Debug Message Status</description>
37207 …<description>Idle state, wait for reception of debug messages, DMA request is cleared</description>
37212 <description>Debug message A received</description>
37217 <description>Debug messages A, B received</description>
37222 <description>Debug messages A, B, C received, DMA request is set</description>
37231 <description>Rx FIFO 1 Acknowledge</description>
37239 <description>Rx FIFO 1 Acknowledge Index</description>
37247 <description>Rx Buffer / FIFO Element Size Configuration</description>
37255 <description>Rx FIFO 0 Data Field Size</description>
37261 <description>8 byte data field</description>
37266 <description>12 byte data field</description>
37271 <description>16 byte data field</description>
37276 <description>20 byte data field</description>
37281 <description>24 byte data field</description>
37286 <description>32 byte data field</description>
37291 <description>48 byte data field</description>
37296 <description>64 byte data field</description>
37303 <description>Rx FIFO 1 Data Field Size</description>
37309 <description>8 byte data field</description>
37314 <description>12 byte data field</description>
37319 <description>16 byte data field</description>
37324 <description>20 byte data field</description>
37329 <description>24 byte data field</description>
37334 <description>32 byte data field</description>
37339 <description>48 byte data field</description>
37344 <description>64 byte data field</description>
37351 <description>Rx Buffer Data Field Size</description>
37357 <description>8 byte data field</description>
37362 <description>12 byte data field</description>
37367 <description>16 byte data field</description>
37372 <description>20 byte data field</description>
37377 <description>24 byte data field</description>
37382 <description>32 byte data field</description>
37387 <description>48 byte data field</description>
37392 <description>64 byte data field</description>
37401 <description>Tx Buffer Configuration</description>
37409 <description>Tx Buffers Start Address</description>
37415 <description>Number of Dedicated Transmit Buffers</description>
37421 <description>Transmit FIFO/Queue Size</description>
37427 <description>Tx FIFO/Queue Mode</description>
37433 <description>Tx FIFO operation</description>
37438 <description>Tx Queue operation</description>
37447 <description>Tx FIFO/Queue Status</description>
37455 <description>Tx FIFO Free Level</description>
37461 <description>Tx FIFO Get Index</description>
37467 <description>Tx FIFO/Queue Put Index</description>
37473 <description>Tx FIFO/Queue Full</description>
37479 <description>Tx FIFO/Queue not full</description>
37484 <description>Tx FIFO/Queue full</description>
37493 <description>Tx Buffer Element Size Configuration</description>
37501 <description>Tx Buffer Data Field Size</description>
37507 <description>8 byte data field</description>
37512 <description>12 byte data field</description>
37517 <description>16 byte data field</description>
37522 <description>20 byte data field</description>
37527 <description>24 byte data field</description>
37532 <description>32 byte data field</description>
37537 <description>48 byte data field</description>
37542 <description>64 byte data field</description>
37551 <description>Tx Buffer Request Pending</description>
37559 <description>Transmission Request Pending</description>
37565 <description>No transmission request pending</description>
37570 <description>Transmission request pending</description>
37579 <description>Tx Buffer Add Request</description>
37587 <description>Add Request</description>
37593 <description>No transmission request added</description>
37598 <description>Transmission requested added</description>
37607 <description>Tx Buffer Cancellation Request</description>
37615 <description>Cancellation Request</description>
37621 <description>No cancellation pending</description>
37626 <description>Cancellation pending</description>
37635 <description>Tx Buffer Transmission Occurred</description>
37643 <description>Transmission Occurred</description>
37649 <description>No transmission occurred</description>
37654 <description>Transmission occurred</description>
37663 <description>Tx Buffer Cancellation Finished</description>
37671 <description>Cancellation Finished</description>
37677 <description>No transmit buffer cancellation</description>
37682 <description>Transmit buffer cancellation finished</description>
37691 <description>Tx Buffer Transmission Interrupt Enable</description>
37699 <description>Transmission Interrupt Enable</description>
37705 <description>Transmission interrupt disabled</description>
37710 <description>Transmission interrupt enable</description>
37719 <description>Tx Buffer Cancellation Finished Interrupt Enable</description>
37727 <description>Cancellation Finished Interrupt Enable</description>
37733 <description>Cancellation finished interrupt disabled</description>
37738 <description>Cancellation finished interrupt enabled</description>
37747 <description>Tx Event FIFO Configuration</description>
37755 <description>Event FIFO Start Address</description>
37761 <description>Event FIFO Size</description>
37767 <description>Event FIFO Watermark</description>
37775 <description>Tx Event FIFO Status</description>
37783 <description>Event FIFO Fill Level</description>
37789 <description>Event FIFO Get Index</description>
37795 <description>Event FIFO Put Index</description>
37801 <description>Event FIFO Full</description>
37807 <description>Tx Event FIFO not full</description>
37812 <description>Tx Event FIFO full</description>
37819 <description>Tx Event FIFO Element Lost</description>
37825 <description>No Tx Event FIFO element lost</description>
37830 …<description>Tx Event FIFO element lost, also set after wr ite attempt to Tx Event FIFO of siz e z…
37839 <description>Tx Event FIFO Acknowledge</description>
37847 <description>Event FIFO Acknowledge Index</description>
37857 <description>DMU</description>
37873 <description>DMU Core Release</description>
37881 <description>Core Release</description>
37887 <description>Step of Core Release</description>
37893 <description>Sub-step of Core Release</description>
37899 <description>Time Stamp Year</description>
37905 <description>Time Stamp Month</description>
37911 <description>Time Stamp Day</description>
37919 <description>DMU Internals</description>
37927 <description>TX Service Request line of DMU</description>
37933 <description>No TX DMA service requested</description>
37938 <description>TX DMA Service requested</description>
37945 <description>RX0 Service Request line of DMU</description>
37951 <description>No RX0 DMA service requested</description>
37956 <description>RX0 DMA Service requested</description>
37963 <description>RX1 Service Request line of DMU</description>
37969 <description>No RX1 DMA service requested</description>
37974 <description>RX1 DMA Service requested</description>
37981 <description>TX Event Service Request line of DMU</description>
37987 <description>No TX Event DMA service requested</description>
37992 <description>TX Event DMA Service requested</description>
37999 <description>TX FIFO/Queue Put Index Previous</description>
38005 <description>DMU is enabled</description>
38011 <description>DMU is disabled</description>
38016 <description>DMU is enabled and can process DMA data</description>
38023 <description>Detect Element Handler State</description>
38029 <description>Detect DMU Element Service</description>
38035 … <description>Queueing of DMU Element does not activate interrupt flag</description>
38040 …<description>Queueing of DMU Element will activate interrupt flag when DMUI.EHS = DMUI.DEHS</descr…
38047 <description>Detect DMU Element Service</description>
38053 … <description>Queueing of DMU Element does not activate interrupt flag</description>
38058 …<description>Queueing of DMU Element will activate interrupt flag when DMUI.EHS = DMUI.DEHS</descr…
38065 <description>Detect DMU Element Service</description>
38071 … <description>Queueing of DMU Element does not activate interrupt flag</description>
38076 …<description>Queueing of DMU Element will activate interrupt flag when DMUI.EHS = DMUI.DEHS</descr…
38083 <description>Detect DMU Element Service</description>
38089 … <description>Queueing of DMU Element does not activate interrupt flag</description>
38094 …<description>Queueing of DMU Element will activate interrupt flag when DMUI.EHS = DMUI.DEHS</descr…
38101 <description>Element Handler State</description>
38107 <description>wait for bit MCAN:CCCR.CCE getting zero</description>
38112 <description>wait for Start Address</description>
38117 <description>wait for Trigger Address</description>
38122 <description>wait for transfer of Element word</description>
38127 <description>acknowledge to MCAN</description>
38132 <description>exception recovery</description>
38139 <description>Actual DMU Element Service</description>
38145 <description>DMU Virtual Buffer is currently not served</description>
38150 <description>DMU Virtual Buffer is currently served</description>
38157 <description>Actual DMU Element Service</description>
38163 <description>DMU Virtual Buffer is currently not served</description>
38168 <description>DMU Virtual Buffer is currently served</description>
38175 <description>Actual DMU Element Service</description>
38181 <description>DMU Virtual Buffer is currently not served</description>
38186 <description>DMU Virtual Buffer is currently served</description>
38193 <description>Actual DMU Element Service</description>
38199 <description>DMU Virtual Buffer is currently not served</description>
38204 <description>DMU Virtual Buffer is currently served</description>
38213 <description>DMU Queueing Counter</description>
38221 <description>TX Element Enqueueing Counter</description>
38227 <description>RX0 Element Dequeueing Counter</description>
38233 <description>RX1 Element Dequeueing Counter</description>
38239 <description>TX Event Element Dequeueing Counter</description>
38247 <description>DMU Interrupt Register</description>
38255 <description>TX Element Not Start Address</description>
38261 <description>Write '1' to clear interrupt flag</description>
38266 <description>No illegal write access</description>
38271 …<description>Write to TX Element begins without using start address, exception recovery started.</…
38278 <description>TX Element Illegal Enqueueing</description>
38284 <description>Write '1' to clear interrupt flag</description>
38289 <description>No illegal enqueueing</description>
38294 …<description>Start of enqueueing without request detected, exception recovery started.</descriptio…
38301 <description>TX Element Illegal Access Sequence</description>
38307 <description>Write '1' to clear interrupt flag</description>
38312 <description>No illegal addressing sequence detected</description>
38317 …<description>Accesses are not strictly linear to ascending and consecutive addresses, exception re…
38324 <description>TX Element Illegal DLC</description>
38330 <description>Write '1' to clear interrupt flag</description>
38335 <description>No illegal DLC detected</description>
38340 … <description>DLC exceeds Tx Buffer element size of MCAN, exception recovery started.</description>
38347 <description>TX Element Write After Trigger Address</description>
38353 <description>Write '1' to clear interrupt flag</description>
38358 <description>No write after Trigger Address</description>
38363 <description>Write after Trigger address detected</description>
38370 <description>TX Element Illegal Read</description>
38376 <description>Write '1' to clear interrupt flag</description>
38381 <description>No read access</description>
38386 …<description>Illegal read access to DMU TX Element section detected, exception recovery started.</…
38393 …<description>A successful enqueueing of a Tx message with the DMU TX Element section sets this fla…
38399 <description>Write '1' to clear interrupt flag</description>
38404 <description>No Tx message enqueued</description>
38409 <description>Tx message successfully enqueued</description>
38416 <description>RX0 Element Not Start Address</description>
38422 <description>Write '1' to clear interrupt flag</description>
38427 <description>No illegal read access</description>
38432 …<description>Read from RX0 Element begins without using start address, exception recovery started.…
38439 <description>RX0 Element Illegal Dequeueing</description>
38445 <description>Write '1' to clear interrupt flag</description>
38450 <description>No illegal dequeueing</description>
38455 …<description>Start of dequeueing without request detected, exception recovery started,</descriptio…
38462 <description>RX0 Element Illegal Access Sequence</description>
38468 <description>Write '1' to clear interrupt flag</description>
38473 <description>No illegal addressing sequence detected</description>
38478 …<description>Accesses are not strictly linear to ascending and consecutive addresses, exception re…
38485 <description>RX0 Element Illegal Write</description>
38491 <description>Write '1' to clear interrupt flag</description>
38496 <description>No write access detected</description>
38501 …<description>Illegal write access to DMU RX0 Element detected, exception recovery started.</descri…
38508 <description>RX0 Element Dequeued</description>
38514 <description>Write '1' to clear interrupt flag</description>
38519 <description>No Rx message dequeued</description>
38524 <description>Rx message successfully dequeued</description>
38531 <description>RX0 Element Illegal Overwrite by timestamp</description>
38537 <description>Write '1' to clear interrupt flag</description>
38542 <description>No illegal overwrite detected</description>
38547 … <description>DMU has internally overwritten the last element word of a SYNC message</description>
38554 <description>Bus Error Uncorrected</description>
38560 <description>Write '1' to clear interrupt flag</description>
38565 … <description>No read slave error detected when reading from Message RAM</description>
38570 <description>Read slave error detected</description>
38577 <description>RX1 Element Not Start Address</description>
38583 <description>Write '1' to clear interrupt flag</description>
38588 <description>No illegal read access</description>
38593 …<description>Read from RX1 Element begins without using start address, exception recovery started.…
38600 <description>RX1 Element Illegal Dequeueing</description>
38606 <description>Write '1' to clear interrupt flag</description>
38611 <description>No illegal dequeueing</description>
38616 …<description>Start of dequeueing without request detected, exception recovery started,</descriptio…
38623 <description>RX0 Element Illegal Access Sequence</description>
38629 <description>Write '1' to clear interrupt flag</description>
38634 <description>No illegal addressing sequence detected</description>
38639 …<description>Accesses are not strictly linear to ascending and consecutive addresses, exception re…
38646 <description>RX1 Element Illegal Write</description>
38652 <description>Write '1' to clear interrupt flag</description>
38657 <description>No write access detected</description>
38662 …<description>Illegal write access to DMU RX1 Element detected, exception recovery started.</descri…
38669 <description>RX0 Element Dequeued</description>
38675 <description>Write '1' to clear interrupt flag</description>
38680 <description>No Rx message dequeued</description>
38685 <description>Rx message successfully dequeued</description>
38692 <description>RX1 Element Illegal Overwrite by timestamp</description>
38698 <description>Write '1' to clear interrupt flag</description>
38703 <description>No illegal overwrite detected</description>
38708 … <description>DMU has internally overwritten the last element word of a SYNC message</description>
38715 <description>TX Event Element Not Start Address</description>
38721 <description>Write '1' to clear interrupt flag</description>
38726 <description>No illegal read access</description>
38731 …<description>Read from TX Event Element begins without using start address, exception recovery sta…
38738 <description>TX Event Element Illegal Dequeueing</description>
38744 <description>Write '1' to clear interrupt flag</description>
38749 <description>No illegal dequeueing</description>
38754 …<description>Start of dequeueing without request detected, exception recovery started.</descriptio…
38761 <description>TX Event Element Illegal Access Sequence</description>
38767 <description>Write '1' to clear interrupt flag</description>
38772 <description>No illegal addressing sequence detected</description>
38777 …<description>Accesses are not strictly linear to ascending and consecutive addresses, exception re…
38784 <description>TX Event Element Illegal Write</description>
38790 <description>Write '1' to clear interrupt flag</description>
38795 <description>No write access detected</description>
38800 …<description>Illegal write access to DMU TX Event Element detected, exception recovery started.</d…
38807 <description>TX Event Element Dequeued</description>
38813 <description>Write '1' to clear interrupt flag</description>
38818 <description>No TX Event Element dequeued</description>
38823 <description>TX Event Element successfully dequeued</description>
38830 <description>Debug Trigger</description>
38836 <description>Write '1' to clear interrupt flag</description>
38841 <description>Debug point not reached</description>
38846 <description>Debug point reached</description>
38853 <description>Illegal Access while in Configuration mode</description>
38859 <description>Write '1' to clear interrupt flag</description>
38864 <description>No Illegal Access while CCE mode</description>
38869 <description>Illegal Access while CCE mode</description>
38878 <description>DMU Interrupt Enable</description>
38886 <description>TX Element Not Start Address Enable</description>
38892 <description>Flag does not activate the interrupt line DMU</description>
38897 <description>the interrupt line DMU will be activated</description>
38906 <description>DMU Configuration</description>
38914 <description>Transfer Timestamp</description>
38920 <description>No timestamp will be transferred via DMU Virtual Buffer</description>
38925 …<description>Timestamp of message will be transferred from TSU via DMU Virtual Buffer</description>
38936 <description>System Trace Macrocell data buffer</description>
38953 <description>Unspecified</description>
38961 …description>Description collection: STM extended stimulus port data buffer area for domain n. NonS…
38974 <description>TDDCONF</description>
38988 <description>System power-up request</description>
38996 <description>Activate power-up request</description>
39002 <description>Power-up request not active</description>
39007 <description>Power-up request active</description>
39016 <description>Debug power-up request</description>
39024 <description>Activate power-up request</description>
39030 <description>Power-up request not active</description>
39035 <description>Power-up request active</description>
39044 <description>Trace port trace clock speed</description>
39052 <description>Trace clock speed</description>
39058 <description>Speed 80MHz</description>
39063 <description>Speed 40MHz</description>
39068 <description>Speed 20MHz</description>
39073 <description>Speed 10MHz</description>
39082 …<description>Combined effective system status of both SWJ-DP and TDDCONF registers originated powe…
39090 <description>System powerup request status</description>
39096 <description>Power not requested</description>
39101 <description>Power requested</description>
39108 <description>Debug domain powerup request status</description>
39114 <description>Power not requested</description>
39119 <description>Power requested</description>
39130 <description>System Trace Macrocell</description>
39144 <description>Controls the DMA transfer request mechanism.</description>
39152 …<description>Determines the sensitivity of the DMA request to the current buffer level in the STM<…
39158 <description>Buffer is &lt;25 percent full.</description>
39163 <description>Buffer is &lt;50 percent full.</description>
39168 <description>Buffer is &lt;75 percent full.</description>
39173 <description>Buffer is &lt;100 percent full.</description>
39182 …<description>Indicates the STPv2 master number of hardware event trace. This number is the master …
39190 …<description>The STPv2 master number that hardware event traces should be associated with.</descri…
39198 <description>Indicates the features of the STM.</description>
39206 <description>STMHETER support</description>
39212 <description>The feature is not implemented.</description>
39217 <description>The feature is implemented.</description>
39224 <description>Hardware event error detection support</description>
39230 <description>The feature is not implemented.</description>
39235 <description>The feature is implemented.</description>
39242 <description>STMHEMASTR support</description>
39248 <description>The feature is not implemented.</description>
39253 <description>The feature is implemented.</description>
39260 <description>The number of hardware events supported by the STM</description>
39268 <description>Indicates the features of hardware event tracing in the STM.</description>
39276 <description>The CLASS field identifies the programmers model</description>
39282 <description>Hardware Event Control programmers model</description>
39289 … <description>The CLASSREV field identifies the revision of the programmers model</description>
39295 …<description>The VENDSPEC field identifies any vendor specific modifications or mappings</descript…
39303 <description>Controls the STM settings.</description>
39311 <description>Global STM enable</description>
39317 <description>The STM is disabled.</description>
39322 <description>The STM is enabled.</description>
39329 <description>Enable or disable timestamp bundling.</description>
39335 …description>Time stamps are disabled. Requests for timestamp generation are ignored, and stimulus …
39340 …<description>Time stamps are enabled. If stimulus writes select timestamping, a timestamp is outpu…
39347 <description>STMSYNCR is implemented so this value is Read As One.</description>
39353 <description>The STM Sync feature is disabled.</description>
39358 <description>The STM Sync feature is enabled.</description>
39365 <description>Compression Enable for Stimulus Ports.</description>
39371 …<description>Compression disabled, data transfers are transmitted at the size of the transaction.<…
39376 … <description>Compression enabled, data transfers are compressed to save bandwidth.</description>
39383 …<description>ATB Trace ID. Setting this value to all zeroes might result in Unpredictable tracing.…
39389 <description>STM is busy, for example the STM trace FIFO is not empty.</description>
39395 <description>STM is not busy.</description>
39400 <description>STM is busy.</description>
39409 <description>Used for implementation defined STM controls.</description>
39417 <description>FIFO Auto-flush.</description>
39423 <description>Auto-flush is disabled.</description>
39428 …<description>Auto-flush is enabled. The STM automatically drains all data it has even if the ATB i…
39435 <description>Is ASYNC priority higher than trace?</description>
39441 <description>ASYNC priority is always lower than trace.</description>
39446 … <description>ASYNC priority escalates on second synchronization request.</description>
39453 <description>Controls arbitration between AXI and HW during flush.</description>
39459 …<description>Priority inversion, when AXI flush is finished, HW gets priority until HW flush is do…
39464 … <description>Priority inversion disabled, AXI always has priority over HW.</description>
39471 … <description>Provides override control for architectural clock gate enable.</description>
39477 … <description>No override, clock gate is controlled by the state of STM.</description>
39482 <description>Override, clock is enabled.</description>
39489 <description>Provides override control for the AFREADY output</description>
39495 <description>No override, AFREADY is controlled by the state of STM.</description>
39500 <description>Override, AFREADY is driven HIGH.</description>
39509 <description>Indicates the features of the STM.</description>
39517 <description>Indicates the implemented STM protocol.</description>
39523 <description>STM implements the STPV2 protocol.</description>
39530 <description>Timestamp support.</description>
39536 <description>Absolute timestamps implemented.</description>
39543 <description>Timestamp frequency indication configuration.</description>
39549 <description>STMTSFREQR is read-only.</description>
39554 <description>STMTSFREQR is read-write.</description>
39561 <description>Timestamp force configuration.</description>
39567 <description>STMTSSTIMR bit 0 is read-only.</description>
39572 <description>STMTSSTIMR bit 0 is read-write.</description>
39579 <description>Trace bus support.</description>
39585 <description>Trigger control support.</description>
39591 <description>Timestamp prescale support</description>
39597 <description>Timestamp prescale is not implemented.</description>
39602 <description>Timestamp prescale is implemented.</description>
39609 <description>STMTCSR.HWTEN support</description>
39615 <description>STMTCSR.HWTEN is not implemented</description>
39622 <description>STMTCSR.SYNCEN support</description>
39628 <description>STMTCSR.SYNCEN implemented but always reads as b1</description>
39635 <description>STMTCSR.SWOEN support</description>
39641 <description>STMTCSR.SWOEN not implemented</description>
39650 <description>Indicates the features of the STM.</description>
39658 <description>STMSPTER support.</description>
39664 <description>STMSPTER is implemented.</description>
39671 <description>STMSPER presence.</description>
39677 <description>STMSPER is implemented.</description>
39682 <description>STMSPER is not implemented.</description>
39689 <description>Data compression on stimulus ports support.</description>
39695 …<description>Data compression support is programmable. STMTCSR.COMPEN is implemented.</description>
39702 <description>Timestamp force configuration.</description>
39708 <description>STMSPOVERRIDER and STMSPMOVERRIDER is not implemented.</description>
39713 <description>STMSPOVERRIDER and STMSPMOVERRIDER is implemented.</description>
39720 <description>STMPRIVMASKR support.</description>
39726 <description>STMPRIVMASKR is not implemented.</description>
39733 <description>Stimulus port transaction type support.</description>
39739 … <description>Both invariant timing and guaranteed transactions are supported.</description>
39746 <description>Fundamental data size.</description>
39752 <description>32-bit data.</description>
39759 <description>Stimulus port type support</description>
39765 <description>Only extended stimulus ports are implemented.</description>
39774 <description>Indicates the features of the STM.</description>
39782 <description>The number of stimulus ports masters implemented, minus 1.</description>
39788 <description>Example: 128 masters implemented.</description>
39797 <description>Integration Test for Cross-Trigger Outputs Register.</description>
39805 … <description>Sets the value of the TRIGOUTSPTE output in integration mode.</description>
39811 <description>Drive logic 0 on output.</description>
39816 <description>Drive logic 1 on output.</description>
39823 <description>Sets the value of the TRIGOUTSW output in integration mode.</description>
39829 <description>Drive logic 0 on output.</description>
39834 <description>Drive logic 1 on output.</description>
39841 … <description>Sets the value of the TRIGOUTHETE output in integration mode.</description>
39847 <description>Drive logic 0 on output.</description>
39852 <description>Drive logic 1 on output.</description>
39859 <description>Sets the value of the ASYNCOUT output in integration mode.</description>
39865 <description>Drive logic 0 on output.</description>
39870 <description>Drive logic 1 on output.</description>
39879 <description>Controls the value of the ATDATAM output in integration mode.</description>
39887 <description>Sets the value of the ATDATAM[0].</description>
39893 <description>Drive logic 0 on output.</description>
39898 <description>Drive logic 1 on output.</description>
39905 <description>Sets the value of the ATDATAM[7] output.</description>
39911 <description>Drive logic 0 on output.</description>
39916 <description>Drive logic 1 on output.</description>
39923 <description>Sets the value of the ATDATAM[15].</description>
39929 <description>Drive logic 0 on output.</description>
39934 <description>Drive logic 1 on output.</description>
39941 <description>Sets the value of the ATDATAM[23].</description>
39947 <description>Drive logic 0 on output.</description>
39952 <description>Drive logic 1 on output.</description>
39959 <description>Sets the value of the ATDATAM[31].</description>
39965 <description>Drive logic 0 on output.</description>
39970 <description>Drive logic 1 on output.</description>
39979 <description>Controls the value of the ATDATAM output in integration mode.</description>
39987 <description>Reads the value of the ATREADYM input.</description>
39993 <description>Pin is at logic 0.</description>
39998 <description>Pin is at logic 1.</description>
40005 <description>Reads the value of the AFVALIDM input.</description>
40011 <description>Pin is at logic 0.</description>
40016 <description>Pin is at logic 1.</description>
40025 <description>Controls the value of the ATIDM output in integration mode.</description>
40033 <description>Sets the value of pin 0 of the ATIDM output.</description>
40039 <description>Pin is at logic 0.</description>
40044 <description>Pin is at logic 1.</description>
40051 <description>Sets the value of pin 1 of the ATIDM output.</description>
40057 <description>Pin is at logic 0.</description>
40062 <description>Pin is at logic 1.</description>
40069 <description>Sets the value of pin 2 of the ATIDM output.</description>
40075 <description>Pin is at logic 0.</description>
40080 <description>Pin is at logic 1.</description>
40087 <description>Sets the value of pin 3 of the ATIDM output.</description>
40093 <description>Pin is at logic 0.</description>
40098 <description>Pin is at logic 1.</description>
40105 <description>Sets the value of pin 4 of the ATIDM output.</description>
40111 <description>Pin is at logic 0.</description>
40116 <description>Pin is at logic 1.</description>
40123 <description>Sets the value of pin 5 of the ATIDM output.</description>
40129 <description>Pin is at logic 0.</description>
40134 <description>Pin is at logic 1.</description>
40141 <description>Sets the value of pin 6 of the ATIDM output.</description>
40147 <description>Pin is at logic 0.</description>
40152 <description>Pin is at logic 1.</description>
40161 …<description>Controls the value of the ATVALIDM, AFREADYM, and ATBYTESM outputs in integration mod…
40169 <description>Sets the value of the ATVALIDM output.</description>
40175 <description>Pin is at logic 0.</description>
40180 <description>Pin is at logic 1.</description>
40187 <description>Sets the value of the AFREADYM_W output.</description>
40193 <description>Pin is at logic 0.</description>
40198 <description>Pin is at logic 1.</description>
40205 <description>Sets the value of pin 0 of the ATBYTESM output.</description>
40211 <description>Pin is at logic 0.</description>
40216 <description>Pin is at logic 1.</description>
40223 <description>Sets the value of pin 1 of the ATBYTESM output.</description>
40229 <description>Pin is at logic 0.</description>
40234 <description>Pin is at logic 1.</description>
40243 <description>Used to enable topology detection.
40245 …he component can be directly controlled for integration testing and topology solving.</description>
40253 …description>Enables the component to switch from functional mode to integration mode and back. If …
40259 <description>Integration mode is disabled.</description>
40264 <description>Integration mode is Enabled.</description>
40273 <description>This is used to enable write access to device registers.</description>
40281 …<description>A write of 0xC5ACCE55 enables further write access to this device. Any other write re…
40287 <description>Unlock register interface.</description>
40296 …<description>This indicates the status of the lock control mechanism. This lock prevents accidenta…
40300 … For most components this covers all registers except for the Lock Access Register.</description>
40308 … <description>Indicates that a lock control mechanism exists for this device.</description>
40314 …<description>No lock control mechanism exists, writes to the Lock Access Register are ignored.</de…
40319 <description>Lock control mechanism is present.</description>
40326 <description>Returns the current status of the Lock.</description>
40332 <description>Write access is allowed to this device.</description>
40337 …<description>Write access to the component is blocked. All writes to control registers are ignored…
40344 …<description>Indicates if the Lock Access Register is implemented as 8-bit or 32-bit.</description>
40350 … <description>This component implements a 32-bit Lock Access Register.</description>
40355 … <description>This component implements an 8-bit Lock Access Register.</description>
40364 <description>Indicates the current level of tracing permitted by the system</description>
40372 <description>Non-secure Invasive Debug</description>
40378 <description>The feature is not implemented.</description>
40383 <description>The feature is implemented.</description>
40390 <description>Non-secure Non-Invasive Debug</description>
40396 <description>The feature is not implemented.</description>
40401 <description>The feature is implemented.</description>
40408 <description>Secure Invasive Debug</description>
40414 <description>The feature is not implemented.</description>
40419 <description>The feature is implemented.</description>
40426 <description>Secure Non-Invasive Debug</description>
40432 <description>The feature is not implemented.</description>
40437 <description>The feature is implemented.</description>
40446 <description>Indicates the capabilities of the STM.</description>
40454 … <description>This value indicates the number of stimulus ports implemented.</description>
40460 <description>Maximum 65,536 stimulus ports can be implemented.</description>
40469 <description>Controls the single-shot comparator.</description>
40477 <description>The main type of the component</description>
40483 <description>Peripheral is a trace source.</description>
40490 <description>The sub-type of the component</description>
40496 <description>Peripheral is a stimulus trace source.</description>
40505 <description>Coresight peripheral identification registers.</description>
40513 <description>Coresight peripheral identification registers.</description>
40521 <description>Coresight peripheral identification registers.</description>
40529 <description>Coresight peripheral identification registers.</description>
40537 <description>Coresight peripheral identification registers.</description>
40545 <description>Coresight component identification registers.</description>
40553 <description>Coresight component identification registers.</description>
40561 <description>Coresight component identification registers.</description>
40569 <description>Coresight component identification registers.</description>
40579 <description>Trace Port Interface Unit</description>
40593 …<description>Each bit location is a single port size that is supported on the device.</description>
40601 <description>Indicates whether the TPIU supports port size of 1-bit.</description>
40607 <description>Port size 1 is not supported.</description>
40612 <description>Port size 1 is supported.</description>
40619 <description>Indicates whether the TPIU supports port size of 2-bit.</description>
40625 <description>Port size 2 is not supported.</description>
40630 <description>Port size 2 is supported.</description>
40637 <description>Indicates whether the TPIU supports port size of 3-bit.</description>
40643 <description>Port size 3 is not supported.</description>
40648 <description>Port size 3 is supported.</description>
40655 <description>Indicates whether the TPIU supports port size of 4-bit.</description>
40661 <description>Port size 4 is not supported.</description>
40666 <description>Port size 4 is supported.</description>
40673 <description>Indicates whether the TPIU supports port size of 5-bit.</description>
40679 <description>Port size 5 is not supported.</description>
40684 <description>Port size 5 is supported.</description>
40691 <description>Indicates whether the TPIU supports port size of 6-bit.</description>
40697 <description>Port size 6 is not supported.</description>
40702 <description>Port size 6 is supported.</description>
40709 <description>Indicates whether the TPIU supports port size of 7-bit.</description>
40715 <description>Port size 7 is not supported.</description>
40720 <description>Port size 7 is supported.</description>
40727 <description>Indicates whether the TPIU supports port size of 8-bit.</description>
40733 <description>Port size 8 is not supported.</description>
40738 <description>Port size 8 is supported.</description>
40745 <description>Indicates whether the TPIU supports port size of 9-bit.</description>
40751 <description>Port size 9 is not supported.</description>
40756 <description>Port size 9 is supported.</description>
40763 <description>Indicates whether the TPIU supports port size of 10-bit.</description>
40769 <description>Port size 10 is not supported.</description>
40774 <description>Port size 10 is supported.</description>
40781 <description>Indicates whether the TPIU supports port size of 11-bit.</description>
40787 <description>Port size 11 is not supported.</description>
40792 <description>Port size 11 is supported.</description>
40799 <description>Indicates whether the TPIU supports port size of 12-bit.</description>
40805 <description>Port size 12 is not supported.</description>
40810 <description>Port size 12 is supported.</description>
40817 <description>Indicates whether the TPIU supports port size of 13-bit.</description>
40823 <description>Port size 13 is not supported.</description>
40828 <description>Port size 13 is supported.</description>
40835 <description>Indicates whether the TPIU supports port size of 14-bit.</description>
40841 <description>Port size 14 is not supported.</description>
40846 <description>Port size 14 is supported.</description>
40853 <description>Indicates whether the TPIU supports port size of 15-bit.</description>
40859 <description>Port size 15 is not supported.</description>
40864 <description>Port size 15 is supported.</description>
40871 <description>Indicates whether the TPIU supports port size of 16-bit.</description>
40877 <description>Port size 16 is not supported.</description>
40882 <description>Port size 16 is supported.</description>
40889 <description>Indicates whether the TPIU supports port size of 17-bit.</description>
40895 <description>Port size 17 is not supported.</description>
40900 <description>Port size 17 is supported.</description>
40907 <description>Indicates whether the TPIU supports port size of 18-bit.</description>
40913 <description>Port size 18 is not supported.</description>
40918 <description>Port size 18 is supported.</description>
40925 <description>Indicates whether the TPIU supports port size of 19-bit.</description>
40931 <description>Port size 19 is not supported.</description>
40936 <description>Port size 19 is supported.</description>
40943 <description>Indicates whether the TPIU supports port size of 20-bit.</description>
40949 <description>Port size 20 is not supported.</description>
40954 <description>Port size 20 is supported.</description>
40961 <description>Indicates whether the TPIU supports port size of 21-bit.</description>
40967 <description>Port size 21 is not supported.</description>
40972 <description>Port size 21 is supported.</description>
40979 <description>Indicates whether the TPIU supports port size of 22-bit.</description>
40985 <description>Port size 22 is not supported.</description>
40990 <description>Port size 22 is supported.</description>
40997 <description>Indicates whether the TPIU supports port size of 23-bit.</description>
41003 <description>Port size 23 is not supported.</description>
41008 <description>Port size 23 is supported.</description>
41015 <description>Indicates whether the TPIU supports port size of 24-bit.</description>
41021 <description>Port size 24 is not supported.</description>
41026 <description>Port size 24 is supported.</description>
41033 <description>Indicates whether the TPIU supports port size of 25-bit.</description>
41039 <description>Port size 25 is not supported.</description>
41044 <description>Port size 25 is supported.</description>
41051 <description>Indicates whether the TPIU supports port size of 26-bit.</description>
41057 <description>Port size 26 is not supported.</description>
41062 <description>Port size 26 is supported.</description>
41069 <description>Indicates whether the TPIU supports port size of 27-bit.</description>
41075 <description>Port size 27 is not supported.</description>
41080 <description>Port size 27 is supported.</description>
41087 <description>Indicates whether the TPIU supports port size of 28-bit.</description>
41093 <description>Port size 28 is not supported.</description>
41098 <description>Port size 28 is supported.</description>
41105 <description>Indicates whether the TPIU supports port size of 29-bit.</description>
41111 <description>Port size 29 is not supported.</description>
41116 <description>Port size 29 is supported.</description>
41123 <description>Indicates whether the TPIU supports port size of 30-bit.</description>
41129 <description>Port size 30 is not supported.</description>
41134 <description>Port size 30 is supported.</description>
41141 <description>Indicates whether the TPIU supports port size of 31-bit.</description>
41147 <description>Port size 31 is not supported.</description>
41152 <description>Port size 31 is supported.</description>
41159 <description>Indicates whether the TPIU supports port size of 32-bit.</description>
41165 <description>Port size 32 is not supported.</description>
41170 <description>Port size 32 is supported.</description>
41179 …<description>Each bit location is a single port size. One bit can be set, and indicates the curren…
41187 <description>Indicates which port size is currently selected.</description>
41193 <description>Port size 1 is not selected.</description>
41198 <description>Port size 1 is selected.</description>
41205 <description>Indicates which port size is currently selected.</description>
41211 <description>Port size 2 is not selected.</description>
41216 <description>Port size 2 is selected.</description>
41223 <description>Indicates which port size is currently selected.</description>
41229 <description>Port size 3 is not selected.</description>
41234 <description>Port size 3 is selected.</description>
41241 <description>Indicates which port size is currently selected.</description>
41247 <description>Port size 4 is not selected.</description>
41252 <description>Port size 4 is selected.</description>
41259 <description>Indicates which port size is currently selected.</description>
41265 <description>Port size 5 is not selected.</description>
41270 <description>Port size 5 is selected.</description>
41277 <description>Indicates which port size is currently selected.</description>
41283 <description>Port size 6 is not selected.</description>
41288 <description>Port size 6 is selected.</description>
41295 <description>Indicates which port size is currently selected.</description>
41301 <description>Port size 7 is not selected.</description>
41306 <description>Port size 7 is selected.</description>
41313 <description>Indicates which port size is currently selected.</description>
41319 <description>Port size 8 is not selected.</description>
41324 <description>Port size 8 is selected.</description>
41331 <description>Indicates which port size is currently selected.</description>
41337 <description>Port size 9 is not selected.</description>
41342 <description>Port size 9 is selected.</description>
41349 <description>Indicates which port size is currently selected.</description>
41355 <description>Port size 10 is not selected.</description>
41360 <description>Port size 10 is selected.</description>
41367 <description>Indicates which port size is currently selected.</description>
41373 <description>Port size 11 is not selected.</description>
41378 <description>Port size 11 is selected.</description>
41385 <description>Indicates which port size is currently selected.</description>
41391 <description>Port size 12 is not selected.</description>
41396 <description>Port size 12 is selected.</description>
41403 <description>Indicates which port size is currently selected.</description>
41409 <description>Port size 13 is not selected.</description>
41414 <description>Port size 13 is selected.</description>
41421 <description>Indicates which port size is currently selected.</description>
41427 <description>Port size 14 is not selected.</description>
41432 <description>Port size 14 is selected.</description>
41439 <description>Indicates which port size is currently selected.</description>
41445 <description>Port size 15 is not selected.</description>
41450 <description>Port size 15 is selected.</description>
41457 <description>Indicates which port size is currently selected.</description>
41463 <description>Port size 16 is not selected.</description>
41468 <description>Port size 16 is selected.</description>
41475 <description>Indicates which port size is currently selected.</description>
41481 <description>Port size 17 is not selected.</description>
41486 <description>Port size 17 is selected.</description>
41493 <description>Indicates which port size is currently selected.</description>
41499 <description>Port size 18 is not selected.</description>
41504 <description>Port size 18 is selected.</description>
41511 <description>Indicates which port size is currently selected.</description>
41517 <description>Port size 19 is not selected.</description>
41522 <description>Port size 19 is selected.</description>
41529 <description>Indicates which port size is currently selected.</description>
41535 <description>Port size 20 is not selected.</description>
41540 <description>Port size 20 is selected.</description>
41547 <description>Indicates which port size is currently selected.</description>
41553 <description>Port size 21 is not selected.</description>
41558 <description>Port size 21 is selected.</description>
41565 <description>Indicates which port size is currently selected.</description>
41571 <description>Port size 22 is not selected.</description>
41576 <description>Port size 22 is selected.</description>
41583 <description>Indicates which port size is currently selected.</description>
41589 <description>Port size 23 is not selected.</description>
41594 <description>Port size 23 is selected.</description>
41601 <description>Indicates which port size is currently selected.</description>
41607 <description>Port size 24 is not selected.</description>
41612 <description>Port size 24 is selected.</description>
41619 <description>Indicates which port size is currently selected.</description>
41625 <description>Port size 25 is not selected.</description>
41630 <description>Port size 25 is selected.</description>
41637 <description>Indicates which port size is currently selected.</description>
41643 <description>Port size 26 is not selected.</description>
41648 <description>Port size 26 is selected.</description>
41655 <description>Indicates which port size is currently selected.</description>
41661 <description>Port size 27 is not selected.</description>
41666 <description>Port size 27 is selected.</description>
41673 <description>Indicates which port size is currently selected.</description>
41679 <description>Port size 28 is not selected.</description>
41684 <description>Port size 28 is selected.</description>
41691 <description>Indicates which port size is currently selected.</description>
41697 <description>Port size 29 is not selected.</description>
41702 <description>Port size 29 is selected.</description>
41709 <description>Indicates which port size is currently selected.</description>
41715 <description>Port size 30 is not selected.</description>
41720 <description>Port size 30 is selected.</description>
41727 <description>Indicates which port size is currently selected.</description>
41733 <description>Port size 31 is not selected.</description>
41738 <description>Port size 31 is selected.</description>
41745 <description>Indicates which port size is currently selected.</description>
41751 <description>Port size 32 is not selected.</description>
41756 <description>Port size 32 is selected.</description>
41765 …description>The Supported_trigger_modes register indicates the implemented trigger counter multipl…
41773 …<description>Indicates whether multiplying the trigger counter by 2^(0+1) is supported.</descripti…
41779 … <description>Multiplying the trigger counter by 2^(0+1) is supported.</description>
41784 … <description>Multiplying the trigger counter by 2^(0+1) is supported.</description>
41791 …<description>Indicates whether multiplying the trigger counter by 2^(1+1) is supported.</descripti…
41797 … <description>Multiplying the trigger counter by 2^(1+1) is supported.</description>
41802 … <description>Multiplying the trigger counter by 2^(1+1) is supported.</description>
41809 …<description>Indicates whether multiplying the trigger counter by 2^(2+1) is supported.</descripti…
41815 … <description>Multiplying the trigger counter by 2^(2+1) is supported.</description>
41820 … <description>Multiplying the trigger counter by 2^(2+1) is supported.</description>
41827 …<description>Indicates whether multiplying the trigger counter by 2^(3+1) is supported.</descripti…
41833 … <description>Multiplying the trigger counter by 2^(3+1) is supported.</description>
41838 … <description>Multiplying the trigger counter by 2^(3+1) is supported.</description>
41845 …<description>Indicates whether multiplying the trigger counter by 2^(4+1) is supported.</descripti…
41851 … <description>Multiplying the trigger counter by 2^(4+1) is supported.</description>
41856 … <description>Multiplying the trigger counter by 2^(4+1) is supported.</description>
41863 … <description>Indicates whether an 8-bit wide counter register is implemented.</description>
41869 <description>An 8-bit wide counter register is implemented.</description>
41874 <description>An 8-bit wide counter register is implemented.</description>
41881 <description>A trigger has occurred and the counter has reached 0.</description>
41887 <description>Trigger has not occurred.</description>
41892 <description>Trigger has occurred.</description>
41899 <description>A trigger has occurred but the counter is not at 0.</description>
41905 … <description>Either a trigger has not occurred or the counter is at 0.</description>
41910 <description>A trigger has occurred but the counter is not at 0.</description>
41919 …description>The Trigger_counter_value register enables delaying the indication of triggers to any …
41927 …<description>8-bit counter value for the number of words to be output from the formatter before a …
41935 …<description>The Trigger_multiplier register contains the selectors for the trigger counter multip…
41943 <description>Multiply the Trigger Counter by 2^n.</description>
41949 <description>Multiplier disabled.</description>
41954 <description>Multiplier enabled.</description>
41961 <description>Multiply the Trigger Counter by 2^n.</description>
41967 <description>Multiplier disabled.</description>
41972 <description>Multiplier enabled.</description>
41979 <description>Multiply the Trigger Counter by 2^n.</description>
41985 <description>Multiplier disabled.</description>
41990 <description>Multiplier enabled.</description>
41997 <description>Multiply the Trigger Counter by 2^n.</description>
42003 <description>Multiplier disabled.</description>
42008 <description>Multiplier enabled.</description>
42015 <description>Multiply the Trigger Counter by 2^n.</description>
42021 <description>Multiplier disabled.</description>
42026 <description>Multiplier enabled.</description>
42035 …description>The Supported_test_pattern_modes register provides a set of known bit sequences or pat…
42043 …<description>Indicates whether the walking 1s pattern is supported as output over the trace port.<…
42049 <description>Test pattern is not supported.</description>
42054 <description>Test pattern is supported.</description>
42061 …<description>Indicates whether the walking 0s pattern is supported as output over the trace port.<…
42067 <description>Test pattern is not supported.</description>
42072 <description>Test pattern is supported.</description>
42079 …<description>Indicates whether the AA/55 pattern is supported as output over the trace port.</desc…
42085 <description>Test pattern is not supported.</description>
42090 <description>Test pattern is supported.</description>
42097 …<description>Indicates whether the FF/00 pattern is supported as output over the trace port.</desc…
42103 <description>Test pattern is not supported.</description>
42108 <description>Test pattern is supported.</description>
42115 <description>Indicates whether timed mode is supported.</description>
42121 <description>Mode is not supported.</description>
42126 <description>Mode is supported.</description>
42133 <description>Indicates whether continuous mode is supported.</description>
42139 <description>Mode is not supported.</description>
42144 <description>Mode is supported.</description>
42153 …<description>Current_test_pattern_mode indicates the current test pattern or mode selected.</descr…
42161 …<description>Indicates whether the walking 1s pattern is supported as output over the trace port.<…
42167 <description>Test pattern is disabled.</description>
42172 <description>Test pattern is enabled.</description>
42179 …<description>Indicates whether the walking 0s pattern is supported as output over the trace port.<…
42185 <description>Test pattern is disabled.</description>
42190 <description>Test pattern is enabled.</description>
42197 …<description>Indicates whether the AA/55 pattern is supported as output over the trace port.</desc…
42203 <description>Test pattern is disabled.</description>
42208 <description>Test pattern is enabled.</description>
42215 …<description>Indicates whether the FF/00 pattern is supported as output over the trace port.</desc…
42221 <description>Test pattern is disabled.</description>
42226 <description>Test pattern is enabled.</description>
42233 <description>Indicates whether timed mode is supported.</description>
42239 <description>Mode is disabled.</description>
42244 <description>Mode is enabled.</description>
42251 <description>Indicates whether continuous mode is supported.</description>
42257 <description>Mode is disabled.</description>
42262 <description>Mode is enabled.</description>
42271 …description>The TPRCR register is an 8-bit counter start value that is decremented. A write sets t…
42279 …description>8-bit counter value to indicate the number of traceclkin cycles for which a pattern ru…
42287 …<description>The FFSR register indicates the current status of the formatter and flush features av…
42295 <description>Flush in progress.</description>
42301 <description>A flush is not in progress.</description>
42306 <description>A flush is in progress.</description>
42313 …description>The formatter has received a stop request signal and all trace data and post-amble is …
42319 <description>Formatter has not stopped.</description>
42324 <description>Formatter has stopped.</description>
42331 <description>Indicates whether the TRACECTL pin is available for use.</description>
42337 <description>TRACECTL pin is not present.</description>
42342 <description>TRACECTL pin is present.</description>
42351 …<description>The FFCR register controls the generation of stop, trigger, and flush events.</descri…
42359 …<description>Do not embed triggers into the formatted stream. Trace disable cycles and triggers ar…
42365 <description>The formatting feature is disabled.</description>
42370 <description>The formatting feature is enabled.</description>
42377 …<description>Is embedded in trigger packets and indicates that no cycle is using sync packets.</de…
42383 <description>The formatting feature is disabled.</description>
42388 <description>The formatting feature is enabled.</description>
42395 <description>Enables the use of the flushin connection.</description>
42401 <description>The formatting feature is disabled.</description>
42406 <description>The formatting feature is enabled.</description>
42413 …<description>Initiates a manual flush of data in the system when a trigger event occurs.</descript…
42419 <description>The formatting feature is disabled.</description>
42424 <description>The formatting feature is enabled.</description>
42431 … <description>Generates a flush. This bit is set to 0 when this flush is serviced.</description>
42437 <description>The formatting feature is disabled.</description>
42442 <description>The formatting feature is enabled.</description>
42449 … <description>Generates a flush. This bit is set to 1 when this flush is serviced.</description>
42455 <description>The formatting feature is disabled.</description>
42460 <description>The formatting feature is enabled.</description>
42467 <description>Indicates a trigger when trigin is asserted.</description>
42473 <description>The formatting feature is disabled.</description>
42478 <description>The formatting feature is enabled.</description>
42485 <description>Indicates a trigger on a trigger event.</description>
42491 <description>The formatting feature is disabled.</description>
42496 <description>The formatting feature is enabled.</description>
42503 … <description>Indicates a trigger when flush completion on afreadys is returned.</description>
42509 <description>The formatting feature is disabled.</description>
42514 <description>The formatting feature is enabled.</description>
42521 <description>Forces the FIFO to drain off any part-completed packets.</description>
42527 <description>The formatting feature is disabled.</description>
42532 <description>The formatting feature is enabled.</description>
42539 …<description>Stops the formatter after a trigger event is observed. Reset to disabled or 0.</descr…
42545 <description>The formatting feature is disabled.</description>
42550 <description>The formatting feature is enabled.</description>
42559 …description>The FSCR register enables the frequency of synchronization information to be optimized…
42567 …<description>12-bit counter reload value. Indicates the number of complete frames between full syn…
42575 …description>Two ports can be used as a control and feedback mechanism for any serializers, pin sha…
42583 <description>EXTCTL inputs.</description>
42589 <description>Input EXTCTL0 is low.</description>
42594 <description>Input EXTCTL0 is high.</description>
42601 <description>EXTCTL inputs.</description>
42607 <description>Input EXTCTL1 is low.</description>
42612 <description>Input EXTCTL1 is high.</description>
42619 <description>EXTCTL inputs.</description>
42625 <description>Input EXTCTL2 is low.</description>
42630 <description>Input EXTCTL2 is high.</description>
42637 <description>EXTCTL inputs.</description>
42643 <description>Input EXTCTL3 is low.</description>
42648 <description>Input EXTCTL3 is high.</description>
42655 <description>EXTCTL inputs.</description>
42661 <description>Input EXTCTL4 is low.</description>
42666 <description>Input EXTCTL4 is high.</description>
42673 <description>EXTCTL inputs.</description>
42679 <description>Input EXTCTL5 is low.</description>
42684 <description>Input EXTCTL5 is high.</description>
42691 <description>EXTCTL inputs.</description>
42697 <description>Input EXTCTL6 is low.</description>
42702 <description>Input EXTCTL6 is high.</description>
42709 <description>EXTCTL inputs.</description>
42715 <description>Input EXTCTL7 is low.</description>
42720 <description>Input EXTCTL7 is high.</description>
42729 …description>Two ports can be used as a control and feedback mechanism for any serializers, pin sha…
42737 <description>EXTCTL outputs.</description>
42743 <description>Output EXTCTL0 is low.</description>
42748 <description>Output EXTCTL0 is high.</description>
42755 <description>EXTCTL outputs.</description>
42761 <description>Output EXTCTL1 is low.</description>
42766 <description>Output EXTCTL1 is high.</description>
42773 <description>EXTCTL outputs.</description>
42779 <description>Output EXTCTL2 is low.</description>
42784 <description>Output EXTCTL2 is high.</description>
42791 <description>EXTCTL outputs.</description>
42797 <description>Output EXTCTL3 is low.</description>
42802 <description>Output EXTCTL3 is high.</description>
42809 <description>EXTCTL outputs.</description>
42815 <description>Output EXTCTL4 is low.</description>
42820 <description>Output EXTCTL4 is high.</description>
42827 <description>EXTCTL outputs.</description>
42833 <description>Output EXTCTL5 is low.</description>
42838 <description>Output EXTCTL5 is high.</description>
42845 <description>EXTCTL outputs.</description>
42851 <description>Output EXTCTL6 is low.</description>
42856 <description>Output EXTCTL6 is high.</description>
42863 <description>EXTCTL outputs.</description>
42869 <description>Output EXTCTL7 is low.</description>
42874 <description>Output EXTCTL7 is high.</description>
42883 …<description>The ITTRFLINACK register enables control of the triginack and flushinack outputs from…
42891 <description>Sets the value of triginack.</description>
42897 <description>Pin is logic 0.</description>
42902 <description>Pin is logic 1.</description>
42909 <description>Sets the value of flushinack.</description>
42915 <description>Pin is logic 0.</description>
42920 <description>Pin is logic 1.</description>
42929 …<description>The ITTRFLIN register contains the values of the flushin and trigin inputs to the TPI…
42937 <description>Reads the value of trigin.</description>
42943 <description>Pin is logic 0.</description>
42948 <description>Pin is logic 1.</description>
42955 <description>Reads the value of flushin.</description>
42961 <description>Pin is logic 0.</description>
42966 <description>Pin is logic 1.</description>
42975 …<description>The ITATBDATA0 register contains the value of the atdatas inputs to the TPIU. The val…
42983 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
42989 <description>Pin is logic 0.</description>
42994 <description>Pin is logic 1.</description>
43001 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
43007 <description>Pin is logic 0.</description>
43012 <description>Pin is logic 1.</description>
43019 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
43025 <description>Pin is logic 0.</description>
43030 <description>Pin is logic 1.</description>
43037 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
43043 <description>Pin is logic 0.</description>
43048 <description>Pin is logic 1.</description>
43055 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
43061 <description>Pin is logic 0.</description>
43066 <description>Pin is logic 1.</description>
43075 … <description>Enables control of the atreadys and afvalids outputs of the TPIU.</description>
43083 <description>Sets the value of afvalid.</description>
43089 <description>Pin is logic 0.</description>
43094 <description>Pin is logic 1.</description>
43101 <description>Sets the value of atready.</description>
43107 <description>Pin is logic 0.</description>
43112 <description>Pin is logic 1.</description>
43121 …<description>The ITATBCTR1 register contains the value of the atids input to the TPIU. This is onl…
43129 <description>Reads the value of atids.</description>
43135 <description>Pin is logic 0.</description>
43140 <description>Pin is logic 1.</description>
43149 …<description>The ITATBCTR0 register captures the values of the atvalids, afreadys, and atbytess in…
43150 …ctly in a system, the value of atbytess is only valid when atvalids, bit[0], is HIGH.</description>
43158 <description>Reads the value of atvalids.</description>
43164 <description>Pin is logic 0.</description>
43169 <description>Pin is logic 1.</description>
43176 <description>Reads the value of afreadys.</description>
43182 <description>Pin is logic 0.</description>
43187 <description>Pin is logic 1.</description>
43194 <description>Reads the value of atbytess.</description>
43200 <description>Pin is logic 0.</description>
43205 <description>Pin is logic 1.</description>
43214 <description>Used to enable topology detection.
43216 …he component can be directly controlled for integration testing and topology solving.</description>
43224 …description>Enables the component to switch from functional mode to integration mode and back. If …
43230 <description>Integration mode is disabled.</description>
43235 <description>Integration mode is Enabled.</description>
43244 …<description>Software can use the claim tag to coordinate application and debugger access to trace…
43245 …ster sets bits in the claim tag, and determines the number of claim bits implemented.</description>
43253 <description>Set claim bit 0 and check if bit is implemented or not.</description>
43260 <description>Claim bit 0 is not implemented.</description>
43265 <description>Claim bit 0 is implemented.</description>
43273 <description>Set claim bit 0.</description>
43280 <description>Set claim bit 1 and check if bit is implemented or not.</description>
43287 <description>Claim bit 1 is not implemented.</description>
43292 <description>Claim bit 1 is implemented.</description>
43300 <description>Set claim bit 1.</description>
43307 <description>Set claim bit 2 and check if bit is implemented or not.</description>
43314 <description>Claim bit 2 is not implemented.</description>
43319 <description>Claim bit 2 is implemented.</description>
43327 <description>Set claim bit 2.</description>
43334 <description>Set claim bit 3 and check if bit is implemented or not.</description>
43341 <description>Claim bit 3 is not implemented.</description>
43346 <description>Claim bit 3 is implemented.</description>
43354 <description>Set claim bit 3.</description>
43363 …<description>Software can use the claim tag to coordinate application and debugger access to trace…
43365 …ets the bits in the claim tag to 0 and determines the current value of the claim tag.</description>
43373 <description>Read or clear claim bit 0.</description>
43380 <description>Claim bit 0 is not set.</description>
43385 <description>Claim bit 0 is set.</description>
43393 <description>Clear claim bit 0.</description>
43400 <description>Read or clear claim bit 1.</description>
43407 <description>Claim bit 1 is not set.</description>
43412 <description>Claim bit 1 is set.</description>
43420 <description>Clear claim bit 1.</description>
43427 <description>Read or clear claim bit 2.</description>
43434 <description>Claim bit 2 is not set.</description>
43439 <description>Claim bit 2 is set.</description>
43447 <description>Clear claim bit 2.</description>
43454 <description>Read or clear claim bit 3.</description>
43461 <description>Claim bit 3 is not set.</description>
43466 <description>Claim bit 3 is set.</description>
43474 <description>Clear claim bit 3.</description>
43483 <description>This is used to enable write access to device registers.</description>
43491 …<description>A write of 0xC5ACCE55 enables further write access to this device. Any other write re…
43497 <description>Unlock register interface.</description>
43506 …<description>This indicates the status of the lock control mechanism. This lock prevents accidenta…
43510 … For most components this covers all registers except for the Lock Access Register.</description>
43518 … <description>Indicates that a lock control mechanism exists for this device.</description>
43524 …<description>No lock control mechanism exists, writes to the Lock Access Register are ignored.</de…
43529 <description>Lock control mechanism is present.</description>
43536 <description>Returns the current status of the Lock.</description>
43542 <description>Write access is allowed to this device.</description>
43547 …<description>Write access to the component is blocked. All writes to control registers are ignored…
43554 …<description>Indicates if the Lock Access Register is implemented as 8-bit or 32-bit.</description>
43560 … <description>This component implements a 32-bit Lock Access Register.</description>
43565 … <description>This component implements an 8-bit Lock Access Register.</description>
43574 <description>Indicates the current level of tracing permitted by the system</description>
43582 <description>Non-secure Invasive Debug</description>
43588 <description>The feature is not implemented.</description>
43593 <description>The feature is implemented.</description>
43600 <description>Non-secure Non-Invasive Debug</description>
43606 <description>The feature is not implemented.</description>
43611 <description>The feature is implemented.</description>
43618 <description>Secure Invasive Debug</description>
43624 <description>The feature is not implemented.</description>
43629 <description>The feature is implemented.</description>
43636 <description>Secure Non-Invasive Debug</description>
43642 <description>The feature is not implemented.</description>
43647 <description>The feature is implemented.</description>
43656 <description>Indicates the capabilities of the component.</description>
43664 …<description>Indicates the hidden level of input multiplexing. When non-zero, this value indicates…
43665 …rted, that is, no multiplexing is present. This value helps detect the ATB structure.</description>
43671 <description>Indicates the relationship between atclk and traceclkin.</description>
43677 <description>atclk and traceclkin are synchronous.</description>
43682 <description>atclk and traceclkin are asynchronous.</description>
43689 <description>FIFO size in powers of 2.</description>
43695 <description>FIFO size of 4 entries, that is, 16 bytes.</description>
43702 <description>Indicates whether trace clock plus data is supported.</description>
43708 <description>Trace clock and data is supported.</description>
43713 <description>Trace clock and data is not supported.</description>
43720 …<description>Indicates whether Serial Wire Output, Manchester encoded format, is supported.</descr…
43726 … <description>Serial Wire Output, Manchester encoded format, is not supported.</description>
43731 … <description>Serial Wire Output, Manchester encoded format, is supported.</description>
43738 … <description>Indicates whether Serial Wire Output, UART or NRZ, is supported.</description>
43744 <description>Serial Wire Output, UART or NRZ, is not supported.</description>
43749 <description>Serial Wire Output, UART or NRZ, is supported.</description>
43758 …description>The DEVTYPE register provides a debugger with information about the component when the…
43766 <description>The main type of the component</description>
43772 <description>Peripheral is a trace sink.</description>
43779 <description>The sub-type of the component</description>
43785 … <description>Indicates that this component is a trace port component.</description>
43794 <description>Coresight peripheral identification registers.</description>
43802 <description>Coresight peripheral identification registers.</description>
43810 <description>Coresight peripheral identification registers.</description>
43818 <description>Coresight peripheral identification registers.</description>
43826 <description>Coresight peripheral identification registers.</description>
43834 <description>Coresight component identification registers.</description>
43842 <description>Coresight component identification registers.</description>
43850 <description>Coresight component identification registers.</description>
43858 <description>Coresight component identification registers.</description>
43868 <description>Embedded Trace Buffer</description>
43882 <description>ETB RAM Depth Register</description>
43890 <description>Defines the depth, in words, of the trace RAM.</description>
43898 <description>ETB Status Register</description>
43906 …<description>RAM Full. The flag indicates when the RAM write pointer has wrapped around.</descript…
43912 …description>The Triggered bit is set when a trigger has been observed. This does not indicate that…
43918 …description>The acquisition complete flag indicates that capture has been completed when the forma…
43924 <description>Formatter pipeline empty. All data stored to RAM.</description>
43932 <description>ETB RAM Read Data Register</description>
43940 <description>Data read from the ETB Trace RAM.</description>
43948 <description>ETB RAM Read Pointer Register</description>
43956 …<description>Sets the read pointer used to read entries from the Trace RAM over the APB interface.…
43964 <description>ETB RAM Write Pointer Register</description>
43972 …<description>Sets the write pointer used to write entries from the CoreSight bus into the Trace RA…
43980 <description>ETB Trigger Counter Register</description>
43988 …description>The counter is used as follows:Trace after - The counter is set to a large value, slig…
43996 <description>ETB Control Register</description>
44004 …description>ETB Trace Capture Enable. This is the master enable bit forcing FtStopped HIGH when Tr…
44012 <description>ETB RAM Write Data Register</description>
44020 …description>Data written to the ETB Trace RAM. When trace capture is disabled, the contents of thi…
44028 <description>ETB Formatter and Flush Status Register</description>
44036 …<description>Flush In Progress. This is an indication of the current state of afvalids.</descripti…
44042 …description>Formatter stopped. The formatter has received a stop request signal and all trace data…
44050 <description>ETB Formatter and Flush Control Register</description>
44058 …description>Do not embed Triggers into the formatted stream. Trace disable cycles and triggers are…
44064 …description>Continuous mode in the ETB corresponds to normal mode with the embedding of triggers. …
44070 …<description>Set this bit to enable use of the flushin connection. This is clear on reset.</descri…
44076 …description>Generate flush using Trigger event. Set this bit to cause a flush of data in the syste…
44082 …description>Setting this bit causes a flush to be generated. This is cleared when this flush has b…
44088 <description>Indicate a trigger on trigin being asserted.</description>
44094 <description>Indicate a trigger on a Trigger Event.</description>
44100 … <description>Indicates a trigger on Flush completion (afreadys being returned).</description>
44106 …description>This forces the FIFO to drain off any part-completed packets. Setting this bit enables…
44112 …<description>Stop the formatter after a Trigger Event is observed. Reset to disabled (zero).</desc…
44120 <description>Integration Test Miscellaneous Output Register 0</description>
44128 <description>Set the value of acqcomp.</description>
44134 <description>Set the value of full output port.</description>
44142 <description>Integration Test Trigger In and Flush In Acknowledge Register</description>
44150 <description>Set the value of triginack.</description>
44156 <description>Set the value of flushinack.</description>
44164 <description>Integration Test Trigger In and Flush In Register</description>
44172 <description>Read the value of trigin.</description>
44178 <description>Read the value of flushin.</description>
44186 <description>Integration Test ATB Data Register 0</description>
44194 <description>Read the value of atdatas[0].</description>
44200 <description>Read the value of atdatas[7].</description>
44206 <description>Read the value of atdatas[15].</description>
44212 <description>Read the value of atdatas[23].</description>
44218 <description>Read the value of atdatas[31].</description>
44226 <description>Integration Test ATB Control Register 2</description>
44234 <description>Set the value of atreadys.</description>
44240 <description>Set the value of afvalids.</description>
44248 <description>Integration Test ATB Control Register 1</description>
44256 <description>Read the value of atids.</description>
44264 <description>Integration Test ATB Control Register 0</description>
44272 <description>Read the value of atvalids.</description>
44278 <description>Read the value of afreadys.</description>
44284 <description>Read the value of atbytess.</description>
44292 <description>Integration Mode Control Register</description>
44300 …<description>Allows the component to switch from functional mode to integration mode or back.</des…
44308 <description>Claim Tag Set Register</description>
44316 <description>This claim tag bit is implemented</description>
44324 <description>Claim Tag Clear Register</description>
44332 … <description>The value present reflects the current setting of the Claim Tag.</description>
44340 <description>Lock Access Register</description>
44348 …description>A write of 0xC5ACCE55 enables further write access to this device. A write of any valu…
44356 <description>Lock Status Register</description>
44364 …description>Indicates that a lock control mechanism exists for this device. This bit reads as 0 wh…
44370 …description>Returns the current status of the Lock. This bit reads as 0 when read from an external…
44376 …<description>Indicates if the Lock Access Register (0xFB0) is implemented as 8-bit or 32-bit</desc…
44384 <description>Authentication Status Register</description>
44392 <description>Indicates the security level for non-secure invasive debug</description>
44398 … <description>Indicates the security level for non-secure non-invasive debug</description>
44404 <description>Indicates the security level for secure invasive debug</description>
44410 <description>Indicates the security level for secure non-invasive debug</description>
44418 <description>Device Configuration Register</description>
44426 …<description>When non-zero this value indicates the type/number of ATB multiplexing present on the…
44432 …<description>This bit returns 0 on reads indicating that the ETB RAM operates synchronously to atc…
44440 <description>Device Type Identifier Register</description>
44448 … <description>Major classification grouping for this debug/trace component</description>
44454 <description>Sub-classification within the major category</description>
44462 <description>Peripheral ID4 Register</description>
44470 …<description>JEDEC continuation code indicating the designer of the component (along with the iden…
44476 …description>This is a 4-bit value that indicates the total contiguous size of the memory window us…
44484 <description>Peripheral ID0 Register</description>
44492 …<description>Bits [7:0] of the component's part number. This is selected by the designer of the co…
44500 <description>Peripheral ID1 Register</description>
44508 …<description>Bits [11:8] of the component's part number. This is selected by the designer of the c…
44514 …<description>Bits 3:0 of the JEDEC identity code indicating the designer of the component (along w…
44522 <description>Peripheral ID2 Register</description>
44530 …<description>Bits 6:4 of the JEDEC identity code indicating the designer of the component (along w…
44536 <description>Always set. Indicates that a JEDEC assigned value is used</description>
44542 …description>The Revision field is an incremental value starting at 0x0 for the first design of thi…
44550 <description>Peripheral ID3 Register</description>
44558 …description>Where the component is reusable IP, this value indicates if the customer has modified …
44564 …description>This field indicates minor errata fixes specific to this design, for example metal fix…
44572 <description>Component ID0 Register</description>
44580 <description>Contains bits [7:0] of the component identification</description>
44588 <description>Component ID1 Register</description>
44596 <description>Contains bits [11:8] of the component identification</description>
44602 …<description>Class of the component. E. g. ROM table, CoreSight component etc. Constitutes bits [1…
44610 <description>Component ID2 Register</description>
44618 <description>Contains bits [23:16] of the component identification</description>
44626 <description>Component ID3 Register</description>
44634 <description>Contains bits [31:24] of the component identification</description>
44644 <description>Cross-Trigger Interface control 0</description>
44659 <description>CTI Control register</description>
44667 <description>Enables or disables the CTI.</description>
44673 … <description>All cross-triggering mapping logic functionality is disabled.</description>
44678 … <description>Cross-triggering mapping logic functionality is enabled.</description>
44687 <description>CTI Interrupt Acknowledge register</description>
44695 <description>Acknowledges the ctitrigout 0 output.</description>
44702 <description>Clears the ctitrigout.</description>
44709 <description>Acknowledges the ctitrigout 1 output.</description>
44716 <description>Clears the ctitrigout.</description>
44723 <description>Acknowledges the ctitrigout 2 output.</description>
44730 <description>Clears the ctitrigout.</description>
44737 <description>Acknowledges the ctitrigout 3 output.</description>
44744 <description>Clears the ctitrigout.</description>
44751 <description>Acknowledges the ctitrigout 4 output.</description>
44758 <description>Clears the ctitrigout.</description>
44765 <description>Acknowledges the ctitrigout 5 output.</description>
44772 <description>Clears the ctitrigout.</description>
44779 <description>Acknowledges the ctitrigout 6 output.</description>
44786 <description>Clears the ctitrigout.</description>
44793 <description>Acknowledges the ctitrigout 7 output.</description>
44800 <description>Clears the ctitrigout.</description>
44809 <description>CTI Application Trigger Set register</description>
44817 <description>Application trigger event for channel 0.</description>
44824 <description>Application trigger 0 is inactive.</description>
44829 <description>Application trigger 0 is active.</description>
44837 <description>Generate channel event for channel 0.</description>
44844 <description>Application trigger event for channel 1.</description>
44851 <description>Application trigger 1 is inactive.</description>
44856 <description>Application trigger 1 is active.</description>
44864 <description>Generate channel event for channel 1.</description>
44871 <description>Application trigger event for channel 2.</description>
44878 <description>Application trigger 2 is inactive.</description>
44883 <description>Application trigger 2 is active.</description>
44891 <description>Generate channel event for channel 2.</description>
44898 <description>Application trigger event for channel 3.</description>
44905 <description>Application trigger 3 is inactive.</description>
44910 <description>Application trigger 3 is active.</description>
44918 <description>Generate channel event for channel 3.</description>
44927 <description>CTI Application Trigger Clear register</description>
44935 …<description>Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register f…
44942 <description>Clears the event for channel 0.</description>
44949 …<description>Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register f…
44956 <description>Clears the event for channel 1.</description>
44963 …<description>Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register f…
44970 <description>Clears the event for channel 2.</description>
44977 …<description>Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register f…
44984 <description>Clears the event for channel 3.</description>
44993 <description>CTI Application Pulse register</description>
45001 …description>Setting a bit HIGH generates a channel event pulse for the selected channel. There is …
45008 <description>Generates an event pulse on channel 0.</description>
45015 …description>Setting a bit HIGH generates a channel event pulse for the selected channel. There is …
45022 <description>Generates an event pulse on channel 1.</description>
45029 …description>Setting a bit HIGH generates a channel event pulse for the selected channel. There is …
45036 <description>Generates an event pulse on channel 2.</description>
45043 …description>Setting a bit HIGH generates a channel event pulse for the selected channel. There is …
45050 <description>Generates an event pulse on channel 3.</description>
45061 <description>Description collection: CTI Trigger to Channel Enable register</description>
45069 …<description>Enables a cross trigger event to channel 0 when a ctitrigin input is activated.</desc…
45075 <description>Input trigger n events are ignored by channel 0.</description>
45080 …<description>When an event is received on input trigger n (ctitrigin[n]), generate an event on cha…
45087 …<description>Enables a cross trigger event to channel 1 when a ctitrigin input is activated.</desc…
45093 <description>Input trigger n events are ignored by channel 1.</description>
45098 …<description>When an event is received on input trigger n (ctitrigin[n]), generate an event on cha…
45105 …<description>Enables a cross trigger event to channel 2 when a ctitrigin input is activated.</desc…
45111 <description>Input trigger n events are ignored by channel 2.</description>
45116 …<description>When an event is received on input trigger n (ctitrigin[n]), generate an event on cha…
45123 …<description>Enables a cross trigger event to channel 3 when a ctitrigin input is activated.</desc…
45129 <description>Input trigger n events are ignored by channel 3.</description>
45134 …<description>When an event is received on input trigger n (ctitrigin[n]), generate an event on cha…
45145 <description>Description collection: CTI Channel to Trigger Enable register</description>
45153 …<description>Enables a cross trigger event to ctitrigout when channel 0 is activated.</description>
45159 <description>Channel 0 is ignored by output trigger n.</description>
45164 …<description>When an event occurs on channel 0, generate an event on output event n (ctitrigout[n]…
45171 …<description>Enables a cross trigger event to ctitrigout when channel 1 is activated.</description>
45177 <description>Channel 1 is ignored by output trigger n.</description>
45182 …<description>When an event occurs on channel 1, generate an event on output event n (ctitrigout[n]…
45189 …<description>Enables a cross trigger event to ctitrigout when channel 2 is activated.</description>
45195 <description>Channel 2 is ignored by output trigger n.</description>
45200 …<description>When an event occurs on channel 2, generate an event on output event n (ctitrigout[n]…
45207 …<description>Enables a cross trigger event to ctitrigout when channel 3 is activated.</description>
45213 <description>Channel 3 is ignored by output trigger n.</description>
45218 …<description>When an event occurs on channel 3, generate an event on output event n (ctitrigout[n]…
45227 <description>CTI Trigger In Status register</description>
45235 <description>Shows the status of ctitrigin0 input.</description>
45241 <description>Ctitrigin 0 is active.</description>
45246 <description>Ctitrigin 0 is inactive.</description>
45253 <description>Shows the status of ctitrigin1 input.</description>
45259 <description>Ctitrigin 1 is active.</description>
45264 <description>Ctitrigin 1 is inactive.</description>
45271 <description>Shows the status of ctitrigin2 input.</description>
45277 <description>Ctitrigin 2 is active.</description>
45282 <description>Ctitrigin 2 is inactive.</description>
45289 <description>Shows the status of ctitrigin3 input.</description>
45295 <description>Ctitrigin 3 is active.</description>
45300 <description>Ctitrigin 3 is inactive.</description>
45307 <description>Shows the status of ctitrigin4 input.</description>
45313 <description>Ctitrigin 4 is active.</description>
45318 <description>Ctitrigin 4 is inactive.</description>
45325 <description>Shows the status of ctitrigin5 input.</description>
45331 <description>Ctitrigin 5 is active.</description>
45336 <description>Ctitrigin 5 is inactive.</description>
45343 <description>Shows the status of ctitrigin6 input.</description>
45349 <description>Ctitrigin 6 is active.</description>
45354 <description>Ctitrigin 6 is inactive.</description>
45361 <description>Shows the status of ctitrigin7 input.</description>
45367 <description>Ctitrigin 7 is active.</description>
45372 <description>Ctitrigin 7 is inactive.</description>
45381 <description>CTI Trigger Out Status register</description>
45389 <description>Shows the status of ctitrigout0 output.</description>
45395 <description>Ctitrigout 0 is active.</description>
45400 <description>Ctitrigout 0 is inactive.</description>
45407 <description>Shows the status of ctitrigout1 output.</description>
45413 <description>Ctitrigout 1 is active.</description>
45418 <description>Ctitrigout 1 is inactive.</description>
45425 <description>Shows the status of ctitrigout2 output.</description>
45431 <description>Ctitrigout 2 is active.</description>
45436 <description>Ctitrigout 2 is inactive.</description>
45443 <description>Shows the status of ctitrigout3 output.</description>
45449 <description>Ctitrigout 3 is active.</description>
45454 <description>Ctitrigout 3 is inactive.</description>
45461 <description>Shows the status of ctitrigout4 output.</description>
45467 <description>Ctitrigout 4 is active.</description>
45472 <description>Ctitrigout 4 is inactive.</description>
45479 <description>Shows the status of ctitrigout5 output.</description>
45485 <description>Ctitrigout 5 is active.</description>
45490 <description>Ctitrigout 5 is inactive.</description>
45497 <description>Shows the status of ctitrigout6 output.</description>
45503 <description>Ctitrigout 6 is active.</description>
45508 <description>Ctitrigout 6 is inactive.</description>
45515 <description>Shows the status of ctitrigout7 output.</description>
45521 <description>Ctitrigout 7 is active.</description>
45526 <description>Ctitrigout 7 is inactive.</description>
45535 <description>CTI Channel In Status register</description>
45543 <description>Shows the status of the ctitrigin 0 input.</description>
45549 <description>Ctichin 0 is active.</description>
45554 <description>Ctichin 0 is inactive.</description>
45561 <description>Shows the status of the ctitrigin 1 input.</description>
45567 <description>Ctichin 1 is active.</description>
45572 <description>Ctichin 1 is inactive.</description>
45579 <description>Shows the status of the ctitrigin 2 input.</description>
45585 <description>Ctichin 2 is active.</description>
45590 <description>Ctichin 2 is inactive.</description>
45597 <description>Shows the status of the ctitrigin 3 input.</description>
45603 <description>Ctichin 3 is active.</description>
45608 <description>Ctichin 3 is inactive.</description>
45617 <description>Enable CTI Channel Gate register</description>
45625 <description>Enable ctichout0.</description>
45631 <description>Enable ctichout channel 0 propagation.</description>
45636 <description>Disable ctichout channel 0 propagation.</description>
45643 <description>Enable ctichout1.</description>
45649 <description>Enable ctichout channel 1 propagation.</description>
45654 <description>Disable ctichout channel 1 propagation.</description>
45661 <description>Enable ctichout2.</description>
45667 <description>Enable ctichout channel 2 propagation.</description>
45672 <description>Disable ctichout channel 2 propagation.</description>
45679 <description>Enable ctichout3.</description>
45685 <description>Enable ctichout channel 3 propagation.</description>
45690 <description>Disable ctichout channel 3 propagation.</description>
45699 <description>Device Architecture register</description>
45707 <description>Contains the CTI device architecture.</description>
45715 <description>Device Configuration register</description>
45723 …<description>Indicates the number of multiplexers available on Trigger Inputs and Trigger Outputs …
45724 … The default value of 0b00000 indicates that no multiplexing is present.</description>
45730 <description>Number of ECT triggers available.</description>
45736 <description>Number of ECT channels available.</description>
45744 <description>Device Type Identifier register</description>
45752 …<description>Major classification of the type of the debug component as specified in the Arm Archi…
45753 debug and trace component.</description>
45759 …<description>Indicates that this component allows a debugger to control other components in an Arm…
45766 …<description>Sub-classification of the type of the debug component as specified in the Arm Archite…
45767 the major classification as specified in the MAJOR field.</description>
45773 … <description>Indicates that this component is a sub-triggering component.</description>
45782 <description>Peripheral ID4 Register</description>
45790 …<description>Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the comp…
45796 <description>JEDEC continuation code.</description>
45803 … <description>Always 0b0000. Indicates that the device only occupies 4KB of memory.</description>
45811 <description>Peripheral ID5 register</description>
45819 <description>Peripheral ID6 register</description>
45827 <description>Peripheral ID7 register</description>
45835 <description>Peripheral ID0 Register</description>
45843 …<description>Bits[7:0] of the 12-bit part number of the component. The designer of the component a…
45849 … <description>Indicates bits[7:0] of the part number of the component.</description>
45858 <description>Peripheral ID1 Register</description>
45866 …<description>Bits[11:8] of the 12-bit part number of the component. The designer of the component …
45872 … <description>Indicates bits[11:8] of the part number of the component.</description>
45879 …<description>Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the comp…
45885 <description>Arm. Bits[3:0] of the JEDEC JEP106 Identity Code</description>
45894 <description>Peripheral ID2 Register</description>
45902 …<description>Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the comp…
45908 <description>Arm. Bits[6:4] of the JEDEC JEP106 Identity Code</description>
45915 … <description>Always 1. Indicates that the JEDEC-assigned designer ID is used.</description>
45921 <description>Peripheral revision</description>
45927 <description>This device is at r0p0</description>
45936 <description>Peripheral ID3 Register</description>
45944 …<description>Customer Modified. Indicates whether the customer has modified the behavior of the co…
45945 …ustomers change this value when they make authorized modifications to this component.</description>
45951 … <description>Indicates that the customer has not modified this component.</description>
45958 …<description>Indicates minor errata fixes specific to the revision of the component being used, fo…
45960 …is field if required, for example, by driving it from registers that reset to 0b0000.</description>
45966 … <description>Indicates that there are no errata fixes to this component.</description>
45975 <description>Component ID0 Register</description>
45983 … <description>Preamble[0]. Contains bits[7:0] of the component identification code.</description>
45989 <description>Bits[7:0] of the identification code.</description>
45998 <description>Component ID1 Register</description>
46006 … <description>Preamble[1]. Contains bits[11:8] of the component identification code.</description>
46012 <description>Bits[11:8] of the identification code.</description>
46019 …<description>Class of the component, for example, whether the component is a ROM table or a generi…
46020 Contains bits[15:12] of the component identification code</description>
46026 <description>Indicates that the component is a CoreSight component.</description>
46035 <description>Component ID2 Register</description>
46043 … <description>Preamble[2]. Contains bits[23:16] of the component identification code.</description>
46049 <description>Bits[23:16] of the identification code.</description>
46058 <description>Component ID3 Register</description>
46066 … <description>Preamble[3]. Contains bits[31:24] of the component identification code.</description>
46072 <description>Bits[31:24] of the identification code.</description>
46083 <description>Cross-Trigger Interface control 1</description>
46090 <description>ATB Replicator module 0</description>
46105 …<description>The IDFILTER0 register enables the programming of ID filtering for master port 0.</de…
46113 <description>Enable or disable ID filtering for IDs 0x00_0x0F.</description>
46119 … <description>Transactions with these IDs are passed on to ATB master port 0.</description>
46124 … <description>Transactions with these IDs are discarded by the replicator.</description>
46131 <description>Enable or disable ID filtering for IDs 0x10_0x1F.</description>
46137 … <description>Transactions with these IDs are passed on to ATB master port 0.</description>
46142 … <description>Transactions with these IDs are discarded by the replicator.</description>
46149 <description>Enable or disable ID filtering for IDs 0x20_0x2F.</description>
46155 … <description>Transactions with these IDs are passed on to ATB master port 0.</description>
46160 … <description>Transactions with these IDs are discarded by the replicator.</description>
46167 <description>Enable or disable ID filtering for IDs 0x30_0x3F.</description>
46173 … <description>Transactions with these IDs are passed on to ATB master port 0.</description>
46178 … <description>Transactions with these IDs are discarded by the replicator.</description>
46185 <description>Enable or disable ID filtering for IDs 0x40_0x4F.</description>
46191 … <description>Transactions with these IDs are passed on to ATB master port 0.</description>
46196 … <description>Transactions with these IDs are discarded by the replicator.</description>
46203 <description>Enable or disable ID filtering for IDs 0x50_0x5F.</description>
46209 … <description>Transactions with these IDs are passed on to ATB master port 0.</description>
46214 … <description>Transactions with these IDs are discarded by the replicator.</description>
46221 <description>Enable or disable ID filtering for IDs 0x60_0x6F.</description>
46227 … <description>Transactions with these IDs are passed on to ATB master port 0.</description>
46232 … <description>Transactions with these IDs are discarded by the replicator.</description>
46239 <description>Enable or disable ID filtering for IDs 0x70_0x7F.</description>
46245 … <description>Transactions with these IDs are passed on to ATB master port 0.</description>
46250 … <description>Transactions with these IDs are discarded by the replicator.</description>
46259 …<description>The IDFILTER1 register enables the programming of ID filtering for master port 1.</de…
46267 <description>Enable or disable ID filtering for IDs 0x00_0x0F.</description>
46273 … <description>Transactions with these IDs are passed on to ATB master port 1.</description>
46278 … <description>Transactions with these IDs are discarded by the replicator.</description>
46285 <description>Enable or disable ID filtering for IDs 0x10_0x1F.</description>
46291 … <description>Transactions with these IDs are passed on to ATB master port 1.</description>
46296 … <description>Transactions with these IDs are discarded by the replicator.</description>
46303 <description>Enable or disable ID filtering for IDs 0x20_0x2F.</description>
46309 … <description>Transactions with these IDs are passed on to ATB master port 1.</description>
46314 … <description>Transactions with these IDs are discarded by the replicator.</description>
46321 <description>Enable or disable ID filtering for IDs 0x30_0x3F.</description>
46327 … <description>Transactions with these IDs are passed on to ATB master port 1.</description>
46332 … <description>Transactions with these IDs are discarded by the replicator.</description>
46339 <description>Enable or disable ID filtering for IDs 0x40_0x4F.</description>
46345 … <description>Transactions with these IDs are passed on to ATB master port 1.</description>
46350 … <description>Transactions with these IDs are discarded by the replicator.</description>
46357 <description>Enable or disable ID filtering for IDs 0x50_0x5F.</description>
46363 … <description>Transactions with these IDs are passed on to ATB master port 1.</description>
46368 … <description>Transactions with these IDs are discarded by the replicator.</description>
46375 <description>Enable or disable ID filtering for IDs 0x60_0x6F.</description>
46381 … <description>Transactions with these IDs are passed on to ATB master port 1.</description>
46386 … <description>Transactions with these IDs are discarded by the replicator.</description>
46393 <description>Enable or disable ID filtering for IDs 0x70_0x7F.</description>
46399 … <description>Transactions with these IDs are passed on to ATB master port 1.</description>
46404 … <description>Transactions with these IDs are discarded by the replicator.</description>
46413 …<description>The ITATBCTR1 register returns the value of the atreadym0, atreadym1, and atvalids in…
46421 <description>Reads the value of the atreadym0 input.</description>
46427 <description>Pin is logic 0.</description>
46432 <description>Pin is logic 1.</description>
46439 <description>Reads the value of the atreadym1 input.</description>
46445 <description>Pin is logic 0.</description>
46450 <description>Pin is logic 1.</description>
46457 <description>Reads the value of the atvalids input.</description>
46463 <description>Pin is logic 0.</description>
46468 <description>Pin is logic 1.</description>
46477 …<description>The ITATBCTR0 register controls the value of the atvalidm0, atvalidm1, and atreadys o…
46485 <description>Sets the value of the atvalidm0 output.</description>
46491 <description>Pin is logic 0.</description>
46496 <description>Pin is logic 1.</description>
46503 <description>Sets the value of the atvalidm1 output.</description>
46509 <description>Pin is logic 0.</description>
46514 <description>Pin is logic 1.</description>
46521 <description>Sets the value of the atreadys output.</description>
46527 <description>Pin is logic 0.</description>
46532 <description>Pin is logic 1.</description>
46541 …<description>The ITCTRL register enables the component to switch from a functional mode, which is …
46542 …e directly controlled for the purposes of integration testing and topology detection.</description>
46550 <description>Integration Mode Enable.</description>
46556 <description>Integration mode disabled.</description>
46561 <description>Integration mode enabled.</description>
46570 …<description>Software can use the claim tag to coordinate application and debugger access to trace…
46571 …ster sets bits in the claim tag, and determines the number of claim bits implemented.</description>
46579 <description>Set claim bit 0 and check if bit is implemented or not.</description>
46586 <description>Claim bit 0 is not implemented.</description>
46591 <description>Claim bit 0 is implemented.</description>
46599 <description>Set claim bit 0.</description>
46606 <description>Set claim bit 1 and check if bit is implemented or not.</description>
46613 <description>Claim bit 1 is not implemented.</description>
46618 <description>Claim bit 1 is implemented.</description>
46626 <description>Set claim bit 1.</description>
46633 <description>Set claim bit 2 and check if bit is implemented or not.</description>
46640 <description>Claim bit 2 is not implemented.</description>
46645 <description>Claim bit 2 is implemented.</description>
46653 <description>Set claim bit 2.</description>
46660 <description>Set claim bit 3 and check if bit is implemented or not.</description>
46667 <description>Claim bit 3 is not implemented.</description>
46672 <description>Claim bit 3 is implemented.</description>
46680 <description>Set claim bit 3.</description>
46689 …<description>Software can use the claim tag to coordinate application and debugger access to trace…
46691 …ets the bits in the claim tag to 0 and determines the current value of the claim tag.</description>
46699 <description>Read or clear claim bit 0.</description>
46706 <description>Claim bit 0 is not set.</description>
46711 <description>Claim bit 0 is set.</description>
46719 <description>Clear claim bit 0.</description>
46726 <description>Read or clear claim bit 1.</description>
46733 <description>Claim bit 1 is not set.</description>
46738 <description>Claim bit 1 is set.</description>
46746 <description>Clear claim bit 1.</description>
46753 <description>Read or clear claim bit 2.</description>
46760 <description>Claim bit 2 is not set.</description>
46765 <description>Claim bit 2 is set.</description>
46773 <description>Clear claim bit 2.</description>
46780 <description>Read or clear claim bit 3.</description>
46787 <description>Claim bit 3 is not set.</description>
46792 <description>Claim bit 3 is set.</description>
46800 <description>Clear claim bit 3.</description>
46809 <description>This is used to enable write access to device registers.</description>
46817 …<description>A write of 0xC5ACCE55 enables further write access to this device. Any other write re…
46823 <description>Unlock register interface.</description>
46832 …<description>This indicates the status of the lock control mechanism. This lock prevents accidenta…
46836 … For most components this covers all registers except for the Lock Access Register.</description>
46844 … <description>Indicates that a lock control mechanism exists for this device.</description>
46850 …<description>No lock control mechanism exists, writes to the Lock Access Register are ignored.</de…
46855 <description>Lock control mechanism is present.</description>
46862 <description>Returns the current status of the Lock.</description>
46868 <description>Write access is allowed to this device.</description>
46873 …<description>Write access to the component is blocked. All writes to control registers are ignored…
46880 …<description>Indicates if the Lock Access Register is implemented as 8-bit or 32-bit.</description>
46886 … <description>This component implements a 32-bit Lock Access Register.</description>
46891 … <description>This component implements an 8-bit Lock Access Register.</description>
46900 <description>Indicates the current level of tracing permitted by the system</description>
46908 <description>Non-secure Invasive Debug</description>
46914 <description>The feature is not implemented.</description>
46919 <description>The feature is implemented.</description>
46926 <description>Non-secure Non-Invasive Debug</description>
46932 <description>The feature is not implemented.</description>
46937 <description>The feature is implemented.</description>
46944 <description>Secure Invasive Debug</description>
46950 <description>The feature is not implemented.</description>
46955 <description>The feature is implemented.</description>
46962 <description>Secure Non-Invasive Debug</description>
46968 <description>The feature is not implemented.</description>
46973 <description>The feature is implemented.</description>
46982 <description>Indicates the capabilities of the component.</description>
46990 <description>Indicates the number of master ports implemented.</description>
46998 …description>The DEVTYPE register provides a debugger with information about the component when the…
47006 <description>The main type of the component</description>
47012 … <description>Indicates that this component has ATB inputs and outputs.</description>
47019 <description>The sub-type of the component</description>
47025 …<description>Indicates that this component replicates trace from a single source to multiple targe…
47034 <description>Coresight peripheral identification registers.</description>
47042 <description>Coresight peripheral identification registers.</description>
47050 <description>Coresight peripheral identification registers.</description>
47058 <description>Coresight peripheral identification registers.</description>
47066 <description>Coresight peripheral identification registers.</description>
47074 <description>Coresight component identification registers.</description>
47082 <description>Coresight component identification registers.</description>
47090 <description>Coresight component identification registers.</description>
47098 <description>Coresight component identification registers.</description>
47108 <description>ATB Replicator module 1</description>
47115 <description>ATB Replicator module 2</description>
47122 <description>ATB Replicator module 3</description>
47129 <description>ATB funnel module 0</description>
47144 …<description>The IDFILTER0 register enables the programming of ID filtering for master port 0.</de…
47152 <description>Enable slave port 0.</description>
47158 …<description>Slave port disabled. This excludes the port from the priority selection scheme.</desc…
47163 <description>Slave port enabled.</description>
47170 <description>Enable slave port 1.</description>
47176 …<description>Slave port disabled. This excludes the port from the priority selection scheme.</desc…
47181 <description>Slave port enabled.</description>
47188 <description>Enable slave port 2.</description>
47194 …<description>Slave port disabled. This excludes the port from the priority selection scheme.</desc…
47199 <description>Slave port enabled.</description>
47206 <description>Enable slave port 3.</description>
47212 …<description>Slave port disabled. This excludes the port from the priority selection scheme.</desc…
47217 <description>Slave port enabled.</description>
47224 <description>Enable slave port 4.</description>
47230 …<description>Slave port disabled. This excludes the port from the priority selection scheme.</desc…
47235 <description>Slave port enabled.</description>
47242 <description>Enable slave port 5.</description>
47248 …<description>Slave port disabled. This excludes the port from the priority selection scheme.</desc…
47253 <description>Slave port enabled.</description>
47260 <description>Enable slave port 6.</description>
47266 …<description>Slave port disabled. This excludes the port from the priority selection scheme.</desc…
47271 <description>Slave port enabled.</description>
47278 <description>Enable slave port 7.</description>
47284 …<description>Slave port disabled. This excludes the port from the priority selection scheme.</desc…
47289 <description>Slave port enabled.</description>
47296 …<description>Hold Time. The formatting scheme can become inefficient when fast switching occurs, a…
47299 …hat can be entered is 0b1110 and this equates to 15 transactions. 0b1111 is reserved.</description>
47307 …description>The Priority_Ctrl_Reg register defines the order in which inputs are selected. Each 3-…
47315 <description>Priority value of port number 0.</description>
47321 <description>Priority value of port number 1.</description>
47327 <description>Priority value of port number 2.</description>
47333 <description>Priority value of port number 3.</description>
47339 <description>Priority value of port number 4.</description>
47345 <description>Priority value of port number 5.</description>
47351 <description>Priority value of port number 6.</description>
47357 <description>Priority value of port number 7.</description>
47365 …<description>The ITATBDATA0 register performs different functions depending on whether the access …
47373 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47379 <description>Pin is logic 0.</description>
47384 <description>Pin is logic 1.</description>
47391 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47397 <description>Pin is logic 0.</description>
47402 <description>Pin is logic 1.</description>
47409 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47415 <description>Pin is logic 0.</description>
47420 <description>Pin is logic 1.</description>
47427 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47433 <description>Pin is logic 0.</description>
47438 <description>Pin is logic 1.</description>
47445 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47451 <description>Pin is logic 0.</description>
47456 <description>Pin is logic 1.</description>
47463 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47469 <description>Pin is logic 0.</description>
47474 <description>Pin is logic 1.</description>
47481 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47487 <description>Pin is logic 0.</description>
47492 <description>Pin is logic 1.</description>
47499 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47505 <description>Pin is logic 0.</description>
47510 <description>Pin is logic 1.</description>
47517 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47523 <description>Pin is logic 0.</description>
47528 <description>Pin is logic 1.</description>
47535 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47541 <description>Pin is logic 0.</description>
47546 <description>Pin is logic 1.</description>
47553 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47559 <description>Pin is logic 0.</description>
47564 <description>Pin is logic 1.</description>
47571 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47577 <description>Pin is logic 0.</description>
47582 <description>Pin is logic 1.</description>
47589 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47595 <description>Pin is logic 0.</description>
47600 <description>Pin is logic 1.</description>
47607 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47613 <description>Pin is logic 0.</description>
47618 <description>Pin is logic 1.</description>
47625 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47631 <description>Pin is logic 0.</description>
47636 <description>Pin is logic 1.</description>
47643 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47649 <description>Pin is logic 0.</description>
47654 <description>Pin is logic 1.</description>
47661 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47667 <description>Pin is logic 0.</description>
47672 <description>Pin is logic 1.</description>
47681 …<description>The ITATBCTR2 register performs different functions depending on whether the access i…
47689 <description>A read access returns the value of atreadym.
47690 …s outputs the data to afvalids[n], where the value of the CTRLREG at 0x000 defines n.</description>
47696 <description>Pin is logic 0.</description>
47701 <description>Pin is logic 1.</description>
47708 <description>A read access returns the value of afvalidm.
47709 …s outputs the data to atreadys[n], where the value of the CTRLREG at 0x000 defines n.</description>
47715 <description>Pin is logic 0.</description>
47720 <description>Pin is logic 1.</description>
47729 …<description>The ITATBCTR1 register performs different functions depending on whether the access i…
47737 …<description>A read returns the value of the atids[n] signals, where the value of the Control Regi…
47738 A write outputs the value to the atidm port.</description>
47744 <description>Pin is logic 0.</description>
47749 <description>Pin is logic 1.</description>
47758 …<description>The ITATBCTR0 register performs different functions depending on whether the access i…
47766 …<description>A read returns the value of the atvalids[n] signal, where the value of the CTRLREG at…
47767 A write outputs the value to atvalidm.</description>
47773 <description>Pin is logic 0.</description>
47778 <description>Pin is logic 1.</description>
47785 …<description>A read returns the value of the afreadys[n] signal, where the value of the Ctrl_Reg a…
47786 A write outputs the value to afreadym.</description>
47792 <description>Pin is logic 0.</description>
47797 <description>Pin is logic 1.</description>
47804 …<description>A read returns the value of the atbytess[n] signal, where the value of the Ctrl_Reg a…
47805 A write outputs the value to atbytesm.</description>
47811 <description>Pin is logic 0.</description>
47816 <description>Pin is logic 1.</description>
47825 …<description>The ITCTRL register enables the component to switch from a functional mode, which is …
47826 …e directly controlled for the purposes of integration testing and topology detection.</description>
47834 <description>Integration Mode Enable.</description>
47840 <description>Integration mode disabled.</description>
47845 <description>Integration mode enabled.</description>
47854 …<description>Software can use the claim tag to coordinate application and debugger access to trace…
47855 …ster sets bits in the claim tag, and determines the number of claim bits implemented.</description>
47863 <description>Set claim bit 0 and check if bit is implemented or not.</description>
47870 <description>Claim bit 0 is not implemented.</description>
47875 <description>Claim bit 0 is implemented.</description>
47883 <description>Set claim bit 0.</description>
47890 <description>Set claim bit 1 and check if bit is implemented or not.</description>
47897 <description>Claim bit 1 is not implemented.</description>
47902 <description>Claim bit 1 is implemented.</description>
47910 <description>Set claim bit 1.</description>
47917 <description>Set claim bit 2 and check if bit is implemented or not.</description>
47924 <description>Claim bit 2 is not implemented.</description>
47929 <description>Claim bit 2 is implemented.</description>
47937 <description>Set claim bit 2.</description>
47944 <description>Set claim bit 3 and check if bit is implemented or not.</description>
47951 <description>Claim bit 3 is not implemented.</description>
47956 <description>Claim bit 3 is implemented.</description>
47964 <description>Set claim bit 3.</description>
47973 …<description>Software can use the claim tag to coordinate application and debugger access to trace…
47975 …ets the bits in the claim tag to 0 and determines the current value of the claim tag.</description>
47983 <description>Read or clear claim bit 0.</description>
47990 <description>Claim bit 0 is not set.</description>
47995 <description>Claim bit 0 is set.</description>
48003 <description>Clear claim bit 0.</description>
48010 <description>Read or clear claim bit 1.</description>
48017 <description>Claim bit 1 is not set.</description>
48022 <description>Claim bit 1 is set.</description>
48030 <description>Clear claim bit 1.</description>
48037 <description>Read or clear claim bit 2.</description>
48044 <description>Claim bit 2 is not set.</description>
48049 <description>Claim bit 2 is set.</description>
48057 <description>Clear claim bit 2.</description>
48064 <description>Read or clear claim bit 3.</description>
48071 <description>Claim bit 3 is not set.</description>
48076 <description>Claim bit 3 is set.</description>
48084 <description>Clear claim bit 3.</description>
48093 <description>This is used to enable write access to device registers.</description>
48101 …<description>A write of 0xC5ACCE55 enables further write access to this device. Any other write re…
48107 <description>Unlock register interface.</description>
48116 …<description>This indicates the status of the lock control mechanism. This lock prevents accidenta…
48120 … For most components this covers all registers except for the Lock Access Register.</description>
48128 … <description>Indicates that a lock control mechanism exists for this device.</description>
48134 …<description>No lock control mechanism exists, writes to the Lock Access Register are ignored.</de…
48139 <description>Lock control mechanism is present.</description>
48146 <description>Returns the current status of the Lock.</description>
48152 <description>Write access is allowed to this device.</description>
48157 …<description>Write access to the component is blocked. All writes to control registers are ignored…
48164 …<description>Indicates if the Lock Access Register is implemented as 8-bit or 32-bit.</description>
48170 … <description>This component implements a 32-bit Lock Access Register.</description>
48175 … <description>This component implements an 8-bit Lock Access Register.</description>
48184 <description>Indicates the current level of tracing permitted by the system</description>
48192 <description>Non-secure Invasive Debug</description>
48198 <description>The feature is not implemented.</description>
48203 <description>The feature is implemented.</description>
48210 <description>Non-secure Non-Invasive Debug</description>
48216 <description>The feature is not implemented.</description>
48221 <description>The feature is implemented.</description>
48228 <description>Secure Invasive Debug</description>
48234 <description>The feature is not implemented.</description>
48239 <description>The feature is implemented.</description>
48246 <description>Secure Non-Invasive Debug</description>
48252 <description>The feature is not implemented.</description>
48257 <description>The feature is implemented.</description>
48266 <description>Indicates the capabilities of the component.</description>
48274 …<description>Indicates the number of input ports connected. 0x0 and 0x1 are illegal values.</descr…
48282 …description>The DEVTYPE register provides a debugger with information about the component when the…
48290 <description>The main type of the component</description>
48296 … <description>Indicates that this component has ATB inputs and outputs.</description>
48303 <description>The sub-type of the component</description>
48309 … <description>This component arbitrates ATB inputs mapping to ATB outputs.</description>
48318 <description>Coresight peripheral identification registers.</description>
48326 <description>Coresight peripheral identification registers.</description>
48334 <description>Coresight peripheral identification registers.</description>
48342 <description>Coresight peripheral identification registers.</description>
48350 <description>Coresight peripheral identification registers.</description>
48358 <description>Coresight component identification registers.</description>
48366 <description>Coresight component identification registers.</description>
48374 <description>Coresight component identification registers.</description>
48382 <description>Coresight component identification registers.</description>
48392 <description>ATB funnel module 1</description>
48399 <description>ATB funnel module 2</description>
48406 <description>ATB funnel module 3</description>
48413 <description>Granular Power Requester</description>
48427 <description>Debug Power Request Register</description>
48435 <description>Bit 0 of the cpwrupreq output port.</description>
48441 <description>Bit 1 of the cpwrupreq output port.</description>
48447 <description>Bit 2 of the cpwrupreq output port.</description>
48453 <description>Bit 3 of the cpwrupreq output port.</description>
48459 <description>Bit 4 of the cpwrupreq output port.</description>
48465 <description>Bit 5 of the cpwrupreq output port.</description>
48471 <description>Bit 6 of the cpwrupreq output port.</description>
48477 <description>Bit 7 of the cpwrupreq output port.</description>
48483 <description>Bit 8 of the cpwrupreq output port.</description>
48491 <description>Debug Power Acknowledge Register</description>
48499 <description>Bit 0 of the cpwrupack input port.</description>
48505 <description>Bit 1 of the cpwrupack input port.</description>
48511 <description>Bit 2 of the cpwrupack input port.</description>
48517 <description>Bit 3 of the cpwrupack input port.</description>
48523 <description>Bit 4 of the cpwrupack input port.</description>
48529 <description>Bit 5 of the cpwrupack input port.</description>
48535 <description>Bit 6 of the cpwrupack input port.</description>
48541 <description>Bit 7 of the cpwrupack input port.</description>
48547 <description>Bit 8 of the cpwrupack input port.</description>
48555 <description>Integration Mode Control Register</description>
48563 …<description>When you read this register, CXGPR returns a zero because no integration functionalit…
48571 <description>Claim Tag Set Register</description>
48579 …description>On Read for each bit 1 means claim tag bit implemented. On Write for each bit 0 has no…
48587 <description>Claim Tag Clear Register</description>
48595 … <description>The value present reflects the present value of the Claim Tag.</description>
48603 <description>Lock Access Register</description>
48611 …description>When you write 0xC5ACCE55, subsequent write operations to this device are enabled. Any…
48619 <description>Lock Status Register</description>
48627 … <description>Indicates that a lock control mechanism is present in this device.</description>
48633 <description>Returns the present lock status of the device.</description>
48639 … <description>Indicates that the Lock Access Register is implemented as 32-bit.</description>
48647 <description>Authentication Status Register</description>
48655 <description>Indicates the security level for Non-Secure Invasive Debug.</description>
48661 … <description>Indicates the security level for Non-Secure Non-Invasive Debug.</description>
48667 <description>Indicates the security level for Secure Invasive Debug.</description>
48673 <description>Indicates the security level for Secure Non-Invasive Debug.</description>
48681 <description>Device Architecture Register</description>
48689 <description>Indicates the architecture of the component.</description>
48695 <description>Indicates the revision of the architecture.</description>
48701 <description>Indicates whether the DEVARCH register is present.</description>
48707 …description>Indicates the JEP106 code pf the architect who specifies the architecture of the compo…
48715 <description>Device Configuration Register</description>
48723 …description>The value present in this field indicates the number of CPWRUP master interfaces avail…
48731 <description>Device Type Identifier Register</description>
48739 …description>Major classification of the type of the debug component as specified in the CoreSight …
48745 …description>Sub-classification of the type of the debug component as specified in the CoreSight Ar…
48753 <description>Peripheral ID4 Register</description>
48761 …description>This is the JEDEC JEP106 continuation code. This code along with, bits[6:4] of the ide…
48767 …description>This is a 4-bit value that indicates the total contiguous size in powers of two of the…
48775 <description>Peripheral ID0 Register</description>
48783 …<description>Bits [7:0] of the components 12 bit part number. The designer of the component assig…
48791 <description>Peripheral ID1 Register</description>
48799 …<description>Bits[11:8] of the components 12 bit part number. The designer of the component assig…
48805 …description>Bits[3:0] of the JEDEC JEP106 identity code. This code, along with bits[6:4] of the id…
48813 <description>Peripheral ID2 Register</description>
48821 …description>Bits[6:4] of the JEDEC JEP106 identity code. This code, along with bits[3:0] of the id…
48827 … <description>Always set. Indicates if the JEDEC assigned designer ID is used.</description>
48833 …description>An incremental value starting from 0x0 for the first revision of this component. This …
48841 <description>Peripheral ID3 Register</description>
48849 …description>Indicates if the customer modified the behavior of the component. In most cases, this …
48855 …description>Indicates minor errata fixes specific to the revision of the component being used, for…
48863 <description>Component ID0 Register</description>
48871 <description>Contains bits[7:0] of the component identification code.</description>
48879 <description>Component ID1 Register</description>
48887 <description>Contains bits [11:8] of the component identification</description>
48893 …description>Class of the component, for example, if the component is a ROM table or a generic Core…
48901 <description>Component ID2 Register</description>
48909 <description>Contains bits [23:16] of the component identification</description>
48917 <description>Component ID3 Register</description>
48925 <description>Contains bits [31:24] of the component identification</description>
48935 <description>VPR CLIC registers</description>
49012 <description>Unspecified</description>
49018 <description>CLIC configuration.</description>
49026 <description>Selective interrupt hardware vectoring.</description>
49032 <description>Selective interrupt hardware vectoring is implemented</description>
49039 <description>Interrupt level encoding.</description>
49045 <description>8 bits = interrupt levels encoded in eight bits</description>
49052 <description>Interrupt privilege mode.</description>
49058 <description>All interrupts are M-mode only</description>
49067 <description>CLIC information.</description>
49075 <description>Maximum number of interrupts supported.</description>
49081 <description>Version</description>
49087 <description>Number of maximum interrupt triggers supported</description>
49097 … <description>Description collection: Interrupt control register for IRQ number [n].</description>
49105 <description>Interrupt Pending bit.</description>
49111 <description>Interrupt not pending</description>
49116 <description>Interrupt pending</description>
49123 <description>Read as 0, write ignored.</description>
49130 <description>Interrupt enable bit.</description>
49136 <description>Interrupt disabled</description>
49141 <description>Interrupt enabled</description>
49148 <description>Read as 0, write ignored.</description>
49155 <description>Selective Hardware Vectoring.</description>
49162 <description>Hardware vectored</description>
49169 <description>Trigger type and polarity for each interrupt input.</description>
49176 <description>Interrupts are edge-triggered</description>
49183 <description>Privilege mode.</description>
49190 <description>Machine mode</description>
49197 <description>Interrupt priority level</description>
49203 <description>Priority level 0</description>
49208 <description>Priority level 1</description>
49213 <description>Priority level 2</description>
49218 <description>Priority level 3</description>
49230 <description>VTIM CSR registers</description>
49246 <description>Unused.</description>
49255 <description>GPIO Tasks and Events</description>
49281 …description>Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on…
49289 …<description>Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in C…
49295 <description>Trigger task</description>
49306 …<description>Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action o…
49314 …<description>Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high.…
49320 <description>Trigger task</description>
49331 …<description>Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action o…
49339 …<description>Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low.<…
49345 <description>Trigger task</description>
49356 <description>Description collection: Subscribe configuration for task OUT[n]</description>
49364 <description>DPPI channel that task OUT[n] will subscribe to</description>
49375 <description>Disable subscription</description>
49380 <description>Enable subscription</description>
49391 <description>Description collection: Subscribe configuration for task SET[n]</description>
49399 <description>DPPI channel that task SET[n] will subscribe to</description>
49410 <description>Disable subscription</description>
49415 <description>Enable subscription</description>
49426 <description>Description collection: Subscribe configuration for task CLR[n]</description>
49434 <description>DPPI channel that task CLR[n] will subscribe to</description>
49445 <description>Disable subscription</description>
49450 <description>Enable subscription</description>
49461 … <description>Description collection: Event from pin specified in CONFIG[n].PSEL</description>
49469 <description>Event from pin specified in CONFIG[n].PSEL</description>
49475 <description>Event not generated</description>
49480 <description>Event generated</description>
49491 <description>Peripheral events.</description>
49497 <description>Description cluster: Non-secure port event from owner n</description>
49506 <description>Non-secure port event from owner n</description>
49512 <description>Event not generated</description>
49517 <description>Event generated</description>
49526 <description>Description cluster: Secure port event from owner n</description>
49535 <description>Secure port event from owner n</description>
49541 <description>Event not generated</description>
49546 <description>Event generated</description>
49558 <description>Description collection: Publish configuration for event IN[n]</description>
49566 <description>DPPI channel that event IN[n] will publish to</description>
49577 <description>Disable publishing</description>
49582 <description>Enable publishing</description>
49593 <description>Publish configuration for events</description>
49599 … <description>Description cluster: Publish configuration for event PORT[n].NONSECURE</description>
49608 <description>DPPI channel that event PORT[n].NONSECURE will publish to</description>
49619 <description>Disable publishing</description>
49624 <description>Enable publishing</description>
49633 … <description>Description cluster: Publish configuration for event PORT[n].SECURE</description>
49642 <description>DPPI channel that event PORT[n].SECURE will publish to</description>
49653 <description>Disable publishing</description>
49658 <description>Enable publishing</description>
49668 <description>Enable interrupt</description>
49676 <description>Write '1' to enable interrupt for event IN[0]</description>
49683 <description>Read: Disabled</description>
49688 <description>Read: Enabled</description>
49696 <description>Enable</description>
49703 <description>Write '1' to enable interrupt for event IN[1]</description>
49710 <description>Read: Disabled</description>
49715 <description>Read: Enabled</description>
49723 <description>Enable</description>
49730 <description>Write '1' to enable interrupt for event IN[2]</description>
49737 <description>Read: Disabled</description>
49742 <description>Read: Enabled</description>
49750 <description>Enable</description>
49757 <description>Write '1' to enable interrupt for event IN[3]</description>
49764 <description>Read: Disabled</description>
49769 <description>Read: Enabled</description>
49777 <description>Enable</description>
49784 <description>Write '1' to enable interrupt for event IN[4]</description>
49791 <description>Read: Disabled</description>
49796 <description>Read: Enabled</description>
49804 <description>Enable</description>
49811 <description>Write '1' to enable interrupt for event IN[5]</description>
49818 <description>Read: Disabled</description>
49823 <description>Read: Enabled</description>
49831 <description>Enable</description>
49838 <description>Write '1' to enable interrupt for event IN[6]</description>
49845 <description>Read: Disabled</description>
49850 <description>Read: Enabled</description>
49858 <description>Enable</description>
49865 <description>Write '1' to enable interrupt for event IN[7]</description>
49872 <description>Read: Disabled</description>
49877 <description>Read: Enabled</description>
49885 <description>Enable</description>
49892 <description>Write '1' to enable interrupt for event PORT0NONSECURE</description>
49899 <description>Read: Disabled</description>
49904 <description>Read: Enabled</description>
49912 <description>Enable</description>
49919 <description>Write '1' to enable interrupt for event PORT0SECURE</description>
49926 <description>Read: Disabled</description>
49931 <description>Read: Enabled</description>
49939 <description>Enable</description>
49946 <description>Write '1' to enable interrupt for event PORT1NONSECURE</description>
49953 <description>Read: Disabled</description>
49958 <description>Read: Enabled</description>
49966 <description>Enable</description>
49973 <description>Write '1' to enable interrupt for event PORT1SECURE</description>
49980 <description>Read: Disabled</description>
49985 <description>Read: Enabled</description>
49993 <description>Enable</description>
50000 <description>Write '1' to enable interrupt for event PORT2NONSECURE</description>
50007 <description>Read: Disabled</description>
50012 <description>Read: Enabled</description>
50020 <description>Enable</description>
50027 <description>Write '1' to enable interrupt for event PORT2SECURE</description>
50034 <description>Read: Disabled</description>
50039 <description>Read: Enabled</description>
50047 <description>Enable</description>
50054 <description>Write '1' to enable interrupt for event PORT3NONSECURE</description>
50061 <description>Read: Disabled</description>
50066 <description>Read: Enabled</description>
50074 <description>Enable</description>
50081 <description>Write '1' to enable interrupt for event PORT3SECURE</description>
50088 <description>Read: Disabled</description>
50093 <description>Read: Enabled</description>
50101 <description>Enable</description>
50110 <description>Disable interrupt</description>
50118 <description>Write '1' to disable interrupt for event IN[0]</description>
50125 <description>Read: Disabled</description>
50130 <description>Read: Enabled</description>
50138 <description>Disable</description>
50145 <description>Write '1' to disable interrupt for event IN[1]</description>
50152 <description>Read: Disabled</description>
50157 <description>Read: Enabled</description>
50165 <description>Disable</description>
50172 <description>Write '1' to disable interrupt for event IN[2]</description>
50179 <description>Read: Disabled</description>
50184 <description>Read: Enabled</description>
50192 <description>Disable</description>
50199 <description>Write '1' to disable interrupt for event IN[3]</description>
50206 <description>Read: Disabled</description>
50211 <description>Read: Enabled</description>
50219 <description>Disable</description>
50226 <description>Write '1' to disable interrupt for event IN[4]</description>
50233 <description>Read: Disabled</description>
50238 <description>Read: Enabled</description>
50246 <description>Disable</description>
50253 <description>Write '1' to disable interrupt for event IN[5]</description>
50260 <description>Read: Disabled</description>
50265 <description>Read: Enabled</description>
50273 <description>Disable</description>
50280 <description>Write '1' to disable interrupt for event IN[6]</description>
50287 <description>Read: Disabled</description>
50292 <description>Read: Enabled</description>
50300 <description>Disable</description>
50307 <description>Write '1' to disable interrupt for event IN[7]</description>
50314 <description>Read: Disabled</description>
50319 <description>Read: Enabled</description>
50327 <description>Disable</description>
50334 <description>Write '1' to disable interrupt for event PORT0NONSECURE</description>
50341 <description>Read: Disabled</description>
50346 <description>Read: Enabled</description>
50354 <description>Disable</description>
50361 <description>Write '1' to disable interrupt for event PORT0SECURE</description>
50368 <description>Read: Disabled</description>
50373 <description>Read: Enabled</description>
50381 <description>Disable</description>
50388 <description>Write '1' to disable interrupt for event PORT1NONSECURE</description>
50395 <description>Read: Disabled</description>
50400 <description>Read: Enabled</description>
50408 <description>Disable</description>
50415 <description>Write '1' to disable interrupt for event PORT1SECURE</description>
50422 <description>Read: Disabled</description>
50427 <description>Read: Enabled</description>
50435 <description>Disable</description>
50442 <description>Write '1' to disable interrupt for event PORT2NONSECURE</description>
50449 <description>Read: Disabled</description>
50454 <description>Read: Enabled</description>
50462 <description>Disable</description>
50469 <description>Write '1' to disable interrupt for event PORT2SECURE</description>
50476 <description>Read: Disabled</description>
50481 <description>Read: Enabled</description>
50489 <description>Disable</description>
50496 <description>Write '1' to disable interrupt for event PORT3NONSECURE</description>
50503 <description>Read: Disabled</description>
50508 <description>Read: Enabled</description>
50516 <description>Disable</description>
50523 <description>Write '1' to disable interrupt for event PORT3SECURE</description>
50530 <description>Read: Disabled</description>
50535 <description>Read: Enabled</description>
50543 <description>Disable</description>
50552 <description>Enable interrupt</description>
50560 <description>Write '1' to enable interrupt for event IN[0]</description>
50567 <description>Read: Disabled</description>
50572 <description>Read: Enabled</description>
50580 <description>Enable</description>
50587 <description>Write '1' to enable interrupt for event IN[1]</description>
50594 <description>Read: Disabled</description>
50599 <description>Read: Enabled</description>
50607 <description>Enable</description>
50614 <description>Write '1' to enable interrupt for event IN[2]</description>
50621 <description>Read: Disabled</description>
50626 <description>Read: Enabled</description>
50634 <description>Enable</description>
50641 <description>Write '1' to enable interrupt for event IN[3]</description>
50648 <description>Read: Disabled</description>
50653 <description>Read: Enabled</description>
50661 <description>Enable</description>
50668 <description>Write '1' to enable interrupt for event IN[4]</description>
50675 <description>Read: Disabled</description>
50680 <description>Read: Enabled</description>
50688 <description>Enable</description>
50695 <description>Write '1' to enable interrupt for event IN[5]</description>
50702 <description>Read: Disabled</description>
50707 <description>Read: Enabled</description>
50715 <description>Enable</description>
50722 <description>Write '1' to enable interrupt for event IN[6]</description>
50729 <description>Read: Disabled</description>
50734 <description>Read: Enabled</description>
50742 <description>Enable</description>
50749 <description>Write '1' to enable interrupt for event IN[7]</description>
50756 <description>Read: Disabled</description>
50761 <description>Read: Enabled</description>
50769 <description>Enable</description>
50776 <description>Write '1' to enable interrupt for event PORT0NONSECURE</description>
50783 <description>Read: Disabled</description>
50788 <description>Read: Enabled</description>
50796 <description>Enable</description>
50803 <description>Write '1' to enable interrupt for event PORT0SECURE</description>
50810 <description>Read: Disabled</description>
50815 <description>Read: Enabled</description>
50823 <description>Enable</description>
50830 <description>Write '1' to enable interrupt for event PORT1NONSECURE</description>
50837 <description>Read: Disabled</description>
50842 <description>Read: Enabled</description>
50850 <description>Enable</description>
50857 <description>Write '1' to enable interrupt for event PORT1SECURE</description>
50864 <description>Read: Disabled</description>
50869 <description>Read: Enabled</description>
50877 <description>Enable</description>
50884 <description>Write '1' to enable interrupt for event PORT2NONSECURE</description>
50891 <description>Read: Disabled</description>
50896 <description>Read: Enabled</description>
50904 <description>Enable</description>
50911 <description>Write '1' to enable interrupt for event PORT2SECURE</description>
50918 <description>Read: Disabled</description>
50923 <description>Read: Enabled</description>
50931 <description>Enable</description>
50938 <description>Write '1' to enable interrupt for event PORT3NONSECURE</description>
50945 <description>Read: Disabled</description>
50950 <description>Read: Enabled</description>
50958 <description>Enable</description>
50965 <description>Write '1' to enable interrupt for event PORT3SECURE</description>
50972 <description>Read: Disabled</description>
50977 <description>Read: Enabled</description>
50985 <description>Enable</description>
50994 <description>Disable interrupt</description>
51002 <description>Write '1' to disable interrupt for event IN[0]</description>
51009 <description>Read: Disabled</description>
51014 <description>Read: Enabled</description>
51022 <description>Disable</description>
51029 <description>Write '1' to disable interrupt for event IN[1]</description>
51036 <description>Read: Disabled</description>
51041 <description>Read: Enabled</description>
51049 <description>Disable</description>
51056 <description>Write '1' to disable interrupt for event IN[2]</description>
51063 <description>Read: Disabled</description>
51068 <description>Read: Enabled</description>
51076 <description>Disable</description>
51083 <description>Write '1' to disable interrupt for event IN[3]</description>
51090 <description>Read: Disabled</description>
51095 <description>Read: Enabled</description>
51103 <description>Disable</description>
51110 <description>Write '1' to disable interrupt for event IN[4]</description>
51117 <description>Read: Disabled</description>
51122 <description>Read: Enabled</description>
51130 <description>Disable</description>
51137 <description>Write '1' to disable interrupt for event IN[5]</description>
51144 <description>Read: Disabled</description>
51149 <description>Read: Enabled</description>
51157 <description>Disable</description>
51164 <description>Write '1' to disable interrupt for event IN[6]</description>
51171 <description>Read: Disabled</description>
51176 <description>Read: Enabled</description>
51184 <description>Disable</description>
51191 <description>Write '1' to disable interrupt for event IN[7]</description>
51198 <description>Read: Disabled</description>
51203 <description>Read: Enabled</description>
51211 <description>Disable</description>
51218 <description>Write '1' to disable interrupt for event PORT0NONSECURE</description>
51225 <description>Read: Disabled</description>
51230 <description>Read: Enabled</description>
51238 <description>Disable</description>
51245 <description>Write '1' to disable interrupt for event PORT0SECURE</description>
51252 <description>Read: Disabled</description>
51257 <description>Read: Enabled</description>
51265 <description>Disable</description>
51272 <description>Write '1' to disable interrupt for event PORT1NONSECURE</description>
51279 <description>Read: Disabled</description>
51284 <description>Read: Enabled</description>
51292 <description>Disable</description>
51299 <description>Write '1' to disable interrupt for event PORT1SECURE</description>
51306 <description>Read: Disabled</description>
51311 <description>Read: Enabled</description>
51319 <description>Disable</description>
51326 <description>Write '1' to disable interrupt for event PORT2NONSECURE</description>
51333 <description>Read: Disabled</description>
51338 <description>Read: Enabled</description>
51346 <description>Disable</description>
51353 <description>Write '1' to disable interrupt for event PORT2SECURE</description>
51360 <description>Read: Disabled</description>
51365 <description>Read: Enabled</description>
51373 <description>Disable</description>
51380 <description>Write '1' to disable interrupt for event PORT3NONSECURE</description>
51387 <description>Read: Disabled</description>
51392 <description>Read: Enabled</description>
51400 <description>Disable</description>
51407 <description>Write '1' to disable interrupt for event PORT3SECURE</description>
51414 <description>Read: Disabled</description>
51419 <description>Read: Enabled</description>
51427 <description>Disable</description>
51436 …<description>Latency selection for Event mode (MODE=Event) with rising or falling edge detection o…
51445 <description>Latency setting</description>
51451 <description>Low power setting</description>
51456 <description>Low latency setting</description>
51467 …<description>Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] …
51475 <description>Mode</description>
51481 …<description>Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module.</descripti…
51486 <description>Event mode</description>
51491 <description>Task mode</description>
51498 …<description>GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event</descrip…
51504 <description>Port number</description>
51510 …description>When In task mode: Operation to be performed on output when OUT[n] task is triggered. …
51516 …<description>Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on…
51521 …<description>Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edg…
51526 …<description>Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling …
51531 …<description>Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin.…
51538 …<description>When in task mode: Initial value of the output when the GPIOTE channel is configured.…
51544 … <description>Task mode: Initial value of pin before task triggering is low</description>
51549 … <description>Task mode: Initial value of pin before task triggering is high</description>
51560 <description>Global Real-time counter</description>
51589 … <description>Description collection: Capture the counter value to CC[n] register</description>
51597 <description>Capture the counter value to CC[n] register</description>
51603 <description>Trigger task</description>
51612 <description>Start the PWM</description>
51620 <description>Start the PWM</description>
51626 <description>Trigger task</description>
51635 <description>Stop the PWM</description>
51643 <description>Stop the PWM</description>
51649 <description>Trigger task</description>
51660 … <description>Description collection: Subscribe configuration for task CAPTURE[n]</description>
51668 <description>DPPI channel that task CAPTURE[n] will subscribe to</description>
51679 <description>Disable subscription</description>
51684 <description>Enable subscription</description>
51695 <description>Description collection: Compare event on CC[n] match</description>
51703 <description>Compare event on CC[n] match</description>
51709 <description>Event not generated</description>
51714 <description>Event generated</description>
51723 … <description>The GRTC low frequency timer is synchronized with the SYSCOUNTER</description>
51731 … <description>The GRTC low frequency timer is synchronized with the SYSCOUNTER</description>
51737 <description>Event not generated</description>
51742 <description>Event generated</description>
51751 <description>Event on end of each PWM period</description>
51759 <description>Event on end of each PWM period</description>
51765 <description>Event not generated</description>
51770 <description>Event generated</description>
51781 … <description>Description collection: Publish configuration for event COMPARE[n]</description>
51789 <description>DPPI channel that event COMPARE[n] will publish to</description>
51800 <description>Disable publishing</description>
51805 <description>Enable publishing</description>
51814 <description>Shortcuts between local events and tasks</description>
51822 <description>Enable or disable interrupt</description>
51830 <description>Enable or disable interrupt for event COMPARE[0]</description>
51836 <description>Disable</description>
51841 <description>Enable</description>
51848 <description>Enable or disable interrupt for event COMPARE[1]</description>
51854 <description>Disable</description>
51859 <description>Enable</description>
51866 <description>Enable or disable interrupt for event COMPARE[2]</description>
51872 <description>Disable</description>
51877 <description>Enable</description>
51884 <description>Enable or disable interrupt for event COMPARE[3]</description>
51890 <description>Disable</description>
51895 <description>Enable</description>
51902 <description>Enable or disable interrupt for event COMPARE[4]</description>
51908 <description>Disable</description>
51913 <description>Enable</description>
51920 <description>Enable or disable interrupt for event COMPARE[5]</description>
51926 <description>Disable</description>
51931 <description>Enable</description>
51938 <description>Enable or disable interrupt for event COMPARE[6]</description>
51944 <description>Disable</description>
51949 <description>Enable</description>
51956 <description>Enable or disable interrupt for event COMPARE[7]</description>
51962 <description>Disable</description>
51967 <description>Enable</description>
51974 <description>Enable or disable interrupt for event COMPARE[8]</description>
51980 <description>Disable</description>
51985 <description>Enable</description>
51992 <description>Enable or disable interrupt for event COMPARE[9]</description>
51998 <description>Disable</description>
52003 <description>Enable</description>
52010 <description>Enable or disable interrupt for event COMPARE[10]</description>
52016 <description>Disable</description>
52021 <description>Enable</description>
52028 <description>Enable or disable interrupt for event COMPARE[11]</description>
52034 <description>Disable</description>
52039 <description>Enable</description>
52046 <description>Enable or disable interrupt for event COMPARE[12]</description>
52052 <description>Disable</description>
52057 <description>Enable</description>
52064 <description>Enable or disable interrupt for event COMPARE[13]</description>
52070 <description>Disable</description>
52075 <description>Enable</description>
52082 <description>Enable or disable interrupt for event COMPARE[14]</description>
52088 <description>Disable</description>
52093 <description>Enable</description>
52100 <description>Enable or disable interrupt for event COMPARE[15]</description>
52106 <description>Disable</description>
52111 <description>Enable</description>
52118 <description>Enable or disable interrupt for event RTCOMPARESYNC</description>
52124 <description>Disable</description>
52129 <description>Enable</description>
52136 <description>Enable or disable interrupt for event PWMPERIODEND</description>
52142 <description>Disable</description>
52147 <description>Enable</description>
52156 <description>Enable interrupt</description>
52164 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
52171 <description>Read: Disabled</description>
52176 <description>Read: Enabled</description>
52184 <description>Enable</description>
52191 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
52198 <description>Read: Disabled</description>
52203 <description>Read: Enabled</description>
52211 <description>Enable</description>
52218 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
52225 <description>Read: Disabled</description>
52230 <description>Read: Enabled</description>
52238 <description>Enable</description>
52245 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
52252 <description>Read: Disabled</description>
52257 <description>Read: Enabled</description>
52265 <description>Enable</description>
52272 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
52279 <description>Read: Disabled</description>
52284 <description>Read: Enabled</description>
52292 <description>Enable</description>
52299 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
52306 <description>Read: Disabled</description>
52311 <description>Read: Enabled</description>
52319 <description>Enable</description>
52326 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
52333 <description>Read: Disabled</description>
52338 <description>Read: Enabled</description>
52346 <description>Enable</description>
52353 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
52360 <description>Read: Disabled</description>
52365 <description>Read: Enabled</description>
52373 <description>Enable</description>
52380 <description>Write '1' to enable interrupt for event COMPARE[8]</description>
52387 <description>Read: Disabled</description>
52392 <description>Read: Enabled</description>
52400 <description>Enable</description>
52407 <description>Write '1' to enable interrupt for event COMPARE[9]</description>
52414 <description>Read: Disabled</description>
52419 <description>Read: Enabled</description>
52427 <description>Enable</description>
52434 <description>Write '1' to enable interrupt for event COMPARE[10]</description>
52441 <description>Read: Disabled</description>
52446 <description>Read: Enabled</description>
52454 <description>Enable</description>
52461 <description>Write '1' to enable interrupt for event COMPARE[11]</description>
52468 <description>Read: Disabled</description>
52473 <description>Read: Enabled</description>
52481 <description>Enable</description>
52488 <description>Write '1' to enable interrupt for event COMPARE[12]</description>
52495 <description>Read: Disabled</description>
52500 <description>Read: Enabled</description>
52508 <description>Enable</description>
52515 <description>Write '1' to enable interrupt for event COMPARE[13]</description>
52522 <description>Read: Disabled</description>
52527 <description>Read: Enabled</description>
52535 <description>Enable</description>
52542 <description>Write '1' to enable interrupt for event COMPARE[14]</description>
52549 <description>Read: Disabled</description>
52554 <description>Read: Enabled</description>
52562 <description>Enable</description>
52569 <description>Write '1' to enable interrupt for event COMPARE[15]</description>
52576 <description>Read: Disabled</description>
52581 <description>Read: Enabled</description>
52589 <description>Enable</description>
52596 <description>Write '1' to enable interrupt for event RTCOMPARESYNC</description>
52603 <description>Read: Disabled</description>
52608 <description>Read: Enabled</description>
52616 <description>Enable</description>
52623 <description>Write '1' to enable interrupt for event PWMPERIODEND</description>
52630 <description>Read: Disabled</description>
52635 <description>Read: Enabled</description>
52643 <description>Enable</description>
52652 <description>Disable interrupt</description>
52660 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
52667 <description>Read: Disabled</description>
52672 <description>Read: Enabled</description>
52680 <description>Disable</description>
52687 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
52694 <description>Read: Disabled</description>
52699 <description>Read: Enabled</description>
52707 <description>Disable</description>
52714 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
52721 <description>Read: Disabled</description>
52726 <description>Read: Enabled</description>
52734 <description>Disable</description>
52741 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
52748 <description>Read: Disabled</description>
52753 <description>Read: Enabled</description>
52761 <description>Disable</description>
52768 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
52775 <description>Read: Disabled</description>
52780 <description>Read: Enabled</description>
52788 <description>Disable</description>
52795 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
52802 <description>Read: Disabled</description>
52807 <description>Read: Enabled</description>
52815 <description>Disable</description>
52822 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
52829 <description>Read: Disabled</description>
52834 <description>Read: Enabled</description>
52842 <description>Disable</description>
52849 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
52856 <description>Read: Disabled</description>
52861 <description>Read: Enabled</description>
52869 <description>Disable</description>
52876 <description>Write '1' to disable interrupt for event COMPARE[8]</description>
52883 <description>Read: Disabled</description>
52888 <description>Read: Enabled</description>
52896 <description>Disable</description>
52903 <description>Write '1' to disable interrupt for event COMPARE[9]</description>
52910 <description>Read: Disabled</description>
52915 <description>Read: Enabled</description>
52923 <description>Disable</description>
52930 <description>Write '1' to disable interrupt for event COMPARE[10]</description>
52937 <description>Read: Disabled</description>
52942 <description>Read: Enabled</description>
52950 <description>Disable</description>
52957 <description>Write '1' to disable interrupt for event COMPARE[11]</description>
52964 <description>Read: Disabled</description>
52969 <description>Read: Enabled</description>
52977 <description>Disable</description>
52984 <description>Write '1' to disable interrupt for event COMPARE[12]</description>
52991 <description>Read: Disabled</description>
52996 <description>Read: Enabled</description>
53004 <description>Disable</description>
53011 <description>Write '1' to disable interrupt for event COMPARE[13]</description>
53018 <description>Read: Disabled</description>
53023 <description>Read: Enabled</description>
53031 <description>Disable</description>
53038 <description>Write '1' to disable interrupt for event COMPARE[14]</description>
53045 <description>Read: Disabled</description>
53050 <description>Read: Enabled</description>
53058 <description>Disable</description>
53065 <description>Write '1' to disable interrupt for event COMPARE[15]</description>
53072 <description>Read: Disabled</description>
53077 <description>Read: Enabled</description>
53085 <description>Disable</description>
53092 <description>Write '1' to disable interrupt for event RTCOMPARESYNC</description>
53099 <description>Read: Disabled</description>
53104 <description>Read: Enabled</description>
53112 <description>Disable</description>
53119 <description>Write '1' to disable interrupt for event PWMPERIODEND</description>
53126 <description>Read: Disabled</description>
53131 <description>Read: Enabled</description>
53139 <description>Disable</description>
53148 <description>Pending interrupts</description>
53156 <description>Read pending status of interrupt for event COMPARE[0]</description>
53163 <description>Read: Not pending</description>
53168 <description>Read: Pending</description>
53175 <description>Read pending status of interrupt for event COMPARE[1]</description>
53182 <description>Read: Not pending</description>
53187 <description>Read: Pending</description>
53194 <description>Read pending status of interrupt for event COMPARE[2]</description>
53201 <description>Read: Not pending</description>
53206 <description>Read: Pending</description>
53213 <description>Read pending status of interrupt for event COMPARE[3]</description>
53220 <description>Read: Not pending</description>
53225 <description>Read: Pending</description>
53232 <description>Read pending status of interrupt for event COMPARE[4]</description>
53239 <description>Read: Not pending</description>
53244 <description>Read: Pending</description>
53251 <description>Read pending status of interrupt for event COMPARE[5]</description>
53258 <description>Read: Not pending</description>
53263 <description>Read: Pending</description>
53270 <description>Read pending status of interrupt for event COMPARE[6]</description>
53277 <description>Read: Not pending</description>
53282 <description>Read: Pending</description>
53289 <description>Read pending status of interrupt for event COMPARE[7]</description>
53296 <description>Read: Not pending</description>
53301 <description>Read: Pending</description>
53308 <description>Read pending status of interrupt for event COMPARE[8]</description>
53315 <description>Read: Not pending</description>
53320 <description>Read: Pending</description>
53327 <description>Read pending status of interrupt for event COMPARE[9]</description>
53334 <description>Read: Not pending</description>
53339 <description>Read: Pending</description>
53346 <description>Read pending status of interrupt for event COMPARE[10]</description>
53353 <description>Read: Not pending</description>
53358 <description>Read: Pending</description>
53365 <description>Read pending status of interrupt for event COMPARE[11]</description>
53372 <description>Read: Not pending</description>
53377 <description>Read: Pending</description>
53384 <description>Read pending status of interrupt for event COMPARE[12]</description>
53391 <description>Read: Not pending</description>
53396 <description>Read: Pending</description>
53403 <description>Read pending status of interrupt for event COMPARE[13]</description>
53410 <description>Read: Not pending</description>
53415 <description>Read: Pending</description>
53422 <description>Read pending status of interrupt for event COMPARE[14]</description>
53429 <description>Read: Not pending</description>
53434 <description>Read: Pending</description>
53441 <description>Read pending status of interrupt for event COMPARE[15]</description>
53448 <description>Read: Not pending</description>
53453 <description>Read: Pending</description>
53460 <description>Read pending status of interrupt for event RTCOMPARESYNC</description>
53467 <description>Read: Not pending</description>
53472 <description>Read: Pending</description>
53479 <description>Read pending status of interrupt for event PWMPERIODEND</description>
53486 <description>Read: Not pending</description>
53491 <description>Read: Pending</description>
53500 <description>Enable or disable interrupt</description>
53508 <description>Enable or disable interrupt for event COMPARE[0]</description>
53514 <description>Disable</description>
53519 <description>Enable</description>
53526 <description>Enable or disable interrupt for event COMPARE[1]</description>
53532 <description>Disable</description>
53537 <description>Enable</description>
53544 <description>Enable or disable interrupt for event COMPARE[2]</description>
53550 <description>Disable</description>
53555 <description>Enable</description>
53562 <description>Enable or disable interrupt for event COMPARE[3]</description>
53568 <description>Disable</description>
53573 <description>Enable</description>
53580 <description>Enable or disable interrupt for event COMPARE[4]</description>
53586 <description>Disable</description>
53591 <description>Enable</description>
53598 <description>Enable or disable interrupt for event COMPARE[5]</description>
53604 <description>Disable</description>
53609 <description>Enable</description>
53616 <description>Enable or disable interrupt for event COMPARE[6]</description>
53622 <description>Disable</description>
53627 <description>Enable</description>
53634 <description>Enable or disable interrupt for event COMPARE[7]</description>
53640 <description>Disable</description>
53645 <description>Enable</description>
53652 <description>Enable or disable interrupt for event COMPARE[8]</description>
53658 <description>Disable</description>
53663 <description>Enable</description>
53670 <description>Enable or disable interrupt for event COMPARE[9]</description>
53676 <description>Disable</description>
53681 <description>Enable</description>
53688 <description>Enable or disable interrupt for event COMPARE[10]</description>
53694 <description>Disable</description>
53699 <description>Enable</description>
53706 <description>Enable or disable interrupt for event COMPARE[11]</description>
53712 <description>Disable</description>
53717 <description>Enable</description>
53724 <description>Enable or disable interrupt for event COMPARE[12]</description>
53730 <description>Disable</description>
53735 <description>Enable</description>
53742 <description>Enable or disable interrupt for event COMPARE[13]</description>
53748 <description>Disable</description>
53753 <description>Enable</description>
53760 <description>Enable or disable interrupt for event COMPARE[14]</description>
53766 <description>Disable</description>
53771 <description>Enable</description>
53778 <description>Enable or disable interrupt for event COMPARE[15]</description>
53784 <description>Disable</description>
53789 <description>Enable</description>
53796 <description>Enable or disable interrupt for event RTCOMPARESYNC</description>
53802 <description>Disable</description>
53807 <description>Enable</description>
53814 <description>Enable or disable interrupt for event PWMPERIODEND</description>
53820 <description>Disable</description>
53825 <description>Enable</description>
53834 <description>Enable interrupt</description>
53842 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
53849 <description>Read: Disabled</description>
53854 <description>Read: Enabled</description>
53862 <description>Enable</description>
53869 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
53876 <description>Read: Disabled</description>
53881 <description>Read: Enabled</description>
53889 <description>Enable</description>
53896 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
53903 <description>Read: Disabled</description>
53908 <description>Read: Enabled</description>
53916 <description>Enable</description>
53923 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
53930 <description>Read: Disabled</description>
53935 <description>Read: Enabled</description>
53943 <description>Enable</description>
53950 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
53957 <description>Read: Disabled</description>
53962 <description>Read: Enabled</description>
53970 <description>Enable</description>
53977 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
53984 <description>Read: Disabled</description>
53989 <description>Read: Enabled</description>
53997 <description>Enable</description>
54004 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
54011 <description>Read: Disabled</description>
54016 <description>Read: Enabled</description>
54024 <description>Enable</description>
54031 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
54038 <description>Read: Disabled</description>
54043 <description>Read: Enabled</description>
54051 <description>Enable</description>
54058 <description>Write '1' to enable interrupt for event COMPARE[8]</description>
54065 <description>Read: Disabled</description>
54070 <description>Read: Enabled</description>
54078 <description>Enable</description>
54085 <description>Write '1' to enable interrupt for event COMPARE[9]</description>
54092 <description>Read: Disabled</description>
54097 <description>Read: Enabled</description>
54105 <description>Enable</description>
54112 <description>Write '1' to enable interrupt for event COMPARE[10]</description>
54119 <description>Read: Disabled</description>
54124 <description>Read: Enabled</description>
54132 <description>Enable</description>
54139 <description>Write '1' to enable interrupt for event COMPARE[11]</description>
54146 <description>Read: Disabled</description>
54151 <description>Read: Enabled</description>
54159 <description>Enable</description>
54166 <description>Write '1' to enable interrupt for event COMPARE[12]</description>
54173 <description>Read: Disabled</description>
54178 <description>Read: Enabled</description>
54186 <description>Enable</description>
54193 <description>Write '1' to enable interrupt for event COMPARE[13]</description>
54200 <description>Read: Disabled</description>
54205 <description>Read: Enabled</description>
54213 <description>Enable</description>
54220 <description>Write '1' to enable interrupt for event COMPARE[14]</description>
54227 <description>Read: Disabled</description>
54232 <description>Read: Enabled</description>
54240 <description>Enable</description>
54247 <description>Write '1' to enable interrupt for event COMPARE[15]</description>
54254 <description>Read: Disabled</description>
54259 <description>Read: Enabled</description>
54267 <description>Enable</description>
54274 <description>Write '1' to enable interrupt for event RTCOMPARESYNC</description>
54281 <description>Read: Disabled</description>
54286 <description>Read: Enabled</description>
54294 <description>Enable</description>
54301 <description>Write '1' to enable interrupt for event PWMPERIODEND</description>
54308 <description>Read: Disabled</description>
54313 <description>Read: Enabled</description>
54321 <description>Enable</description>
54330 <description>Disable interrupt</description>
54338 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
54345 <description>Read: Disabled</description>
54350 <description>Read: Enabled</description>
54358 <description>Disable</description>
54365 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
54372 <description>Read: Disabled</description>
54377 <description>Read: Enabled</description>
54385 <description>Disable</description>
54392 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
54399 <description>Read: Disabled</description>
54404 <description>Read: Enabled</description>
54412 <description>Disable</description>
54419 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
54426 <description>Read: Disabled</description>
54431 <description>Read: Enabled</description>
54439 <description>Disable</description>
54446 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
54453 <description>Read: Disabled</description>
54458 <description>Read: Enabled</description>
54466 <description>Disable</description>
54473 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
54480 <description>Read: Disabled</description>
54485 <description>Read: Enabled</description>
54493 <description>Disable</description>
54500 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
54507 <description>Read: Disabled</description>
54512 <description>Read: Enabled</description>
54520 <description>Disable</description>
54527 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
54534 <description>Read: Disabled</description>
54539 <description>Read: Enabled</description>
54547 <description>Disable</description>
54554 <description>Write '1' to disable interrupt for event COMPARE[8]</description>
54561 <description>Read: Disabled</description>
54566 <description>Read: Enabled</description>
54574 <description>Disable</description>
54581 <description>Write '1' to disable interrupt for event COMPARE[9]</description>
54588 <description>Read: Disabled</description>
54593 <description>Read: Enabled</description>
54601 <description>Disable</description>
54608 <description>Write '1' to disable interrupt for event COMPARE[10]</description>
54615 <description>Read: Disabled</description>
54620 <description>Read: Enabled</description>
54628 <description>Disable</description>
54635 <description>Write '1' to disable interrupt for event COMPARE[11]</description>
54642 <description>Read: Disabled</description>
54647 <description>Read: Enabled</description>
54655 <description>Disable</description>
54662 <description>Write '1' to disable interrupt for event COMPARE[12]</description>
54669 <description>Read: Disabled</description>
54674 <description>Read: Enabled</description>
54682 <description>Disable</description>
54689 <description>Write '1' to disable interrupt for event COMPARE[13]</description>
54696 <description>Read: Disabled</description>
54701 <description>Read: Enabled</description>
54709 <description>Disable</description>
54716 <description>Write '1' to disable interrupt for event COMPARE[14]</description>
54723 <description>Read: Disabled</description>
54728 <description>Read: Enabled</description>
54736 <description>Disable</description>
54743 <description>Write '1' to disable interrupt for event COMPARE[15]</description>
54750 <description>Read: Disabled</description>
54755 <description>Read: Enabled</description>
54763 <description>Disable</description>
54770 <description>Write '1' to disable interrupt for event RTCOMPARESYNC</description>
54777 <description>Read: Disabled</description>
54782 <description>Read: Enabled</description>
54790 <description>Disable</description>
54797 <description>Write '1' to disable interrupt for event PWMPERIODEND</description>
54804 <description>Read: Disabled</description>
54809 <description>Read: Enabled</description>
54817 <description>Disable</description>
54826 <description>Pending interrupts</description>
54834 <description>Read pending status of interrupt for event COMPARE[0]</description>
54841 <description>Read: Not pending</description>
54846 <description>Read: Pending</description>
54853 <description>Read pending status of interrupt for event COMPARE[1]</description>
54860 <description>Read: Not pending</description>
54865 <description>Read: Pending</description>
54872 <description>Read pending status of interrupt for event COMPARE[2]</description>
54879 <description>Read: Not pending</description>
54884 <description>Read: Pending</description>
54891 <description>Read pending status of interrupt for event COMPARE[3]</description>
54898 <description>Read: Not pending</description>
54903 <description>Read: Pending</description>
54910 <description>Read pending status of interrupt for event COMPARE[4]</description>
54917 <description>Read: Not pending</description>
54922 <description>Read: Pending</description>
54929 <description>Read pending status of interrupt for event COMPARE[5]</description>
54936 <description>Read: Not pending</description>
54941 <description>Read: Pending</description>
54948 <description>Read pending status of interrupt for event COMPARE[6]</description>
54955 <description>Read: Not pending</description>
54960 <description>Read: Pending</description>
54967 <description>Read pending status of interrupt for event COMPARE[7]</description>
54974 <description>Read: Not pending</description>
54979 <description>Read: Pending</description>
54986 <description>Read pending status of interrupt for event COMPARE[8]</description>
54993 <description>Read: Not pending</description>
54998 <description>Read: Pending</description>
55005 <description>Read pending status of interrupt for event COMPARE[9]</description>
55012 <description>Read: Not pending</description>
55017 <description>Read: Pending</description>
55024 <description>Read pending status of interrupt for event COMPARE[10]</description>
55031 <description>Read: Not pending</description>
55036 <description>Read: Pending</description>
55043 <description>Read pending status of interrupt for event COMPARE[11]</description>
55050 <description>Read: Not pending</description>
55055 <description>Read: Pending</description>
55062 <description>Read pending status of interrupt for event COMPARE[12]</description>
55069 <description>Read: Not pending</description>
55074 <description>Read: Pending</description>
55081 <description>Read pending status of interrupt for event COMPARE[13]</description>
55088 <description>Read: Not pending</description>
55093 <description>Read: Pending</description>
55100 <description>Read pending status of interrupt for event COMPARE[14]</description>
55107 <description>Read: Not pending</description>
55112 <description>Read: Pending</description>
55119 <description>Read pending status of interrupt for event COMPARE[15]</description>
55126 <description>Read: Not pending</description>
55131 <description>Read: Pending</description>
55138 <description>Read pending status of interrupt for event RTCOMPARESYNC</description>
55145 <description>Read: Not pending</description>
55150 <description>Read: Pending</description>
55157 <description>Read pending status of interrupt for event PWMPERIODEND</description>
55164 <description>Read: Not pending</description>
55169 <description>Read: Pending</description>
55178 <description>Enable or disable interrupt</description>
55186 <description>Enable or disable interrupt for event COMPARE[0]</description>
55192 <description>Disable</description>
55197 <description>Enable</description>
55204 <description>Enable or disable interrupt for event COMPARE[1]</description>
55210 <description>Disable</description>
55215 <description>Enable</description>
55222 <description>Enable or disable interrupt for event COMPARE[2]</description>
55228 <description>Disable</description>
55233 <description>Enable</description>
55240 <description>Enable or disable interrupt for event COMPARE[3]</description>
55246 <description>Disable</description>
55251 <description>Enable</description>
55258 <description>Enable or disable interrupt for event COMPARE[4]</description>
55264 <description>Disable</description>
55269 <description>Enable</description>
55276 <description>Enable or disable interrupt for event COMPARE[5]</description>
55282 <description>Disable</description>
55287 <description>Enable</description>
55294 <description>Enable or disable interrupt for event COMPARE[6]</description>
55300 <description>Disable</description>
55305 <description>Enable</description>
55312 <description>Enable or disable interrupt for event COMPARE[7]</description>
55318 <description>Disable</description>
55323 <description>Enable</description>
55330 <description>Enable or disable interrupt for event COMPARE[8]</description>
55336 <description>Disable</description>
55341 <description>Enable</description>
55348 <description>Enable or disable interrupt for event COMPARE[9]</description>
55354 <description>Disable</description>
55359 <description>Enable</description>
55366 <description>Enable or disable interrupt for event COMPARE[10]</description>
55372 <description>Disable</description>
55377 <description>Enable</description>
55384 <description>Enable or disable interrupt for event COMPARE[11]</description>
55390 <description>Disable</description>
55395 <description>Enable</description>
55402 <description>Enable or disable interrupt for event COMPARE[12]</description>
55408 <description>Disable</description>
55413 <description>Enable</description>
55420 <description>Enable or disable interrupt for event COMPARE[13]</description>
55426 <description>Disable</description>
55431 <description>Enable</description>
55438 <description>Enable or disable interrupt for event COMPARE[14]</description>
55444 <description>Disable</description>
55449 <description>Enable</description>
55456 <description>Enable or disable interrupt for event COMPARE[15]</description>
55462 <description>Disable</description>
55467 <description>Enable</description>
55474 <description>Enable or disable interrupt for event RTCOMPARESYNC</description>
55480 <description>Disable</description>
55485 <description>Enable</description>
55492 <description>Enable or disable interrupt for event PWMPERIODEND</description>
55498 <description>Disable</description>
55503 <description>Enable</description>
55512 <description>Enable interrupt</description>
55520 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
55527 <description>Read: Disabled</description>
55532 <description>Read: Enabled</description>
55540 <description>Enable</description>
55547 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
55554 <description>Read: Disabled</description>
55559 <description>Read: Enabled</description>
55567 <description>Enable</description>
55574 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
55581 <description>Read: Disabled</description>
55586 <description>Read: Enabled</description>
55594 <description>Enable</description>
55601 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
55608 <description>Read: Disabled</description>
55613 <description>Read: Enabled</description>
55621 <description>Enable</description>
55628 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
55635 <description>Read: Disabled</description>
55640 <description>Read: Enabled</description>
55648 <description>Enable</description>
55655 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
55662 <description>Read: Disabled</description>
55667 <description>Read: Enabled</description>
55675 <description>Enable</description>
55682 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
55689 <description>Read: Disabled</description>
55694 <description>Read: Enabled</description>
55702 <description>Enable</description>
55709 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
55716 <description>Read: Disabled</description>
55721 <description>Read: Enabled</description>
55729 <description>Enable</description>
55736 <description>Write '1' to enable interrupt for event COMPARE[8]</description>
55743 <description>Read: Disabled</description>
55748 <description>Read: Enabled</description>
55756 <description>Enable</description>
55763 <description>Write '1' to enable interrupt for event COMPARE[9]</description>
55770 <description>Read: Disabled</description>
55775 <description>Read: Enabled</description>
55783 <description>Enable</description>
55790 <description>Write '1' to enable interrupt for event COMPARE[10]</description>
55797 <description>Read: Disabled</description>
55802 <description>Read: Enabled</description>
55810 <description>Enable</description>
55817 <description>Write '1' to enable interrupt for event COMPARE[11]</description>
55824 <description>Read: Disabled</description>
55829 <description>Read: Enabled</description>
55837 <description>Enable</description>
55844 <description>Write '1' to enable interrupt for event COMPARE[12]</description>
55851 <description>Read: Disabled</description>
55856 <description>Read: Enabled</description>
55864 <description>Enable</description>
55871 <description>Write '1' to enable interrupt for event COMPARE[13]</description>
55878 <description>Read: Disabled</description>
55883 <description>Read: Enabled</description>
55891 <description>Enable</description>
55898 <description>Write '1' to enable interrupt for event COMPARE[14]</description>
55905 <description>Read: Disabled</description>
55910 <description>Read: Enabled</description>
55918 <description>Enable</description>
55925 <description>Write '1' to enable interrupt for event COMPARE[15]</description>
55932 <description>Read: Disabled</description>
55937 <description>Read: Enabled</description>
55945 <description>Enable</description>
55952 <description>Write '1' to enable interrupt for event RTCOMPARESYNC</description>
55959 <description>Read: Disabled</description>
55964 <description>Read: Enabled</description>
55972 <description>Enable</description>
55979 <description>Write '1' to enable interrupt for event PWMPERIODEND</description>
55986 <description>Read: Disabled</description>
55991 <description>Read: Enabled</description>
55999 <description>Enable</description>
56008 <description>Disable interrupt</description>
56016 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
56023 <description>Read: Disabled</description>
56028 <description>Read: Enabled</description>
56036 <description>Disable</description>
56043 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
56050 <description>Read: Disabled</description>
56055 <description>Read: Enabled</description>
56063 <description>Disable</description>
56070 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
56077 <description>Read: Disabled</description>
56082 <description>Read: Enabled</description>
56090 <description>Disable</description>
56097 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
56104 <description>Read: Disabled</description>
56109 <description>Read: Enabled</description>
56117 <description>Disable</description>
56124 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
56131 <description>Read: Disabled</description>
56136 <description>Read: Enabled</description>
56144 <description>Disable</description>
56151 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
56158 <description>Read: Disabled</description>
56163 <description>Read: Enabled</description>
56171 <description>Disable</description>
56178 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
56185 <description>Read: Disabled</description>
56190 <description>Read: Enabled</description>
56198 <description>Disable</description>
56205 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
56212 <description>Read: Disabled</description>
56217 <description>Read: Enabled</description>
56225 <description>Disable</description>
56232 <description>Write '1' to disable interrupt for event COMPARE[8]</description>
56239 <description>Read: Disabled</description>
56244 <description>Read: Enabled</description>
56252 <description>Disable</description>
56259 <description>Write '1' to disable interrupt for event COMPARE[9]</description>
56266 <description>Read: Disabled</description>
56271 <description>Read: Enabled</description>
56279 <description>Disable</description>
56286 <description>Write '1' to disable interrupt for event COMPARE[10]</description>
56293 <description>Read: Disabled</description>
56298 <description>Read: Enabled</description>
56306 <description>Disable</description>
56313 <description>Write '1' to disable interrupt for event COMPARE[11]</description>
56320 <description>Read: Disabled</description>
56325 <description>Read: Enabled</description>
56333 <description>Disable</description>
56340 <description>Write '1' to disable interrupt for event COMPARE[12]</description>
56347 <description>Read: Disabled</description>
56352 <description>Read: Enabled</description>
56360 <description>Disable</description>
56367 <description>Write '1' to disable interrupt for event COMPARE[13]</description>
56374 <description>Read: Disabled</description>
56379 <description>Read: Enabled</description>
56387 <description>Disable</description>
56394 <description>Write '1' to disable interrupt for event COMPARE[14]</description>
56401 <description>Read: Disabled</description>
56406 <description>Read: Enabled</description>
56414 <description>Disable</description>
56421 <description>Write '1' to disable interrupt for event COMPARE[15]</description>
56428 <description>Read: Disabled</description>
56433 <description>Read: Enabled</description>
56441 <description>Disable</description>
56448 <description>Write '1' to disable interrupt for event RTCOMPARESYNC</description>
56455 <description>Read: Disabled</description>
56460 <description>Read: Enabled</description>
56468 <description>Disable</description>
56475 <description>Write '1' to disable interrupt for event PWMPERIODEND</description>
56482 <description>Read: Disabled</description>
56487 <description>Read: Enabled</description>
56495 <description>Disable</description>
56504 <description>Pending interrupts</description>
56512 <description>Read pending status of interrupt for event COMPARE[0]</description>
56519 <description>Read: Not pending</description>
56524 <description>Read: Pending</description>
56531 <description>Read pending status of interrupt for event COMPARE[1]</description>
56538 <description>Read: Not pending</description>
56543 <description>Read: Pending</description>
56550 <description>Read pending status of interrupt for event COMPARE[2]</description>
56557 <description>Read: Not pending</description>
56562 <description>Read: Pending</description>
56569 <description>Read pending status of interrupt for event COMPARE[3]</description>
56576 <description>Read: Not pending</description>
56581 <description>Read: Pending</description>
56588 <description>Read pending status of interrupt for event COMPARE[4]</description>
56595 <description>Read: Not pending</description>
56600 <description>Read: Pending</description>
56607 <description>Read pending status of interrupt for event COMPARE[5]</description>
56614 <description>Read: Not pending</description>
56619 <description>Read: Pending</description>
56626 <description>Read pending status of interrupt for event COMPARE[6]</description>
56633 <description>Read: Not pending</description>
56638 <description>Read: Pending</description>
56645 <description>Read pending status of interrupt for event COMPARE[7]</description>
56652 <description>Read: Not pending</description>
56657 <description>Read: Pending</description>
56664 <description>Read pending status of interrupt for event COMPARE[8]</description>
56671 <description>Read: Not pending</description>
56676 <description>Read: Pending</description>
56683 <description>Read pending status of interrupt for event COMPARE[9]</description>
56690 <description>Read: Not pending</description>
56695 <description>Read: Pending</description>
56702 <description>Read pending status of interrupt for event COMPARE[10]</description>
56709 <description>Read: Not pending</description>
56714 <description>Read: Pending</description>
56721 <description>Read pending status of interrupt for event COMPARE[11]</description>
56728 <description>Read: Not pending</description>
56733 <description>Read: Pending</description>
56740 <description>Read pending status of interrupt for event COMPARE[12]</description>
56747 <description>Read: Not pending</description>
56752 <description>Read: Pending</description>
56759 <description>Read pending status of interrupt for event COMPARE[13]</description>
56766 <description>Read: Not pending</description>
56771 <description>Read: Pending</description>
56778 <description>Read pending status of interrupt for event COMPARE[14]</description>
56785 <description>Read: Not pending</description>
56790 <description>Read: Pending</description>
56797 <description>Read pending status of interrupt for event COMPARE[15]</description>
56804 <description>Read: Not pending</description>
56809 <description>Read: Pending</description>
56816 <description>Read pending status of interrupt for event RTCOMPARESYNC</description>
56823 <description>Read: Not pending</description>
56828 <description>Read: Pending</description>
56835 <description>Read pending status of interrupt for event PWMPERIODEND</description>
56842 <description>Read: Not pending</description>
56847 <description>Read: Pending</description>
56856 <description>Enable or disable interrupt</description>
56864 <description>Enable or disable interrupt for event COMPARE[0]</description>
56870 <description>Disable</description>
56875 <description>Enable</description>
56882 <description>Enable or disable interrupt for event COMPARE[1]</description>
56888 <description>Disable</description>
56893 <description>Enable</description>
56900 <description>Enable or disable interrupt for event COMPARE[2]</description>
56906 <description>Disable</description>
56911 <description>Enable</description>
56918 <description>Enable or disable interrupt for event COMPARE[3]</description>
56924 <description>Disable</description>
56929 <description>Enable</description>
56936 <description>Enable or disable interrupt for event COMPARE[4]</description>
56942 <description>Disable</description>
56947 <description>Enable</description>
56954 <description>Enable or disable interrupt for event COMPARE[5]</description>
56960 <description>Disable</description>
56965 <description>Enable</description>
56972 <description>Enable or disable interrupt for event COMPARE[6]</description>
56978 <description>Disable</description>
56983 <description>Enable</description>
56990 <description>Enable or disable interrupt for event COMPARE[7]</description>
56996 <description>Disable</description>
57001 <description>Enable</description>
57008 <description>Enable or disable interrupt for event COMPARE[8]</description>
57014 <description>Disable</description>
57019 <description>Enable</description>
57026 <description>Enable or disable interrupt for event COMPARE[9]</description>
57032 <description>Disable</description>
57037 <description>Enable</description>
57044 <description>Enable or disable interrupt for event COMPARE[10]</description>
57050 <description>Disable</description>
57055 <description>Enable</description>
57062 <description>Enable or disable interrupt for event COMPARE[11]</description>
57068 <description>Disable</description>
57073 <description>Enable</description>
57080 <description>Enable or disable interrupt for event COMPARE[12]</description>
57086 <description>Disable</description>
57091 <description>Enable</description>
57098 <description>Enable or disable interrupt for event COMPARE[13]</description>
57104 <description>Disable</description>
57109 <description>Enable</description>
57116 <description>Enable or disable interrupt for event COMPARE[14]</description>
57122 <description>Disable</description>
57127 <description>Enable</description>
57134 <description>Enable or disable interrupt for event COMPARE[15]</description>
57140 <description>Disable</description>
57145 <description>Enable</description>
57152 <description>Enable or disable interrupt for event RTCOMPARESYNC</description>
57158 <description>Disable</description>
57163 <description>Enable</description>
57170 <description>Enable or disable interrupt for event PWMPERIODEND</description>
57176 <description>Disable</description>
57181 <description>Enable</description>
57190 <description>Enable interrupt</description>
57198 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
57205 <description>Read: Disabled</description>
57210 <description>Read: Enabled</description>
57218 <description>Enable</description>
57225 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
57232 <description>Read: Disabled</description>
57237 <description>Read: Enabled</description>
57245 <description>Enable</description>
57252 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
57259 <description>Read: Disabled</description>
57264 <description>Read: Enabled</description>
57272 <description>Enable</description>
57279 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
57286 <description>Read: Disabled</description>
57291 <description>Read: Enabled</description>
57299 <description>Enable</description>
57306 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
57313 <description>Read: Disabled</description>
57318 <description>Read: Enabled</description>
57326 <description>Enable</description>
57333 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
57340 <description>Read: Disabled</description>
57345 <description>Read: Enabled</description>
57353 <description>Enable</description>
57360 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
57367 <description>Read: Disabled</description>
57372 <description>Read: Enabled</description>
57380 <description>Enable</description>
57387 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
57394 <description>Read: Disabled</description>
57399 <description>Read: Enabled</description>
57407 <description>Enable</description>
57414 <description>Write '1' to enable interrupt for event COMPARE[8]</description>
57421 <description>Read: Disabled</description>
57426 <description>Read: Enabled</description>
57434 <description>Enable</description>
57441 <description>Write '1' to enable interrupt for event COMPARE[9]</description>
57448 <description>Read: Disabled</description>
57453 <description>Read: Enabled</description>
57461 <description>Enable</description>
57468 <description>Write '1' to enable interrupt for event COMPARE[10]</description>
57475 <description>Read: Disabled</description>
57480 <description>Read: Enabled</description>
57488 <description>Enable</description>
57495 <description>Write '1' to enable interrupt for event COMPARE[11]</description>
57502 <description>Read: Disabled</description>
57507 <description>Read: Enabled</description>
57515 <description>Enable</description>
57522 <description>Write '1' to enable interrupt for event COMPARE[12]</description>
57529 <description>Read: Disabled</description>
57534 <description>Read: Enabled</description>
57542 <description>Enable</description>
57549 <description>Write '1' to enable interrupt for event COMPARE[13]</description>
57556 <description>Read: Disabled</description>
57561 <description>Read: Enabled</description>
57569 <description>Enable</description>
57576 <description>Write '1' to enable interrupt for event COMPARE[14]</description>
57583 <description>Read: Disabled</description>
57588 <description>Read: Enabled</description>
57596 <description>Enable</description>
57603 <description>Write '1' to enable interrupt for event COMPARE[15]</description>
57610 <description>Read: Disabled</description>
57615 <description>Read: Enabled</description>
57623 <description>Enable</description>
57630 <description>Write '1' to enable interrupt for event RTCOMPARESYNC</description>
57637 <description>Read: Disabled</description>
57642 <description>Read: Enabled</description>
57650 <description>Enable</description>
57657 <description>Write '1' to enable interrupt for event PWMPERIODEND</description>
57664 <description>Read: Disabled</description>
57669 <description>Read: Enabled</description>
57677 <description>Enable</description>
57686 <description>Disable interrupt</description>
57694 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
57701 <description>Read: Disabled</description>
57706 <description>Read: Enabled</description>
57714 <description>Disable</description>
57721 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
57728 <description>Read: Disabled</description>
57733 <description>Read: Enabled</description>
57741 <description>Disable</description>
57748 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
57755 <description>Read: Disabled</description>
57760 <description>Read: Enabled</description>
57768 <description>Disable</description>
57775 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
57782 <description>Read: Disabled</description>
57787 <description>Read: Enabled</description>
57795 <description>Disable</description>
57802 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
57809 <description>Read: Disabled</description>
57814 <description>Read: Enabled</description>
57822 <description>Disable</description>
57829 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
57836 <description>Read: Disabled</description>
57841 <description>Read: Enabled</description>
57849 <description>Disable</description>
57856 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
57863 <description>Read: Disabled</description>
57868 <description>Read: Enabled</description>
57876 <description>Disable</description>
57883 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
57890 <description>Read: Disabled</description>
57895 <description>Read: Enabled</description>
57903 <description>Disable</description>
57910 <description>Write '1' to disable interrupt for event COMPARE[8]</description>
57917 <description>Read: Disabled</description>
57922 <description>Read: Enabled</description>
57930 <description>Disable</description>
57937 <description>Write '1' to disable interrupt for event COMPARE[9]</description>
57944 <description>Read: Disabled</description>
57949 <description>Read: Enabled</description>
57957 <description>Disable</description>
57964 <description>Write '1' to disable interrupt for event COMPARE[10]</description>
57971 <description>Read: Disabled</description>
57976 <description>Read: Enabled</description>
57984 <description>Disable</description>
57991 <description>Write '1' to disable interrupt for event COMPARE[11]</description>
57998 <description>Read: Disabled</description>
58003 <description>Read: Enabled</description>
58011 <description>Disable</description>
58018 <description>Write '1' to disable interrupt for event COMPARE[12]</description>
58025 <description>Read: Disabled</description>
58030 <description>Read: Enabled</description>
58038 <description>Disable</description>
58045 <description>Write '1' to disable interrupt for event COMPARE[13]</description>
58052 <description>Read: Disabled</description>
58057 <description>Read: Enabled</description>
58065 <description>Disable</description>
58072 <description>Write '1' to disable interrupt for event COMPARE[14]</description>
58079 <description>Read: Disabled</description>
58084 <description>Read: Enabled</description>
58092 <description>Disable</description>
58099 <description>Write '1' to disable interrupt for event COMPARE[15]</description>
58106 <description>Read: Disabled</description>
58111 <description>Read: Enabled</description>
58119 <description>Disable</description>
58126 <description>Write '1' to disable interrupt for event RTCOMPARESYNC</description>
58133 <description>Read: Disabled</description>
58138 <description>Read: Enabled</description>
58146 <description>Disable</description>
58153 <description>Write '1' to disable interrupt for event PWMPERIODEND</description>
58160 <description>Read: Disabled</description>
58165 <description>Read: Enabled</description>
58173 <description>Disable</description>
58182 <description>Pending interrupts</description>
58190 <description>Read pending status of interrupt for event COMPARE[0]</description>
58197 <description>Read: Not pending</description>
58202 <description>Read: Pending</description>
58209 <description>Read pending status of interrupt for event COMPARE[1]</description>
58216 <description>Read: Not pending</description>
58221 <description>Read: Pending</description>
58228 <description>Read pending status of interrupt for event COMPARE[2]</description>
58235 <description>Read: Not pending</description>
58240 <description>Read: Pending</description>
58247 <description>Read pending status of interrupt for event COMPARE[3]</description>
58254 <description>Read: Not pending</description>
58259 <description>Read: Pending</description>
58266 <description>Read pending status of interrupt for event COMPARE[4]</description>
58273 <description>Read: Not pending</description>
58278 <description>Read: Pending</description>
58285 <description>Read pending status of interrupt for event COMPARE[5]</description>
58292 <description>Read: Not pending</description>
58297 <description>Read: Pending</description>
58304 <description>Read pending status of interrupt for event COMPARE[6]</description>
58311 <description>Read: Not pending</description>
58316 <description>Read: Pending</description>
58323 <description>Read pending status of interrupt for event COMPARE[7]</description>
58330 <description>Read: Not pending</description>
58335 <description>Read: Pending</description>
58342 <description>Read pending status of interrupt for event COMPARE[8]</description>
58349 <description>Read: Not pending</description>
58354 <description>Read: Pending</description>
58361 <description>Read pending status of interrupt for event COMPARE[9]</description>
58368 <description>Read: Not pending</description>
58373 <description>Read: Pending</description>
58380 <description>Read pending status of interrupt for event COMPARE[10]</description>
58387 <description>Read: Not pending</description>
58392 <description>Read: Pending</description>
58399 <description>Read pending status of interrupt for event COMPARE[11]</description>
58406 <description>Read: Not pending</description>
58411 <description>Read: Pending</description>
58418 <description>Read pending status of interrupt for event COMPARE[12]</description>
58425 <description>Read: Not pending</description>
58430 <description>Read: Pending</description>
58437 <description>Read pending status of interrupt for event COMPARE[13]</description>
58444 <description>Read: Not pending</description>
58449 <description>Read: Pending</description>
58456 <description>Read pending status of interrupt for event COMPARE[14]</description>
58463 <description>Read: Not pending</description>
58468 <description>Read: Pending</description>
58475 <description>Read pending status of interrupt for event COMPARE[15]</description>
58482 <description>Read: Not pending</description>
58487 <description>Read: Pending</description>
58494 <description>Read pending status of interrupt for event RTCOMPARESYNC</description>
58501 <description>Read: Not pending</description>
58506 <description>Read: Pending</description>
58513 <description>Read pending status of interrupt for event PWMPERIODEND</description>
58520 <description>Read: Not pending</description>
58525 <description>Read: Pending</description>
58534 <description>Enable or disable interrupt</description>
58542 <description>Enable or disable interrupt for event COMPARE[0]</description>
58548 <description>Disable</description>
58553 <description>Enable</description>
58560 <description>Enable or disable interrupt for event COMPARE[1]</description>
58566 <description>Disable</description>
58571 <description>Enable</description>
58578 <description>Enable or disable interrupt for event COMPARE[2]</description>
58584 <description>Disable</description>
58589 <description>Enable</description>
58596 <description>Enable or disable interrupt for event COMPARE[3]</description>
58602 <description>Disable</description>
58607 <description>Enable</description>
58614 <description>Enable or disable interrupt for event COMPARE[4]</description>
58620 <description>Disable</description>
58625 <description>Enable</description>
58632 <description>Enable or disable interrupt for event COMPARE[5]</description>
58638 <description>Disable</description>
58643 <description>Enable</description>
58650 <description>Enable or disable interrupt for event COMPARE[6]</description>
58656 <description>Disable</description>
58661 <description>Enable</description>
58668 <description>Enable or disable interrupt for event COMPARE[7]</description>
58674 <description>Disable</description>
58679 <description>Enable</description>
58686 <description>Enable or disable interrupt for event COMPARE[8]</description>
58692 <description>Disable</description>
58697 <description>Enable</description>
58704 <description>Enable or disable interrupt for event COMPARE[9]</description>
58710 <description>Disable</description>
58715 <description>Enable</description>
58722 <description>Enable or disable interrupt for event COMPARE[10]</description>
58728 <description>Disable</description>
58733 <description>Enable</description>
58740 <description>Enable or disable interrupt for event COMPARE[11]</description>
58746 <description>Disable</description>
58751 <description>Enable</description>
58758 <description>Enable or disable interrupt for event COMPARE[12]</description>
58764 <description>Disable</description>
58769 <description>Enable</description>
58776 <description>Enable or disable interrupt for event COMPARE[13]</description>
58782 <description>Disable</description>
58787 <description>Enable</description>
58794 <description>Enable or disable interrupt for event COMPARE[14]</description>
58800 <description>Disable</description>
58805 <description>Enable</description>
58812 <description>Enable or disable interrupt for event COMPARE[15]</description>
58818 <description>Disable</description>
58823 <description>Enable</description>
58830 <description>Enable or disable interrupt for event RTCOMPARESYNC</description>
58836 <description>Disable</description>
58841 <description>Enable</description>
58848 <description>Enable or disable interrupt for event PWMPERIODEND</description>
58854 <description>Disable</description>
58859 <description>Enable</description>
58868 <description>Enable interrupt</description>
58876 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
58883 <description>Read: Disabled</description>
58888 <description>Read: Enabled</description>
58896 <description>Enable</description>
58903 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
58910 <description>Read: Disabled</description>
58915 <description>Read: Enabled</description>
58923 <description>Enable</description>
58930 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
58937 <description>Read: Disabled</description>
58942 <description>Read: Enabled</description>
58950 <description>Enable</description>
58957 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
58964 <description>Read: Disabled</description>
58969 <description>Read: Enabled</description>
58977 <description>Enable</description>
58984 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
58991 <description>Read: Disabled</description>
58996 <description>Read: Enabled</description>
59004 <description>Enable</description>
59011 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
59018 <description>Read: Disabled</description>
59023 <description>Read: Enabled</description>
59031 <description>Enable</description>
59038 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
59045 <description>Read: Disabled</description>
59050 <description>Read: Enabled</description>
59058 <description>Enable</description>
59065 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
59072 <description>Read: Disabled</description>
59077 <description>Read: Enabled</description>
59085 <description>Enable</description>
59092 <description>Write '1' to enable interrupt for event COMPARE[8]</description>
59099 <description>Read: Disabled</description>
59104 <description>Read: Enabled</description>
59112 <description>Enable</description>
59119 <description>Write '1' to enable interrupt for event COMPARE[9]</description>
59126 <description>Read: Disabled</description>
59131 <description>Read: Enabled</description>
59139 <description>Enable</description>
59146 <description>Write '1' to enable interrupt for event COMPARE[10]</description>
59153 <description>Read: Disabled</description>
59158 <description>Read: Enabled</description>
59166 <description>Enable</description>
59173 <description>Write '1' to enable interrupt for event COMPARE[11]</description>
59180 <description>Read: Disabled</description>
59185 <description>Read: Enabled</description>
59193 <description>Enable</description>
59200 <description>Write '1' to enable interrupt for event COMPARE[12]</description>
59207 <description>Read: Disabled</description>
59212 <description>Read: Enabled</description>
59220 <description>Enable</description>
59227 <description>Write '1' to enable interrupt for event COMPARE[13]</description>
59234 <description>Read: Disabled</description>
59239 <description>Read: Enabled</description>
59247 <description>Enable</description>
59254 <description>Write '1' to enable interrupt for event COMPARE[14]</description>
59261 <description>Read: Disabled</description>
59266 <description>Read: Enabled</description>
59274 <description>Enable</description>
59281 <description>Write '1' to enable interrupt for event COMPARE[15]</description>
59288 <description>Read: Disabled</description>
59293 <description>Read: Enabled</description>
59301 <description>Enable</description>
59308 <description>Write '1' to enable interrupt for event RTCOMPARESYNC</description>
59315 <description>Read: Disabled</description>
59320 <description>Read: Enabled</description>
59328 <description>Enable</description>
59335 <description>Write '1' to enable interrupt for event PWMPERIODEND</description>
59342 <description>Read: Disabled</description>
59347 <description>Read: Enabled</description>
59355 <description>Enable</description>
59364 <description>Disable interrupt</description>
59372 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
59379 <description>Read: Disabled</description>
59384 <description>Read: Enabled</description>
59392 <description>Disable</description>
59399 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
59406 <description>Read: Disabled</description>
59411 <description>Read: Enabled</description>
59419 <description>Disable</description>
59426 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
59433 <description>Read: Disabled</description>
59438 <description>Read: Enabled</description>
59446 <description>Disable</description>
59453 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
59460 <description>Read: Disabled</description>
59465 <description>Read: Enabled</description>
59473 <description>Disable</description>
59480 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
59487 <description>Read: Disabled</description>
59492 <description>Read: Enabled</description>
59500 <description>Disable</description>
59507 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
59514 <description>Read: Disabled</description>
59519 <description>Read: Enabled</description>
59527 <description>Disable</description>
59534 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
59541 <description>Read: Disabled</description>
59546 <description>Read: Enabled</description>
59554 <description>Disable</description>
59561 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
59568 <description>Read: Disabled</description>
59573 <description>Read: Enabled</description>
59581 <description>Disable</description>
59588 <description>Write '1' to disable interrupt for event COMPARE[8]</description>
59595 <description>Read: Disabled</description>
59600 <description>Read: Enabled</description>
59608 <description>Disable</description>
59615 <description>Write '1' to disable interrupt for event COMPARE[9]</description>
59622 <description>Read: Disabled</description>
59627 <description>Read: Enabled</description>
59635 <description>Disable</description>
59642 <description>Write '1' to disable interrupt for event COMPARE[10]</description>
59649 <description>Read: Disabled</description>
59654 <description>Read: Enabled</description>
59662 <description>Disable</description>
59669 <description>Write '1' to disable interrupt for event COMPARE[11]</description>
59676 <description>Read: Disabled</description>
59681 <description>Read: Enabled</description>
59689 <description>Disable</description>
59696 <description>Write '1' to disable interrupt for event COMPARE[12]</description>
59703 <description>Read: Disabled</description>
59708 <description>Read: Enabled</description>
59716 <description>Disable</description>
59723 <description>Write '1' to disable interrupt for event COMPARE[13]</description>
59730 <description>Read: Disabled</description>
59735 <description>Read: Enabled</description>
59743 <description>Disable</description>
59750 <description>Write '1' to disable interrupt for event COMPARE[14]</description>
59757 <description>Read: Disabled</description>
59762 <description>Read: Enabled</description>
59770 <description>Disable</description>
59777 <description>Write '1' to disable interrupt for event COMPARE[15]</description>
59784 <description>Read: Disabled</description>
59789 <description>Read: Enabled</description>
59797 <description>Disable</description>
59804 <description>Write '1' to disable interrupt for event RTCOMPARESYNC</description>
59811 <description>Read: Disabled</description>
59816 <description>Read: Enabled</description>
59824 <description>Disable</description>
59831 <description>Write '1' to disable interrupt for event PWMPERIODEND</description>
59838 <description>Read: Disabled</description>
59843 <description>Read: Enabled</description>
59851 <description>Disable</description>
59860 <description>Pending interrupts</description>
59868 <description>Read pending status of interrupt for event COMPARE[0]</description>
59875 <description>Read: Not pending</description>
59880 <description>Read: Pending</description>
59887 <description>Read pending status of interrupt for event COMPARE[1]</description>
59894 <description>Read: Not pending</description>
59899 <description>Read: Pending</description>
59906 <description>Read pending status of interrupt for event COMPARE[2]</description>
59913 <description>Read: Not pending</description>
59918 <description>Read: Pending</description>
59925 <description>Read pending status of interrupt for event COMPARE[3]</description>
59932 <description>Read: Not pending</description>
59937 <description>Read: Pending</description>
59944 <description>Read pending status of interrupt for event COMPARE[4]</description>
59951 <description>Read: Not pending</description>
59956 <description>Read: Pending</description>
59963 <description>Read pending status of interrupt for event COMPARE[5]</description>
59970 <description>Read: Not pending</description>
59975 <description>Read: Pending</description>
59982 <description>Read pending status of interrupt for event COMPARE[6]</description>
59989 <description>Read: Not pending</description>
59994 <description>Read: Pending</description>
60001 <description>Read pending status of interrupt for event COMPARE[7]</description>
60008 <description>Read: Not pending</description>
60013 <description>Read: Pending</description>
60020 <description>Read pending status of interrupt for event COMPARE[8]</description>
60027 <description>Read: Not pending</description>
60032 <description>Read: Pending</description>
60039 <description>Read pending status of interrupt for event COMPARE[9]</description>
60046 <description>Read: Not pending</description>
60051 <description>Read: Pending</description>
60058 <description>Read pending status of interrupt for event COMPARE[10]</description>
60065 <description>Read: Not pending</description>
60070 <description>Read: Pending</description>
60077 <description>Read pending status of interrupt for event COMPARE[11]</description>
60084 <description>Read: Not pending</description>
60089 <description>Read: Pending</description>
60096 <description>Read pending status of interrupt for event COMPARE[12]</description>
60103 <description>Read: Not pending</description>
60108 <description>Read: Pending</description>
60115 <description>Read pending status of interrupt for event COMPARE[13]</description>
60122 <description>Read: Not pending</description>
60127 <description>Read: Pending</description>
60134 <description>Read pending status of interrupt for event COMPARE[14]</description>
60141 <description>Read: Not pending</description>
60146 <description>Read: Pending</description>
60153 <description>Read pending status of interrupt for event COMPARE[15]</description>
60160 <description>Read: Not pending</description>
60165 <description>Read: Pending</description>
60172 <description>Read pending status of interrupt for event RTCOMPARESYNC</description>
60179 <description>Read: Not pending</description>
60184 <description>Read: Pending</description>
60191 <description>Read pending status of interrupt for event PWMPERIODEND</description>
60198 <description>Read: Not pending</description>
60203 <description>Read: Pending</description>
60212 <description>Enable or disable interrupt</description>
60220 <description>Enable or disable interrupt for event COMPARE[0]</description>
60226 <description>Disable</description>
60231 <description>Enable</description>
60238 <description>Enable or disable interrupt for event COMPARE[1]</description>
60244 <description>Disable</description>
60249 <description>Enable</description>
60256 <description>Enable or disable interrupt for event COMPARE[2]</description>
60262 <description>Disable</description>
60267 <description>Enable</description>
60274 <description>Enable or disable interrupt for event COMPARE[3]</description>
60280 <description>Disable</description>
60285 <description>Enable</description>
60292 <description>Enable or disable interrupt for event COMPARE[4]</description>
60298 <description>Disable</description>
60303 <description>Enable</description>
60310 <description>Enable or disable interrupt for event COMPARE[5]</description>
60316 <description>Disable</description>
60321 <description>Enable</description>
60328 <description>Enable or disable interrupt for event COMPARE[6]</description>
60334 <description>Disable</description>
60339 <description>Enable</description>
60346 <description>Enable or disable interrupt for event COMPARE[7]</description>
60352 <description>Disable</description>
60357 <description>Enable</description>
60364 <description>Enable or disable interrupt for event COMPARE[8]</description>
60370 <description>Disable</description>
60375 <description>Enable</description>
60382 <description>Enable or disable interrupt for event COMPARE[9]</description>
60388 <description>Disable</description>
60393 <description>Enable</description>
60400 <description>Enable or disable interrupt for event COMPARE[10]</description>
60406 <description>Disable</description>
60411 <description>Enable</description>
60418 <description>Enable or disable interrupt for event COMPARE[11]</description>
60424 <description>Disable</description>
60429 <description>Enable</description>
60436 <description>Enable or disable interrupt for event COMPARE[12]</description>
60442 <description>Disable</description>
60447 <description>Enable</description>
60454 <description>Enable or disable interrupt for event COMPARE[13]</description>
60460 <description>Disable</description>
60465 <description>Enable</description>
60472 <description>Enable or disable interrupt for event COMPARE[14]</description>
60478 <description>Disable</description>
60483 <description>Enable</description>
60490 <description>Enable or disable interrupt for event COMPARE[15]</description>
60496 <description>Disable</description>
60501 <description>Enable</description>
60508 <description>Enable or disable interrupt for event RTCOMPARESYNC</description>
60514 <description>Disable</description>
60519 <description>Enable</description>
60526 <description>Enable or disable interrupt for event PWMPERIODEND</description>
60532 <description>Disable</description>
60537 <description>Enable</description>
60546 <description>Enable interrupt</description>
60554 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
60561 <description>Read: Disabled</description>
60566 <description>Read: Enabled</description>
60574 <description>Enable</description>
60581 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
60588 <description>Read: Disabled</description>
60593 <description>Read: Enabled</description>
60601 <description>Enable</description>
60608 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
60615 <description>Read: Disabled</description>
60620 <description>Read: Enabled</description>
60628 <description>Enable</description>
60635 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
60642 <description>Read: Disabled</description>
60647 <description>Read: Enabled</description>
60655 <description>Enable</description>
60662 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
60669 <description>Read: Disabled</description>
60674 <description>Read: Enabled</description>
60682 <description>Enable</description>
60689 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
60696 <description>Read: Disabled</description>
60701 <description>Read: Enabled</description>
60709 <description>Enable</description>
60716 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
60723 <description>Read: Disabled</description>
60728 <description>Read: Enabled</description>
60736 <description>Enable</description>
60743 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
60750 <description>Read: Disabled</description>
60755 <description>Read: Enabled</description>
60763 <description>Enable</description>
60770 <description>Write '1' to enable interrupt for event COMPARE[8]</description>
60777 <description>Read: Disabled</description>
60782 <description>Read: Enabled</description>
60790 <description>Enable</description>
60797 <description>Write '1' to enable interrupt for event COMPARE[9]</description>
60804 <description>Read: Disabled</description>
60809 <description>Read: Enabled</description>
60817 <description>Enable</description>
60824 <description>Write '1' to enable interrupt for event COMPARE[10]</description>
60831 <description>Read: Disabled</description>
60836 <description>Read: Enabled</description>
60844 <description>Enable</description>
60851 <description>Write '1' to enable interrupt for event COMPARE[11]</description>
60858 <description>Read: Disabled</description>
60863 <description>Read: Enabled</description>
60871 <description>Enable</description>
60878 <description>Write '1' to enable interrupt for event COMPARE[12]</description>
60885 <description>Read: Disabled</description>
60890 <description>Read: Enabled</description>
60898 <description>Enable</description>
60905 <description>Write '1' to enable interrupt for event COMPARE[13]</description>
60912 <description>Read: Disabled</description>
60917 <description>Read: Enabled</description>
60925 <description>Enable</description>
60932 <description>Write '1' to enable interrupt for event COMPARE[14]</description>
60939 <description>Read: Disabled</description>
60944 <description>Read: Enabled</description>
60952 <description>Enable</description>
60959 <description>Write '1' to enable interrupt for event COMPARE[15]</description>
60966 <description>Read: Disabled</description>
60971 <description>Read: Enabled</description>
60979 <description>Enable</description>
60986 <description>Write '1' to enable interrupt for event RTCOMPARESYNC</description>
60993 <description>Read: Disabled</description>
60998 <description>Read: Enabled</description>
61006 <description>Enable</description>
61013 <description>Write '1' to enable interrupt for event PWMPERIODEND</description>
61020 <description>Read: Disabled</description>
61025 <description>Read: Enabled</description>
61033 <description>Enable</description>
61042 <description>Disable interrupt</description>
61050 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
61057 <description>Read: Disabled</description>
61062 <description>Read: Enabled</description>
61070 <description>Disable</description>
61077 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
61084 <description>Read: Disabled</description>
61089 <description>Read: Enabled</description>
61097 <description>Disable</description>
61104 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
61111 <description>Read: Disabled</description>
61116 <description>Read: Enabled</description>
61124 <description>Disable</description>
61131 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
61138 <description>Read: Disabled</description>
61143 <description>Read: Enabled</description>
61151 <description>Disable</description>
61158 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
61165 <description>Read: Disabled</description>
61170 <description>Read: Enabled</description>
61178 <description>Disable</description>
61185 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
61192 <description>Read: Disabled</description>
61197 <description>Read: Enabled</description>
61205 <description>Disable</description>
61212 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
61219 <description>Read: Disabled</description>
61224 <description>Read: Enabled</description>
61232 <description>Disable</description>
61239 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
61246 <description>Read: Disabled</description>
61251 <description>Read: Enabled</description>
61259 <description>Disable</description>
61266 <description>Write '1' to disable interrupt for event COMPARE[8]</description>
61273 <description>Read: Disabled</description>
61278 <description>Read: Enabled</description>
61286 <description>Disable</description>
61293 <description>Write '1' to disable interrupt for event COMPARE[9]</description>
61300 <description>Read: Disabled</description>
61305 <description>Read: Enabled</description>
61313 <description>Disable</description>
61320 <description>Write '1' to disable interrupt for event COMPARE[10]</description>
61327 <description>Read: Disabled</description>
61332 <description>Read: Enabled</description>
61340 <description>Disable</description>
61347 <description>Write '1' to disable interrupt for event COMPARE[11]</description>
61354 <description>Read: Disabled</description>
61359 <description>Read: Enabled</description>
61367 <description>Disable</description>
61374 <description>Write '1' to disable interrupt for event COMPARE[12]</description>
61381 <description>Read: Disabled</description>
61386 <description>Read: Enabled</description>
61394 <description>Disable</description>
61401 <description>Write '1' to disable interrupt for event COMPARE[13]</description>
61408 <description>Read: Disabled</description>
61413 <description>Read: Enabled</description>
61421 <description>Disable</description>
61428 <description>Write '1' to disable interrupt for event COMPARE[14]</description>
61435 <description>Read: Disabled</description>
61440 <description>Read: Enabled</description>
61448 <description>Disable</description>
61455 <description>Write '1' to disable interrupt for event COMPARE[15]</description>
61462 <description>Read: Disabled</description>
61467 <description>Read: Enabled</description>
61475 <description>Disable</description>
61482 <description>Write '1' to disable interrupt for event RTCOMPARESYNC</description>
61489 <description>Read: Disabled</description>
61494 <description>Read: Enabled</description>
61502 <description>Disable</description>
61509 <description>Write '1' to disable interrupt for event PWMPERIODEND</description>
61516 <description>Read: Disabled</description>
61521 <description>Read: Enabled</description>
61529 <description>Disable</description>
61538 <description>Pending interrupts</description>
61546 <description>Read pending status of interrupt for event COMPARE[0]</description>
61553 <description>Read: Not pending</description>
61558 <description>Read: Pending</description>
61565 <description>Read pending status of interrupt for event COMPARE[1]</description>
61572 <description>Read: Not pending</description>
61577 <description>Read: Pending</description>
61584 <description>Read pending status of interrupt for event COMPARE[2]</description>
61591 <description>Read: Not pending</description>
61596 <description>Read: Pending</description>
61603 <description>Read pending status of interrupt for event COMPARE[3]</description>
61610 <description>Read: Not pending</description>
61615 <description>Read: Pending</description>
61622 <description>Read pending status of interrupt for event COMPARE[4]</description>
61629 <description>Read: Not pending</description>
61634 <description>Read: Pending</description>
61641 <description>Read pending status of interrupt for event COMPARE[5]</description>
61648 <description>Read: Not pending</description>
61653 <description>Read: Pending</description>
61660 <description>Read pending status of interrupt for event COMPARE[6]</description>
61667 <description>Read: Not pending</description>
61672 <description>Read: Pending</description>
61679 <description>Read pending status of interrupt for event COMPARE[7]</description>
61686 <description>Read: Not pending</description>
61691 <description>Read: Pending</description>
61698 <description>Read pending status of interrupt for event COMPARE[8]</description>
61705 <description>Read: Not pending</description>
61710 <description>Read: Pending</description>
61717 <description>Read pending status of interrupt for event COMPARE[9]</description>
61724 <description>Read: Not pending</description>
61729 <description>Read: Pending</description>
61736 <description>Read pending status of interrupt for event COMPARE[10]</description>
61743 <description>Read: Not pending</description>
61748 <description>Read: Pending</description>
61755 <description>Read pending status of interrupt for event COMPARE[11]</description>
61762 <description>Read: Not pending</description>
61767 <description>Read: Pending</description>
61774 <description>Read pending status of interrupt for event COMPARE[12]</description>
61781 <description>Read: Not pending</description>
61786 <description>Read: Pending</description>
61793 <description>Read pending status of interrupt for event COMPARE[13]</description>
61800 <description>Read: Not pending</description>
61805 <description>Read: Pending</description>
61812 <description>Read pending status of interrupt for event COMPARE[14]</description>
61819 <description>Read: Not pending</description>
61824 <description>Read: Pending</description>
61831 <description>Read pending status of interrupt for event COMPARE[15]</description>
61838 <description>Read: Not pending</description>
61843 <description>Read: Pending</description>
61850 <description>Read pending status of interrupt for event RTCOMPARESYNC</description>
61857 <description>Read: Not pending</description>
61862 <description>Read: Pending</description>
61869 <description>Read pending status of interrupt for event PWMPERIODEND</description>
61876 <description>Read: Not pending</description>
61881 <description>Read: Pending</description>
61890 <description>Enable or disable interrupt</description>
61898 <description>Enable or disable interrupt for event COMPARE[0]</description>
61904 <description>Disable</description>
61909 <description>Enable</description>
61916 <description>Enable or disable interrupt for event COMPARE[1]</description>
61922 <description>Disable</description>
61927 <description>Enable</description>
61934 <description>Enable or disable interrupt for event COMPARE[2]</description>
61940 <description>Disable</description>
61945 <description>Enable</description>
61952 <description>Enable or disable interrupt for event COMPARE[3]</description>
61958 <description>Disable</description>
61963 <description>Enable</description>
61970 <description>Enable or disable interrupt for event COMPARE[4]</description>
61976 <description>Disable</description>
61981 <description>Enable</description>
61988 <description>Enable or disable interrupt for event COMPARE[5]</description>
61994 <description>Disable</description>
61999 <description>Enable</description>
62006 <description>Enable or disable interrupt for event COMPARE[6]</description>
62012 <description>Disable</description>
62017 <description>Enable</description>
62024 <description>Enable or disable interrupt for event COMPARE[7]</description>
62030 <description>Disable</description>
62035 <description>Enable</description>
62042 <description>Enable or disable interrupt for event COMPARE[8]</description>
62048 <description>Disable</description>
62053 <description>Enable</description>
62060 <description>Enable or disable interrupt for event COMPARE[9]</description>
62066 <description>Disable</description>
62071 <description>Enable</description>
62078 <description>Enable or disable interrupt for event COMPARE[10]</description>
62084 <description>Disable</description>
62089 <description>Enable</description>
62096 <description>Enable or disable interrupt for event COMPARE[11]</description>
62102 <description>Disable</description>
62107 <description>Enable</description>
62114 <description>Enable or disable interrupt for event COMPARE[12]</description>
62120 <description>Disable</description>
62125 <description>Enable</description>
62132 <description>Enable or disable interrupt for event COMPARE[13]</description>
62138 <description>Disable</description>
62143 <description>Enable</description>
62150 <description>Enable or disable interrupt for event COMPARE[14]</description>
62156 <description>Disable</description>
62161 <description>Enable</description>
62168 <description>Enable or disable interrupt for event COMPARE[15]</description>
62174 <description>Disable</description>
62179 <description>Enable</description>
62186 <description>Enable or disable interrupt for event RTCOMPARESYNC</description>
62192 <description>Disable</description>
62197 <description>Enable</description>
62204 <description>Enable or disable interrupt for event PWMPERIODEND</description>
62210 <description>Disable</description>
62215 <description>Enable</description>
62224 <description>Enable interrupt</description>
62232 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
62239 <description>Read: Disabled</description>
62244 <description>Read: Enabled</description>
62252 <description>Enable</description>
62259 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
62266 <description>Read: Disabled</description>
62271 <description>Read: Enabled</description>
62279 <description>Enable</description>
62286 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
62293 <description>Read: Disabled</description>
62298 <description>Read: Enabled</description>
62306 <description>Enable</description>
62313 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
62320 <description>Read: Disabled</description>
62325 <description>Read: Enabled</description>
62333 <description>Enable</description>
62340 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
62347 <description>Read: Disabled</description>
62352 <description>Read: Enabled</description>
62360 <description>Enable</description>
62367 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
62374 <description>Read: Disabled</description>
62379 <description>Read: Enabled</description>
62387 <description>Enable</description>
62394 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
62401 <description>Read: Disabled</description>
62406 <description>Read: Enabled</description>
62414 <description>Enable</description>
62421 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
62428 <description>Read: Disabled</description>
62433 <description>Read: Enabled</description>
62441 <description>Enable</description>
62448 <description>Write '1' to enable interrupt for event COMPARE[8]</description>
62455 <description>Read: Disabled</description>
62460 <description>Read: Enabled</description>
62468 <description>Enable</description>
62475 <description>Write '1' to enable interrupt for event COMPARE[9]</description>
62482 <description>Read: Disabled</description>
62487 <description>Read: Enabled</description>
62495 <description>Enable</description>
62502 <description>Write '1' to enable interrupt for event COMPARE[10]</description>
62509 <description>Read: Disabled</description>
62514 <description>Read: Enabled</description>
62522 <description>Enable</description>
62529 <description>Write '1' to enable interrupt for event COMPARE[11]</description>
62536 <description>Read: Disabled</description>
62541 <description>Read: Enabled</description>
62549 <description>Enable</description>
62556 <description>Write '1' to enable interrupt for event COMPARE[12]</description>
62563 <description>Read: Disabled</description>
62568 <description>Read: Enabled</description>
62576 <description>Enable</description>
62583 <description>Write '1' to enable interrupt for event COMPARE[13]</description>
62590 <description>Read: Disabled</description>
62595 <description>Read: Enabled</description>
62603 <description>Enable</description>
62610 <description>Write '1' to enable interrupt for event COMPARE[14]</description>
62617 <description>Read: Disabled</description>
62622 <description>Read: Enabled</description>
62630 <description>Enable</description>
62637 <description>Write '1' to enable interrupt for event COMPARE[15]</description>
62644 <description>Read: Disabled</description>
62649 <description>Read: Enabled</description>
62657 <description>Enable</description>
62664 <description>Write '1' to enable interrupt for event RTCOMPARESYNC</description>
62671 <description>Read: Disabled</description>
62676 <description>Read: Enabled</description>
62684 <description>Enable</description>
62691 <description>Write '1' to enable interrupt for event PWMPERIODEND</description>
62698 <description>Read: Disabled</description>
62703 <description>Read: Enabled</description>
62711 <description>Enable</description>
62720 <description>Disable interrupt</description>
62728 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
62735 <description>Read: Disabled</description>
62740 <description>Read: Enabled</description>
62748 <description>Disable</description>
62755 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
62762 <description>Read: Disabled</description>
62767 <description>Read: Enabled</description>
62775 <description>Disable</description>
62782 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
62789 <description>Read: Disabled</description>
62794 <description>Read: Enabled</description>
62802 <description>Disable</description>
62809 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
62816 <description>Read: Disabled</description>
62821 <description>Read: Enabled</description>
62829 <description>Disable</description>
62836 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
62843 <description>Read: Disabled</description>
62848 <description>Read: Enabled</description>
62856 <description>Disable</description>
62863 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
62870 <description>Read: Disabled</description>
62875 <description>Read: Enabled</description>
62883 <description>Disable</description>
62890 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
62897 <description>Read: Disabled</description>
62902 <description>Read: Enabled</description>
62910 <description>Disable</description>
62917 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
62924 <description>Read: Disabled</description>
62929 <description>Read: Enabled</description>
62937 <description>Disable</description>
62944 <description>Write '1' to disable interrupt for event COMPARE[8]</description>
62951 <description>Read: Disabled</description>
62956 <description>Read: Enabled</description>
62964 <description>Disable</description>
62971 <description>Write '1' to disable interrupt for event COMPARE[9]</description>
62978 <description>Read: Disabled</description>
62983 <description>Read: Enabled</description>
62991 <description>Disable</description>
62998 <description>Write '1' to disable interrupt for event COMPARE[10]</description>
63005 <description>Read: Disabled</description>
63010 <description>Read: Enabled</description>
63018 <description>Disable</description>
63025 <description>Write '1' to disable interrupt for event COMPARE[11]</description>
63032 <description>Read: Disabled</description>
63037 <description>Read: Enabled</description>
63045 <description>Disable</description>
63052 <description>Write '1' to disable interrupt for event COMPARE[12]</description>
63059 <description>Read: Disabled</description>
63064 <description>Read: Enabled</description>
63072 <description>Disable</description>
63079 <description>Write '1' to disable interrupt for event COMPARE[13]</description>
63086 <description>Read: Disabled</description>
63091 <description>Read: Enabled</description>
63099 <description>Disable</description>
63106 <description>Write '1' to disable interrupt for event COMPARE[14]</description>
63113 <description>Read: Disabled</description>
63118 <description>Read: Enabled</description>
63126 <description>Disable</description>
63133 <description>Write '1' to disable interrupt for event COMPARE[15]</description>
63140 <description>Read: Disabled</description>
63145 <description>Read: Enabled</description>
63153 <description>Disable</description>
63160 <description>Write '1' to disable interrupt for event RTCOMPARESYNC</description>
63167 <description>Read: Disabled</description>
63172 <description>Read: Enabled</description>
63180 <description>Disable</description>
63187 <description>Write '1' to disable interrupt for event PWMPERIODEND</description>
63194 <description>Read: Disabled</description>
63199 <description>Read: Enabled</description>
63207 <description>Disable</description>
63216 <description>Pending interrupts</description>
63224 <description>Read pending status of interrupt for event COMPARE[0]</description>
63231 <description>Read: Not pending</description>
63236 <description>Read: Pending</description>
63243 <description>Read pending status of interrupt for event COMPARE[1]</description>
63250 <description>Read: Not pending</description>
63255 <description>Read: Pending</description>
63262 <description>Read pending status of interrupt for event COMPARE[2]</description>
63269 <description>Read: Not pending</description>
63274 <description>Read: Pending</description>
63281 <description>Read pending status of interrupt for event COMPARE[3]</description>
63288 <description>Read: Not pending</description>
63293 <description>Read: Pending</description>
63300 <description>Read pending status of interrupt for event COMPARE[4]</description>
63307 <description>Read: Not pending</description>
63312 <description>Read: Pending</description>
63319 <description>Read pending status of interrupt for event COMPARE[5]</description>
63326 <description>Read: Not pending</description>
63331 <description>Read: Pending</description>
63338 <description>Read pending status of interrupt for event COMPARE[6]</description>
63345 <description>Read: Not pending</description>
63350 <description>Read: Pending</description>
63357 <description>Read pending status of interrupt for event COMPARE[7]</description>
63364 <description>Read: Not pending</description>
63369 <description>Read: Pending</description>
63376 <description>Read pending status of interrupt for event COMPARE[8]</description>
63383 <description>Read: Not pending</description>
63388 <description>Read: Pending</description>
63395 <description>Read pending status of interrupt for event COMPARE[9]</description>
63402 <description>Read: Not pending</description>
63407 <description>Read: Pending</description>
63414 <description>Read pending status of interrupt for event COMPARE[10]</description>
63421 <description>Read: Not pending</description>
63426 <description>Read: Pending</description>
63433 <description>Read pending status of interrupt for event COMPARE[11]</description>
63440 <description>Read: Not pending</description>
63445 <description>Read: Pending</description>
63452 <description>Read pending status of interrupt for event COMPARE[12]</description>
63459 <description>Read: Not pending</description>
63464 <description>Read: Pending</description>
63471 <description>Read pending status of interrupt for event COMPARE[13]</description>
63478 <description>Read: Not pending</description>
63483 <description>Read: Pending</description>
63490 <description>Read pending status of interrupt for event COMPARE[14]</description>
63497 <description>Read: Not pending</description>
63502 <description>Read: Pending</description>
63509 <description>Read pending status of interrupt for event COMPARE[15]</description>
63516 <description>Read: Not pending</description>
63521 <description>Read: Pending</description>
63528 <description>Read pending status of interrupt for event RTCOMPARESYNC</description>
63535 <description>Read: Not pending</description>
63540 <description>Read: Pending</description>
63547 <description>Read pending status of interrupt for event PWMPERIODEND</description>
63554 <description>Read: Not pending</description>
63559 <description>Read: Pending</description>
63568 <description>Enable or disable interrupt</description>
63576 <description>Enable or disable interrupt for event COMPARE[0]</description>
63582 <description>Disable</description>
63587 <description>Enable</description>
63594 <description>Enable or disable interrupt for event COMPARE[1]</description>
63600 <description>Disable</description>
63605 <description>Enable</description>
63612 <description>Enable or disable interrupt for event COMPARE[2]</description>
63618 <description>Disable</description>
63623 <description>Enable</description>
63630 <description>Enable or disable interrupt for event COMPARE[3]</description>
63636 <description>Disable</description>
63641 <description>Enable</description>
63648 <description>Enable or disable interrupt for event COMPARE[4]</description>
63654 <description>Disable</description>
63659 <description>Enable</description>
63666 <description>Enable or disable interrupt for event COMPARE[5]</description>
63672 <description>Disable</description>
63677 <description>Enable</description>
63684 <description>Enable or disable interrupt for event COMPARE[6]</description>
63690 <description>Disable</description>
63695 <description>Enable</description>
63702 <description>Enable or disable interrupt for event COMPARE[7]</description>
63708 <description>Disable</description>
63713 <description>Enable</description>
63720 <description>Enable or disable interrupt for event COMPARE[8]</description>
63726 <description>Disable</description>
63731 <description>Enable</description>
63738 <description>Enable or disable interrupt for event COMPARE[9]</description>
63744 <description>Disable</description>
63749 <description>Enable</description>
63756 <description>Enable or disable interrupt for event COMPARE[10]</description>
63762 <description>Disable</description>
63767 <description>Enable</description>
63774 <description>Enable or disable interrupt for event COMPARE[11]</description>
63780 <description>Disable</description>
63785 <description>Enable</description>
63792 <description>Enable or disable interrupt for event COMPARE[12]</description>
63798 <description>Disable</description>
63803 <description>Enable</description>
63810 <description>Enable or disable interrupt for event COMPARE[13]</description>
63816 <description>Disable</description>
63821 <description>Enable</description>
63828 <description>Enable or disable interrupt for event COMPARE[14]</description>
63834 <description>Disable</description>
63839 <description>Enable</description>
63846 <description>Enable or disable interrupt for event COMPARE[15]</description>
63852 <description>Disable</description>
63857 <description>Enable</description>
63864 <description>Enable or disable interrupt for event RTCOMPARESYNC</description>
63870 <description>Disable</description>
63875 <description>Enable</description>
63882 <description>Enable or disable interrupt for event PWMPERIODEND</description>
63888 <description>Disable</description>
63893 <description>Enable</description>
63902 <description>Enable interrupt</description>
63910 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
63917 <description>Read: Disabled</description>
63922 <description>Read: Enabled</description>
63930 <description>Enable</description>
63937 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
63944 <description>Read: Disabled</description>
63949 <description>Read: Enabled</description>
63957 <description>Enable</description>
63964 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
63971 <description>Read: Disabled</description>
63976 <description>Read: Enabled</description>
63984 <description>Enable</description>
63991 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
63998 <description>Read: Disabled</description>
64003 <description>Read: Enabled</description>
64011 <description>Enable</description>
64018 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
64025 <description>Read: Disabled</description>
64030 <description>Read: Enabled</description>
64038 <description>Enable</description>
64045 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
64052 <description>Read: Disabled</description>
64057 <description>Read: Enabled</description>
64065 <description>Enable</description>
64072 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
64079 <description>Read: Disabled</description>
64084 <description>Read: Enabled</description>
64092 <description>Enable</description>
64099 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
64106 <description>Read: Disabled</description>
64111 <description>Read: Enabled</description>
64119 <description>Enable</description>
64126 <description>Write '1' to enable interrupt for event COMPARE[8]</description>
64133 <description>Read: Disabled</description>
64138 <description>Read: Enabled</description>
64146 <description>Enable</description>
64153 <description>Write '1' to enable interrupt for event COMPARE[9]</description>
64160 <description>Read: Disabled</description>
64165 <description>Read: Enabled</description>
64173 <description>Enable</description>
64180 <description>Write '1' to enable interrupt for event COMPARE[10]</description>
64187 <description>Read: Disabled</description>
64192 <description>Read: Enabled</description>
64200 <description>Enable</description>
64207 <description>Write '1' to enable interrupt for event COMPARE[11]</description>
64214 <description>Read: Disabled</description>
64219 <description>Read: Enabled</description>
64227 <description>Enable</description>
64234 <description>Write '1' to enable interrupt for event COMPARE[12]</description>
64241 <description>Read: Disabled</description>
64246 <description>Read: Enabled</description>
64254 <description>Enable</description>
64261 <description>Write '1' to enable interrupt for event COMPARE[13]</description>
64268 <description>Read: Disabled</description>
64273 <description>Read: Enabled</description>
64281 <description>Enable</description>
64288 <description>Write '1' to enable interrupt for event COMPARE[14]</description>
64295 <description>Read: Disabled</description>
64300 <description>Read: Enabled</description>
64308 <description>Enable</description>
64315 <description>Write '1' to enable interrupt for event COMPARE[15]</description>
64322 <description>Read: Disabled</description>
64327 <description>Read: Enabled</description>
64335 <description>Enable</description>
64342 <description>Write '1' to enable interrupt for event RTCOMPARESYNC</description>
64349 <description>Read: Disabled</description>
64354 <description>Read: Enabled</description>
64362 <description>Enable</description>
64369 <description>Write '1' to enable interrupt for event PWMPERIODEND</description>
64376 <description>Read: Disabled</description>
64381 <description>Read: Enabled</description>
64389 <description>Enable</description>
64398 <description>Disable interrupt</description>
64406 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
64413 <description>Read: Disabled</description>
64418 <description>Read: Enabled</description>
64426 <description>Disable</description>
64433 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
64440 <description>Read: Disabled</description>
64445 <description>Read: Enabled</description>
64453 <description>Disable</description>
64460 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
64467 <description>Read: Disabled</description>
64472 <description>Read: Enabled</description>
64480 <description>Disable</description>
64487 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
64494 <description>Read: Disabled</description>
64499 <description>Read: Enabled</description>
64507 <description>Disable</description>
64514 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
64521 <description>Read: Disabled</description>
64526 <description>Read: Enabled</description>
64534 <description>Disable</description>
64541 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
64548 <description>Read: Disabled</description>
64553 <description>Read: Enabled</description>
64561 <description>Disable</description>
64568 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
64575 <description>Read: Disabled</description>
64580 <description>Read: Enabled</description>
64588 <description>Disable</description>
64595 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
64602 <description>Read: Disabled</description>
64607 <description>Read: Enabled</description>
64615 <description>Disable</description>
64622 <description>Write '1' to disable interrupt for event COMPARE[8]</description>
64629 <description>Read: Disabled</description>
64634 <description>Read: Enabled</description>
64642 <description>Disable</description>
64649 <description>Write '1' to disable interrupt for event COMPARE[9]</description>
64656 <description>Read: Disabled</description>
64661 <description>Read: Enabled</description>
64669 <description>Disable</description>
64676 <description>Write '1' to disable interrupt for event COMPARE[10]</description>
64683 <description>Read: Disabled</description>
64688 <description>Read: Enabled</description>
64696 <description>Disable</description>
64703 <description>Write '1' to disable interrupt for event COMPARE[11]</description>
64710 <description>Read: Disabled</description>
64715 <description>Read: Enabled</description>
64723 <description>Disable</description>
64730 <description>Write '1' to disable interrupt for event COMPARE[12]</description>
64737 <description>Read: Disabled</description>
64742 <description>Read: Enabled</description>
64750 <description>Disable</description>
64757 <description>Write '1' to disable interrupt for event COMPARE[13]</description>
64764 <description>Read: Disabled</description>
64769 <description>Read: Enabled</description>
64777 <description>Disable</description>
64784 <description>Write '1' to disable interrupt for event COMPARE[14]</description>
64791 <description>Read: Disabled</description>
64796 <description>Read: Enabled</description>
64804 <description>Disable</description>
64811 <description>Write '1' to disable interrupt for event COMPARE[15]</description>
64818 <description>Read: Disabled</description>
64823 <description>Read: Enabled</description>
64831 <description>Disable</description>
64838 <description>Write '1' to disable interrupt for event RTCOMPARESYNC</description>
64845 <description>Read: Disabled</description>
64850 <description>Read: Enabled</description>
64858 <description>Disable</description>
64865 <description>Write '1' to disable interrupt for event PWMPERIODEND</description>
64872 <description>Read: Disabled</description>
64877 <description>Read: Enabled</description>
64885 <description>Disable</description>
64894 <description>Pending interrupts</description>
64902 <description>Read pending status of interrupt for event COMPARE[0]</description>
64909 <description>Read: Not pending</description>
64914 <description>Read: Pending</description>
64921 <description>Read pending status of interrupt for event COMPARE[1]</description>
64928 <description>Read: Not pending</description>
64933 <description>Read: Pending</description>
64940 <description>Read pending status of interrupt for event COMPARE[2]</description>
64947 <description>Read: Not pending</description>
64952 <description>Read: Pending</description>
64959 <description>Read pending status of interrupt for event COMPARE[3]</description>
64966 <description>Read: Not pending</description>
64971 <description>Read: Pending</description>
64978 <description>Read pending status of interrupt for event COMPARE[4]</description>
64985 <description>Read: Not pending</description>
64990 <description>Read: Pending</description>
64997 <description>Read pending status of interrupt for event COMPARE[5]</description>
65004 <description>Read: Not pending</description>
65009 <description>Read: Pending</description>
65016 <description>Read pending status of interrupt for event COMPARE[6]</description>
65023 <description>Read: Not pending</description>
65028 <description>Read: Pending</description>
65035 <description>Read pending status of interrupt for event COMPARE[7]</description>
65042 <description>Read: Not pending</description>
65047 <description>Read: Pending</description>
65054 <description>Read pending status of interrupt for event COMPARE[8]</description>
65061 <description>Read: Not pending</description>
65066 <description>Read: Pending</description>
65073 <description>Read pending status of interrupt for event COMPARE[9]</description>
65080 <description>Read: Not pending</description>
65085 <description>Read: Pending</description>
65092 <description>Read pending status of interrupt for event COMPARE[10]</description>
65099 <description>Read: Not pending</description>
65104 <description>Read: Pending</description>
65111 <description>Read pending status of interrupt for event COMPARE[11]</description>
65118 <description>Read: Not pending</description>
65123 <description>Read: Pending</description>
65130 <description>Read pending status of interrupt for event COMPARE[12]</description>
65137 <description>Read: Not pending</description>
65142 <description>Read: Pending</description>
65149 <description>Read pending status of interrupt for event COMPARE[13]</description>
65156 <description>Read: Not pending</description>
65161 <description>Read: Pending</description>
65168 <description>Read pending status of interrupt for event COMPARE[14]</description>
65175 <description>Read: Not pending</description>
65180 <description>Read: Pending</description>
65187 <description>Read pending status of interrupt for event COMPARE[15]</description>
65194 <description>Read: Not pending</description>
65199 <description>Read: Pending</description>
65206 <description>Read pending status of interrupt for event RTCOMPARESYNC</description>
65213 <description>Read: Not pending</description>
65218 <description>Read: Pending</description>
65225 <description>Read pending status of interrupt for event PWMPERIODEND</description>
65232 <description>Read: Not pending</description>
65237 <description>Read: Pending</description>
65246 <description>Enable or disable interrupt</description>
65254 <description>Enable or disable interrupt for event COMPARE[0]</description>
65260 <description>Disable</description>
65265 <description>Enable</description>
65272 <description>Enable or disable interrupt for event COMPARE[1]</description>
65278 <description>Disable</description>
65283 <description>Enable</description>
65290 <description>Enable or disable interrupt for event COMPARE[2]</description>
65296 <description>Disable</description>
65301 <description>Enable</description>
65308 <description>Enable or disable interrupt for event COMPARE[3]</description>
65314 <description>Disable</description>
65319 <description>Enable</description>
65326 <description>Enable or disable interrupt for event COMPARE[4]</description>
65332 <description>Disable</description>
65337 <description>Enable</description>
65344 <description>Enable or disable interrupt for event COMPARE[5]</description>
65350 <description>Disable</description>
65355 <description>Enable</description>
65362 <description>Enable or disable interrupt for event COMPARE[6]</description>
65368 <description>Disable</description>
65373 <description>Enable</description>
65380 <description>Enable or disable interrupt for event COMPARE[7]</description>
65386 <description>Disable</description>
65391 <description>Enable</description>
65398 <description>Enable or disable interrupt for event COMPARE[8]</description>
65404 <description>Disable</description>
65409 <description>Enable</description>
65416 <description>Enable or disable interrupt for event COMPARE[9]</description>
65422 <description>Disable</description>
65427 <description>Enable</description>
65434 <description>Enable or disable interrupt for event COMPARE[10]</description>
65440 <description>Disable</description>
65445 <description>Enable</description>
65452 <description>Enable or disable interrupt for event COMPARE[11]</description>
65458 <description>Disable</description>
65463 <description>Enable</description>
65470 <description>Enable or disable interrupt for event COMPARE[12]</description>
65476 <description>Disable</description>
65481 <description>Enable</description>
65488 <description>Enable or disable interrupt for event COMPARE[13]</description>
65494 <description>Disable</description>
65499 <description>Enable</description>
65506 <description>Enable or disable interrupt for event COMPARE[14]</description>
65512 <description>Disable</description>
65517 <description>Enable</description>
65524 <description>Enable or disable interrupt for event COMPARE[15]</description>
65530 <description>Disable</description>
65535 <description>Enable</description>
65542 <description>Enable or disable interrupt for event RTCOMPARESYNC</description>
65548 <description>Disable</description>
65553 <description>Enable</description>
65560 <description>Enable or disable interrupt for event PWMPERIODEND</description>
65566 <description>Disable</description>
65571 <description>Enable</description>
65580 <description>Enable interrupt</description>
65588 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
65595 <description>Read: Disabled</description>
65600 <description>Read: Enabled</description>
65608 <description>Enable</description>
65615 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
65622 <description>Read: Disabled</description>
65627 <description>Read: Enabled</description>
65635 <description>Enable</description>
65642 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
65649 <description>Read: Disabled</description>
65654 <description>Read: Enabled</description>
65662 <description>Enable</description>
65669 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
65676 <description>Read: Disabled</description>
65681 <description>Read: Enabled</description>
65689 <description>Enable</description>
65696 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
65703 <description>Read: Disabled</description>
65708 <description>Read: Enabled</description>
65716 <description>Enable</description>
65723 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
65730 <description>Read: Disabled</description>
65735 <description>Read: Enabled</description>
65743 <description>Enable</description>
65750 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
65757 <description>Read: Disabled</description>
65762 <description>Read: Enabled</description>
65770 <description>Enable</description>
65777 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
65784 <description>Read: Disabled</description>
65789 <description>Read: Enabled</description>
65797 <description>Enable</description>
65804 <description>Write '1' to enable interrupt for event COMPARE[8]</description>
65811 <description>Read: Disabled</description>
65816 <description>Read: Enabled</description>
65824 <description>Enable</description>
65831 <description>Write '1' to enable interrupt for event COMPARE[9]</description>
65838 <description>Read: Disabled</description>
65843 <description>Read: Enabled</description>
65851 <description>Enable</description>
65858 <description>Write '1' to enable interrupt for event COMPARE[10]</description>
65865 <description>Read: Disabled</description>
65870 <description>Read: Enabled</description>
65878 <description>Enable</description>
65885 <description>Write '1' to enable interrupt for event COMPARE[11]</description>
65892 <description>Read: Disabled</description>
65897 <description>Read: Enabled</description>
65905 <description>Enable</description>
65912 <description>Write '1' to enable interrupt for event COMPARE[12]</description>
65919 <description>Read: Disabled</description>
65924 <description>Read: Enabled</description>
65932 <description>Enable</description>
65939 <description>Write '1' to enable interrupt for event COMPARE[13]</description>
65946 <description>Read: Disabled</description>
65951 <description>Read: Enabled</description>
65959 <description>Enable</description>
65966 <description>Write '1' to enable interrupt for event COMPARE[14]</description>
65973 <description>Read: Disabled</description>
65978 <description>Read: Enabled</description>
65986 <description>Enable</description>
65993 <description>Write '1' to enable interrupt for event COMPARE[15]</description>
66000 <description>Read: Disabled</description>
66005 <description>Read: Enabled</description>
66013 <description>Enable</description>
66020 <description>Write '1' to enable interrupt for event RTCOMPARESYNC</description>
66027 <description>Read: Disabled</description>
66032 <description>Read: Enabled</description>
66040 <description>Enable</description>
66047 <description>Write '1' to enable interrupt for event PWMPERIODEND</description>
66054 <description>Read: Disabled</description>
66059 <description>Read: Enabled</description>
66067 <description>Enable</description>
66076 <description>Disable interrupt</description>
66084 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
66091 <description>Read: Disabled</description>
66096 <description>Read: Enabled</description>
66104 <description>Disable</description>
66111 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
66118 <description>Read: Disabled</description>
66123 <description>Read: Enabled</description>
66131 <description>Disable</description>
66138 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
66145 <description>Read: Disabled</description>
66150 <description>Read: Enabled</description>
66158 <description>Disable</description>
66165 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
66172 <description>Read: Disabled</description>
66177 <description>Read: Enabled</description>
66185 <description>Disable</description>
66192 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
66199 <description>Read: Disabled</description>
66204 <description>Read: Enabled</description>
66212 <description>Disable</description>
66219 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
66226 <description>Read: Disabled</description>
66231 <description>Read: Enabled</description>
66239 <description>Disable</description>
66246 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
66253 <description>Read: Disabled</description>
66258 <description>Read: Enabled</description>
66266 <description>Disable</description>
66273 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
66280 <description>Read: Disabled</description>
66285 <description>Read: Enabled</description>
66293 <description>Disable</description>
66300 <description>Write '1' to disable interrupt for event COMPARE[8]</description>
66307 <description>Read: Disabled</description>
66312 <description>Read: Enabled</description>
66320 <description>Disable</description>
66327 <description>Write '1' to disable interrupt for event COMPARE[9]</description>
66334 <description>Read: Disabled</description>
66339 <description>Read: Enabled</description>
66347 <description>Disable</description>
66354 <description>Write '1' to disable interrupt for event COMPARE[10]</description>
66361 <description>Read: Disabled</description>
66366 <description>Read: Enabled</description>
66374 <description>Disable</description>
66381 <description>Write '1' to disable interrupt for event COMPARE[11]</description>
66388 <description>Read: Disabled</description>
66393 <description>Read: Enabled</description>
66401 <description>Disable</description>
66408 <description>Write '1' to disable interrupt for event COMPARE[12]</description>
66415 <description>Read: Disabled</description>
66420 <description>Read: Enabled</description>
66428 <description>Disable</description>
66435 <description>Write '1' to disable interrupt for event COMPARE[13]</description>
66442 <description>Read: Disabled</description>
66447 <description>Read: Enabled</description>
66455 <description>Disable</description>
66462 <description>Write '1' to disable interrupt for event COMPARE[14]</description>
66469 <description>Read: Disabled</description>
66474 <description>Read: Enabled</description>
66482 <description>Disable</description>
66489 <description>Write '1' to disable interrupt for event COMPARE[15]</description>
66496 <description>Read: Disabled</description>
66501 <description>Read: Enabled</description>
66509 <description>Disable</description>
66516 <description>Write '1' to disable interrupt for event RTCOMPARESYNC</description>
66523 <description>Read: Disabled</description>
66528 <description>Read: Enabled</description>
66536 <description>Disable</description>
66543 <description>Write '1' to disable interrupt for event PWMPERIODEND</description>
66550 <description>Read: Disabled</description>
66555 <description>Read: Enabled</description>
66563 <description>Disable</description>
66572 <description>Pending interrupts</description>
66580 <description>Read pending status of interrupt for event COMPARE[0]</description>
66587 <description>Read: Not pending</description>
66592 <description>Read: Pending</description>
66599 <description>Read pending status of interrupt for event COMPARE[1]</description>
66606 <description>Read: Not pending</description>
66611 <description>Read: Pending</description>
66618 <description>Read pending status of interrupt for event COMPARE[2]</description>
66625 <description>Read: Not pending</description>
66630 <description>Read: Pending</description>
66637 <description>Read pending status of interrupt for event COMPARE[3]</description>
66644 <description>Read: Not pending</description>
66649 <description>Read: Pending</description>
66656 <description>Read pending status of interrupt for event COMPARE[4]</description>
66663 <description>Read: Not pending</description>
66668 <description>Read: Pending</description>
66675 <description>Read pending status of interrupt for event COMPARE[5]</description>
66682 <description>Read: Not pending</description>
66687 <description>Read: Pending</description>
66694 <description>Read pending status of interrupt for event COMPARE[6]</description>
66701 <description>Read: Not pending</description>
66706 <description>Read: Pending</description>
66713 <description>Read pending status of interrupt for event COMPARE[7]</description>
66720 <description>Read: Not pending</description>
66725 <description>Read: Pending</description>
66732 <description>Read pending status of interrupt for event COMPARE[8]</description>
66739 <description>Read: Not pending</description>
66744 <description>Read: Pending</description>
66751 <description>Read pending status of interrupt for event COMPARE[9]</description>
66758 <description>Read: Not pending</description>
66763 <description>Read: Pending</description>
66770 <description>Read pending status of interrupt for event COMPARE[10]</description>
66777 <description>Read: Not pending</description>
66782 <description>Read: Pending</description>
66789 <description>Read pending status of interrupt for event COMPARE[11]</description>
66796 <description>Read: Not pending</description>
66801 <description>Read: Pending</description>
66808 <description>Read pending status of interrupt for event COMPARE[12]</description>
66815 <description>Read: Not pending</description>
66820 <description>Read: Pending</description>
66827 <description>Read pending status of interrupt for event COMPARE[13]</description>
66834 <description>Read: Not pending</description>
66839 <description>Read: Pending</description>
66846 <description>Read pending status of interrupt for event COMPARE[14]</description>
66853 <description>Read: Not pending</description>
66858 <description>Read: Pending</description>
66865 <description>Read pending status of interrupt for event COMPARE[15]</description>
66872 <description>Read: Not pending</description>
66877 <description>Read: Pending</description>
66884 <description>Read pending status of interrupt for event RTCOMPARESYNC</description>
66891 <description>Read: Not pending</description>
66896 <description>Read: Pending</description>
66903 <description>Read pending status of interrupt for event PWMPERIODEND</description>
66910 <description>Read: Not pending</description>
66915 <description>Read: Pending</description>
66924 <description>Enable or disable interrupt</description>
66932 <description>Enable or disable interrupt for event COMPARE[0]</description>
66938 <description>Disable</description>
66943 <description>Enable</description>
66950 <description>Enable or disable interrupt for event COMPARE[1]</description>
66956 <description>Disable</description>
66961 <description>Enable</description>
66968 <description>Enable or disable interrupt for event COMPARE[2]</description>
66974 <description>Disable</description>
66979 <description>Enable</description>
66986 <description>Enable or disable interrupt for event COMPARE[3]</description>
66992 <description>Disable</description>
66997 <description>Enable</description>
67004 <description>Enable or disable interrupt for event COMPARE[4]</description>
67010 <description>Disable</description>
67015 <description>Enable</description>
67022 <description>Enable or disable interrupt for event COMPARE[5]</description>
67028 <description>Disable</description>
67033 <description>Enable</description>
67040 <description>Enable or disable interrupt for event COMPARE[6]</description>
67046 <description>Disable</description>
67051 <description>Enable</description>
67058 <description>Enable or disable interrupt for event COMPARE[7]</description>
67064 <description>Disable</description>
67069 <description>Enable</description>
67076 <description>Enable or disable interrupt for event COMPARE[8]</description>
67082 <description>Disable</description>
67087 <description>Enable</description>
67094 <description>Enable or disable interrupt for event COMPARE[9]</description>
67100 <description>Disable</description>
67105 <description>Enable</description>
67112 <description>Enable or disable interrupt for event COMPARE[10]</description>
67118 <description>Disable</description>
67123 <description>Enable</description>
67130 <description>Enable or disable interrupt for event COMPARE[11]</description>
67136 <description>Disable</description>
67141 <description>Enable</description>
67148 <description>Enable or disable interrupt for event COMPARE[12]</description>
67154 <description>Disable</description>
67159 <description>Enable</description>
67166 <description>Enable or disable interrupt for event COMPARE[13]</description>
67172 <description>Disable</description>
67177 <description>Enable</description>
67184 <description>Enable or disable interrupt for event COMPARE[14]</description>
67190 <description>Disable</description>
67195 <description>Enable</description>
67202 <description>Enable or disable interrupt for event COMPARE[15]</description>
67208 <description>Disable</description>
67213 <description>Enable</description>
67220 <description>Enable or disable interrupt for event RTCOMPARESYNC</description>
67226 <description>Disable</description>
67231 <description>Enable</description>
67238 <description>Enable or disable interrupt for event PWMPERIODEND</description>
67244 <description>Disable</description>
67249 <description>Enable</description>
67258 <description>Enable interrupt</description>
67266 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
67273 <description>Read: Disabled</description>
67278 <description>Read: Enabled</description>
67286 <description>Enable</description>
67293 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
67300 <description>Read: Disabled</description>
67305 <description>Read: Enabled</description>
67313 <description>Enable</description>
67320 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
67327 <description>Read: Disabled</description>
67332 <description>Read: Enabled</description>
67340 <description>Enable</description>
67347 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
67354 <description>Read: Disabled</description>
67359 <description>Read: Enabled</description>
67367 <description>Enable</description>
67374 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
67381 <description>Read: Disabled</description>
67386 <description>Read: Enabled</description>
67394 <description>Enable</description>
67401 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
67408 <description>Read: Disabled</description>
67413 <description>Read: Enabled</description>
67421 <description>Enable</description>
67428 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
67435 <description>Read: Disabled</description>
67440 <description>Read: Enabled</description>
67448 <description>Enable</description>
67455 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
67462 <description>Read: Disabled</description>
67467 <description>Read: Enabled</description>
67475 <description>Enable</description>
67482 <description>Write '1' to enable interrupt for event COMPARE[8]</description>
67489 <description>Read: Disabled</description>
67494 <description>Read: Enabled</description>
67502 <description>Enable</description>
67509 <description>Write '1' to enable interrupt for event COMPARE[9]</description>
67516 <description>Read: Disabled</description>
67521 <description>Read: Enabled</description>
67529 <description>Enable</description>
67536 <description>Write '1' to enable interrupt for event COMPARE[10]</description>
67543 <description>Read: Disabled</description>
67548 <description>Read: Enabled</description>
67556 <description>Enable</description>
67563 <description>Write '1' to enable interrupt for event COMPARE[11]</description>
67570 <description>Read: Disabled</description>
67575 <description>Read: Enabled</description>
67583 <description>Enable</description>
67590 <description>Write '1' to enable interrupt for event COMPARE[12]</description>
67597 <description>Read: Disabled</description>
67602 <description>Read: Enabled</description>
67610 <description>Enable</description>
67617 <description>Write '1' to enable interrupt for event COMPARE[13]</description>
67624 <description>Read: Disabled</description>
67629 <description>Read: Enabled</description>
67637 <description>Enable</description>
67644 <description>Write '1' to enable interrupt for event COMPARE[14]</description>
67651 <description>Read: Disabled</description>
67656 <description>Read: Enabled</description>
67664 <description>Enable</description>
67671 <description>Write '1' to enable interrupt for event COMPARE[15]</description>
67678 <description>Read: Disabled</description>
67683 <description>Read: Enabled</description>
67691 <description>Enable</description>
67698 <description>Write '1' to enable interrupt for event RTCOMPARESYNC</description>
67705 <description>Read: Disabled</description>
67710 <description>Read: Enabled</description>
67718 <description>Enable</description>
67725 <description>Write '1' to enable interrupt for event PWMPERIODEND</description>
67732 <description>Read: Disabled</description>
67737 <description>Read: Enabled</description>
67745 <description>Enable</description>
67754 <description>Disable interrupt</description>
67762 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
67769 <description>Read: Disabled</description>
67774 <description>Read: Enabled</description>
67782 <description>Disable</description>
67789 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
67796 <description>Read: Disabled</description>
67801 <description>Read: Enabled</description>
67809 <description>Disable</description>
67816 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
67823 <description>Read: Disabled</description>
67828 <description>Read: Enabled</description>
67836 <description>Disable</description>
67843 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
67850 <description>Read: Disabled</description>
67855 <description>Read: Enabled</description>
67863 <description>Disable</description>
67870 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
67877 <description>Read: Disabled</description>
67882 <description>Read: Enabled</description>
67890 <description>Disable</description>
67897 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
67904 <description>Read: Disabled</description>
67909 <description>Read: Enabled</description>
67917 <description>Disable</description>
67924 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
67931 <description>Read: Disabled</description>
67936 <description>Read: Enabled</description>
67944 <description>Disable</description>
67951 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
67958 <description>Read: Disabled</description>
67963 <description>Read: Enabled</description>
67971 <description>Disable</description>
67978 <description>Write '1' to disable interrupt for event COMPARE[8]</description>
67985 <description>Read: Disabled</description>
67990 <description>Read: Enabled</description>
67998 <description>Disable</description>
68005 <description>Write '1' to disable interrupt for event COMPARE[9]</description>
68012 <description>Read: Disabled</description>
68017 <description>Read: Enabled</description>
68025 <description>Disable</description>
68032 <description>Write '1' to disable interrupt for event COMPARE[10]</description>
68039 <description>Read: Disabled</description>
68044 <description>Read: Enabled</description>
68052 <description>Disable</description>
68059 <description>Write '1' to disable interrupt for event COMPARE[11]</description>
68066 <description>Read: Disabled</description>
68071 <description>Read: Enabled</description>
68079 <description>Disable</description>
68086 <description>Write '1' to disable interrupt for event COMPARE[12]</description>
68093 <description>Read: Disabled</description>
68098 <description>Read: Enabled</description>
68106 <description>Disable</description>
68113 <description>Write '1' to disable interrupt for event COMPARE[13]</description>
68120 <description>Read: Disabled</description>
68125 <description>Read: Enabled</description>
68133 <description>Disable</description>
68140 <description>Write '1' to disable interrupt for event COMPARE[14]</description>
68147 <description>Read: Disabled</description>
68152 <description>Read: Enabled</description>
68160 <description>Disable</description>
68167 <description>Write '1' to disable interrupt for event COMPARE[15]</description>
68174 <description>Read: Disabled</description>
68179 <description>Read: Enabled</description>
68187 <description>Disable</description>
68194 <description>Write '1' to disable interrupt for event RTCOMPARESYNC</description>
68201 <description>Read: Disabled</description>
68206 <description>Read: Enabled</description>
68214 <description>Disable</description>
68221 <description>Write '1' to disable interrupt for event PWMPERIODEND</description>
68228 <description>Read: Disabled</description>
68233 <description>Read: Enabled</description>
68241 <description>Disable</description>
68250 <description>Pending interrupts</description>
68258 <description>Read pending status of interrupt for event COMPARE[0]</description>
68265 <description>Read: Not pending</description>
68270 <description>Read: Pending</description>
68277 <description>Read pending status of interrupt for event COMPARE[1]</description>
68284 <description>Read: Not pending</description>
68289 <description>Read: Pending</description>
68296 <description>Read pending status of interrupt for event COMPARE[2]</description>
68303 <description>Read: Not pending</description>
68308 <description>Read: Pending</description>
68315 <description>Read pending status of interrupt for event COMPARE[3]</description>
68322 <description>Read: Not pending</description>
68327 <description>Read: Pending</description>
68334 <description>Read pending status of interrupt for event COMPARE[4]</description>
68341 <description>Read: Not pending</description>
68346 <description>Read: Pending</description>
68353 <description>Read pending status of interrupt for event COMPARE[5]</description>
68360 <description>Read: Not pending</description>
68365 <description>Read: Pending</description>
68372 <description>Read pending status of interrupt for event COMPARE[6]</description>
68379 <description>Read: Not pending</description>
68384 <description>Read: Pending</description>
68391 <description>Read pending status of interrupt for event COMPARE[7]</description>
68398 <description>Read: Not pending</description>
68403 <description>Read: Pending</description>
68410 <description>Read pending status of interrupt for event COMPARE[8]</description>
68417 <description>Read: Not pending</description>
68422 <description>Read: Pending</description>
68429 <description>Read pending status of interrupt for event COMPARE[9]</description>
68436 <description>Read: Not pending</description>
68441 <description>Read: Pending</description>
68448 <description>Read pending status of interrupt for event COMPARE[10]</description>
68455 <description>Read: Not pending</description>
68460 <description>Read: Pending</description>
68467 <description>Read pending status of interrupt for event COMPARE[11]</description>
68474 <description>Read: Not pending</description>
68479 <description>Read: Pending</description>
68486 <description>Read pending status of interrupt for event COMPARE[12]</description>
68493 <description>Read: Not pending</description>
68498 <description>Read: Pending</description>
68505 <description>Read pending status of interrupt for event COMPARE[13]</description>
68512 <description>Read: Not pending</description>
68517 <description>Read: Pending</description>
68524 <description>Read pending status of interrupt for event COMPARE[14]</description>
68531 <description>Read: Not pending</description>
68536 <description>Read: Pending</description>
68543 <description>Read pending status of interrupt for event COMPARE[15]</description>
68550 <description>Read: Not pending</description>
68555 <description>Read: Pending</description>
68562 <description>Read pending status of interrupt for event RTCOMPARESYNC</description>
68569 <description>Read: Not pending</description>
68574 <description>Read: Pending</description>
68581 <description>Read pending status of interrupt for event PWMPERIODEND</description>
68588 <description>Read: Not pending</description>
68593 <description>Read: Pending</description>
68602 <description>Enable or disable interrupt</description>
68610 <description>Enable or disable interrupt for event COMPARE[0]</description>
68616 <description>Disable</description>
68621 <description>Enable</description>
68628 <description>Enable or disable interrupt for event COMPARE[1]</description>
68634 <description>Disable</description>
68639 <description>Enable</description>
68646 <description>Enable or disable interrupt for event COMPARE[2]</description>
68652 <description>Disable</description>
68657 <description>Enable</description>
68664 <description>Enable or disable interrupt for event COMPARE[3]</description>
68670 <description>Disable</description>
68675 <description>Enable</description>
68682 <description>Enable or disable interrupt for event COMPARE[4]</description>
68688 <description>Disable</description>
68693 <description>Enable</description>
68700 <description>Enable or disable interrupt for event COMPARE[5]</description>
68706 <description>Disable</description>
68711 <description>Enable</description>
68718 <description>Enable or disable interrupt for event COMPARE[6]</description>
68724 <description>Disable</description>
68729 <description>Enable</description>
68736 <description>Enable or disable interrupt for event COMPARE[7]</description>
68742 <description>Disable</description>
68747 <description>Enable</description>
68754 <description>Enable or disable interrupt for event COMPARE[8]</description>
68760 <description>Disable</description>
68765 <description>Enable</description>
68772 <description>Enable or disable interrupt for event COMPARE[9]</description>
68778 <description>Disable</description>
68783 <description>Enable</description>
68790 <description>Enable or disable interrupt for event COMPARE[10]</description>
68796 <description>Disable</description>
68801 <description>Enable</description>
68808 <description>Enable or disable interrupt for event COMPARE[11]</description>
68814 <description>Disable</description>
68819 <description>Enable</description>
68826 <description>Enable or disable interrupt for event COMPARE[12]</description>
68832 <description>Disable</description>
68837 <description>Enable</description>
68844 <description>Enable or disable interrupt for event COMPARE[13]</description>
68850 <description>Disable</description>
68855 <description>Enable</description>
68862 <description>Enable or disable interrupt for event COMPARE[14]</description>
68868 <description>Disable</description>
68873 <description>Enable</description>
68880 <description>Enable or disable interrupt for event COMPARE[15]</description>
68886 <description>Disable</description>
68891 <description>Enable</description>
68898 <description>Enable or disable interrupt for event RTCOMPARESYNC</description>
68904 <description>Disable</description>
68909 <description>Enable</description>
68916 <description>Enable or disable interrupt for event PWMPERIODEND</description>
68922 <description>Disable</description>
68927 <description>Enable</description>
68936 <description>Enable interrupt</description>
68944 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
68951 <description>Read: Disabled</description>
68956 <description>Read: Enabled</description>
68964 <description>Enable</description>
68971 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
68978 <description>Read: Disabled</description>
68983 <description>Read: Enabled</description>
68991 <description>Enable</description>
68998 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
69005 <description>Read: Disabled</description>
69010 <description>Read: Enabled</description>
69018 <description>Enable</description>
69025 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
69032 <description>Read: Disabled</description>
69037 <description>Read: Enabled</description>
69045 <description>Enable</description>
69052 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
69059 <description>Read: Disabled</description>
69064 <description>Read: Enabled</description>
69072 <description>Enable</description>
69079 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
69086 <description>Read: Disabled</description>
69091 <description>Read: Enabled</description>
69099 <description>Enable</description>
69106 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
69113 <description>Read: Disabled</description>
69118 <description>Read: Enabled</description>
69126 <description>Enable</description>
69133 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
69140 <description>Read: Disabled</description>
69145 <description>Read: Enabled</description>
69153 <description>Enable</description>
69160 <description>Write '1' to enable interrupt for event COMPARE[8]</description>
69167 <description>Read: Disabled</description>
69172 <description>Read: Enabled</description>
69180 <description>Enable</description>
69187 <description>Write '1' to enable interrupt for event COMPARE[9]</description>
69194 <description>Read: Disabled</description>
69199 <description>Read: Enabled</description>
69207 <description>Enable</description>
69214 <description>Write '1' to enable interrupt for event COMPARE[10]</description>
69221 <description>Read: Disabled</description>
69226 <description>Read: Enabled</description>
69234 <description>Enable</description>
69241 <description>Write '1' to enable interrupt for event COMPARE[11]</description>
69248 <description>Read: Disabled</description>
69253 <description>Read: Enabled</description>
69261 <description>Enable</description>
69268 <description>Write '1' to enable interrupt for event COMPARE[12]</description>
69275 <description>Read: Disabled</description>
69280 <description>Read: Enabled</description>
69288 <description>Enable</description>
69295 <description>Write '1' to enable interrupt for event COMPARE[13]</description>
69302 <description>Read: Disabled</description>
69307 <description>Read: Enabled</description>
69315 <description>Enable</description>
69322 <description>Write '1' to enable interrupt for event COMPARE[14]</description>
69329 <description>Read: Disabled</description>
69334 <description>Read: Enabled</description>
69342 <description>Enable</description>
69349 <description>Write '1' to enable interrupt for event COMPARE[15]</description>
69356 <description>Read: Disabled</description>
69361 <description>Read: Enabled</description>
69369 <description>Enable</description>
69376 <description>Write '1' to enable interrupt for event RTCOMPARESYNC</description>
69383 <description>Read: Disabled</description>
69388 <description>Read: Enabled</description>
69396 <description>Enable</description>
69403 <description>Write '1' to enable interrupt for event PWMPERIODEND</description>
69410 <description>Read: Disabled</description>
69415 <description>Read: Enabled</description>
69423 <description>Enable</description>
69432 <description>Disable interrupt</description>
69440 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
69447 <description>Read: Disabled</description>
69452 <description>Read: Enabled</description>
69460 <description>Disable</description>
69467 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
69474 <description>Read: Disabled</description>
69479 <description>Read: Enabled</description>
69487 <description>Disable</description>
69494 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
69501 <description>Read: Disabled</description>
69506 <description>Read: Enabled</description>
69514 <description>Disable</description>
69521 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
69528 <description>Read: Disabled</description>
69533 <description>Read: Enabled</description>
69541 <description>Disable</description>
69548 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
69555 <description>Read: Disabled</description>
69560 <description>Read: Enabled</description>
69568 <description>Disable</description>
69575 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
69582 <description>Read: Disabled</description>
69587 <description>Read: Enabled</description>
69595 <description>Disable</description>
69602 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
69609 <description>Read: Disabled</description>
69614 <description>Read: Enabled</description>
69622 <description>Disable</description>
69629 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
69636 <description>Read: Disabled</description>
69641 <description>Read: Enabled</description>
69649 <description>Disable</description>
69656 <description>Write '1' to disable interrupt for event COMPARE[8]</description>
69663 <description>Read: Disabled</description>
69668 <description>Read: Enabled</description>
69676 <description>Disable</description>
69683 <description>Write '1' to disable interrupt for event COMPARE[9]</description>
69690 <description>Read: Disabled</description>
69695 <description>Read: Enabled</description>
69703 <description>Disable</description>
69710 <description>Write '1' to disable interrupt for event COMPARE[10]</description>
69717 <description>Read: Disabled</description>
69722 <description>Read: Enabled</description>
69730 <description>Disable</description>
69737 <description>Write '1' to disable interrupt for event COMPARE[11]</description>
69744 <description>Read: Disabled</description>
69749 <description>Read: Enabled</description>
69757 <description>Disable</description>
69764 <description>Write '1' to disable interrupt for event COMPARE[12]</description>
69771 <description>Read: Disabled</description>
69776 <description>Read: Enabled</description>
69784 <description>Disable</description>
69791 <description>Write '1' to disable interrupt for event COMPARE[13]</description>
69798 <description>Read: Disabled</description>
69803 <description>Read: Enabled</description>
69811 <description>Disable</description>
69818 <description>Write '1' to disable interrupt for event COMPARE[14]</description>
69825 <description>Read: Disabled</description>
69830 <description>Read: Enabled</description>
69838 <description>Disable</description>
69845 <description>Write '1' to disable interrupt for event COMPARE[15]</description>
69852 <description>Read: Disabled</description>
69857 <description>Read: Enabled</description>
69865 <description>Disable</description>
69872 <description>Write '1' to disable interrupt for event RTCOMPARESYNC</description>
69879 <description>Read: Disabled</description>
69884 <description>Read: Enabled</description>
69892 <description>Disable</description>
69899 <description>Write '1' to disable interrupt for event PWMPERIODEND</description>
69906 <description>Read: Disabled</description>
69911 <description>Read: Enabled</description>
69919 <description>Disable</description>
69928 <description>Pending interrupts</description>
69936 <description>Read pending status of interrupt for event COMPARE[0]</description>
69943 <description>Read: Not pending</description>
69948 <description>Read: Pending</description>
69955 <description>Read pending status of interrupt for event COMPARE[1]</description>
69962 <description>Read: Not pending</description>
69967 <description>Read: Pending</description>
69974 <description>Read pending status of interrupt for event COMPARE[2]</description>
69981 <description>Read: Not pending</description>
69986 <description>Read: Pending</description>
69993 <description>Read pending status of interrupt for event COMPARE[3]</description>
70000 <description>Read: Not pending</description>
70005 <description>Read: Pending</description>
70012 <description>Read pending status of interrupt for event COMPARE[4]</description>
70019 <description>Read: Not pending</description>
70024 <description>Read: Pending</description>
70031 <description>Read pending status of interrupt for event COMPARE[5]</description>
70038 <description>Read: Not pending</description>
70043 <description>Read: Pending</description>
70050 <description>Read pending status of interrupt for event COMPARE[6]</description>
70057 <description>Read: Not pending</description>
70062 <description>Read: Pending</description>
70069 <description>Read pending status of interrupt for event COMPARE[7]</description>
70076 <description>Read: Not pending</description>
70081 <description>Read: Pending</description>
70088 <description>Read pending status of interrupt for event COMPARE[8]</description>
70095 <description>Read: Not pending</description>
70100 <description>Read: Pending</description>
70107 <description>Read pending status of interrupt for event COMPARE[9]</description>
70114 <description>Read: Not pending</description>
70119 <description>Read: Pending</description>
70126 <description>Read pending status of interrupt for event COMPARE[10]</description>
70133 <description>Read: Not pending</description>
70138 <description>Read: Pending</description>
70145 <description>Read pending status of interrupt for event COMPARE[11]</description>
70152 <description>Read: Not pending</description>
70157 <description>Read: Pending</description>
70164 <description>Read pending status of interrupt for event COMPARE[12]</description>
70171 <description>Read: Not pending</description>
70176 <description>Read: Pending</description>
70183 <description>Read pending status of interrupt for event COMPARE[13]</description>
70190 <description>Read: Not pending</description>
70195 <description>Read: Pending</description>
70202 <description>Read pending status of interrupt for event COMPARE[14]</description>
70209 <description>Read: Not pending</description>
70214 <description>Read: Pending</description>
70221 <description>Read pending status of interrupt for event COMPARE[15]</description>
70228 <description>Read: Not pending</description>
70233 <description>Read: Pending</description>
70240 <description>Read pending status of interrupt for event RTCOMPARESYNC</description>
70247 <description>Read: Not pending</description>
70252 <description>Read: Pending</description>
70259 <description>Read pending status of interrupt for event PWMPERIODEND</description>
70266 <description>Read: Not pending</description>
70271 <description>Read: Pending</description>
70280 <description>Enable or disable event routing</description>
70288 <description>Enable or disable event routing for event PWMPERIODEND</description>
70294 <description>Disable</description>
70299 <description>Enable</description>
70308 <description>Enable event routing</description>
70316 <description>Write '1' to enable event routing for event PWMPERIODEND</description>
70323 <description>Read: Disabled</description>
70328 <description>Read: Enabled</description>
70336 <description>Enable</description>
70345 <description>Disable event routing</description>
70353 <description>Write '1' to disable event routing for event PWMPERIODEND</description>
70360 <description>Read: Disabled</description>
70365 <description>Read: Enabled</description>
70373 <description>Disable</description>
70382 <description>Counter mode selection</description>
70390 <description>Automatic enable to keep the SYSCOUNTER active.</description>
70396 <description>Default configuration to keep the SYSCOUNTER active.</description>
70401 …<description>In addition to the above mode, any local CPU that is not sleeping keep the SYSCOUNTER…
70408 <description>Enable the SYSCOUNTER</description>
70414 <description>SYSCOUNTER disabled</description>
70419 <description>SYSCOUNTER enabled</description>
70430 <description>Unspecified</description>
70436 …<description>Description cluster: The lower 32-bits of Capture/Compare register CC[n]</description>
70444 <description>Capture/Compare low value in 1 us</description>
70452 …<description>Description cluster: The higher 32-bits of Capture/Compare register CC[n]</descriptio…
70460 <description>Capture/Compare high value in 1 us</description>
70468 …<description>Description cluster: Count to add to CC[n] when this register is written.</descriptio…
70476 <description>Count to add to CC[n]</description>
70482 <description>Configure the Capture/Compare register</description>
70488 <description>Adds SYSCOUNTER value.</description>
70493 <description>Adds CC value.</description>
70502 <description>Description cluster: Configure Capture/Compare register CC[n]</description>
70510 <description>Configure the Capture/Compare register</description>
70516 <description>Capture/Compare register CC[n] Disabled.</description>
70521 <description>Capture/Compare register CC[n] enabled.</description>
70531 … <description>Timeout after all CPUs gone into sleep state to stop the SYSCOUNTER</description>
70539 <description>Number of 32Ki cycles</description>
70547 … <description>Count to add to CC[0] when the event EVENTS_COMPARE[0] triggers.</description>
70555 <description>Count to add to CC[0]</description>
70563 <description>PWM configuration.</description>
70571 <description>The PWM compare value</description>
70579 <description>Configuration of clock output</description>
70587 <description>Enable 32Ki clock output on pin</description>
70593 <description>Disabled</description>
70598 <description>Enabled</description>
70605 <description>Enable fast clock output on pin</description>
70611 <description>Disabled</description>
70616 <description>Enabled</description>
70625 <description>Clock Configuration</description>
70633 <description>Fast clock divisor value of clock output</description>
70639 <description>GRTC LFCLK clock source selection</description>
70646 <description>GRTC LFCLK clock source is LFXO</description>
70651 <description>GRTC LFCLK clock source is system LFCLK</description>
70656 <description>GRTC LFCLK clock source is LFLPRC</description>
70667 <description>Unspecified</description>
70673 … <description>Description cluster: The lower 32-bits of the SYSCOUNTER for index [n]</description>
70681 <description>The lower 32-bits of the SYSCOUNTER value.</description>
70689 … <description>Description cluster: The higher 20-bits of the SYSCOUNTER for index [n]</description>
70697 <description>The higher 20-bits of the SYSCOUNTER value.</description>
70703 <description>SYSCOUNTER busy status</description>
70709 <description>SYSCOUNTER is ready for read</description>
70714 …<description>SYSCOUNTER is busy, so not ready for read (value returned in the VALUE field of this …
70721 <description>The SYSCOUNTERL overflow indication after reading it.</description>
70727 <description>SYSCOUNTERL is not overflown</description>
70732 <description>SYSCOUNTERL overflown</description>
70741 …<description>Description cluster: Request to keep the SYSCOUNTER in the active state and prevent g…
70749 <description>Keep SYSCOUNTER in active state</description>
70755 <description>Allow SYSCOUNTER to go to sleep</description>
70760 <description>Keep SYSCOUNTER active</description>
70772 <description>Trace buffer monitor</description>
70790 <description>Start counter</description>
70798 <description>Start counter</description>
70804 <description>Trigger task</description>
70813 <description>Stop counter, clear counter value</description>
70821 <description>Stop counter, clear counter value</description>
70827 <description>Trigger task</description>
70836 <description>Save current counter value to COUNTSNAPSHOT</description>
70844 <description>Save current counter value to COUNTSNAPSHOT</description>
70850 <description>Trigger task</description>
70859 <description>Counter value equals half-full</description>
70867 <description>Counter value equals half-full</description>
70873 <description>Event not generated</description>
70878 <description>Event generated</description>
70887 <description>Counter value equals full</description>
70895 <description>Counter value equals full</description>
70901 <description>Event not generated</description>
70906 <description>Event generated</description>
70915 <description>Counter value saved to COUNTSNAPSHOT due to flush</description>
70923 <description>Counter value saved to COUNTSNAPSHOT due to flush</description>
70929 <description>Event not generated</description>
70934 <description>Event generated</description>
70943 <description>Enable or disable interrupt</description>
70951 <description>Enable or disable interrupt for event HALFFULL</description>
70957 <description>Disable</description>
70962 <description>Enable</description>
70969 <description>Enable or disable interrupt for event FULL</description>
70975 <description>Disable</description>
70980 <description>Enable</description>
70987 <description>Enable or disable interrupt for event FLUSH</description>
70993 <description>Disable</description>
70998 <description>Enable</description>
71007 <description>Enable interrupt</description>
71015 <description>Write '1' to enable interrupt for event HALFFULL</description>
71022 <description>Read: Disabled</description>
71027 <description>Read: Enabled</description>
71035 <description>Enable</description>
71042 <description>Write '1' to enable interrupt for event FULL</description>
71049 <description>Read: Disabled</description>
71054 <description>Read: Enabled</description>
71062 <description>Enable</description>
71069 <description>Write '1' to enable interrupt for event FLUSH</description>
71076 <description>Read: Disabled</description>
71081 <description>Read: Enabled</description>
71089 <description>Enable</description>
71098 <description>Disable interrupt</description>
71106 <description>Write '1' to disable interrupt for event HALFFULL</description>
71113 <description>Read: Disabled</description>
71118 <description>Read: Enabled</description>
71126 <description>Disable</description>
71133 <description>Write '1' to disable interrupt for event FULL</description>
71140 <description>Read: Disabled</description>
71145 <description>Read: Enabled</description>
71153 <description>Disable</description>
71160 <description>Write '1' to disable interrupt for event FLUSH</description>
71167 <description>Read: Disabled</description>
71172 <description>Read: Enabled</description>
71180 <description>Disable</description>
71189 <description>Pending interrupts</description>
71197 <description>Read pending status of interrupt for event HALFFULL</description>
71204 <description>Read: Not pending</description>
71209 <description>Read: Pending</description>
71216 <description>Read pending status of interrupt for event FULL</description>
71223 <description>Read: Not pending</description>
71228 <description>Read: Pending</description>
71235 <description>Read pending status of interrupt for event FLUSH</description>
71242 <description>Read: Not pending</description>
71247 <description>Read: Pending</description>
71256 <description>System RAM trace buffer total size in bytes</description>
71264 …<description>Must only be configured in STOP mode. Must be programmed to multiple of 16 bytes to m…
71266 maximum value 0x1000 i.e. 4096 bytes.</description>
71272 <description>0 bytes</description>
71277 <description>16 bytes</description>
71282 <description>4096 bytes</description>
71291 <description>Counter current value</description>
71299 …<description>Counter current value. Only writable when counter is in stopped state. Writing when n…
71300 state will generate a bus fault.</description>
71308 <description>Copy of the current COUNT value</description>
71316 … <description>TASKS_FLUSH will copy the current COUNT value to this register.</description>
71326 <description>USBHS</description>
71344 <description>Start the USB peripheral.</description>
71352 <description>Start the USB peripheral.</description>
71358 <description>Trigger task</description>
71367 <description>Stop the USB peripheral</description>
71375 <description>Stop the USB peripheral</description>
71381 <description>Trigger task</description>
71390 <description>Subscribe configuration for task START</description>
71398 <description>DPPI channel that task START will subscribe to</description>
71409 <description>Disable subscription</description>
71414 <description>Enable subscription</description>
71423 <description>Subscribe configuration for task STOP</description>
71431 <description>DPPI channel that task STOP will subscribe to</description>
71442 <description>Disable subscription</description>
71447 <description>Enable subscription</description>
71456 <description>Event indicating that interrupt triggered at USBHS core</description>
71464 <description>Event indicating that interrupt triggered at USBHS core</description>
71470 <description>Event not generated</description>
71475 <description>Event generated</description>
71484 <description>Publish configuration for event CORE</description>
71492 <description>DPPI channel that event CORE will publish to</description>
71503 <description>Disable publishing</description>
71508 <description>Enable publishing</description>
71517 <description>Enable interrupt</description>
71525 <description>Write '1' to enable interrupt for event CORE</description>
71532 <description>Read: Disabled</description>
71537 <description>Read: Enabled</description>
71545 <description>Enable</description>
71554 <description>Disable interrupt</description>
71562 <description>Write '1' to disable interrupt for event CORE</description>
71569 <description>Read: Disabled</description>
71574 <description>Read: Enabled</description>
71582 <description>Disable</description>
71591 <description>Pending interrupts</description>
71599 <description>Read pending status of interrupt for event CORE</description>
71606 <description>Read: Not pending</description>
71611 <description>Read: Pending</description>
71620 <description>Enable USB peripheral.</description>
71628 <description>Enable USB Controller</description>
71634 <description>USB Controller disabled.</description>
71639 <description>USB Controller enabled.</description>
71646 <description>Enable USB PHY</description>
71652 <description>USB PHY disabled.</description>
71657 <description>USB PHY enabled.</description>
71666 <description>Unspecified</description>
71672 <description>USB PHY parameter overrides</description>
71680 <description>PLL Integral Path Tune</description>
71686 <description>PLL Proportional Path Tune</description>
71692 <description>Disconnect Threshold Adjustment</description>
71698 <description>Squelch Threshold Adjustment</description>
71704 <description>Data Detect Voltage Adjustment</description>
71710 <description>Transmitter High-Speed Crossover Adjustment</description>
71716 <description>FS/LS Source Impedance Adjustment</description>
71722 <description>HS DC Voltage Level Adjustment</description>
71728 <description>HS Transmitter Rise/Fall Time Adjustment</description>
71734 <description>USB Source Impedance Adjustment</description>
71740 <description>HS Transmitter Pre-Emphasis Current Control</description>
71746 <description>HS Transmitter Pre-Emphasis Duration Control</description>
71754 <description>USB PHY clock configurations</description>
71762 <description>Select reference clock frequency</description>
71768 <description>Reference clock is 19.2MHz.</description>
71773 <description>Reference clock is 20MHz.</description>
71778 <description>Reference clock is 24MHz.</description>
71783 <description>Reference clock is 50MHz.</description>
71790 <description>PLL bandwidth adjustment</description>
71796 <description>PLL bandwidth adjustment disabled.</description>
71801 <description>PLL bandwidth adjustment enabled.</description>
71808 <description>Common block power down control</description>
71814 …<description>The REFCLOCK_LOGIC,bias and PLL blocks are powered in sleep or suspend mode.</descrip…
71819 …<description>The REFCLOCK_LOGIC, bias and PLL blocks are powered down in suspend mode and bias and…
71820 blocks are powered down in sleep mode.</description>
71829 … <description>Values that are used to override the input signals to the PHY.</description>
71837 <description>This field controls the pull-down resistor on D+</description>
71843 <description>The pull-down resistor on D+ is enabled</description>
71848 <description>The pull-down resistor on D+ is disabled</description>
71855 <description>This field controls the pull-down resistor on D-</description>
71861 <description>The pull-down resistor on D+ is enabled</description>
71866 <description>The pull-down resistor on D+ is disabled</description>
71883 <description>External Memory Interface</description>
71901 <description>Start operation.</description>
71909 <description>Start operation.</description>
71915 <description>Trigger task</description>
71924 <description>Stop operation.</description>
71932 <description>Stop operation.</description>
71938 <description>Trigger task</description>
71947 <description>Event indicating that interrupt triggered at EXMIF core</description>
71955 <description>Event indicating that interrupt triggered at EXMIF core</description>
71961 <description>Event not generated</description>
71966 <description>Event generated</description>
71975 …<description>Event indicating that the START task is completed and the EXMIF has started.</descrip…
71983 …<description>Event indicating that the START task is completed and the EXMIF has started.</descrip…
71989 <description>Event not generated</description>
71994 <description>Event generated</description>
72003 <description>Enable or disable interrupt</description>
72011 <description>Enable or disable interrupt for event CORE</description>
72017 <description>Disable</description>
72022 <description>Enable</description>
72029 <description>Enable or disable interrupt for event STARTED</description>
72035 <description>Disable</description>
72040 <description>Enable</description>
72049 <description>Enable interrupt</description>
72057 <description>Write '1' to enable interrupt for event CORE</description>
72064 <description>Read: Disabled</description>
72069 <description>Read: Enabled</description>
72077 <description>Enable</description>
72084 <description>Write '1' to enable interrupt for event STARTED</description>
72091 <description>Read: Disabled</description>
72096 <description>Read: Enabled</description>
72104 <description>Enable</description>
72113 <description>Disable interrupt</description>
72121 <description>Write '1' to disable interrupt for event CORE</description>
72128 <description>Read: Disabled</description>
72133 <description>Read: Enabled</description>
72141 <description>Disable</description>
72148 <description>Write '1' to disable interrupt for event STARTED</description>
72155 <description>Read: Disabled</description>
72160 <description>Read: Enabled</description>
72168 <description>Disable</description>
72177 <description>Pending interrupts</description>
72185 <description>Read pending status of interrupt for event CORE</description>
72192 <description>Read: Not pending</description>
72197 <description>Read: Pending</description>
72204 <description>Read pending status of interrupt for event STARTED</description>
72211 <description>Read: Not pending</description>
72216 <description>Read: Pending</description>
72225 <description>Configuration for external memory device 1.</description>
72231 <description>Address offset for external memory device 1.</description>
72239 <description>External memory Offset.</description>
72247 <description>Upper address range for external memory device 1.</description>
72255 <description>Upper limit address.</description>
72263 <description>Enable or disable external memory access.</description>
72271 … <description>Enable or disable external memory access from AXI interface.</description>
72277 <description>Disable external memory.</description>
72282 <description>Enable external memory.</description>
72292 <description>Configuration for external memory device 2.</description>
72299 <description>Address offset for external memory device 2.</description>
72307 <description>External memory Offset.</description>
72315 <description>Upper address range for external memory device 2.</description>
72323 <description>Upper limit address.</description>
72331 <description>Enable or disable external memory access.</description>
72339 … <description>Enable or disable external memory access from AXI interface.</description>
72345 <description>Disable external memory.</description>
72350 <description>Enable external memory.</description>
72360 <description>Unspecified</description>
72367 … <description>Enable or disable locked APB access to serial memory controller.</description>
72375 <description>Enable or disable locked APB access to SSI.</description>
72381 <description>Disable locked APB access.</description>
72386 <description>Enable locked APB access.</description>
72395 <description>Reset the external memory.</description>
72408 <description>Reset is cleared.</description>
72413 <description>Reset is set.</description>
72423 <description>Unspecified</description>
72429 <description>Unspecified</description>
72435 <description>This register controls the serial data transfer.</description>
72443 <description>Data Frame Size.</description>
72449 <description>Unspecified</description>
72454 <description>Unspecified</description>
72459 <description>Unspecified</description>
72464 <description>Unspecified</description>
72469 <description>Unspecified</description>
72474 <description>Unspecified</description>
72479 <description>Unspecified</description>
72484 <description>Unspecified</description>
72489 <description>Unspecified</description>
72494 <description>Unspecified</description>
72499 <description>Unspecified</description>
72504 <description>Unspecified</description>
72509 <description>Unspecified</description>
72514 <description>Unspecified</description>
72519 <description>Unspecified</description>
72524 <description>Unspecified</description>
72529 <description>Unspecified</description>
72534 <description>Unspecified</description>
72539 <description>Unspecified</description>
72544 <description>Unspecified</description>
72549 <description>Unspecified</description>
72554 <description>Unspecified</description>
72559 <description>Unspecified</description>
72564 <description>Unspecified</description>
72569 <description>Unspecified</description>
72574 <description>Unspecified</description>
72579 <description>Unspecified</description>
72584 <description>Unspecified</description>
72589 <description>Unspecified</description>
72594 <description>Unspecified</description>
72599 <description>Unspecified</description>
72604 <description>Unspecified</description>
72611 <description>Frame Format.</description>
72617 <description>Unspecified</description>
72622 <description>Unspecified</description>
72627 <description>Unspecified</description>
72634 <description>Serial Clock Phase.</description>
72640 <description>Unspecified</description>
72645 <description>Unspecified</description>
72652 <description>Serial Clock Polarity.</description>
72658 <description>Unspecified</description>
72663 <description>Unspecified</description>
72670 <description>Transfer Mode.</description>
72676 <description>Unspecified</description>
72681 <description>Unspecified</description>
72686 <description>Unspecified</description>
72691 <description>Unspecified</description>
72698 <description>Slave Output Enable.</description>
72704 <description>Unspecified</description>
72709 <description>Unspecified</description>
72716 <description>Shift Register Loop.</description>
72722 <description>Unspecified</description>
72727 <description>Unspecified</description>
72734 <description>Slave Select Toggle Enable.</description>
72740 <description>Unspecified</description>
72745 <description>Unspecified</description>
72752 <description>Control Frame Size.</description>
72758 <description>Unspecified</description>
72763 <description>Unspecified</description>
72768 <description>Unspecified</description>
72773 <description>Unspecified</description>
72778 <description>Unspecified</description>
72783 <description>Unspecified</description>
72788 <description>Unspecified</description>
72793 <description>Unspecified</description>
72798 <description>Unspecified</description>
72803 <description>Unspecified</description>
72808 <description>Unspecified</description>
72813 <description>Unspecified</description>
72818 <description>Unspecified</description>
72823 <description>Unspecified</description>
72828 <description>Unspecified</description>
72833 <description>Unspecified</description>
72840 <description>SPI Frame Format</description>
72846 <description>Unspecified</description>
72851 <description>Unspecified</description>
72856 <description>Unspecified</description>
72861 <description>Unspecified</description>
72868 <description>SPI Hyperbus Frame format enable.</description>
72874 <description>Unspecified</description>
72879 <description>Unspecified</description>
72886 <description>Enable Dynamic wait states in SPI mode of operation.</description>
72893 <description>Unspecified</description>
72898 <description>Unspecified</description>
72905 … <description>This field selects if DWC_ssi is working in Master or Slave mode</description>
72912 <description>Unspecified</description>
72917 <description>Unspecified</description>
72926 …<description>This register exists only when the DWC_ssi is configured as a master device.</descrip…
72934 <description>Number of Data Frames.</description>
72942 <description>This register enables and disables the DWC_ssi.</description>
72950 <description>SSI Enable.</description>
72956 <description>Unspecified</description>
72961 <description>Unspecified</description>
72970 …<description>This register controls the direction of the data word for the half-duplex Microwire s…
72978 <description>Microwire Transfer Mode.</description>
72984 <description>Unspecified</description>
72989 <description>Unspecified</description>
72996 <description>Microwire Control.</description>
73002 <description>Unspecified</description>
73007 <description>Unspecified</description>
73014 <description>Microwire Handshaking.</description>
73020 <description>Unspecified</description>
73025 <description>Unspecified</description>
73034 …<description>This register is valid only when the DWC_ssi is configured as a master device.</descr…
73042 <description>Slave Select Enable Flag.</description>
73048 <description>Unspecified</description>
73053 <description>Unspecified</description>
73062 …<description>This register is valid only when the DWC_ssi is configured as a master device.</descr…
73070 <description>SSI Clock Divider.</description>
73078 …<description>This register controls the threshold value for the transmit FIFO memory..</descriptio…
73086 <description>Transmit FIFO Threshold.</description>
73092 <description>Transfer start FIFO level.</description>
73100 …<description>This register controls the threshold value for the receive FIFO memory..</description>
73108 <description>Receive FIFO Threshold.</description>
73116 …<description>This register contains the number of valid data entries in the transmit FIFO memory.<…
73124 <description>Transmit FIFO Level.</description>
73133 …<description>This register contains the number of valid data entries in the receive FIFO memory.</…
73141 <description>Receive FIFO Level.</description>
73150 …description>This is a read-only register used to indicate the current transfer status, FIFO status…
73158 <description>SSI Busy Flag.</description>
73165 <description>Unspecified</description>
73170 <description>Unspecified</description>
73177 <description>Transmit FIFO Not Full.</description>
73184 <description>Unspecified</description>
73189 <description>Unspecified</description>
73196 <description>Transmit FIFO Empty.</description>
73203 <description>Unspecified</description>
73208 <description>Unspecified</description>
73215 <description>Receive FIFO Not Empty.</description>
73222 <description>Unspecified</description>
73227 <description>Unspecified</description>
73234 <description>Receive FIFO Full.</description>
73241 <description>Unspecified</description>
73246 <description>Unspecified</description>
73253 <description>Transmission Error.</description>
73260 <description>Unspecified</description>
73265 <description>Unspecified</description>
73272 <description>Data Collision Error.</description>
73279 <description>Unspecified</description>
73284 <description>Unspecified</description>
73293 …<description>This read/write register masks or enables all interrupts generated by the DWC_ssi.</d…
73301 <description>Transmit FIFO Empty Interrupt Mask</description>
73307 <description>Unspecified</description>
73312 <description>Unspecified</description>
73319 <description>Transmit FIFO Overflow Interrupt Mask</description>
73325 <description>Unspecified</description>
73330 <description>Unspecified</description>
73337 <description>Receive FIFO Underflow Interrupt Mask</description>
73343 <description>Unspecified</description>
73348 <description>Unspecified</description>
73355 <description>Receive FIFO Overflow Interrupt Mask</description>
73361 <description>Unspecified</description>
73366 <description>Unspecified</description>
73373 <description>Receive FIFO Full Interrupt Mask</description>
73379 <description>ssi_rxf_intr interrupt is masked</description>
73384 <description>ssi_rxf_intr interrupt is not masked</description>
73391 <description>Multi-Master Contention Interrupt Mask.</description>
73397 <description>Unspecified</description>
73402 <description>Unspecified</description>
73409 <description>XIP Receive FIFO Overflow Interrupt Mask</description>
73415 <description>Unspecified</description>
73420 <description>Unspecified</description>
73427 <description>Transmit FIFO Underflow Interrupt Mask</description>
73433 <description>Unspecified</description>
73438 <description>Unspecified</description>
73445 <description>SSI Done Interrupt Mask</description>
73452 <description>Unspecified</description>
73457 <description>Unspecified</description>
73466 …<description>This register reports the status of the DWC_ssi interrupts after they have been maske…
73474 <description>Transmit FIFO Empty Interrupt Status</description>
73481 <description>Unspecified</description>
73486 <description>Unspecified</description>
73493 <description>Transmit FIFO Overflow Interrupt Status</description>
73500 <description>Unspecified</description>
73505 <description>Unspecified</description>
73512 <description>Receive FIFO Underflow Interrupt Status</description>
73519 <description>Unspecified</description>
73524 <description>Unspecified</description>
73531 <description>Receive FIFO Overflow Interrupt Status</description>
73538 <description>Unspecified</description>
73543 <description>Unspecified</description>
73550 <description>Receive FIFO Full Interrupt Status</description>
73557 <description>Unspecified</description>
73562 <description>Unspecified</description>
73569 <description>Multi-Master Contention Interrupt Status.</description>
73576 <description>Unspecified</description>
73581 <description>Unspecified</description>
73588 <description>XIP Receive FIFO Overflow Interrupt Status</description>
73595 <description>Unspecified</description>
73600 <description>Unspecified</description>
73607 <description>Transmit FIFO Underflow Interrupt Status</description>
73614 <description>Unspecified</description>
73619 <description>Unspecified</description>
73626 <description>SSI Done Interrupt Status</description>
73633 <description>Unspecified</description>
73638 <description>Unspecified</description>
73647 <description>Raw Interrupt Status Register</description>
73655 <description>Transmit FIFO Empty Raw Interrupt Status</description>
73662 <description>Unspecified</description>
73667 <description>Unspecified</description>
73674 <description>Transmit FIFO Overflow Raw Interrupt Status</description>
73681 <description>Unspecified</description>
73686 <description>Unspecified</description>
73693 <description>Receive FIFO Underflow Raw Interrupt Status</description>
73700 <description>Unspecified</description>
73705 <description>Unspecified</description>
73712 <description>Receive FIFO Overflow Raw Interrupt Status</description>
73719 <description>Unspecified</description>
73724 <description>Unspecified</description>
73731 <description>Receive FIFO Full Raw Interrupt Status</description>
73738 <description>Unspecified</description>
73743 <description>Unspecified</description>
73750 <description>Multi-Master Contention Raw Interrupt Status.</description>
73757 <description>Unspecified</description>
73762 <description>Unspecified</description>
73769 <description>XIP Receive FIFO Overflow Raw Interrupt Status</description>
73776 <description>Unspecified</description>
73781 <description>Unspecified</description>
73788 <description>Transmit FIFO Underflow Interrupt Raw Status</description>
73795 <description>Unspecified</description>
73800 <description>Unspecified</description>
73807 <description>SSI Done Interrupt Raw Status</description>
73814 <description>Unspecified</description>
73819 <description>Unspecified</description>
73828 <description>Transmit FIFO Error Interrupt Clear Register</description>
73836 <description>Clear Transmit FIFO Overflow/Underflow Interrupt.</description>
73845 <description>Receive FIFO Overflow Interrupt Clear Register</description>
73853 <description>Clear Receive FIFO Overflow Interrupt.</description>
73862 <description>Receive FIFO Underflow Interrupt Clear Register</description>
73870 <description>Clear Receive FIFO Underflow Interrupt.</description>
73879 <description>Multi-Master Interrupt Clear Register</description>
73887 <description>Clear Multi-Master Contention Interrupt.</description>
73896 <description>Interrupt Clear Register</description>
73904 <description>Clear Interrupts.</description>
73913 …description>This register contains the peripherals identification code, which is written into the …
73921 <description>Identification code.</description>
73930 … <description>This read-only register stores the specific DWC_ssi component version.</description>
73938 … <description>Contains the hex representation of the Synopsys component version.</description>
73949 …<description>Description collection: The DWC_ssi data register is a 32-bit read/write buffer for t…
73957 <description>Data Register.</description>
73965 …<description>This register is only valid when the DWC_ssi is configured with rxd sample delay logi…
73973 <description>Receive Data (rxd) Sample Delay.</description>
73979 <description>Receive Data (rxd) Sampling Edge.</description>
73987 …<description>This register is used to control the serial data transfer in enhanced SPI mode of ope…
73995 <description>Address and instruction transfer format.</description>
74001 <description>Unspecified</description>
74006 <description>Unspecified</description>
74011 <description>Unspecified</description>
74016 <description>Unspecified</description>
74023 <description>This bit defines Length of Address to be transmitted.</description>
74029 <description>Unspecified</description>
74034 <description>Unspecified</description>
74039 <description>Unspecified</description>
74044 <description>Unspecified</description>
74049 <description>Unspecified</description>
74054 <description>Unspecified</description>
74059 <description>Unspecified</description>
74064 <description>Unspecified</description>
74069 <description>Unspecified</description>
74074 <description>Unspecified</description>
74079 <description>Unspecified</description>
74084 <description>Unspecified</description>
74089 <description>Unspecified</description>
74094 <description>Unspecified</description>
74099 <description>Unspecified</description>
74104 <description>Unspecified</description>
74111 <description>Mode bits enable in XIP mode.</description>
74118 <description>Dual/Quad/Octal mode instruction length in bits.</description>
74124 <description>Unspecified</description>
74129 <description>Unspecified</description>
74134 <description>Unspecified</description>
74139 <description>Unspecified</description>
74146 …<description>Wait cycles in Dual/Quad/Octal mode between control frames transmit and data receptio…
74152 <description>SPI DDR Enable bit.</description>
74158 <description>Instruction DDR Enable bit.</description>
74164 <description>Read data strobe enable bit.</description>
74170 <description>Fix DFS for XIP transfers.</description>
74177 <description>XIP instruction enable bit.</description>
74184 <description>Enable continuous transfer in XIP mode.</description>
74191 <description>SPI data mask enable bit.</description>
74197 …<description>Enable rxds signaling during address and command phase of Hyperbus transfer.</descrip…
74203 <description>XIP Mode bits length.</description>
74210 <description>Unspecified</description>
74215 <description>Unspecified</description>
74220 <description>Unspecified</description>
74225 <description>Unspecified</description>
74232 <description>Enables XIP pre-fetch functionality in DWC_ssi.</description>
74239 <description>Enables clock stretching capability in SPI transfers.</description>
74247 … <description>This Register is valid only when SSIC_HAS_DDR is equal to 1.</description>
74255 …<description>TXD Drive edge register which decided the driving edge of transmit data.</description>
74263 …<description>This register carries the mode bits which are sent in the XIP mode of operation after…
74271 … <description>XIP mode bits to be sent after address phase of XIP transfer.</description>
74280 <description>Unspecified</description>
74286 <description>This Register is valid only when SSIC_XIP_EN is equal to 1.</description>
74294 <description>XIP INCR transfer opcode.</description>
74302 <description>This Register is valid only when SSIC_XIP_EN is equal to 1.</description>
74310 <description>XIP WRAP transfer opcode.</description>
74318 … <description>This Register is valid only when SSIC_CONCURRENT_XIP_EN is equal to 1.</description>
74326 <description>SPI Frame Format</description>
74332 <description>Unspecified</description>
74337 <description>Unspecified</description>
74342 <description>Unspecified</description>
74347 <description>Unspecified</description>
74354 <description>Address and instruction transfer format.</description>
74360 <description>Unspecified</description>
74365 <description>Unspecified</description>
74370 <description>Unspecified</description>
74375 <description>Unspecified</description>
74382 <description>This bit defines Length of Address to be transmitted.</description>
74388 <description>Unspecified</description>
74393 <description>Unspecified</description>
74398 <description>Unspecified</description>
74403 <description>Unspecified</description>
74408 <description>Unspecified</description>
74413 <description>Unspecified</description>
74418 <description>Unspecified</description>
74423 <description>Unspecified</description>
74428 <description>Unspecified</description>
74433 <description>Unspecified</description>
74438 <description>Unspecified</description>
74443 <description>Unspecified</description>
74448 <description>Unspecified</description>
74453 <description>Unspecified</description>
74458 <description>Unspecified</description>
74463 <description>Unspecified</description>
74470 <description>Dual/Quad/Octal mode instruction length in bits.</description>
74476 <description>Unspecified</description>
74481 <description>Unspecified</description>
74486 <description>Unspecified</description>
74491 <description>Unspecified</description>
74498 <description>Mode bits enable in XIP mode.</description>
74504 …<description>Wait cycles in Dual/Quad/Octal mode between control frames transmit and data receptio…
74510 <description>Fix DFS for XIP transfers.</description>
74516 <description>SPI DDR Enable bit.</description>
74522 <description>Instruction DDR Enable bit.</description>
74528 <description>Read data strobe enable bit.</description>
74534 <description>XIP instruction enable bit.</description>
74540 <description>Enable continuous transfer in XIP mode.</description>
74547 <description>SPI Hyperbus Frame format enable for XIP transfers.</description>
74553 …<description>Enable rxds signaling during address and command phase of Hyperbus transfer.</descrip…
74559 <description>XIP Mode bits length.</description>
74565 <description>Unspecified</description>
74570 <description>Unspecified</description>
74575 <description>Unspecified</description>
74580 <description>Unspecified</description>
74587 <description>Enables XIP pre-fetch functionality in DWC_ssi.</description>
74595 <description>XIP Receive FIFO Overflow Interrupt Clear Register</description>
74603 <description>Clear XIP Receive FIFO Overflow Interrupt.</description>
74612 …<description>This Register is valid only when both SSIC_XIP_WRITE_REG_EN is set to 1.</description>
74620 <description>XIP Write INCR transfer opcode.</description>
74626 <description>Reserved bits - Read Only</description>
74635 …<description>This Register is valid only when both SSIC_XIP_WRITE_REG_EN is set to 1.</description>
74643 <description>XIP Write WRAP transfer opcode.</description>
74649 <description>Reserved bits - Read Only</description>
74658 … <description>This Register is valid only when SSIC_XIP_WRITE_REG_EN is equal to 1.</description>
74666 <description>SPI Frame Format</description>
74672 <description>Unspecified</description>
74677 <description>Unspecified</description>
74682 <description>Unspecified</description>
74687 <description>Unspecified</description>
74694 <description>Address and instruction transfer format.</description>
74700 <description>Unspecified</description>
74705 <description>Unspecified</description>
74710 <description>Unspecified</description>
74715 <description>Unspecified</description>
74722 <description>This bit defines Length of Address to be transmitted.</description>
74728 <description>Unspecified</description>
74733 <description>Unspecified</description>
74738 <description>Unspecified</description>
74743 <description>Unspecified</description>
74748 <description>Unspecified</description>
74753 <description>Unspecified</description>
74758 <description>Unspecified</description>
74763 <description>Unspecified</description>
74768 <description>Unspecified</description>
74775 <description>Dual/Quad/Octal mode instruction length in bits.</description>
74781 <description>Unspecified</description>
74786 <description>Unspecified</description>
74791 <description>Unspecified</description>
74796 <description>Unspecified</description>
74803 <description>SPI DDR Enable bit.</description>
74809 <description>Instruction DDR Enable bit.</description>
74815 … <description>SPI Hyperbus Frame format enable for XIP Write transfers.</description>
74821 …<description>Enable rxds signaling during address and command phase of Hyperbus transfer.</descrip…
74827 <description>Reserved bits - Read Only</description>
74834 …<description>Wait cycles in Dual/Quad/Octal mode between control frames transmit and data receptio…
74840 <description>Reserved bits - Read Only</description>
74853 <description>BELLBOARD public registers</description>
74871 <description>Description collection: Task TRIGGER[n]</description>
74879 <description>Task TRIGGER[n]</description>
74885 <description>Trigger task</description>
74896 <description>AUXPLL</description>
74911 <description>Start the AUXPLL</description>
74919 <description>Start the AUXPLL</description>
74925 <description>Trigger task</description>
74934 <description>Stop the AUXPLL</description>
74942 <description>Stop the AUXPLL</description>
74948 <description>Trigger task</description>
74957 <description>Change fine frequency</description>
74965 <description>Change fine frequency</description>
74971 <description>Trigger task</description>
74980 <description>Change base frequency</description>
74988 <description>Change base frequency</description>
74994 <description>Trigger task</description>
75003 <description>Start automated frequency increment</description>
75011 <description>Start automated frequency increment</description>
75017 <description>Trigger task</description>
75026 <description>Stop automated frequency increment</description>
75034 <description>Stop automated frequency increment</description>
75040 <description>Trigger task</description>
75049 <description>AUXPLL started</description>
75057 <description>AUXPLL started</description>
75063 <description>Event not generated</description>
75068 <description>Event generated</description>
75077 <description>AUXPLL stopped</description>
75085 <description>AUXPLL stopped</description>
75091 <description>Event not generated</description>
75096 <description>Event generated</description>
75105 <description>AUXPLL locked</description>
75113 <description>AUXPLL locked</description>
75119 <description>Event not generated</description>
75124 <description>Event generated</description>
75133 <description>Enable or disable interrupt</description>
75141 <description>Enable or disable interrupt for event STARTED</description>
75147 <description>Disable</description>
75152 <description>Enable</description>
75159 <description>Enable or disable interrupt for event STOPPED</description>
75165 <description>Disable</description>
75170 <description>Enable</description>
75177 <description>Enable or disable interrupt for event LOCKED</description>
75183 <description>Disable</description>
75188 <description>Enable</description>
75197 <description>Enable interrupt</description>
75205 <description>Write '1' to enable interrupt for event STARTED</description>
75212 <description>Read: Disabled</description>
75217 <description>Read: Enabled</description>
75225 <description>Enable</description>
75232 <description>Write '1' to enable interrupt for event STOPPED</description>
75239 <description>Read: Disabled</description>
75244 <description>Read: Enabled</description>
75252 <description>Enable</description>
75259 <description>Write '1' to enable interrupt for event LOCKED</description>
75266 <description>Read: Disabled</description>
75271 <description>Read: Enabled</description>
75279 <description>Enable</description>
75288 <description>Disable interrupt</description>
75296 <description>Write '1' to disable interrupt for event STARTED</description>
75303 <description>Read: Disabled</description>
75308 <description>Read: Enabled</description>
75316 <description>Disable</description>
75323 <description>Write '1' to disable interrupt for event STOPPED</description>
75330 <description>Read: Disabled</description>
75335 <description>Read: Enabled</description>
75343 <description>Disable</description>
75350 <description>Write '1' to disable interrupt for event LOCKED</description>
75357 <description>Read: Disabled</description>
75362 <description>Read: Enabled</description>
75370 <description>Disable</description>
75379 <description>Pending interrupts</description>
75387 <description>Read pending status of interrupt for event STARTED</description>
75394 <description>Read: Not pending</description>
75399 <description>Read: Pending</description>
75406 <description>Read pending status of interrupt for event STOPPED</description>
75413 <description>Read: Not pending</description>
75418 <description>Read: Pending</description>
75425 <description>Read pending status of interrupt for event LOCKED</description>
75432 <description>Read: Not pending</description>
75437 <description>Read: Pending</description>
75446 <description>Status of AUXPLL</description>
75454 <description>AUXPLL mode</description>
75460 <description>Freerunning mode</description>
75465 <description>Locked mode</description>
75472 <description>AUXPLL running status</description>
75478 <description>PLL not running</description>
75483 <description>PLL running</description>
75490 <description>Actual fractional PLL divider ratio</description>
75498 <description>Unspecified</description>
75504 <description>AUXPLL configuration</description>
75512 <description>Output buffer drive strength selection</description>
75518 <description>Lowest drive strength</description>
75523 <description>Highest drive strength</description>
75530 <description>Constant current tune for ring oscillator</description>
75536 <description>Minimum current</description>
75541 <description>Default current for audio and USB</description>
75546 <description>Maximum current</description>
75553 <description>Turn off sigma delta modulation</description>
75559 <description>Sigma Delta Modulator enabled</description>
75564 <description>Sigma Delta Modulator disabled</description>
75571 <description>Turn off dither in sigma delta modulator</description>
75577 <description>Dither enabled</description>
75582 <description>Dither disabled</description>
75589 <description>Loop divider base settings</description>
75595 <description>Low range divider setting</description>
75600 <description>Mid range divider setting</description>
75605 <description>High range divider setting</description>
75610 <description>Maximum static divider setting</description>
75620 <description>Unspecified</description>
75626 <description>Ring oscillator core process corner tuning</description>
75634 <description>Tuning value</description>
75640 <description>Highest frequency</description>
75645 <description>Default center frequency for audio and USB</description>
75650 <description>Lowest frequency</description>
75660 <description>Unspecified</description>
75666 <description>AUXPLL frequency selection</description>
75674 <description>Set fractional PLL divider ratio</description>
75680 <description>Division ratio of 4</description>
75685 <description>Division ratio for audio 44.1kHz frequency family</description>
75690 <description>Division ratio for USB PHY 24MHz clock</description>
75695 <description>Division ratio for audio 48kHz frequency family</description>
75700 <description>Division ratio of 5</description>
75709 <description>Frequency increment</description>
75717 <description>Signed 8-bit frequency increment, applied to FREQUENCY</description>
75725 <description>Frequency increment period in 1 us steps</description>
75733 <description>Frequency increment period</description>
75741 <description>AUXPLL output prescaler</description>
75749 <description>Prescaler ratio</description>
75755 … <description>Divider disabled. Bypassed external clock still supported</description>
75760 <description>Divide by 1</description>
75765 <description>Divide by 2</description>
75770 <description>Divide by 3</description>
75775 <description>Divide by 4</description>
75780 <description>Divide by 6</description>
75785 <description>Divide by 8</description>
75790 <description>Divide by 12</description>
75795 <description>Divide by 16</description>
75804 <description>Freerunning mode control</description>
75812 <description>Freerunning mode control</description>
75818 <description>Automatically handled by the AUXPLL peripheral</description>
75823 <description>Keep AUXPLL in freerunning mode</description>
75828 <description>Keep AUXPLL in locked mode</description>
75838 <description>Enable LOCK for mirrored registers</description>
75846 <description>Lock for mirrored registers</description>
75852 <description>Lock disabled</description>
75857 <description>Lock enabled</description>
75868 <description>VPR peripheral registers</description>
75885 <description>Description collection: VPR task [n] register</description>
75893 <description>VPR task [n] register</description>
75899 <description>Trigger task</description>
75910 <description>IPCT APB registers 0</description>
75932 …<description>Description collection: Trigger event on IPCT source channel n if there are no active…
75940 …<description>Trigger event on IPCT source channel n if there are no active signals present on that…
75946 <description>Trigger task</description>
75957 …<description>Description collection: Flush IPCT sink channel n. Any pending IPCT signal on that ch…
75959 configuring the SHORTS register accordingly.</description>
75967 <description>Flush IPCT sink channel n. Any pending IPCT signal on that channel will
75969 configuring the SHORTS register accordingly.</description>
75975 <description>Trigger task</description>
75986 … <description>Description collection: Subscribe configuration for task SEND[n]</description>
75994 <description>DPPI channel that task SEND[n] will subscribe to</description>
76005 <description>Disable subscription</description>
76010 <description>Enable subscription</description>
76021 … <description>Description collection: Subscribe configuration for task FLUSH[n]</description>
76029 <description>DPPI channel that task FLUSH[n] will subscribe to</description>
76040 <description>Disable subscription</description>
76045 <description>Enable subscription</description>
76056 <description>Description collection: Event received on IPCT sink channel n</description>
76064 <description>Event received on IPCT sink channel n</description>
76070 <description>Event not generated</description>
76075 <description>Event generated</description>
76086 … <description>Description collection: Event received when hardware handshake of SEND task for IPCT
76088 on that channel.</description>
76096 <description>Event received when hardware handshake of SEND task for IPCT
76098 on that channel.</description>
76104 <description>Event not generated</description>
76109 <description>Event generated</description>
76120 … <description>Description collection: Publish configuration for event RECEIVE[n]</description>
76128 <description>DPPI channel that event RECEIVE[n] will publish to</description>
76139 <description>Disable publishing</description>
76144 <description>Enable publishing</description>
76155 … <description>Description collection: Publish configuration for event READY[n]</description>
76163 <description>DPPI channel that event READY[n] will publish to</description>
76174 <description>Disable publishing</description>
76179 <description>Enable publishing</description>
76188 <description>Shortcuts between local events and tasks</description>
76196 <description>Shortcut between event RECEIVE[0] and task FLUSH[0]</description>
76202 <description>Disable shortcut</description>
76207 <description>Enable shortcut</description>
76214 <description>Shortcut between event RECEIVE[1] and task FLUSH[1]</description>
76220 <description>Disable shortcut</description>
76225 <description>Enable shortcut</description>
76232 <description>Shortcut between event RECEIVE[2] and task FLUSH[2]</description>
76238 <description>Disable shortcut</description>
76243 <description>Enable shortcut</description>
76250 <description>Shortcut between event RECEIVE[3] and task FLUSH[3]</description>
76256 <description>Disable shortcut</description>
76261 <description>Enable shortcut</description>
76268 <description>Shortcut between event RECEIVE[4] and task FLUSH[4]</description>
76274 <description>Disable shortcut</description>
76279 <description>Enable shortcut</description>
76286 <description>Shortcut between event RECEIVE[5] and task FLUSH[5]</description>
76292 <description>Disable shortcut</description>
76297 <description>Enable shortcut</description>
76304 <description>Shortcut between event RECEIVE[6] and task FLUSH[6]</description>
76310 <description>Disable shortcut</description>
76315 <description>Enable shortcut</description>
76322 <description>Shortcut between event RECEIVE[7] and task FLUSH[7]</description>
76328 <description>Disable shortcut</description>
76333 <description>Enable shortcut</description>
76342 <description>Enable or disable interrupt</description>
76350 <description>Enable or disable interrupt for event RECEIVE[0]</description>
76356 <description>Disable</description>
76361 <description>Enable</description>
76368 <description>Enable or disable interrupt for event RECEIVE[1]</description>
76374 <description>Disable</description>
76379 <description>Enable</description>
76386 <description>Enable or disable interrupt for event RECEIVE[2]</description>
76392 <description>Disable</description>
76397 <description>Enable</description>
76404 <description>Enable or disable interrupt for event RECEIVE[3]</description>
76410 <description>Disable</description>
76415 <description>Enable</description>
76422 <description>Enable or disable interrupt for event RECEIVE[4]</description>
76428 <description>Disable</description>
76433 <description>Enable</description>
76440 <description>Enable or disable interrupt for event RECEIVE[5]</description>
76446 <description>Disable</description>
76451 <description>Enable</description>
76458 <description>Enable or disable interrupt for event RECEIVE[6]</description>
76464 <description>Disable</description>
76469 <description>Enable</description>
76476 <description>Enable or disable interrupt for event RECEIVE[7]</description>
76482 <description>Disable</description>
76487 <description>Enable</description>
76494 <description>Enable or disable interrupt for event READY[0]</description>
76500 <description>Disable</description>
76505 <description>Enable</description>
76512 <description>Enable or disable interrupt for event READY[1]</description>
76518 <description>Disable</description>
76523 <description>Enable</description>
76530 <description>Enable or disable interrupt for event READY[2]</description>
76536 <description>Disable</description>
76541 <description>Enable</description>
76548 <description>Enable or disable interrupt for event READY[3]</description>
76554 <description>Disable</description>
76559 <description>Enable</description>
76566 <description>Enable or disable interrupt for event READY[4]</description>
76572 <description>Disable</description>
76577 <description>Enable</description>
76584 <description>Enable or disable interrupt for event READY[5]</description>
76590 <description>Disable</description>
76595 <description>Enable</description>
76602 <description>Enable or disable interrupt for event READY[6]</description>
76608 <description>Disable</description>
76613 <description>Enable</description>
76620 <description>Enable or disable interrupt for event READY[7]</description>
76626 <description>Disable</description>
76631 <description>Enable</description>
76640 <description>Enable interrupt</description>
76648 <description>Write '1' to enable interrupt for event RECEIVE[0]</description>
76655 <description>Read: Disabled</description>
76660 <description>Read: Enabled</description>
76668 <description>Enable</description>
76675 <description>Write '1' to enable interrupt for event RECEIVE[1]</description>
76682 <description>Read: Disabled</description>
76687 <description>Read: Enabled</description>
76695 <description>Enable</description>
76702 <description>Write '1' to enable interrupt for event RECEIVE[2]</description>
76709 <description>Read: Disabled</description>
76714 <description>Read: Enabled</description>
76722 <description>Enable</description>
76729 <description>Write '1' to enable interrupt for event RECEIVE[3]</description>
76736 <description>Read: Disabled</description>
76741 <description>Read: Enabled</description>
76749 <description>Enable</description>
76756 <description>Write '1' to enable interrupt for event RECEIVE[4]</description>
76763 <description>Read: Disabled</description>
76768 <description>Read: Enabled</description>
76776 <description>Enable</description>
76783 <description>Write '1' to enable interrupt for event RECEIVE[5]</description>
76790 <description>Read: Disabled</description>
76795 <description>Read: Enabled</description>
76803 <description>Enable</description>
76810 <description>Write '1' to enable interrupt for event RECEIVE[6]</description>
76817 <description>Read: Disabled</description>
76822 <description>Read: Enabled</description>
76830 <description>Enable</description>
76837 <description>Write '1' to enable interrupt for event RECEIVE[7]</description>
76844 <description>Read: Disabled</description>
76849 <description>Read: Enabled</description>
76857 <description>Enable</description>
76864 <description>Write '1' to enable interrupt for event READY[0]</description>
76871 <description>Read: Disabled</description>
76876 <description>Read: Enabled</description>
76884 <description>Enable</description>
76891 <description>Write '1' to enable interrupt for event READY[1]</description>
76898 <description>Read: Disabled</description>
76903 <description>Read: Enabled</description>
76911 <description>Enable</description>
76918 <description>Write '1' to enable interrupt for event READY[2]</description>
76925 <description>Read: Disabled</description>
76930 <description>Read: Enabled</description>
76938 <description>Enable</description>
76945 <description>Write '1' to enable interrupt for event READY[3]</description>
76952 <description>Read: Disabled</description>
76957 <description>Read: Enabled</description>
76965 <description>Enable</description>
76972 <description>Write '1' to enable interrupt for event READY[4]</description>
76979 <description>Read: Disabled</description>
76984 <description>Read: Enabled</description>
76992 <description>Enable</description>
76999 <description>Write '1' to enable interrupt for event READY[5]</description>
77006 <description>Read: Disabled</description>
77011 <description>Read: Enabled</description>
77019 <description>Enable</description>
77026 <description>Write '1' to enable interrupt for event READY[6]</description>
77033 <description>Read: Disabled</description>
77038 <description>Read: Enabled</description>
77046 <description>Enable</description>
77053 <description>Write '1' to enable interrupt for event READY[7]</description>
77060 <description>Read: Disabled</description>
77065 <description>Read: Enabled</description>
77073 <description>Enable</description>
77082 <description>Disable interrupt</description>
77090 <description>Write '1' to disable interrupt for event RECEIVE[0]</description>
77097 <description>Read: Disabled</description>
77102 <description>Read: Enabled</description>
77110 <description>Disable</description>
77117 <description>Write '1' to disable interrupt for event RECEIVE[1]</description>
77124 <description>Read: Disabled</description>
77129 <description>Read: Enabled</description>
77137 <description>Disable</description>
77144 <description>Write '1' to disable interrupt for event RECEIVE[2]</description>
77151 <description>Read: Disabled</description>
77156 <description>Read: Enabled</description>
77164 <description>Disable</description>
77171 <description>Write '1' to disable interrupt for event RECEIVE[3]</description>
77178 <description>Read: Disabled</description>
77183 <description>Read: Enabled</description>
77191 <description>Disable</description>
77198 <description>Write '1' to disable interrupt for event RECEIVE[4]</description>
77205 <description>Read: Disabled</description>
77210 <description>Read: Enabled</description>
77218 <description>Disable</description>
77225 <description>Write '1' to disable interrupt for event RECEIVE[5]</description>
77232 <description>Read: Disabled</description>
77237 <description>Read: Enabled</description>
77245 <description>Disable</description>
77252 <description>Write '1' to disable interrupt for event RECEIVE[6]</description>
77259 <description>Read: Disabled</description>
77264 <description>Read: Enabled</description>
77272 <description>Disable</description>
77279 <description>Write '1' to disable interrupt for event RECEIVE[7]</description>
77286 <description>Read: Disabled</description>
77291 <description>Read: Enabled</description>
77299 <description>Disable</description>
77306 <description>Write '1' to disable interrupt for event READY[0]</description>
77313 <description>Read: Disabled</description>
77318 <description>Read: Enabled</description>
77326 <description>Disable</description>
77333 <description>Write '1' to disable interrupt for event READY[1]</description>
77340 <description>Read: Disabled</description>
77345 <description>Read: Enabled</description>
77353 <description>Disable</description>
77360 <description>Write '1' to disable interrupt for event READY[2]</description>
77367 <description>Read: Disabled</description>
77372 <description>Read: Enabled</description>
77380 <description>Disable</description>
77387 <description>Write '1' to disable interrupt for event READY[3]</description>
77394 <description>Read: Disabled</description>
77399 <description>Read: Enabled</description>
77407 <description>Disable</description>
77414 <description>Write '1' to disable interrupt for event READY[4]</description>
77421 <description>Read: Disabled</description>
77426 <description>Read: Enabled</description>
77434 <description>Disable</description>
77441 <description>Write '1' to disable interrupt for event READY[5]</description>
77448 <description>Read: Disabled</description>
77453 <description>Read: Enabled</description>
77461 <description>Disable</description>
77468 <description>Write '1' to disable interrupt for event READY[6]</description>
77475 <description>Read: Disabled</description>
77480 <description>Read: Enabled</description>
77488 <description>Disable</description>
77495 <description>Write '1' to disable interrupt for event READY[7]</description>
77502 <description>Read: Disabled</description>
77507 <description>Read: Enabled</description>
77515 <description>Disable</description>
77524 <description>Pending interrupts</description>
77532 <description>Read pending status of interrupt for event RECEIVE[0]</description>
77539 <description>Read: Not pending</description>
77544 <description>Read: Pending</description>
77551 <description>Read pending status of interrupt for event RECEIVE[1]</description>
77558 <description>Read: Not pending</description>
77563 <description>Read: Pending</description>
77570 <description>Read pending status of interrupt for event RECEIVE[2]</description>
77577 <description>Read: Not pending</description>
77582 <description>Read: Pending</description>
77589 <description>Read pending status of interrupt for event RECEIVE[3]</description>
77596 <description>Read: Not pending</description>
77601 <description>Read: Pending</description>
77608 <description>Read pending status of interrupt for event RECEIVE[4]</description>
77615 <description>Read: Not pending</description>
77620 <description>Read: Pending</description>
77627 <description>Read pending status of interrupt for event RECEIVE[5]</description>
77634 <description>Read: Not pending</description>
77639 <description>Read: Pending</description>
77646 <description>Read pending status of interrupt for event RECEIVE[6]</description>
77653 <description>Read: Not pending</description>
77658 <description>Read: Pending</description>
77665 <description>Read pending status of interrupt for event RECEIVE[7]</description>
77672 <description>Read: Not pending</description>
77677 <description>Read: Pending</description>
77684 <description>Read pending status of interrupt for event READY[0]</description>
77691 <description>Read: Not pending</description>
77696 <description>Read: Pending</description>
77703 <description>Read pending status of interrupt for event READY[1]</description>
77710 <description>Read: Not pending</description>
77715 <description>Read: Pending</description>
77722 <description>Read pending status of interrupt for event READY[2]</description>
77729 <description>Read: Not pending</description>
77734 <description>Read: Pending</description>
77741 <description>Read pending status of interrupt for event READY[3]</description>
77748 <description>Read: Not pending</description>
77753 <description>Read: Pending</description>
77760 <description>Read pending status of interrupt for event READY[4]</description>
77767 <description>Read: Not pending</description>
77772 <description>Read: Pending</description>
77779 <description>Read pending status of interrupt for event READY[5]</description>
77786 <description>Read: Not pending</description>
77791 <description>Read: Pending</description>
77798 <description>Read pending status of interrupt for event READY[6]</description>
77805 <description>Read: Not pending</description>
77810 <description>Read: Pending</description>
77817 <description>Read pending status of interrupt for event READY[7]</description>
77824 <description>Read: Not pending</description>
77829 <description>Read: Pending</description>
77838 <description>Unspecified</description>
77844 <description>Overflow status for SEND tasks Write 0 to clear</description>
77852 <description>Overflow status for SEND[0] task</description>
77858 <description>Task overflow has happened</description>
77863 <description>Task overflow has not happened</description>
77870 <description>Overflow status for SEND[1] task</description>
77876 <description>Task overflow has happened</description>
77881 <description>Task overflow has not happened</description>
77888 <description>Overflow status for SEND[2] task</description>
77894 <description>Task overflow has happened</description>
77899 <description>Task overflow has not happened</description>
77906 <description>Overflow status for SEND[3] task</description>
77912 <description>Task overflow has happened</description>
77917 <description>Task overflow has not happened</description>
77924 <description>Overflow status for SEND[4] task</description>
77930 <description>Task overflow has happened</description>
77935 <description>Task overflow has not happened</description>
77942 <description>Overflow status for SEND[5] task</description>
77948 <description>Task overflow has happened</description>
77953 <description>Task overflow has not happened</description>
77960 <description>Overflow status for SEND[6] task</description>
77966 <description>Task overflow has happened</description>
77971 <description>Task overflow has not happened</description>
77978 <description>Overflow status for SEND[7] task</description>
77984 <description>Task overflow has happened</description>
77989 <description>Task overflow has not happened</description>
78001 <description>MUTEX 0</description>
78018 <description>Description collection: Mutex register</description>
78026 <description>Mutex register n</description>
78032 <description>Mutex n is in unlocked state</description>
78037 <description>Mutex n is in locked state</description>
78048 <description>I3C 0</description>
78067 <description>Event indicating that interrupt triggered at I3C core</description>
78075 <description>Event indicating that interrupt triggered at I3C core</description>
78081 <description>Event not generated</description>
78086 <description>Event generated</description>
78095 <description>Event indicating that interrupt triggered at I3C DMA</description>
78103 <description>Event indicating that interrupt triggered at I3C DMA</description>
78109 <description>Event not generated</description>
78114 <description>Event generated</description>
78123 <description>Enable or disable interrupt</description>
78131 <description>Enable or disable interrupt for event CORE</description>
78137 <description>Disable</description>
78142 <description>Enable</description>
78149 <description>Enable or disable interrupt for event DMA</description>
78155 <description>Disable</description>
78160 <description>Enable</description>
78169 <description>Enable interrupt</description>
78177 <description>Write '1' to enable interrupt for event CORE</description>
78184 <description>Read: Disabled</description>
78189 <description>Read: Enabled</description>
78197 <description>Enable</description>
78204 <description>Write '1' to enable interrupt for event DMA</description>
78211 <description>Read: Disabled</description>
78216 <description>Read: Enabled</description>
78224 <description>Enable</description>
78233 <description>Disable interrupt</description>
78241 <description>Write '1' to disable interrupt for event CORE</description>
78248 <description>Read: Disabled</description>
78253 <description>Read: Enabled</description>
78261 <description>Disable</description>
78268 <description>Write '1' to disable interrupt for event DMA</description>
78275 <description>Read: Disabled</description>
78280 <description>Read: Enabled</description>
78288 <description>Disable</description>
78297 <description>Pending interrupts</description>
78305 <description>Read pending status of interrupt for event CORE</description>
78312 <description>Read: Not pending</description>
78317 <description>Read: Pending</description>
78324 <description>Read pending status of interrupt for event DMA</description>
78331 <description>Read: Not pending</description>
78336 <description>Read: Pending</description>
78345 <description>Enable I3C peripheral.</description>
78353 <description>Enable</description>
78359 <description>I3C peripheral disabled.</description>
78364 <description>I3C peripheral enabled.</description>
78373 <description>Unspecified</description>
78379 <description>Start offset of recovered clock</description>
78387 <description>Value</description>
78395 …<description>Maximum cycle ratio between SDA/SCL and CDR (clock and data recovery) clock</descript…
78403 <description>Value</description>
78411 <description>Maximum skew between SCL and SCL in CDR clock cycles</description>
78419 <description>Value</description>
78428 <description>I3C slave interface 0</description>
78436 <description>I2C or I3C mode select signal</description>
78442 <description>Unspecified</description>
78447 <description>Unspecified</description>
78454 <description>Slave activity mode for GETSTATUS CCC</description>
78460 <description>Pending interrupt information for GETSTATUS CCC</description>
78466 <description>Slave static address valid</description>
78472 <description>Unspecified</description>
78477 <description>Unspecified</description>
78484 <description>Slave static address</description>
78490 <description>Slave maximum read data rate</description>
78496 <description>Slave maximum write write rate</description>
78502 <description>Slave maximum clock data turnaround time</description>
78508 <description>Device Characteristic Register value</description>
78516 <description>I3C slave interface 1</description>
78524 <description>Slave wakeup signal</description>
78531 <description>Unspecified</description>
78536 <description>Unspecified</description>
78545 <description>Slave Device Provisioned ID 0</description>
78553 <description>Additional Meaning</description>
78559 <description>Instance ID</description>
78565 <description>Part ID</description>
78573 <description>Slave Device Provisioned ID 1</description>
78581 <description>Provisional ID Type Selector</description>
78587 <description>MIPI Manufacturer ID</description>
78595 …<description>Enable or disable the SDA high-keeper used for Master-to-Slave and Slave-to-Master bu…
78603 <description>Enable or disable the SDA high-keeper</description>
78609 <description>High-keeper disabled.</description>
78614 <description>High-keeper enabled.</description>
78623 …<description>Enable or disable the SCL high-keeper used for Master-to-Slave and Slave-to-Master bu…
78631 <description>Enable or disable the SCL high-keeper</description>
78637 <description>High-keeper disabled.</description>
78642 <description>High-keeper enabled.</description>
78653 <description>VPR peripheral registers 0</description>
78674 <description>Description collection: VPR task [n] register</description>
78682 <description>VPR task [n] register</description>
78688 <description>Trigger task</description>
78699 …<description>Description collection: Subscribe configuration for task TASKS_TRIGGER[n]</descriptio…
78707 <description>Subscription enable bit</description>
78713 <description>Disable subscription</description>
78718 <description>Enable subscription</description>
78729 <description>Description collection: VPR event [n] register</description>
78737 <description>VPR event [n] register</description>
78743 <description>Event not generated</description>
78748 <description>Event generated</description>
78759 …<description>Description collection: Publish configuration for event EVENTS_TRIGGERED[n]</descript…
78767 <description>Publication enable bit</description>
78773 <description>Disable publishing</description>
78778 <description>Enable publishing</description>
78787 <description>Enable or disable interrupt</description>
78795 <description>Enable or disable interrupt for event TRIGGERED[0]</description>
78801 <description>Disable</description>
78806 <description>Enable</description>
78813 <description>Enable or disable interrupt for event TRIGGERED[1]</description>
78819 <description>Disable</description>
78824 <description>Enable</description>
78831 <description>Enable or disable interrupt for event TRIGGERED[2]</description>
78837 <description>Disable</description>
78842 <description>Enable</description>
78849 <description>Enable or disable interrupt for event TRIGGERED[3]</description>
78855 <description>Disable</description>
78860 <description>Enable</description>
78867 <description>Enable or disable interrupt for event TRIGGERED[4]</description>
78873 <description>Disable</description>
78878 <description>Enable</description>
78885 <description>Enable or disable interrupt for event TRIGGERED[5]</description>
78891 <description>Disable</description>
78896 <description>Enable</description>
78903 <description>Enable or disable interrupt for event TRIGGERED[6]</description>
78909 <description>Disable</description>
78914 <description>Enable</description>
78921 <description>Enable or disable interrupt for event TRIGGERED[7]</description>
78927 <description>Disable</description>
78932 <description>Enable</description>
78939 <description>Enable or disable interrupt for event TRIGGERED[8]</description>
78945 <description>Disable</description>
78950 <description>Enable</description>
78957 <description>Enable or disable interrupt for event TRIGGERED[9]</description>
78963 <description>Disable</description>
78968 <description>Enable</description>
78975 <description>Enable or disable interrupt for event TRIGGERED[10]</description>
78981 <description>Disable</description>
78986 <description>Enable</description>
78993 <description>Enable or disable interrupt for event TRIGGERED[11]</description>
78999 <description>Disable</description>
79004 <description>Enable</description>
79011 <description>Enable or disable interrupt for event TRIGGERED[12]</description>
79017 <description>Disable</description>
79022 <description>Enable</description>
79029 <description>Enable or disable interrupt for event TRIGGERED[13]</description>
79035 <description>Disable</description>
79040 <description>Enable</description>
79047 <description>Enable or disable interrupt for event TRIGGERED[14]</description>
79053 <description>Disable</description>
79058 <description>Enable</description>
79065 <description>Enable or disable interrupt for event TRIGGERED[15]</description>
79071 <description>Disable</description>
79076 <description>Enable</description>
79083 <description>Enable or disable interrupt for event TRIGGERED[16]</description>
79089 <description>Disable</description>
79094 <description>Enable</description>
79101 <description>Enable or disable interrupt for event TRIGGERED[17]</description>
79107 <description>Disable</description>
79112 <description>Enable</description>
79119 <description>Enable or disable interrupt for event TRIGGERED[18]</description>
79125 <description>Disable</description>
79130 <description>Enable</description>
79137 <description>Enable or disable interrupt for event TRIGGERED[19]</description>
79143 <description>Disable</description>
79148 <description>Enable</description>
79155 <description>Enable or disable interrupt for event TRIGGERED[20]</description>
79161 <description>Disable</description>
79166 <description>Enable</description>
79173 <description>Enable or disable interrupt for event TRIGGERED[21]</description>
79179 <description>Disable</description>
79184 <description>Enable</description>
79191 <description>Enable or disable interrupt for event TRIGGERED[22]</description>
79197 <description>Disable</description>
79202 <description>Enable</description>
79209 <description>Enable or disable interrupt for event TRIGGERED[23]</description>
79215 <description>Disable</description>
79220 <description>Enable</description>
79227 <description>Enable or disable interrupt for event TRIGGERED[24]</description>
79233 <description>Disable</description>
79238 <description>Enable</description>
79245 <description>Enable or disable interrupt for event TRIGGERED[25]</description>
79251 <description>Disable</description>
79256 <description>Enable</description>
79263 <description>Enable or disable interrupt for event TRIGGERED[26]</description>
79269 <description>Disable</description>
79274 <description>Enable</description>
79281 <description>Enable or disable interrupt for event TRIGGERED[27]</description>
79287 <description>Disable</description>
79292 <description>Enable</description>
79299 <description>Enable or disable interrupt for event TRIGGERED[28]</description>
79305 <description>Disable</description>
79310 <description>Enable</description>
79317 <description>Enable or disable interrupt for event TRIGGERED[29]</description>
79323 <description>Disable</description>
79328 <description>Enable</description>
79335 <description>Enable or disable interrupt for event TRIGGERED[30]</description>
79341 <description>Disable</description>
79346 <description>Enable</description>
79353 <description>Enable or disable interrupt for event TRIGGERED[31]</description>
79359 <description>Disable</description>
79364 <description>Enable</description>
79373 <description>Enable interrupt</description>
79381 <description>Write '1' to enable interrupt for event TRIGGERED[0]</description>
79388 <description>Read: Disabled</description>
79393 <description>Read: Enabled</description>
79401 <description>Enable</description>
79408 <description>Write '1' to enable interrupt for event TRIGGERED[1]</description>
79415 <description>Read: Disabled</description>
79420 <description>Read: Enabled</description>
79428 <description>Enable</description>
79435 <description>Write '1' to enable interrupt for event TRIGGERED[2]</description>
79442 <description>Read: Disabled</description>
79447 <description>Read: Enabled</description>
79455 <description>Enable</description>
79462 <description>Write '1' to enable interrupt for event TRIGGERED[3]</description>
79469 <description>Read: Disabled</description>
79474 <description>Read: Enabled</description>
79482 <description>Enable</description>
79489 <description>Write '1' to enable interrupt for event TRIGGERED[4]</description>
79496 <description>Read: Disabled</description>
79501 <description>Read: Enabled</description>
79509 <description>Enable</description>
79516 <description>Write '1' to enable interrupt for event TRIGGERED[5]</description>
79523 <description>Read: Disabled</description>
79528 <description>Read: Enabled</description>
79536 <description>Enable</description>
79543 <description>Write '1' to enable interrupt for event TRIGGERED[6]</description>
79550 <description>Read: Disabled</description>
79555 <description>Read: Enabled</description>
79563 <description>Enable</description>
79570 <description>Write '1' to enable interrupt for event TRIGGERED[7]</description>
79577 <description>Read: Disabled</description>
79582 <description>Read: Enabled</description>
79590 <description>Enable</description>
79597 <description>Write '1' to enable interrupt for event TRIGGERED[8]</description>
79604 <description>Read: Disabled</description>
79609 <description>Read: Enabled</description>
79617 <description>Enable</description>
79624 <description>Write '1' to enable interrupt for event TRIGGERED[9]</description>
79631 <description>Read: Disabled</description>
79636 <description>Read: Enabled</description>
79644 <description>Enable</description>
79651 <description>Write '1' to enable interrupt for event TRIGGERED[10]</description>
79658 <description>Read: Disabled</description>
79663 <description>Read: Enabled</description>
79671 <description>Enable</description>
79678 <description>Write '1' to enable interrupt for event TRIGGERED[11]</description>
79685 <description>Read: Disabled</description>
79690 <description>Read: Enabled</description>
79698 <description>Enable</description>
79705 <description>Write '1' to enable interrupt for event TRIGGERED[12]</description>
79712 <description>Read: Disabled</description>
79717 <description>Read: Enabled</description>
79725 <description>Enable</description>
79732 <description>Write '1' to enable interrupt for event TRIGGERED[13]</description>
79739 <description>Read: Disabled</description>
79744 <description>Read: Enabled</description>
79752 <description>Enable</description>
79759 <description>Write '1' to enable interrupt for event TRIGGERED[14]</description>
79766 <description>Read: Disabled</description>
79771 <description>Read: Enabled</description>
79779 <description>Enable</description>
79786 <description>Write '1' to enable interrupt for event TRIGGERED[15]</description>
79793 <description>Read: Disabled</description>
79798 <description>Read: Enabled</description>
79806 <description>Enable</description>
79813 <description>Write '1' to enable interrupt for event TRIGGERED[16]</description>
79820 <description>Read: Disabled</description>
79825 <description>Read: Enabled</description>
79833 <description>Enable</description>
79840 <description>Write '1' to enable interrupt for event TRIGGERED[17]</description>
79847 <description>Read: Disabled</description>
79852 <description>Read: Enabled</description>
79860 <description>Enable</description>
79867 <description>Write '1' to enable interrupt for event TRIGGERED[18]</description>
79874 <description>Read: Disabled</description>
79879 <description>Read: Enabled</description>
79887 <description>Enable</description>
79894 <description>Write '1' to enable interrupt for event TRIGGERED[19]</description>
79901 <description>Read: Disabled</description>
79906 <description>Read: Enabled</description>
79914 <description>Enable</description>
79921 <description>Write '1' to enable interrupt for event TRIGGERED[20]</description>
79928 <description>Read: Disabled</description>
79933 <description>Read: Enabled</description>
79941 <description>Enable</description>
79948 <description>Write '1' to enable interrupt for event TRIGGERED[21]</description>
79955 <description>Read: Disabled</description>
79960 <description>Read: Enabled</description>
79968 <description>Enable</description>
79975 <description>Write '1' to enable interrupt for event TRIGGERED[22]</description>
79982 <description>Read: Disabled</description>
79987 <description>Read: Enabled</description>
79995 <description>Enable</description>
80002 <description>Write '1' to enable interrupt for event TRIGGERED[23]</description>
80009 <description>Read: Disabled</description>
80014 <description>Read: Enabled</description>
80022 <description>Enable</description>
80029 <description>Write '1' to enable interrupt for event TRIGGERED[24]</description>
80036 <description>Read: Disabled</description>
80041 <description>Read: Enabled</description>
80049 <description>Enable</description>
80056 <description>Write '1' to enable interrupt for event TRIGGERED[25]</description>
80063 <description>Read: Disabled</description>
80068 <description>Read: Enabled</description>
80076 <description>Enable</description>
80083 <description>Write '1' to enable interrupt for event TRIGGERED[26]</description>
80090 <description>Read: Disabled</description>
80095 <description>Read: Enabled</description>
80103 <description>Enable</description>
80110 <description>Write '1' to enable interrupt for event TRIGGERED[27]</description>
80117 <description>Read: Disabled</description>
80122 <description>Read: Enabled</description>
80130 <description>Enable</description>
80137 <description>Write '1' to enable interrupt for event TRIGGERED[28]</description>
80144 <description>Read: Disabled</description>
80149 <description>Read: Enabled</description>
80157 <description>Enable</description>
80164 <description>Write '1' to enable interrupt for event TRIGGERED[29]</description>
80171 <description>Read: Disabled</description>
80176 <description>Read: Enabled</description>
80184 <description>Enable</description>
80191 <description>Write '1' to enable interrupt for event TRIGGERED[30]</description>
80198 <description>Read: Disabled</description>
80203 <description>Read: Enabled</description>
80211 <description>Enable</description>
80218 <description>Write '1' to enable interrupt for event TRIGGERED[31]</description>
80225 <description>Read: Disabled</description>
80230 <description>Read: Enabled</description>
80238 <description>Enable</description>
80247 <description>Disable interrupt</description>
80255 <description>Write '1' to disable interrupt for event TRIGGERED[0]</description>
80262 <description>Read: Disabled</description>
80267 <description>Read: Enabled</description>
80275 <description>Disable</description>
80282 <description>Write '1' to disable interrupt for event TRIGGERED[1]</description>
80289 <description>Read: Disabled</description>
80294 <description>Read: Enabled</description>
80302 <description>Disable</description>
80309 <description>Write '1' to disable interrupt for event TRIGGERED[2]</description>
80316 <description>Read: Disabled</description>
80321 <description>Read: Enabled</description>
80329 <description>Disable</description>
80336 <description>Write '1' to disable interrupt for event TRIGGERED[3]</description>
80343 <description>Read: Disabled</description>
80348 <description>Read: Enabled</description>
80356 <description>Disable</description>
80363 <description>Write '1' to disable interrupt for event TRIGGERED[4]</description>
80370 <description>Read: Disabled</description>
80375 <description>Read: Enabled</description>
80383 <description>Disable</description>
80390 <description>Write '1' to disable interrupt for event TRIGGERED[5]</description>
80397 <description>Read: Disabled</description>
80402 <description>Read: Enabled</description>
80410 <description>Disable</description>
80417 <description>Write '1' to disable interrupt for event TRIGGERED[6]</description>
80424 <description>Read: Disabled</description>
80429 <description>Read: Enabled</description>
80437 <description>Disable</description>
80444 <description>Write '1' to disable interrupt for event TRIGGERED[7]</description>
80451 <description>Read: Disabled</description>
80456 <description>Read: Enabled</description>
80464 <description>Disable</description>
80471 <description>Write '1' to disable interrupt for event TRIGGERED[8]</description>
80478 <description>Read: Disabled</description>
80483 <description>Read: Enabled</description>
80491 <description>Disable</description>
80498 <description>Write '1' to disable interrupt for event TRIGGERED[9]</description>
80505 <description>Read: Disabled</description>
80510 <description>Read: Enabled</description>
80518 <description>Disable</description>
80525 <description>Write '1' to disable interrupt for event TRIGGERED[10]</description>
80532 <description>Read: Disabled</description>
80537 <description>Read: Enabled</description>
80545 <description>Disable</description>
80552 <description>Write '1' to disable interrupt for event TRIGGERED[11]</description>
80559 <description>Read: Disabled</description>
80564 <description>Read: Enabled</description>
80572 <description>Disable</description>
80579 <description>Write '1' to disable interrupt for event TRIGGERED[12]</description>
80586 <description>Read: Disabled</description>
80591 <description>Read: Enabled</description>
80599 <description>Disable</description>
80606 <description>Write '1' to disable interrupt for event TRIGGERED[13]</description>
80613 <description>Read: Disabled</description>
80618 <description>Read: Enabled</description>
80626 <description>Disable</description>
80633 <description>Write '1' to disable interrupt for event TRIGGERED[14]</description>
80640 <description>Read: Disabled</description>
80645 <description>Read: Enabled</description>
80653 <description>Disable</description>
80660 <description>Write '1' to disable interrupt for event TRIGGERED[15]</description>
80667 <description>Read: Disabled</description>
80672 <description>Read: Enabled</description>
80680 <description>Disable</description>
80687 <description>Write '1' to disable interrupt for event TRIGGERED[16]</description>
80694 <description>Read: Disabled</description>
80699 <description>Read: Enabled</description>
80707 <description>Disable</description>
80714 <description>Write '1' to disable interrupt for event TRIGGERED[17]</description>
80721 <description>Read: Disabled</description>
80726 <description>Read: Enabled</description>
80734 <description>Disable</description>
80741 <description>Write '1' to disable interrupt for event TRIGGERED[18]</description>
80748 <description>Read: Disabled</description>
80753 <description>Read: Enabled</description>
80761 <description>Disable</description>
80768 <description>Write '1' to disable interrupt for event TRIGGERED[19]</description>
80775 <description>Read: Disabled</description>
80780 <description>Read: Enabled</description>
80788 <description>Disable</description>
80795 <description>Write '1' to disable interrupt for event TRIGGERED[20]</description>
80802 <description>Read: Disabled</description>
80807 <description>Read: Enabled</description>
80815 <description>Disable</description>
80822 <description>Write '1' to disable interrupt for event TRIGGERED[21]</description>
80829 <description>Read: Disabled</description>
80834 <description>Read: Enabled</description>
80842 <description>Disable</description>
80849 <description>Write '1' to disable interrupt for event TRIGGERED[22]</description>
80856 <description>Read: Disabled</description>
80861 <description>Read: Enabled</description>
80869 <description>Disable</description>
80876 <description>Write '1' to disable interrupt for event TRIGGERED[23]</description>
80883 <description>Read: Disabled</description>
80888 <description>Read: Enabled</description>
80896 <description>Disable</description>
80903 <description>Write '1' to disable interrupt for event TRIGGERED[24]</description>
80910 <description>Read: Disabled</description>
80915 <description>Read: Enabled</description>
80923 <description>Disable</description>
80930 <description>Write '1' to disable interrupt for event TRIGGERED[25]</description>
80937 <description>Read: Disabled</description>
80942 <description>Read: Enabled</description>
80950 <description>Disable</description>
80957 <description>Write '1' to disable interrupt for event TRIGGERED[26]</description>
80964 <description>Read: Disabled</description>
80969 <description>Read: Enabled</description>
80977 <description>Disable</description>
80984 <description>Write '1' to disable interrupt for event TRIGGERED[27]</description>
80991 <description>Read: Disabled</description>
80996 <description>Read: Enabled</description>
81004 <description>Disable</description>
81011 <description>Write '1' to disable interrupt for event TRIGGERED[28]</description>
81018 <description>Read: Disabled</description>
81023 <description>Read: Enabled</description>
81031 <description>Disable</description>
81038 <description>Write '1' to disable interrupt for event TRIGGERED[29]</description>
81045 <description>Read: Disabled</description>
81050 <description>Read: Enabled</description>
81058 <description>Disable</description>
81065 <description>Write '1' to disable interrupt for event TRIGGERED[30]</description>
81072 <description>Read: Disabled</description>
81077 <description>Read: Enabled</description>
81085 <description>Disable</description>
81092 <description>Write '1' to disable interrupt for event TRIGGERED[31]</description>
81099 <description>Read: Disabled</description>
81104 <description>Read: Enabled</description>
81112 <description>Disable</description>
81121 <description>Pending interrupts</description>
81129 <description>Read pending status of interrupt for event TRIGGERED[0]</description>
81136 <description>Read: Not pending</description>
81141 <description>Read: Pending</description>
81148 <description>Read pending status of interrupt for event TRIGGERED[1]</description>
81155 <description>Read: Not pending</description>
81160 <description>Read: Pending</description>
81167 <description>Read pending status of interrupt for event TRIGGERED[2]</description>
81174 <description>Read: Not pending</description>
81179 <description>Read: Pending</description>
81186 <description>Read pending status of interrupt for event TRIGGERED[3]</description>
81193 <description>Read: Not pending</description>
81198 <description>Read: Pending</description>
81205 <description>Read pending status of interrupt for event TRIGGERED[4]</description>
81212 <description>Read: Not pending</description>
81217 <description>Read: Pending</description>
81224 <description>Read pending status of interrupt for event TRIGGERED[5]</description>
81231 <description>Read: Not pending</description>
81236 <description>Read: Pending</description>
81243 <description>Read pending status of interrupt for event TRIGGERED[6]</description>
81250 <description>Read: Not pending</description>
81255 <description>Read: Pending</description>
81262 <description>Read pending status of interrupt for event TRIGGERED[7]</description>
81269 <description>Read: Not pending</description>
81274 <description>Read: Pending</description>
81281 <description>Read pending status of interrupt for event TRIGGERED[8]</description>
81288 <description>Read: Not pending</description>
81293 <description>Read: Pending</description>
81300 <description>Read pending status of interrupt for event TRIGGERED[9]</description>
81307 <description>Read: Not pending</description>
81312 <description>Read: Pending</description>
81319 <description>Read pending status of interrupt for event TRIGGERED[10]</description>
81326 <description>Read: Not pending</description>
81331 <description>Read: Pending</description>
81338 <description>Read pending status of interrupt for event TRIGGERED[11]</description>
81345 <description>Read: Not pending</description>
81350 <description>Read: Pending</description>
81357 <description>Read pending status of interrupt for event TRIGGERED[12]</description>
81364 <description>Read: Not pending</description>
81369 <description>Read: Pending</description>
81376 <description>Read pending status of interrupt for event TRIGGERED[13]</description>
81383 <description>Read: Not pending</description>
81388 <description>Read: Pending</description>
81395 <description>Read pending status of interrupt for event TRIGGERED[14]</description>
81402 <description>Read: Not pending</description>
81407 <description>Read: Pending</description>
81414 <description>Read pending status of interrupt for event TRIGGERED[15]</description>
81421 <description>Read: Not pending</description>
81426 <description>Read: Pending</description>
81433 <description>Read pending status of interrupt for event TRIGGERED[16]</description>
81440 <description>Read: Not pending</description>
81445 <description>Read: Pending</description>
81452 <description>Read pending status of interrupt for event TRIGGERED[17]</description>
81459 <description>Read: Not pending</description>
81464 <description>Read: Pending</description>
81471 <description>Read pending status of interrupt for event TRIGGERED[18]</description>
81478 <description>Read: Not pending</description>
81483 <description>Read: Pending</description>
81490 <description>Read pending status of interrupt for event TRIGGERED[19]</description>
81497 <description>Read: Not pending</description>
81502 <description>Read: Pending</description>
81509 <description>Read pending status of interrupt for event TRIGGERED[20]</description>
81516 <description>Read: Not pending</description>
81521 <description>Read: Pending</description>
81528 <description>Read pending status of interrupt for event TRIGGERED[21]</description>
81535 <description>Read: Not pending</description>
81540 <description>Read: Pending</description>
81547 <description>Read pending status of interrupt for event TRIGGERED[22]</description>
81554 <description>Read: Not pending</description>
81559 <description>Read: Pending</description>
81566 <description>Read pending status of interrupt for event TRIGGERED[23]</description>
81573 <description>Read: Not pending</description>
81578 <description>Read: Pending</description>
81585 <description>Read pending status of interrupt for event TRIGGERED[24]</description>
81592 <description>Read: Not pending</description>
81597 <description>Read: Pending</description>
81604 <description>Read pending status of interrupt for event TRIGGERED[25]</description>
81611 <description>Read: Not pending</description>
81616 <description>Read: Pending</description>
81623 <description>Read pending status of interrupt for event TRIGGERED[26]</description>
81630 <description>Read: Not pending</description>
81635 <description>Read: Pending</description>
81642 <description>Read pending status of interrupt for event TRIGGERED[27]</description>
81649 <description>Read: Not pending</description>
81654 <description>Read: Pending</description>
81661 <description>Read pending status of interrupt for event TRIGGERED[28]</description>
81668 <description>Read: Not pending</description>
81673 <description>Read: Pending</description>
81680 <description>Read pending status of interrupt for event TRIGGERED[29]</description>
81687 <description>Read: Not pending</description>
81692 <description>Read: Pending</description>
81699 <description>Read pending status of interrupt for event TRIGGERED[30]</description>
81706 <description>Read: Not pending</description>
81711 <description>Read: Pending</description>
81718 <description>Read pending status of interrupt for event TRIGGERED[31]</description>
81725 <description>Read: Not pending</description>
81730 <description>Read: Pending</description>
81739 <description>Unspecified</description>
81745 <description>Abstract Data 0. Read/write data for argument 0</description>
81753 <description>Abstract Data 0</description>
81761 <description>Abstract Data 1. Read/write data for argument 1</description>
81769 <description>Abstract Data 1</description>
81777 <description>Debug Module Control</description>
81785 <description>Reset signal for the debug module.</description>
81791 <description>Reset the debug module itself</description>
81796 <description>Normal operation</description>
81803 <description>Reset signal output from the debug module to the system.</description>
81809 <description>Reset inactive</description>
81814 <description>Reset active</description>
81821 <description>Clear the halt on reset request.</description>
81828 <description>No operation when written 0.</description>
81833 <description>Clears the halt on reset request</description>
81840 <description>Set the halt on reset request.</description>
81847 <description>No operation when written 0.</description>
81852 <description>Sets the halt on reset request</description>
81859 <description>The high 10 bits of hartsel.</description>
81866 <description>The low 10 bits of hartsel.</description>
81873 <description>Definition of currently selected harts.</description>
81880 <description>Single hart selected.</description>
81885 <description>Multiple harts selected</description>
81892 <description>Clear the havereset.</description>
81899 <description>No operation when written 0.</description>
81904 <description>Clears the havereset for selected harts.</description>
81911 <description>Reset harts.</description>
81917 <description>Reset de-asserted.</description>
81922 <description>Reset asserted.</description>
81929 <description>Resume currently selected harts.</description>
81936 <description>No operation when written 0.</description>
81941 <description>Currently selected harts resumed.</description>
81948 <description>Halt currently selected harts.</description>
81955 … <description>Clears halt request bit for all currently selected harts.</description>
81960 <description>Currently selected harts halted.</description>
81969 <description>Debug Module Status</description>
81977 <description>Version of the debug module.</description>
81983 <description>Debug module not present.</description>
81988 …<description>There is a Debug Module and it conforms to version 0.11 of this specifcation.</descri…
81993 …<description>There is a Debug Module and it conforms to version 0.13 of this specifcation.</descri…
81998 …<description>There is a Debug Module but it does not conform to any available version of the spec.…
82005 <description>Configuration string.</description>
82011 …<description>The confstrptr0..confstrptr3 holds information which is not relevant to the configura…
82016 …<description>The confstrptr0..confstrptr3 holds the address of the configuration string.</descript…
82023 <description>Halt-on-reset support status.</description>
82029 <description>Halt-on-reset is supported.</description>
82034 <description>Halt-on-reset is not supported.</description>
82041 <description>Authentication busy status.</description>
82047 <description>The authentication module is ready.</description>
82052 <description>The authentication module is busy.</description>
82059 <description>Authentication status.</description>
82065 … <description>Authentication required before using the debug module.</description>
82070 <description>Authentication passed.</description>
82077 <description>Any currently selected harts halted status.</description>
82083 <description>None of the currently selected harts halted.</description>
82088 <description>Any of the currently selected harts halted.</description>
82095 <description>All currently selected harts halted status.</description>
82101 <description>Not all of the currently selected harts halted.</description>
82106 <description>All of the currently selected harts halted.</description>
82113 <description>Any currently selected harts running status.</description>
82119 <description>None of the currently selected harts running.</description>
82124 <description>Any of the currently selected harts running.</description>
82131 <description>All currently selected harts running status.</description>
82137 <description>Not all of the currently selected harts running.</description>
82142 <description>All of the currently selected harts running.</description>
82149 <description>Any currently selected harts unavailable status.</description>
82155 <description>None of the currently selected harts unavailable.</description>
82160 <description>Any of the currently selected harts unavailable.</description>
82167 <description>All currently selected harts unavailable status.</description>
82173 <description>Not all of the currently selected harts unavailable.</description>
82178 <description>All of the currently selected harts unavailable.</description>
82185 <description>Any currently selected harts nonexistent status.</description>
82191 <description>None of the currently selected harts nonexistent.</description>
82196 <description>Any of the currently selected harts nonexistent.</description>
82203 <description>All currently selected harts nonexistent status.</description>
82209 <description>Not all of the currently selected harts nonexistent.</description>
82214 <description>All of the currently selected harts nonexistent.</description>
82221 … <description>Any currently selected harts acknowledged last resume request.</description>
82227 … <description>None of the currently selected harts acknowledged last resume request.</description>
82232 … <description>Any of the currently selected harts acknowledged last resume request.</description>
82239 <description>All currently selected harts acknowledged last resume</description>
82245 …<description>Not all of the currently selected harts acknowledged last resume request.</descriptio…
82250 … <description>All of the currently selected harts acknowledged last resume request.</description>
82257 …<description>Any currently selected harts have been reset and reset is not acknowledged.</descript…
82263 …<description>None of the currently selected harts have been reset and reset is not acknowledget.</…
82268 …<description>Any of the currently selected harts have been reset and reset is not acknowledge.</de…
82275 …<description>All currently selected harts have been reset and reset is not acknowledge</descriptio…
82281 …<description>Not all of the currently selected harts have been reset and reset is not acknowledge.…
82286 …<description>All of the currently selected harts have been reset and reset is not acknowledge.</de…
82293 …<description>Implicit ebreak instruction at the non-existent word immediately after the Program Bu…
82299 <description>No implicit ebreak instruction.</description>
82304 <description>Implicit ebreak instruction.</description>
82313 <description>Hart Information</description>
82321 <description>Data Address</description>
82328 <description>Data Size</description>
82335 <description>Data Access</description>
82342 <description>The data registers are shadowed in the hart
82344 corresponds to a single argument.</description>
82349 <description>The data registers are shadowed in the hart's
82351 the memory map.</description>
82358 <description>Number of dscratch registers</description>
82367 <description>Halt Summary 1</description>
82375 <description>Halt Summary 1</description>
82384 <description>Hart Array Window Select</description>
82392 …<description>The high bits of this field may be tied to 0, depending on how large the array mask r…
82393 … E.g. on a system with 48 harts only bit 0 of this field may actually be writable.</description>
82402 <description>Hart Array Window</description>
82410 <description>Mask data.</description>
82418 <description>Abstract Control and Status</description>
82426 …<description>Number of data registers that are implemented as part of the abstract command interfa…
82433 <description>Command error when the abstract command fails.</description>
82439 <description>No error.</description>
82444 <description>An abstract command was executing while command,
82446 or written. This status is only written if cmderr contains 0</description>
82451 <description>The requested command is notsupported,
82452 regardless of whether the hart is running or not.</description>
82457 <description>An exception occurred while executing the
82458 command (e.g. while executing theProgram Buffer).</description>
82463 <description>The abstract command couldn't execute
82464 … because the hart wasn't in the required state (running/halted). or unavailable.</description>
82469 <description>The abstract command failed due to abus
82470 error (e.g. alignment, access size, or timeout).</description>
82475 <description>The command failed for another reason.</description>
82482 <description>Abstract command execution status.</description>
82489 <description>Not busy.</description>
82494 <description>An abstract command is currently being executed.
82495 …t as soon as command is written, and is not cleared until that command has completed.</description>
82502 … <description>Size of the Program Buffer, in 32-bit words. Valid sizes are 0 - 1.</description>
82511 <description>Abstract command</description>
82519 …<description>This Field is interpreted in a command specific manner, described for each abstract c…
82525 … <description>The type determines the overall functionality of this abstract command.</description>
82531 <description>Register Access Command</description>
82536 <description>Quick Access Command</description>
82541 <description>Memory Access Command</description>
82550 <description>Abstract Command Autoexec</description>
82558 …<description>When a bit in this field is 1, read or write accesses to the corresponding data word …
82559 command in command to be executed again.</description>
82566 …<description>When a bit in this field is 1, read or write accesses to the corresponding progbuf wo…
82567 the command in command to be executed again.</description>
82578 <description>Description collection: Configuration String Pointer [n]</description>
82586 <description>Address</description>
82595 <description>Next Debug Module</description>
82603 <description>Address</description>
82614 <description>Description collection: Program Buffer [n]</description>
82622 <description>Data</description>
82631 <description>Authentication Data</description>
82639 <description>Data</description>
82648 <description>Halt Summary 2</description>
82656 <description>Halt Summary 2</description>
82665 <description>Halt Summary 3</description>
82673 <description>Halt Summary 3</description>
82682 <description>System Bus Addres 127:96</description>
82690 <description>Accesses bits 127:96 of the physical address in
82692 wide).</description>
82701 <description>System Bus Access Control and Status</description>
82715 <description>8-bit system bus accesses are supported.</description>
82728 <description>16-bit system bus accesses are supported.</description>
82741 <description>32-bit system bus accesses are supported.</description>
82754 <description>64-bit system bus accesses are supported.</description>
82767 <description>128-bit system bus accesses are supported.</description>
82774 …<description>Width of system bus addresses in bits. (0 indicates there is no bus access support.)<…
82787 <description>There was no bus error.</description>
82792 <description>There was a timeout.</description>
82797 <description>A bad address was accessed.</description>
82802 <description>There was an alignment error.</description>
82807 <description>An access of unsupported size was requested.</description>
82812 <description>Other.</description>
82825 <description>Every read from sbdata0 automatically
82826 triggers a system bus read at the (possibly autoincremented) address.</description>
82839 <description>sbaddress is incremented by the access
82840 size (in bytes) selected in sbaccess after every system bus access.</description>
82853 <description>8-bit.</description>
82858 <description>16-bit.</description>
82863 <description>32-bit.</description>
82868 <description>64-bit.</description>
82873 <description>128-bit.</description>
82886 <description>Every write to sbaddress0 automatically
82887 triggers a system bus read at the new address.</description>
82900 <description>System bus master is not busy.</description>
82905 <description>System bus master is busy.</description>
82918 <description>No error.</description>
82923 <description>Debugger access attempted while one in progress.</description>
82936 <description>The System Bus interface conforms to mainline
82937 … drafts of thia RISC-V External Debug Support spec older than 1 January, 2018.</description>
82942 …<description>The System Bus interface conforms to RISC-V External Debug Support version 0.14.0-DRA…
82943 Other values are reserved for future versions.</description>
82952 <description>System Bus Addres 31:0</description>
82960 <description>Accesses bits 31:0 of the physical address in
82961 sbaddress.</description>
82970 <description>System Bus Addres 63:32</description>
82978 <description>Accesses bits 63:32 of the physical address in
82980 wide).</description>
82989 <description>System Bus Addres 95:64</description>
82997 <description>Accesses bits 95:64 of the physical address in
82999 wide).</description>
83008 <description>System Bus Data 31:0</description>
83016 <description>Accesses bits 31:0 of sbdata</description>
83025 <description>System Bus Data 63:32</description>
83033 <description>Accesses bits 63:32 of sbdata (if the system bus
83034 is that wide).</description>
83043 <description>System Bus Data 95:64</description>
83051 <description>Accesses bits 95:64 of sbdata (if the system bus
83052 is that wide).</description>
83061 <description>System Bus Data 127:96</description>
83069 <description>Accesses bits 127:96 of sbdata (if the system bus
83070 is that wide).</description>
83079 <description>Halt summary 0</description>
83087 <description>Halt summary 0</description>
83097 <description>State of the CPU after a core reset</description>
83105 <description>Controls CPU running state after a core reset.</description>
83111 …<description>CPU stopped. If this is the CPU state after a core reset, setting this bit will chang…
83116 …description>CPU running. If this is the CPU state after a core reset, clearing this bit will chang…
83125 <description>Initial value of the PC at CPU start.</description>
83133 <description>Initial value of the PC at CPU start.</description>
83143 <description>Controller Area Network</description>
83162 <description>Start the CAN peripheral.</description>
83170 <description>Start the CAN peripheral.</description>
83176 <description>Trigger task</description>
83185 <description>Request to stop the CAN peripheral</description>
83193 <description>Request to stop the CAN peripheral</description>
83199 <description>Trigger task</description>
83208 <description>Stop the CAN peripheral</description>
83216 <description>Stop the CAN peripheral</description>
83222 <description>Trigger task</description>
83233 …<description>Description collection: Event indicating that interrupt n triggered at CAN core</desc…
83241 <description>Event indicating that interrupt n triggered at CAN core</description>
83247 <description>Event not generated</description>
83252 <description>Event generated</description>
83261 <description>Event indicating that interrupt triggered at CAN DMU</description>
83269 <description>Event indicating that interrupt triggered at CAN DMU</description>
83275 <description>Event not generated</description>
83280 <description>Event generated</description>
83289 <description>Event indicating that interrupt triggered at CAN DMA</description>
83297 <description>Event indicating that interrupt triggered at CAN DMA</description>
83303 <description>Event not generated</description>
83308 <description>Event generated</description>
83317 <description>Event indicating that the CAN is ready to be stopped</description>
83325 <description>Event indicating that the CAN is ready to be stopped</description>
83331 <description>Event not generated</description>
83336 <description>Event generated</description>
83345 <description>Shortcuts between local events and tasks</description>
83353 <description>Shortcut between event READYFORSTOP and task STOP</description>
83359 <description>Disable shortcut</description>
83364 <description>Enable shortcut</description>
83373 <description>Enable or disable interrupt</description>
83381 <description>Enable or disable interrupt for event CORE[0]</description>
83387 <description>Disable</description>
83392 <description>Enable</description>
83399 <description>Enable or disable interrupt for event CORE[1]</description>
83405 <description>Disable</description>
83410 <description>Enable</description>
83417 <description>Enable or disable interrupt for event DMU</description>
83423 <description>Disable</description>
83428 <description>Enable</description>
83435 <description>Enable or disable interrupt for event DMA</description>
83441 <description>Disable</description>
83446 <description>Enable</description>
83453 <description>Enable or disable interrupt for event READYFORSTOP</description>
83459 <description>Disable</description>
83464 <description>Enable</description>
83473 <description>Enable interrupt</description>
83481 <description>Write '1' to enable interrupt for event CORE[0]</description>
83488 <description>Read: Disabled</description>
83493 <description>Read: Enabled</description>
83501 <description>Enable</description>
83508 <description>Write '1' to enable interrupt for event CORE[1]</description>
83515 <description>Read: Disabled</description>
83520 <description>Read: Enabled</description>
83528 <description>Enable</description>
83535 <description>Write '1' to enable interrupt for event DMU</description>
83542 <description>Read: Disabled</description>
83547 <description>Read: Enabled</description>
83555 <description>Enable</description>
83562 <description>Write '1' to enable interrupt for event DMA</description>
83569 <description>Read: Disabled</description>
83574 <description>Read: Enabled</description>
83582 <description>Enable</description>
83589 <description>Write '1' to enable interrupt for event READYFORSTOP</description>
83596 <description>Read: Disabled</description>
83601 <description>Read: Enabled</description>
83609 <description>Enable</description>
83618 <description>Disable interrupt</description>
83626 <description>Write '1' to disable interrupt for event CORE[0]</description>
83633 <description>Read: Disabled</description>
83638 <description>Read: Enabled</description>
83646 <description>Disable</description>
83653 <description>Write '1' to disable interrupt for event CORE[1]</description>
83660 <description>Read: Disabled</description>
83665 <description>Read: Enabled</description>
83673 <description>Disable</description>
83680 <description>Write '1' to disable interrupt for event DMU</description>
83687 <description>Read: Disabled</description>
83692 <description>Read: Enabled</description>
83700 <description>Disable</description>
83707 <description>Write '1' to disable interrupt for event DMA</description>
83714 <description>Read: Disabled</description>
83719 <description>Read: Enabled</description>
83727 <description>Disable</description>
83734 <description>Write '1' to disable interrupt for event READYFORSTOP</description>
83741 <description>Read: Disabled</description>
83746 <description>Read: Enabled</description>
83754 <description>Disable</description>
83763 <description>Pending interrupts</description>
83771 <description>Read pending status of interrupt for event CORE[0]</description>
83778 <description>Read: Not pending</description>
83783 <description>Read: Pending</description>
83790 <description>Read pending status of interrupt for event CORE[1]</description>
83797 <description>Read: Not pending</description>
83802 <description>Read: Pending</description>
83809 <description>Read pending status of interrupt for event DMU</description>
83816 <description>Read: Not pending</description>
83821 <description>Read: Pending</description>
83828 <description>Read pending status of interrupt for event DMA</description>
83835 <description>Read: Not pending</description>
83840 <description>Read: Pending</description>
83847 <description>Read pending status of interrupt for event READYFORSTOP</description>
83854 <description>Read: Not pending</description>
83859 <description>Read: Pending</description>
83870 …description>MVDMA performs direct-memory-accesses between memories. Data is transferred according …
83889 <description>Pause operation.</description>
83897 <description>Pause operation.</description>
83903 <description>Trigger task</description>
83912 <description>Reset operation.</description>
83920 <description>Reset operation.</description>
83926 <description>Trigger task</description>
83937 …<description>Description collection: Start operation of job list n. Base address for successive TA…
83945 …<description>Start operation of job list n. Base address for successive TASKS_STARTs.</description>
83951 <description>Trigger task</description>
83962 … <description>Description collection: Subscribe configuration for task START[n]</description>
83970 <description>DPPI channel that task START[n] will subscribe to</description>
83981 <description>Disable subscription</description>
83986 <description>Enable subscription</description>
83995 … <description>Event indicating that Sink data descriptor list has been completed.</description>
84003 … <description>Event indicating that Sink data descriptor list has been completed.</description>
84009 <description>Event not generated</description>
84014 <description>Event generated</description>
84023 <description>Event indicating that the source list processing has started.</description>
84031 … <description>Event indicating that the source list processing has started.</description>
84037 <description>Event not generated</description>
84042 <description>Event generated</description>
84051 <description>Event indicating that the data transfer has been paused.</description>
84059 <description>Event indicating that the data transfer has been paused.</description>
84065 <description>Event not generated</description>
84070 <description>Event generated</description>
84079 <description>Event indicating that the peripheral has been reset.</description>
84087 <description>Event indicating that the peripheral has been reset.</description>
84093 <description>Event not generated</description>
84098 <description>Event generated</description>
84107 <description>Peripheral events.</description>
84113 …<description>Event indicating that a bus error has been received on the Source channel.</descripti…
84121 …<description>Event indicating that a bus error has been received on the Source channel.</descripti…
84127 <description>Event not generated</description>
84132 <description>Event generated</description>
84141 …<description>Event indicating that a job on the Source channel with EVENT_ENABLE active has been p…
84149 …<description>Event indicating that a job on the Source channel with EVENT_ENABLE active has been p…
84155 <description>Event not generated</description>
84160 <description>Event generated</description>
84170 <description>Peripheral events.</description>
84176 …<description>Event indicating that a bus error has been received on the Sink channel.</description>
84184 …<description>Event indicating that a bus error has been received on the Sink channel.</description>
84190 <description>Event not generated</description>
84195 <description>Event generated</description>
84204 …<description>Event indicating that a job on the Sink channel with EVENT_ENABLE active has been pro…
84212 …<description>Event indicating that a job on the Sink channel with EVENT_ENABLE active has been pro…
84218 <description>Event not generated</description>
84223 <description>Event generated</description>
84235 …description>Description collection: Event indicating that the operation started by the task START[…
84243 …description>Event indicating that the operation started by the task START[n] has been completed. B…
84249 <description>Event not generated</description>
84254 <description>Event generated</description>
84263 <description>Publish configuration for event END</description>
84271 <description>DPPI channel that event END will publish to</description>
84282 <description>Disable publishing</description>
84287 <description>Enable publishing</description>
84296 <description>Publish configuration for events</description>
84302 <description>Publish configuration for event SOURCE.SELECTJOBDONE</description>
84310 … <description>DPPI channel that event SOURCE.SELECTJOBDONE will publish to</description>
84321 <description>Disable publishing</description>
84326 <description>Enable publishing</description>
84336 <description>Publish configuration for events</description>
84342 <description>Publish configuration for event SINK.SELECTJOBDONE</description>
84350 … <description>DPPI channel that event SINK.SELECTJOBDONE will publish to</description>
84361 <description>Disable publishing</description>
84366 <description>Enable publishing</description>
84378 … <description>Description collection: Publish configuration for event COMPLETED[n]</description>
84386 <description>DPPI channel that event COMPLETED[n] will publish to</description>
84397 <description>Disable publishing</description>
84402 <description>Enable publishing</description>
84411 <description>Enable or disable interrupt</description>
84419 <description>Enable or disable interrupt for event END</description>
84425 <description>Disable</description>
84430 <description>Enable</description>
84437 <description>Enable or disable interrupt for event STARTED</description>
84443 <description>Disable</description>
84448 <description>Enable</description>
84455 <description>Enable or disable interrupt for event PAUSED</description>
84461 <description>Disable</description>
84466 <description>Enable</description>
84473 <description>Enable or disable interrupt for event RESET</description>
84479 <description>Disable</description>
84484 <description>Enable</description>
84491 <description>Enable or disable interrupt for event SOURCEBUSERROR</description>
84497 <description>Disable</description>
84502 <description>Enable</description>
84509 <description>Enable or disable interrupt for event SOURCESELECTJOBDONE</description>
84515 <description>Disable</description>
84520 <description>Enable</description>
84527 <description>Enable or disable interrupt for event SINKBUSERROR</description>
84533 <description>Disable</description>
84538 <description>Enable</description>
84545 <description>Enable or disable interrupt for event SINKSELECTJOBDONE</description>
84551 <description>Disable</description>
84556 <description>Enable</description>
84563 <description>Enable or disable interrupt for event COMPLETED[0]</description>
84569 <description>Disable</description>
84574 <description>Enable</description>
84581 <description>Enable or disable interrupt for event COMPLETED[1]</description>
84587 <description>Disable</description>
84592 <description>Enable</description>
84599 <description>Enable or disable interrupt for event COMPLETED[2]</description>
84605 <description>Disable</description>
84610 <description>Enable</description>
84617 <description>Enable or disable interrupt for event COMPLETED[3]</description>
84623 <description>Disable</description>
84628 <description>Enable</description>
84635 <description>Enable or disable interrupt for event COMPLETED[4]</description>
84641 <description>Disable</description>
84646 <description>Enable</description>
84653 <description>Enable or disable interrupt for event COMPLETED[5]</description>
84659 <description>Disable</description>
84664 <description>Enable</description>
84671 <description>Enable or disable interrupt for event COMPLETED[6]</description>
84677 <description>Disable</description>
84682 <description>Enable</description>
84689 <description>Enable or disable interrupt for event COMPLETED[7]</description>
84695 <description>Disable</description>
84700 <description>Enable</description>
84709 <description>Enable interrupt</description>
84717 <description>Write '1' to enable interrupt for event END</description>
84724 <description>Read: Disabled</description>
84729 <description>Read: Enabled</description>
84737 <description>Enable</description>
84744 <description>Write '1' to enable interrupt for event STARTED</description>
84751 <description>Read: Disabled</description>
84756 <description>Read: Enabled</description>
84764 <description>Enable</description>
84771 <description>Write '1' to enable interrupt for event PAUSED</description>
84778 <description>Read: Disabled</description>
84783 <description>Read: Enabled</description>
84791 <description>Enable</description>
84798 <description>Write '1' to enable interrupt for event RESET</description>
84805 <description>Read: Disabled</description>
84810 <description>Read: Enabled</description>
84818 <description>Enable</description>
84825 <description>Write '1' to enable interrupt for event SOURCEBUSERROR</description>
84832 <description>Read: Disabled</description>
84837 <description>Read: Enabled</description>
84845 <description>Enable</description>
84852 <description>Write '1' to enable interrupt for event SOURCESELECTJOBDONE</description>
84859 <description>Read: Disabled</description>
84864 <description>Read: Enabled</description>
84872 <description>Enable</description>
84879 <description>Write '1' to enable interrupt for event SINKBUSERROR</description>
84886 <description>Read: Disabled</description>
84891 <description>Read: Enabled</description>
84899 <description>Enable</description>
84906 <description>Write '1' to enable interrupt for event SINKSELECTJOBDONE</description>
84913 <description>Read: Disabled</description>
84918 <description>Read: Enabled</description>
84926 <description>Enable</description>
84933 <description>Write '1' to enable interrupt for event COMPLETED[0]</description>
84940 <description>Read: Disabled</description>
84945 <description>Read: Enabled</description>
84953 <description>Enable</description>
84960 <description>Write '1' to enable interrupt for event COMPLETED[1]</description>
84967 <description>Read: Disabled</description>
84972 <description>Read: Enabled</description>
84980 <description>Enable</description>
84987 <description>Write '1' to enable interrupt for event COMPLETED[2]</description>
84994 <description>Read: Disabled</description>
84999 <description>Read: Enabled</description>
85007 <description>Enable</description>
85014 <description>Write '1' to enable interrupt for event COMPLETED[3]</description>
85021 <description>Read: Disabled</description>
85026 <description>Read: Enabled</description>
85034 <description>Enable</description>
85041 <description>Write '1' to enable interrupt for event COMPLETED[4]</description>
85048 <description>Read: Disabled</description>
85053 <description>Read: Enabled</description>
85061 <description>Enable</description>
85068 <description>Write '1' to enable interrupt for event COMPLETED[5]</description>
85075 <description>Read: Disabled</description>
85080 <description>Read: Enabled</description>
85088 <description>Enable</description>
85095 <description>Write '1' to enable interrupt for event COMPLETED[6]</description>
85102 <description>Read: Disabled</description>
85107 <description>Read: Enabled</description>
85115 <description>Enable</description>
85122 <description>Write '1' to enable interrupt for event COMPLETED[7]</description>
85129 <description>Read: Disabled</description>
85134 <description>Read: Enabled</description>
85142 <description>Enable</description>
85151 <description>Disable interrupt</description>
85159 <description>Write '1' to disable interrupt for event END</description>
85166 <description>Read: Disabled</description>
85171 <description>Read: Enabled</description>
85179 <description>Disable</description>
85186 <description>Write '1' to disable interrupt for event STARTED</description>
85193 <description>Read: Disabled</description>
85198 <description>Read: Enabled</description>
85206 <description>Disable</description>
85213 <description>Write '1' to disable interrupt for event PAUSED</description>
85220 <description>Read: Disabled</description>
85225 <description>Read: Enabled</description>
85233 <description>Disable</description>
85240 <description>Write '1' to disable interrupt for event RESET</description>
85247 <description>Read: Disabled</description>
85252 <description>Read: Enabled</description>
85260 <description>Disable</description>
85267 <description>Write '1' to disable interrupt for event SOURCEBUSERROR</description>
85274 <description>Read: Disabled</description>
85279 <description>Read: Enabled</description>
85287 <description>Disable</description>
85294 … <description>Write '1' to disable interrupt for event SOURCESELECTJOBDONE</description>
85301 <description>Read: Disabled</description>
85306 <description>Read: Enabled</description>
85314 <description>Disable</description>
85321 <description>Write '1' to disable interrupt for event SINKBUSERROR</description>
85328 <description>Read: Disabled</description>
85333 <description>Read: Enabled</description>
85341 <description>Disable</description>
85348 <description>Write '1' to disable interrupt for event SINKSELECTJOBDONE</description>
85355 <description>Read: Disabled</description>
85360 <description>Read: Enabled</description>
85368 <description>Disable</description>
85375 <description>Write '1' to disable interrupt for event COMPLETED[0]</description>
85382 <description>Read: Disabled</description>
85387 <description>Read: Enabled</description>
85395 <description>Disable</description>
85402 <description>Write '1' to disable interrupt for event COMPLETED[1]</description>
85409 <description>Read: Disabled</description>
85414 <description>Read: Enabled</description>
85422 <description>Disable</description>
85429 <description>Write '1' to disable interrupt for event COMPLETED[2]</description>
85436 <description>Read: Disabled</description>
85441 <description>Read: Enabled</description>
85449 <description>Disable</description>
85456 <description>Write '1' to disable interrupt for event COMPLETED[3]</description>
85463 <description>Read: Disabled</description>
85468 <description>Read: Enabled</description>
85476 <description>Disable</description>
85483 <description>Write '1' to disable interrupt for event COMPLETED[4]</description>
85490 <description>Read: Disabled</description>
85495 <description>Read: Enabled</description>
85503 <description>Disable</description>
85510 <description>Write '1' to disable interrupt for event COMPLETED[5]</description>
85517 <description>Read: Disabled</description>
85522 <description>Read: Enabled</description>
85530 <description>Disable</description>
85537 <description>Write '1' to disable interrupt for event COMPLETED[6]</description>
85544 <description>Read: Disabled</description>
85549 <description>Read: Enabled</description>
85557 <description>Disable</description>
85564 <description>Write '1' to disable interrupt for event COMPLETED[7]</description>
85571 <description>Read: Disabled</description>
85576 <description>Read: Enabled</description>
85584 <description>Disable</description>
85593 <description>Pending interrupts</description>
85601 <description>Read pending status of interrupt for event END</description>
85608 <description>Read: Not pending</description>
85613 <description>Read: Pending</description>
85620 <description>Read pending status of interrupt for event STARTED</description>
85627 <description>Read: Not pending</description>
85632 <description>Read: Pending</description>
85639 <description>Read pending status of interrupt for event PAUSED</description>
85646 <description>Read: Not pending</description>
85651 <description>Read: Pending</description>
85658 <description>Read pending status of interrupt for event RESET</description>
85665 <description>Read: Not pending</description>
85670 <description>Read: Pending</description>
85677 <description>Read pending status of interrupt for event SOURCEBUSERROR</description>
85684 <description>Read: Not pending</description>
85689 <description>Read: Pending</description>
85696 … <description>Read pending status of interrupt for event SOURCESELECTJOBDONE</description>
85703 <description>Read: Not pending</description>
85708 <description>Read: Pending</description>
85715 <description>Read pending status of interrupt for event SINKBUSERROR</description>
85722 <description>Read: Not pending</description>
85727 <description>Read: Pending</description>
85734 … <description>Read pending status of interrupt for event SINKSELECTJOBDONE</description>
85741 <description>Read: Not pending</description>
85746 <description>Read: Pending</description>
85753 <description>Read pending status of interrupt for event COMPLETED[0]</description>
85760 <description>Read: Not pending</description>
85765 <description>Read: Pending</description>
85772 <description>Read pending status of interrupt for event COMPLETED[1]</description>
85779 <description>Read: Not pending</description>
85784 <description>Read: Pending</description>
85791 <description>Read pending status of interrupt for event COMPLETED[2]</description>
85798 <description>Read: Not pending</description>
85803 <description>Read: Pending</description>
85810 <description>Read pending status of interrupt for event COMPLETED[3]</description>
85817 <description>Read: Not pending</description>
85822 <description>Read: Pending</description>
85829 <description>Read pending status of interrupt for event COMPLETED[4]</description>
85836 <description>Read: Not pending</description>
85841 <description>Read: Pending</description>
85848 <description>Read pending status of interrupt for event COMPLETED[5]</description>
85855 <description>Read: Not pending</description>
85860 <description>Read: Pending</description>
85867 <description>Read pending status of interrupt for event COMPLETED[6]</description>
85874 <description>Read: Not pending</description>
85879 <description>Read: Pending</description>
85886 <description>Read pending status of interrupt for event COMPLETED[7]</description>
85893 <description>Read: Not pending</description>
85898 <description>Read: Pending</description>
85907 <description>MVDMA status registers.</description>
85913 <description>CRC checksum calculation result</description>
85921 <description>Result</description>
85929 …<description>Status of intermediate fifo: empty, not empty and full information available.</descri…
85937 <description>Result</description>
85943 <description>Fifo is empty.</description>
85948 <description>Fifo contains data.</description>
85953 <description>Fifo is full.</description>
85962 <description>Status of DMA transfer.</description>
85970 <description>DMA activity</description>
85976 <description>DMA is in IDLE state.</description>
85981 <description>Data being transferred.</description>
85991 <description>MVDMA configuration registers.</description>
85997 <description>Configure MVDMA mode of operation.</description>
86010 …<description>Registers SOURCE.LISTPTR and SINK.LISTPTR contain start address of a single job list.…
86015 …<description>Registers SOURCE.LISTPTR and SINK.LISTPTR contain start address of a list of job list…
86025 <description>Source channel configuration and status.</description>
86031 …<description>Start address of Source job list or list of job list pointers, depending on value of …
86039 <description>Source job descriptor list address.</description>
86047 <description>Source bus error status.</description>
86055 <description>Bus error type</description>
86061 <description>There are no errors.</description>
86066 …<description>Error related to memory when reading joblist, or error related to memory/register whe…
86071 …<description>Error related to the joblist address when reading joblist, or error related to addres…
86080 …description>Latest address being accessed on the Source channel.If a bus error occurs, these regis…
86088 <description>Source address</description>
86096 …<description>Number of completed jobs in the current Source descriptor list. This resets to 0 when…
86104 <description>Source job count</description>
86113 <description>Sink channel configuration and status.</description>
86119 …<description>Start address of Sink job list or list of job list pointers, depending on value of CO…
86127 <description>Sink descriptor list address.</description>
86135 <description>Sink bus error status.</description>
86143 <description>Bus error type</description>
86149 <description>There are no errors.</description>
86154 <description>Error related to memory when reading joblist.</description>
86159 … <description>Error related to the joblist address when reading joblist.</description>
86164 <description>Error related to memory/register when writing data.</description>
86169 … <description>Error related to the memory/register address when writing data.</description>
86178 …description>Latest address being accessed on the Sink channel. If a bus error occurs, these regist…
86186 <description>Sink address</description>
86194 …<description>Number of completed jobs in the current Sink descriptor list. This resets to 0 when a…
86202 <description>Sink job count</description>
86213 <description>RAM Controller</description>
86228 <description>Waitstates for read operations.</description>
86236 <description>Number of waitstates for a read from the RAM.</description>
86246 <description>I3C 1</description>
86257 <description>Distributed programmable peripheral interconnect controller 0</description>
86275 <description>Channel group tasks</description>
86281 <description>Description cluster: Enable channel group n</description>
86289 <description>Enable channel group n</description>
86295 <description>Trigger task</description>
86304 <description>Description cluster: Disable channel group n</description>
86312 <description>Disable channel group n</description>
86318 <description>Trigger task</description>
86330 <description>Subscribe configuration for tasks</description>
86336 … <description>Description cluster: Subscribe configuration for task CHG[n].EN</description>
86344 <description>DPPI channel that task CHG[n].EN will subscribe to</description>
86355 <description>Disable subscription</description>
86360 <description>Enable subscription</description>
86369 … <description>Description cluster: Subscribe configuration for task CHG[n].DIS</description>
86377 <description>DPPI channel that task CHG[n].DIS will subscribe to</description>
86388 <description>Disable subscription</description>
86393 <description>Enable subscription</description>
86403 <description>Channel enable register</description>
86411 <description>Enable or disable channel 0</description>
86417 <description>Disable channel</description>
86422 <description>Enable channel</description>
86429 <description>Enable or disable channel 1</description>
86435 <description>Disable channel</description>
86440 <description>Enable channel</description>
86447 <description>Enable or disable channel 2</description>
86453 <description>Disable channel</description>
86458 <description>Enable channel</description>
86465 <description>Enable or disable channel 3</description>
86471 <description>Disable channel</description>
86476 <description>Enable channel</description>
86483 <description>Enable or disable channel 4</description>
86489 <description>Disable channel</description>
86494 <description>Enable channel</description>
86501 <description>Enable or disable channel 5</description>
86507 <description>Disable channel</description>
86512 <description>Enable channel</description>
86519 <description>Enable or disable channel 6</description>
86525 <description>Disable channel</description>
86530 <description>Enable channel</description>
86537 <description>Enable or disable channel 7</description>
86543 <description>Disable channel</description>
86548 <description>Enable channel</description>
86555 <description>Enable or disable channel 8</description>
86561 <description>Disable channel</description>
86566 <description>Enable channel</description>
86573 <description>Enable or disable channel 9</description>
86579 <description>Disable channel</description>
86584 <description>Enable channel</description>
86591 <description>Enable or disable channel 10</description>
86597 <description>Disable channel</description>
86602 <description>Enable channel</description>
86609 <description>Enable or disable channel 11</description>
86615 <description>Disable channel</description>
86620 <description>Enable channel</description>
86627 <description>Enable or disable channel 12</description>
86633 <description>Disable channel</description>
86638 <description>Enable channel</description>
86645 <description>Enable or disable channel 13</description>
86651 <description>Disable channel</description>
86656 <description>Enable channel</description>
86663 <description>Enable or disable channel 14</description>
86669 <description>Disable channel</description>
86674 <description>Enable channel</description>
86681 <description>Enable or disable channel 15</description>
86687 <description>Disable channel</description>
86692 <description>Enable channel</description>
86699 <description>Enable or disable channel 16</description>
86705 <description>Disable channel</description>
86710 <description>Enable channel</description>
86717 <description>Enable or disable channel 17</description>
86723 <description>Disable channel</description>
86728 <description>Enable channel</description>
86735 <description>Enable or disable channel 18</description>
86741 <description>Disable channel</description>
86746 <description>Enable channel</description>
86753 <description>Enable or disable channel 19</description>
86759 <description>Disable channel</description>
86764 <description>Enable channel</description>
86771 <description>Enable or disable channel 20</description>
86777 <description>Disable channel</description>
86782 <description>Enable channel</description>
86789 <description>Enable or disable channel 21</description>
86795 <description>Disable channel</description>
86800 <description>Enable channel</description>
86807 <description>Enable or disable channel 22</description>
86813 <description>Disable channel</description>
86818 <description>Enable channel</description>
86825 <description>Enable or disable channel 23</description>
86831 <description>Disable channel</description>
86836 <description>Enable channel</description>
86843 <description>Enable or disable channel 24</description>
86849 <description>Disable channel</description>
86854 <description>Enable channel</description>
86861 <description>Enable or disable channel 25</description>
86867 <description>Disable channel</description>
86872 <description>Enable channel</description>
86879 <description>Enable or disable channel 26</description>
86885 <description>Disable channel</description>
86890 <description>Enable channel</description>
86897 <description>Enable or disable channel 27</description>
86903 <description>Disable channel</description>
86908 <description>Enable channel</description>
86915 <description>Enable or disable channel 28</description>
86921 <description>Disable channel</description>
86926 <description>Enable channel</description>
86933 <description>Enable or disable channel 29</description>
86939 <description>Disable channel</description>
86944 <description>Enable channel</description>
86951 <description>Enable or disable channel 30</description>
86957 <description>Disable channel</description>
86962 <description>Enable channel</description>
86969 <description>Enable or disable channel 31</description>
86975 <description>Disable channel</description>
86980 <description>Enable channel</description>
86989 <description>Channel enable set register</description>
86998 <description>Channel 0 enable set register. Writing 0 has no effect.</description>
87005 <description>Read: Channel disabled</description>
87010 <description>Read: Channel enabled</description>
87018 <description>Write: Enable channel</description>
87025 <description>Channel 1 enable set register. Writing 0 has no effect.</description>
87032 <description>Read: Channel disabled</description>
87037 <description>Read: Channel enabled</description>
87045 <description>Write: Enable channel</description>
87052 <description>Channel 2 enable set register. Writing 0 has no effect.</description>
87059 <description>Read: Channel disabled</description>
87064 <description>Read: Channel enabled</description>
87072 <description>Write: Enable channel</description>
87079 <description>Channel 3 enable set register. Writing 0 has no effect.</description>
87086 <description>Read: Channel disabled</description>
87091 <description>Read: Channel enabled</description>
87099 <description>Write: Enable channel</description>
87106 <description>Channel 4 enable set register. Writing 0 has no effect.</description>
87113 <description>Read: Channel disabled</description>
87118 <description>Read: Channel enabled</description>
87126 <description>Write: Enable channel</description>
87133 <description>Channel 5 enable set register. Writing 0 has no effect.</description>
87140 <description>Read: Channel disabled</description>
87145 <description>Read: Channel enabled</description>
87153 <description>Write: Enable channel</description>
87160 <description>Channel 6 enable set register. Writing 0 has no effect.</description>
87167 <description>Read: Channel disabled</description>
87172 <description>Read: Channel enabled</description>
87180 <description>Write: Enable channel</description>
87187 <description>Channel 7 enable set register. Writing 0 has no effect.</description>
87194 <description>Read: Channel disabled</description>
87199 <description>Read: Channel enabled</description>
87207 <description>Write: Enable channel</description>
87214 <description>Channel 8 enable set register. Writing 0 has no effect.</description>
87221 <description>Read: Channel disabled</description>
87226 <description>Read: Channel enabled</description>
87234 <description>Write: Enable channel</description>
87241 <description>Channel 9 enable set register. Writing 0 has no effect.</description>
87248 <description>Read: Channel disabled</description>
87253 <description>Read: Channel enabled</description>
87261 <description>Write: Enable channel</description>
87268 <description>Channel 10 enable set register. Writing 0 has no effect.</description>
87275 <description>Read: Channel disabled</description>
87280 <description>Read: Channel enabled</description>
87288 <description>Write: Enable channel</description>
87295 <description>Channel 11 enable set register. Writing 0 has no effect.</description>
87302 <description>Read: Channel disabled</description>
87307 <description>Read: Channel enabled</description>
87315 <description>Write: Enable channel</description>
87322 <description>Channel 12 enable set register. Writing 0 has no effect.</description>
87329 <description>Read: Channel disabled</description>
87334 <description>Read: Channel enabled</description>
87342 <description>Write: Enable channel</description>
87349 <description>Channel 13 enable set register. Writing 0 has no effect.</description>
87356 <description>Read: Channel disabled</description>
87361 <description>Read: Channel enabled</description>
87369 <description>Write: Enable channel</description>
87376 <description>Channel 14 enable set register. Writing 0 has no effect.</description>
87383 <description>Read: Channel disabled</description>
87388 <description>Read: Channel enabled</description>
87396 <description>Write: Enable channel</description>
87403 <description>Channel 15 enable set register. Writing 0 has no effect.</description>
87410 <description>Read: Channel disabled</description>
87415 <description>Read: Channel enabled</description>
87423 <description>Write: Enable channel</description>
87430 <description>Channel 16 enable set register. Writing 0 has no effect.</description>
87437 <description>Read: Channel disabled</description>
87442 <description>Read: Channel enabled</description>
87450 <description>Write: Enable channel</description>
87457 <description>Channel 17 enable set register. Writing 0 has no effect.</description>
87464 <description>Read: Channel disabled</description>
87469 <description>Read: Channel enabled</description>
87477 <description>Write: Enable channel</description>
87484 <description>Channel 18 enable set register. Writing 0 has no effect.</description>
87491 <description>Read: Channel disabled</description>
87496 <description>Read: Channel enabled</description>
87504 <description>Write: Enable channel</description>
87511 <description>Channel 19 enable set register. Writing 0 has no effect.</description>
87518 <description>Read: Channel disabled</description>
87523 <description>Read: Channel enabled</description>
87531 <description>Write: Enable channel</description>
87538 <description>Channel 20 enable set register. Writing 0 has no effect.</description>
87545 <description>Read: Channel disabled</description>
87550 <description>Read: Channel enabled</description>
87558 <description>Write: Enable channel</description>
87565 <description>Channel 21 enable set register. Writing 0 has no effect.</description>
87572 <description>Read: Channel disabled</description>
87577 <description>Read: Channel enabled</description>
87585 <description>Write: Enable channel</description>
87592 <description>Channel 22 enable set register. Writing 0 has no effect.</description>
87599 <description>Read: Channel disabled</description>
87604 <description>Read: Channel enabled</description>
87612 <description>Write: Enable channel</description>
87619 <description>Channel 23 enable set register. Writing 0 has no effect.</description>
87626 <description>Read: Channel disabled</description>
87631 <description>Read: Channel enabled</description>
87639 <description>Write: Enable channel</description>
87646 <description>Channel 24 enable set register. Writing 0 has no effect.</description>
87653 <description>Read: Channel disabled</description>
87658 <description>Read: Channel enabled</description>
87666 <description>Write: Enable channel</description>
87673 <description>Channel 25 enable set register. Writing 0 has no effect.</description>
87680 <description>Read: Channel disabled</description>
87685 <description>Read: Channel enabled</description>
87693 <description>Write: Enable channel</description>
87700 <description>Channel 26 enable set register. Writing 0 has no effect.</description>
87707 <description>Read: Channel disabled</description>
87712 <description>Read: Channel enabled</description>
87720 <description>Write: Enable channel</description>
87727 <description>Channel 27 enable set register. Writing 0 has no effect.</description>
87734 <description>Read: Channel disabled</description>
87739 <description>Read: Channel enabled</description>
87747 <description>Write: Enable channel</description>
87754 <description>Channel 28 enable set register. Writing 0 has no effect.</description>
87761 <description>Read: Channel disabled</description>
87766 <description>Read: Channel enabled</description>
87774 <description>Write: Enable channel</description>
87781 <description>Channel 29 enable set register. Writing 0 has no effect.</description>
87788 <description>Read: Channel disabled</description>
87793 <description>Read: Channel enabled</description>
87801 <description>Write: Enable channel</description>
87808 <description>Channel 30 enable set register. Writing 0 has no effect.</description>
87815 <description>Read: Channel disabled</description>
87820 <description>Read: Channel enabled</description>
87828 <description>Write: Enable channel</description>
87835 <description>Channel 31 enable set register. Writing 0 has no effect.</description>
87842 <description>Read: Channel disabled</description>
87847 <description>Read: Channel enabled</description>
87855 <description>Write: Enable channel</description>
87864 <description>Channel enable clear register</description>
87873 <description>Channel 0 enable clear register. Writing 0 has no effect.</description>
87880 <description>Read: Channel disabled</description>
87885 <description>Read: Channel enabled</description>
87893 <description>Write: Disable channel</description>
87900 <description>Channel 1 enable clear register. Writing 0 has no effect.</description>
87907 <description>Read: Channel disabled</description>
87912 <description>Read: Channel enabled</description>
87920 <description>Write: Disable channel</description>
87927 <description>Channel 2 enable clear register. Writing 0 has no effect.</description>
87934 <description>Read: Channel disabled</description>
87939 <description>Read: Channel enabled</description>
87947 <description>Write: Disable channel</description>
87954 <description>Channel 3 enable clear register. Writing 0 has no effect.</description>
87961 <description>Read: Channel disabled</description>
87966 <description>Read: Channel enabled</description>
87974 <description>Write: Disable channel</description>
87981 <description>Channel 4 enable clear register. Writing 0 has no effect.</description>
87988 <description>Read: Channel disabled</description>
87993 <description>Read: Channel enabled</description>
88001 <description>Write: Disable channel</description>
88008 <description>Channel 5 enable clear register. Writing 0 has no effect.</description>
88015 <description>Read: Channel disabled</description>
88020 <description>Read: Channel enabled</description>
88028 <description>Write: Disable channel</description>
88035 <description>Channel 6 enable clear register. Writing 0 has no effect.</description>
88042 <description>Read: Channel disabled</description>
88047 <description>Read: Channel enabled</description>
88055 <description>Write: Disable channel</description>
88062 <description>Channel 7 enable clear register. Writing 0 has no effect.</description>
88069 <description>Read: Channel disabled</description>
88074 <description>Read: Channel enabled</description>
88082 <description>Write: Disable channel</description>
88089 <description>Channel 8 enable clear register. Writing 0 has no effect.</description>
88096 <description>Read: Channel disabled</description>
88101 <description>Read: Channel enabled</description>
88109 <description>Write: Disable channel</description>
88116 <description>Channel 9 enable clear register. Writing 0 has no effect.</description>
88123 <description>Read: Channel disabled</description>
88128 <description>Read: Channel enabled</description>
88136 <description>Write: Disable channel</description>
88143 <description>Channel 10 enable clear register. Writing 0 has no effect.</description>
88150 <description>Read: Channel disabled</description>
88155 <description>Read: Channel enabled</description>
88163 <description>Write: Disable channel</description>
88170 <description>Channel 11 enable clear register. Writing 0 has no effect.</description>
88177 <description>Read: Channel disabled</description>
88182 <description>Read: Channel enabled</description>
88190 <description>Write: Disable channel</description>
88197 <description>Channel 12 enable clear register. Writing 0 has no effect.</description>
88204 <description>Read: Channel disabled</description>
88209 <description>Read: Channel enabled</description>
88217 <description>Write: Disable channel</description>
88224 <description>Channel 13 enable clear register. Writing 0 has no effect.</description>
88231 <description>Read: Channel disabled</description>
88236 <description>Read: Channel enabled</description>
88244 <description>Write: Disable channel</description>
88251 <description>Channel 14 enable clear register. Writing 0 has no effect.</description>
88258 <description>Read: Channel disabled</description>
88263 <description>Read: Channel enabled</description>
88271 <description>Write: Disable channel</description>
88278 <description>Channel 15 enable clear register. Writing 0 has no effect.</description>
88285 <description>Read: Channel disabled</description>
88290 <description>Read: Channel enabled</description>
88298 <description>Write: Disable channel</description>
88305 <description>Channel 16 enable clear register. Writing 0 has no effect.</description>
88312 <description>Read: Channel disabled</description>
88317 <description>Read: Channel enabled</description>
88325 <description>Write: Disable channel</description>
88332 <description>Channel 17 enable clear register. Writing 0 has no effect.</description>
88339 <description>Read: Channel disabled</description>
88344 <description>Read: Channel enabled</description>
88352 <description>Write: Disable channel</description>
88359 <description>Channel 18 enable clear register. Writing 0 has no effect.</description>
88366 <description>Read: Channel disabled</description>
88371 <description>Read: Channel enabled</description>
88379 <description>Write: Disable channel</description>
88386 <description>Channel 19 enable clear register. Writing 0 has no effect.</description>
88393 <description>Read: Channel disabled</description>
88398 <description>Read: Channel enabled</description>
88406 <description>Write: Disable channel</description>
88413 <description>Channel 20 enable clear register. Writing 0 has no effect.</description>
88420 <description>Read: Channel disabled</description>
88425 <description>Read: Channel enabled</description>
88433 <description>Write: Disable channel</description>
88440 <description>Channel 21 enable clear register. Writing 0 has no effect.</description>
88447 <description>Read: Channel disabled</description>
88452 <description>Read: Channel enabled</description>
88460 <description>Write: Disable channel</description>
88467 <description>Channel 22 enable clear register. Writing 0 has no effect.</description>
88474 <description>Read: Channel disabled</description>
88479 <description>Read: Channel enabled</description>
88487 <description>Write: Disable channel</description>
88494 <description>Channel 23 enable clear register. Writing 0 has no effect.</description>
88501 <description>Read: Channel disabled</description>
88506 <description>Read: Channel enabled</description>
88514 <description>Write: Disable channel</description>
88521 <description>Channel 24 enable clear register. Writing 0 has no effect.</description>
88528 <description>Read: Channel disabled</description>
88533 <description>Read: Channel enabled</description>
88541 <description>Write: Disable channel</description>
88548 <description>Channel 25 enable clear register. Writing 0 has no effect.</description>
88555 <description>Read: Channel disabled</description>
88560 <description>Read: Channel enabled</description>
88568 <description>Write: Disable channel</description>
88575 <description>Channel 26 enable clear register. Writing 0 has no effect.</description>
88582 <description>Read: Channel disabled</description>
88587 <description>Read: Channel enabled</description>
88595 <description>Write: Disable channel</description>
88602 <description>Channel 27 enable clear register. Writing 0 has no effect.</description>
88609 <description>Read: Channel disabled</description>
88614 <description>Read: Channel enabled</description>
88622 <description>Write: Disable channel</description>
88629 <description>Channel 28 enable clear register. Writing 0 has no effect.</description>
88636 <description>Read: Channel disabled</description>
88641 <description>Read: Channel enabled</description>
88649 <description>Write: Disable channel</description>
88656 <description>Channel 29 enable clear register. Writing 0 has no effect.</description>
88663 <description>Read: Channel disabled</description>
88668 <description>Read: Channel enabled</description>
88676 <description>Write: Disable channel</description>
88683 <description>Channel 30 enable clear register. Writing 0 has no effect.</description>
88690 <description>Read: Channel disabled</description>
88695 <description>Read: Channel enabled</description>
88703 <description>Write: Disable channel</description>
88710 <description>Channel 31 enable clear register. Writing 0 has no effect.</description>
88717 <description>Read: Channel disabled</description>
88722 <description>Read: Channel enabled</description>
88730 <description>Write: Disable channel</description>
88741 …description>Description collection: Channel group n Note: Writes to this register are ignored if e…
88749 <description>Include or exclude channel 0</description>
88755 <description>Exclude</description>
88760 <description>Include</description>
88767 <description>Include or exclude channel 1</description>
88773 <description>Exclude</description>
88778 <description>Include</description>
88785 <description>Include or exclude channel 2</description>
88791 <description>Exclude</description>
88796 <description>Include</description>
88803 <description>Include or exclude channel 3</description>
88809 <description>Exclude</description>
88814 <description>Include</description>
88821 <description>Include or exclude channel 4</description>
88827 <description>Exclude</description>
88832 <description>Include</description>
88839 <description>Include or exclude channel 5</description>
88845 <description>Exclude</description>
88850 <description>Include</description>
88857 <description>Include or exclude channel 6</description>
88863 <description>Exclude</description>
88868 <description>Include</description>
88875 <description>Include or exclude channel 7</description>
88881 <description>Exclude</description>
88886 <description>Include</description>
88893 <description>Include or exclude channel 8</description>
88899 <description>Exclude</description>
88904 <description>Include</description>
88911 <description>Include or exclude channel 9</description>
88917 <description>Exclude</description>
88922 <description>Include</description>
88929 <description>Include or exclude channel 10</description>
88935 <description>Exclude</description>
88940 <description>Include</description>
88947 <description>Include or exclude channel 11</description>
88953 <description>Exclude</description>
88958 <description>Include</description>
88965 <description>Include or exclude channel 12</description>
88971 <description>Exclude</description>
88976 <description>Include</description>
88983 <description>Include or exclude channel 13</description>
88989 <description>Exclude</description>
88994 <description>Include</description>
89001 <description>Include or exclude channel 14</description>
89007 <description>Exclude</description>
89012 <description>Include</description>
89019 <description>Include or exclude channel 15</description>
89025 <description>Exclude</description>
89030 <description>Include</description>
89037 <description>Include or exclude channel 16</description>
89043 <description>Exclude</description>
89048 <description>Include</description>
89055 <description>Include or exclude channel 17</description>
89061 <description>Exclude</description>
89066 <description>Include</description>
89073 <description>Include or exclude channel 18</description>
89079 <description>Exclude</description>
89084 <description>Include</description>
89091 <description>Include or exclude channel 19</description>
89097 <description>Exclude</description>
89102 <description>Include</description>
89109 <description>Include or exclude channel 20</description>
89115 <description>Exclude</description>
89120 <description>Include</description>
89127 <description>Include or exclude channel 21</description>
89133 <description>Exclude</description>
89138 <description>Include</description>
89145 <description>Include or exclude channel 22</description>
89151 <description>Exclude</description>
89156 <description>Include</description>
89163 <description>Include or exclude channel 23</description>
89169 <description>Exclude</description>
89174 <description>Include</description>
89181 <description>Include or exclude channel 24</description>
89187 <description>Exclude</description>
89192 <description>Include</description>
89199 <description>Include or exclude channel 25</description>
89205 <description>Exclude</description>
89210 <description>Include</description>
89217 <description>Include or exclude channel 26</description>
89223 <description>Exclude</description>
89228 <description>Include</description>
89235 <description>Include or exclude channel 27</description>
89241 <description>Exclude</description>
89246 <description>Include</description>
89253 <description>Include or exclude channel 28</description>
89259 <description>Exclude</description>
89264 <description>Include</description>
89271 <description>Include or exclude channel 29</description>
89277 <description>Exclude</description>
89282 <description>Include</description>
89289 <description>Include or exclude channel 30</description>
89295 <description>Exclude</description>
89300 <description>Include</description>
89307 <description>Include or exclude channel 31</description>
89313 <description>Exclude</description>
89318 <description>Include</description>
89329 <description>Timer/Counter 0</description>
89348 <description>Start Timer</description>
89356 <description>Start Timer</description>
89362 <description>Trigger task</description>
89371 <description>Stop Timer</description>
89379 <description>Stop Timer</description>
89385 <description>Trigger task</description>
89394 <description>Increment Timer (Counter mode only)</description>
89402 <description>Increment Timer (Counter mode only)</description>
89408 <description>Trigger task</description>
89417 <description>Clear time</description>
89425 <description>Clear time</description>
89431 <description>Trigger task</description>
89442 <description>Description collection: Capture Timer value to CC[n] register</description>
89450 <description>Capture Timer value to CC[n] register</description>
89456 <description>Trigger task</description>
89465 <description>Subscribe configuration for task START</description>
89473 <description>DPPI channel that task START will subscribe to</description>
89484 <description>Disable subscription</description>
89489 <description>Enable subscription</description>
89498 <description>Subscribe configuration for task STOP</description>
89506 <description>DPPI channel that task STOP will subscribe to</description>
89517 <description>Disable subscription</description>
89522 <description>Enable subscription</description>
89531 <description>Subscribe configuration for task COUNT</description>
89539 <description>DPPI channel that task COUNT will subscribe to</description>
89550 <description>Disable subscription</description>
89555 <description>Enable subscription</description>
89564 <description>Subscribe configuration for task CLEAR</description>
89572 <description>DPPI channel that task CLEAR will subscribe to</description>
89583 <description>Disable subscription</description>
89588 <description>Enable subscription</description>
89599 … <description>Description collection: Subscribe configuration for task CAPTURE[n]</description>
89607 <description>DPPI channel that task CAPTURE[n] will subscribe to</description>
89618 <description>Disable subscription</description>
89623 <description>Enable subscription</description>
89634 <description>Description collection: Compare event on CC[n] match</description>
89642 <description>Compare event on CC[n] match</description>
89648 <description>Event not generated</description>
89653 <description>Event generated</description>
89664 … <description>Description collection: Publish configuration for event COMPARE[n]</description>
89672 <description>DPPI channel that event COMPARE[n] will publish to</description>
89683 <description>Disable publishing</description>
89688 <description>Enable publishing</description>
89697 <description>Shortcuts between local events and tasks</description>
89705 <description>Shortcut between event COMPARE[0] and task CLEAR</description>
89711 <description>Disable shortcut</description>
89716 <description>Enable shortcut</description>
89723 <description>Shortcut between event COMPARE[1] and task CLEAR</description>
89729 <description>Disable shortcut</description>
89734 <description>Enable shortcut</description>
89741 <description>Shortcut between event COMPARE[2] and task CLEAR</description>
89747 <description>Disable shortcut</description>
89752 <description>Enable shortcut</description>
89759 <description>Shortcut between event COMPARE[3] and task CLEAR</description>
89765 <description>Disable shortcut</description>
89770 <description>Enable shortcut</description>
89777 <description>Shortcut between event COMPARE[4] and task CLEAR</description>
89783 <description>Disable shortcut</description>
89788 <description>Enable shortcut</description>
89795 <description>Shortcut between event COMPARE[5] and task CLEAR</description>
89801 <description>Disable shortcut</description>
89806 <description>Enable shortcut</description>
89813 <description>Shortcut between event COMPARE[6] and task CLEAR</description>
89819 <description>Disable shortcut</description>
89824 <description>Enable shortcut</description>
89831 <description>Shortcut between event COMPARE[7] and task CLEAR</description>
89837 <description>Disable shortcut</description>
89842 <description>Enable shortcut</description>
89849 <description>Shortcut between event COMPARE[0] and task STOP</description>
89855 <description>Disable shortcut</description>
89860 <description>Enable shortcut</description>
89867 <description>Shortcut between event COMPARE[1] and task STOP</description>
89873 <description>Disable shortcut</description>
89878 <description>Enable shortcut</description>
89885 <description>Shortcut between event COMPARE[2] and task STOP</description>
89891 <description>Disable shortcut</description>
89896 <description>Enable shortcut</description>
89903 <description>Shortcut between event COMPARE[3] and task STOP</description>
89909 <description>Disable shortcut</description>
89914 <description>Enable shortcut</description>
89921 <description>Shortcut between event COMPARE[4] and task STOP</description>
89927 <description>Disable shortcut</description>
89932 <description>Enable shortcut</description>
89939 <description>Shortcut between event COMPARE[5] and task STOP</description>
89945 <description>Disable shortcut</description>
89950 <description>Enable shortcut</description>
89957 <description>Shortcut between event COMPARE[6] and task STOP</description>
89963 <description>Disable shortcut</description>
89968 <description>Enable shortcut</description>
89975 <description>Shortcut between event COMPARE[7] and task STOP</description>
89981 <description>Disable shortcut</description>
89986 <description>Enable shortcut</description>
89995 <description>Enable or disable interrupt</description>
90003 <description>Enable or disable interrupt for event COMPARE[0]</description>
90009 <description>Disable</description>
90014 <description>Enable</description>
90021 <description>Enable or disable interrupt for event COMPARE[1]</description>
90027 <description>Disable</description>
90032 <description>Enable</description>
90039 <description>Enable or disable interrupt for event COMPARE[2]</description>
90045 <description>Disable</description>
90050 <description>Enable</description>
90057 <description>Enable or disable interrupt for event COMPARE[3]</description>
90063 <description>Disable</description>
90068 <description>Enable</description>
90075 <description>Enable or disable interrupt for event COMPARE[4]</description>
90081 <description>Disable</description>
90086 <description>Enable</description>
90093 <description>Enable or disable interrupt for event COMPARE[5]</description>
90099 <description>Disable</description>
90104 <description>Enable</description>
90111 <description>Enable or disable interrupt for event COMPARE[6]</description>
90117 <description>Disable</description>
90122 <description>Enable</description>
90129 <description>Enable or disable interrupt for event COMPARE[7]</description>
90135 <description>Disable</description>
90140 <description>Enable</description>
90149 <description>Enable interrupt</description>
90157 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
90164 <description>Read: Disabled</description>
90169 <description>Read: Enabled</description>
90177 <description>Enable</description>
90184 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
90191 <description>Read: Disabled</description>
90196 <description>Read: Enabled</description>
90204 <description>Enable</description>
90211 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
90218 <description>Read: Disabled</description>
90223 <description>Read: Enabled</description>
90231 <description>Enable</description>
90238 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
90245 <description>Read: Disabled</description>
90250 <description>Read: Enabled</description>
90258 <description>Enable</description>
90265 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
90272 <description>Read: Disabled</description>
90277 <description>Read: Enabled</description>
90285 <description>Enable</description>
90292 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
90299 <description>Read: Disabled</description>
90304 <description>Read: Enabled</description>
90312 <description>Enable</description>
90319 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
90326 <description>Read: Disabled</description>
90331 <description>Read: Enabled</description>
90339 <description>Enable</description>
90346 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
90353 <description>Read: Disabled</description>
90358 <description>Read: Enabled</description>
90366 <description>Enable</description>
90375 <description>Disable interrupt</description>
90383 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
90390 <description>Read: Disabled</description>
90395 <description>Read: Enabled</description>
90403 <description>Disable</description>
90410 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
90417 <description>Read: Disabled</description>
90422 <description>Read: Enabled</description>
90430 <description>Disable</description>
90437 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
90444 <description>Read: Disabled</description>
90449 <description>Read: Enabled</description>
90457 <description>Disable</description>
90464 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
90471 <description>Read: Disabled</description>
90476 <description>Read: Enabled</description>
90484 <description>Disable</description>
90491 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
90498 <description>Read: Disabled</description>
90503 <description>Read: Enabled</description>
90511 <description>Disable</description>
90518 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
90525 <description>Read: Disabled</description>
90530 <description>Read: Enabled</description>
90538 <description>Disable</description>
90545 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
90552 <description>Read: Disabled</description>
90557 <description>Read: Enabled</description>
90565 <description>Disable</description>
90572 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
90579 <description>Read: Disabled</description>
90584 <description>Read: Enabled</description>
90592 <description>Disable</description>
90601 <description>Timer mode selection</description>
90609 <description>Timer mode</description>
90615 <description>Select Timer mode</description>
90620 <description>Deprecated enumerator - Select Counter mode</description>
90625 <description>Select Low Power Counter mode</description>
90634 <description>Configure the number of bits used by the TIMER</description>
90642 <description>Timer bit width</description>
90648 <description>16 bit timer bit width</description>
90653 <description>8 bit timer bit width</description>
90658 <description>24 bit timer bit width</description>
90663 <description>32 bit timer bit width</description>
90672 <description>Timer prescaler register</description>
90680 <description>Prescaler value</description>
90690 <description>Description collection: Capture/Compare register n</description>
90698 <description>Capture/Compare value</description>
90708 …<description>Description collection: Enable one-shot operation for Capture/Compare channel n</desc…
90716 <description>Enable one-shot operation</description>
90722 <description>Disable one-shot operation</description>
90727 <description>Enable one-shot operation</description>
90738 <description>Timer/Counter 1</description>
90749 <description>Pulse width modulation unit 0</description>
90768 …<description>Stops PWM pulse generation on all channels at the end of current PWM period, and stop…
90776 …<description>Stops PWM pulse generation on all channels at the end of current PWM period, and stop…
90782 <description>Trigger task</description>
90791 …description>Steps by one value in the current sequence on all enabled channels if DECODER.MODE=Nex…
90799 …description>Steps by one value in the current sequence on all enabled channels if DECODER.MODE=Nex…
90805 <description>Trigger task</description>
90814 <description>Peripheral tasks.</description>
90822 <description>Peripheral tasks.</description>
90828 …description>Description cluster: Starts operation using easyDMA to load the values. See peripheral…
90836 …<description>Starts operation using easyDMA to load the values. See peripheral description for ope…
90842 <description>Trigger task</description>
90851 …<description>Description cluster: Stops operation using easyDMA. This does not trigger an END even…
90859 … <description>Stops operation using easyDMA. This does not trigger an END event.</description>
90865 <description>Trigger task</description>
90876 <description>Subscribe configuration for task STOP</description>
90884 <description>DPPI channel that task STOP will subscribe to</description>
90895 <description>Disable subscription</description>
90900 <description>Enable subscription</description>
90909 <description>Subscribe configuration for task NEXTSTEP</description>
90917 <description>DPPI channel that task NEXTSTEP will subscribe to</description>
90928 <description>Disable subscription</description>
90933 <description>Enable subscription</description>
90942 <description>Subscribe configuration for tasks</description>
90950 <description>Subscribe configuration for tasks</description>
90956 <description>Description cluster: Subscribe configuration for task START</description>
90964 <description>DPPI channel that task START will subscribe to</description>
90975 <description>Disable subscription</description>
90980 <description>Enable subscription</description>
90989 <description>Description cluster: Subscribe configuration for task STOP</description>
90997 <description>DPPI channel that task STOP will subscribe to</description>
91008 <description>Disable subscription</description>
91013 <description>Enable subscription</description>
91024 … <description>Response to STOP task, emitted when PWM pulses are no longer generated</description>
91032 … <description>Response to STOP task, emitted when PWM pulses are no longer generated</description>
91038 <description>Event not generated</description>
91043 <description>Event generated</description>
91054 <description>Description collection: First PWM period started on sequence n</description>
91062 <description>First PWM period started on sequence n</description>
91068 <description>Event not generated</description>
91073 <description>Event generated</description>
91084 …<description>Description collection: Emitted at end of every sequence n, when last value from RAM …
91092 …<description>Emitted at end of every sequence n, when last value from RAM has been applied to wave…
91098 <description>Event not generated</description>
91103 <description>Event generated</description>
91112 <description>Emitted at the end of each PWM period</description>
91120 <description>Emitted at the end of each PWM period</description>
91126 <description>Event not generated</description>
91131 <description>Event generated</description>
91140 …<description>Concatenated sequences have been played the amount of times defined in LOOP.CNT</desc…
91148 …<description>Concatenated sequences have been played the amount of times defined in LOOP.CNT</desc…
91154 <description>Event not generated</description>
91159 <description>Event generated</description>
91168 …<description>Emitted when retrieving from RAM does not complete in time for the PWM module</descri…
91176 …<description>Emitted when retrieving from RAM does not complete in time for the PWM module</descri…
91182 <description>Event not generated</description>
91187 <description>Event generated</description>
91196 <description>Peripheral events.</description>
91204 <description>Peripheral events.</description>
91210 …<description>Description cluster: Generated after all MAXCNT bytes have been transferred</descript…
91218 <description>Generated after all MAXCNT bytes have been transferred</description>
91224 <description>Event not generated</description>
91229 <description>Event generated</description>
91238 …description>Description cluster: Generated when EasyDMA has buffered the .PTR and .MAXCNT register…
91246 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
91252 <description>Event not generated</description>
91257 <description>Event generated</description>
91266 … <description>Description cluster: An error occured during the bus transfer.</description>
91274 <description>An error occured during the bus transfer.</description>
91280 <description>Event not generated</description>
91285 <description>Event generated</description>
91298 …<description>Description collection: This event is generated when the compare matches for the comp…
91306 …<description>This event is generated when the compare matches for the compare channel [n].</descri…
91312 <description>Event not generated</description>
91317 <description>Event generated</description>
91326 <description>Publish configuration for event STOPPED</description>
91334 <description>DPPI channel that event STOPPED will publish to</description>
91345 <description>Disable publishing</description>
91350 <description>Enable publishing</description>
91361 … <description>Description collection: Publish configuration for event SEQSTARTED[n]</description>
91369 <description>DPPI channel that event SEQSTARTED[n] will publish to</description>
91380 <description>Disable publishing</description>
91385 <description>Enable publishing</description>
91396 … <description>Description collection: Publish configuration for event SEQEND[n]</description>
91404 <description>DPPI channel that event SEQEND[n] will publish to</description>
91415 <description>Disable publishing</description>
91420 <description>Enable publishing</description>
91429 <description>Publish configuration for event PWMPERIODEND</description>
91437 <description>DPPI channel that event PWMPERIODEND will publish to</description>
91448 <description>Disable publishing</description>
91453 <description>Enable publishing</description>
91462 <description>Publish configuration for event LOOPSDONE</description>
91470 <description>DPPI channel that event LOOPSDONE will publish to</description>
91481 <description>Disable publishing</description>
91486 <description>Enable publishing</description>
91495 <description>Publish configuration for event RAMUNDERFLOW</description>
91503 <description>DPPI channel that event RAMUNDERFLOW will publish to</description>
91514 <description>Disable publishing</description>
91519 <description>Enable publishing</description>
91528 <description>Publish configuration for events</description>
91536 <description>Publish configuration for events</description>
91542 <description>Description cluster: Publish configuration for event END</description>
91550 <description>DPPI channel that event END will publish to</description>
91561 <description>Disable publishing</description>
91566 <description>Enable publishing</description>
91575 <description>Description cluster: Publish configuration for event READY</description>
91583 <description>DPPI channel that event READY will publish to</description>
91594 <description>Disable publishing</description>
91599 <description>Enable publishing</description>
91608 … <description>Description cluster: Publish configuration for event BUSERROR</description>
91616 <description>DPPI channel that event BUSERROR will publish to</description>
91627 <description>Disable publishing</description>
91632 <description>Enable publishing</description>
91645 … <description>Description collection: Publish configuration for event COMPAREMATCH[n]</description>
91653 <description>DPPI channel that event COMPAREMATCH[n] will publish to</description>
91664 <description>Disable publishing</description>
91669 <description>Enable publishing</description>
91678 <description>Shortcuts between local events and tasks</description>
91686 <description>Shortcut between event SEQEND[n] and task STOP</description>
91692 <description>Disable shortcut</description>
91697 <description>Enable shortcut</description>
91704 <description>Shortcut between event SEQEND[n] and task STOP</description>
91710 <description>Disable shortcut</description>
91715 <description>Enable shortcut</description>
91722 <description>Shortcut between event LOOPSDONE and task DMA.SEQ[n].START</description>
91728 <description>Disable shortcut</description>
91733 <description>Enable shortcut</description>
91740 <description>Shortcut between event LOOPSDONE and task DMA.SEQ[n].START</description>
91746 <description>Disable shortcut</description>
91751 <description>Enable shortcut</description>
91758 <description>Shortcut between event LOOPSDONE and task STOP</description>
91764 <description>Disable shortcut</description>
91769 <description>Enable shortcut</description>
91776 <description>Shortcut between event RAMUNDERFLOW and task STOP</description>
91782 <description>Disable shortcut</description>
91787 <description>Enable shortcut</description>
91794 <description>Shortcut between event DMA.SEQ[n].BUSERROR and task STOP</description>
91800 <description>Disable shortcut</description>
91805 <description>Enable shortcut</description>
91812 <description>Shortcut between event DMA.SEQ[n].BUSERROR and task STOP</description>
91818 <description>Disable shortcut</description>
91823 <description>Enable shortcut</description>
91832 <description>Enable or disable interrupt</description>
91840 <description>Enable or disable interrupt for event STOPPED</description>
91846 <description>Disable</description>
91851 <description>Enable</description>
91858 <description>Enable or disable interrupt for event SEQSTARTED[0]</description>
91864 <description>Disable</description>
91869 <description>Enable</description>
91876 <description>Enable or disable interrupt for event SEQSTARTED[1]</description>
91882 <description>Disable</description>
91887 <description>Enable</description>
91894 <description>Enable or disable interrupt for event SEQEND[0]</description>
91900 <description>Disable</description>
91905 <description>Enable</description>
91912 <description>Enable or disable interrupt for event SEQEND[1]</description>
91918 <description>Disable</description>
91923 <description>Enable</description>
91930 <description>Enable or disable interrupt for event PWMPERIODEND</description>
91936 <description>Disable</description>
91941 <description>Enable</description>
91948 <description>Enable or disable interrupt for event LOOPSDONE</description>
91954 <description>Disable</description>
91959 <description>Enable</description>
91966 <description>Enable or disable interrupt for event RAMUNDERFLOW</description>
91972 <description>Disable</description>
91977 <description>Enable</description>
91984 <description>Enable or disable interrupt for event DMASEQ0END</description>
91990 <description>Disable</description>
91995 <description>Enable</description>
92002 <description>Enable or disable interrupt for event DMASEQ0READY</description>
92008 <description>Disable</description>
92013 <description>Enable</description>
92020 <description>Enable or disable interrupt for event DMASEQ0BUSERROR</description>
92026 <description>Disable</description>
92031 <description>Enable</description>
92038 <description>Enable or disable interrupt for event DMASEQ1END</description>
92044 <description>Disable</description>
92049 <description>Enable</description>
92056 <description>Enable or disable interrupt for event DMASEQ1READY</description>
92062 <description>Disable</description>
92067 <description>Enable</description>
92074 <description>Enable or disable interrupt for event DMASEQ1BUSERROR</description>
92080 <description>Disable</description>
92085 <description>Enable</description>
92092 <description>Enable or disable interrupt for event COMPAREMATCH[0]</description>
92098 <description>Disable</description>
92103 <description>Enable</description>
92110 <description>Enable or disable interrupt for event COMPAREMATCH[1]</description>
92116 <description>Disable</description>
92121 <description>Enable</description>
92128 <description>Enable or disable interrupt for event COMPAREMATCH[2]</description>
92134 <description>Disable</description>
92139 <description>Enable</description>
92146 <description>Enable or disable interrupt for event COMPAREMATCH[3]</description>
92152 <description>Disable</description>
92157 <description>Enable</description>
92166 <description>Enable interrupt</description>
92174 <description>Write '1' to enable interrupt for event STOPPED</description>
92181 <description>Read: Disabled</description>
92186 <description>Read: Enabled</description>
92194 <description>Enable</description>
92201 <description>Write '1' to enable interrupt for event SEQSTARTED[0]</description>
92208 <description>Read: Disabled</description>
92213 <description>Read: Enabled</description>
92221 <description>Enable</description>
92228 <description>Write '1' to enable interrupt for event SEQSTARTED[1]</description>
92235 <description>Read: Disabled</description>
92240 <description>Read: Enabled</description>
92248 <description>Enable</description>
92255 <description>Write '1' to enable interrupt for event SEQEND[0]</description>
92262 <description>Read: Disabled</description>
92267 <description>Read: Enabled</description>
92275 <description>Enable</description>
92282 <description>Write '1' to enable interrupt for event SEQEND[1]</description>
92289 <description>Read: Disabled</description>
92294 <description>Read: Enabled</description>
92302 <description>Enable</description>
92309 <description>Write '1' to enable interrupt for event PWMPERIODEND</description>
92316 <description>Read: Disabled</description>
92321 <description>Read: Enabled</description>
92329 <description>Enable</description>
92336 <description>Write '1' to enable interrupt for event LOOPSDONE</description>
92343 <description>Read: Disabled</description>
92348 <description>Read: Enabled</description>
92356 <description>Enable</description>
92363 <description>Write '1' to enable interrupt for event RAMUNDERFLOW</description>
92370 <description>Read: Disabled</description>
92375 <description>Read: Enabled</description>
92383 <description>Enable</description>
92390 <description>Write '1' to enable interrupt for event DMASEQ0END</description>
92397 <description>Read: Disabled</description>
92402 <description>Read: Enabled</description>
92410 <description>Enable</description>
92417 <description>Write '1' to enable interrupt for event DMASEQ0READY</description>
92424 <description>Read: Disabled</description>
92429 <description>Read: Enabled</description>
92437 <description>Enable</description>
92444 <description>Write '1' to enable interrupt for event DMASEQ0BUSERROR</description>
92451 <description>Read: Disabled</description>
92456 <description>Read: Enabled</description>
92464 <description>Enable</description>
92471 <description>Write '1' to enable interrupt for event DMASEQ1END</description>
92478 <description>Read: Disabled</description>
92483 <description>Read: Enabled</description>
92491 <description>Enable</description>
92498 <description>Write '1' to enable interrupt for event DMASEQ1READY</description>
92505 <description>Read: Disabled</description>
92510 <description>Read: Enabled</description>
92518 <description>Enable</description>
92525 <description>Write '1' to enable interrupt for event DMASEQ1BUSERROR</description>
92532 <description>Read: Disabled</description>
92537 <description>Read: Enabled</description>
92545 <description>Enable</description>
92552 <description>Write '1' to enable interrupt for event COMPAREMATCH[0]</description>
92559 <description>Read: Disabled</description>
92564 <description>Read: Enabled</description>
92572 <description>Enable</description>
92579 <description>Write '1' to enable interrupt for event COMPAREMATCH[1]</description>
92586 <description>Read: Disabled</description>
92591 <description>Read: Enabled</description>
92599 <description>Enable</description>
92606 <description>Write '1' to enable interrupt for event COMPAREMATCH[2]</description>
92613 <description>Read: Disabled</description>
92618 <description>Read: Enabled</description>
92626 <description>Enable</description>
92633 <description>Write '1' to enable interrupt for event COMPAREMATCH[3]</description>
92640 <description>Read: Disabled</description>
92645 <description>Read: Enabled</description>
92653 <description>Enable</description>
92662 <description>Disable interrupt</description>
92670 <description>Write '1' to disable interrupt for event STOPPED</description>
92677 <description>Read: Disabled</description>
92682 <description>Read: Enabled</description>
92690 <description>Disable</description>
92697 <description>Write '1' to disable interrupt for event SEQSTARTED[0]</description>
92704 <description>Read: Disabled</description>
92709 <description>Read: Enabled</description>
92717 <description>Disable</description>
92724 <description>Write '1' to disable interrupt for event SEQSTARTED[1]</description>
92731 <description>Read: Disabled</description>
92736 <description>Read: Enabled</description>
92744 <description>Disable</description>
92751 <description>Write '1' to disable interrupt for event SEQEND[0]</description>
92758 <description>Read: Disabled</description>
92763 <description>Read: Enabled</description>
92771 <description>Disable</description>
92778 <description>Write '1' to disable interrupt for event SEQEND[1]</description>
92785 <description>Read: Disabled</description>
92790 <description>Read: Enabled</description>
92798 <description>Disable</description>
92805 <description>Write '1' to disable interrupt for event PWMPERIODEND</description>
92812 <description>Read: Disabled</description>
92817 <description>Read: Enabled</description>
92825 <description>Disable</description>
92832 <description>Write '1' to disable interrupt for event LOOPSDONE</description>
92839 <description>Read: Disabled</description>
92844 <description>Read: Enabled</description>
92852 <description>Disable</description>
92859 <description>Write '1' to disable interrupt for event RAMUNDERFLOW</description>
92866 <description>Read: Disabled</description>
92871 <description>Read: Enabled</description>
92879 <description>Disable</description>
92886 <description>Write '1' to disable interrupt for event DMASEQ0END</description>
92893 <description>Read: Disabled</description>
92898 <description>Read: Enabled</description>
92906 <description>Disable</description>
92913 <description>Write '1' to disable interrupt for event DMASEQ0READY</description>
92920 <description>Read: Disabled</description>
92925 <description>Read: Enabled</description>
92933 <description>Disable</description>
92940 <description>Write '1' to disable interrupt for event DMASEQ0BUSERROR</description>
92947 <description>Read: Disabled</description>
92952 <description>Read: Enabled</description>
92960 <description>Disable</description>
92967 <description>Write '1' to disable interrupt for event DMASEQ1END</description>
92974 <description>Read: Disabled</description>
92979 <description>Read: Enabled</description>
92987 <description>Disable</description>
92994 <description>Write '1' to disable interrupt for event DMASEQ1READY</description>
93001 <description>Read: Disabled</description>
93006 <description>Read: Enabled</description>
93014 <description>Disable</description>
93021 <description>Write '1' to disable interrupt for event DMASEQ1BUSERROR</description>
93028 <description>Read: Disabled</description>
93033 <description>Read: Enabled</description>
93041 <description>Disable</description>
93048 <description>Write '1' to disable interrupt for event COMPAREMATCH[0]</description>
93055 <description>Read: Disabled</description>
93060 <description>Read: Enabled</description>
93068 <description>Disable</description>
93075 <description>Write '1' to disable interrupt for event COMPAREMATCH[1]</description>
93082 <description>Read: Disabled</description>
93087 <description>Read: Enabled</description>
93095 <description>Disable</description>
93102 <description>Write '1' to disable interrupt for event COMPAREMATCH[2]</description>
93109 <description>Read: Disabled</description>
93114 <description>Read: Enabled</description>
93122 <description>Disable</description>
93129 <description>Write '1' to disable interrupt for event COMPAREMATCH[3]</description>
93136 <description>Read: Disabled</description>
93141 <description>Read: Enabled</description>
93149 <description>Disable</description>
93158 <description>Pending interrupts</description>
93166 <description>Read pending status of interrupt for event STOPPED</description>
93173 <description>Read: Not pending</description>
93178 <description>Read: Pending</description>
93185 <description>Read pending status of interrupt for event SEQSTARTED[0]</description>
93192 <description>Read: Not pending</description>
93197 <description>Read: Pending</description>
93204 <description>Read pending status of interrupt for event SEQSTARTED[1]</description>
93211 <description>Read: Not pending</description>
93216 <description>Read: Pending</description>
93223 <description>Read pending status of interrupt for event SEQEND[0]</description>
93230 <description>Read: Not pending</description>
93235 <description>Read: Pending</description>
93242 <description>Read pending status of interrupt for event SEQEND[1]</description>
93249 <description>Read: Not pending</description>
93254 <description>Read: Pending</description>
93261 <description>Read pending status of interrupt for event PWMPERIODEND</description>
93268 <description>Read: Not pending</description>
93273 <description>Read: Pending</description>
93280 <description>Read pending status of interrupt for event LOOPSDONE</description>
93287 <description>Read: Not pending</description>
93292 <description>Read: Pending</description>
93299 <description>Read pending status of interrupt for event RAMUNDERFLOW</description>
93306 <description>Read: Not pending</description>
93311 <description>Read: Pending</description>
93318 <description>Read pending status of interrupt for event DMASEQ0END</description>
93325 <description>Read: Not pending</description>
93330 <description>Read: Pending</description>
93337 <description>Read pending status of interrupt for event DMASEQ0READY</description>
93344 <description>Read: Not pending</description>
93349 <description>Read: Pending</description>
93356 <description>Read pending status of interrupt for event DMASEQ0BUSERROR</description>
93363 <description>Read: Not pending</description>
93368 <description>Read: Pending</description>
93375 <description>Read pending status of interrupt for event DMASEQ1END</description>
93382 <description>Read: Not pending</description>
93387 <description>Read: Pending</description>
93394 <description>Read pending status of interrupt for event DMASEQ1READY</description>
93401 <description>Read: Not pending</description>
93406 <description>Read: Pending</description>
93413 <description>Read pending status of interrupt for event DMASEQ1BUSERROR</description>
93420 <description>Read: Not pending</description>
93425 <description>Read: Pending</description>
93432 <description>Read pending status of interrupt for event COMPAREMATCH[0]</description>
93439 <description>Read: Not pending</description>
93444 <description>Read: Pending</description>
93451 <description>Read pending status of interrupt for event COMPAREMATCH[1]</description>
93458 <description>Read: Not pending</description>
93463 <description>Read: Pending</description>
93470 <description>Read pending status of interrupt for event COMPAREMATCH[2]</description>
93477 <description>Read: Not pending</description>
93482 <description>Read: Pending</description>
93489 <description>Read pending status of interrupt for event COMPAREMATCH[3]</description>
93496 <description>Read: Not pending</description>
93501 <description>Read: Pending</description>
93510 <description>PWM module enable register</description>
93518 <description>Enable or disable PWM module</description>
93524 <description>Disabled</description>
93529 <description>Enable</description>
93538 <description>Selects operating mode of the wave counter</description>
93546 <description>Selects up mode or up-and-down mode for the counter</description>
93552 <description>Up counter, edge-aligned PWM duty cycle</description>
93557 <description>Up and down counter, center-aligned PWM duty cycle</description>
93566 <description>Value up to which the pulse generator counter counts</description>
93574 …description>Value up to which the pulse generator counter counts. This register is ignored when DE…
93582 <description>Configuration for PWM_CLK</description>
93590 <description>Prescaler of PWM_CLK</description>
93596 <description>Divide by 1 (16 MHz)</description>
93601 <description>Divide by 2 (8 MHz)</description>
93606 <description>Divide by 4 (4 MHz)</description>
93611 <description>Divide by 8 (2 MHz)</description>
93616 <description>Divide by 16 (1 MHz)</description>
93621 <description>Divide by 32 (500 kHz)</description>
93626 <description>Divide by 64 (250 kHz)</description>
93631 <description>Divide by 128 (125 kHz)</description>
93640 <description>Configuration of the decoder</description>
93648 … <description>How a sequence is read from RAM and spread to the compare register</description>
93654 <description>1st half word (16-bit) used in all PWM channels 0..3</description>
93659 … <description>1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3</description>
93664 … <description>1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3</description>
93669 … <description>1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP</description>
93676 <description>Selects source for advancing the active sequence</description>
93682 … <description>SEQ[n].REFRESH is used to determine loading internal compare registers</description>
93687 …<description>NEXTSTEP task causes a new value to be loaded to internal compare registers</descript…
93696 <description>Number of playbacks of a loop</description>
93704 <description>Number of playbacks of pattern cycles</description>
93710 <description>Looping disabled (stop at the end of the sequence)</description>
93719 <description>Configure the output value on the PWM channel during idle</description>
93727 <description>Idle output value for PWM channel [0]</description>
93733 <description>Idle output value for PWM channel [1]</description>
93739 <description>Idle output value for PWM channel [2]</description>
93745 <description>Idle output value for PWM channel [3]</description>
93755 <description>Unspecified</description>
93761 …<description>Description cluster: Number of additional PWM periods between samples loaded into com…
93769 …<description>Number of additional PWM periods between samples loaded into compare register (load e…
93775 <description>Update every PWM period</description>
93784 <description>Description cluster: Time added after the sequence</description>
93792 <description>Time added after the sequence in PWM periods</description>
93801 <description>Unspecified</description>
93809 <description>Description collection: Output pin select for PWM channel n</description>
93817 <description>Pin number</description>
93823 <description>Port number</description>
93829 <description>Connection</description>
93835 <description>Disconnect</description>
93840 <description>Connect</description>
93850 <description>Unspecified</description>
93858 <description>Unspecified</description>
93864 <description>Description cluster: RAM buffer start address</description>
93872 …<description>RAM buffer start address for this EasyDMA channel. This address is a word aligned Dat…
93880 … <description>Description cluster: Maximum number of bytes in channel buffer</description>
93888 <description>Maximum number of bytes in channel buffer</description>
93896 …<description>Description cluster: Number of bytes transferred in the last transaction, updated aft…
93904 …<description>Number of bytes transferred in the last transaction. In case of NACK error, includes …
93912 …<description>Description cluster: Number of bytes transferred in the current transaction</descript…
93920 …<description>Number of bytes transferred in the current transaction. Continuously updated.</descri…
93928 …<description>Description cluster: Terminate the transaction if a BUSERROR event is detected.</desc…
93941 <description>Disable</description>
93946 <description>Enable</description>
93955 …<description>Description cluster: Address of transaction that generated the last BUSERROR event.</…
93974 <description>SPI Slave 0</description>
93993 <description>Acquire SPI semaphore</description>
94001 <description>Acquire SPI semaphore</description>
94007 <description>Trigger task</description>
94016 <description>Release SPI semaphore, enabling the SPI slave to acquire it</description>
94024 <description>Release SPI semaphore, enabling the SPI slave to acquire it</description>
94030 <description>Trigger task</description>
94039 <description>Peripheral tasks.</description>
94045 <description>Peripheral tasks.</description>
94053 …<description>Description collection: Enables the MATCH[n] event by setting the ENABLE[n] bit in th…
94061 …<description>Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register.</desc…
94067 <description>Trigger task</description>
94078 …<description>Description collection: Disables the MATCH[n] event by clearing the ENABLE[n] bit in …
94086 …<description>Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register.</de…
94092 <description>Trigger task</description>
94103 <description>Subscribe configuration for task ACQUIRE</description>
94111 <description>DPPI channel that task ACQUIRE will subscribe to</description>
94122 <description>Disable subscription</description>
94127 <description>Enable subscription</description>
94136 <description>Subscribe configuration for task RELEASE</description>
94144 <description>DPPI channel that task RELEASE will subscribe to</description>
94155 <description>Disable subscription</description>
94160 <description>Enable subscription</description>
94169 <description>Subscribe configuration for tasks</description>
94175 <description>Subscribe configuration for tasks</description>
94183 … <description>Description collection: Subscribe configuration for task ENABLEMATCH[n]</description>
94191 <description>DPPI channel that task ENABLEMATCH[n] will subscribe to</description>
94202 <description>Disable subscription</description>
94207 <description>Enable subscription</description>
94218 …<description>Description collection: Subscribe configuration for task DISABLEMATCH[n]</description>
94226 … <description>DPPI channel that task DISABLEMATCH[n] will subscribe to</description>
94237 <description>Disable subscription</description>
94242 <description>Enable subscription</description>
94253 <description>Granted transaction completed</description>
94261 <description>Granted transaction completed</description>
94267 <description>Event not generated</description>
94272 <description>Event generated</description>
94281 <description>Semaphore acquired</description>
94289 <description>Semaphore acquired</description>
94295 <description>Event not generated</description>
94300 <description>Event generated</description>
94309 <description>Peripheral events.</description>
94315 <description>Peripheral events.</description>
94321 <description>Generated after all MAXCNT bytes have been transferred</description>
94329 <description>Generated after all MAXCNT bytes have been transferred</description>
94335 <description>Event not generated</description>
94340 <description>Event generated</description>
94349 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
94357 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
94363 <description>Event not generated</description>
94368 <description>Event generated</description>
94377 <description>An error occured during the bus transfer.</description>
94385 <description>An error occured during the bus transfer.</description>
94391 <description>Event not generated</description>
94396 <description>Event generated</description>
94407 … <description>Description collection: Pattern match is detected on the DMA data bus.</description>
94415 <description>Pattern match is detected on the DMA data bus.</description>
94421 <description>Event not generated</description>
94426 <description>Event generated</description>
94436 <description>Peripheral events.</description>
94442 <description>Generated after all MAXCNT bytes have been transferred</description>
94450 <description>Generated after all MAXCNT bytes have been transferred</description>
94456 <description>Event not generated</description>
94461 <description>Event generated</description>
94470 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
94478 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
94484 <description>Event not generated</description>
94489 <description>Event generated</description>
94498 <description>An error occured during the bus transfer.</description>
94506 <description>An error occured during the bus transfer.</description>
94512 <description>Event not generated</description>
94517 <description>Event generated</description>
94528 <description>Publish configuration for event END</description>
94536 <description>DPPI channel that event END will publish to</description>
94547 <description>Disable publishing</description>
94552 <description>Enable publishing</description>
94561 <description>Publish configuration for event ACQUIRED</description>
94569 <description>DPPI channel that event ACQUIRED will publish to</description>
94580 <description>Disable publishing</description>
94585 <description>Enable publishing</description>
94594 <description>Publish configuration for events</description>
94600 <description>Publish configuration for events</description>
94606 <description>Publish configuration for event END</description>
94614 <description>DPPI channel that event END will publish to</description>
94625 <description>Disable publishing</description>
94630 <description>Enable publishing</description>
94639 <description>Publish configuration for event READY</description>
94647 <description>DPPI channel that event READY will publish to</description>
94658 <description>Disable publishing</description>
94663 <description>Enable publishing</description>
94672 <description>Publish configuration for event BUSERROR</description>
94680 <description>DPPI channel that event BUSERROR will publish to</description>
94691 <description>Disable publishing</description>
94696 <description>Enable publishing</description>
94707 … <description>Description collection: Publish configuration for event MATCH[n]</description>
94715 <description>DPPI channel that event MATCH[n] will publish to</description>
94726 <description>Disable publishing</description>
94731 <description>Enable publishing</description>
94741 <description>Publish configuration for events</description>
94747 <description>Publish configuration for event END</description>
94755 <description>DPPI channel that event END will publish to</description>
94766 <description>Disable publishing</description>
94771 <description>Enable publishing</description>
94780 <description>Publish configuration for event READY</description>
94788 <description>DPPI channel that event READY will publish to</description>
94799 <description>Disable publishing</description>
94804 <description>Enable publishing</description>
94813 <description>Publish configuration for event BUSERROR</description>
94821 <description>DPPI channel that event BUSERROR will publish to</description>
94832 <description>Disable publishing</description>
94837 <description>Enable publishing</description>
94848 <description>Shortcuts between local events and tasks</description>
94856 <description>Shortcut between event END and task ACQUIRE</description>
94862 <description>Disable shortcut</description>
94867 <description>Enable shortcut</description>
94874 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows daisy-ch…
94880 <description>Disable shortcut</description>
94885 <description>Enable shortcut</description>
94892 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows daisy-ch…
94898 <description>Disable shortcut</description>
94903 <description>Enable shortcut</description>
94910 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows daisy-ch…
94916 <description>Disable shortcut</description>
94921 <description>Enable shortcut</description>
94928 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows daisy-ch…
94934 <description>Disable shortcut</description>
94939 <description>Enable shortcut</description>
94946 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
94952 <description>Disable shortcut</description>
94957 <description>Enable shortcut</description>
94964 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
94970 <description>Disable shortcut</description>
94975 <description>Enable shortcut</description>
94982 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
94988 <description>Disable shortcut</description>
94993 <description>Enable shortcut</description>
95000 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
95006 <description>Disable shortcut</description>
95011 <description>Enable shortcut</description>
95020 <description>Enable interrupt</description>
95028 <description>Write '1' to enable interrupt for event END</description>
95035 <description>Read: Disabled</description>
95040 <description>Read: Enabled</description>
95048 <description>Enable</description>
95055 <description>Write '1' to enable interrupt for event ACQUIRED</description>
95062 <description>Read: Disabled</description>
95067 <description>Read: Enabled</description>
95075 <description>Enable</description>
95082 <description>Write '1' to enable interrupt for event DMARXEND</description>
95089 <description>Read: Disabled</description>
95094 <description>Read: Enabled</description>
95102 <description>Enable</description>
95109 <description>Write '1' to enable interrupt for event DMARXREADY</description>
95116 <description>Read: Disabled</description>
95121 <description>Read: Enabled</description>
95129 <description>Enable</description>
95136 <description>Write '1' to enable interrupt for event DMARXBUSERROR</description>
95143 <description>Read: Disabled</description>
95148 <description>Read: Enabled</description>
95156 <description>Enable</description>
95163 <description>Write '1' to enable interrupt for event DMARXMATCH[0]</description>
95170 <description>Read: Disabled</description>
95175 <description>Read: Enabled</description>
95183 <description>Enable</description>
95190 <description>Write '1' to enable interrupt for event DMARXMATCH[1]</description>
95197 <description>Read: Disabled</description>
95202 <description>Read: Enabled</description>
95210 <description>Enable</description>
95217 <description>Write '1' to enable interrupt for event DMARXMATCH[2]</description>
95224 <description>Read: Disabled</description>
95229 <description>Read: Enabled</description>
95237 <description>Enable</description>
95244 <description>Write '1' to enable interrupt for event DMARXMATCH[3]</description>
95251 <description>Read: Disabled</description>
95256 <description>Read: Enabled</description>
95264 <description>Enable</description>
95271 <description>Write '1' to enable interrupt for event DMATXEND</description>
95278 <description>Read: Disabled</description>
95283 <description>Read: Enabled</description>
95291 <description>Enable</description>
95298 <description>Write '1' to enable interrupt for event DMATXREADY</description>
95305 <description>Read: Disabled</description>
95310 <description>Read: Enabled</description>
95318 <description>Enable</description>
95325 <description>Write '1' to enable interrupt for event DMATXBUSERROR</description>
95332 <description>Read: Disabled</description>
95337 <description>Read: Enabled</description>
95345 <description>Enable</description>
95354 <description>Disable interrupt</description>
95362 <description>Write '1' to disable interrupt for event END</description>
95369 <description>Read: Disabled</description>
95374 <description>Read: Enabled</description>
95382 <description>Disable</description>
95389 <description>Write '1' to disable interrupt for event ACQUIRED</description>
95396 <description>Read: Disabled</description>
95401 <description>Read: Enabled</description>
95409 <description>Disable</description>
95416 <description>Write '1' to disable interrupt for event DMARXEND</description>
95423 <description>Read: Disabled</description>
95428 <description>Read: Enabled</description>
95436 <description>Disable</description>
95443 <description>Write '1' to disable interrupt for event DMARXREADY</description>
95450 <description>Read: Disabled</description>
95455 <description>Read: Enabled</description>
95463 <description>Disable</description>
95470 <description>Write '1' to disable interrupt for event DMARXBUSERROR</description>
95477 <description>Read: Disabled</description>
95482 <description>Read: Enabled</description>
95490 <description>Disable</description>
95497 <description>Write '1' to disable interrupt for event DMARXMATCH[0]</description>
95504 <description>Read: Disabled</description>
95509 <description>Read: Enabled</description>
95517 <description>Disable</description>
95524 <description>Write '1' to disable interrupt for event DMARXMATCH[1]</description>
95531 <description>Read: Disabled</description>
95536 <description>Read: Enabled</description>
95544 <description>Disable</description>
95551 <description>Write '1' to disable interrupt for event DMARXMATCH[2]</description>
95558 <description>Read: Disabled</description>
95563 <description>Read: Enabled</description>
95571 <description>Disable</description>
95578 <description>Write '1' to disable interrupt for event DMARXMATCH[3]</description>
95585 <description>Read: Disabled</description>
95590 <description>Read: Enabled</description>
95598 <description>Disable</description>
95605 <description>Write '1' to disable interrupt for event DMATXEND</description>
95612 <description>Read: Disabled</description>
95617 <description>Read: Enabled</description>
95625 <description>Disable</description>
95632 <description>Write '1' to disable interrupt for event DMATXREADY</description>
95639 <description>Read: Disabled</description>
95644 <description>Read: Enabled</description>
95652 <description>Disable</description>
95659 <description>Write '1' to disable interrupt for event DMATXBUSERROR</description>
95666 <description>Read: Disabled</description>
95671 <description>Read: Enabled</description>
95679 <description>Disable</description>
95688 <description>Semaphore status register</description>
95696 <description>Semaphore status</description>
95702 <description>Semaphore is free</description>
95707 <description>Semaphore is assigned to CPU</description>
95712 <description>Semaphore is assigned to SPI slave</description>
95717 … <description>Semaphore is assigned to SPI but a handover to the CPU is pending</description>
95726 <description>Status from last transaction</description>
95734 <description>TX buffer over-read detected, and prevented</description>
95741 <description>Read: error not present</description>
95746 <description>Read: error present</description>
95754 <description>Write: clear error on writing '1'</description>
95761 <description>RX buffer overflow detected, and prevented</description>
95768 <description>Read: error not present</description>
95773 <description>Read: error present</description>
95781 <description>Write: clear error on writing '1'</description>
95790 <description>Enable SPI slave</description>
95798 <description>Enable or disable SPI slave</description>
95804 <description>Disable SPI slave</description>
95809 <description>Enable SPI slave</description>
95818 <description>Configuration register</description>
95826 <description>Bit order</description>
95832 <description>Most significant bit shifted out first</description>
95837 <description>Least significant bit shifted out first</description>
95844 <description>Serial clock (SCK) phase</description>
95850 … <description>Sample on leading edge of clock, shift serial data on trailing edge</description>
95855 … <description>Sample on trailing edge of clock, shift serial data on leading edge</description>
95862 <description>Serial clock (SCK) polarity</description>
95868 <description>Active high</description>
95873 <description>Active low</description>
95882 …<description>Default character. Character clocked out in case of an ignored transaction.</descript…
95890 …<description>Default character. Character clocked out in case of an ignored transaction.</descript…
95898 <description>Over-read character</description>
95906 …<description>Over-read character. Character clocked out after an over-read of the transmit buffer.…
95914 <description>Unspecified</description>
95920 <description>Pin select for SCK</description>
95928 <description>Pin number</description>
95934 <description>Port number</description>
95940 <description>Connection</description>
95946 <description>Disconnect</description>
95951 <description>Connect</description>
95960 <description>Pin select for MISO signal</description>
95968 <description>Pin number</description>
95974 <description>Port number</description>
95980 <description>Connection</description>
95986 <description>Disconnect</description>
95991 <description>Connect</description>
96000 <description>Pin select for MOSI signal</description>
96008 <description>Pin number</description>
96014 <description>Port number</description>
96020 <description>Connection</description>
96026 <description>Disconnect</description>
96031 <description>Connect</description>
96040 <description>Pin select for CSN signal</description>
96048 <description>Pin number</description>
96054 <description>Port number</description>
96060 <description>Connection</description>
96066 <description>Disconnect</description>
96071 <description>Connect</description>
96081 <description>Unspecified</description>
96087 <description>Unspecified</description>
96093 <description>RAM buffer start address</description>
96101 …<description>RAM buffer start address for this EasyDMA channel. This address is a word aligned Dat…
96109 <description>Maximum number of bytes in channel buffer</description>
96117 <description>Maximum number of bytes in channel buffer</description>
96125 …<description>Number of bytes transferred in the last transaction, updated after the END event. Als…
96133 …<description>Number of bytes transferred in the last transaction. In case of NACK error, includes …
96141 <description>Number of bytes transferred in the current transaction</description>
96149 …<description>Number of bytes transferred in the current transaction. Continuously updated.</descri…
96157 <description>EasyDMA list type</description>
96165 <description>List type</description>
96171 <description>Disable EasyDMA list</description>
96176 <description>Use array list</description>
96185 <description>Terminate the transaction if a BUSERROR event is detected.</description>
96198 <description>Disable</description>
96203 <description>Enable</description>
96212 … <description>Address of transaction that generated the last BUSERROR event.</description>
96227 … <description>Registers to control the behavior of the pattern matcher engine</description>
96233 <description>Configure individual match events</description>
96241 <description>Enable match filter 0</description>
96247 <description>Match filter disabled</description>
96252 <description>Match filter enabled</description>
96259 <description>Enable match filter 1</description>
96265 <description>Match filter disabled</description>
96270 <description>Match filter enabled</description>
96277 <description>Enable match filter 2</description>
96283 <description>Match filter disabled</description>
96288 <description>Match filter enabled</description>
96295 <description>Enable match filter 3</description>
96301 <description>Match filter disabled</description>
96306 <description>Match filter enabled</description>
96313 <description>Configure match filter 0 as one-shot or sticky</description>
96319 <description>Match filter stays enabled until disabled by task</description>
96324 … <description>Match filter stays enabled until next data word is received</description>
96331 <description>Configure match filter 1 as one-shot or sticky</description>
96337 <description>Match filter stays enabled until disabled by task</description>
96342 … <description>Match filter stays enabled until next data word is received</description>
96349 <description>Configure match filter 2 as one-shot or sticky</description>
96355 <description>Match filter stays enabled until disabled by task</description>
96360 … <description>Match filter stays enabled until next data word is received</description>
96367 <description>Configure match filter 3 as one-shot or sticky</description>
96373 <description>Match filter stays enabled until disabled by task</description>
96378 … <description>Match filter stays enabled until next data word is received</description>
96389 …<description>Description collection: The data to look for - any match will trigger the MATCH[n] ev…
96397 <description>Data to look for</description>
96407 <description>Unspecified</description>
96413 <description>RAM buffer start address</description>
96421 …<description>RAM buffer start address for this EasyDMA channel. This address is a word aligned Dat…
96429 <description>Maximum number of bytes in channel buffer</description>
96437 <description>Maximum number of bytes in channel buffer</description>
96445 …<description>Number of bytes transferred in the last transaction, updated after the END event. Als…
96453 …<description>Number of bytes transferred in the last transaction. In case of NACK error, includes …
96461 <description>Number of bytes transferred in the current transaction</description>
96469 …<description>Number of bytes transferred in the current transaction. Continuously updated.</descri…
96477 <description>EasyDMA list type</description>
96485 <description>List type</description>
96491 <description>Disable EasyDMA list</description>
96496 <description>Use array list</description>
96505 <description>Terminate the transaction if a BUSERROR event is detected.</description>
96518 <description>Disable</description>
96523 <description>Enable</description>
96532 … <description>Address of transaction that generated the last BUSERROR event.</description>
96551 <description>Serial Peripheral Interface Master with EasyDMA 0</description>
96570 <description>Start SPI transaction</description>
96578 <description>Start SPI transaction</description>
96584 <description>Trigger task</description>
96593 <description>Stop SPI transaction</description>
96601 <description>Stop SPI transaction</description>
96607 <description>Trigger task</description>
96616 <description>Suspend SPI transaction</description>
96624 <description>Suspend SPI transaction</description>
96630 <description>Trigger task</description>
96639 <description>Resume SPI transaction</description>
96647 <description>Resume SPI transaction</description>
96653 <description>Trigger task</description>
96662 <description>Peripheral tasks.</description>
96668 <description>Peripheral tasks.</description>
96676 …<description>Description collection: Enables the MATCH[n] event by setting the ENABLE[n] bit in th…
96684 …<description>Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register.</desc…
96690 <description>Trigger task</description>
96701 …<description>Description collection: Disables the MATCH[n] event by clearing the ENABLE[n] bit in …
96709 …<description>Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register.</de…
96715 <description>Trigger task</description>
96726 <description>Subscribe configuration for task START</description>
96734 <description>DPPI channel that task START will subscribe to</description>
96745 <description>Disable subscription</description>
96750 <description>Enable subscription</description>
96759 <description>Subscribe configuration for task STOP</description>
96767 <description>DPPI channel that task STOP will subscribe to</description>
96778 <description>Disable subscription</description>
96783 <description>Enable subscription</description>
96792 <description>Subscribe configuration for task SUSPEND</description>
96800 <description>DPPI channel that task SUSPEND will subscribe to</description>
96811 <description>Disable subscription</description>
96816 <description>Enable subscription</description>
96825 <description>Subscribe configuration for task RESUME</description>
96833 <description>DPPI channel that task RESUME will subscribe to</description>
96844 <description>Disable subscription</description>
96849 <description>Enable subscription</description>
96858 <description>Subscribe configuration for tasks</description>
96864 <description>Subscribe configuration for tasks</description>
96872 … <description>Description collection: Subscribe configuration for task ENABLEMATCH[n]</description>
96880 <description>DPPI channel that task ENABLEMATCH[n] will subscribe to</description>
96891 <description>Disable subscription</description>
96896 <description>Enable subscription</description>
96907 …<description>Description collection: Subscribe configuration for task DISABLEMATCH[n]</description>
96915 … <description>DPPI channel that task DISABLEMATCH[n] will subscribe to</description>
96926 <description>Disable subscription</description>
96931 <description>Enable subscription</description>
96942 <description>SPI transaction has started</description>
96950 <description>SPI transaction has started</description>
96956 <description>Event not generated</description>
96961 <description>Event generated</description>
96970 <description>SPI transaction has stopped</description>
96978 <description>SPI transaction has stopped</description>
96984 <description>Event not generated</description>
96989 <description>Event generated</description>
96998 <description>End of RXD buffer and TXD buffer reached</description>
97006 <description>End of RXD buffer and TXD buffer reached</description>
97012 <description>Event not generated</description>
97017 <description>Event generated</description>
97026 <description>Peripheral events.</description>
97032 <description>Peripheral events.</description>
97038 <description>Generated after all MAXCNT bytes have been transferred</description>
97046 <description>Generated after all MAXCNT bytes have been transferred</description>
97052 <description>Event not generated</description>
97057 <description>Event generated</description>
97066 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
97074 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
97080 <description>Event not generated</description>
97085 <description>Event generated</description>
97094 <description>An error occured during the bus transfer.</description>
97102 <description>An error occured during the bus transfer.</description>
97108 <description>Event not generated</description>
97113 <description>Event generated</description>
97124 … <description>Description collection: Pattern match is detected on the DMA data bus.</description>
97132 <description>Pattern match is detected on the DMA data bus.</description>
97138 <description>Event not generated</description>
97143 <description>Event generated</description>
97153 <description>Peripheral events.</description>
97159 <description>Generated after all MAXCNT bytes have been transferred</description>
97167 <description>Generated after all MAXCNT bytes have been transferred</description>
97173 <description>Event not generated</description>
97178 <description>Event generated</description>
97187 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
97195 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
97201 <description>Event not generated</description>
97206 <description>Event generated</description>
97215 <description>An error occured during the bus transfer.</description>
97223 <description>An error occured during the bus transfer.</description>
97229 <description>Event not generated</description>
97234 <description>Event generated</description>
97245 <description>Publish configuration for event STARTED</description>
97253 <description>DPPI channel that event STARTED will publish to</description>
97264 <description>Disable publishing</description>
97269 <description>Enable publishing</description>
97278 <description>Publish configuration for event STOPPED</description>
97286 <description>DPPI channel that event STOPPED will publish to</description>
97297 <description>Disable publishing</description>
97302 <description>Enable publishing</description>
97311 <description>Publish configuration for event END</description>
97319 <description>DPPI channel that event END will publish to</description>
97330 <description>Disable publishing</description>
97335 <description>Enable publishing</description>
97344 <description>Publish configuration for events</description>
97350 <description>Publish configuration for events</description>
97356 <description>Publish configuration for event END</description>
97364 <description>DPPI channel that event END will publish to</description>
97375 <description>Disable publishing</description>
97380 <description>Enable publishing</description>
97389 <description>Publish configuration for event READY</description>
97397 <description>DPPI channel that event READY will publish to</description>
97408 <description>Disable publishing</description>
97413 <description>Enable publishing</description>
97422 <description>Publish configuration for event BUSERROR</description>
97430 <description>DPPI channel that event BUSERROR will publish to</description>
97441 <description>Disable publishing</description>
97446 <description>Enable publishing</description>
97457 … <description>Description collection: Publish configuration for event MATCH[n]</description>
97465 <description>DPPI channel that event MATCH[n] will publish to</description>
97476 <description>Disable publishing</description>
97481 <description>Enable publishing</description>
97491 <description>Publish configuration for events</description>
97497 <description>Publish configuration for event END</description>
97505 <description>DPPI channel that event END will publish to</description>
97516 <description>Disable publishing</description>
97521 <description>Enable publishing</description>
97530 <description>Publish configuration for event READY</description>
97538 <description>DPPI channel that event READY will publish to</description>
97549 <description>Disable publishing</description>
97554 <description>Enable publishing</description>
97563 <description>Publish configuration for event BUSERROR</description>
97571 <description>DPPI channel that event BUSERROR will publish to</description>
97582 <description>Disable publishing</description>
97587 <description>Enable publishing</description>
97598 <description>Shortcuts between local events and tasks</description>
97606 <description>Shortcut between event END and task START</description>
97612 <description>Disable shortcut</description>
97617 <description>Enable shortcut</description>
97624 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows daisy-ch…
97630 <description>Disable shortcut</description>
97635 <description>Enable shortcut</description>
97642 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows daisy-ch…
97648 <description>Disable shortcut</description>
97653 <description>Enable shortcut</description>
97660 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows daisy-ch…
97666 <description>Disable shortcut</description>
97671 <description>Enable shortcut</description>
97678 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows daisy-ch…
97684 <description>Disable shortcut</description>
97689 <description>Enable shortcut</description>
97696 … <description>Shortcut between event DMA.RX.MATCH[0] and task DMA.RX.DISABLEMATCH[0]</description>
97702 <description>Disable shortcut</description>
97707 <description>Enable shortcut</description>
97714 … <description>Shortcut between event DMA.RX.MATCH[1] and task DMA.RX.DISABLEMATCH[1]</description>
97720 <description>Disable shortcut</description>
97725 <description>Enable shortcut</description>
97732 … <description>Shortcut between event DMA.RX.MATCH[2] and task DMA.RX.DISABLEMATCH[2]</description>
97738 <description>Disable shortcut</description>
97743 <description>Enable shortcut</description>
97750 … <description>Shortcut between event DMA.RX.MATCH[3] and task DMA.RX.DISABLEMATCH[3]</description>
97756 <description>Disable shortcut</description>
97761 <description>Enable shortcut</description>
97770 <description>Enable interrupt</description>
97778 <description>Write '1' to enable interrupt for event STARTED</description>
97785 <description>Read: Disabled</description>
97790 <description>Read: Enabled</description>
97798 <description>Enable</description>
97805 <description>Write '1' to enable interrupt for event STOPPED</description>
97812 <description>Read: Disabled</description>
97817 <description>Read: Enabled</description>
97825 <description>Enable</description>
97832 <description>Write '1' to enable interrupt for event END</description>
97839 <description>Read: Disabled</description>
97844 <description>Read: Enabled</description>
97852 <description>Enable</description>
97859 <description>Write '1' to enable interrupt for event DMARXEND</description>
97866 <description>Read: Disabled</description>
97871 <description>Read: Enabled</description>
97879 <description>Enable</description>
97886 <description>Write '1' to enable interrupt for event DMARXREADY</description>
97893 <description>Read: Disabled</description>
97898 <description>Read: Enabled</description>
97906 <description>Enable</description>
97913 <description>Write '1' to enable interrupt for event DMARXBUSERROR</description>
97920 <description>Read: Disabled</description>
97925 <description>Read: Enabled</description>
97933 <description>Enable</description>
97940 <description>Write '1' to enable interrupt for event DMARXMATCH[0]</description>
97947 <description>Read: Disabled</description>
97952 <description>Read: Enabled</description>
97960 <description>Enable</description>
97967 <description>Write '1' to enable interrupt for event DMARXMATCH[1]</description>
97974 <description>Read: Disabled</description>
97979 <description>Read: Enabled</description>
97987 <description>Enable</description>
97994 <description>Write '1' to enable interrupt for event DMARXMATCH[2]</description>
98001 <description>Read: Disabled</description>
98006 <description>Read: Enabled</description>
98014 <description>Enable</description>
98021 <description>Write '1' to enable interrupt for event DMARXMATCH[3]</description>
98028 <description>Read: Disabled</description>
98033 <description>Read: Enabled</description>
98041 <description>Enable</description>
98048 <description>Write '1' to enable interrupt for event DMATXEND</description>
98055 <description>Read: Disabled</description>
98060 <description>Read: Enabled</description>
98068 <description>Enable</description>
98075 <description>Write '1' to enable interrupt for event DMATXREADY</description>
98082 <description>Read: Disabled</description>
98087 <description>Read: Enabled</description>
98095 <description>Enable</description>
98102 <description>Write '1' to enable interrupt for event DMATXBUSERROR</description>
98109 <description>Read: Disabled</description>
98114 <description>Read: Enabled</description>
98122 <description>Enable</description>
98131 <description>Disable interrupt</description>
98139 <description>Write '1' to disable interrupt for event STARTED</description>
98146 <description>Read: Disabled</description>
98151 <description>Read: Enabled</description>
98159 <description>Disable</description>
98166 <description>Write '1' to disable interrupt for event STOPPED</description>
98173 <description>Read: Disabled</description>
98178 <description>Read: Enabled</description>
98186 <description>Disable</description>
98193 <description>Write '1' to disable interrupt for event END</description>
98200 <description>Read: Disabled</description>
98205 <description>Read: Enabled</description>
98213 <description>Disable</description>
98220 <description>Write '1' to disable interrupt for event DMARXEND</description>
98227 <description>Read: Disabled</description>
98232 <description>Read: Enabled</description>
98240 <description>Disable</description>
98247 <description>Write '1' to disable interrupt for event DMARXREADY</description>
98254 <description>Read: Disabled</description>
98259 <description>Read: Enabled</description>
98267 <description>Disable</description>
98274 <description>Write '1' to disable interrupt for event DMARXBUSERROR</description>
98281 <description>Read: Disabled</description>
98286 <description>Read: Enabled</description>
98294 <description>Disable</description>
98301 <description>Write '1' to disable interrupt for event DMARXMATCH[0]</description>
98308 <description>Read: Disabled</description>
98313 <description>Read: Enabled</description>
98321 <description>Disable</description>
98328 <description>Write '1' to disable interrupt for event DMARXMATCH[1]</description>
98335 <description>Read: Disabled</description>
98340 <description>Read: Enabled</description>
98348 <description>Disable</description>
98355 <description>Write '1' to disable interrupt for event DMARXMATCH[2]</description>
98362 <description>Read: Disabled</description>
98367 <description>Read: Enabled</description>
98375 <description>Disable</description>
98382 <description>Write '1' to disable interrupt for event DMARXMATCH[3]</description>
98389 <description>Read: Disabled</description>
98394 <description>Read: Enabled</description>
98402 <description>Disable</description>
98409 <description>Write '1' to disable interrupt for event DMATXEND</description>
98416 <description>Read: Disabled</description>
98421 <description>Read: Enabled</description>
98429 <description>Disable</description>
98436 <description>Write '1' to disable interrupt for event DMATXREADY</description>
98443 <description>Read: Disabled</description>
98448 <description>Read: Enabled</description>
98456 <description>Disable</description>
98463 <description>Write '1' to disable interrupt for event DMATXBUSERROR</description>
98470 <description>Read: Disabled</description>
98475 <description>Read: Enabled</description>
98483 <description>Disable</description>
98492 <description>Enable SPIM</description>
98500 <description>Enable or disable SPIM</description>
98506 <description>Disable SPIM</description>
98511 <description>Enable SPIM</description>
98520 <description>The prescaler is used to set the SPI frequency.</description>
98528 <description>Core clock to SCK divisor</description>
98536 <description>Configuration register</description>
98544 <description>Bit order</description>
98550 <description>Most significant bit shifted out first</description>
98555 <description>Least significant bit shifted out first</description>
98562 <description>Serial clock (SCK) phase</description>
98568 … <description>Sample on leading edge of clock, shift serial data on trailing edge</description>
98573 … <description>Sample on trailing edge of clock, shift serial data on leading edge</description>
98580 <description>Serial clock (SCK) polarity</description>
98586 <description>Active high</description>
98591 <description>Active low</description>
98600 …description>Stall status for EasyDMA RAM accesses. The fields in this register are set to STALL by…
98608 <description>Stall status for EasyDMA RAM reads</description>
98614 <description>No stall</description>
98619 <description>A stall has occurred</description>
98628 <description>Unspecified</description>
98634 <description>Sample delay for input serial data on MISO</description>
98642 …description>Sample delay for input serial data on MISO. The value specifies the number of SPIM cor…
98650 …description>Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, t…
98658 …description>Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, t…
98667 <description>DCX configuration</description>
98675 …description>This register specifies the number of command bytes preceding the data bytes. The PSEL…
98683 <description>Polarity of CSN output</description>
98691 <description>Polarity of CSN output</description>
98697 <description>Active low (idle state high)</description>
98702 <description>Active high (idle state low)</description>
98711 …<description>Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MA…
98719 …<description>Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MA…
98727 <description>Unspecified</description>
98733 <description>Pin select for SCK</description>
98741 <description>Pin number</description>
98747 <description>Port number</description>
98753 <description>Connection</description>
98759 <description>Disconnect</description>
98764 <description>Connect</description>
98773 <description>Pin select for MOSI signal</description>
98781 <description>Pin number</description>
98787 <description>Port number</description>
98793 <description>Connection</description>
98799 <description>Disconnect</description>
98804 <description>Connect</description>
98813 <description>Pin select for MISO signal</description>
98821 <description>Pin number</description>
98827 <description>Port number</description>
98833 <description>Connection</description>
98839 <description>Disconnect</description>
98844 <description>Connect</description>
98853 <description>Pin select for DCX signal</description>
98861 <description>Pin number</description>
98867 <description>Port number</description>
98873 <description>Connection</description>
98879 <description>Disconnect</description>
98884 <description>Connect</description>
98893 <description>Pin select for CSN</description>
98901 <description>Pin number</description>
98907 <description>Port number</description>
98913 <description>Connection</description>
98919 <description>Disconnect</description>
98924 <description>Connect</description>
98934 <description>Unspecified</description>
98940 <description>Unspecified</description>
98946 <description>RAM buffer start address</description>
98954 …<description>RAM buffer start address for this EasyDMA channel. This address is a word aligned Dat…
98962 <description>Maximum number of bytes in channel buffer</description>
98970 <description>Maximum number of bytes in channel buffer</description>
98978 …<description>Number of bytes transferred in the last transaction, updated after the END event. Als…
98986 …<description>Number of bytes transferred in the last transaction. In case of NACK error, includes …
98994 <description>Number of bytes transferred in the current transaction</description>
99002 …<description>Number of bytes transferred in the current transaction. Continuously updated.</descri…
99010 <description>EasyDMA list type</description>
99018 <description>List type</description>
99024 <description>Disable EasyDMA list</description>
99029 <description>Use array list</description>
99038 <description>Terminate the transaction if a BUSERROR event is detected.</description>
99051 <description>Disable</description>
99056 <description>Enable</description>
99065 … <description>Address of transaction that generated the last BUSERROR event.</description>
99080 … <description>Registers to control the behavior of the pattern matcher engine</description>
99086 <description>Configure individual match events</description>
99094 <description>Enable match filter 0</description>
99100 <description>Match filter disabled</description>
99105 <description>Match filter enabled</description>
99112 <description>Enable match filter 1</description>
99118 <description>Match filter disabled</description>
99123 <description>Match filter enabled</description>
99130 <description>Enable match filter 2</description>
99136 <description>Match filter disabled</description>
99141 <description>Match filter enabled</description>
99148 <description>Enable match filter 3</description>
99154 <description>Match filter disabled</description>
99159 <description>Match filter enabled</description>
99166 <description>Configure match filter 0 as one-shot or sticky</description>
99172 <description>Match filter stays enabled until disabled by task</description>
99177 … <description>Match filter stays enabled until next data word is received</description>
99184 <description>Configure match filter 1 as one-shot or sticky</description>
99190 <description>Match filter stays enabled until disabled by task</description>
99195 … <description>Match filter stays enabled until next data word is received</description>
99202 <description>Configure match filter 2 as one-shot or sticky</description>
99208 <description>Match filter stays enabled until disabled by task</description>
99213 … <description>Match filter stays enabled until next data word is received</description>
99220 <description>Configure match filter 3 as one-shot or sticky</description>
99226 <description>Match filter stays enabled until disabled by task</description>
99231 … <description>Match filter stays enabled until next data word is received</description>
99242 …<description>Description collection: The data to look for - any match will trigger the MATCH[n] ev…
99250 <description>Data to look for</description>
99260 <description>Unspecified</description>
99266 <description>RAM buffer start address</description>
99274 …<description>RAM buffer start address for this EasyDMA channel. This address is a word aligned Dat…
99282 <description>Maximum number of bytes in channel buffer</description>
99290 <description>Maximum number of bytes in channel buffer</description>
99298 …<description>Number of bytes transferred in the last transaction, updated after the END event. Als…
99306 …<description>Number of bytes transferred in the last transaction. In case of NACK error, includes …
99314 <description>Number of bytes transferred in the current transaction</description>
99322 …<description>Number of bytes transferred in the current transaction. Continuously updated.</descri…
99330 <description>EasyDMA list type</description>
99338 <description>List type</description>
99344 <description>Disable EasyDMA list</description>
99349 <description>Use array list</description>
99358 <description>Terminate the transaction if a BUSERROR event is detected.</description>
99371 <description>Disable</description>
99376 <description>Enable</description>
99385 … <description>Address of transaction that generated the last BUSERROR event.</description>
99404 <description>UART with EasyDMA 0</description>
99424 <description>Flush RX FIFO into RX buffer</description>
99432 <description>Flush RX FIFO into RX buffer</description>
99438 <description>Trigger task</description>
99447 <description>Peripheral tasks.</description>
99453 <description>Peripheral tasks.</description>
99459 …<description>Starts operation using easyDMA to load the values. See peripheral description for ope…
99467 …<description>Starts operation using easyDMA to load the values. See peripheral description for ope…
99473 <description>Trigger task</description>
99482 … <description>Stops operation using easyDMA. This does not trigger an END event.</description>
99490 … <description>Stops operation using easyDMA. This does not trigger an END event.</description>
99496 <description>Trigger task</description>
99507 …<description>Description collection: Enables the MATCH[n] event by setting the ENABLE[n] bit in th…
99515 …<description>Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register.</desc…
99521 <description>Trigger task</description>
99532 …<description>Description collection: Disables the MATCH[n] event by clearing the ENABLE[n] bit in …
99540 …<description>Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register.</de…
99546 <description>Trigger task</description>
99556 <description>Peripheral tasks.</description>
99562 …<description>Starts operation using easyDMA to load the values. See peripheral description for ope…
99570 …<description>Starts operation using easyDMA to load the values. See peripheral description for ope…
99576 <description>Trigger task</description>
99585 … <description>Stops operation using easyDMA. This does not trigger an END event.</description>
99593 … <description>Stops operation using easyDMA. This does not trigger an END event.</description>
99599 <description>Trigger task</description>
99610 <description>Subscribe configuration for task FLUSHRX</description>
99618 <description>DPPI channel that task FLUSHRX will subscribe to</description>
99629 <description>Disable subscription</description>
99634 <description>Enable subscription</description>
99643 <description>Subscribe configuration for tasks</description>
99649 <description>Subscribe configuration for tasks</description>
99655 <description>Subscribe configuration for task START</description>
99663 <description>DPPI channel that task START will subscribe to</description>
99674 <description>Disable subscription</description>
99679 <description>Enable subscription</description>
99688 <description>Subscribe configuration for task STOP</description>
99696 <description>DPPI channel that task STOP will subscribe to</description>
99707 <description>Disable subscription</description>
99712 <description>Enable subscription</description>
99723 … <description>Description collection: Subscribe configuration for task ENABLEMATCH[n]</description>
99731 <description>DPPI channel that task ENABLEMATCH[n] will subscribe to</description>
99742 <description>Disable subscription</description>
99747 <description>Enable subscription</description>
99758 …<description>Description collection: Subscribe configuration for task DISABLEMATCH[n]</description>
99766 … <description>DPPI channel that task DISABLEMATCH[n] will subscribe to</description>
99777 <description>Disable subscription</description>
99782 <description>Enable subscription</description>
99792 <description>Subscribe configuration for tasks</description>
99798 <description>Subscribe configuration for task START</description>
99806 <description>DPPI channel that task START will subscribe to</description>
99817 <description>Disable subscription</description>
99822 <description>Enable subscription</description>
99831 <description>Subscribe configuration for task STOP</description>
99839 <description>DPPI channel that task STOP will subscribe to</description>
99850 <description>Disable subscription</description>
99855 <description>Enable subscription</description>
99866 <description>CTS is activated (set low). Clear To Send.</description>
99874 <description>CTS is activated (set low). Clear To Send.</description>
99880 <description>Event not generated</description>
99885 <description>Event generated</description>
99894 <description>CTS is deactivated (set high). Not Clear To Send.</description>
99902 <description>CTS is deactivated (set high). Not Clear To Send.</description>
99908 <description>Event not generated</description>
99913 <description>Event generated</description>
99922 <description>Data sent from TXD</description>
99930 <description>Data sent from TXD</description>
99936 <description>Event not generated</description>
99941 <description>Event generated</description>
99950 … <description>Data received in RXD (but potentially not yet transferred to Data RAM)</description>
99958 … <description>Data received in RXD (but potentially not yet transferred to Data RAM)</description>
99964 <description>Event not generated</description>
99969 <description>Event generated</description>
99978 <description>Error detected</description>
99986 <description>Error detected</description>
99992 <description>Event not generated</description>
99997 <description>Event generated</description>
100006 <description>Receiver timeout</description>
100014 <description>Receiver timeout</description>
100020 <description>Event not generated</description>
100025 <description>Event generated</description>
100034 <description>Transmitter stopped</description>
100042 <description>Transmitter stopped</description>
100048 <description>Event not generated</description>
100053 <description>Event generated</description>
100062 <description>Peripheral events.</description>
100068 <description>Peripheral events.</description>
100074 <description>Generated after all MAXCNT bytes have been transferred</description>
100082 <description>Generated after all MAXCNT bytes have been transferred</description>
100088 <description>Event not generated</description>
100093 <description>Event generated</description>
100102 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
100110 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
100116 <description>Event not generated</description>
100121 <description>Event generated</description>
100130 <description>An error occured during the bus transfer.</description>
100138 <description>An error occured during the bus transfer.</description>
100144 <description>Event not generated</description>
100149 <description>Event generated</description>
100160 … <description>Description collection: Pattern match is detected on the DMA data bus.</description>
100168 <description>Pattern match is detected on the DMA data bus.</description>
100174 <description>Event not generated</description>
100179 <description>Event generated</description>
100189 <description>Peripheral events.</description>
100195 <description>Generated after all MAXCNT bytes have been transferred</description>
100203 <description>Generated after all MAXCNT bytes have been transferred</description>
100209 <description>Event not generated</description>
100214 <description>Event generated</description>
100223 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
100231 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
100237 <description>Event not generated</description>
100242 <description>Event generated</description>
100251 <description>An error occured during the bus transfer.</description>
100259 <description>An error occured during the bus transfer.</description>
100265 <description>Event not generated</description>
100270 <description>Event generated</description>
100281 <description>Timed out due to bus being idle while receiving data.</description>
100289 <description>Timed out due to bus being idle while receiving data.</description>
100295 <description>Event not generated</description>
100300 <description>Event generated</description>
100309 <description>Publish configuration for event CTS</description>
100317 <description>DPPI channel that event CTS will publish to</description>
100328 <description>Disable publishing</description>
100333 <description>Enable publishing</description>
100342 <description>Publish configuration for event NCTS</description>
100350 <description>DPPI channel that event NCTS will publish to</description>
100361 <description>Disable publishing</description>
100366 <description>Enable publishing</description>
100375 <description>Publish configuration for event TXDRDY</description>
100383 <description>DPPI channel that event TXDRDY will publish to</description>
100394 <description>Disable publishing</description>
100399 <description>Enable publishing</description>
100408 <description>Publish configuration for event RXDRDY</description>
100416 <description>DPPI channel that event RXDRDY will publish to</description>
100427 <description>Disable publishing</description>
100432 <description>Enable publishing</description>
100441 <description>Publish configuration for event ERROR</description>
100449 <description>DPPI channel that event ERROR will publish to</description>
100460 <description>Disable publishing</description>
100465 <description>Enable publishing</description>
100474 <description>Publish configuration for event RXTO</description>
100482 <description>DPPI channel that event RXTO will publish to</description>
100493 <description>Disable publishing</description>
100498 <description>Enable publishing</description>
100507 <description>Publish configuration for event TXSTOPPED</description>
100515 <description>DPPI channel that event TXSTOPPED will publish to</description>
100526 <description>Disable publishing</description>
100531 <description>Enable publishing</description>
100540 <description>Publish configuration for events</description>
100546 <description>Publish configuration for events</description>
100552 <description>Publish configuration for event END</description>
100560 <description>DPPI channel that event END will publish to</description>
100571 <description>Disable publishing</description>
100576 <description>Enable publishing</description>
100585 <description>Publish configuration for event READY</description>
100593 <description>DPPI channel that event READY will publish to</description>
100604 <description>Disable publishing</description>
100609 <description>Enable publishing</description>
100618 <description>Publish configuration for event BUSERROR</description>
100626 <description>DPPI channel that event BUSERROR will publish to</description>
100637 <description>Disable publishing</description>
100642 <description>Enable publishing</description>
100653 … <description>Description collection: Publish configuration for event MATCH[n]</description>
100661 <description>DPPI channel that event MATCH[n] will publish to</description>
100672 <description>Disable publishing</description>
100677 <description>Enable publishing</description>
100687 <description>Publish configuration for events</description>
100693 <description>Publish configuration for event END</description>
100701 <description>DPPI channel that event END will publish to</description>
100712 <description>Disable publishing</description>
100717 <description>Enable publishing</description>
100726 <description>Publish configuration for event READY</description>
100734 <description>DPPI channel that event READY will publish to</description>
100745 <description>Disable publishing</description>
100750 <description>Enable publishing</description>
100759 <description>Publish configuration for event BUSERROR</description>
100767 <description>DPPI channel that event BUSERROR will publish to</description>
100778 <description>Disable publishing</description>
100783 <description>Enable publishing</description>
100794 <description>Publish configuration for event FRAMETIMEOUT</description>
100802 <description>DPPI channel that event FRAMETIMEOUT will publish to</description>
100813 <description>Disable publishing</description>
100818 <description>Enable publishing</description>
100827 <description>Shortcuts between local events and tasks</description>
100835 <description>Shortcut between event DMA.RX.END and task DMA.RX.START</description>
100841 <description>Disable shortcut</description>
100846 <description>Enable shortcut</description>
100853 <description>Shortcut between event DMA.RX.END and task DMA.RX.STOP</description>
100859 <description>Disable shortcut</description>
100864 <description>Enable shortcut</description>
100871 <description>Shortcut between event DMA.TX.END and task DMA.TX.STOP</description>
100877 <description>Disable shortcut</description>
100882 <description>Enable shortcut</description>
100889 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows daisy-ch…
100895 <description>Disable shortcut</description>
100900 <description>Enable shortcut</description>
100907 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows daisy-ch…
100913 <description>Disable shortcut</description>
100918 <description>Enable shortcut</description>
100925 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows daisy-ch…
100931 <description>Disable shortcut</description>
100936 <description>Enable shortcut</description>
100943 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows daisy-ch…
100949 <description>Disable shortcut</description>
100954 <description>Enable shortcut</description>
100961 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
100967 <description>Disable shortcut</description>
100972 <description>Enable shortcut</description>
100979 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
100985 <description>Disable shortcut</description>
100990 <description>Enable shortcut</description>
100997 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
101003 <description>Disable shortcut</description>
101008 <description>Enable shortcut</description>
101015 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
101021 <description>Disable shortcut</description>
101026 <description>Enable shortcut</description>
101033 <description>Shortcut between event FRAMETIMEOUT and task DMA.RX.STOP</description>
101039 <description>Disable shortcut</description>
101044 <description>Enable shortcut</description>
101053 <description>Enable or disable interrupt</description>
101061 <description>Enable or disable interrupt for event CTS</description>
101067 <description>Disable</description>
101072 <description>Enable</description>
101079 <description>Enable or disable interrupt for event NCTS</description>
101085 <description>Disable</description>
101090 <description>Enable</description>
101097 <description>Enable or disable interrupt for event TXDRDY</description>
101103 <description>Disable</description>
101108 <description>Enable</description>
101115 <description>Enable or disable interrupt for event RXDRDY</description>
101121 <description>Disable</description>
101126 <description>Enable</description>
101133 <description>Enable or disable interrupt for event ERROR</description>
101139 <description>Disable</description>
101144 <description>Enable</description>
101151 <description>Enable or disable interrupt for event RXTO</description>
101157 <description>Disable</description>
101162 <description>Enable</description>
101169 <description>Enable or disable interrupt for event TXSTOPPED</description>
101175 <description>Disable</description>
101180 <description>Enable</description>
101187 <description>Enable or disable interrupt for event DMARXEND</description>
101193 <description>Disable</description>
101198 <description>Enable</description>
101205 <description>Enable or disable interrupt for event DMARXREADY</description>
101211 <description>Disable</description>
101216 <description>Enable</description>
101223 <description>Enable or disable interrupt for event DMARXBUSERROR</description>
101229 <description>Disable</description>
101234 <description>Enable</description>
101241 <description>Enable or disable interrupt for event DMARXMATCH[0]</description>
101247 <description>Disable</description>
101252 <description>Enable</description>
101259 <description>Enable or disable interrupt for event DMARXMATCH[1]</description>
101265 <description>Disable</description>
101270 <description>Enable</description>
101277 <description>Enable or disable interrupt for event DMARXMATCH[2]</description>
101283 <description>Disable</description>
101288 <description>Enable</description>
101295 <description>Enable or disable interrupt for event DMARXMATCH[3]</description>
101301 <description>Disable</description>
101306 <description>Enable</description>
101313 <description>Enable or disable interrupt for event DMATXEND</description>
101319 <description>Disable</description>
101324 <description>Enable</description>
101331 <description>Enable or disable interrupt for event DMATXREADY</description>
101337 <description>Disable</description>
101342 <description>Enable</description>
101349 <description>Enable or disable interrupt for event DMATXBUSERROR</description>
101355 <description>Disable</description>
101360 <description>Enable</description>
101367 <description>Enable or disable interrupt for event FRAMETIMEOUT</description>
101373 <description>Disable</description>
101378 <description>Enable</description>
101387 <description>Enable interrupt</description>
101395 <description>Write '1' to enable interrupt for event CTS</description>
101402 <description>Read: Disabled</description>
101407 <description>Read: Enabled</description>
101415 <description>Enable</description>
101422 <description>Write '1' to enable interrupt for event NCTS</description>
101429 <description>Read: Disabled</description>
101434 <description>Read: Enabled</description>
101442 <description>Enable</description>
101449 <description>Write '1' to enable interrupt for event TXDRDY</description>
101456 <description>Read: Disabled</description>
101461 <description>Read: Enabled</description>
101469 <description>Enable</description>
101476 <description>Write '1' to enable interrupt for event RXDRDY</description>
101483 <description>Read: Disabled</description>
101488 <description>Read: Enabled</description>
101496 <description>Enable</description>
101503 <description>Write '1' to enable interrupt for event ERROR</description>
101510 <description>Read: Disabled</description>
101515 <description>Read: Enabled</description>
101523 <description>Enable</description>
101530 <description>Write '1' to enable interrupt for event RXTO</description>
101537 <description>Read: Disabled</description>
101542 <description>Read: Enabled</description>
101550 <description>Enable</description>
101557 <description>Write '1' to enable interrupt for event TXSTOPPED</description>
101564 <description>Read: Disabled</description>
101569 <description>Read: Enabled</description>
101577 <description>Enable</description>
101584 <description>Write '1' to enable interrupt for event DMARXEND</description>
101591 <description>Read: Disabled</description>
101596 <description>Read: Enabled</description>
101604 <description>Enable</description>
101611 <description>Write '1' to enable interrupt for event DMARXREADY</description>
101618 <description>Read: Disabled</description>
101623 <description>Read: Enabled</description>
101631 <description>Enable</description>
101638 <description>Write '1' to enable interrupt for event DMARXBUSERROR</description>
101645 <description>Read: Disabled</description>
101650 <description>Read: Enabled</description>
101658 <description>Enable</description>
101665 <description>Write '1' to enable interrupt for event DMARXMATCH[0]</description>
101672 <description>Read: Disabled</description>
101677 <description>Read: Enabled</description>
101685 <description>Enable</description>
101692 <description>Write '1' to enable interrupt for event DMARXMATCH[1]</description>
101699 <description>Read: Disabled</description>
101704 <description>Read: Enabled</description>
101712 <description>Enable</description>
101719 <description>Write '1' to enable interrupt for event DMARXMATCH[2]</description>
101726 <description>Read: Disabled</description>
101731 <description>Read: Enabled</description>
101739 <description>Enable</description>
101746 <description>Write '1' to enable interrupt for event DMARXMATCH[3]</description>
101753 <description>Read: Disabled</description>
101758 <description>Read: Enabled</description>
101766 <description>Enable</description>
101773 <description>Write '1' to enable interrupt for event DMATXEND</description>
101780 <description>Read: Disabled</description>
101785 <description>Read: Enabled</description>
101793 <description>Enable</description>
101800 <description>Write '1' to enable interrupt for event DMATXREADY</description>
101807 <description>Read: Disabled</description>
101812 <description>Read: Enabled</description>
101820 <description>Enable</description>
101827 <description>Write '1' to enable interrupt for event DMATXBUSERROR</description>
101834 <description>Read: Disabled</description>
101839 <description>Read: Enabled</description>
101847 <description>Enable</description>
101854 <description>Write '1' to enable interrupt for event FRAMETIMEOUT</description>
101861 <description>Read: Disabled</description>
101866 <description>Read: Enabled</description>
101874 <description>Enable</description>
101883 <description>Disable interrupt</description>
101891 <description>Write '1' to disable interrupt for event CTS</description>
101898 <description>Read: Disabled</description>
101903 <description>Read: Enabled</description>
101911 <description>Disable</description>
101918 <description>Write '1' to disable interrupt for event NCTS</description>
101925 <description>Read: Disabled</description>
101930 <description>Read: Enabled</description>
101938 <description>Disable</description>
101945 <description>Write '1' to disable interrupt for event TXDRDY</description>
101952 <description>Read: Disabled</description>
101957 <description>Read: Enabled</description>
101965 <description>Disable</description>
101972 <description>Write '1' to disable interrupt for event RXDRDY</description>
101979 <description>Read: Disabled</description>
101984 <description>Read: Enabled</description>
101992 <description>Disable</description>
101999 <description>Write '1' to disable interrupt for event ERROR</description>
102006 <description>Read: Disabled</description>
102011 <description>Read: Enabled</description>
102019 <description>Disable</description>
102026 <description>Write '1' to disable interrupt for event RXTO</description>
102033 <description>Read: Disabled</description>
102038 <description>Read: Enabled</description>
102046 <description>Disable</description>
102053 <description>Write '1' to disable interrupt for event TXSTOPPED</description>
102060 <description>Read: Disabled</description>
102065 <description>Read: Enabled</description>
102073 <description>Disable</description>
102080 <description>Write '1' to disable interrupt for event DMARXEND</description>
102087 <description>Read: Disabled</description>
102092 <description>Read: Enabled</description>
102100 <description>Disable</description>
102107 <description>Write '1' to disable interrupt for event DMARXREADY</description>
102114 <description>Read: Disabled</description>
102119 <description>Read: Enabled</description>
102127 <description>Disable</description>
102134 <description>Write '1' to disable interrupt for event DMARXBUSERROR</description>
102141 <description>Read: Disabled</description>
102146 <description>Read: Enabled</description>
102154 <description>Disable</description>
102161 <description>Write '1' to disable interrupt for event DMARXMATCH[0]</description>
102168 <description>Read: Disabled</description>
102173 <description>Read: Enabled</description>
102181 <description>Disable</description>
102188 <description>Write '1' to disable interrupt for event DMARXMATCH[1]</description>
102195 <description>Read: Disabled</description>
102200 <description>Read: Enabled</description>
102208 <description>Disable</description>
102215 <description>Write '1' to disable interrupt for event DMARXMATCH[2]</description>
102222 <description>Read: Disabled</description>
102227 <description>Read: Enabled</description>
102235 <description>Disable</description>
102242 <description>Write '1' to disable interrupt for event DMARXMATCH[3]</description>
102249 <description>Read: Disabled</description>
102254 <description>Read: Enabled</description>
102262 <description>Disable</description>
102269 <description>Write '1' to disable interrupt for event DMATXEND</description>
102276 <description>Read: Disabled</description>
102281 <description>Read: Enabled</description>
102289 <description>Disable</description>
102296 <description>Write '1' to disable interrupt for event DMATXREADY</description>
102303 <description>Read: Disabled</description>
102308 <description>Read: Enabled</description>
102316 <description>Disable</description>
102323 <description>Write '1' to disable interrupt for event DMATXBUSERROR</description>
102330 <description>Read: Disabled</description>
102335 <description>Read: Enabled</description>
102343 <description>Disable</description>
102350 <description>Write '1' to disable interrupt for event FRAMETIMEOUT</description>
102357 <description>Read: Disabled</description>
102362 <description>Read: Enabled</description>
102370 <description>Disable</description>
102379 <description>Error source</description>
102388 <description>Overrun error</description>
102395 <description>Read: error not present</description>
102400 <description>Read: error present</description>
102407 <description>Parity error</description>
102414 <description>Read: error not present</description>
102419 <description>Read: error present</description>
102426 <description>Framing error occurred</description>
102433 <description>Read: error not present</description>
102438 <description>Read: error present</description>
102445 <description>Break condition</description>
102452 <description>Read: error not present</description>
102457 <description>Read: error present</description>
102466 <description>Enable UART</description>
102474 <description>Enable or disable UARTE</description>
102480 <description>Disable UARTE</description>
102485 <description>Enable UARTE</description>
102494 <description>Baud rate. Accuracy depends on the HFCLK source selected.</description>
102502 <description>Baud rate</description>
102508 …<description>1200 baud (actual rate: 1205) when UARTE has 16 MHz peripheral clock frequency</descr…
102513 …<description>2400 baud (actual rate: 2396) when UARTE has 16 MHz peripheral clock frequency</descr…
102518 …<description>4800 baud (actual rate: 4808) when UARTE has 16 MHz peripheral clock frequency</descr…
102523 …<description>9600 baud (actual rate: 9598) when UARTE has 16 MHz peripheral clock frequency</descr…
102528 …<description>14400 baud (actual rate: 14401) when UARTE has 16 MHz peripheral clock frequency</des…
102533 …<description>19200 baud (actual rate: 19208) when UARTE has 16 MHz peripheral clock frequency</des…
102538 …<description>28800 baud (actual rate: 28777) when UARTE has 16 MHz peripheral clock frequency</des…
102543 … <description>31250 baud when UARTE has 16 MHz peripheral clock frequency</description>
102548 …<description>38400 baud (actual rate: 38369) when UARTE has 16 MHz peripheral clock frequency</des…
102553 …<description>56000 baud (actual rate: 55944) when UARTE has 16 MHz peripheral clock frequency</des…
102558 …<description>57600 baud (actual rate: 57554) when UARTE has 16 MHz peripheral clock frequency</des…
102563 …<description>76800 baud (actual rate: 76923) when UARTE has 16 MHz peripheral clock frequency</des…
102568 …<description>115200 baud (actual rate: 115108) when UARTE has 16 MHz peripheral clock frequency</d…
102573 …<description>230400 baud (actual rate: 231884) when UARTE has 16 MHz peripheral clock frequency</d…
102578 … <description>250000 baud when UARTE has 16 MHz peripheral clock frequency</description>
102583 …<description>460800 baud (actual rate: 457143) when UARTE has 16 MHz peripheral clock frequency</d…
102588 …<description>921600 baud (actual rate: 941176) when UARTE has 16 MHz peripheral clock frequency</d…
102593 … <description>1 megabaud when UARTE has 16 MHz peripheral clock frequency</description>
102602 …<description>Configuration of parity, hardware flow control, framesize, and packet timeout.</descr…
102610 <description>Hardware flow control</description>
102616 <description>Disabled</description>
102621 <description>Enabled</description>
102628 <description>Parity</description>
102634 <description>Exclude parity bit</description>
102639 <description>Include even parity bit</description>
102646 <description>Stop bits</description>
102652 <description>One stop bit</description>
102657 <description>Two stop bits</description>
102664 <description>Even or odd parity type</description>
102670 <description>Even parity</description>
102675 <description>Odd parity</description>
102682 <description>Set the data frame size</description>
102688 … <description>9 bit data frame size. 9th bit is treated as address bit.</description>
102693 <description>8 bit data frame size.</description>
102698 <description>7 bit data frame size.</description>
102703 <description>6 bit data frame size.</description>
102708 <description>5 bit data frame size.</description>
102713 <description>4 bit data frame size.</description>
102720 …<description>Select if data is trimmed from MSB or LSB end when the data frame size is less than 8…
102726 <description>Data is trimmed from MSB end.</description>
102731 <description>Data is trimmed from LSB end.</description>
102738 <description>Enable packet timeout.</description>
102744 <description>Packet timeout is disabled.</description>
102749 <description>Packet timeout is enabled.</description>
102754 <description>Packet timeout is disabled.</description>
102759 <description>Packet timeout is enabled.</description>
102768 … <description>Set the address of the UARTE for RX when used in 9 bit data frame mode.</description>
102776 <description>Set address</description>
102784 … <description>Set the number of UARTE bits to count before triggering packet timeout.</description>
102792 <description>Number of UARTE bits before timeout.</description>
102800 <description>Unspecified</description>
102806 <description>Pin select for TXD signal</description>
102814 <description>Pin number</description>
102820 <description>Port number</description>
102826 <description>Connection</description>
102832 <description>Disconnect</description>
102837 <description>Connect</description>
102846 <description>Pin select for CTS signal</description>
102854 <description>Pin number</description>
102860 <description>Port number</description>
102866 <description>Connection</description>
102872 <description>Disconnect</description>
102877 <description>Connect</description>
102886 <description>Pin select for RXD signal</description>
102894 <description>Pin number</description>
102900 <description>Port number</description>
102906 <description>Connection</description>
102912 <description>Disconnect</description>
102917 <description>Connect</description>
102926 <description>Pin select for RTS signal</description>
102934 <description>Pin number</description>
102940 <description>Port number</description>
102946 <description>Connection</description>
102952 <description>Disconnect</description>
102957 <description>Connect</description>
102967 <description>Unspecified</description>
102973 <description>Unspecified</description>
102979 <description>RAM buffer start address</description>
102987 …<description>RAM buffer start address for this EasyDMA channel. This address is a word aligned Dat…
102995 <description>Maximum number of bytes in channel buffer</description>
103003 <description>Maximum number of bytes in channel buffer</description>
103011 …<description>Number of bytes transferred in the last transaction, updated after the END event. Als…
103019 …<description>Number of bytes transferred in the last transaction. In case of NACK error, includes …
103027 <description>Number of bytes transferred in the current transaction</description>
103035 …<description>Number of bytes transferred in the current transaction. Continuously updated.</descri…
103043 <description>EasyDMA list type</description>
103051 <description>List type</description>
103057 <description>Disable EasyDMA list</description>
103062 <description>Use array list</description>
103071 <description>Terminate the transaction if a BUSERROR event is detected.</description>
103084 <description>Disable</description>
103089 <description>Enable</description>
103098 … <description>Address of transaction that generated the last BUSERROR event.</description>
103113 … <description>Registers to control the behavior of the pattern matcher engine</description>
103119 <description>Configure individual match events</description>
103127 <description>Enable match filter 0</description>
103133 <description>Match filter disabled</description>
103138 <description>Match filter enabled</description>
103145 <description>Enable match filter 1</description>
103151 <description>Match filter disabled</description>
103156 <description>Match filter enabled</description>
103163 <description>Enable match filter 2</description>
103169 <description>Match filter disabled</description>
103174 <description>Match filter enabled</description>
103181 <description>Enable match filter 3</description>
103187 <description>Match filter disabled</description>
103192 <description>Match filter enabled</description>
103199 <description>Configure match filter 0 as one-shot or continous</description>
103205 <description>Match filter stays enabled until disabled by task</description>
103210 … <description>Match filter stays enabled until next data word is received</description>
103217 <description>Configure match filter 1 as one-shot or continous</description>
103223 <description>Match filter stays enabled until disabled by task</description>
103228 … <description>Match filter stays enabled until next data word is received</description>
103235 <description>Configure match filter 2 as one-shot or continous</description>
103241 <description>Match filter stays enabled until disabled by task</description>
103246 … <description>Match filter stays enabled until next data word is received</description>
103253 <description>Configure match filter 3 as one-shot or continous</description>
103259 <description>Match filter stays enabled until disabled by task</description>
103264 … <description>Match filter stays enabled until next data word is received</description>
103275 …<description>Description collection: The data to look for - any match will trigger the MATCH[n] ev…
103283 <description>Data to look for</description>
103293 <description>Unspecified</description>
103299 <description>RAM buffer start address</description>
103307 …<description>RAM buffer start address for this EasyDMA channel. This address is a word aligned Dat…
103315 <description>Maximum number of bytes in channel buffer</description>
103323 <description>Maximum number of bytes in channel buffer</description>
103331 …<description>Number of bytes transferred in the last transaction, updated after the END event. Als…
103339 …<description>Number of bytes transferred in the last transaction. In case of NACK error, includes …
103347 <description>Number of bytes transferred in the current transaction</description>
103355 …<description>Number of bytes transferred in the current transaction. Continuously updated.</descri…
103363 <description>EasyDMA list type</description>
103371 <description>List type</description>
103377 <description>Disable EasyDMA list</description>
103382 <description>Use array list</description>
103391 <description>Terminate the transaction if a BUSERROR event is detected.</description>
103404 <description>Disable</description>
103409 <description>Enable</description>
103418 … <description>Address of transaction that generated the last BUSERROR event.</description>
103437 <description>Serial Peripheral Interface Master with EasyDMA 1</description>
103448 <description>VPR peripheral registers 1</description>
103459 <description>IPCT APB registers 1</description>
103471 <description>Distributed programmable peripheral interconnect controller 1</description>
103479 <description>MUTEX 1</description>
103486 <description>Real-time counter 0</description>
103505 <description>Start RTC counter</description>
103513 <description>Start RTC counter</description>
103519 <description>Trigger task</description>
103528 <description>Stop RTC counter</description>
103536 <description>Stop RTC counter</description>
103542 <description>Trigger task</description>
103551 <description>Clear RTC counter</description>
103559 <description>Clear RTC counter</description>
103565 <description>Trigger task</description>
103574 <description>Set counter to: maximum value - 0xF</description>
103582 <description>Set counter to: maximum value - 0xF</description>
103588 <description>Trigger task</description>
103599 <description>Description collection: Capture RTC counter to CC[n] register</description>
103607 <description>Capture RTC counter to CC[n] register</description>
103613 <description>Trigger task</description>
103622 <description>Subscribe configuration for task START</description>
103630 <description>DPPI channel that task START will subscribe to</description>
103641 <description>Disable subscription</description>
103646 <description>Enable subscription</description>
103655 <description>Subscribe configuration for task STOP</description>
103663 <description>DPPI channel that task STOP will subscribe to</description>
103674 <description>Disable subscription</description>
103679 <description>Enable subscription</description>
103688 <description>Subscribe configuration for task CLEAR</description>
103696 <description>DPPI channel that task CLEAR will subscribe to</description>
103707 <description>Disable subscription</description>
103712 <description>Enable subscription</description>
103721 <description>Subscribe configuration for task TRIGOVRFLW</description>
103729 <description>DPPI channel that task TRIGOVRFLW will subscribe to</description>
103740 <description>Disable subscription</description>
103745 <description>Enable subscription</description>
103756 … <description>Description collection: Subscribe configuration for task CAPTURE[n]</description>
103764 <description>DPPI channel that task CAPTURE[n] will subscribe to</description>
103775 <description>Disable subscription</description>
103780 <description>Enable subscription</description>
103789 <description>Event on counter increment</description>
103797 <description>Event on counter increment</description>
103803 <description>Event not generated</description>
103808 <description>Event generated</description>
103817 <description>Event on counter overflow</description>
103825 <description>Event on counter overflow</description>
103831 <description>Event not generated</description>
103836 <description>Event generated</description>
103847 <description>Description collection: Compare event on CC[n] match</description>
103855 <description>Compare event on CC[n] match</description>
103861 <description>Event not generated</description>
103866 <description>Event generated</description>
103875 <description>Publish configuration for event TICK</description>
103883 <description>DPPI channel that event TICK will publish to</description>
103894 <description>Disable publishing</description>
103899 <description>Enable publishing</description>
103908 <description>Publish configuration for event OVRFLW</description>
103916 <description>DPPI channel that event OVRFLW will publish to</description>
103927 <description>Disable publishing</description>
103932 <description>Enable publishing</description>
103943 … <description>Description collection: Publish configuration for event COMPARE[n]</description>
103951 <description>DPPI channel that event COMPARE[n] will publish to</description>
103962 <description>Disable publishing</description>
103967 <description>Enable publishing</description>
103976 <description>Shortcuts between local events and tasks</description>
103984 <description>Shortcut between event COMPARE[0] and task CLEAR</description>
103990 <description>Disable shortcut</description>
103995 <description>Enable shortcut</description>
104002 <description>Shortcut between event COMPARE[1] and task CLEAR</description>
104008 <description>Disable shortcut</description>
104013 <description>Enable shortcut</description>
104020 <description>Shortcut between event COMPARE[2] and task CLEAR</description>
104026 <description>Disable shortcut</description>
104031 <description>Enable shortcut</description>
104038 <description>Shortcut between event COMPARE[3] and task CLEAR</description>
104044 <description>Disable shortcut</description>
104049 <description>Enable shortcut</description>
104056 <description>Shortcut between event COMPARE[4] and task CLEAR</description>
104062 <description>Disable shortcut</description>
104067 <description>Enable shortcut</description>
104074 <description>Shortcut between event COMPARE[5] and task CLEAR</description>
104080 <description>Disable shortcut</description>
104085 <description>Enable shortcut</description>
104092 <description>Shortcut between event COMPARE[6] and task CLEAR</description>
104098 <description>Disable shortcut</description>
104103 <description>Enable shortcut</description>
104110 <description>Shortcut between event COMPARE[7] and task CLEAR</description>
104116 <description>Disable shortcut</description>
104121 <description>Enable shortcut</description>
104130 <description>Enable interrupt</description>
104138 <description>Write '1' to enable interrupt for event TICK</description>
104145 <description>Read: Disabled</description>
104150 <description>Read: Enabled</description>
104158 <description>Enable</description>
104165 <description>Write '1' to enable interrupt for event OVRFLW</description>
104172 <description>Read: Disabled</description>
104177 <description>Read: Enabled</description>
104185 <description>Enable</description>
104192 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
104199 <description>Read: Disabled</description>
104204 <description>Read: Enabled</description>
104212 <description>Enable</description>
104219 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
104226 <description>Read: Disabled</description>
104231 <description>Read: Enabled</description>
104239 <description>Enable</description>
104246 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
104253 <description>Read: Disabled</description>
104258 <description>Read: Enabled</description>
104266 <description>Enable</description>
104273 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
104280 <description>Read: Disabled</description>
104285 <description>Read: Enabled</description>
104293 <description>Enable</description>
104300 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
104307 <description>Read: Disabled</description>
104312 <description>Read: Enabled</description>
104320 <description>Enable</description>
104327 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
104334 <description>Read: Disabled</description>
104339 <description>Read: Enabled</description>
104347 <description>Enable</description>
104354 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
104361 <description>Read: Disabled</description>
104366 <description>Read: Enabled</description>
104374 <description>Enable</description>
104381 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
104388 <description>Read: Disabled</description>
104393 <description>Read: Enabled</description>
104401 <description>Enable</description>
104410 <description>Disable interrupt</description>
104418 <description>Write '1' to disable interrupt for event TICK</description>
104425 <description>Read: Disabled</description>
104430 <description>Read: Enabled</description>
104438 <description>Disable</description>
104445 <description>Write '1' to disable interrupt for event OVRFLW</description>
104452 <description>Read: Disabled</description>
104457 <description>Read: Enabled</description>
104465 <description>Disable</description>
104472 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
104479 <description>Read: Disabled</description>
104484 <description>Read: Enabled</description>
104492 <description>Disable</description>
104499 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
104506 <description>Read: Disabled</description>
104511 <description>Read: Enabled</description>
104519 <description>Disable</description>
104526 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
104533 <description>Read: Disabled</description>
104538 <description>Read: Enabled</description>
104546 <description>Disable</description>
104553 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
104560 <description>Read: Disabled</description>
104565 <description>Read: Enabled</description>
104573 <description>Disable</description>
104580 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
104587 <description>Read: Disabled</description>
104592 <description>Read: Enabled</description>
104600 <description>Disable</description>
104607 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
104614 <description>Read: Disabled</description>
104619 <description>Read: Enabled</description>
104627 <description>Disable</description>
104634 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
104641 <description>Read: Disabled</description>
104646 <description>Read: Enabled</description>
104654 <description>Disable</description>
104661 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
104668 <description>Read: Disabled</description>
104673 <description>Read: Enabled</description>
104681 <description>Disable</description>
104690 <description>Enable or disable event routing</description>
104698 <description>Enable or disable event routing for event TICK</description>
104704 <description>Disable</description>
104709 <description>Enable</description>
104716 <description>Enable or disable event routing for event OVRFLW</description>
104722 <description>Disable</description>
104727 <description>Enable</description>
104734 <description>Enable or disable event routing for event COMPARE[0]</description>
104740 <description>Disable</description>
104745 <description>Enable</description>
104752 <description>Enable or disable event routing for event COMPARE[1]</description>
104758 <description>Disable</description>
104763 <description>Enable</description>
104770 <description>Enable or disable event routing for event COMPARE[2]</description>
104776 <description>Disable</description>
104781 <description>Enable</description>
104788 <description>Enable or disable event routing for event COMPARE[3]</description>
104794 <description>Disable</description>
104799 <description>Enable</description>
104806 <description>Enable or disable event routing for event COMPARE[4]</description>
104812 <description>Disable</description>
104817 <description>Enable</description>
104824 <description>Enable or disable event routing for event COMPARE[5]</description>
104830 <description>Disable</description>
104835 <description>Enable</description>
104842 <description>Enable or disable event routing for event COMPARE[6]</description>
104848 <description>Disable</description>
104853 <description>Enable</description>
104860 <description>Enable or disable event routing for event COMPARE[7]</description>
104866 <description>Disable</description>
104871 <description>Enable</description>
104880 <description>Enable event routing</description>
104888 <description>Write '1' to enable event routing for event TICK</description>
104895 <description>Read: Disabled</description>
104900 <description>Read: Enabled</description>
104908 <description>Enable</description>
104915 <description>Write '1' to enable event routing for event OVRFLW</description>
104922 <description>Read: Disabled</description>
104927 <description>Read: Enabled</description>
104935 <description>Enable</description>
104942 <description>Write '1' to enable event routing for event COMPARE[0]</description>
104949 <description>Read: Disabled</description>
104954 <description>Read: Enabled</description>
104962 <description>Enable</description>
104969 <description>Write '1' to enable event routing for event COMPARE[1]</description>
104976 <description>Read: Disabled</description>
104981 <description>Read: Enabled</description>
104989 <description>Enable</description>
104996 <description>Write '1' to enable event routing for event COMPARE[2]</description>
105003 <description>Read: Disabled</description>
105008 <description>Read: Enabled</description>
105016 <description>Enable</description>
105023 <description>Write '1' to enable event routing for event COMPARE[3]</description>
105030 <description>Read: Disabled</description>
105035 <description>Read: Enabled</description>
105043 <description>Enable</description>
105050 <description>Write '1' to enable event routing for event COMPARE[4]</description>
105057 <description>Read: Disabled</description>
105062 <description>Read: Enabled</description>
105070 <description>Enable</description>
105077 <description>Write '1' to enable event routing for event COMPARE[5]</description>
105084 <description>Read: Disabled</description>
105089 <description>Read: Enabled</description>
105097 <description>Enable</description>
105104 <description>Write '1' to enable event routing for event COMPARE[6]</description>
105111 <description>Read: Disabled</description>
105116 <description>Read: Enabled</description>
105124 <description>Enable</description>
105131 <description>Write '1' to enable event routing for event COMPARE[7]</description>
105138 <description>Read: Disabled</description>
105143 <description>Read: Enabled</description>
105151 <description>Enable</description>
105160 <description>Disable event routing</description>
105168 <description>Write '1' to disable event routing for event TICK</description>
105175 <description>Read: Disabled</description>
105180 <description>Read: Enabled</description>
105188 <description>Disable</description>
105195 <description>Write '1' to disable event routing for event OVRFLW</description>
105202 <description>Read: Disabled</description>
105207 <description>Read: Enabled</description>
105215 <description>Disable</description>
105222 <description>Write '1' to disable event routing for event COMPARE[0]</description>
105229 <description>Read: Disabled</description>
105234 <description>Read: Enabled</description>
105242 <description>Disable</description>
105249 <description>Write '1' to disable event routing for event COMPARE[1]</description>
105256 <description>Read: Disabled</description>
105261 <description>Read: Enabled</description>
105269 <description>Disable</description>
105276 <description>Write '1' to disable event routing for event COMPARE[2]</description>
105283 <description>Read: Disabled</description>
105288 <description>Read: Enabled</description>
105296 <description>Disable</description>
105303 <description>Write '1' to disable event routing for event COMPARE[3]</description>
105310 <description>Read: Disabled</description>
105315 <description>Read: Enabled</description>
105323 <description>Disable</description>
105330 <description>Write '1' to disable event routing for event COMPARE[4]</description>
105337 <description>Read: Disabled</description>
105342 <description>Read: Enabled</description>
105350 <description>Disable</description>
105357 <description>Write '1' to disable event routing for event COMPARE[5]</description>
105364 <description>Read: Disabled</description>
105369 <description>Read: Enabled</description>
105377 <description>Disable</description>
105384 <description>Write '1' to disable event routing for event COMPARE[6]</description>
105391 <description>Read: Disabled</description>
105396 <description>Read: Enabled</description>
105404 <description>Disable</description>
105411 <description>Write '1' to disable event routing for event COMPARE[7]</description>
105418 <description>Read: Disabled</description>
105423 <description>Read: Enabled</description>
105431 <description>Disable</description>
105440 <description>Current counter value</description>
105448 <description>Counter value</description>
105456 …<description>12-bit prescaler for counter frequency (32768 / (PRESCALER + 1)). Must be written whe…
105464 <description>Prescaler value</description>
105474 <description>Description collection: Compare register n</description>
105482 <description>Compare value</description>
105492 <description>Real-time counter 1</description>
105503 <description>Watchdog Timer 0</description>
105522 <description>Start WDT</description>
105530 <description>Start WDT</description>
105536 <description>Trigger task</description>
105545 <description>Stop WDT</description>
105553 <description>Stop WDT</description>
105559 <description>Trigger task</description>
105568 <description>Subscribe configuration for task START</description>
105576 <description>DPPI channel that task START will subscribe to</description>
105587 <description>Disable subscription</description>
105592 <description>Enable subscription</description>
105601 <description>Subscribe configuration for task STOP</description>
105609 <description>DPPI channel that task STOP will subscribe to</description>
105620 <description>Disable subscription</description>
105625 <description>Enable subscription</description>
105634 <description>Watchdog timeout</description>
105642 <description>Watchdog timeout</description>
105648 <description>Event not generated</description>
105653 <description>Event generated</description>
105662 <description>Watchdog stopped</description>
105670 <description>Watchdog stopped</description>
105676 <description>Event not generated</description>
105681 <description>Event generated</description>
105690 <description>Publish configuration for event TIMEOUT</description>
105698 <description>DPPI channel that event TIMEOUT will publish to</description>
105709 <description>Disable publishing</description>
105714 <description>Enable publishing</description>
105723 <description>Publish configuration for event STOPPED</description>
105731 <description>DPPI channel that event STOPPED will publish to</description>
105742 <description>Disable publishing</description>
105747 <description>Enable publishing</description>
105756 <description>Enable or disable interrupt</description>
105764 <description>Enable or disable interrupt for event TIMEOUT</description>
105770 <description>Disable</description>
105775 <description>Enable</description>
105782 <description>Enable or disable interrupt for event STOPPED</description>
105788 <description>Disable</description>
105793 <description>Enable</description>
105802 <description>Enable interrupt</description>
105810 <description>Write '1' to enable interrupt for event TIMEOUT</description>
105817 <description>Read: Disabled</description>
105822 <description>Read: Enabled</description>
105830 <description>Enable</description>
105837 <description>Write '1' to enable interrupt for event STOPPED</description>
105844 <description>Read: Disabled</description>
105849 <description>Read: Enabled</description>
105857 <description>Enable</description>
105866 <description>Disable interrupt</description>
105874 <description>Write '1' to disable interrupt for event TIMEOUT</description>
105881 <description>Read: Disabled</description>
105886 <description>Read: Enabled</description>
105894 <description>Disable</description>
105901 <description>Write '1' to disable interrupt for event STOPPED</description>
105908 <description>Read: Disabled</description>
105913 <description>Read: Enabled</description>
105921 <description>Disable</description>
105930 <description>Enable or disable interrupt</description>
105938 <description>Enable or disable interrupt for event TIMEOUT</description>
105944 <description>Disable</description>
105949 <description>Enable</description>
105956 <description>Enable or disable interrupt for event STOPPED</description>
105962 <description>Disable</description>
105967 <description>Enable</description>
105976 <description>Enable interrupt</description>
105984 <description>Write '1' to enable interrupt for event TIMEOUT</description>
105991 <description>Read: Disabled</description>
105996 <description>Read: Enabled</description>
106004 <description>Enable</description>
106011 <description>Write '1' to enable interrupt for event STOPPED</description>
106018 <description>Read: Disabled</description>
106023 <description>Read: Enabled</description>
106031 <description>Enable</description>
106040 <description>Disable interrupt</description>
106048 <description>Write '1' to disable interrupt for event TIMEOUT</description>
106055 <description>Read: Disabled</description>
106060 <description>Read: Enabled</description>
106068 <description>Disable</description>
106075 <description>Write '1' to disable interrupt for event STOPPED</description>
106082 <description>Read: Disabled</description>
106087 <description>Read: Enabled</description>
106095 <description>Disable</description>
106104 <description>Run status</description>
106112 <description>Indicates whether or not WDT is running</description>
106118 <description>Watchdog is not running</description>
106123 <description>Watchdog is running</description>
106132 <description>Request status</description>
106140 <description>Request status for RR[0] register</description>
106146 … <description>RR[0] register is not enabled, or are already requesting reload</description>
106151 … <description>RR[0] register is enabled, and are not yet requesting reload</description>
106158 <description>Request status for RR[1] register</description>
106164 … <description>RR[1] register is not enabled, or are already requesting reload</description>
106169 … <description>RR[1] register is enabled, and are not yet requesting reload</description>
106176 <description>Request status for RR[2] register</description>
106182 … <description>RR[2] register is not enabled, or are already requesting reload</description>
106187 … <description>RR[2] register is enabled, and are not yet requesting reload</description>
106194 <description>Request status for RR[3] register</description>
106200 … <description>RR[3] register is not enabled, or are already requesting reload</description>
106205 … <description>RR[3] register is enabled, and are not yet requesting reload</description>
106212 <description>Request status for RR[4] register</description>
106218 … <description>RR[4] register is not enabled, or are already requesting reload</description>
106223 … <description>RR[4] register is enabled, and are not yet requesting reload</description>
106230 <description>Request status for RR[5] register</description>
106236 … <description>RR[5] register is not enabled, or are already requesting reload</description>
106241 … <description>RR[5] register is enabled, and are not yet requesting reload</description>
106248 <description>Request status for RR[6] register</description>
106254 … <description>RR[6] register is not enabled, or are already requesting reload</description>
106259 … <description>RR[6] register is enabled, and are not yet requesting reload</description>
106266 <description>Request status for RR[7] register</description>
106272 … <description>RR[7] register is not enabled, or are already requesting reload</description>
106277 … <description>RR[7] register is enabled, and are not yet requesting reload</description>
106286 <description>Counter reload value</description>
106294 … <description>Counter reload value in number of cycles of the 32.768 kHz clock</description>
106302 <description>Enable register for reload request registers</description>
106310 <description>Enable or disable RR[0] register</description>
106316 <description>Disable RR[0] register</description>
106321 <description>Enable RR[0] register</description>
106328 <description>Enable or disable RR[1] register</description>
106334 <description>Disable RR[1] register</description>
106339 <description>Enable RR[1] register</description>
106346 <description>Enable or disable RR[2] register</description>
106352 <description>Disable RR[2] register</description>
106357 <description>Enable RR[2] register</description>
106364 <description>Enable or disable RR[3] register</description>
106370 <description>Disable RR[3] register</description>
106375 <description>Enable RR[3] register</description>
106382 <description>Enable or disable RR[4] register</description>
106388 <description>Disable RR[4] register</description>
106393 <description>Enable RR[4] register</description>
106400 <description>Enable or disable RR[5] register</description>
106406 <description>Disable RR[5] register</description>
106411 <description>Enable RR[5] register</description>
106418 <description>Enable or disable RR[6] register</description>
106424 <description>Disable RR[6] register</description>
106429 <description>Enable RR[6] register</description>
106436 <description>Enable or disable RR[7] register</description>
106442 <description>Disable RR[7] register</description>
106447 <description>Enable RR[7] register</description>
106456 <description>Configuration register</description>
106464 …<description>Configure WDT to either be paused, or kept running, while the CPU is sleeping</descri…
106470 <description>Pause WDT while the CPU is sleeping</description>
106475 <description>Keep WDT running while the CPU is sleeping</description>
106482 …<description>Configure WDT to either be paused, or kept running, while the CPU is halted by the de…
106488 <description>Pause WDT while the CPU is halted by the debugger</description>
106493 … <description>Keep WDT running while the CPU is halted by the debugger</description>
106500 <description>Allow stopping WDT</description>
106506 <description>Do not allow stopping WDT</description>
106511 <description>Allow stopping WDT</description>
106520 <description>Task stop enable</description>
106528 <description>Allow stopping WDT</description>
106534 <description>Value to allow stopping WDT</description>
106545 <description>Description collection: Reload request n</description>
106553 <description>Reload request register</description>
106559 <description>Value to request a reload of the watchdog timer</description>
106570 <description>Watchdog Timer 1</description>
106581 <description>Event generator unit</description>
106602 …<description>Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event…
106610 … <description>Trigger n for triggering the corresponding TRIGGERED[n] event</description>
106616 <description>Trigger task</description>
106627 … <description>Description collection: Subscribe configuration for task TRIGGER[n]</description>
106635 <description>DPPI channel that task TRIGGER[n] will subscribe to</description>
106646 <description>Disable subscription</description>
106651 <description>Enable subscription</description>
106662 …<description>Description collection: Event number n generated by triggering the corresponding TRIG…
106670 …<description>Event number n generated by triggering the corresponding TRIGGER[n] task</description>
106676 <description>Event not generated</description>
106681 <description>Event generated</description>
106692 … <description>Description collection: Publish configuration for event TRIGGERED[n]</description>
106700 <description>DPPI channel that event TRIGGERED[n] will publish to</description>
106711 <description>Disable publishing</description>
106716 <description>Enable publishing</description>
106725 <description>Enable or disable interrupt</description>
106733 <description>Enable or disable interrupt for event TRIGGERED[0]</description>
106739 <description>Disable</description>
106744 <description>Enable</description>
106751 <description>Enable or disable interrupt for event TRIGGERED[1]</description>
106757 <description>Disable</description>
106762 <description>Enable</description>
106769 <description>Enable or disable interrupt for event TRIGGERED[2]</description>
106775 <description>Disable</description>
106780 <description>Enable</description>
106787 <description>Enable or disable interrupt for event TRIGGERED[3]</description>
106793 <description>Disable</description>
106798 <description>Enable</description>
106805 <description>Enable or disable interrupt for event TRIGGERED[4]</description>
106811 <description>Disable</description>
106816 <description>Enable</description>
106823 <description>Enable or disable interrupt for event TRIGGERED[5]</description>
106829 <description>Disable</description>
106834 <description>Enable</description>
106841 <description>Enable or disable interrupt for event TRIGGERED[6]</description>
106847 <description>Disable</description>
106852 <description>Enable</description>
106859 <description>Enable or disable interrupt for event TRIGGERED[7]</description>
106865 <description>Disable</description>
106870 <description>Enable</description>
106877 <description>Enable or disable interrupt for event TRIGGERED[8]</description>
106883 <description>Disable</description>
106888 <description>Enable</description>
106895 <description>Enable or disable interrupt for event TRIGGERED[9]</description>
106901 <description>Disable</description>
106906 <description>Enable</description>
106913 <description>Enable or disable interrupt for event TRIGGERED[10]</description>
106919 <description>Disable</description>
106924 <description>Enable</description>
106931 <description>Enable or disable interrupt for event TRIGGERED[11]</description>
106937 <description>Disable</description>
106942 <description>Enable</description>
106949 <description>Enable or disable interrupt for event TRIGGERED[12]</description>
106955 <description>Disable</description>
106960 <description>Enable</description>
106967 <description>Enable or disable interrupt for event TRIGGERED[13]</description>
106973 <description>Disable</description>
106978 <description>Enable</description>
106985 <description>Enable or disable interrupt for event TRIGGERED[14]</description>
106991 <description>Disable</description>
106996 <description>Enable</description>
107003 <description>Enable or disable interrupt for event TRIGGERED[15]</description>
107009 <description>Disable</description>
107014 <description>Enable</description>
107023 <description>Enable interrupt</description>
107031 <description>Write '1' to enable interrupt for event TRIGGERED[0]</description>
107038 <description>Read: Disabled</description>
107043 <description>Read: Enabled</description>
107051 <description>Enable</description>
107058 <description>Write '1' to enable interrupt for event TRIGGERED[1]</description>
107065 <description>Read: Disabled</description>
107070 <description>Read: Enabled</description>
107078 <description>Enable</description>
107085 <description>Write '1' to enable interrupt for event TRIGGERED[2]</description>
107092 <description>Read: Disabled</description>
107097 <description>Read: Enabled</description>
107105 <description>Enable</description>
107112 <description>Write '1' to enable interrupt for event TRIGGERED[3]</description>
107119 <description>Read: Disabled</description>
107124 <description>Read: Enabled</description>
107132 <description>Enable</description>
107139 <description>Write '1' to enable interrupt for event TRIGGERED[4]</description>
107146 <description>Read: Disabled</description>
107151 <description>Read: Enabled</description>
107159 <description>Enable</description>
107166 <description>Write '1' to enable interrupt for event TRIGGERED[5]</description>
107173 <description>Read: Disabled</description>
107178 <description>Read: Enabled</description>
107186 <description>Enable</description>
107193 <description>Write '1' to enable interrupt for event TRIGGERED[6]</description>
107200 <description>Read: Disabled</description>
107205 <description>Read: Enabled</description>
107213 <description>Enable</description>
107220 <description>Write '1' to enable interrupt for event TRIGGERED[7]</description>
107227 <description>Read: Disabled</description>
107232 <description>Read: Enabled</description>
107240 <description>Enable</description>
107247 <description>Write '1' to enable interrupt for event TRIGGERED[8]</description>
107254 <description>Read: Disabled</description>
107259 <description>Read: Enabled</description>
107267 <description>Enable</description>
107274 <description>Write '1' to enable interrupt for event TRIGGERED[9]</description>
107281 <description>Read: Disabled</description>
107286 <description>Read: Enabled</description>
107294 <description>Enable</description>
107301 <description>Write '1' to enable interrupt for event TRIGGERED[10]</description>
107308 <description>Read: Disabled</description>
107313 <description>Read: Enabled</description>
107321 <description>Enable</description>
107328 <description>Write '1' to enable interrupt for event TRIGGERED[11]</description>
107335 <description>Read: Disabled</description>
107340 <description>Read: Enabled</description>
107348 <description>Enable</description>
107355 <description>Write '1' to enable interrupt for event TRIGGERED[12]</description>
107362 <description>Read: Disabled</description>
107367 <description>Read: Enabled</description>
107375 <description>Enable</description>
107382 <description>Write '1' to enable interrupt for event TRIGGERED[13]</description>
107389 <description>Read: Disabled</description>
107394 <description>Read: Enabled</description>
107402 <description>Enable</description>
107409 <description>Write '1' to enable interrupt for event TRIGGERED[14]</description>
107416 <description>Read: Disabled</description>
107421 <description>Read: Enabled</description>
107429 <description>Enable</description>
107436 <description>Write '1' to enable interrupt for event TRIGGERED[15]</description>
107443 <description>Read: Disabled</description>
107448 <description>Read: Enabled</description>
107456 <description>Enable</description>
107465 <description>Disable interrupt</description>
107473 <description>Write '1' to disable interrupt for event TRIGGERED[0]</description>
107480 <description>Read: Disabled</description>
107485 <description>Read: Enabled</description>
107493 <description>Disable</description>
107500 <description>Write '1' to disable interrupt for event TRIGGERED[1]</description>
107507 <description>Read: Disabled</description>
107512 <description>Read: Enabled</description>
107520 <description>Disable</description>
107527 <description>Write '1' to disable interrupt for event TRIGGERED[2]</description>
107534 <description>Read: Disabled</description>
107539 <description>Read: Enabled</description>
107547 <description>Disable</description>
107554 <description>Write '1' to disable interrupt for event TRIGGERED[3]</description>
107561 <description>Read: Disabled</description>
107566 <description>Read: Enabled</description>
107574 <description>Disable</description>
107581 <description>Write '1' to disable interrupt for event TRIGGERED[4]</description>
107588 <description>Read: Disabled</description>
107593 <description>Read: Enabled</description>
107601 <description>Disable</description>
107608 <description>Write '1' to disable interrupt for event TRIGGERED[5]</description>
107615 <description>Read: Disabled</description>
107620 <description>Read: Enabled</description>
107628 <description>Disable</description>
107635 <description>Write '1' to disable interrupt for event TRIGGERED[6]</description>
107642 <description>Read: Disabled</description>
107647 <description>Read: Enabled</description>
107655 <description>Disable</description>
107662 <description>Write '1' to disable interrupt for event TRIGGERED[7]</description>
107669 <description>Read: Disabled</description>
107674 <description>Read: Enabled</description>
107682 <description>Disable</description>
107689 <description>Write '1' to disable interrupt for event TRIGGERED[8]</description>
107696 <description>Read: Disabled</description>
107701 <description>Read: Enabled</description>
107709 <description>Disable</description>
107716 <description>Write '1' to disable interrupt for event TRIGGERED[9]</description>
107723 <description>Read: Disabled</description>
107728 <description>Read: Enabled</description>
107736 <description>Disable</description>
107743 <description>Write '1' to disable interrupt for event TRIGGERED[10]</description>
107750 <description>Read: Disabled</description>
107755 <description>Read: Enabled</description>
107763 <description>Disable</description>
107770 <description>Write '1' to disable interrupt for event TRIGGERED[11]</description>
107777 <description>Read: Disabled</description>
107782 <description>Read: Enabled</description>
107790 <description>Disable</description>
107797 <description>Write '1' to disable interrupt for event TRIGGERED[12]</description>
107804 <description>Read: Disabled</description>
107809 <description>Read: Enabled</description>
107817 <description>Disable</description>
107824 <description>Write '1' to disable interrupt for event TRIGGERED[13]</description>
107831 <description>Read: Disabled</description>
107836 <description>Read: Enabled</description>
107844 <description>Disable</description>
107851 <description>Write '1' to disable interrupt for event TRIGGERED[14]</description>
107858 <description>Read: Disabled</description>
107863 <description>Read: Enabled</description>
107871 <description>Disable</description>
107878 <description>Write '1' to disable interrupt for event TRIGGERED[15]</description>
107885 <description>Read: Disabled</description>
107890 <description>Read: Enabled</description>
107898 <description>Disable</description>
107907 <description>Pending interrupts</description>
107915 <description>Read pending status of interrupt for event TRIGGERED[0]</description>
107922 <description>Read: Not pending</description>
107927 <description>Read: Pending</description>
107934 <description>Read pending status of interrupt for event TRIGGERED[1]</description>
107941 <description>Read: Not pending</description>
107946 <description>Read: Pending</description>
107953 <description>Read pending status of interrupt for event TRIGGERED[2]</description>
107960 <description>Read: Not pending</description>
107965 <description>Read: Pending</description>
107972 <description>Read pending status of interrupt for event TRIGGERED[3]</description>
107979 <description>Read: Not pending</description>
107984 <description>Read: Pending</description>
107991 <description>Read pending status of interrupt for event TRIGGERED[4]</description>
107998 <description>Read: Not pending</description>
108003 <description>Read: Pending</description>
108010 <description>Read pending status of interrupt for event TRIGGERED[5]</description>
108017 <description>Read: Not pending</description>
108022 <description>Read: Pending</description>
108029 <description>Read pending status of interrupt for event TRIGGERED[6]</description>
108036 <description>Read: Not pending</description>
108041 <description>Read: Pending</description>
108048 <description>Read pending status of interrupt for event TRIGGERED[7]</description>
108055 <description>Read: Not pending</description>
108060 <description>Read: Pending</description>
108067 <description>Read pending status of interrupt for event TRIGGERED[8]</description>
108074 <description>Read: Not pending</description>
108079 <description>Read: Pending</description>
108086 <description>Read pending status of interrupt for event TRIGGERED[9]</description>
108093 <description>Read: Not pending</description>
108098 <description>Read: Pending</description>
108105 <description>Read pending status of interrupt for event TRIGGERED[10]</description>
108112 <description>Read: Not pending</description>
108117 <description>Read: Pending</description>
108124 <description>Read pending status of interrupt for event TRIGGERED[11]</description>
108131 <description>Read: Not pending</description>
108136 <description>Read: Pending</description>
108143 <description>Read pending status of interrupt for event TRIGGERED[12]</description>
108150 <description>Read: Not pending</description>
108155 <description>Read: Pending</description>
108162 <description>Read pending status of interrupt for event TRIGGERED[13]</description>
108169 <description>Read: Not pending</description>
108174 <description>Read: Pending</description>
108181 <description>Read pending status of interrupt for event TRIGGERED[14]</description>
108188 <description>Read: Not pending</description>
108193 <description>Read: Pending</description>
108200 <description>Read pending status of interrupt for event TRIGGERED[15]</description>
108207 <description>Read: Not pending</description>
108212 <description>Read: Pending</description>
108223 <description>GPIO Port 0</description>
108239 <description>Write GPIO port</description>
108247 <description>Pin 0</description>
108253 <description>Pin driver is low</description>
108258 <description>Pin driver is high</description>
108265 <description>Pin 1</description>
108271 <description>Pin driver is low</description>
108276 <description>Pin driver is high</description>
108283 <description>Pin 2</description>
108289 <description>Pin driver is low</description>
108294 <description>Pin driver is high</description>
108301 <description>Pin 3</description>
108307 <description>Pin driver is low</description>
108312 <description>Pin driver is high</description>
108319 <description>Pin 4</description>
108325 <description>Pin driver is low</description>
108330 <description>Pin driver is high</description>
108337 <description>Pin 5</description>
108343 <description>Pin driver is low</description>
108348 <description>Pin driver is high</description>
108355 <description>Pin 6</description>
108361 <description>Pin driver is low</description>
108366 <description>Pin driver is high</description>
108373 <description>Pin 7</description>
108379 <description>Pin driver is low</description>
108384 <description>Pin driver is high</description>
108391 <description>Pin 8</description>
108397 <description>Pin driver is low</description>
108402 <description>Pin driver is high</description>
108409 <description>Pin 9</description>
108415 <description>Pin driver is low</description>
108420 <description>Pin driver is high</description>
108427 <description>Pin 10</description>
108433 <description>Pin driver is low</description>
108438 <description>Pin driver is high</description>
108445 <description>Pin 11</description>
108451 <description>Pin driver is low</description>
108456 <description>Pin driver is high</description>
108463 <description>Pin 12</description>
108469 <description>Pin driver is low</description>
108474 <description>Pin driver is high</description>
108481 <description>Pin 13</description>
108487 <description>Pin driver is low</description>
108492 <description>Pin driver is high</description>
108499 <description>Pin 14</description>
108505 <description>Pin driver is low</description>
108510 <description>Pin driver is high</description>
108517 <description>Pin 15</description>
108523 <description>Pin driver is low</description>
108528 <description>Pin driver is high</description>
108535 <description>Pin 16</description>
108541 <description>Pin driver is low</description>
108546 <description>Pin driver is high</description>
108553 <description>Pin 17</description>
108559 <description>Pin driver is low</description>
108564 <description>Pin driver is high</description>
108571 <description>Pin 18</description>
108577 <description>Pin driver is low</description>
108582 <description>Pin driver is high</description>
108589 <description>Pin 19</description>
108595 <description>Pin driver is low</description>
108600 <description>Pin driver is high</description>
108607 <description>Pin 20</description>
108613 <description>Pin driver is low</description>
108618 <description>Pin driver is high</description>
108625 <description>Pin 21</description>
108631 <description>Pin driver is low</description>
108636 <description>Pin driver is high</description>
108643 <description>Pin 22</description>
108649 <description>Pin driver is low</description>
108654 <description>Pin driver is high</description>
108661 <description>Pin 23</description>
108667 <description>Pin driver is low</description>
108672 <description>Pin driver is high</description>
108679 <description>Pin 24</description>
108685 <description>Pin driver is low</description>
108690 <description>Pin driver is high</description>
108697 <description>Pin 25</description>
108703 <description>Pin driver is low</description>
108708 <description>Pin driver is high</description>
108715 <description>Pin 26</description>
108721 <description>Pin driver is low</description>
108726 <description>Pin driver is high</description>
108733 <description>Pin 27</description>
108739 <description>Pin driver is low</description>
108744 <description>Pin driver is high</description>
108751 <description>Pin 28</description>
108757 <description>Pin driver is low</description>
108762 <description>Pin driver is high</description>
108769 <description>Pin 29</description>
108775 <description>Pin driver is low</description>
108780 <description>Pin driver is high</description>
108787 <description>Pin 30</description>
108793 <description>Pin driver is low</description>
108798 <description>Pin driver is high</description>
108805 <description>Pin 31</description>
108811 <description>Pin driver is low</description>
108816 <description>Pin driver is high</description>
108825 <description>Set individual bits in GPIO port</description>
108834 <description>Pin 0</description>
108841 <description>Read: pin driver is low</description>
108846 <description>Read: pin driver is high</description>
108854 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
108861 <description>Pin 1</description>
108868 <description>Read: pin driver is low</description>
108873 <description>Read: pin driver is high</description>
108881 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
108888 <description>Pin 2</description>
108895 <description>Read: pin driver is low</description>
108900 <description>Read: pin driver is high</description>
108908 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
108915 <description>Pin 3</description>
108922 <description>Read: pin driver is low</description>
108927 <description>Read: pin driver is high</description>
108935 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
108942 <description>Pin 4</description>
108949 <description>Read: pin driver is low</description>
108954 <description>Read: pin driver is high</description>
108962 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
108969 <description>Pin 5</description>
108976 <description>Read: pin driver is low</description>
108981 <description>Read: pin driver is high</description>
108989 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
108996 <description>Pin 6</description>
109003 <description>Read: pin driver is low</description>
109008 <description>Read: pin driver is high</description>
109016 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109023 <description>Pin 7</description>
109030 <description>Read: pin driver is low</description>
109035 <description>Read: pin driver is high</description>
109043 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109050 <description>Pin 8</description>
109057 <description>Read: pin driver is low</description>
109062 <description>Read: pin driver is high</description>
109070 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109077 <description>Pin 9</description>
109084 <description>Read: pin driver is low</description>
109089 <description>Read: pin driver is high</description>
109097 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109104 <description>Pin 10</description>
109111 <description>Read: pin driver is low</description>
109116 <description>Read: pin driver is high</description>
109124 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109131 <description>Pin 11</description>
109138 <description>Read: pin driver is low</description>
109143 <description>Read: pin driver is high</description>
109151 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109158 <description>Pin 12</description>
109165 <description>Read: pin driver is low</description>
109170 <description>Read: pin driver is high</description>
109178 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109185 <description>Pin 13</description>
109192 <description>Read: pin driver is low</description>
109197 <description>Read: pin driver is high</description>
109205 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109212 <description>Pin 14</description>
109219 <description>Read: pin driver is low</description>
109224 <description>Read: pin driver is high</description>
109232 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109239 <description>Pin 15</description>
109246 <description>Read: pin driver is low</description>
109251 <description>Read: pin driver is high</description>
109259 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109266 <description>Pin 16</description>
109273 <description>Read: pin driver is low</description>
109278 <description>Read: pin driver is high</description>
109286 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109293 <description>Pin 17</description>
109300 <description>Read: pin driver is low</description>
109305 <description>Read: pin driver is high</description>
109313 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109320 <description>Pin 18</description>
109327 <description>Read: pin driver is low</description>
109332 <description>Read: pin driver is high</description>
109340 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109347 <description>Pin 19</description>
109354 <description>Read: pin driver is low</description>
109359 <description>Read: pin driver is high</description>
109367 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109374 <description>Pin 20</description>
109381 <description>Read: pin driver is low</description>
109386 <description>Read: pin driver is high</description>
109394 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109401 <description>Pin 21</description>
109408 <description>Read: pin driver is low</description>
109413 <description>Read: pin driver is high</description>
109421 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109428 <description>Pin 22</description>
109435 <description>Read: pin driver is low</description>
109440 <description>Read: pin driver is high</description>
109448 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109455 <description>Pin 23</description>
109462 <description>Read: pin driver is low</description>
109467 <description>Read: pin driver is high</description>
109475 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109482 <description>Pin 24</description>
109489 <description>Read: pin driver is low</description>
109494 <description>Read: pin driver is high</description>
109502 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109509 <description>Pin 25</description>
109516 <description>Read: pin driver is low</description>
109521 <description>Read: pin driver is high</description>
109529 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109536 <description>Pin 26</description>
109543 <description>Read: pin driver is low</description>
109548 <description>Read: pin driver is high</description>
109556 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109563 <description>Pin 27</description>
109570 <description>Read: pin driver is low</description>
109575 <description>Read: pin driver is high</description>
109583 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109590 <description>Pin 28</description>
109597 <description>Read: pin driver is low</description>
109602 <description>Read: pin driver is high</description>
109610 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109617 <description>Pin 29</description>
109624 <description>Read: pin driver is low</description>
109629 <description>Read: pin driver is high</description>
109637 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109644 <description>Pin 30</description>
109651 <description>Read: pin driver is low</description>
109656 <description>Read: pin driver is high</description>
109664 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109671 <description>Pin 31</description>
109678 <description>Read: pin driver is low</description>
109683 <description>Read: pin driver is high</description>
109691 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109700 <description>Clear individual bits in GPIO port</description>
109709 <description>Pin 0</description>
109716 <description>Read: pin driver is low</description>
109721 <description>Read: pin driver is high</description>
109729 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
109736 <description>Pin 1</description>
109743 <description>Read: pin driver is low</description>
109748 <description>Read: pin driver is high</description>
109756 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
109763 <description>Pin 2</description>
109770 <description>Read: pin driver is low</description>
109775 <description>Read: pin driver is high</description>
109783 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
109790 <description>Pin 3</description>
109797 <description>Read: pin driver is low</description>
109802 <description>Read: pin driver is high</description>
109810 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
109817 <description>Pin 4</description>
109824 <description>Read: pin driver is low</description>
109829 <description>Read: pin driver is high</description>
109837 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
109844 <description>Pin 5</description>
109851 <description>Read: pin driver is low</description>
109856 <description>Read: pin driver is high</description>
109864 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
109871 <description>Pin 6</description>
109878 <description>Read: pin driver is low</description>
109883 <description>Read: pin driver is high</description>
109891 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
109898 <description>Pin 7</description>
109905 <description>Read: pin driver is low</description>
109910 <description>Read: pin driver is high</description>
109918 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
109925 <description>Pin 8</description>
109932 <description>Read: pin driver is low</description>
109937 <description>Read: pin driver is high</description>
109945 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
109952 <description>Pin 9</description>
109959 <description>Read: pin driver is low</description>
109964 <description>Read: pin driver is high</description>
109972 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
109979 <description>Pin 10</description>
109986 <description>Read: pin driver is low</description>
109991 <description>Read: pin driver is high</description>
109999 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110006 <description>Pin 11</description>
110013 <description>Read: pin driver is low</description>
110018 <description>Read: pin driver is high</description>
110026 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110033 <description>Pin 12</description>
110040 <description>Read: pin driver is low</description>
110045 <description>Read: pin driver is high</description>
110053 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110060 <description>Pin 13</description>
110067 <description>Read: pin driver is low</description>
110072 <description>Read: pin driver is high</description>
110080 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110087 <description>Pin 14</description>
110094 <description>Read: pin driver is low</description>
110099 <description>Read: pin driver is high</description>
110107 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110114 <description>Pin 15</description>
110121 <description>Read: pin driver is low</description>
110126 <description>Read: pin driver is high</description>
110134 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110141 <description>Pin 16</description>
110148 <description>Read: pin driver is low</description>
110153 <description>Read: pin driver is high</description>
110161 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110168 <description>Pin 17</description>
110175 <description>Read: pin driver is low</description>
110180 <description>Read: pin driver is high</description>
110188 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110195 <description>Pin 18</description>
110202 <description>Read: pin driver is low</description>
110207 <description>Read: pin driver is high</description>
110215 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110222 <description>Pin 19</description>
110229 <description>Read: pin driver is low</description>
110234 <description>Read: pin driver is high</description>
110242 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110249 <description>Pin 20</description>
110256 <description>Read: pin driver is low</description>
110261 <description>Read: pin driver is high</description>
110269 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110276 <description>Pin 21</description>
110283 <description>Read: pin driver is low</description>
110288 <description>Read: pin driver is high</description>
110296 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110303 <description>Pin 22</description>
110310 <description>Read: pin driver is low</description>
110315 <description>Read: pin driver is high</description>
110323 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110330 <description>Pin 23</description>
110337 <description>Read: pin driver is low</description>
110342 <description>Read: pin driver is high</description>
110350 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110357 <description>Pin 24</description>
110364 <description>Read: pin driver is low</description>
110369 <description>Read: pin driver is high</description>
110377 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110384 <description>Pin 25</description>
110391 <description>Read: pin driver is low</description>
110396 <description>Read: pin driver is high</description>
110404 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110411 <description>Pin 26</description>
110418 <description>Read: pin driver is low</description>
110423 <description>Read: pin driver is high</description>
110431 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110438 <description>Pin 27</description>
110445 <description>Read: pin driver is low</description>
110450 <description>Read: pin driver is high</description>
110458 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110465 <description>Pin 28</description>
110472 <description>Read: pin driver is low</description>
110477 <description>Read: pin driver is high</description>
110485 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110492 <description>Pin 29</description>
110499 <description>Read: pin driver is low</description>
110504 <description>Read: pin driver is high</description>
110512 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110519 <description>Pin 30</description>
110526 <description>Read: pin driver is low</description>
110531 <description>Read: pin driver is high</description>
110539 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110546 <description>Pin 31</description>
110553 <description>Read: pin driver is low</description>
110558 <description>Read: pin driver is high</description>
110566 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110575 <description>Read GPIO port</description>
110583 <description>Pin 0</description>
110589 <description>Pin input is low</description>
110594 <description>Pin input is high</description>
110601 <description>Pin 1</description>
110607 <description>Pin input is low</description>
110612 <description>Pin input is high</description>
110619 <description>Pin 2</description>
110625 <description>Pin input is low</description>
110630 <description>Pin input is high</description>
110637 <description>Pin 3</description>
110643 <description>Pin input is low</description>
110648 <description>Pin input is high</description>
110655 <description>Pin 4</description>
110661 <description>Pin input is low</description>
110666 <description>Pin input is high</description>
110673 <description>Pin 5</description>
110679 <description>Pin input is low</description>
110684 <description>Pin input is high</description>
110691 <description>Pin 6</description>
110697 <description>Pin input is low</description>
110702 <description>Pin input is high</description>
110709 <description>Pin 7</description>
110715 <description>Pin input is low</description>
110720 <description>Pin input is high</description>
110727 <description>Pin 8</description>
110733 <description>Pin input is low</description>
110738 <description>Pin input is high</description>
110745 <description>Pin 9</description>
110751 <description>Pin input is low</description>
110756 <description>Pin input is high</description>
110763 <description>Pin 10</description>
110769 <description>Pin input is low</description>
110774 <description>Pin input is high</description>
110781 <description>Pin 11</description>
110787 <description>Pin input is low</description>
110792 <description>Pin input is high</description>
110799 <description>Pin 12</description>
110805 <description>Pin input is low</description>
110810 <description>Pin input is high</description>
110817 <description>Pin 13</description>
110823 <description>Pin input is low</description>
110828 <description>Pin input is high</description>
110835 <description>Pin 14</description>
110841 <description>Pin input is low</description>
110846 <description>Pin input is high</description>
110853 <description>Pin 15</description>
110859 <description>Pin input is low</description>
110864 <description>Pin input is high</description>
110871 <description>Pin 16</description>
110877 <description>Pin input is low</description>
110882 <description>Pin input is high</description>
110889 <description>Pin 17</description>
110895 <description>Pin input is low</description>
110900 <description>Pin input is high</description>
110907 <description>Pin 18</description>
110913 <description>Pin input is low</description>
110918 <description>Pin input is high</description>
110925 <description>Pin 19</description>
110931 <description>Pin input is low</description>
110936 <description>Pin input is high</description>
110943 <description>Pin 20</description>
110949 <description>Pin input is low</description>
110954 <description>Pin input is high</description>
110961 <description>Pin 21</description>
110967 <description>Pin input is low</description>
110972 <description>Pin input is high</description>
110979 <description>Pin 22</description>
110985 <description>Pin input is low</description>
110990 <description>Pin input is high</description>
110997 <description>Pin 23</description>
111003 <description>Pin input is low</description>
111008 <description>Pin input is high</description>
111015 <description>Pin 24</description>
111021 <description>Pin input is low</description>
111026 <description>Pin input is high</description>
111033 <description>Pin 25</description>
111039 <description>Pin input is low</description>
111044 <description>Pin input is high</description>
111051 <description>Pin 26</description>
111057 <description>Pin input is low</description>
111062 <description>Pin input is high</description>
111069 <description>Pin 27</description>
111075 <description>Pin input is low</description>
111080 <description>Pin input is high</description>
111087 <description>Pin 28</description>
111093 <description>Pin input is low</description>
111098 <description>Pin input is high</description>
111105 <description>Pin 29</description>
111111 <description>Pin input is low</description>
111116 <description>Pin input is high</description>
111123 <description>Pin 30</description>
111129 <description>Pin input is low</description>
111134 <description>Pin input is high</description>
111141 <description>Pin 31</description>
111147 <description>Pin input is low</description>
111152 <description>Pin input is high</description>
111161 <description>Direction of GPIO pins</description>
111169 <description>Pin 0</description>
111175 <description>Pin set as input</description>
111180 <description>Pin set as output</description>
111187 <description>Pin 1</description>
111193 <description>Pin set as input</description>
111198 <description>Pin set as output</description>
111205 <description>Pin 2</description>
111211 <description>Pin set as input</description>
111216 <description>Pin set as output</description>
111223 <description>Pin 3</description>
111229 <description>Pin set as input</description>
111234 <description>Pin set as output</description>
111241 <description>Pin 4</description>
111247 <description>Pin set as input</description>
111252 <description>Pin set as output</description>
111259 <description>Pin 5</description>
111265 <description>Pin set as input</description>
111270 <description>Pin set as output</description>
111277 <description>Pin 6</description>
111283 <description>Pin set as input</description>
111288 <description>Pin set as output</description>
111295 <description>Pin 7</description>
111301 <description>Pin set as input</description>
111306 <description>Pin set as output</description>
111313 <description>Pin 8</description>
111319 <description>Pin set as input</description>
111324 <description>Pin set as output</description>
111331 <description>Pin 9</description>
111337 <description>Pin set as input</description>
111342 <description>Pin set as output</description>
111349 <description>Pin 10</description>
111355 <description>Pin set as input</description>
111360 <description>Pin set as output</description>
111367 <description>Pin 11</description>
111373 <description>Pin set as input</description>
111378 <description>Pin set as output</description>
111385 <description>Pin 12</description>
111391 <description>Pin set as input</description>
111396 <description>Pin set as output</description>
111403 <description>Pin 13</description>
111409 <description>Pin set as input</description>
111414 <description>Pin set as output</description>
111421 <description>Pin 14</description>
111427 <description>Pin set as input</description>
111432 <description>Pin set as output</description>
111439 <description>Pin 15</description>
111445 <description>Pin set as input</description>
111450 <description>Pin set as output</description>
111457 <description>Pin 16</description>
111463 <description>Pin set as input</description>
111468 <description>Pin set as output</description>
111475 <description>Pin 17</description>
111481 <description>Pin set as input</description>
111486 <description>Pin set as output</description>
111493 <description>Pin 18</description>
111499 <description>Pin set as input</description>
111504 <description>Pin set as output</description>
111511 <description>Pin 19</description>
111517 <description>Pin set as input</description>
111522 <description>Pin set as output</description>
111529 <description>Pin 20</description>
111535 <description>Pin set as input</description>
111540 <description>Pin set as output</description>
111547 <description>Pin 21</description>
111553 <description>Pin set as input</description>
111558 <description>Pin set as output</description>
111565 <description>Pin 22</description>
111571 <description>Pin set as input</description>
111576 <description>Pin set as output</description>
111583 <description>Pin 23</description>
111589 <description>Pin set as input</description>
111594 <description>Pin set as output</description>
111601 <description>Pin 24</description>
111607 <description>Pin set as input</description>
111612 <description>Pin set as output</description>
111619 <description>Pin 25</description>
111625 <description>Pin set as input</description>
111630 <description>Pin set as output</description>
111637 <description>Pin 26</description>
111643 <description>Pin set as input</description>
111648 <description>Pin set as output</description>
111655 <description>Pin 27</description>
111661 <description>Pin set as input</description>
111666 <description>Pin set as output</description>
111673 <description>Pin 28</description>
111679 <description>Pin set as input</description>
111684 <description>Pin set as output</description>
111691 <description>Pin 29</description>
111697 <description>Pin set as input</description>
111702 <description>Pin set as output</description>
111709 <description>Pin 30</description>
111715 <description>Pin set as input</description>
111720 <description>Pin set as output</description>
111727 <description>Pin 31</description>
111733 <description>Pin set as input</description>
111738 <description>Pin set as output</description>
111747 <description>DIR set register</description>
111756 <description>Set as output pin 0</description>
111763 <description>Read: pin set as input</description>
111768 <description>Read: pin set as output</description>
111776 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
111783 <description>Set as output pin 1</description>
111790 <description>Read: pin set as input</description>
111795 <description>Read: pin set as output</description>
111803 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
111810 <description>Set as output pin 2</description>
111817 <description>Read: pin set as input</description>
111822 <description>Read: pin set as output</description>
111830 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
111837 <description>Set as output pin 3</description>
111844 <description>Read: pin set as input</description>
111849 <description>Read: pin set as output</description>
111857 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
111864 <description>Set as output pin 4</description>
111871 <description>Read: pin set as input</description>
111876 <description>Read: pin set as output</description>
111884 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
111891 <description>Set as output pin 5</description>
111898 <description>Read: pin set as input</description>
111903 <description>Read: pin set as output</description>
111911 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
111918 <description>Set as output pin 6</description>
111925 <description>Read: pin set as input</description>
111930 <description>Read: pin set as output</description>
111938 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
111945 <description>Set as output pin 7</description>
111952 <description>Read: pin set as input</description>
111957 <description>Read: pin set as output</description>
111965 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
111972 <description>Set as output pin 8</description>
111979 <description>Read: pin set as input</description>
111984 <description>Read: pin set as output</description>
111992 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
111999 <description>Set as output pin 9</description>
112006 <description>Read: pin set as input</description>
112011 <description>Read: pin set as output</description>
112019 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112026 <description>Set as output pin 10</description>
112033 <description>Read: pin set as input</description>
112038 <description>Read: pin set as output</description>
112046 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112053 <description>Set as output pin 11</description>
112060 <description>Read: pin set as input</description>
112065 <description>Read: pin set as output</description>
112073 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112080 <description>Set as output pin 12</description>
112087 <description>Read: pin set as input</description>
112092 <description>Read: pin set as output</description>
112100 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112107 <description>Set as output pin 13</description>
112114 <description>Read: pin set as input</description>
112119 <description>Read: pin set as output</description>
112127 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112134 <description>Set as output pin 14</description>
112141 <description>Read: pin set as input</description>
112146 <description>Read: pin set as output</description>
112154 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112161 <description>Set as output pin 15</description>
112168 <description>Read: pin set as input</description>
112173 <description>Read: pin set as output</description>
112181 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112188 <description>Set as output pin 16</description>
112195 <description>Read: pin set as input</description>
112200 <description>Read: pin set as output</description>
112208 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112215 <description>Set as output pin 17</description>
112222 <description>Read: pin set as input</description>
112227 <description>Read: pin set as output</description>
112235 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112242 <description>Set as output pin 18</description>
112249 <description>Read: pin set as input</description>
112254 <description>Read: pin set as output</description>
112262 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112269 <description>Set as output pin 19</description>
112276 <description>Read: pin set as input</description>
112281 <description>Read: pin set as output</description>
112289 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112296 <description>Set as output pin 20</description>
112303 <description>Read: pin set as input</description>
112308 <description>Read: pin set as output</description>
112316 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112323 <description>Set as output pin 21</description>
112330 <description>Read: pin set as input</description>
112335 <description>Read: pin set as output</description>
112343 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112350 <description>Set as output pin 22</description>
112357 <description>Read: pin set as input</description>
112362 <description>Read: pin set as output</description>
112370 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112377 <description>Set as output pin 23</description>
112384 <description>Read: pin set as input</description>
112389 <description>Read: pin set as output</description>
112397 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112404 <description>Set as output pin 24</description>
112411 <description>Read: pin set as input</description>
112416 <description>Read: pin set as output</description>
112424 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112431 <description>Set as output pin 25</description>
112438 <description>Read: pin set as input</description>
112443 <description>Read: pin set as output</description>
112451 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112458 <description>Set as output pin 26</description>
112465 <description>Read: pin set as input</description>
112470 <description>Read: pin set as output</description>
112478 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112485 <description>Set as output pin 27</description>
112492 <description>Read: pin set as input</description>
112497 <description>Read: pin set as output</description>
112505 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112512 <description>Set as output pin 28</description>
112519 <description>Read: pin set as input</description>
112524 <description>Read: pin set as output</description>
112532 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112539 <description>Set as output pin 29</description>
112546 <description>Read: pin set as input</description>
112551 <description>Read: pin set as output</description>
112559 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112566 <description>Set as output pin 30</description>
112573 <description>Read: pin set as input</description>
112578 <description>Read: pin set as output</description>
112586 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112593 <description>Set as output pin 31</description>
112600 <description>Read: pin set as input</description>
112605 <description>Read: pin set as output</description>
112613 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112622 <description>DIR clear register</description>
112631 <description>Set as input pin 0</description>
112638 <description>Read: pin set as input</description>
112643 <description>Read: pin set as output</description>
112651 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
112658 <description>Set as input pin 1</description>
112665 <description>Read: pin set as input</description>
112670 <description>Read: pin set as output</description>
112678 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
112685 <description>Set as input pin 2</description>
112692 <description>Read: pin set as input</description>
112697 <description>Read: pin set as output</description>
112705 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
112712 <description>Set as input pin 3</description>
112719 <description>Read: pin set as input</description>
112724 <description>Read: pin set as output</description>
112732 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
112739 <description>Set as input pin 4</description>
112746 <description>Read: pin set as input</description>
112751 <description>Read: pin set as output</description>
112759 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
112766 <description>Set as input pin 5</description>
112773 <description>Read: pin set as input</description>
112778 <description>Read: pin set as output</description>
112786 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
112793 <description>Set as input pin 6</description>
112800 <description>Read: pin set as input</description>
112805 <description>Read: pin set as output</description>
112813 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
112820 <description>Set as input pin 7</description>
112827 <description>Read: pin set as input</description>
112832 <description>Read: pin set as output</description>
112840 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
112847 <description>Set as input pin 8</description>
112854 <description>Read: pin set as input</description>
112859 <description>Read: pin set as output</description>
112867 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
112874 <description>Set as input pin 9</description>
112881 <description>Read: pin set as input</description>
112886 <description>Read: pin set as output</description>
112894 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
112901 <description>Set as input pin 10</description>
112908 <description>Read: pin set as input</description>
112913 <description>Read: pin set as output</description>
112921 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
112928 <description>Set as input pin 11</description>
112935 <description>Read: pin set as input</description>
112940 <description>Read: pin set as output</description>
112948 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
112955 <description>Set as input pin 12</description>
112962 <description>Read: pin set as input</description>
112967 <description>Read: pin set as output</description>
112975 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
112982 <description>Set as input pin 13</description>
112989 <description>Read: pin set as input</description>
112994 <description>Read: pin set as output</description>
113002 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
113009 <description>Set as input pin 14</description>
113016 <description>Read: pin set as input</description>
113021 <description>Read: pin set as output</description>
113029 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
113036 <description>Set as input pin 15</description>
113043 <description>Read: pin set as input</description>
113048 <description>Read: pin set as output</description>
113056 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
113063 <description>Set as input pin 16</description>
113070 <description>Read: pin set as input</description>
113075 <description>Read: pin set as output</description>
113083 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
113090 <description>Set as input pin 17</description>
113097 <description>Read: pin set as input</description>
113102 <description>Read: pin set as output</description>
113110 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
113117 <description>Set as input pin 18</description>
113124 <description>Read: pin set as input</description>
113129 <description>Read: pin set as output</description>
113137 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
113144 <description>Set as input pin 19</description>
113151 <description>Read: pin set as input</description>
113156 <description>Read: pin set as output</description>
113164 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
113171 <description>Set as input pin 20</description>
113178 <description>Read: pin set as input</description>
113183 <description>Read: pin set as output</description>
113191 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
113198 <description>Set as input pin 21</description>
113205 <description>Read: pin set as input</description>
113210 <description>Read: pin set as output</description>
113218 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
113225 <description>Set as input pin 22</description>
113232 <description>Read: pin set as input</description>
113237 <description>Read: pin set as output</description>
113245 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
113252 <description>Set as input pin 23</description>
113259 <description>Read: pin set as input</description>
113264 <description>Read: pin set as output</description>
113272 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
113279 <description>Set as input pin 24</description>
113286 <description>Read: pin set as input</description>
113291 <description>Read: pin set as output</description>
113299 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
113306 <description>Set as input pin 25</description>
113313 <description>Read: pin set as input</description>
113318 <description>Read: pin set as output</description>
113326 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
113333 <description>Set as input pin 26</description>
113340 <description>Read: pin set as input</description>
113345 <description>Read: pin set as output</description>
113353 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
113360 <description>Set as input pin 27</description>
113367 <description>Read: pin set as input</description>
113372 <description>Read: pin set as output</description>
113380 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
113387 <description>Set as input pin 28</description>
113394 <description>Read: pin set as input</description>
113399 <description>Read: pin set as output</description>
113407 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
113414 <description>Set as input pin 29</description>
113421 <description>Read: pin set as input</description>
113426 <description>Read: pin set as output</description>
113434 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
113441 <description>Set as input pin 30</description>
113448 <description>Read: pin set as input</description>
113453 <description>Read: pin set as output</description>
113461 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
113468 <description>Set as input pin 31</description>
113475 <description>Read: pin set as input</description>
113480 <description>Read: pin set as output</description>
113488 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
113497 …<description>Latch register indicating what GPIO pins that have met the criteria set in the PIN_CN…
113505 …<description>Status on whether PIN0 has met criteria set in PIN_CNF[0].SENSE register. Write '1' t…
113511 <description>Criteria has not been met</description>
113516 <description>Criteria has been met</description>
113523 …<description>Status on whether PIN1 has met criteria set in PIN_CNF[1].SENSE register. Write '1' t…
113529 <description>Criteria has not been met</description>
113534 <description>Criteria has been met</description>
113541 …<description>Status on whether PIN2 has met criteria set in PIN_CNF[2].SENSE register. Write '1' t…
113547 <description>Criteria has not been met</description>
113552 <description>Criteria has been met</description>
113559 …<description>Status on whether PIN3 has met criteria set in PIN_CNF[3].SENSE register. Write '1' t…
113565 <description>Criteria has not been met</description>
113570 <description>Criteria has been met</description>
113577 …<description>Status on whether PIN4 has met criteria set in PIN_CNF[4].SENSE register. Write '1' t…
113583 <description>Criteria has not been met</description>
113588 <description>Criteria has been met</description>
113595 …<description>Status on whether PIN5 has met criteria set in PIN_CNF[5].SENSE register. Write '1' t…
113601 <description>Criteria has not been met</description>
113606 <description>Criteria has been met</description>
113613 …<description>Status on whether PIN6 has met criteria set in PIN_CNF[6].SENSE register. Write '1' t…
113619 <description>Criteria has not been met</description>
113624 <description>Criteria has been met</description>
113631 …<description>Status on whether PIN7 has met criteria set in PIN_CNF[7].SENSE register. Write '1' t…
113637 <description>Criteria has not been met</description>
113642 <description>Criteria has been met</description>
113649 …<description>Status on whether PIN8 has met criteria set in PIN_CNF[8].SENSE register. Write '1' t…
113655 <description>Criteria has not been met</description>
113660 <description>Criteria has been met</description>
113667 …<description>Status on whether PIN9 has met criteria set in PIN_CNF[9].SENSE register. Write '1' t…
113673 <description>Criteria has not been met</description>
113678 <description>Criteria has been met</description>
113685 …<description>Status on whether PIN10 has met criteria set in PIN_CNF[10].SENSE register. Write '1'…
113691 <description>Criteria has not been met</description>
113696 <description>Criteria has been met</description>
113703 …<description>Status on whether PIN11 has met criteria set in PIN_CNF[11].SENSE register. Write '1'…
113709 <description>Criteria has not been met</description>
113714 <description>Criteria has been met</description>
113721 …<description>Status on whether PIN12 has met criteria set in PIN_CNF[12].SENSE register. Write '1'…
113727 <description>Criteria has not been met</description>
113732 <description>Criteria has been met</description>
113739 …<description>Status on whether PIN13 has met criteria set in PIN_CNF[13].SENSE register. Write '1'…
113745 <description>Criteria has not been met</description>
113750 <description>Criteria has been met</description>
113757 …<description>Status on whether PIN14 has met criteria set in PIN_CNF[14].SENSE register. Write '1'…
113763 <description>Criteria has not been met</description>
113768 <description>Criteria has been met</description>
113775 …<description>Status on whether PIN15 has met criteria set in PIN_CNF[15].SENSE register. Write '1'…
113781 <description>Criteria has not been met</description>
113786 <description>Criteria has been met</description>
113793 …<description>Status on whether PIN16 has met criteria set in PIN_CNF[16].SENSE register. Write '1'…
113799 <description>Criteria has not been met</description>
113804 <description>Criteria has been met</description>
113811 …<description>Status on whether PIN17 has met criteria set in PIN_CNF[17].SENSE register. Write '1'…
113817 <description>Criteria has not been met</description>
113822 <description>Criteria has been met</description>
113829 …<description>Status on whether PIN18 has met criteria set in PIN_CNF[18].SENSE register. Write '1'…
113835 <description>Criteria has not been met</description>
113840 <description>Criteria has been met</description>
113847 …<description>Status on whether PIN19 has met criteria set in PIN_CNF[19].SENSE register. Write '1'…
113853 <description>Criteria has not been met</description>
113858 <description>Criteria has been met</description>
113865 …<description>Status on whether PIN20 has met criteria set in PIN_CNF[20].SENSE register. Write '1'…
113871 <description>Criteria has not been met</description>
113876 <description>Criteria has been met</description>
113883 …<description>Status on whether PIN21 has met criteria set in PIN_CNF[21].SENSE register. Write '1'…
113889 <description>Criteria has not been met</description>
113894 <description>Criteria has been met</description>
113901 …<description>Status on whether PIN22 has met criteria set in PIN_CNF[22].SENSE register. Write '1'…
113907 <description>Criteria has not been met</description>
113912 <description>Criteria has been met</description>
113919 …<description>Status on whether PIN23 has met criteria set in PIN_CNF[23].SENSE register. Write '1'…
113925 <description>Criteria has not been met</description>
113930 <description>Criteria has been met</description>
113937 …<description>Status on whether PIN24 has met criteria set in PIN_CNF[24].SENSE register. Write '1'…
113943 <description>Criteria has not been met</description>
113948 <description>Criteria has been met</description>
113955 …<description>Status on whether PIN25 has met criteria set in PIN_CNF[25].SENSE register. Write '1'…
113961 <description>Criteria has not been met</description>
113966 <description>Criteria has been met</description>
113973 …<description>Status on whether PIN26 has met criteria set in PIN_CNF[26].SENSE register. Write '1'…
113979 <description>Criteria has not been met</description>
113984 <description>Criteria has been met</description>
113991 …<description>Status on whether PIN27 has met criteria set in PIN_CNF[27].SENSE register. Write '1'…
113997 <description>Criteria has not been met</description>
114002 <description>Criteria has been met</description>
114009 …<description>Status on whether PIN28 has met criteria set in PIN_CNF[28].SENSE register. Write '1'…
114015 <description>Criteria has not been met</description>
114020 <description>Criteria has been met</description>
114027 …<description>Status on whether PIN29 has met criteria set in PIN_CNF[29].SENSE register. Write '1'…
114033 <description>Criteria has not been met</description>
114038 <description>Criteria has been met</description>
114045 …<description>Status on whether PIN30 has met criteria set in PIN_CNF[30].SENSE register. Write '1'…
114051 <description>Criteria has not been met</description>
114056 <description>Criteria has been met</description>
114063 …<description>Status on whether PIN31 has met criteria set in PIN_CNF[31].SENSE register. Write '1'…
114069 <description>Criteria has not been met</description>
114074 <description>Criteria has been met</description>
114083 <description>Select between default DETECT signal behavior and LDETECT mode</description>
114092 … <description>Select between default DETECT signal behavior and LDETECT mode</description>
114098 <description>DETECT directly connected to PIN DETECT signals</description>
114103 <description>Use the latched LDETECT behavior</description>
114112 <description>Unspecified</description>
114118 <description>Drive control for impedance matching of the pins in this port</description>
114127 <description>Enable 50 ohms impedance to the pins in this port</description>
114133 <description>Disabled</description>
114138 <description>Enable</description>
114145 <description>Enable 100 ohms impedance to the pins in this port</description>
114151 <description>Disabled</description>
114156 <description>Enable</description>
114163 <description>Enable 200 ohms impedance to the pins in this port</description>
114169 <description>Disabled</description>
114174 <description>Enable</description>
114181 <description>Enable 400 ohms impedance to the pins in this port</description>
114187 <description>Disabled</description>
114192 <description>Enable</description>
114199 <description>Enable 800 ohms impedance to the pins in this port</description>
114205 <description>Disabled</description>
114210 <description>Enable</description>
114217 <description>Enable 1600 ohms impedance to the pins in this port</description>
114223 <description>Disabled</description>
114228 <description>Enable</description>
114238 …<description>RETAIN of each individual GPIO pin. Pins with their RETAIN bit set keep their state i…
114241 all its state including the output value, DIR and PORTCNF settings.</description>
114249 <description>Pin 0</description>
114255 <description>Pin not retained</description>
114260 <description>Pin retained</description>
114267 <description>Pin 1</description>
114273 <description>Pin not retained</description>
114278 <description>Pin retained</description>
114285 <description>Pin 2</description>
114291 <description>Pin not retained</description>
114296 <description>Pin retained</description>
114303 <description>Pin 3</description>
114309 <description>Pin not retained</description>
114314 <description>Pin retained</description>
114321 <description>Pin 4</description>
114327 <description>Pin not retained</description>
114332 <description>Pin retained</description>
114339 <description>Pin 5</description>
114345 <description>Pin not retained</description>
114350 <description>Pin retained</description>
114357 <description>Pin 6</description>
114363 <description>Pin not retained</description>
114368 <description>Pin retained</description>
114375 <description>Pin 7</description>
114381 <description>Pin not retained</description>
114386 <description>Pin retained</description>
114393 <description>Pin 8</description>
114399 <description>Pin not retained</description>
114404 <description>Pin retained</description>
114411 <description>Pin 9</description>
114417 <description>Pin not retained</description>
114422 <description>Pin retained</description>
114429 <description>Pin 10</description>
114435 <description>Pin not retained</description>
114440 <description>Pin retained</description>
114447 <description>Pin 11</description>
114453 <description>Pin not retained</description>
114458 <description>Pin retained</description>
114465 <description>Pin 12</description>
114471 <description>Pin not retained</description>
114476 <description>Pin retained</description>
114483 <description>Pin 13</description>
114489 <description>Pin not retained</description>
114494 <description>Pin retained</description>
114501 <description>Pin 14</description>
114507 <description>Pin not retained</description>
114512 <description>Pin retained</description>
114519 <description>Pin 15</description>
114525 <description>Pin not retained</description>
114530 <description>Pin retained</description>
114537 <description>Pin 16</description>
114543 <description>Pin not retained</description>
114548 <description>Pin retained</description>
114555 <description>Pin 17</description>
114561 <description>Pin not retained</description>
114566 <description>Pin retained</description>
114573 <description>Pin 18</description>
114579 <description>Pin not retained</description>
114584 <description>Pin retained</description>
114591 <description>Pin 19</description>
114597 <description>Pin not retained</description>
114602 <description>Pin retained</description>
114609 <description>Pin 20</description>
114615 <description>Pin not retained</description>
114620 <description>Pin retained</description>
114627 <description>Pin 21</description>
114633 <description>Pin not retained</description>
114638 <description>Pin retained</description>
114645 <description>Pin 22</description>
114651 <description>Pin not retained</description>
114656 <description>Pin retained</description>
114663 <description>Pin 23</description>
114669 <description>Pin not retained</description>
114674 <description>Pin retained</description>
114681 <description>Pin 24</description>
114687 <description>Pin not retained</description>
114692 <description>Pin retained</description>
114699 <description>Pin 25</description>
114705 <description>Pin not retained</description>
114710 <description>Pin retained</description>
114717 <description>Pin 26</description>
114723 <description>Pin not retained</description>
114728 <description>Pin retained</description>
114735 <description>Pin 27</description>
114741 <description>Pin not retained</description>
114746 <description>Pin retained</description>
114753 <description>Pin 28</description>
114759 <description>Pin not retained</description>
114764 <description>Pin retained</description>
114771 <description>Pin 29</description>
114777 <description>Pin not retained</description>
114782 <description>Pin retained</description>
114789 <description>Pin 30</description>
114795 <description>Pin not retained</description>
114800 <description>Pin retained</description>
114807 <description>Pin 31</description>
114813 <description>Pin not retained</description>
114818 <description>Pin retained</description>
114827 <description>Set RETAIN for individual GPIO pins</description>
114836 <description>Set RETAIN for pin 0</description>
114843 <description>Read: pin not retained</description>
114848 <description>Read: pin retained</description>
114856 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
114863 <description>Set RETAIN for pin 1</description>
114870 <description>Read: pin not retained</description>
114875 <description>Read: pin retained</description>
114883 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
114890 <description>Set RETAIN for pin 2</description>
114897 <description>Read: pin not retained</description>
114902 <description>Read: pin retained</description>
114910 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
114917 <description>Set RETAIN for pin 3</description>
114924 <description>Read: pin not retained</description>
114929 <description>Read: pin retained</description>
114937 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
114944 <description>Set RETAIN for pin 4</description>
114951 <description>Read: pin not retained</description>
114956 <description>Read: pin retained</description>
114964 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
114971 <description>Set RETAIN for pin 5</description>
114978 <description>Read: pin not retained</description>
114983 <description>Read: pin retained</description>
114991 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
114998 <description>Set RETAIN for pin 6</description>
115005 <description>Read: pin not retained</description>
115010 <description>Read: pin retained</description>
115018 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115025 <description>Set RETAIN for pin 7</description>
115032 <description>Read: pin not retained</description>
115037 <description>Read: pin retained</description>
115045 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115052 <description>Set RETAIN for pin 8</description>
115059 <description>Read: pin not retained</description>
115064 <description>Read: pin retained</description>
115072 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115079 <description>Set RETAIN for pin 9</description>
115086 <description>Read: pin not retained</description>
115091 <description>Read: pin retained</description>
115099 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115106 <description>Set RETAIN for pin 10</description>
115113 <description>Read: pin not retained</description>
115118 <description>Read: pin retained</description>
115126 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115133 <description>Set RETAIN for pin 11</description>
115140 <description>Read: pin not retained</description>
115145 <description>Read: pin retained</description>
115153 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115160 <description>Set RETAIN for pin 12</description>
115167 <description>Read: pin not retained</description>
115172 <description>Read: pin retained</description>
115180 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115187 <description>Set RETAIN for pin 13</description>
115194 <description>Read: pin not retained</description>
115199 <description>Read: pin retained</description>
115207 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115214 <description>Set RETAIN for pin 14</description>
115221 <description>Read: pin not retained</description>
115226 <description>Read: pin retained</description>
115234 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115241 <description>Set RETAIN for pin 15</description>
115248 <description>Read: pin not retained</description>
115253 <description>Read: pin retained</description>
115261 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115268 <description>Set RETAIN for pin 16</description>
115275 <description>Read: pin not retained</description>
115280 <description>Read: pin retained</description>
115288 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115295 <description>Set RETAIN for pin 17</description>
115302 <description>Read: pin not retained</description>
115307 <description>Read: pin retained</description>
115315 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115322 <description>Set RETAIN for pin 18</description>
115329 <description>Read: pin not retained</description>
115334 <description>Read: pin retained</description>
115342 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115349 <description>Set RETAIN for pin 19</description>
115356 <description>Read: pin not retained</description>
115361 <description>Read: pin retained</description>
115369 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115376 <description>Set RETAIN for pin 20</description>
115383 <description>Read: pin not retained</description>
115388 <description>Read: pin retained</description>
115396 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115403 <description>Set RETAIN for pin 21</description>
115410 <description>Read: pin not retained</description>
115415 <description>Read: pin retained</description>
115423 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115430 <description>Set RETAIN for pin 22</description>
115437 <description>Read: pin not retained</description>
115442 <description>Read: pin retained</description>
115450 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115457 <description>Set RETAIN for pin 23</description>
115464 <description>Read: pin not retained</description>
115469 <description>Read: pin retained</description>
115477 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115484 <description>Set RETAIN for pin 24</description>
115491 <description>Read: pin not retained</description>
115496 <description>Read: pin retained</description>
115504 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115511 <description>Set RETAIN for pin 25</description>
115518 <description>Read: pin not retained</description>
115523 <description>Read: pin retained</description>
115531 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115538 <description>Set RETAIN for pin 26</description>
115545 <description>Read: pin not retained</description>
115550 <description>Read: pin retained</description>
115558 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115565 <description>Set RETAIN for pin 27</description>
115572 <description>Read: pin not retained</description>
115577 <description>Read: pin retained</description>
115585 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115592 <description>Set RETAIN for pin 28</description>
115599 <description>Read: pin not retained</description>
115604 <description>Read: pin retained</description>
115612 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115619 <description>Set RETAIN for pin 29</description>
115626 <description>Read: pin not retained</description>
115631 <description>Read: pin retained</description>
115639 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115646 <description>Set RETAIN for pin 30</description>
115653 <description>Read: pin not retained</description>
115658 <description>Read: pin retained</description>
115666 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115673 <description>Set RETAIN for pin 31</description>
115680 <description>Read: pin not retained</description>
115685 <description>Read: pin retained</description>
115693 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115702 <description>Clear RETAIN for individual GPIO pins</description>
115711 <description>Clear RETAIN for pin 0</description>
115718 <description>Read: pin not retained</description>
115723 <description>Read: pin retained</description>
115731 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
115738 <description>Clear RETAIN for pin 1</description>
115745 <description>Read: pin not retained</description>
115750 <description>Read: pin retained</description>
115758 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
115765 <description>Clear RETAIN for pin 2</description>
115772 <description>Read: pin not retained</description>
115777 <description>Read: pin retained</description>
115785 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
115792 <description>Clear RETAIN for pin 3</description>
115799 <description>Read: pin not retained</description>
115804 <description>Read: pin retained</description>
115812 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
115819 <description>Clear RETAIN for pin 4</description>
115826 <description>Read: pin not retained</description>
115831 <description>Read: pin retained</description>
115839 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
115846 <description>Clear RETAIN for pin 5</description>
115853 <description>Read: pin not retained</description>
115858 <description>Read: pin retained</description>
115866 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
115873 <description>Clear RETAIN for pin 6</description>
115880 <description>Read: pin not retained</description>
115885 <description>Read: pin retained</description>
115893 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
115900 <description>Clear RETAIN for pin 7</description>
115907 <description>Read: pin not retained</description>
115912 <description>Read: pin retained</description>
115920 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
115927 <description>Clear RETAIN for pin 8</description>
115934 <description>Read: pin not retained</description>
115939 <description>Read: pin retained</description>
115947 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
115954 <description>Clear RETAIN for pin 9</description>
115961 <description>Read: pin not retained</description>
115966 <description>Read: pin retained</description>
115974 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
115981 <description>Clear RETAIN for pin 10</description>
115988 <description>Read: pin not retained</description>
115993 <description>Read: pin retained</description>
116001 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116008 <description>Clear RETAIN for pin 11</description>
116015 <description>Read: pin not retained</description>
116020 <description>Read: pin retained</description>
116028 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116035 <description>Clear RETAIN for pin 12</description>
116042 <description>Read: pin not retained</description>
116047 <description>Read: pin retained</description>
116055 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116062 <description>Clear RETAIN for pin 13</description>
116069 <description>Read: pin not retained</description>
116074 <description>Read: pin retained</description>
116082 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116089 <description>Clear RETAIN for pin 14</description>
116096 <description>Read: pin not retained</description>
116101 <description>Read: pin retained</description>
116109 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116116 <description>Clear RETAIN for pin 15</description>
116123 <description>Read: pin not retained</description>
116128 <description>Read: pin retained</description>
116136 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116143 <description>Clear RETAIN for pin 16</description>
116150 <description>Read: pin not retained</description>
116155 <description>Read: pin retained</description>
116163 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116170 <description>Clear RETAIN for pin 17</description>
116177 <description>Read: pin not retained</description>
116182 <description>Read: pin retained</description>
116190 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116197 <description>Clear RETAIN for pin 18</description>
116204 <description>Read: pin not retained</description>
116209 <description>Read: pin retained</description>
116217 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116224 <description>Clear RETAIN for pin 19</description>
116231 <description>Read: pin not retained</description>
116236 <description>Read: pin retained</description>
116244 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116251 <description>Clear RETAIN for pin 20</description>
116258 <description>Read: pin not retained</description>
116263 <description>Read: pin retained</description>
116271 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116278 <description>Clear RETAIN for pin 21</description>
116285 <description>Read: pin not retained</description>
116290 <description>Read: pin retained</description>
116298 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116305 <description>Clear RETAIN for pin 22</description>
116312 <description>Read: pin not retained</description>
116317 <description>Read: pin retained</description>
116325 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116332 <description>Clear RETAIN for pin 23</description>
116339 <description>Read: pin not retained</description>
116344 <description>Read: pin retained</description>
116352 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116359 <description>Clear RETAIN for pin 24</description>
116366 <description>Read: pin not retained</description>
116371 <description>Read: pin retained</description>
116379 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116386 <description>Clear RETAIN for pin 25</description>
116393 <description>Read: pin not retained</description>
116398 <description>Read: pin retained</description>
116406 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116413 <description>Clear RETAIN for pin 26</description>
116420 <description>Read: pin not retained</description>
116425 <description>Read: pin retained</description>
116433 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116440 <description>Clear RETAIN for pin 27</description>
116447 <description>Read: pin not retained</description>
116452 <description>Read: pin retained</description>
116460 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116467 <description>Clear RETAIN for pin 28</description>
116474 <description>Read: pin not retained</description>
116479 <description>Read: pin retained</description>
116487 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116494 <description>Clear RETAIN for pin 29</description>
116501 <description>Read: pin not retained</description>
116506 <description>Read: pin retained</description>
116514 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116521 <description>Clear RETAIN for pin 30</description>
116528 <description>Read: pin not retained</description>
116533 <description>Read: pin retained</description>
116541 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116548 <description>Clear RETAIN for pin 31</description>
116555 <description>Read: pin not retained</description>
116560 <description>Read: pin retained</description>
116568 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116579 <description>Description collection: Pin n configuration of GPIO pin</description>
116587 <description>Pin direction. Same physical register as DIR register</description>
116593 <description>Configure pin as an input pin</description>
116598 <description>Configure pin as an output pin</description>
116605 <description>Connect or disconnect input buffer</description>
116611 <description>Connect input buffer</description>
116616 <description>Disconnect input buffer</description>
116623 <description>Pull configuration</description>
116629 <description>No pull</description>
116634 <description>Pull down on pin</description>
116639 <description>Pull up on pin</description>
116646 <description>Drive configuration for '0'</description>
116652 <description>Standard '0'</description>
116657 <description>High drive '0'</description>
116662 <description>Disconnect '0'(normally used for wired-or connections)</description>
116667 <description>Extra high drive '0'</description>
116674 <description>Drive configuration for '1'</description>
116680 <description>Standard '1'</description>
116685 <description>High drive '1'</description>
116690 <description>Disconnect '1'(normally used for wired-or connections)</description>
116695 <description>Extra high drive '1'</description>
116702 <description>Pin sensing mechanism</description>
116708 <description>Disabled</description>
116713 <description>Sense for high level</description>
116718 <description>Sense for low level</description>
116725 <description>Enable clock on the pin.</description>
116731 <description>Clock disabled</description>
116736 <description>Clock enabled</description>
116747 <description>GPIO Port 1</description>
116755 <description>GPIO Port 2</description>
116763 <description>GPIO Port 3</description>
116771 <description>GPIO Port 4</description>
116779 <description>GPIO Port 5</description>
116787 <description>Distributed programmable peripheral interconnect controller 2</description>
116795 <description>Analog to Digital Converter</description>
116813 <description>Start the ADC and prepare the result buffer in RAM</description>
116821 <description>Start the ADC and prepare the result buffer in RAM</description>
116827 <description>Trigger task</description>
116836 …description>Take one ADC sample, if scan is enabled all channels are sampled. This task requires t…
116844 …description>Take one ADC sample, if scan is enabled all channels are sampled. This task requires t…
116850 <description>Trigger task</description>
116859 <description>Stop the ADC and terminate any on-going conversion</description>
116867 <description>Stop the ADC and terminate any on-going conversion</description>
116873 <description>Trigger task</description>
116882 <description>Starts offset auto-calibration</description>
116890 <description>Starts offset auto-calibration</description>
116896 <description>Trigger task</description>
116905 <description>Subscribe configuration for task START</description>
116913 <description>DPPI channel that task START will subscribe to</description>
116924 <description>Disable subscription</description>
116929 <description>Enable subscription</description>
116938 <description>Subscribe configuration for task SAMPLE</description>
116946 <description>DPPI channel that task SAMPLE will subscribe to</description>
116957 <description>Disable subscription</description>
116962 <description>Enable subscription</description>
116971 <description>Subscribe configuration for task STOP</description>
116979 <description>DPPI channel that task STOP will subscribe to</description>
116990 <description>Disable subscription</description>
116995 <description>Enable subscription</description>
117004 <description>Subscribe configuration for task CALIBRATEOFFSET</description>
117012 <description>DPPI channel that task CALIBRATEOFFSET will subscribe to</description>
117023 <description>Disable subscription</description>
117028 <description>Enable subscription</description>
117037 <description>The ADC has started</description>
117045 <description>The ADC has started</description>
117051 <description>Event not generated</description>
117056 <description>Event generated</description>
117065 <description>The ADC has filled up the Result buffer</description>
117073 <description>The ADC has filled up the Result buffer</description>
117079 <description>Event not generated</description>
117084 <description>Event generated</description>
117093 …description>A conversion task has been completed. Depending on the mode, multiple conversions migh…
117101 …description>A conversion task has been completed. Depending on the mode, multiple conversions migh…
117107 <description>Event not generated</description>
117112 <description>Event generated</description>
117121 <description>A result is ready to get transferred to RAM.</description>
117129 <description>A result is ready to get transferred to RAM.</description>
117135 <description>Event not generated</description>
117140 <description>Event generated</description>
117149 <description>Calibration is complete</description>
117157 <description>Calibration is complete</description>
117163 <description>Event not generated</description>
117168 <description>Event generated</description>
117177 <description>The ADC has stopped</description>
117185 <description>The ADC has stopped</description>
117191 <description>Event not generated</description>
117196 <description>Event generated</description>
117207 <description>Peripheral events.</description>
117213 … <description>Description cluster: Last results is equal or above CH[n].LIMIT.HIGH</description>
117221 <description>Last results is equal or above CH[n].LIMIT.HIGH</description>
117227 <description>Event not generated</description>
117232 <description>Event generated</description>
117241 … <description>Description cluster: Last results is equal or below CH[n].LIMIT.LOW</description>
117249 <description>Last results is equal or below CH[n].LIMIT.LOW</description>
117255 <description>Event not generated</description>
117260 <description>Event generated</description>
117270 <description>Publish configuration for event STARTED</description>
117278 <description>DPPI channel that event STARTED will publish to</description>
117289 <description>Disable publishing</description>
117294 <description>Enable publishing</description>
117303 <description>Publish configuration for event END</description>
117311 <description>DPPI channel that event END will publish to</description>
117322 <description>Disable publishing</description>
117327 <description>Enable publishing</description>
117336 <description>Publish configuration for event DONE</description>
117344 <description>DPPI channel that event DONE will publish to</description>
117355 <description>Disable publishing</description>
117360 <description>Enable publishing</description>
117369 <description>Publish configuration for event RESULTDONE</description>
117377 <description>DPPI channel that event RESULTDONE will publish to</description>
117388 <description>Disable publishing</description>
117393 <description>Enable publishing</description>
117402 <description>Publish configuration for event CALIBRATEDONE</description>
117410 <description>DPPI channel that event CALIBRATEDONE will publish to</description>
117421 <description>Disable publishing</description>
117426 <description>Enable publishing</description>
117435 <description>Publish configuration for event STOPPED</description>
117443 <description>DPPI channel that event STOPPED will publish to</description>
117454 <description>Disable publishing</description>
117459 <description>Enable publishing</description>
117470 <description>Publish configuration for events</description>
117476 … <description>Description cluster: Publish configuration for event CH[n].LIMITH</description>
117484 <description>DPPI channel that event CH[n].LIMITH will publish to</description>
117495 <description>Disable publishing</description>
117500 <description>Enable publishing</description>
117509 … <description>Description cluster: Publish configuration for event CH[n].LIMITL</description>
117517 <description>DPPI channel that event CH[n].LIMITL will publish to</description>
117528 <description>Disable publishing</description>
117533 <description>Enable publishing</description>
117543 <description>Enable or disable interrupt</description>
117551 <description>Enable or disable interrupt for event STARTED</description>
117557 <description>Disable</description>
117562 <description>Enable</description>
117569 <description>Enable or disable interrupt for event END</description>
117575 <description>Disable</description>
117580 <description>Enable</description>
117587 <description>Enable or disable interrupt for event DONE</description>
117593 <description>Disable</description>
117598 <description>Enable</description>
117605 <description>Enable or disable interrupt for event RESULTDONE</description>
117611 <description>Disable</description>
117616 <description>Enable</description>
117623 <description>Enable or disable interrupt for event CALIBRATEDONE</description>
117629 <description>Disable</description>
117634 <description>Enable</description>
117641 <description>Enable or disable interrupt for event STOPPED</description>
117647 <description>Disable</description>
117652 <description>Enable</description>
117659 <description>Enable or disable interrupt for event CH0LIMITH</description>
117665 <description>Disable</description>
117670 <description>Enable</description>
117677 <description>Enable or disable interrupt for event CH0LIMITL</description>
117683 <description>Disable</description>
117688 <description>Enable</description>
117695 <description>Enable or disable interrupt for event CH1LIMITH</description>
117701 <description>Disable</description>
117706 <description>Enable</description>
117713 <description>Enable or disable interrupt for event CH1LIMITL</description>
117719 <description>Disable</description>
117724 <description>Enable</description>
117731 <description>Enable or disable interrupt for event CH2LIMITH</description>
117737 <description>Disable</description>
117742 <description>Enable</description>
117749 <description>Enable or disable interrupt for event CH2LIMITL</description>
117755 <description>Disable</description>
117760 <description>Enable</description>
117767 <description>Enable or disable interrupt for event CH3LIMITH</description>
117773 <description>Disable</description>
117778 <description>Enable</description>
117785 <description>Enable or disable interrupt for event CH3LIMITL</description>
117791 <description>Disable</description>
117796 <description>Enable</description>
117803 <description>Enable or disable interrupt for event CH4LIMITH</description>
117809 <description>Disable</description>
117814 <description>Enable</description>
117821 <description>Enable or disable interrupt for event CH4LIMITL</description>
117827 <description>Disable</description>
117832 <description>Enable</description>
117839 <description>Enable or disable interrupt for event CH5LIMITH</description>
117845 <description>Disable</description>
117850 <description>Enable</description>
117857 <description>Enable or disable interrupt for event CH5LIMITL</description>
117863 <description>Disable</description>
117868 <description>Enable</description>
117875 <description>Enable or disable interrupt for event CH6LIMITH</description>
117881 <description>Disable</description>
117886 <description>Enable</description>
117893 <description>Enable or disable interrupt for event CH6LIMITL</description>
117899 <description>Disable</description>
117904 <description>Enable</description>
117911 <description>Enable or disable interrupt for event CH7LIMITH</description>
117917 <description>Disable</description>
117922 <description>Enable</description>
117929 <description>Enable or disable interrupt for event CH7LIMITL</description>
117935 <description>Disable</description>
117940 <description>Enable</description>
117949 <description>Enable interrupt</description>
117957 <description>Write '1' to enable interrupt for event STARTED</description>
117964 <description>Read: Disabled</description>
117969 <description>Read: Enabled</description>
117977 <description>Enable</description>
117984 <description>Write '1' to enable interrupt for event END</description>
117991 <description>Read: Disabled</description>
117996 <description>Read: Enabled</description>
118004 <description>Enable</description>
118011 <description>Write '1' to enable interrupt for event DONE</description>
118018 <description>Read: Disabled</description>
118023 <description>Read: Enabled</description>
118031 <description>Enable</description>
118038 <description>Write '1' to enable interrupt for event RESULTDONE</description>
118045 <description>Read: Disabled</description>
118050 <description>Read: Enabled</description>
118058 <description>Enable</description>
118065 <description>Write '1' to enable interrupt for event CALIBRATEDONE</description>
118072 <description>Read: Disabled</description>
118077 <description>Read: Enabled</description>
118085 <description>Enable</description>
118092 <description>Write '1' to enable interrupt for event STOPPED</description>
118099 <description>Read: Disabled</description>
118104 <description>Read: Enabled</description>
118112 <description>Enable</description>
118119 <description>Write '1' to enable interrupt for event CH0LIMITH</description>
118126 <description>Read: Disabled</description>
118131 <description>Read: Enabled</description>
118139 <description>Enable</description>
118146 <description>Write '1' to enable interrupt for event CH0LIMITL</description>
118153 <description>Read: Disabled</description>
118158 <description>Read: Enabled</description>
118166 <description>Enable</description>
118173 <description>Write '1' to enable interrupt for event CH1LIMITH</description>
118180 <description>Read: Disabled</description>
118185 <description>Read: Enabled</description>
118193 <description>Enable</description>
118200 <description>Write '1' to enable interrupt for event CH1LIMITL</description>
118207 <description>Read: Disabled</description>
118212 <description>Read: Enabled</description>
118220 <description>Enable</description>
118227 <description>Write '1' to enable interrupt for event CH2LIMITH</description>
118234 <description>Read: Disabled</description>
118239 <description>Read: Enabled</description>
118247 <description>Enable</description>
118254 <description>Write '1' to enable interrupt for event CH2LIMITL</description>
118261 <description>Read: Disabled</description>
118266 <description>Read: Enabled</description>
118274 <description>Enable</description>
118281 <description>Write '1' to enable interrupt for event CH3LIMITH</description>
118288 <description>Read: Disabled</description>
118293 <description>Read: Enabled</description>
118301 <description>Enable</description>
118308 <description>Write '1' to enable interrupt for event CH3LIMITL</description>
118315 <description>Read: Disabled</description>
118320 <description>Read: Enabled</description>
118328 <description>Enable</description>
118335 <description>Write '1' to enable interrupt for event CH4LIMITH</description>
118342 <description>Read: Disabled</description>
118347 <description>Read: Enabled</description>
118355 <description>Enable</description>
118362 <description>Write '1' to enable interrupt for event CH4LIMITL</description>
118369 <description>Read: Disabled</description>
118374 <description>Read: Enabled</description>
118382 <description>Enable</description>
118389 <description>Write '1' to enable interrupt for event CH5LIMITH</description>
118396 <description>Read: Disabled</description>
118401 <description>Read: Enabled</description>
118409 <description>Enable</description>
118416 <description>Write '1' to enable interrupt for event CH5LIMITL</description>
118423 <description>Read: Disabled</description>
118428 <description>Read: Enabled</description>
118436 <description>Enable</description>
118443 <description>Write '1' to enable interrupt for event CH6LIMITH</description>
118450 <description>Read: Disabled</description>
118455 <description>Read: Enabled</description>
118463 <description>Enable</description>
118470 <description>Write '1' to enable interrupt for event CH6LIMITL</description>
118477 <description>Read: Disabled</description>
118482 <description>Read: Enabled</description>
118490 <description>Enable</description>
118497 <description>Write '1' to enable interrupt for event CH7LIMITH</description>
118504 <description>Read: Disabled</description>
118509 <description>Read: Enabled</description>
118517 <description>Enable</description>
118524 <description>Write '1' to enable interrupt for event CH7LIMITL</description>
118531 <description>Read: Disabled</description>
118536 <description>Read: Enabled</description>
118544 <description>Enable</description>
118553 <description>Disable interrupt</description>
118561 <description>Write '1' to disable interrupt for event STARTED</description>
118568 <description>Read: Disabled</description>
118573 <description>Read: Enabled</description>
118581 <description>Disable</description>
118588 <description>Write '1' to disable interrupt for event END</description>
118595 <description>Read: Disabled</description>
118600 <description>Read: Enabled</description>
118608 <description>Disable</description>
118615 <description>Write '1' to disable interrupt for event DONE</description>
118622 <description>Read: Disabled</description>
118627 <description>Read: Enabled</description>
118635 <description>Disable</description>
118642 <description>Write '1' to disable interrupt for event RESULTDONE</description>
118649 <description>Read: Disabled</description>
118654 <description>Read: Enabled</description>
118662 <description>Disable</description>
118669 <description>Write '1' to disable interrupt for event CALIBRATEDONE</description>
118676 <description>Read: Disabled</description>
118681 <description>Read: Enabled</description>
118689 <description>Disable</description>
118696 <description>Write '1' to disable interrupt for event STOPPED</description>
118703 <description>Read: Disabled</description>
118708 <description>Read: Enabled</description>
118716 <description>Disable</description>
118723 <description>Write '1' to disable interrupt for event CH0LIMITH</description>
118730 <description>Read: Disabled</description>
118735 <description>Read: Enabled</description>
118743 <description>Disable</description>
118750 <description>Write '1' to disable interrupt for event CH0LIMITL</description>
118757 <description>Read: Disabled</description>
118762 <description>Read: Enabled</description>
118770 <description>Disable</description>
118777 <description>Write '1' to disable interrupt for event CH1LIMITH</description>
118784 <description>Read: Disabled</description>
118789 <description>Read: Enabled</description>
118797 <description>Disable</description>
118804 <description>Write '1' to disable interrupt for event CH1LIMITL</description>
118811 <description>Read: Disabled</description>
118816 <description>Read: Enabled</description>
118824 <description>Disable</description>
118831 <description>Write '1' to disable interrupt for event CH2LIMITH</description>
118838 <description>Read: Disabled</description>
118843 <description>Read: Enabled</description>
118851 <description>Disable</description>
118858 <description>Write '1' to disable interrupt for event CH2LIMITL</description>
118865 <description>Read: Disabled</description>
118870 <description>Read: Enabled</description>
118878 <description>Disable</description>
118885 <description>Write '1' to disable interrupt for event CH3LIMITH</description>
118892 <description>Read: Disabled</description>
118897 <description>Read: Enabled</description>
118905 <description>Disable</description>
118912 <description>Write '1' to disable interrupt for event CH3LIMITL</description>
118919 <description>Read: Disabled</description>
118924 <description>Read: Enabled</description>
118932 <description>Disable</description>
118939 <description>Write '1' to disable interrupt for event CH4LIMITH</description>
118946 <description>Read: Disabled</description>
118951 <description>Read: Enabled</description>
118959 <description>Disable</description>
118966 <description>Write '1' to disable interrupt for event CH4LIMITL</description>
118973 <description>Read: Disabled</description>
118978 <description>Read: Enabled</description>
118986 <description>Disable</description>
118993 <description>Write '1' to disable interrupt for event CH5LIMITH</description>
119000 <description>Read: Disabled</description>
119005 <description>Read: Enabled</description>
119013 <description>Disable</description>
119020 <description>Write '1' to disable interrupt for event CH5LIMITL</description>
119027 <description>Read: Disabled</description>
119032 <description>Read: Enabled</description>
119040 <description>Disable</description>
119047 <description>Write '1' to disable interrupt for event CH6LIMITH</description>
119054 <description>Read: Disabled</description>
119059 <description>Read: Enabled</description>
119067 <description>Disable</description>
119074 <description>Write '1' to disable interrupt for event CH6LIMITL</description>
119081 <description>Read: Disabled</description>
119086 <description>Read: Enabled</description>
119094 <description>Disable</description>
119101 <description>Write '1' to disable interrupt for event CH7LIMITH</description>
119108 <description>Read: Disabled</description>
119113 <description>Read: Enabled</description>
119121 <description>Disable</description>
119128 <description>Write '1' to disable interrupt for event CH7LIMITL</description>
119135 <description>Read: Disabled</description>
119140 <description>Read: Enabled</description>
119148 <description>Disable</description>
119157 <description>Status</description>
119165 <description>Status</description>
119171 <description>ADC is ready. No on-going conversion.</description>
119176 <description>ADC is busy. Single conversion in progress.</description>
119185 <description>Unspecified</description>
119193 <description>Description collection: Linearity calibration coefficient</description>
119201 <description>value</description>
119210 <description>Enable or disable ADC</description>
119218 <description>Enable or disable ADC</description>
119224 <description>Disable ADC</description>
119229 <description>Enable ADC</description>
119240 <description>Unspecified</description>
119246 <description>Description cluster: Input positive pin selection for CH[n]</description>
119254 <description>GPIO pin selection.</description>
119260 <description>GPIO port selection</description>
119266 <description>Connection</description>
119272 <description>Not connected</description>
119277 <description>Select analog input</description>
119286 <description>Description cluster: Input negative pin selection for CH[n]</description>
119294 <description>GPIO pin selection.</description>
119300 <description>GPIO Port selection</description>
119306 <description>Connection</description>
119312 <description>Not connected</description>
119317 <description>Select analog input</description>
119326 <description>Description cluster: Input configuration for CH[n]</description>
119334 <description>Gain control</description>
119340 <description>2/3</description>
119345 <description>1</description>
119350 <description>2</description>
119355 <description>4</description>
119360 <description>1/2</description>
119367 <description>Enable burst mode</description>
119373 <description>Burst mode is disabled (normal operation)</description>
119378 …<description>Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, …
119385 <description>Reference control</description>
119391 <description>Internal reference (1.024 V)</description>
119396 <description>External reference given at PADC_EXT_REF_1V2</description>
119403 <description>Enable differential mode</description>
119409 …<description>Single ended, PSELN will be ignored, negative input to ADC shorted to GND</descriptio…
119414 <description>Differential</description>
119421 …<description>Acquisition time, the time the ADC uses to sample the input voltage. Resulting acquis…
119427 … <description>Conversion time. Resulting conversion time is ((TCONV+1) x 250 ns)</description>
119435 … <description>Description cluster: High/low limits for event monitoring a channel</description>
119443 <description>Low level limit</description>
119449 <description>High level limit</description>
119458 <description>Resolution configuration</description>
119466 <description>Set the resolution</description>
119472 <description>8 bit</description>
119477 <description>10 bit</description>
119482 <description>12 bit</description>
119487 <description>14 bit</description>
119496 …description>Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTIO…
119504 <description>Oversample control</description>
119510 <description>Bypass oversampling</description>
119515 <description>Oversample 2x</description>
119520 <description>Oversample 4x</description>
119525 <description>Oversample 8x</description>
119530 <description>Oversample 16x</description>
119535 <description>Oversample 32x</description>
119540 <description>Oversample 64x</description>
119545 <description>Oversample 128x</description>
119550 <description>Oversample 256x</description>
119559 <description>Controls normal or continuous sample rate</description>
119567 <description>Capture and compare value. Sample rate is 16 MHz/CC</description>
119573 <description>Select mode for sample rate control</description>
119579 <description>Rate is controlled from SAMPLE task</description>
119584 … <description>Rate is controlled from local timer (use CC to control the rate)</description>
119593 <description>RESULT EasyDMA channel</description>
119599 <description>Data pointer</description>
119607 <description>Data pointer</description>
119615 <description>Maximum number of buffer bytes to transfer</description>
119623 <description>Maximum number of buffer bytes to transfer</description>
119631 …<description>Number of buffer bytes transferred since last START, updated after the END or STOPPED…
119639 …<description>Number of buffer bytes transferred since last START, updated after the END or STOPPED…
119647 …<description>Number of buffer bytes transferred since last START, continuously updated</descriptio…
119655 …<description>Number of buffer bytes transferred since last START, continuously updated.</descripti…
119664 <description>Enable noise shaping</description>
119672 <description>Enable noise shaping</description>
119678 … <description>Disable noiseshaping. Oversampling based on accumulate and average.</description>
119683 …description>Noiseshaping and decimating. Larger passband. Provides a 100kS/s cut off frequency, 8x…
119688 …description>Noiseshaping and decimating. Smaller passband. Recommended resolution setting is 14 bi…
119699 <description>Comparator</description>
119717 <description>Start comparator</description>
119725 <description>Start comparator</description>
119731 <description>Trigger task</description>
119740 <description>Stop comparator</description>
119748 <description>Stop comparator</description>
119754 <description>Trigger task</description>
119763 …<description>Sample comparator value. This task requires that COMP has been started by the START T…
119771 …<description>Sample comparator value. This task requires that COMP has been started by the START T…
119777 <description>Trigger task</description>
119786 <description>Subscribe configuration for task START</description>
119794 <description>DPPI channel that task START will subscribe to</description>
119805 <description>Disable subscription</description>
119810 <description>Enable subscription</description>
119819 <description>Subscribe configuration for task STOP</description>
119827 <description>DPPI channel that task STOP will subscribe to</description>
119838 <description>Disable subscription</description>
119843 <description>Enable subscription</description>
119852 <description>Subscribe configuration for task SAMPLE</description>
119860 <description>DPPI channel that task SAMPLE will subscribe to</description>
119871 <description>Disable subscription</description>
119876 <description>Enable subscription</description>
119885 <description>COMP is ready and output is valid</description>
119893 <description>COMP is ready and output is valid</description>
119899 <description>Event not generated</description>
119904 <description>Event generated</description>
119913 <description>Downward crossing</description>
119921 <description>Downward crossing</description>
119927 <description>Event not generated</description>
119932 <description>Event generated</description>
119941 <description>Upward crossing</description>
119949 <description>Upward crossing</description>
119955 <description>Event not generated</description>
119960 <description>Event generated</description>
119969 <description>Downward or upward crossing</description>
119977 <description>Downward or upward crossing</description>
119983 <description>Event not generated</description>
119988 <description>Event generated</description>
119997 <description>Publish configuration for event READY</description>
120005 <description>DPPI channel that event READY will publish to</description>
120016 <description>Disable publishing</description>
120021 <description>Enable publishing</description>
120030 <description>Publish configuration for event DOWN</description>
120038 <description>DPPI channel that event DOWN will publish to</description>
120049 <description>Disable publishing</description>
120054 <description>Enable publishing</description>
120063 <description>Publish configuration for event UP</description>
120071 <description>DPPI channel that event UP will publish to</description>
120082 <description>Disable publishing</description>
120087 <description>Enable publishing</description>
120096 <description>Publish configuration for event CROSS</description>
120104 <description>DPPI channel that event CROSS will publish to</description>
120115 <description>Disable publishing</description>
120120 <description>Enable publishing</description>
120129 <description>Shortcuts between local events and tasks</description>
120137 <description>Shortcut between event READY and task SAMPLE</description>
120143 <description>Disable shortcut</description>
120148 <description>Enable shortcut</description>
120155 <description>Shortcut between event READY and task STOP</description>
120161 <description>Disable shortcut</description>
120166 <description>Enable shortcut</description>
120173 <description>Shortcut between event DOWN and task STOP</description>
120179 <description>Disable shortcut</description>
120184 <description>Enable shortcut</description>
120191 <description>Shortcut between event UP and task STOP</description>
120197 <description>Disable shortcut</description>
120202 <description>Enable shortcut</description>
120209 <description>Shortcut between event CROSS and task STOP</description>
120215 <description>Disable shortcut</description>
120220 <description>Enable shortcut</description>
120229 <description>Enable or disable interrupt</description>
120237 <description>Enable or disable interrupt for event READY</description>
120243 <description>Disable</description>
120248 <description>Enable</description>
120255 <description>Enable or disable interrupt for event DOWN</description>
120261 <description>Disable</description>
120266 <description>Enable</description>
120273 <description>Enable or disable interrupt for event UP</description>
120279 <description>Disable</description>
120284 <description>Enable</description>
120291 <description>Enable or disable interrupt for event CROSS</description>
120297 <description>Disable</description>
120302 <description>Enable</description>
120311 <description>Enable interrupt</description>
120319 <description>Write '1' to enable interrupt for event READY</description>
120326 <description>Read: Disabled</description>
120331 <description>Read: Enabled</description>
120339 <description>Enable</description>
120346 <description>Write '1' to enable interrupt for event DOWN</description>
120353 <description>Read: Disabled</description>
120358 <description>Read: Enabled</description>
120366 <description>Enable</description>
120373 <description>Write '1' to enable interrupt for event UP</description>
120380 <description>Read: Disabled</description>
120385 <description>Read: Enabled</description>
120393 <description>Enable</description>
120400 <description>Write '1' to enable interrupt for event CROSS</description>
120407 <description>Read: Disabled</description>
120412 <description>Read: Enabled</description>
120420 <description>Enable</description>
120429 <description>Disable interrupt</description>
120437 <description>Write '1' to disable interrupt for event READY</description>
120444 <description>Read: Disabled</description>
120449 <description>Read: Enabled</description>
120457 <description>Disable</description>
120464 <description>Write '1' to disable interrupt for event DOWN</description>
120471 <description>Read: Disabled</description>
120476 <description>Read: Enabled</description>
120484 <description>Disable</description>
120491 <description>Write '1' to disable interrupt for event UP</description>
120498 <description>Read: Disabled</description>
120503 <description>Read: Enabled</description>
120511 <description>Disable</description>
120518 <description>Write '1' to disable interrupt for event CROSS</description>
120525 <description>Read: Disabled</description>
120530 <description>Read: Enabled</description>
120538 <description>Disable</description>
120547 <description>Pending interrupts</description>
120555 <description>Read pending status of interrupt for event READY</description>
120562 <description>Read: Not pending</description>
120567 <description>Read: Pending</description>
120574 <description>Read pending status of interrupt for event DOWN</description>
120581 <description>Read: Not pending</description>
120586 <description>Read: Pending</description>
120593 <description>Read pending status of interrupt for event UP</description>
120600 <description>Read: Not pending</description>
120605 <description>Read: Pending</description>
120612 <description>Read pending status of interrupt for event CROSS</description>
120619 <description>Read: Not pending</description>
120624 <description>Read: Pending</description>
120633 <description>Compare result</description>
120641 <description>Result of last compare. Decision point SAMPLE task.</description>
120647 … <description>Input voltage is below the threshold (VIN+ &lt; VIN-)</description>
120652 … <description>Input voltage is above the threshold (VIN+ &gt; VIN-)</description>
120661 <description>COMP enable</description>
120669 <description>Enable or disable COMP</description>
120675 <description>Disable</description>
120680 <description>Enable</description>
120689 <description>Pin select</description>
120697 <description>Analog pin select</description>
120703 <description>GPIO Port selection</description>
120711 <description>Reference source select for single-ended mode</description>
120719 <description>Reference select</description>
120725 <description>VREF = internal 1.2 V reference</description>
120730 <description>VREF = internal 1.8 V reference</description>
120735 <description>VREF = AREF</description>
120744 <description>External reference select</description>
120752 <description>External analog reference pin select</description>
120758 <description>GPIO Port selection</description>
120766 <description>Threshold configuration for hysteresis unit</description>
120774 <description>VDOWN = (THDOWN+1)/64*VREF</description>
120780 <description>VUP = (THUP+1)/64*VREF</description>
120788 <description>Mode configuration</description>
120796 <description>Speed and power modes</description>
120802 <description>Low-power mode</description>
120807 <description>High-speed mode</description>
120814 <description>Main operation modes</description>
120820 <description>Single-ended mode</description>
120825 <description>Differential mode</description>
120834 <description>Comparator hysteresis enable</description>
120842 <description>Comparator hysteresis</description>
120848 <description>Comparator hysteresis disabled</description>
120853 <description>Comparator hysteresis enabled</description>
120862 <description>Current source select on analog input</description>
120870 <description>Current source select on analog input</description>
120876 <description>Current source disabled</description>
120881 <description>Current source enabled (+/- 2.5 uA)</description>
120886 <description>Current source enabled (+/- 5 uA)</description>
120891 <description>Current source enabled (+/- 10 uA)</description>
120900 <description>Trim internal band gap reference</description>
120908 <description>Trimming value in 2's complement</description>
120918 <description>Low-power comparator</description>
120937 <description>Start comparator</description>
120945 <description>Start comparator</description>
120951 <description>Trigger task</description>
120960 <description>Stop comparator</description>
120968 <description>Stop comparator</description>
120974 <description>Trigger task</description>
120983 …<description>Sample comparator value. This task requires that LPCOMP has been started by the START…
120991 …<description>Sample comparator value. This task requires that LPCOMP has been started by the START…
120997 <description>Trigger task</description>
121006 <description>Subscribe configuration for task START</description>
121014 <description>DPPI channel that task START will subscribe to</description>
121025 <description>Disable subscription</description>
121030 <description>Enable subscription</description>
121039 <description>Subscribe configuration for task STOP</description>
121047 <description>DPPI channel that task STOP will subscribe to</description>
121058 <description>Disable subscription</description>
121063 <description>Enable subscription</description>
121072 <description>Subscribe configuration for task SAMPLE</description>
121080 <description>DPPI channel that task SAMPLE will subscribe to</description>
121091 <description>Disable subscription</description>
121096 <description>Enable subscription</description>
121105 <description>LPCOMP is ready and output is valid</description>
121113 <description>LPCOMP is ready and output is valid</description>
121119 <description>Event not generated</description>
121124 <description>Event generated</description>
121133 <description>Downward crossing</description>
121141 <description>Downward crossing</description>
121147 <description>Event not generated</description>
121152 <description>Event generated</description>
121161 <description>Upward crossing</description>
121169 <description>Upward crossing</description>
121175 <description>Event not generated</description>
121180 <description>Event generated</description>
121189 <description>Downward or upward crossing</description>
121197 <description>Downward or upward crossing</description>
121203 <description>Event not generated</description>
121208 <description>Event generated</description>
121217 <description>Publish configuration for event READY</description>
121225 <description>DPPI channel that event READY will publish to</description>
121236 <description>Disable publishing</description>
121241 <description>Enable publishing</description>
121250 <description>Publish configuration for event DOWN</description>
121258 <description>DPPI channel that event DOWN will publish to</description>
121269 <description>Disable publishing</description>
121274 <description>Enable publishing</description>
121283 <description>Publish configuration for event UP</description>
121291 <description>DPPI channel that event UP will publish to</description>
121302 <description>Disable publishing</description>
121307 <description>Enable publishing</description>
121316 <description>Publish configuration for event CROSS</description>
121324 <description>DPPI channel that event CROSS will publish to</description>
121335 <description>Disable publishing</description>
121340 <description>Enable publishing</description>
121349 <description>Shortcuts between local events and tasks</description>
121357 <description>Shortcut between event READY and task SAMPLE</description>
121363 <description>Disable shortcut</description>
121368 <description>Enable shortcut</description>
121375 <description>Shortcut between event READY and task STOP</description>
121381 <description>Disable shortcut</description>
121386 <description>Enable shortcut</description>
121393 <description>Shortcut between event DOWN and task STOP</description>
121399 <description>Disable shortcut</description>
121404 <description>Enable shortcut</description>
121411 <description>Shortcut between event UP and task STOP</description>
121417 <description>Disable shortcut</description>
121422 <description>Enable shortcut</description>
121429 <description>Shortcut between event CROSS and task STOP</description>
121435 <description>Disable shortcut</description>
121440 <description>Enable shortcut</description>
121449 <description>Enable or disable interrupt</description>
121457 <description>Enable or disable interrupt for event READY</description>
121463 <description>Disable</description>
121468 <description>Enable</description>
121475 <description>Enable or disable interrupt for event DOWN</description>
121481 <description>Disable</description>
121486 <description>Enable</description>
121493 <description>Enable or disable interrupt for event UP</description>
121499 <description>Disable</description>
121504 <description>Enable</description>
121511 <description>Enable or disable interrupt for event CROSS</description>
121517 <description>Disable</description>
121522 <description>Enable</description>
121531 <description>Enable interrupt</description>
121539 <description>Write '1' to enable interrupt for event READY</description>
121546 <description>Read: Disabled</description>
121551 <description>Read: Enabled</description>
121559 <description>Enable</description>
121566 <description>Write '1' to enable interrupt for event DOWN</description>
121573 <description>Read: Disabled</description>
121578 <description>Read: Enabled</description>
121586 <description>Enable</description>
121593 <description>Write '1' to enable interrupt for event UP</description>
121600 <description>Read: Disabled</description>
121605 <description>Read: Enabled</description>
121613 <description>Enable</description>
121620 <description>Write '1' to enable interrupt for event CROSS</description>
121627 <description>Read: Disabled</description>
121632 <description>Read: Enabled</description>
121640 <description>Enable</description>
121649 <description>Disable interrupt</description>
121657 <description>Write '1' to disable interrupt for event READY</description>
121664 <description>Read: Disabled</description>
121669 <description>Read: Enabled</description>
121677 <description>Disable</description>
121684 <description>Write '1' to disable interrupt for event DOWN</description>
121691 <description>Read: Disabled</description>
121696 <description>Read: Enabled</description>
121704 <description>Disable</description>
121711 <description>Write '1' to disable interrupt for event UP</description>
121718 <description>Read: Disabled</description>
121723 <description>Read: Enabled</description>
121731 <description>Disable</description>
121738 <description>Write '1' to disable interrupt for event CROSS</description>
121745 <description>Read: Disabled</description>
121750 <description>Read: Enabled</description>
121758 <description>Disable</description>
121767 <description>Pending interrupts</description>
121775 <description>Read pending status of interrupt for event READY</description>
121782 <description>Read: Not pending</description>
121787 <description>Read: Pending</description>
121794 <description>Read pending status of interrupt for event DOWN</description>
121801 <description>Read: Not pending</description>
121806 <description>Read: Pending</description>
121813 <description>Read pending status of interrupt for event UP</description>
121820 <description>Read: Not pending</description>
121825 <description>Read: Pending</description>
121832 <description>Read pending status of interrupt for event CROSS</description>
121839 <description>Read: Not pending</description>
121844 <description>Read: Pending</description>
121853 <description>Compare result</description>
121861 <description>Result of last compare. Decision point SAMPLE task.</description>
121867 … <description>Input voltage is below the reference threshold (VIN+ &lt; VIN-)</description>
121872 … <description>Input voltage is above the reference threshold (VIN+ &gt; VIN-)</description>
121881 <description>Enable LPCOMP</description>
121889 <description>Enable or disable LPCOMP</description>
121895 <description>Disable</description>
121900 <description>Enable</description>
121909 <description>Input pin select</description>
121917 <description>Analog pin select</description>
121923 <description>GPIO Port selection</description>
121931 <description>Reference select</description>
121939 <description>Reference select</description>
121945 <description>VDD * 1/8 selected as reference</description>
121950 <description>VDD * 2/8 selected as reference</description>
121955 <description>VDD * 3/8 selected as reference</description>
121960 <description>VDD * 4/8 selected as reference</description>
121965 <description>VDD * 5/8 selected as reference</description>
121970 <description>VDD * 6/8 selected as reference</description>
121975 <description>VDD * 7/8 selected as reference</description>
121980 <description>External analog reference selected</description>
121985 <description>VDD * 1/16 selected as reference</description>
121990 <description>VDD * 3/16 selected as reference</description>
121995 <description>VDD * 5/16 selected as reference</description>
122000 <description>VDD * 7/16 selected as reference</description>
122005 <description>VDD * 9/16 selected as reference</description>
122010 <description>VDD * 11/16 selected as reference</description>
122015 <description>VDD * 13/16 selected as reference</description>
122020 <description>VDD * 15/16 selected as reference</description>
122029 <description>External reference select</description>
122037 <description>External analog reference pin select</description>
122043 <description>GPIO Port selection</description>
122051 <description>Analog detect configuration</description>
122059 <description>Analog detect configuration</description>
122065 …<description>Generate ANADETECT on crossing, both upward crossing and downward crossing</descripti…
122070 <description>Generate ANADETECT on upward crossing only</description>
122075 <description>Generate ANADETECT on downward crossing only</description>
122084 <description>Comparator hysteresis enable</description>
122092 <description>Comparator hysteresis enable</description>
122098 <description>Comparator hysteresis disabled</description>
122103 <description>Comparator hysteresis enabled</description>
122114 <description>Temperature Sensor</description>
122132 <description>Start temperature measurement</description>
122140 <description>Start temperature measurement</description>
122146 <description>Trigger task</description>
122155 <description>Stop temperature measurement</description>
122163 <description>Stop temperature measurement</description>
122169 <description>Trigger task</description>
122178 <description>Subscribe configuration for task START</description>
122186 <description>DPPI channel that task START will subscribe to</description>
122197 <description>Disable subscription</description>
122202 <description>Enable subscription</description>
122211 <description>Subscribe configuration for task STOP</description>
122219 <description>DPPI channel that task STOP will subscribe to</description>
122230 <description>Disable subscription</description>
122235 <description>Enable subscription</description>
122244 <description>Temperature measurement complete, data ready</description>
122252 <description>Temperature measurement complete, data ready</description>
122258 <description>Event not generated</description>
122263 <description>Event generated</description>
122272 <description>Publish configuration for event DATARDY</description>
122280 <description>DPPI channel that event DATARDY will publish to</description>
122291 <description>Disable publishing</description>
122296 <description>Enable publishing</description>
122305 <description>Enable interrupt</description>
122313 <description>Write '1' to enable interrupt for event DATARDY</description>
122320 <description>Read: Disabled</description>
122325 <description>Read: Enabled</description>
122333 <description>Enable</description>
122342 <description>Disable interrupt</description>
122350 <description>Write '1' to disable interrupt for event DATARDY</description>
122357 <description>Read: Disabled</description>
122362 <description>Read: Enabled</description>
122370 <description>Disable</description>
122379 <description>Temperature in degC (0.25deg steps)</description>
122388 <description>Temperature in degC (0.25deg steps)</description>
122396 <description>Slope of 1st piece wise linear function</description>
122404 <description>Slope of 1st piece wise linear function</description>
122412 <description>Slope of 2nd piece wise linear function</description>
122420 <description>Slope of 2nd piece wise linear function</description>
122428 <description>Slope of 3rd piece wise linear function</description>
122436 <description>Slope of 3rd piece wise linear function</description>
122444 <description>Slope of 4th piece wise linear function</description>
122452 <description>Slope of 4th piece wise linear function</description>
122460 <description>Slope of 5th piece wise linear function</description>
122468 <description>Slope of 5th piece wise linear function</description>
122476 <description>Slope of 6th piece wise linear function</description>
122484 <description>Slope of 6th piece wise linear function</description>
122492 <description>Slope of 7th piece wise linear function</description>
122500 <description>Slope of 7th piece wise linear function</description>
122508 <description>y-intercept of 1st piece wise linear function</description>
122516 <description>y-intercept of 1st piece wise linear function</description>
122524 <description>y-intercept of 2nd piece wise linear function</description>
122532 <description>y-intercept of 2nd piece wise linear function</description>
122540 <description>y-intercept of 3rd piece wise linear function</description>
122548 <description>y-intercept of 3rd piece wise linear function</description>
122556 <description>y-intercept of 4th piece wise linear function</description>
122564 <description>y-intercept of 4th piece wise linear function</description>
122572 <description>y-intercept of 5th piece wise linear function</description>
122580 <description>y-intercept of 5th piece wise linear function</description>
122588 <description>y-intercept of 6th piece wise linear function</description>
122596 <description>y-intercept of 6th piece wise linear function</description>
122604 <description>y-intercept of 7th piece wise linear function</description>
122612 <description>y-intercept of 7th piece wise linear function</description>
122620 <description>End point of 1st piece wise linear function</description>
122628 <description>End point of 1st piece wise linear function</description>
122636 <description>End point of 2nd piece wise linear function</description>
122644 <description>End point of 2nd piece wise linear function</description>
122652 <description>End point of 3rd piece wise linear function</description>
122660 <description>End point of 3rd piece wise linear function</description>
122668 <description>End point of 4th piece wise linear function</description>
122676 <description>End point of 4th piece wise linear function</description>
122684 <description>End point of 5th piece wise linear function</description>
122692 <description>End point of 5th piece wise linear function</description>
122700 <description>End point of 6th piece wise linear function</description>
122708 <description>End point of 6th piece wise linear function</description>
122718 <description>NFC-A compatible radio NFC-A compatible radio</description>
122736 …<description>Activate NFCT peripheral for incoming and outgoing frames, change state to activated<…
122744 …<description>Activate NFCT peripheral for incoming and outgoing frames, change state to activated<…
122750 <description>Trigger task</description>
122759 <description>Disable NFCT peripheral</description>
122767 <description>Disable NFCT peripheral</description>
122773 <description>Trigger task</description>
122782 <description>Enable NFC sense field mode, change state to sense mode</description>
122790 <description>Enable NFC sense field mode, change state to sense mode</description>
122796 <description>Trigger task</description>
122805 … <description>Start transmission of an outgoing frame, change state to transmit</description>
122813 … <description>Start transmission of an outgoing frame, change state to transmit</description>
122819 <description>Trigger task</description>
122828 <description>Stops an issued transmission of a frame</description>
122836 <description>Stops an issued transmission of a frame</description>
122842 <description>Trigger task</description>
122851 <description>Initializes the EasyDMA for receive.</description>
122859 <description>Initializes the EasyDMA for receive.</description>
122865 <description>Trigger task</description>
122874 <description>Force state machine to IDLE state</description>
122882 <description>Force state machine to IDLE state</description>
122888 <description>Trigger task</description>
122897 <description>Force state machine to SLEEP_A state</description>
122905 <description>Force state machine to SLEEP_A state</description>
122911 <description>Trigger task</description>
122920 <description>Subscribe configuration for task ACTIVATE</description>
122928 <description>DPPI channel that task ACTIVATE will subscribe to</description>
122939 <description>Disable subscription</description>
122944 <description>Enable subscription</description>
122953 <description>Subscribe configuration for task DISABLE</description>
122961 <description>DPPI channel that task DISABLE will subscribe to</description>
122972 <description>Disable subscription</description>
122977 <description>Enable subscription</description>
122986 <description>Subscribe configuration for task SENSE</description>
122994 <description>DPPI channel that task SENSE will subscribe to</description>
123005 <description>Disable subscription</description>
123010 <description>Enable subscription</description>
123019 <description>Subscribe configuration for task STARTTX</description>
123027 <description>DPPI channel that task STARTTX will subscribe to</description>
123038 <description>Disable subscription</description>
123043 <description>Enable subscription</description>
123052 <description>Subscribe configuration for task STOPTX</description>
123060 <description>DPPI channel that task STOPTX will subscribe to</description>
123071 <description>Disable subscription</description>
123076 <description>Enable subscription</description>
123085 <description>Subscribe configuration for task ENABLERXDATA</description>
123093 <description>DPPI channel that task ENABLERXDATA will subscribe to</description>
123104 <description>Disable subscription</description>
123109 <description>Enable subscription</description>
123118 <description>Subscribe configuration for task GOIDLE</description>
123126 <description>DPPI channel that task GOIDLE will subscribe to</description>
123137 <description>Disable subscription</description>
123142 <description>Enable subscription</description>
123151 <description>Subscribe configuration for task GOSLEEP</description>
123159 <description>DPPI channel that task GOSLEEP will subscribe to</description>
123170 <description>Disable subscription</description>
123175 <description>Enable subscription</description>
123184 <description>The NFCT peripheral is ready to receive and send frames</description>
123192 <description>The NFCT peripheral is ready to receive and send frames</description>
123198 <description>Event not generated</description>
123203 <description>Event generated</description>
123212 <description>Remote NFC field detected</description>
123220 <description>Remote NFC field detected</description>
123226 <description>Event not generated</description>
123231 <description>Event generated</description>
123240 <description>Remote NFC field lost</description>
123248 <description>Remote NFC field lost</description>
123254 <description>Event not generated</description>
123259 <description>Event generated</description>
123268 <description>Marks the start of the first symbol of a transmitted frame</description>
123276 <description>Marks the start of the first symbol of a transmitted frame</description>
123282 <description>Event not generated</description>
123287 <description>Event generated</description>
123296 <description>Marks the end of the last transmitted on-air symbol of a frame</description>
123304 … <description>Marks the end of the last transmitted on-air symbol of a frame</description>
123310 <description>Event not generated</description>
123315 <description>Event generated</description>
123324 <description>Marks the end of the first symbol of a received frame</description>
123332 <description>Marks the end of the first symbol of a received frame</description>
123338 <description>Event not generated</description>
123343 <description>Event generated</description>
123352 …<description>Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has …
123360 …<description>Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has …
123366 <description>Event not generated</description>
123371 <description>Event generated</description>
123380 …<description>NFC error reported. The ERRORSTATUS register contains details on the source of the er…
123388 …<description>NFC error reported. The ERRORSTATUS register contains details on the source of the er…
123394 <description>Event not generated</description>
123399 <description>Event generated</description>
123408 …<description>NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the sour…
123416 …<description>NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the sour…
123422 <description>Event not generated</description>
123427 <description>Event generated</description>
123436 … <description>RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full.</description>
123444 … <description>RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full.</description>
123450 <description>Event not generated</description>
123455 <description>Event generated</description>
123464 …<description>Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer<…
123472 …<description>Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer<…
123478 <description>Event not generated</description>
123483 <description>Event generated</description>
123492 <description>Auto collision resolution process has started</description>
123500 <description>Auto collision resolution process has started</description>
123506 <description>Event not generated</description>
123511 <description>Event generated</description>
123520 <description>NFC auto collision resolution error reported.</description>
123528 <description>NFC auto collision resolution error reported.</description>
123534 <description>Event not generated</description>
123539 <description>Event generated</description>
123548 <description>NFC auto collision resolution successfully completed</description>
123556 <description>NFC auto collision resolution successfully completed</description>
123562 <description>Event not generated</description>
123567 <description>Event generated</description>
123576 <description>EasyDMA is ready to receive or send frames.</description>
123584 <description>EasyDMA is ready to receive or send frames.</description>
123590 <description>Event not generated</description>
123595 <description>Event generated</description>
123604 <description>Publish configuration for event READY</description>
123612 <description>DPPI channel that event READY will publish to</description>
123623 <description>Disable publishing</description>
123628 <description>Enable publishing</description>
123637 <description>Publish configuration for event FIELDDETECTED</description>
123645 <description>DPPI channel that event FIELDDETECTED will publish to</description>
123656 <description>Disable publishing</description>
123661 <description>Enable publishing</description>
123670 <description>Publish configuration for event FIELDLOST</description>
123678 <description>DPPI channel that event FIELDLOST will publish to</description>
123689 <description>Disable publishing</description>
123694 <description>Enable publishing</description>
123703 <description>Publish configuration for event TXFRAMESTART</description>
123711 <description>DPPI channel that event TXFRAMESTART will publish to</description>
123722 <description>Disable publishing</description>
123727 <description>Enable publishing</description>
123736 <description>Publish configuration for event TXFRAMEEND</description>
123744 <description>DPPI channel that event TXFRAMEEND will publish to</description>
123755 <description>Disable publishing</description>
123760 <description>Enable publishing</description>
123769 <description>Publish configuration for event RXFRAMESTART</description>
123777 <description>DPPI channel that event RXFRAMESTART will publish to</description>
123788 <description>Disable publishing</description>
123793 <description>Enable publishing</description>
123802 <description>Publish configuration for event RXFRAMEEND</description>
123810 <description>DPPI channel that event RXFRAMEEND will publish to</description>
123821 <description>Disable publishing</description>
123826 <description>Enable publishing</description>
123835 <description>Publish configuration for event ERROR</description>
123843 <description>DPPI channel that event ERROR will publish to</description>
123854 <description>Disable publishing</description>
123859 <description>Enable publishing</description>
123868 <description>Publish configuration for event RXERROR</description>
123876 <description>DPPI channel that event RXERROR will publish to</description>
123887 <description>Disable publishing</description>
123892 <description>Enable publishing</description>
123901 <description>Publish configuration for event ENDRX</description>
123909 <description>DPPI channel that event ENDRX will publish to</description>
123920 <description>Disable publishing</description>
123925 <description>Enable publishing</description>
123934 <description>Publish configuration for event ENDTX</description>
123942 <description>DPPI channel that event ENDTX will publish to</description>
123953 <description>Disable publishing</description>
123958 <description>Enable publishing</description>
123967 <description>Publish configuration for event AUTOCOLRESSTARTED</description>
123975 <description>DPPI channel that event AUTOCOLRESSTARTED will publish to</description>
123986 <description>Disable publishing</description>
123991 <description>Enable publishing</description>
124000 <description>Publish configuration for event COLLISION</description>
124008 <description>DPPI channel that event COLLISION will publish to</description>
124019 <description>Disable publishing</description>
124024 <description>Enable publishing</description>
124033 <description>Publish configuration for event SELECTED</description>
124041 <description>DPPI channel that event SELECTED will publish to</description>
124052 <description>Disable publishing</description>
124057 <description>Enable publishing</description>
124066 <description>Publish configuration for event STARTED</description>
124074 <description>DPPI channel that event STARTED will publish to</description>
124085 <description>Disable publishing</description>
124090 <description>Enable publishing</description>
124099 <description>Shortcuts between local events and tasks</description>
124107 <description>Shortcut between event FIELDDETECTED and task ACTIVATE</description>
124113 <description>Disable shortcut</description>
124118 <description>Enable shortcut</description>
124125 <description>Shortcut between event FIELDLOST and task SENSE</description>
124131 <description>Disable shortcut</description>
124136 <description>Enable shortcut</description>
124143 <description>Shortcut between event TXFRAMEEND and task ENABLERXDATA</description>
124149 <description>Disable shortcut</description>
124154 <description>Enable shortcut</description>
124163 <description>Enable or disable interrupt</description>
124171 <description>Enable or disable interrupt for event READY</description>
124177 <description>Disable</description>
124182 <description>Enable</description>
124189 <description>Enable or disable interrupt for event FIELDDETECTED</description>
124195 <description>Disable</description>
124200 <description>Enable</description>
124207 <description>Enable or disable interrupt for event FIELDLOST</description>
124213 <description>Disable</description>
124218 <description>Enable</description>
124225 <description>Enable or disable interrupt for event TXFRAMESTART</description>
124231 <description>Disable</description>
124236 <description>Enable</description>
124243 <description>Enable or disable interrupt for event TXFRAMEEND</description>
124249 <description>Disable</description>
124254 <description>Enable</description>
124261 <description>Enable or disable interrupt for event RXFRAMESTART</description>
124267 <description>Disable</description>
124272 <description>Enable</description>
124279 <description>Enable or disable interrupt for event RXFRAMEEND</description>
124285 <description>Disable</description>
124290 <description>Enable</description>
124297 <description>Enable or disable interrupt for event ERROR</description>
124303 <description>Disable</description>
124308 <description>Enable</description>
124315 <description>Enable or disable interrupt for event RXERROR</description>
124321 <description>Disable</description>
124326 <description>Enable</description>
124333 <description>Enable or disable interrupt for event ENDRX</description>
124339 <description>Disable</description>
124344 <description>Enable</description>
124351 <description>Enable or disable interrupt for event ENDTX</description>
124357 <description>Disable</description>
124362 <description>Enable</description>
124369 <description>Enable or disable interrupt for event AUTOCOLRESSTARTED</description>
124375 <description>Disable</description>
124380 <description>Enable</description>
124387 <description>Enable or disable interrupt for event COLLISION</description>
124393 <description>Disable</description>
124398 <description>Enable</description>
124405 <description>Enable or disable interrupt for event SELECTED</description>
124411 <description>Disable</description>
124416 <description>Enable</description>
124423 <description>Enable or disable interrupt for event STARTED</description>
124429 <description>Disable</description>
124434 <description>Enable</description>
124443 <description>Enable interrupt</description>
124451 <description>Write '1' to enable interrupt for event READY</description>
124458 <description>Read: Disabled</description>
124463 <description>Read: Enabled</description>
124471 <description>Enable</description>
124478 <description>Write '1' to enable interrupt for event FIELDDETECTED</description>
124485 <description>Read: Disabled</description>
124490 <description>Read: Enabled</description>
124498 <description>Enable</description>
124505 <description>Write '1' to enable interrupt for event FIELDLOST</description>
124512 <description>Read: Disabled</description>
124517 <description>Read: Enabled</description>
124525 <description>Enable</description>
124532 <description>Write '1' to enable interrupt for event TXFRAMESTART</description>
124539 <description>Read: Disabled</description>
124544 <description>Read: Enabled</description>
124552 <description>Enable</description>
124559 <description>Write '1' to enable interrupt for event TXFRAMEEND</description>
124566 <description>Read: Disabled</description>
124571 <description>Read: Enabled</description>
124579 <description>Enable</description>
124586 <description>Write '1' to enable interrupt for event RXFRAMESTART</description>
124593 <description>Read: Disabled</description>
124598 <description>Read: Enabled</description>
124606 <description>Enable</description>
124613 <description>Write '1' to enable interrupt for event RXFRAMEEND</description>
124620 <description>Read: Disabled</description>
124625 <description>Read: Enabled</description>
124633 <description>Enable</description>
124640 <description>Write '1' to enable interrupt for event ERROR</description>
124647 <description>Read: Disabled</description>
124652 <description>Read: Enabled</description>
124660 <description>Enable</description>
124667 <description>Write '1' to enable interrupt for event RXERROR</description>
124674 <description>Read: Disabled</description>
124679 <description>Read: Enabled</description>
124687 <description>Enable</description>
124694 <description>Write '1' to enable interrupt for event ENDRX</description>
124701 <description>Read: Disabled</description>
124706 <description>Read: Enabled</description>
124714 <description>Enable</description>
124721 <description>Write '1' to enable interrupt for event ENDTX</description>
124728 <description>Read: Disabled</description>
124733 <description>Read: Enabled</description>
124741 <description>Enable</description>
124748 <description>Write '1' to enable interrupt for event AUTOCOLRESSTARTED</description>
124755 <description>Read: Disabled</description>
124760 <description>Read: Enabled</description>
124768 <description>Enable</description>
124775 <description>Write '1' to enable interrupt for event COLLISION</description>
124782 <description>Read: Disabled</description>
124787 <description>Read: Enabled</description>
124795 <description>Enable</description>
124802 <description>Write '1' to enable interrupt for event SELECTED</description>
124809 <description>Read: Disabled</description>
124814 <description>Read: Enabled</description>
124822 <description>Enable</description>
124829 <description>Write '1' to enable interrupt for event STARTED</description>
124836 <description>Read: Disabled</description>
124841 <description>Read: Enabled</description>
124849 <description>Enable</description>
124858 <description>Disable interrupt</description>
124866 <description>Write '1' to disable interrupt for event READY</description>
124873 <description>Read: Disabled</description>
124878 <description>Read: Enabled</description>
124886 <description>Disable</description>
124893 <description>Write '1' to disable interrupt for event FIELDDETECTED</description>
124900 <description>Read: Disabled</description>
124905 <description>Read: Enabled</description>
124913 <description>Disable</description>
124920 <description>Write '1' to disable interrupt for event FIELDLOST</description>
124927 <description>Read: Disabled</description>
124932 <description>Read: Enabled</description>
124940 <description>Disable</description>
124947 <description>Write '1' to disable interrupt for event TXFRAMESTART</description>
124954 <description>Read: Disabled</description>
124959 <description>Read: Enabled</description>
124967 <description>Disable</description>
124974 <description>Write '1' to disable interrupt for event TXFRAMEEND</description>
124981 <description>Read: Disabled</description>
124986 <description>Read: Enabled</description>
124994 <description>Disable</description>
125001 <description>Write '1' to disable interrupt for event RXFRAMESTART</description>
125008 <description>Read: Disabled</description>
125013 <description>Read: Enabled</description>
125021 <description>Disable</description>
125028 <description>Write '1' to disable interrupt for event RXFRAMEEND</description>
125035 <description>Read: Disabled</description>
125040 <description>Read: Enabled</description>
125048 <description>Disable</description>
125055 <description>Write '1' to disable interrupt for event ERROR</description>
125062 <description>Read: Disabled</description>
125067 <description>Read: Enabled</description>
125075 <description>Disable</description>
125082 <description>Write '1' to disable interrupt for event RXERROR</description>
125089 <description>Read: Disabled</description>
125094 <description>Read: Enabled</description>
125102 <description>Disable</description>
125109 <description>Write '1' to disable interrupt for event ENDRX</description>
125116 <description>Read: Disabled</description>
125121 <description>Read: Enabled</description>
125129 <description>Disable</description>
125136 <description>Write '1' to disable interrupt for event ENDTX</description>
125143 <description>Read: Disabled</description>
125148 <description>Read: Enabled</description>
125156 <description>Disable</description>
125163 <description>Write '1' to disable interrupt for event AUTOCOLRESSTARTED</description>
125170 <description>Read: Disabled</description>
125175 <description>Read: Enabled</description>
125183 <description>Disable</description>
125190 <description>Write '1' to disable interrupt for event COLLISION</description>
125197 <description>Read: Disabled</description>
125202 <description>Read: Enabled</description>
125210 <description>Disable</description>
125217 <description>Write '1' to disable interrupt for event SELECTED</description>
125224 <description>Read: Disabled</description>
125229 <description>Read: Enabled</description>
125237 <description>Disable</description>
125244 <description>Write '1' to disable interrupt for event STARTED</description>
125251 <description>Read: Disabled</description>
125256 <description>Read: Enabled</description>
125264 <description>Disable</description>
125273 <description>NFC Error Status register</description>
125282 …<description>No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX</descrip…
125290 <description>Unspecified</description>
125296 <description>Result of last incoming frame</description>
125305 <description>No valid end of frame (EoF) detected</description>
125311 <description>Valid CRC detected</description>
125316 <description>CRC received does not match local check</description>
125323 <description>Parity status of received frame</description>
125329 <description>Frame received with parity OK</description>
125334 <description>Frame received with parity error</description>
125341 <description>Overrun detected</description>
125347 <description>No overrun detected</description>
125352 <description>Overrun error</description>
125362 <description>Current operating state of NFC tag</description>
125370 <description>NfcTag state</description>
125376 <description>Disabled or sense</description>
125381 <description>RampUp</description>
125386 <description>Idle</description>
125391 <description>Receive</description>
125396 <description>FrameDelay</description>
125401 <description>Transmit</description>
125410 <description>Sleep state during automatic collision resolution</description>
125418 … <description>Reflects the sleep state during automatic collision resolution. Set to IDLE
125420 GOSLEEP task.</description>
125426 <description>State is IDLE.</description>
125431 <description>State is SLEEP_A.</description>
125440 <description>Indicates the presence or not of a valid field</description>
125448 …<description>Indicates if a valid field is present. Available only in the activated state.</descri…
125454 <description>No valid field detected</description>
125459 <description>Valid field detected</description>
125466 <description>Indicates if the low level has locked to the field</description>
125472 <description>Not locked to field</description>
125477 <description>Locked to field</description>
125486 <description>Minimum frame delay</description>
125494 <description>Minimum frame delay in number of 13.56 MHz clock cycles</description>
125502 <description>Maximum frame delay</description>
125510 <description>Maximum frame delay in number of 13.56 MHz clock cycles</description>
125518 <description>Configuration register for the Frame Delay Timer</description>
125526 <description>Configuration register for the Frame Delay Timer</description>
125532 …<description>Transmission is independent of frame timer and will start when the STARTTX task is tr…
125537 … <description>Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX</description>
125542 <description>Frame is transmitted exactly at FRAMEDELAYMAX</description>
125547 …<description>Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX</descripti…
125556 <description>Packet pointer for TXD and RXD data storage in Data RAM</description>
125564 …<description>Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-align…
125572 … <description>Size of the RAM buffer allocated to TXD and RXD data storage each</description>
125580 … <description>Size of the RAM buffer allocated to TXD and RXD data storage each</description>
125588 <description>Unspecified</description>
125594 <description>Configuration of outgoing frames</description>
125602 <description>Indicates if parity is added to the frame</description>
125608 <description>Parity is not added to TX frames</description>
125613 <description>Parity is added to TX frames</description>
125620 <description>Discarding unused bits at start or end of a frame</description>
125626 <description>Unused bits are discarded at end of frame (EoF)</description>
125631 <description>Unused bits are discarded at start of frame (SoF)</description>
125638 <description>Adding SoF or not in TX frames</description>
125644 <description>SoF symbol not added</description>
125649 <description>SoF symbol added</description>
125656 <description>CRC mode for outgoing frames</description>
125662 <description>CRC is not added to the frame</description>
125667 …<description>16 bit CRC added to the frame based on all the data read from RAM that is used in the…
125676 <description>Size of outgoing frame</description>
125684 …<description>Number of bits in the last or first byte read from RAM that shall be included in the …
125690 …<description>Number of complete bytes that shall be included in the frame, excluding CRC, parity, …
125699 <description>Unspecified</description>
125705 <description>Configuration of incoming frames</description>
125713 <description>Indicates if parity expected in RX frame</description>
125719 <description>Parity is not expected in RX frames</description>
125724 <description>Parity is expected in RX frames</description>
125731 <description>SoF expected or not in RX frames</description>
125737 <description>SoF symbol is not expected in RX frames</description>
125742 <description>SoF symbol is expected in RX frames</description>
125749 <description>CRC mode for incoming frames</description>
125755 <description>CRC is not expected in RX frames</description>
125760 … <description>Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated</description>
125769 <description>Size of last incoming frame</description>
125777 …<description>Number of bits in the last byte in the frame, if less than 8 (including CRC, but excl…
125783 …<description>Number of complete bytes received in the frame (including CRC, but excluding parity a…
125792 …<description>Enables the modulation output to a GPIO pin which can be connected to a second extern…
125800 <description>Configuration of modulation control.</description>
125806 <description>Invalid, defaults to same behaviour as for Internal</description>
125811 <description>Use internal modulator only</description>
125816 <description>Output digital modulation signal to a GPIO pin.</description>
125821 …<description>Use internal modulator and output digital modulation signal to a GPIO pin.</descripti…
125830 <description>Pin select for Modulation control</description>
125838 <description>Pin number</description>
125844 <description>Port number</description>
125850 <description>Connection</description>
125856 <description>Disconnect</description>
125861 <description>Connect</description>
125870 <description>Configure EasyDMA mode</description>
125878 <description>Enable low-power operation, or use low-latency</description>
125884 <description>Low-latency operation</description>
125889 <description>Low-power operation</description>
125894 <description>Full Low-power operation</description>
125903 <description>Unspecified</description>
125909 <description>Last NFCID1 part (4, 7 or 10 bytes ID)</description>
125917 <description>NFCID1 byte Z (very last byte sent)</description>
125923 <description>NFCID1 byte Y</description>
125929 <description>NFCID1 byte X</description>
125935 <description>NFCID1 byte W</description>
125943 <description>Second last NFCID1 part (7 or 10 bytes ID)</description>
125951 <description>NFCID1 byte V</description>
125957 <description>NFCID1 byte U</description>
125963 <description>NFCID1 byte T</description>
125971 <description>Third last NFCID1 part (10 bytes ID)</description>
125979 <description>NFCID1 byte S</description>
125985 <description>NFCID1 byte R</description>
125991 <description>NFCID1 byte Q</description>
126000 …<description>Controls the auto collision resolution function. This setting must be done before the…
126008 <description>Enables/disables auto collision resolution</description>
126014 <description>Auto collision resolution enabled</description>
126019 <description>Auto collision resolution disabled</description>
126028 <description>NFC-A SENS_RES auto-response settings</description>
126036 …description>Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum,…
126042 <description>SDD pattern 00000</description>
126047 <description>SDD pattern 00001</description>
126052 <description>SDD pattern 00010</description>
126057 <description>SDD pattern 00100</description>
126062 <description>SDD pattern 01000</description>
126067 <description>SDD pattern 10000</description>
126074 <description>Reserved for future use. Shall be 0.</description>
126080 …<description>NFCID1 size. This value is used by the auto collision resolution engine.</description>
126086 <description>NFCID1 size: single (4 bytes)</description>
126091 <description>NFCID1 size: double (7 bytes)</description>
126096 <description>NFCID1 size: triple (10 bytes)</description>
126103 …description>Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in t…
126109 <description>Reserved for future use. Shall be 0.</description>
126117 <description>NFC-A SEL_RES auto-response settings</description>
126125 <description>Reserved for future use. Shall be 0.</description>
126131 …description>Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protoco…
126137 <description>Reserved for future use. Shall be 0.</description>
126143 …<description>Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Pr…
126149 <description>Reserved for future use. Shall be 0.</description>
126157 <description>NFC pad configuration</description>
126165 <description>Enable NFC pads</description>
126171 <description>NFC pads are used as GPIO pins</description>
126176 <description>The NFC pads are configured as NFC antenna pins</description>
126187 <description>Distributed programmable peripheral interconnect controller 3</description>
126195 <description>Time division multiplexed audio interface 0</description>
126214 … <description>Starts continuous TDM transfer. Also starts MCK when this is enabled</description>
126222 … <description>Starts continuous TDM transfer. Also starts MCK when this is enabled</description>
126228 <description>Trigger task</description>
126237 <description>Stops TDM transfer after the completion of MAXCNT words. Triggering this
126238 task will cause the STOPPED event to be generated.</description>
126246 <description>Stops TDM transfer after the completion of MAXCNT words. Triggering this
126247 task will cause the STOPPED event to be generated.</description>
126253 <description>Trigger task</description>
126262 <description>Abort TDM transfer without completing MAXCNT words. Triggering this task
126263 will cause the ABORTED event to be generated.</description>
126271 <description>Abort TDM transfer without completing MAXCNT words. Triggering this task
126272 will cause the ABORTED event to be generated.</description>
126278 <description>Trigger task</description>
126287 <description>Subscribe configuration for task START</description>
126295 <description>DPPI channel that task START will subscribe to</description>
126306 <description>Disable subscription</description>
126311 <description>Enable subscription</description>
126320 <description>Subscribe configuration for task STOP</description>
126328 <description>DPPI channel that task STOP will subscribe to</description>
126339 <description>Disable subscription</description>
126344 <description>Enable subscription</description>
126353 <description>Subscribe configuration for task ABORT</description>
126361 <description>DPPI channel that task ABORT will subscribe to</description>
126372 <description>Disable subscription</description>
126377 <description>Enable subscription</description>
126386 <description>The RXD.PTR register has been copied to internal double-buffers.
126387 …, this event will be generated for every RXTXD.MAXCNT words received on the SDIN pin.</description>
126395 <description>The RXD.PTR register has been copied to internal double-buffers.
126396 …, this event will be generated for every RXTXD.MAXCNT words received on the SDIN pin.</description>
126402 <description>Event not generated</description>
126407 <description>Event generated</description>
126416 <description>Transfer stopped.</description>
126424 <description>Transfer stopped.</description>
126430 <description>Event not generated</description>
126435 <description>Event generated</description>
126444 <description>Transfer aborted.</description>
126452 <description>Transfer aborted.</description>
126458 <description>Event not generated</description>
126463 <description>Event generated</description>
126472 <description>The TDX.PTR register has been copied to internal double-buffers.
126473 … event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin.</description>
126481 <description>The TDX.PTR register has been copied to internal double-buffers.
126482 … event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin.</description>
126488 <description>Event not generated</description>
126493 <description>Event generated</description>
126502 …<description>MAXCNT block event, generated on the active edge of FSYNC of every MAXCNT block</desc…
126510 …<description>MAXCNT block event, generated on the active edge of FSYNC of every MAXCNT block</desc…
126516 <description>Event not generated</description>
126521 <description>Event generated</description>
126530 <description>Publish configuration for event RXPTRUPD</description>
126538 <description>DPPI channel that event RXPTRUPD will publish to</description>
126549 <description>Disable publishing</description>
126554 <description>Enable publishing</description>
126563 <description>Publish configuration for event STOPPED</description>
126571 <description>DPPI channel that event STOPPED will publish to</description>
126582 <description>Disable publishing</description>
126587 <description>Enable publishing</description>
126596 <description>Publish configuration for event ABORTED</description>
126604 <description>DPPI channel that event ABORTED will publish to</description>
126615 <description>Disable publishing</description>
126620 <description>Enable publishing</description>
126629 <description>Publish configuration for event TXPTRUPD</description>
126637 <description>DPPI channel that event TXPTRUPD will publish to</description>
126648 <description>Disable publishing</description>
126653 <description>Enable publishing</description>
126662 <description>Publish configuration for event MAXCNT</description>
126670 <description>DPPI channel that event MAXCNT will publish to</description>
126681 <description>Disable publishing</description>
126686 <description>Enable publishing</description>
126695 <description>Enable or disable interrupt</description>
126703 <description>Enable or disable interrupt for event RXPTRUPD</description>
126709 <description>Disable</description>
126714 <description>Enable</description>
126721 <description>Enable or disable interrupt for event STOPPED</description>
126727 <description>Disable</description>
126732 <description>Enable</description>
126739 <description>Enable or disable interrupt for event ABORTED</description>
126745 <description>Disable</description>
126750 <description>Enable</description>
126757 <description>Enable or disable interrupt for event TXPTRUPD</description>
126763 <description>Disable</description>
126768 <description>Enable</description>
126775 <description>Enable or disable interrupt for event MAXCNT</description>
126781 <description>Disable</description>
126786 <description>Enable</description>
126795 <description>Enable interrupt</description>
126803 <description>Write '1' to enable interrupt for event RXPTRUPD</description>
126810 <description>Read: Disabled</description>
126815 <description>Read: Enabled</description>
126823 <description>Enable</description>
126830 <description>Write '1' to enable interrupt for event STOPPED</description>
126837 <description>Read: Disabled</description>
126842 <description>Read: Enabled</description>
126850 <description>Enable</description>
126857 <description>Write '1' to enable interrupt for event ABORTED</description>
126864 <description>Read: Disabled</description>
126869 <description>Read: Enabled</description>
126877 <description>Enable</description>
126884 <description>Write '1' to enable interrupt for event TXPTRUPD</description>
126891 <description>Read: Disabled</description>
126896 <description>Read: Enabled</description>
126904 <description>Enable</description>
126911 <description>Write '1' to enable interrupt for event MAXCNT</description>
126918 <description>Read: Disabled</description>
126923 <description>Read: Enabled</description>
126931 <description>Enable</description>
126940 <description>Disable interrupt</description>
126948 <description>Write '1' to disable interrupt for event RXPTRUPD</description>
126955 <description>Read: Disabled</description>
126960 <description>Read: Enabled</description>
126968 <description>Disable</description>
126975 <description>Write '1' to disable interrupt for event STOPPED</description>
126982 <description>Read: Disabled</description>
126987 <description>Read: Enabled</description>
126995 <description>Disable</description>
127002 <description>Write '1' to disable interrupt for event ABORTED</description>
127009 <description>Read: Disabled</description>
127014 <description>Read: Enabled</description>
127022 <description>Disable</description>
127029 <description>Write '1' to disable interrupt for event TXPTRUPD</description>
127036 <description>Read: Disabled</description>
127041 <description>Read: Enabled</description>
127049 <description>Disable</description>
127056 <description>Write '1' to disable interrupt for event MAXCNT</description>
127063 <description>Read: Disabled</description>
127068 <description>Read: Enabled</description>
127076 <description>Disable</description>
127085 <description>Enable TDM</description>
127093 <description>Enable TDM</description>
127099 <description>Disable</description>
127104 <description>Enable</description>
127113 <description>Configuration registers.</description>
127119 <description>Mode configuration</description>
127127 <description>Mode configuration</description>
127133 …<description>Master mode. SCK and FSYNC generated from internal master clock (MCK) and output on P…
127138 …<description>Slave mode. SCK and FSYNC generated by external master and received on PSEL.SCK and P…
127147 <description>Reception (RX) and transmission (TX) enable.</description>
127155 <description>Enable reception or transmission.</description>
127161 …description>Enable both reception and transmission. Data will be written to the RXD.PTR address an…
127166 …<description>Enable reception, disable transmission. Data will be written to the RXD.PTR address.<…
127171 …<description>Enable transmission, disable reception. Data will be transmitted from the TXD.PTR add…
127180 <description>Unspecified</description>
127186 <description>Master clock generator enable.</description>
127194 <description>Master clock generator enable.</description>
127200 <description>Master clock generator disabled.</description>
127205 <description>Master clock generator enabled.</description>
127214 <description>MCK divider.</description>
127222 <description>MCK frequency configuration</description>
127228 <description>CK divided by 2</description>
127233 <description>CK divided by 3</description>
127238 <description>CK divided by 4</description>
127243 <description>CK divided by 5</description>
127248 <description>CK divided by 6</description>
127253 <description>CK divided by 8</description>
127258 <description>CK divided by 10</description>
127263 <description>CK divided by 11</description>
127268 <description>CK divided by 15</description>
127273 <description>CK divided by 16</description>
127278 <description>CK divided by 21</description>
127283 <description>CK divided by 23</description>
127288 <description>CK divided by 30</description>
127293 <description>CK divided by 31</description>
127298 <description>CK divided by 32</description>
127303 <description>CK divided by 42</description>
127308 <description>CK divided by 63</description>
127313 <description>CK divided by 125</description>
127322 <description>MCK clock source selection</description>
127330 <description>Clock source selection</description>
127336 <description>32MHz peripheral clock</description>
127341 <description>Audio PLL clock</description>
127348 …<description>Bypass clock generator. MCK will be equal to source input. If bypass is enabled the M…
127354 <description>Disable bypass</description>
127359 <description>Enable bypass</description>
127369 <description>Unspecified</description>
127375 <description>SCK divider.</description>
127383 <description>SCK frequency configuration</description>
127389 <description>CK divided by 2</description>
127394 <description>CK divided by 3</description>
127399 <description>CK divided by 4</description>
127404 <description>CK divided by 5</description>
127409 <description>CK divided by 6</description>
127414 <description>CK divided by 8</description>
127419 <description>CK divided by 10</description>
127424 <description>CK divided by 11</description>
127429 <description>CK divided by 15</description>
127434 <description>CK divided by 16</description>
127439 <description>CK divided by 21</description>
127444 <description>CK divided by 23</description>
127449 <description>CK divided by 30</description>
127454 <description>CK divided by 31</description>
127459 <description>CK divided by 32</description>
127464 <description>CK divided by 42</description>
127469 <description>CK divided by 63</description>
127474 <description>CK divided by 125</description>
127483 <description>SCK clock source selection</description>
127491 <description>Clock source selection</description>
127497 <description>32MHz peripheral clock</description>
127502 <description>Audio PLL clock</description>
127509 …<description>Bypass clock generator. SCK will be equal to source input. If bypass is enabled the S…
127515 <description>Disable bypass</description>
127520 <description>Enable bypass</description>
127529 <description>Set SCK Polarity.</description>
127537 <description>Set the polarity of the active SCK edge.</description>
127543 … <description>TX data is written to the SDOUT pin on the falling edge of SCK, ready to be
127544 received on the rising edge of SCK.</description>
127549 … <description>TX data is written to the SDOUT pin on the rising edge of SCK, ready to be
127550 received on the falling edge of SCK.</description>
127560 <description>Sample and word width configuration.</description>
127568 <description>Sample and word width</description>
127574 <description>8 bit sample in an 8-bit word.</description>
127579 <description>16 bit sample in a 16-bit word.</description>
127584 <description>24 bit sample in a 24-bit word.</description>
127589 <description>32 bit sample in a 32-bit word.</description>
127594 <description>8 bit sample in a 16-bit word.</description>
127599 <description>8 bit sample in a 32-bit word.</description>
127604 <description>16 bit sample in a 32-bit word.</description>
127609 <description>24 bit sample in a 32-bit word.</description>
127618 <description>Alignment of sample within the audio data word.</description>
127626 <description>Alignment of sample within the audio data word.</description>
127632 <description>Left-aligned.</description>
127637 <description>Right-aligned.</description>
127646 <description>Unspecified</description>
127652 <description>Select which channels are to be used.</description>
127665 <description>Disable Rx channel data.</description>
127670 <description>Enable Rx channel data.</description>
127682 <description>Disable Rx channel data.</description>
127687 <description>Enable Rx channel data.</description>
127699 <description>Disable Rx channel data.</description>
127704 <description>Enable Rx channel data.</description>
127716 <description>Disable Rx channel data.</description>
127721 <description>Enable Rx channel data.</description>
127733 <description>Disable Rx channel data.</description>
127738 <description>Enable Rx channel data.</description>
127750 <description>Disable Rx channel data.</description>
127755 <description>Enable Rx channel data.</description>
127767 <description>Disable Rx channel data.</description>
127772 <description>Enable Rx channel data.</description>
127784 <description>Disable Rx channel data.</description>
127789 <description>Enable Rx channel data.</description>
127801 <description>Disable Tx channel data.</description>
127806 <description>Enable Tx channel data.</description>
127818 <description>Disable Tx channel data.</description>
127823 <description>Enable Tx channel data.</description>
127835 <description>Disable Tx channel data.</description>
127840 <description>Enable Tx channel data.</description>
127852 <description>Disable Tx channel data.</description>
127857 <description>Enable Tx channel data.</description>
127869 <description>Disable Tx channel data.</description>
127874 <description>Enable Tx channel data.</description>
127886 <description>Disable Tx channel data.</description>
127891 <description>Enable Tx channel data.</description>
127903 <description>Disable Tx channel data.</description>
127908 <description>Enable Tx channel data.</description>
127920 <description>Disable Tx channel data.</description>
127925 <description>Enable Tx channel data.</description>
127934 <description>Select number of channels.</description>
127942 <description>Select number of channels.</description>
127948 <description>1-channel audio (mono).</description>
127953 <description>2-channel audio (stereo).</description>
127958 <description>3-channel audio.</description>
127963 <description>4-channel audio.</description>
127968 <description>5-channel audio.</description>
127973 <description>6-channel audio.</description>
127978 <description>7-channel audio.</description>
127983 <description>8-channel audio.</description>
127992 <description>Set channel delay.</description>
128000 …<description>Configure number of inactive SCK periods from edge of FSYNC until start of first data…
128006 <description>No delay. Used with I2S DSP/Aligned format.</description>
128011 … <description>One clock pulse delay. Used with Original I2S format.</description>
128016 <description>Two clock pulses delay.</description>
128026 <description>Unspecified</description>
128032 <description>Set FSYNC Polarity.</description>
128040 <description>Set the polarity of the active period of FSYNC.</description>
128046 <description>Frame starts at falling edge of FSYNC.</description>
128051 <description>Frame starts at rising edge of FSYNC.</description>
128060 <description>Set FSYNC Duration.</description>
128068 … <description>Set the duration of the active period of FSYNC in Master mode.</description>
128074 <description>FSYNC is active for the duration of one SCK pulse</description>
128079 <description>FSYNC is active for the duration of channel</description>
128089 … <description>Over-read sample: Extra sample bytes that are transmitted after TXD.MAXCNT bytes
128090 have been transmitted, in the case when RXD.MAXCNT is greater than TXD.MAXCNT.</description>
128098 … <description>Data transmitted after TXD.MAXCNT bytes have been transmitted in the case when
128099 RXD.MAXCNT is greater than TXD.MAXCNT.</description>
128108 <description>Unspecified</description>
128114 <description>Pin select for MCK signal</description>
128122 <description>Pin number</description>
128128 <description>Port number</description>
128134 <description>Connection</description>
128140 <description>Disconnect</description>
128145 <description>Connect</description>
128154 <description>Pin select for SCK signal</description>
128162 <description>Pin number</description>
128168 <description>Port number</description>
128174 <description>Connection</description>
128180 <description>Disconnect</description>
128185 <description>Connect</description>
128194 <description>Pin select for FSYNC signal</description>
128202 <description>Pin number</description>
128208 <description>Port number</description>
128214 <description>Connection</description>
128220 <description>Disconnect</description>
128225 <description>Connect</description>
128234 <description>Pin select for SDIN signal</description>
128242 <description>Pin number</description>
128248 <description>Port number</description>
128254 <description>Connection</description>
128260 <description>Disconnect</description>
128265 <description>Connect</description>
128274 <description>Pin select for SDOUT signal</description>
128282 <description>Pin number</description>
128288 <description>Port number</description>
128294 <description>Connection</description>
128300 <description>Disconnect</description>
128305 <description>Connect</description>
128315 <description>Unspecified</description>
128321 <description>RAM buffer start address</description>
128329 …<description>RAM buffer start address for this EasyDMA channel. This address is a word aligned Dat…
128337 <description>Maximum number of bytes in channel buffer</description>
128345 <description>Maximum number of bytes in channel buffer</description>
128353 …<description>Number of bytes transferred in the last transaction, updated after the END event.</de…
128361 …<description>Number of bytes transferred in the last transaction. In case of NACK error, includes …
128369 <description>Number of bytes transferred in the current transaction</description>
128377 …<description>Number of bytes transferred in the current transaction. Continuously updated.</descri…
128385 <description>Configure EasyDMA mode</description>
128393 <description>Enable low-power operation, or use low-latency</description>
128399 <description>Low-latency operation</description>
128404 <description>Low-power operation</description>
128413 <description>Terminate the transaction if a BUSERROR event is detected.</description>
128426 <description>Disable</description>
128431 <description>Enable</description>
128440 … <description>Address of transaction that generated the last BUSERROR event.</description>
128456 <description>Unspecified</description>
128462 <description>RAM buffer start address</description>
128470 …<description>RAM buffer start address for this EasyDMA channel. This address is a word aligned Dat…
128478 <description>Maximum number of bytes in channel buffer</description>
128486 <description>Maximum number of bytes in channel buffer</description>
128494 …<description>Number of bytes transferred in the last transaction, updated after the END event.</de…
128502 …<description>Number of bytes transferred in the last transaction. In case of NACK error, includes …
128510 <description>Number of bytes transferred in the current transaction</description>
128518 …<description>Number of bytes transferred in the current transaction. Continuously updated.</descri…
128526 <description>Configure EasyDMA mode</description>
128534 <description>Enable low-power operation, or use low-latency</description>
128540 <description>Low-latency operation</description>
128545 <description>Low-power operation</description>
128554 <description>Terminate the transaction if a BUSERROR event is detected.</description>
128567 <description>Disable</description>
128572 <description>Enable</description>
128581 … <description>Address of transaction that generated the last BUSERROR event.</description>
128599 <description>Pulse Density Modulation (Digital Microphone) Interface</description>
128617 <description>Starts continuous PDM transfer</description>
128625 <description>Starts continuous PDM transfer</description>
128631 <description>Trigger task</description>
128640 <description>Stops PDM transfer</description>
128648 <description>Stops PDM transfer</description>
128654 <description>Trigger task</description>
128663 <description>Subscribe configuration for task START</description>
128671 <description>DPPI channel that task START will subscribe to</description>
128682 <description>Disable subscription</description>
128687 <description>Enable subscription</description>
128696 <description>Subscribe configuration for task STOP</description>
128704 <description>DPPI channel that task STOP will subscribe to</description>
128715 <description>Disable subscription</description>
128720 <description>Enable subscription</description>
128729 <description>PDM transfer has started</description>
128737 <description>PDM transfer has started</description>
128743 <description>Event not generated</description>
128748 <description>Event generated</description>
128757 <description>PDM transfer has finished</description>
128765 <description>PDM transfer has finished</description>
128771 <description>Event not generated</description>
128776 <description>Event generated</description>
128785 …description>The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample aft…
128793 …description>The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample aft…
128799 <description>Event not generated</description>
128804 <description>Event generated</description>
128813 <description>Peripheral events.</description>
128819 … <description>This event is generated if an error occurs during the bus transfer.</description>
128827 … <description>This event is generated if an error occurs during the bus transfer.</description>
128833 <description>Event not generated</description>
128838 <description>Event generated</description>
128848 <description>Publish configuration for event STARTED</description>
128856 <description>DPPI channel that event STARTED will publish to</description>
128867 <description>Disable publishing</description>
128872 <description>Enable publishing</description>
128881 <description>Publish configuration for event STOPPED</description>
128889 <description>DPPI channel that event STOPPED will publish to</description>
128900 <description>Disable publishing</description>
128905 <description>Enable publishing</description>
128914 <description>Publish configuration for event END</description>
128922 <description>DPPI channel that event END will publish to</description>
128933 <description>Disable publishing</description>
128938 <description>Enable publishing</description>
128947 <description>Publish configuration for events</description>
128953 <description>Publish configuration for event DMA.BUSERROR</description>
128961 <description>DPPI channel that event DMA.BUSERROR will publish to</description>
128972 <description>Disable publishing</description>
128977 <description>Enable publishing</description>
128987 <description>Enable or disable interrupt</description>
128995 <description>Enable or disable interrupt for event STARTED</description>
129001 <description>Disable</description>
129006 <description>Enable</description>
129013 <description>Enable or disable interrupt for event STOPPED</description>
129019 <description>Disable</description>
129024 <description>Enable</description>
129031 <description>Enable or disable interrupt for event END</description>
129037 <description>Disable</description>
129042 <description>Enable</description>
129049 <description>Enable or disable interrupt for event DMABUSERROR</description>
129055 <description>Disable</description>
129060 <description>Enable</description>
129069 <description>Enable interrupt</description>
129077 <description>Write '1' to enable interrupt for event STARTED</description>
129084 <description>Read: Disabled</description>
129089 <description>Read: Enabled</description>
129097 <description>Enable</description>
129104 <description>Write '1' to enable interrupt for event STOPPED</description>
129111 <description>Read: Disabled</description>
129116 <description>Read: Enabled</description>
129124 <description>Enable</description>
129131 <description>Write '1' to enable interrupt for event END</description>
129138 <description>Read: Disabled</description>
129143 <description>Read: Enabled</description>
129151 <description>Enable</description>
129158 <description>Write '1' to enable interrupt for event DMABUSERROR</description>
129165 <description>Read: Disabled</description>
129170 <description>Read: Enabled</description>
129178 <description>Enable</description>
129187 <description>Disable interrupt</description>
129195 <description>Write '1' to disable interrupt for event STARTED</description>
129202 <description>Read: Disabled</description>
129207 <description>Read: Enabled</description>
129215 <description>Disable</description>
129222 <description>Write '1' to disable interrupt for event STOPPED</description>
129229 <description>Read: Disabled</description>
129234 <description>Read: Enabled</description>
129242 <description>Disable</description>
129249 <description>Write '1' to disable interrupt for event END</description>
129256 <description>Read: Disabled</description>
129261 <description>Read: Enabled</description>
129269 <description>Disable</description>
129276 <description>Write '1' to disable interrupt for event DMABUSERROR</description>
129283 <description>Read: Disabled</description>
129288 <description>Read: Enabled</description>
129296 <description>Disable</description>
129305 <description>Pending interrupts</description>
129313 <description>Read pending status of interrupt for event STARTED</description>
129320 <description>Read: Not pending</description>
129325 <description>Read: Pending</description>
129332 <description>Read pending status of interrupt for event STOPPED</description>
129339 <description>Read: Not pending</description>
129344 <description>Read: Pending</description>
129351 <description>Read pending status of interrupt for event END</description>
129358 <description>Read: Not pending</description>
129363 <description>Read: Pending</description>
129370 <description>Read pending status of interrupt for event DMABUSERROR</description>
129377 <description>Read: Not pending</description>
129382 <description>Read: Pending</description>
129391 <description>PDM module enable register</description>
129399 <description>Enable or disable PDM module</description>
129405 <description>Disable</description>
129410 <description>Enable</description>
129419 <description>PDM clock generator control</description>
129427 <description>PDM_CLK frequency configuration. Enumerations are deprecated, use
129429 register are ignored and shall be set to zero.</description>
129435 <description>PDM_CLK = 32 MHz / 32 = 1.000 MHz</description>
129440 … <description>PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64.</description>
129445 <description>PDM_CLK = 32 MHz / 30 = 1.067 MHz</description>
129450 <description>PDM_CLK = 32 MHz / 26 = 1.231 MHz</description>
129455 … <description>PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80.</description>
129460 <description>PDM_CLK = 32 MHz / 24 = 1.333 MHz</description>
129469 <description>Defines the routing of the connected PDM microphone signals</description>
129477 <description>Mono or stereo operation</description>
129483 …<description>Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=…
129488 …<description>Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; …
129495 <description>Defines on which PDM_CLK edge left (or mono) is sampled.</description>
129501 <description>Left (or mono) is sampled on falling edge of PDM_CLK</description>
129506 <description>Left (or mono) is sampled on rising edge of PDM_CLK</description>
129515 <description>Left output gain adjustment</description>
129523 …description>Left output gain adjustment, in 0.5 dB steps, around the default module gain (see elec…
129529 <description>-20 dB gain adjustment (minimum)</description>
129534 <description>0 dB gain adjustment</description>
129539 <description>+20 dB gain adjustment (maximum)</description>
129548 <description>Right output gain adjustment</description>
129556 …<description>Right output gain adjustment, in 0.5 dB steps, around the default module gain (see el…
129562 <description>-20 dB gain adjustment (minimum)</description>
129567 <description>0 dB gain adjustment</description>
129572 <description>+20 dB gain adjustment (maximum)</description>
129581 …<description>Selects the decimation ratio between PDM_CLK and output sample rate. Change PDMCLKCTR…
129589 … <description>Selects the decimation ratio between PDM_CLK and output sample rate</description>
129595 <description>Ratio of 32</description>
129600 <description>Ratio of 48</description>
129605 <description>Ratio of 50</description>
129610 <description>Ratio of 64</description>
129615 <description>Ratio of 80</description>
129620 <description>Ratio of 96</description>
129625 <description>Ratio of 100</description>
129630 <description>Ratio of 128</description>
129639 <description>Unspecified</description>
129645 <description>Pin number configuration for PDM CLK signal</description>
129653 <description>Pin number</description>
129659 <description>Port number</description>
129665 <description>Connection</description>
129671 <description>Disconnect</description>
129676 <description>Connect</description>
129685 <description>Pin number configuration for PDM DIN signal</description>
129693 <description>Pin number</description>
129699 <description>Port number</description>
129705 <description>Connection</description>
129711 <description>Disconnect</description>
129716 <description>Connect</description>
129726 <description>Master clock generator configuration</description>
129734 <description>Master clock source selection</description>
129740 <description>32 MHz peripheral clock</description>
129745 <description>Audio PLL clock</description>
129754 <description>Unspecified</description>
129760 <description>RAM address pointer to write samples to with EasyDMA</description>
129768 <description>Address to write PCM samples to over DMA</description>
129776 <description>Number of bytes to allocate memory for in EasyDMA mode</description>
129784 <description>Length of DMA RAM allocation in number of bytes</description>
129793 <description>Unspecified</description>
129799 <description>Terminate the transaction if a BUSERROR event is detected.</description>
129812 <description>Disable</description>
129817 <description>Enable</description>
129826 … <description>Address of transaction that generated the last BUSERROR event.</description>
129844 <description>Quadrature Decoder 0</description>
129863 <description>Task starting the quadrature decoder</description>
129871 <description>Task starting the quadrature decoder</description>
129877 <description>Trigger task</description>
129886 <description>Task stopping the quadrature decoder</description>
129894 <description>Task stopping the quadrature decoder</description>
129900 <description>Trigger task</description>
129909 <description>Read and clear ACC and ACCDBL</description>
129917 <description>Read and clear ACC and ACCDBL</description>
129923 <description>Trigger task</description>
129932 <description>Read and clear ACC</description>
129940 <description>Read and clear ACC</description>
129946 <description>Trigger task</description>
129955 <description>Read and clear ACCDBL</description>
129963 <description>Read and clear ACCDBL</description>
129969 <description>Trigger task</description>
129978 <description>Subscribe configuration for task START</description>
129986 <description>DPPI channel that task START will subscribe to</description>
129997 <description>Disable subscription</description>
130002 <description>Enable subscription</description>
130011 <description>Subscribe configuration for task STOP</description>
130019 <description>DPPI channel that task STOP will subscribe to</description>
130030 <description>Disable subscription</description>
130035 <description>Enable subscription</description>
130044 <description>Subscribe configuration for task READCLRACC</description>
130052 <description>DPPI channel that task READCLRACC will subscribe to</description>
130063 <description>Disable subscription</description>
130068 <description>Enable subscription</description>
130077 <description>Subscribe configuration for task RDCLRACC</description>
130085 <description>DPPI channel that task RDCLRACC will subscribe to</description>
130096 <description>Disable subscription</description>
130101 <description>Enable subscription</description>
130110 <description>Subscribe configuration for task RDCLRDBL</description>
130118 <description>DPPI channel that task RDCLRDBL will subscribe to</description>
130129 <description>Disable subscription</description>
130134 <description>Enable subscription</description>
130143 …<description>Event being generated for every new sample value written to the SAMPLE register</desc…
130151 …<description>Event being generated for every new sample value written to the SAMPLE register</desc…
130157 <description>Event not generated</description>
130162 <description>Event generated</description>
130171 <description>Non-null report ready</description>
130179 <description>Non-null report ready</description>
130185 <description>Event not generated</description>
130190 <description>Event generated</description>
130199 <description>ACC or ACCDBL register overflow</description>
130207 <description>ACC or ACCDBL register overflow</description>
130213 <description>Event not generated</description>
130218 <description>Event generated</description>
130227 <description>Double displacement(s) detected</description>
130235 <description>Double displacement(s) detected</description>
130241 <description>Event not generated</description>
130246 <description>Event generated</description>
130255 <description>QDEC has been stopped</description>
130263 <description>QDEC has been stopped</description>
130269 <description>Event not generated</description>
130274 <description>Event generated</description>
130283 <description>Publish configuration for event SAMPLERDY</description>
130291 <description>DPPI channel that event SAMPLERDY will publish to</description>
130302 <description>Disable publishing</description>
130307 <description>Enable publishing</description>
130316 <description>Publish configuration for event REPORTRDY</description>
130324 <description>DPPI channel that event REPORTRDY will publish to</description>
130335 <description>Disable publishing</description>
130340 <description>Enable publishing</description>
130349 <description>Publish configuration for event ACCOF</description>
130357 <description>DPPI channel that event ACCOF will publish to</description>
130368 <description>Disable publishing</description>
130373 <description>Enable publishing</description>
130382 <description>Publish configuration for event DBLRDY</description>
130390 <description>DPPI channel that event DBLRDY will publish to</description>
130401 <description>Disable publishing</description>
130406 <description>Enable publishing</description>
130415 <description>Publish configuration for event STOPPED</description>
130423 <description>DPPI channel that event STOPPED will publish to</description>
130434 <description>Disable publishing</description>
130439 <description>Enable publishing</description>
130448 <description>Shortcuts between local events and tasks</description>
130456 <description>Shortcut between event REPORTRDY and task READCLRACC</description>
130462 <description>Disable shortcut</description>
130467 <description>Enable shortcut</description>
130474 <description>Shortcut between event SAMPLERDY and task STOP</description>
130480 <description>Disable shortcut</description>
130485 <description>Enable shortcut</description>
130492 <description>Shortcut between event REPORTRDY and task RDCLRACC</description>
130498 <description>Disable shortcut</description>
130503 <description>Enable shortcut</description>
130510 <description>Shortcut between event REPORTRDY and task STOP</description>
130516 <description>Disable shortcut</description>
130521 <description>Enable shortcut</description>
130528 <description>Shortcut between event DBLRDY and task RDCLRDBL</description>
130534 <description>Disable shortcut</description>
130539 <description>Enable shortcut</description>
130546 <description>Shortcut between event DBLRDY and task STOP</description>
130552 <description>Disable shortcut</description>
130557 <description>Enable shortcut</description>
130564 <description>Shortcut between event SAMPLERDY and task READCLRACC</description>
130570 <description>Disable shortcut</description>
130575 <description>Enable shortcut</description>
130584 <description>Enable interrupt</description>
130592 <description>Write '1' to enable interrupt for event SAMPLERDY</description>
130599 <description>Read: Disabled</description>
130604 <description>Read: Enabled</description>
130612 <description>Enable</description>
130619 <description>Write '1' to enable interrupt for event REPORTRDY</description>
130626 <description>Read: Disabled</description>
130631 <description>Read: Enabled</description>
130639 <description>Enable</description>
130646 <description>Write '1' to enable interrupt for event ACCOF</description>
130653 <description>Read: Disabled</description>
130658 <description>Read: Enabled</description>
130666 <description>Enable</description>
130673 <description>Write '1' to enable interrupt for event DBLRDY</description>
130680 <description>Read: Disabled</description>
130685 <description>Read: Enabled</description>
130693 <description>Enable</description>
130700 <description>Write '1' to enable interrupt for event STOPPED</description>
130707 <description>Read: Disabled</description>
130712 <description>Read: Enabled</description>
130720 <description>Enable</description>
130729 <description>Disable interrupt</description>
130737 <description>Write '1' to disable interrupt for event SAMPLERDY</description>
130744 <description>Read: Disabled</description>
130749 <description>Read: Enabled</description>
130757 <description>Disable</description>
130764 <description>Write '1' to disable interrupt for event REPORTRDY</description>
130771 <description>Read: Disabled</description>
130776 <description>Read: Enabled</description>
130784 <description>Disable</description>
130791 <description>Write '1' to disable interrupt for event ACCOF</description>
130798 <description>Read: Disabled</description>
130803 <description>Read: Enabled</description>
130811 <description>Disable</description>
130818 <description>Write '1' to disable interrupt for event DBLRDY</description>
130825 <description>Read: Disabled</description>
130830 <description>Read: Enabled</description>
130838 <description>Disable</description>
130845 <description>Write '1' to disable interrupt for event STOPPED</description>
130852 <description>Read: Disabled</description>
130857 <description>Read: Enabled</description>
130865 <description>Disable</description>
130874 <description>Enable the quadrature decoder</description>
130882 <description>Enable or disable the quadrature decoder</description>
130888 <description>Disable</description>
130893 <description>Enable</description>
130902 <description>LED output pin polarity</description>
130910 <description>LED output pin polarity</description>
130916 <description>Led active on output pin low</description>
130921 <description>Led active on output pin high</description>
130930 <description>Sample period</description>
130938 … <description>Sample period. The SAMPLE register will be updated for every new sample</description>
130944 <description>128 us</description>
130949 <description>256 us</description>
130954 <description>512 us</description>
130959 <description>1024 us</description>
130964 <description>2048 us</description>
130969 <description>4096 us</description>
130974 <description>8192 us</description>
130979 <description>16384 us</description>
130984 <description>32768 us</description>
130989 <description>65536 us</description>
130994 <description>131072 us</description>
131003 <description>Motion sample value</description>
131012 <description>Last motion sample</description>
131020 …<description>Number of samples to be taken before REPORTRDY and DBLRDY events can be generated</de…
131028 …<description>Specifies the number of samples to be accumulated in the ACC register before the REPO…
131034 <description>10 samples/report</description>
131039 <description>40 samples/report</description>
131044 <description>80 samples/report</description>
131049 <description>120 samples/report</description>
131054 <description>160 samples/report</description>
131059 <description>200 samples/report</description>
131064 <description>240 samples/report</description>
131069 <description>280 samples/report</description>
131074 <description>1 sample/report</description>
131083 <description>Register accumulating the valid transitions</description>
131092 …<description>Register accumulating all valid samples (not double transition) read from the SAMPLE …
131100 …<description>Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task</description>
131109 <description>Snapshot of the ACC register.</description>
131117 <description>Unspecified</description>
131123 <description>Pin select for LED signal</description>
131131 <description>Pin number</description>
131137 <description>Port number</description>
131143 <description>Connection</description>
131149 <description>Disconnect</description>
131154 <description>Connect</description>
131163 <description>Pin select for A signal</description>
131171 <description>Pin number</description>
131177 <description>Port number</description>
131183 <description>Connection</description>
131189 <description>Disconnect</description>
131194 <description>Connect</description>
131203 <description>Pin select for B signal</description>
131211 <description>Pin number</description>
131217 <description>Port number</description>
131223 <description>Connection</description>
131229 <description>Disconnect</description>
131234 <description>Connect</description>
131244 <description>Enable input debounce filters</description>
131252 <description>Enable input debounce filters</description>
131258 <description>Debounce input filters disabled</description>
131263 <description>Debounce input filters enabled</description>
131272 <description>Time period the LED is switched ON prior to sampling</description>
131280 <description>Period in us the LED is switched on prior to sampling</description>
131288 <description>Register accumulating the number of detected double transitions</description>
131296 …<description>Register accumulating the number of detected double or illegal transitions. ( SAMPLE …
131304 … <description>Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task</description>
131312 …<description>Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDB…
131322 <description>Quadrature Decoder 1</description>
131333 <description>Time division multiplexed audio interface 1</description>
131344 <description>Distributed programmable peripheral interconnect controller 4</description>
131352 <description>Timer/Counter 2</description>
131363 <description>Timer/Counter 3</description>
131374 <description>Pulse width modulation unit 1</description>
131385 <description>Serial Peripheral Interface Master with EasyDMA 2</description>
131396 <description>SPI Slave 1</description>
131408 <description>I2C compatible Two-Wire Master Interface with EasyDMA 0</description>
131428 …<description>Stop TWI transaction. Must be issued while the TWI master is not suspended.</descript…
131436 …<description>Stop TWI transaction. Must be issued while the TWI master is not suspended.</descript…
131442 <description>Trigger task</description>
131451 <description>Suspend TWI transaction</description>
131459 <description>Suspend TWI transaction</description>
131465 <description>Trigger task</description>
131474 <description>Resume TWI transaction</description>
131482 <description>Resume TWI transaction</description>
131488 <description>Trigger task</description>
131497 <description>Peripheral tasks.</description>
131503 <description>Peripheral tasks.</description>
131509 …<description>Starts operation using easyDMA to load the values. See peripheral description for ope…
131517 …<description>Starts operation using easyDMA to load the values. See peripheral description for ope…
131523 <description>Trigger task</description>
131532 … <description>Stops operation using easyDMA. This does not trigger an END event.</description>
131540 … <description>Stops operation using easyDMA. This does not trigger an END event.</description>
131546 <description>Trigger task</description>
131557 …<description>Description collection: Enables the MATCH[n] event by setting the ENABLE[n] bit in th…
131565 …<description>Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register.</desc…
131571 <description>Trigger task</description>
131582 …<description>Description collection: Disables the MATCH[n] event by clearing the ENABLE[n] bit in …
131590 …<description>Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register.</de…
131596 <description>Trigger task</description>
131606 <description>Peripheral tasks.</description>
131612 …<description>Starts operation using easyDMA to load the values. See peripheral description for ope…
131620 …<description>Starts operation using easyDMA to load the values. See peripheral description for ope…
131626 <description>Trigger task</description>
131635 … <description>Stops operation using easyDMA. This does not trigger an END event.</description>
131643 … <description>Stops operation using easyDMA. This does not trigger an END event.</description>
131649 <description>Trigger task</description>
131660 <description>Subscribe configuration for task STOP</description>
131668 <description>DPPI channel that task STOP will subscribe to</description>
131679 <description>Disable subscription</description>
131684 <description>Enable subscription</description>
131693 <description>Subscribe configuration for task SUSPEND</description>
131701 <description>DPPI channel that task SUSPEND will subscribe to</description>
131712 <description>Disable subscription</description>
131717 <description>Enable subscription</description>
131726 <description>Subscribe configuration for task RESUME</description>
131734 <description>DPPI channel that task RESUME will subscribe to</description>
131745 <description>Disable subscription</description>
131750 <description>Enable subscription</description>
131759 <description>Subscribe configuration for tasks</description>
131765 <description>Subscribe configuration for tasks</description>
131771 <description>Subscribe configuration for task START</description>
131779 <description>DPPI channel that task START will subscribe to</description>
131790 <description>Disable subscription</description>
131795 <description>Enable subscription</description>
131804 <description>Subscribe configuration for task STOP</description>
131812 <description>DPPI channel that task STOP will subscribe to</description>
131823 <description>Disable subscription</description>
131828 <description>Enable subscription</description>
131839 … <description>Description collection: Subscribe configuration for task ENABLEMATCH[n]</description>
131847 <description>DPPI channel that task ENABLEMATCH[n] will subscribe to</description>
131858 <description>Disable subscription</description>
131863 <description>Enable subscription</description>
131874 …<description>Description collection: Subscribe configuration for task DISABLEMATCH[n]</description>
131882 … <description>DPPI channel that task DISABLEMATCH[n] will subscribe to</description>
131893 <description>Disable subscription</description>
131898 <description>Enable subscription</description>
131908 <description>Subscribe configuration for tasks</description>
131914 <description>Subscribe configuration for task START</description>
131922 <description>DPPI channel that task START will subscribe to</description>
131933 <description>Disable subscription</description>
131938 <description>Enable subscription</description>
131947 <description>Subscribe configuration for task STOP</description>
131955 <description>DPPI channel that task STOP will subscribe to</description>
131966 <description>Disable subscription</description>
131971 <description>Enable subscription</description>
131982 <description>TWI stopped</description>
131990 <description>TWI stopped</description>
131996 <description>Event not generated</description>
132001 <description>Event generated</description>
132010 <description>TWI error</description>
132018 <description>TWI error</description>
132024 <description>Event not generated</description>
132029 <description>Event generated</description>
132038 <description>SUSPEND task has been issued, TWI traffic is now suspended.</description>
132046 <description>SUSPEND task has been issued, TWI traffic is now suspended.</description>
132052 <description>Event not generated</description>
132057 <description>Event generated</description>
132066 <description>Byte boundary, starting to receive the last byte</description>
132074 <description>Byte boundary, starting to receive the last byte</description>
132080 <description>Event not generated</description>
132085 <description>Event generated</description>
132094 <description>Byte boundary, starting to transmit the last byte</description>
132102 <description>Byte boundary, starting to transmit the last byte</description>
132108 <description>Event not generated</description>
132113 <description>Event generated</description>
132122 <description>Peripheral events.</description>
132128 <description>Peripheral events.</description>
132134 <description>Generated after all MAXCNT bytes have been transferred</description>
132142 <description>Generated after all MAXCNT bytes have been transferred</description>
132148 <description>Event not generated</description>
132153 <description>Event generated</description>
132162 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
132170 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
132176 <description>Event not generated</description>
132181 <description>Event generated</description>
132190 <description>An error occured during the bus transfer.</description>
132198 <description>An error occured during the bus transfer.</description>
132204 <description>Event not generated</description>
132209 <description>Event generated</description>
132220 … <description>Description collection: Pattern match is detected on the DMA data bus.</description>
132228 <description>Pattern match is detected on the DMA data bus.</description>
132234 <description>Event not generated</description>
132239 <description>Event generated</description>
132249 <description>Peripheral events.</description>
132255 <description>Generated after all MAXCNT bytes have been transferred</description>
132263 <description>Generated after all MAXCNT bytes have been transferred</description>
132269 <description>Event not generated</description>
132274 <description>Event generated</description>
132283 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
132291 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
132297 <description>Event not generated</description>
132302 <description>Event generated</description>
132311 <description>An error occured during the bus transfer.</description>
132319 <description>An error occured during the bus transfer.</description>
132325 <description>Event not generated</description>
132330 <description>Event generated</description>
132341 <description>Publish configuration for event STOPPED</description>
132349 <description>DPPI channel that event STOPPED will publish to</description>
132360 <description>Disable publishing</description>
132365 <description>Enable publishing</description>
132374 <description>Publish configuration for event ERROR</description>
132382 <description>DPPI channel that event ERROR will publish to</description>
132393 <description>Disable publishing</description>
132398 <description>Enable publishing</description>
132407 <description>Publish configuration for event SUSPENDED</description>
132415 <description>DPPI channel that event SUSPENDED will publish to</description>
132426 <description>Disable publishing</description>
132431 <description>Enable publishing</description>
132440 <description>Publish configuration for event LASTRX</description>
132448 <description>DPPI channel that event LASTRX will publish to</description>
132459 <description>Disable publishing</description>
132464 <description>Enable publishing</description>
132473 <description>Publish configuration for event LASTTX</description>
132481 <description>DPPI channel that event LASTTX will publish to</description>
132492 <description>Disable publishing</description>
132497 <description>Enable publishing</description>
132506 <description>Publish configuration for events</description>
132512 <description>Publish configuration for events</description>
132518 <description>Publish configuration for event END</description>
132526 <description>DPPI channel that event END will publish to</description>
132537 <description>Disable publishing</description>
132542 <description>Enable publishing</description>
132551 <description>Publish configuration for event READY</description>
132559 <description>DPPI channel that event READY will publish to</description>
132570 <description>Disable publishing</description>
132575 <description>Enable publishing</description>
132584 <description>Publish configuration for event BUSERROR</description>
132592 <description>DPPI channel that event BUSERROR will publish to</description>
132603 <description>Disable publishing</description>
132608 <description>Enable publishing</description>
132619 … <description>Description collection: Publish configuration for event MATCH[n]</description>
132627 <description>DPPI channel that event MATCH[n] will publish to</description>
132638 <description>Disable publishing</description>
132643 <description>Enable publishing</description>
132653 <description>Publish configuration for events</description>
132659 <description>Publish configuration for event END</description>
132667 <description>DPPI channel that event END will publish to</description>
132678 <description>Disable publishing</description>
132683 <description>Enable publishing</description>
132692 <description>Publish configuration for event READY</description>
132700 <description>DPPI channel that event READY will publish to</description>
132711 <description>Disable publishing</description>
132716 <description>Enable publishing</description>
132725 <description>Publish configuration for event BUSERROR</description>
132733 <description>DPPI channel that event BUSERROR will publish to</description>
132744 <description>Disable publishing</description>
132749 <description>Enable publishing</description>
132760 <description>Shortcuts between local events and tasks</description>
132768 <description>Shortcut between event LASTTX and task DMA.RX.START</description>
132774 <description>Disable shortcut</description>
132779 <description>Enable shortcut</description>
132786 <description>Shortcut between event LASTTX and task SUSPEND</description>
132792 <description>Disable shortcut</description>
132797 <description>Enable shortcut</description>
132804 <description>Shortcut between event LASTTX and task STOP</description>
132810 <description>Disable shortcut</description>
132815 <description>Enable shortcut</description>
132822 <description>Shortcut between event LASTRX and task DMA.TX.START</description>
132828 <description>Disable shortcut</description>
132833 <description>Enable shortcut</description>
132840 <description>Shortcut between event LASTRX and task STOP</description>
132846 <description>Disable shortcut</description>
132851 <description>Enable shortcut</description>
132858 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows daisy-ch…
132864 <description>Disable shortcut</description>
132869 <description>Enable shortcut</description>
132876 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows daisy-ch…
132882 <description>Disable shortcut</description>
132887 <description>Enable shortcut</description>
132894 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows daisy-ch…
132900 <description>Disable shortcut</description>
132905 <description>Enable shortcut</description>
132912 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows daisy-ch…
132918 <description>Disable shortcut</description>
132923 <description>Enable shortcut</description>
132930 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
132936 <description>Disable shortcut</description>
132941 <description>Enable shortcut</description>
132948 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
132954 <description>Disable shortcut</description>
132959 <description>Enable shortcut</description>
132966 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
132972 <description>Disable shortcut</description>
132977 <description>Enable shortcut</description>
132984 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
132990 <description>Disable shortcut</description>
132995 <description>Enable shortcut</description>
133004 <description>Enable or disable interrupt</description>
133012 <description>Enable or disable interrupt for event STOPPED</description>
133018 <description>Disable</description>
133023 <description>Enable</description>
133030 <description>Enable or disable interrupt for event ERROR</description>
133036 <description>Disable</description>
133041 <description>Enable</description>
133048 <description>Enable or disable interrupt for event SUSPENDED</description>
133054 <description>Disable</description>
133059 <description>Enable</description>
133066 <description>Enable or disable interrupt for event LASTRX</description>
133072 <description>Disable</description>
133077 <description>Enable</description>
133084 <description>Enable or disable interrupt for event LASTTX</description>
133090 <description>Disable</description>
133095 <description>Enable</description>
133102 <description>Enable or disable interrupt for event DMARXEND</description>
133108 <description>Disable</description>
133113 <description>Enable</description>
133120 <description>Enable or disable interrupt for event DMARXREADY</description>
133126 <description>Disable</description>
133131 <description>Enable</description>
133138 <description>Enable or disable interrupt for event DMARXBUSERROR</description>
133144 <description>Disable</description>
133149 <description>Enable</description>
133156 <description>Enable or disable interrupt for event DMARXMATCH[0]</description>
133162 <description>Disable</description>
133167 <description>Enable</description>
133174 <description>Enable or disable interrupt for event DMARXMATCH[1]</description>
133180 <description>Disable</description>
133185 <description>Enable</description>
133192 <description>Enable or disable interrupt for event DMARXMATCH[2]</description>
133198 <description>Disable</description>
133203 <description>Enable</description>
133210 <description>Enable or disable interrupt for event DMARXMATCH[3]</description>
133216 <description>Disable</description>
133221 <description>Enable</description>
133228 <description>Enable or disable interrupt for event DMATXEND</description>
133234 <description>Disable</description>
133239 <description>Enable</description>
133246 <description>Enable or disable interrupt for event DMATXREADY</description>
133252 <description>Disable</description>
133257 <description>Enable</description>
133264 <description>Enable or disable interrupt for event DMATXBUSERROR</description>
133270 <description>Disable</description>
133275 <description>Enable</description>
133284 <description>Enable interrupt</description>
133292 <description>Write '1' to enable interrupt for event STOPPED</description>
133299 <description>Read: Disabled</description>
133304 <description>Read: Enabled</description>
133312 <description>Enable</description>
133319 <description>Write '1' to enable interrupt for event ERROR</description>
133326 <description>Read: Disabled</description>
133331 <description>Read: Enabled</description>
133339 <description>Enable</description>
133346 <description>Write '1' to enable interrupt for event SUSPENDED</description>
133353 <description>Read: Disabled</description>
133358 <description>Read: Enabled</description>
133366 <description>Enable</description>
133373 <description>Write '1' to enable interrupt for event LASTRX</description>
133380 <description>Read: Disabled</description>
133385 <description>Read: Enabled</description>
133393 <description>Enable</description>
133400 <description>Write '1' to enable interrupt for event LASTTX</description>
133407 <description>Read: Disabled</description>
133412 <description>Read: Enabled</description>
133420 <description>Enable</description>
133427 <description>Write '1' to enable interrupt for event DMARXEND</description>
133434 <description>Read: Disabled</description>
133439 <description>Read: Enabled</description>
133447 <description>Enable</description>
133454 <description>Write '1' to enable interrupt for event DMARXREADY</description>
133461 <description>Read: Disabled</description>
133466 <description>Read: Enabled</description>
133474 <description>Enable</description>
133481 <description>Write '1' to enable interrupt for event DMARXBUSERROR</description>
133488 <description>Read: Disabled</description>
133493 <description>Read: Enabled</description>
133501 <description>Enable</description>
133508 <description>Write '1' to enable interrupt for event DMARXMATCH[0]</description>
133515 <description>Read: Disabled</description>
133520 <description>Read: Enabled</description>
133528 <description>Enable</description>
133535 <description>Write '1' to enable interrupt for event DMARXMATCH[1]</description>
133542 <description>Read: Disabled</description>
133547 <description>Read: Enabled</description>
133555 <description>Enable</description>
133562 <description>Write '1' to enable interrupt for event DMARXMATCH[2]</description>
133569 <description>Read: Disabled</description>
133574 <description>Read: Enabled</description>
133582 <description>Enable</description>
133589 <description>Write '1' to enable interrupt for event DMARXMATCH[3]</description>
133596 <description>Read: Disabled</description>
133601 <description>Read: Enabled</description>
133609 <description>Enable</description>
133616 <description>Write '1' to enable interrupt for event DMATXEND</description>
133623 <description>Read: Disabled</description>
133628 <description>Read: Enabled</description>
133636 <description>Enable</description>
133643 <description>Write '1' to enable interrupt for event DMATXREADY</description>
133650 <description>Read: Disabled</description>
133655 <description>Read: Enabled</description>
133663 <description>Enable</description>
133670 <description>Write '1' to enable interrupt for event DMATXBUSERROR</description>
133677 <description>Read: Disabled</description>
133682 <description>Read: Enabled</description>
133690 <description>Enable</description>
133699 <description>Disable interrupt</description>
133707 <description>Write '1' to disable interrupt for event STOPPED</description>
133714 <description>Read: Disabled</description>
133719 <description>Read: Enabled</description>
133727 <description>Disable</description>
133734 <description>Write '1' to disable interrupt for event ERROR</description>
133741 <description>Read: Disabled</description>
133746 <description>Read: Enabled</description>
133754 <description>Disable</description>
133761 <description>Write '1' to disable interrupt for event SUSPENDED</description>
133768 <description>Read: Disabled</description>
133773 <description>Read: Enabled</description>
133781 <description>Disable</description>
133788 <description>Write '1' to disable interrupt for event LASTRX</description>
133795 <description>Read: Disabled</description>
133800 <description>Read: Enabled</description>
133808 <description>Disable</description>
133815 <description>Write '1' to disable interrupt for event LASTTX</description>
133822 <description>Read: Disabled</description>
133827 <description>Read: Enabled</description>
133835 <description>Disable</description>
133842 <description>Write '1' to disable interrupt for event DMARXEND</description>
133849 <description>Read: Disabled</description>
133854 <description>Read: Enabled</description>
133862 <description>Disable</description>
133869 <description>Write '1' to disable interrupt for event DMARXREADY</description>
133876 <description>Read: Disabled</description>
133881 <description>Read: Enabled</description>
133889 <description>Disable</description>
133896 <description>Write '1' to disable interrupt for event DMARXBUSERROR</description>
133903 <description>Read: Disabled</description>
133908 <description>Read: Enabled</description>
133916 <description>Disable</description>
133923 <description>Write '1' to disable interrupt for event DMARXMATCH[0]</description>
133930 <description>Read: Disabled</description>
133935 <description>Read: Enabled</description>
133943 <description>Disable</description>
133950 <description>Write '1' to disable interrupt for event DMARXMATCH[1]</description>
133957 <description>Read: Disabled</description>
133962 <description>Read: Enabled</description>
133970 <description>Disable</description>
133977 <description>Write '1' to disable interrupt for event DMARXMATCH[2]</description>
133984 <description>Read: Disabled</description>
133989 <description>Read: Enabled</description>
133997 <description>Disable</description>
134004 <description>Write '1' to disable interrupt for event DMARXMATCH[3]</description>
134011 <description>Read: Disabled</description>
134016 <description>Read: Enabled</description>
134024 <description>Disable</description>
134031 <description>Write '1' to disable interrupt for event DMATXEND</description>
134038 <description>Read: Disabled</description>
134043 <description>Read: Enabled</description>
134051 <description>Disable</description>
134058 <description>Write '1' to disable interrupt for event DMATXREADY</description>
134065 <description>Read: Disabled</description>
134070 <description>Read: Enabled</description>
134078 <description>Disable</description>
134085 <description>Write '1' to disable interrupt for event DMATXBUSERROR</description>
134092 <description>Read: Disabled</description>
134097 <description>Read: Enabled</description>
134105 <description>Disable</description>
134114 <description>Error source</description>
134123 <description>Overrun error</description>
134129 <description>Error did not occur</description>
134134 <description>Error occurred</description>
134141 … <description>NACK received after sending the address (write '1' to clear)</description>
134147 <description>Error did not occur</description>
134152 <description>Error occurred</description>
134159 … <description>NACK received after sending a data byte (write '1' to clear)</description>
134165 <description>Error did not occur</description>
134170 <description>Error occurred</description>
134179 <description>Enable TWIM</description>
134187 <description>Enable or disable TWIM</description>
134193 <description>Disable TWIM</description>
134198 <description>Enable TWIM</description>
134207 <description>TWI frequency. Accuracy depends on the HFCLK source selected.</description>
134215 <description>TWI master clock frequency</description>
134221 <description>100 kbps</description>
134226 <description>250 kbps</description>
134231 <description>400 kbps</description>
134236 <description>1000 kbps</description>
134245 <description>Address used in the TWI transfer</description>
134253 <description>Address used in the TWI transfer</description>
134261 <description>Unspecified</description>
134267 <description>Pin select for SCL signal</description>
134275 <description>Pin number</description>
134281 <description>Port number</description>
134287 <description>Connection</description>
134293 <description>Disconnect</description>
134298 <description>Connect</description>
134307 <description>Pin select for SDA signal</description>
134315 <description>Pin number</description>
134321 <description>Port number</description>
134327 <description>Connection</description>
134333 <description>Disconnect</description>
134338 <description>Connect</description>
134348 <description>Unspecified</description>
134354 <description>Unspecified</description>
134360 <description>RAM buffer start address</description>
134368 …<description>RAM buffer start address for this EasyDMA channel. This address is a word aligned Dat…
134376 <description>Maximum number of bytes in channel buffer</description>
134384 <description>Maximum number of bytes in channel buffer</description>
134392 …<description>Number of bytes transferred in the last transaction, updated after the END event. Als…
134400 …<description>Number of bytes transferred in the last transaction. In case of NACK error, includes …
134408 <description>Number of bytes transferred in the current transaction</description>
134416 …<description>Number of bytes transferred in the current transaction. Continuously updated.</descri…
134424 <description>EasyDMA list type</description>
134432 <description>List type</description>
134438 <description>Disable EasyDMA list</description>
134443 <description>Use array list</description>
134452 <description>Terminate the transaction if a BUSERROR event is detected.</description>
134465 <description>Disable</description>
134470 <description>Enable</description>
134479 … <description>Address of transaction that generated the last BUSERROR event.</description>
134494 … <description>Registers to control the behavior of the pattern matcher engine</description>
134500 <description>Configure individual match events</description>
134508 <description>Enable match filter 0</description>
134514 <description>Match filter disabled</description>
134519 <description>Match filter enabled</description>
134526 <description>Enable match filter 1</description>
134532 <description>Match filter disabled</description>
134537 <description>Match filter enabled</description>
134544 <description>Enable match filter 2</description>
134550 <description>Match filter disabled</description>
134555 <description>Match filter enabled</description>
134562 <description>Enable match filter 3</description>
134568 <description>Match filter disabled</description>
134573 <description>Match filter enabled</description>
134580 <description>Configure match filter 0 as one-shot or sticky</description>
134586 <description>Match filter stays enabled until disabled by task</description>
134591 … <description>Match filter stays enabled until next data word is received</description>
134598 <description>Configure match filter 1 as one-shot or sticky</description>
134604 <description>Match filter stays enabled until disabled by task</description>
134609 … <description>Match filter stays enabled until next data word is received</description>
134616 <description>Configure match filter 2 as one-shot or sticky</description>
134622 <description>Match filter stays enabled until disabled by task</description>
134627 … <description>Match filter stays enabled until next data word is received</description>
134634 <description>Configure match filter 3 as one-shot or sticky</description>
134640 <description>Match filter stays enabled until disabled by task</description>
134645 … <description>Match filter stays enabled until next data word is received</description>
134656 …<description>Description collection: The data to look for - any match will trigger the MATCH[n] ev…
134664 <description>Data to look for</description>
134674 <description>Unspecified</description>
134680 <description>RAM buffer start address</description>
134688 …<description>RAM buffer start address for this EasyDMA channel. This address is a word aligned Dat…
134696 <description>Maximum number of bytes in channel buffer</description>
134704 <description>Maximum number of bytes in channel buffer</description>
134712 …<description>Number of bytes transferred in the last transaction, updated after the END event. Als…
134720 …<description>Number of bytes transferred in the last transaction. In case of NACK error, includes …
134728 <description>Number of bytes transferred in the current transaction</description>
134736 …<description>Number of bytes transferred in the current transaction. Continuously updated.</descri…
134744 <description>EasyDMA list type</description>
134752 <description>List type</description>
134758 <description>Disable EasyDMA list</description>
134763 <description>Use array list</description>
134772 <description>Terminate the transaction if a BUSERROR event is detected.</description>
134785 <description>Disable</description>
134790 <description>Enable</description>
134799 … <description>Address of transaction that generated the last BUSERROR event.</description>
134818 <description>I2C compatible Two-Wire Slave Interface with EasyDMA 0</description>
134838 <description>Stop TWI transaction</description>
134846 <description>Stop TWI transaction</description>
134852 <description>Trigger task</description>
134861 <description>Suspend TWI transaction</description>
134869 <description>Suspend TWI transaction</description>
134875 <description>Trigger task</description>
134884 <description>Resume TWI transaction</description>
134892 <description>Resume TWI transaction</description>
134898 <description>Trigger task</description>
134907 <description>Prepare the TWI slave to respond to a write command</description>
134915 <description>Prepare the TWI slave to respond to a write command</description>
134921 <description>Trigger task</description>
134930 <description>Prepare the TWI slave to respond to a read command</description>
134938 <description>Prepare the TWI slave to respond to a read command</description>
134944 <description>Trigger task</description>
134953 <description>Peripheral tasks.</description>
134959 <description>Peripheral tasks.</description>
134967 …<description>Description collection: Enables the MATCH[n] event by setting the ENABLE[n] bit in th…
134975 …<description>Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register.</desc…
134981 <description>Trigger task</description>
134992 …<description>Description collection: Disables the MATCH[n] event by clearing the ENABLE[n] bit in …
135000 …<description>Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register.</de…
135006 <description>Trigger task</description>
135017 <description>Subscribe configuration for task STOP</description>
135025 <description>DPPI channel that task STOP will subscribe to</description>
135036 <description>Disable subscription</description>
135041 <description>Enable subscription</description>
135050 <description>Subscribe configuration for task SUSPEND</description>
135058 <description>DPPI channel that task SUSPEND will subscribe to</description>
135069 <description>Disable subscription</description>
135074 <description>Enable subscription</description>
135083 <description>Subscribe configuration for task RESUME</description>
135091 <description>DPPI channel that task RESUME will subscribe to</description>
135102 <description>Disable subscription</description>
135107 <description>Enable subscription</description>
135116 <description>Subscribe configuration for task PREPARERX</description>
135124 <description>DPPI channel that task PREPARERX will subscribe to</description>
135135 <description>Disable subscription</description>
135140 <description>Enable subscription</description>
135149 <description>Subscribe configuration for task PREPARETX</description>
135157 <description>DPPI channel that task PREPARETX will subscribe to</description>
135168 <description>Disable subscription</description>
135173 <description>Enable subscription</description>
135182 <description>Subscribe configuration for tasks</description>
135188 <description>Subscribe configuration for tasks</description>
135196 … <description>Description collection: Subscribe configuration for task ENABLEMATCH[n]</description>
135204 <description>DPPI channel that task ENABLEMATCH[n] will subscribe to</description>
135215 <description>Disable subscription</description>
135220 <description>Enable subscription</description>
135231 …<description>Description collection: Subscribe configuration for task DISABLEMATCH[n]</description>
135239 … <description>DPPI channel that task DISABLEMATCH[n] will subscribe to</description>
135250 <description>Disable subscription</description>
135255 <description>Enable subscription</description>
135266 <description>TWI stopped</description>
135274 <description>TWI stopped</description>
135280 <description>Event not generated</description>
135285 <description>Event generated</description>
135294 <description>TWI error</description>
135302 <description>TWI error</description>
135308 <description>Event not generated</description>
135313 <description>Event generated</description>
135322 <description>Write command received</description>
135330 <description>Write command received</description>
135336 <description>Event not generated</description>
135341 <description>Event generated</description>
135350 <description>Read command received</description>
135358 <description>Read command received</description>
135364 <description>Event not generated</description>
135369 <description>Event generated</description>
135378 <description>Peripheral events.</description>
135384 <description>Peripheral events.</description>
135390 <description>Generated after all MAXCNT bytes have been transferred</description>
135398 <description>Generated after all MAXCNT bytes have been transferred</description>
135404 <description>Event not generated</description>
135409 <description>Event generated</description>
135418 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
135426 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
135432 <description>Event not generated</description>
135437 <description>Event generated</description>
135446 <description>An error occured during the bus transfer.</description>
135454 <description>An error occured during the bus transfer.</description>
135460 <description>Event not generated</description>
135465 <description>Event generated</description>
135476 … <description>Description collection: Pattern match is detected on the DMA data bus.</description>
135484 <description>Pattern match is detected on the DMA data bus.</description>
135490 <description>Event not generated</description>
135495 <description>Event generated</description>
135505 <description>Peripheral events.</description>
135511 <description>Generated after all MAXCNT bytes have been transferred</description>
135519 <description>Generated after all MAXCNT bytes have been transferred</description>
135525 <description>Event not generated</description>
135530 <description>Event generated</description>
135539 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
135547 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
135553 <description>Event not generated</description>
135558 <description>Event generated</description>
135567 <description>An error occured during the bus transfer.</description>
135575 <description>An error occured during the bus transfer.</description>
135581 <description>Event not generated</description>
135586 <description>Event generated</description>
135597 <description>Publish configuration for event STOPPED</description>
135605 <description>DPPI channel that event STOPPED will publish to</description>
135616 <description>Disable publishing</description>
135621 <description>Enable publishing</description>
135630 <description>Publish configuration for event ERROR</description>
135638 <description>DPPI channel that event ERROR will publish to</description>
135649 <description>Disable publishing</description>
135654 <description>Enable publishing</description>
135663 <description>Publish configuration for event WRITE</description>
135671 <description>DPPI channel that event WRITE will publish to</description>
135682 <description>Disable publishing</description>
135687 <description>Enable publishing</description>
135696 <description>Publish configuration for event READ</description>
135704 <description>DPPI channel that event READ will publish to</description>
135715 <description>Disable publishing</description>
135720 <description>Enable publishing</description>
135729 <description>Publish configuration for events</description>
135735 <description>Publish configuration for events</description>
135741 <description>Publish configuration for event END</description>
135749 <description>DPPI channel that event END will publish to</description>
135760 <description>Disable publishing</description>
135765 <description>Enable publishing</description>
135774 <description>Publish configuration for event READY</description>
135782 <description>DPPI channel that event READY will publish to</description>
135793 <description>Disable publishing</description>
135798 <description>Enable publishing</description>
135807 <description>Publish configuration for event BUSERROR</description>
135815 <description>DPPI channel that event BUSERROR will publish to</description>
135826 <description>Disable publishing</description>
135831 <description>Enable publishing</description>
135842 … <description>Description collection: Publish configuration for event MATCH[n]</description>
135850 <description>DPPI channel that event MATCH[n] will publish to</description>
135861 <description>Disable publishing</description>
135866 <description>Enable publishing</description>
135876 <description>Publish configuration for events</description>
135882 <description>Publish configuration for event END</description>
135890 <description>DPPI channel that event END will publish to</description>
135901 <description>Disable publishing</description>
135906 <description>Enable publishing</description>
135915 <description>Publish configuration for event READY</description>
135923 <description>DPPI channel that event READY will publish to</description>
135934 <description>Disable publishing</description>
135939 <description>Enable publishing</description>
135948 <description>Publish configuration for event BUSERROR</description>
135956 <description>DPPI channel that event BUSERROR will publish to</description>
135967 <description>Disable publishing</description>
135972 <description>Enable publishing</description>
135983 <description>Shortcuts between local events and tasks</description>
135991 <description>Shortcut between event WRITE and task SUSPEND</description>
135997 <description>Disable shortcut</description>
136002 <description>Enable shortcut</description>
136009 <description>Shortcut between event READ and task SUSPEND</description>
136015 <description>Disable shortcut</description>
136020 <description>Enable shortcut</description>
136027 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows daisy-ch…
136033 <description>Disable shortcut</description>
136038 <description>Enable shortcut</description>
136045 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows daisy-ch…
136051 <description>Disable shortcut</description>
136056 <description>Enable shortcut</description>
136063 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows daisy-ch…
136069 <description>Disable shortcut</description>
136074 <description>Enable shortcut</description>
136081 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows daisy-ch…
136087 <description>Disable shortcut</description>
136092 <description>Enable shortcut</description>
136099 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
136105 <description>Disable shortcut</description>
136110 <description>Enable shortcut</description>
136117 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
136123 <description>Disable shortcut</description>
136128 <description>Enable shortcut</description>
136135 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
136141 <description>Disable shortcut</description>
136146 <description>Enable shortcut</description>
136153 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
136159 <description>Disable shortcut</description>
136164 <description>Enable shortcut</description>
136173 <description>Enable or disable interrupt</description>
136181 <description>Enable or disable interrupt for event STOPPED</description>
136187 <description>Disable</description>
136192 <description>Enable</description>
136199 <description>Enable or disable interrupt for event ERROR</description>
136205 <description>Disable</description>
136210 <description>Enable</description>
136217 <description>Enable or disable interrupt for event WRITE</description>
136223 <description>Disable</description>
136228 <description>Enable</description>
136235 <description>Enable or disable interrupt for event READ</description>
136241 <description>Disable</description>
136246 <description>Enable</description>
136253 <description>Enable or disable interrupt for event DMARXEND</description>
136259 <description>Disable</description>
136264 <description>Enable</description>
136271 <description>Enable or disable interrupt for event DMARXREADY</description>
136277 <description>Disable</description>
136282 <description>Enable</description>
136289 <description>Enable or disable interrupt for event DMARXBUSERROR</description>
136295 <description>Disable</description>
136300 <description>Enable</description>
136307 <description>Enable or disable interrupt for event DMARXMATCH[0]</description>
136313 <description>Disable</description>
136318 <description>Enable</description>
136325 <description>Enable or disable interrupt for event DMARXMATCH[1]</description>
136331 <description>Disable</description>
136336 <description>Enable</description>
136343 <description>Enable or disable interrupt for event DMARXMATCH[2]</description>
136349 <description>Disable</description>
136354 <description>Enable</description>
136361 <description>Enable or disable interrupt for event DMARXMATCH[3]</description>
136367 <description>Disable</description>
136372 <description>Enable</description>
136379 <description>Enable or disable interrupt for event DMATXEND</description>
136385 <description>Disable</description>
136390 <description>Enable</description>
136397 <description>Enable or disable interrupt for event DMATXREADY</description>
136403 <description>Disable</description>
136408 <description>Enable</description>
136415 <description>Enable or disable interrupt for event DMATXBUSERROR</description>
136421 <description>Disable</description>
136426 <description>Enable</description>
136435 <description>Enable interrupt</description>
136443 <description>Write '1' to enable interrupt for event STOPPED</description>
136450 <description>Read: Disabled</description>
136455 <description>Read: Enabled</description>
136463 <description>Enable</description>
136470 <description>Write '1' to enable interrupt for event ERROR</description>
136477 <description>Read: Disabled</description>
136482 <description>Read: Enabled</description>
136490 <description>Enable</description>
136497 <description>Write '1' to enable interrupt for event WRITE</description>
136504 <description>Read: Disabled</description>
136509 <description>Read: Enabled</description>
136517 <description>Enable</description>
136524 <description>Write '1' to enable interrupt for event READ</description>
136531 <description>Read: Disabled</description>
136536 <description>Read: Enabled</description>
136544 <description>Enable</description>
136551 <description>Write '1' to enable interrupt for event DMARXEND</description>
136558 <description>Read: Disabled</description>
136563 <description>Read: Enabled</description>
136571 <description>Enable</description>
136578 <description>Write '1' to enable interrupt for event DMARXREADY</description>
136585 <description>Read: Disabled</description>
136590 <description>Read: Enabled</description>
136598 <description>Enable</description>
136605 <description>Write '1' to enable interrupt for event DMARXBUSERROR</description>
136612 <description>Read: Disabled</description>
136617 <description>Read: Enabled</description>
136625 <description>Enable</description>
136632 <description>Write '1' to enable interrupt for event DMARXMATCH[0]</description>
136639 <description>Read: Disabled</description>
136644 <description>Read: Enabled</description>
136652 <description>Enable</description>
136659 <description>Write '1' to enable interrupt for event DMARXMATCH[1]</description>
136666 <description>Read: Disabled</description>
136671 <description>Read: Enabled</description>
136679 <description>Enable</description>
136686 <description>Write '1' to enable interrupt for event DMARXMATCH[2]</description>
136693 <description>Read: Disabled</description>
136698 <description>Read: Enabled</description>
136706 <description>Enable</description>
136713 <description>Write '1' to enable interrupt for event DMARXMATCH[3]</description>
136720 <description>Read: Disabled</description>
136725 <description>Read: Enabled</description>
136733 <description>Enable</description>
136740 <description>Write '1' to enable interrupt for event DMATXEND</description>
136747 <description>Read: Disabled</description>
136752 <description>Read: Enabled</description>
136760 <description>Enable</description>
136767 <description>Write '1' to enable interrupt for event DMATXREADY</description>
136774 <description>Read: Disabled</description>
136779 <description>Read: Enabled</description>
136787 <description>Enable</description>
136794 <description>Write '1' to enable interrupt for event DMATXBUSERROR</description>
136801 <description>Read: Disabled</description>
136806 <description>Read: Enabled</description>
136814 <description>Enable</description>
136823 <description>Disable interrupt</description>
136831 <description>Write '1' to disable interrupt for event STOPPED</description>
136838 <description>Read: Disabled</description>
136843 <description>Read: Enabled</description>
136851 <description>Disable</description>
136858 <description>Write '1' to disable interrupt for event ERROR</description>
136865 <description>Read: Disabled</description>
136870 <description>Read: Enabled</description>
136878 <description>Disable</description>
136885 <description>Write '1' to disable interrupt for event WRITE</description>
136892 <description>Read: Disabled</description>
136897 <description>Read: Enabled</description>
136905 <description>Disable</description>
136912 <description>Write '1' to disable interrupt for event READ</description>
136919 <description>Read: Disabled</description>
136924 <description>Read: Enabled</description>
136932 <description>Disable</description>
136939 <description>Write '1' to disable interrupt for event DMARXEND</description>
136946 <description>Read: Disabled</description>
136951 <description>Read: Enabled</description>
136959 <description>Disable</description>
136966 <description>Write '1' to disable interrupt for event DMARXREADY</description>
136973 <description>Read: Disabled</description>
136978 <description>Read: Enabled</description>
136986 <description>Disable</description>
136993 <description>Write '1' to disable interrupt for event DMARXBUSERROR</description>
137000 <description>Read: Disabled</description>
137005 <description>Read: Enabled</description>
137013 <description>Disable</description>
137020 <description>Write '1' to disable interrupt for event DMARXMATCH[0]</description>
137027 <description>Read: Disabled</description>
137032 <description>Read: Enabled</description>
137040 <description>Disable</description>
137047 <description>Write '1' to disable interrupt for event DMARXMATCH[1]</description>
137054 <description>Read: Disabled</description>
137059 <description>Read: Enabled</description>
137067 <description>Disable</description>
137074 <description>Write '1' to disable interrupt for event DMARXMATCH[2]</description>
137081 <description>Read: Disabled</description>
137086 <description>Read: Enabled</description>
137094 <description>Disable</description>
137101 <description>Write '1' to disable interrupt for event DMARXMATCH[3]</description>
137108 <description>Read: Disabled</description>
137113 <description>Read: Enabled</description>
137121 <description>Disable</description>
137128 <description>Write '1' to disable interrupt for event DMATXEND</description>
137135 <description>Read: Disabled</description>
137140 <description>Read: Enabled</description>
137148 <description>Disable</description>
137155 <description>Write '1' to disable interrupt for event DMATXREADY</description>
137162 <description>Read: Disabled</description>
137167 <description>Read: Enabled</description>
137175 <description>Disable</description>
137182 <description>Write '1' to disable interrupt for event DMATXBUSERROR</description>
137189 <description>Read: Disabled</description>
137194 <description>Read: Enabled</description>
137202 <description>Disable</description>
137211 <description>Error source</description>
137220 <description>RX buffer overflow detected, and prevented</description>
137226 <description>Error did not occur</description>
137231 <description>Error occurred</description>
137238 <description>NACK sent after receiving a data byte</description>
137244 <description>Error did not occur</description>
137249 <description>Error occurred</description>
137256 <description>TX buffer over-read detected, and prevented</description>
137262 <description>Error did not occur</description>
137267 <description>Error occurred</description>
137276 <description>Status register indicating which address had a match</description>
137284 …<description>Indication of which address in ADDRESS that matched the incoming address</description>
137292 <description>Enable TWIS</description>
137300 <description>Enable or disable TWIS</description>
137306 <description>Disable TWIS</description>
137311 <description>Enable TWIS</description>
137322 <description>Description collection: TWI slave address n</description>
137330 <description>TWI slave address</description>
137338 <description>Configuration register for the address match mechanism</description>
137346 <description>Enable or disable address matching on ADDRESS[0]</description>
137352 <description>Disabled</description>
137357 <description>Enabled</description>
137364 <description>Enable or disable address matching on ADDRESS[1]</description>
137370 <description>Disabled</description>
137375 <description>Enabled</description>
137384 …<description>Over-read character. Character sent out in case of an over-read of the transmit buffe…
137392 …<description>Over-read character. Character sent out in case of an over-read of the transmit buffe…
137400 <description>Unspecified</description>
137406 <description>Pin select for SCL signal</description>
137414 <description>Pin number</description>
137420 <description>Port number</description>
137426 <description>Connection</description>
137432 <description>Disconnect</description>
137437 <description>Connect</description>
137446 <description>Pin select for SDA signal</description>
137454 <description>Pin number</description>
137460 <description>Port number</description>
137466 <description>Connection</description>
137472 <description>Disconnect</description>
137477 <description>Connect</description>
137487 <description>Unspecified</description>
137493 <description>Unspecified</description>
137499 <description>RAM buffer start address</description>
137507 …<description>RAM buffer start address for this EasyDMA channel. This address is a word aligned Dat…
137515 <description>Maximum number of bytes in channel buffer</description>
137523 <description>Maximum number of bytes in channel buffer</description>
137531 …<description>Number of bytes transferred in the last transaction, updated after the END event. Als…
137539 …<description>Number of bytes transferred in the last transaction. In case of NACK error, includes …
137547 <description>Number of bytes transferred in the current transaction</description>
137555 …<description>Number of bytes transferred in the current transaction. Continuously updated.</descri…
137563 <description>EasyDMA list type</description>
137571 <description>List type</description>
137577 <description>Disable EasyDMA list</description>
137582 <description>Use array list</description>
137591 <description>Terminate the transaction if a BUSERROR event is detected.</description>
137604 <description>Disable</description>
137609 <description>Enable</description>
137618 … <description>Address of transaction that generated the last BUSERROR event.</description>
137633 … <description>Registers to control the behavior of the pattern matcher engine</description>
137639 <description>Configure individual match events</description>
137647 <description>Enable match filter 0</description>
137653 <description>Match filter disabled</description>
137658 <description>Match filter enabled</description>
137665 <description>Enable match filter 1</description>
137671 <description>Match filter disabled</description>
137676 <description>Match filter enabled</description>
137683 <description>Enable match filter 2</description>
137689 <description>Match filter disabled</description>
137694 <description>Match filter enabled</description>
137701 <description>Enable match filter 3</description>
137707 <description>Match filter disabled</description>
137712 <description>Match filter enabled</description>
137719 <description>Configure match filter 0 as one-shot or sticky</description>
137725 <description>Match filter stays enabled until disabled by task</description>
137730 … <description>Match filter stays enabled until next data word is received</description>
137737 <description>Configure match filter 1 as one-shot or sticky</description>
137743 <description>Match filter stays enabled until disabled by task</description>
137748 … <description>Match filter stays enabled until next data word is received</description>
137755 <description>Configure match filter 2 as one-shot or sticky</description>
137761 <description>Match filter stays enabled until disabled by task</description>
137766 … <description>Match filter stays enabled until next data word is received</description>
137773 <description>Configure match filter 3 as one-shot or sticky</description>
137779 <description>Match filter stays enabled until disabled by task</description>
137784 … <description>Match filter stays enabled until next data word is received</description>
137795 …<description>Description collection: The data to look for - any match will trigger the MATCH[n] ev…
137803 <description>Data to look for</description>
137813 <description>Unspecified</description>
137819 <description>RAM buffer start address</description>
137827 …<description>RAM buffer start address for this EasyDMA channel. This address is a word aligned Dat…
137835 <description>Maximum number of bytes in channel buffer</description>
137843 <description>Maximum number of bytes in channel buffer</description>
137851 …<description>Number of bytes transferred in the last transaction, updated after the END event. Als…
137859 …<description>Number of bytes transferred in the last transaction. In case of NACK error, includes …
137867 <description>Number of bytes transferred in the current transaction</description>
137875 …<description>Number of bytes transferred in the current transaction. Continuously updated.</descri…
137883 <description>EasyDMA list type</description>
137891 <description>List type</description>
137897 <description>Disable EasyDMA list</description>
137902 <description>Use array list</description>
137911 <description>Terminate the transaction if a BUSERROR event is detected.</description>
137924 <description>Disable</description>
137929 <description>Enable</description>
137938 … <description>Address of transaction that generated the last BUSERROR event.</description>
137957 <description>UART with EasyDMA 1</description>
137969 <description>Serial Peripheral Interface Master with EasyDMA 3</description>
137980 <description>SPI Slave 2</description>
137992 <description>I2C compatible Two-Wire Master Interface with EasyDMA 1</description>
138004 <description>I2C compatible Two-Wire Slave Interface with EasyDMA 1</description>
138016 <description>UART with EasyDMA 2</description>
138028 <description>Distributed programmable peripheral interconnect controller 5</description>
138036 <description>Timer/Counter 4</description>
138047 <description>Timer/Counter 5</description>
138058 <description>Pulse width modulation unit 2</description>
138069 <description>Serial Peripheral Interface Master with EasyDMA 4</description>
138080 <description>SPI Slave 3</description>
138092 <description>I2C compatible Two-Wire Master Interface with EasyDMA 2</description>
138104 <description>I2C compatible Two-Wire Slave Interface with EasyDMA 2</description>
138116 <description>UART with EasyDMA 3</description>
138128 <description>Serial Peripheral Interface Master with EasyDMA 5</description>
138139 <description>SPI Slave 4</description>
138151 <description>I2C compatible Two-Wire Master Interface with EasyDMA 3</description>
138163 <description>I2C compatible Two-Wire Slave Interface with EasyDMA 3</description>
138175 <description>UART with EasyDMA 4</description>
138187 <description>Distributed programmable peripheral interconnect controller 6</description>
138195 <description>Timer/Counter 6</description>
138206 <description>Timer/Counter 7</description>
138217 <description>Pulse width modulation unit 3</description>
138228 <description>Serial Peripheral Interface Master with EasyDMA 6</description>
138239 <description>SPI Slave 5</description>
138251 <description>I2C compatible Two-Wire Master Interface with EasyDMA 4</description>
138263 <description>I2C compatible Two-Wire Slave Interface with EasyDMA 4</description>
138275 <description>UART with EasyDMA 5</description>
138287 <description>Serial Peripheral Interface Master with EasyDMA 7</description>
138298 <description>SPI Slave 6</description>
138310 <description>I2C compatible Two-Wire Master Interface with EasyDMA 5</description>
138322 <description>I2C compatible Two-Wire Slave Interface with EasyDMA 5</description>
138334 <description>UART with EasyDMA 6</description>
138346 <description>Distributed programmable peripheral interconnect controller 7</description>
138354 <description>Timer/Counter 8</description>
138365 <description>Timer/Counter 9</description>
138376 <description>Pulse width modulation unit 4</description>
138387 <description>Serial Peripheral Interface Master with EasyDMA 8</description>
138398 <description>SPI Slave 7</description>
138410 <description>I2C compatible Two-Wire Master Interface with EasyDMA 6</description>
138422 <description>I2C compatible Two-Wire Slave Interface with EasyDMA 6</description>
138434 <description>UART with EasyDMA 7</description>
138446 <description>Serial Peripheral Interface Master with EasyDMA 9</description>
138457 <description>SPI Slave 8</description>
138469 <description>I2C compatible Two-Wire Master Interface with EasyDMA 7</description>
138481 <description>I2C compatible Two-Wire Slave Interface with EasyDMA 7</description>
138493 <description>UART with EasyDMA 8</description>