Lines Matching full:description
9 …<description>nRF54H20 reference description for system-on-chip with many ARM 32-bit Cortex-M33 mic…
54 <description>Factory Information Configuration Registers</description>
68 <description>Unspecified</description>
74 <description>Device address type.</description>
82 <description>Device address type.</description>
88 <description>Public address.</description>
93 <description>Random address.</description>
104 <description>Description collection: 48 bit device address.</description>
112 <description>Device address [n].</description>
122 <description>Description collection: Encryption Root.</description>
130 <description>Encryption root word [n].</description>
140 <description>Description collection: Identity Root.</description>
148 <description>Identity root word [n].</description>
157 <description>Unspecified</description>
165 <description>Description collection: Default header for NFC Tag.</description>
173 <description>Unique identifier byte 0</description>
179 <description>Unique identifier byte 1</description>
185 <description>Unique identifier byte 2</description>
191 <description>Unique identifier byte 3</description>
200 <description>Device info</description>
206 <description>Configuration identifier</description>
214 <description>Identification number for the HW</description>
222 <description>Part code</description>
230 <description>Part code</description>
236 <description>Unspecified</description>
245 <description>Part Variant, Hardware version and Production configuration</description>
253 …<description>Part Variant, Hardware version and Production configuration, encoded as ASCII</descri…
259 <description>Unspecified</description>
268 <description>Package option</description>
276 <description>Package option</description>
282 <description>Unspecified</description>
291 <description>RAM variant</description>
299 <description>RAM variant</description>
305 <description>Unspecified</description>
314 <description>MRAM variant</description>
322 <description>MRAM variant</description>
328 <description>Unspecified</description>
337 <description>Code memory page size in bytes</description>
345 <description>Code memory page size in bytes</description>
351 <description>Unspecified</description>
360 <description>Code memory size</description>
368 <description>Code memory size in number of pages</description>
374 <description>Unspecified</description>
383 <description>Device type</description>
391 <description>Device type</description>
397 <description>Device is an physical DIE</description>
402 <description>Device is an FPGA</description>
412 <description>Unspecified</description>
418 <description>Unspecified</description>
424 <description>Unspecified</description>
432 <description>Description collection: Trim value for GLOBAL.SAADC.CAL</description>
440 <description>Trim value</description>
448 <description>Trim value for GLOBAL.SAADC.CALREF</description>
456 <description>Trim value</description>
466 … <description>Description collection: Trim value for GLOBAL.SAADC.TRIM.LINCALCOEFF</description>
474 <description>Trim value</description>
483 <description>Unspecified</description>
489 <description>Trim value for NFCT.BIASCFG</description>
497 <description>Trim value</description>
506 <description>Unspecified</description>
512 <description>Unspecified</description>
518 <description>Trim value for GLOBAL.CANPLL.TRIM.CTUNE</description>
526 <description>Trim value</description>
536 <description>Unspecified</description>
542 <description>Trim value for GLOBAL.COMP.REFTRIM</description>
550 <description>Trim value</description>
560 <description>Unspecified</description>
566 <description>Unspecified</description>
572 <description>Unspecified</description>
578 <description>Trim value for APPLICATION.HSFLL.TRIM.VSUP</description>
586 <description>Trim value</description>
596 … <description>Description collection: Trim value for APPLICATION.HSFLL.TRIM.COARSE</description>
604 <description>Trim value</description>
614 … <description>Description collection: Trim value for APPLICATION.HSFLL.TRIM.FINE</description>
622 <description>Trim value</description>
630 <description>Trim value for APPLICATION.HSFLL.TRIM.TCOEF</description>
638 <description>Trim value</description>
648 <description>Unspecified</description>
656 <description>Unspecified</description>
662 …<description>Description cluster: Trim value for APPLICATION.MEMCONF.BLOCKTYPE[n].TRIM</descriptio…
670 <description>Trim value</description>
681 <description>Unspecified</description>
687 <description>Unspecified</description>
693 <description>Unspecified</description>
699 <description>Trim value for RADIOCORE.HSFLL.TRIM.VSUP</description>
707 <description>Trim value</description>
717 … <description>Description collection: Trim value for RADIOCORE.HSFLL.TRIM.COARSE</description>
725 <description>Trim value</description>
735 … <description>Description collection: Trim value for RADIOCORE.HSFLL.TRIM.FINE</description>
743 <description>Trim value</description>
751 <description>Trim value for RADIOCORE.HSFLL.TRIM.TCOEF</description>
759 <description>Trim value</description>
769 <description>Unspecified</description>
777 <description>Unspecified</description>
783 … <description>Description cluster: Trim value for RADIOCORE.MEMCONF.BLOCKTYPE[n].TRIM</description>
791 <description>Trim value</description>
805 <description>USBHSCORE</description>
820 <description>Control and Status Register</description>
828 <description>Mode: Host only. VBUS Valid Override Enable (VbvalidOvEn)</description>
834 …<description>Override is disabled and bvalid signal from the respective PHY selected is used inter…
839 …<description>The vbus-valid signal received from the PHY is overridden with GOTGCTL.VbvalidOvVal</…
846 <description>Mode: Host only. VBUS Valid OverrideValue (VbvalidOvVal)</description>
852 <description>vbusvalid value when GOTGCTL.VbvalidOvEn = 1</description>
857 <description>vbusvalid value when GOTGCTL.VbvalidOvEn is 1</description>
864 …<description>Mode: Host only. A-Peripheral Session Valid Override Enable (AvalidOvEn)</description>
870 <description>Derive AValid from PHY</description>
875 <description>Derive Avalid from GOTGCTL.AvalidOvVal</description>
882 … <description>Mode: Host only. A-Peripheral Session Valid OverrideValue (AvalidOvVal)</description>
888 <description>Avalid value is 1'b0 when GOTGCTL.AvalidOvEn =1</description>
893 <description>Avalid value is 1'b1 when GOTGCTL.AvalidOvEn =1</description>
900 …<description>Mode: Device only. B-Peripheral Session Valid Override Value (BvalidOvEn)</descriptio…
906 …<description>Override is disabled and bvalid signal from the respective PHY selected is used inter…
911 …<description>Internally Bvalid received from the PHY is overridden with GOTGCTL.BvalidOvVal</descr…
918 …<description>Mode: Device only. B-Peripheral Session Valid OverrideValue (BvalidOvVal)</descriptio…
924 <description>Bvalid value when GOTGCTL.BvalidOvEn =1</description>
929 <description>Bvalid value when GOTGCTL.BvalidOvEn =1</description>
936 <description>Mode: Host and Device. Debounce Filter Bypass</description>
942 <description>Debounce Filter Bypass is disabled.</description>
947 <description>Debounce Filter Bypass is enabled.</description>
954 <description>Mode: Host and Device. Connector ID Status (ConIDSts)</description>
961 <description>The core is in A-Device mode.</description>
966 <description>The core is in B-Device mode.</description>
973 <description>Mode: Host only. Long/Short Debounce Time (DbncTime)</description>
980 …<description>Long debounce time, used for physical connections (100 ms + 2.5 micro-sec)</descripti…
985 … <description>Short debounce time, used for soft connections (2.5 micro-sec)</description>
992 <description>Mode: Host only. A-Session Valid (ASesVld)</description>
999 <description>A-session is not valid.</description>
1004 <description>A-session is valid.</description>
1011 <description>Mode: Device only. B-Session Valid (BSesVld)</description>
1018 <description>B-session is not valid.</description>
1023 <description>B-session is valid.</description>
1030 <description>OTG Version (OTGVer)</description>
1036 <description>Supports OTG Version 1.3</description>
1041 <description>Supports OTG Version 2.0</description>
1048 <description>Current Mode of Operation (CurMod)</description>
1055 <description>Current mode is device mode.</description>
1060 <description>Current mode is host mode.</description>
1067 <description>Mode: Host and Device. Multi Valued ID pin (MultValIdBC)</description>
1074 <description>B-Device connected to ACA. VBUS is on.</description>
1079 <description>B-Device connected to ACA. VBUS is off.</description>
1084 <description>A-Device connected to ACA</description>
1089 <description>A-Device not connected to ACA</description>
1094 <description>B-Device not connected to ACA</description>
1101 …description>Mode: Device Only. This bit when programmed to 1'b1 results in the core asserting chir…
1107 …<description>The controller does not assert chirp_on before sending an actual Chirp 'K' signal on …
1112 …<description>The controller asserts chirp_on before sending an actual Chirp 'K' signal on USB.</de…
1121 <description>Interrupt Register</description>
1129 <description>Mode: Host and Device. Session End Detected (SesEndDet)</description>
1135 <description>Session is Active</description>
1140 <description>SessionEnd utmiotg_bvalid signal is deasserted</description>
1147 …<description>Mode: Host and Device. Session Request Success Status Change (SesReqSucStsChng)</desc…
1153 <description>No Change in Session Request Status</description>
1158 <description>Session Request Status has changed</description>
1165 …<description>Mode: Host and Device. Host Negotiation Success Status Change (HstNegSucStsChng)</des…
1171 <description>No Change</description>
1176 <description>Host Negotiation Status Change</description>
1183 <description>Mode:Host and Device. Host Negotiation Detected (HstNegDet)</description>
1189 <description>No Active HNP Request</description>
1194 <description>Active HNP request detected</description>
1201 … <description>Mode: Host and Device. A-Device Timeout Change (ADevTOUTChg)</description>
1207 <description>No A-Device Timeout</description>
1212 <description>A-Device Timeout</description>
1219 <description>Mode: Host only. Debounce Done (DbnceDone)</description>
1225 <description>After Connect waiting for Debounce to complete</description>
1230 <description>Debounce completed</description>
1237 …<description>This bit when set indicates that there is a change in the value of at least one ACA p…
1243 <description>Indicates there is no change in ACA pin value</description>
1248 <description>Indicates there is a change in ACA pin value</description>
1257 <description>AHB Configuration Register</description>
1265 <description>Mode: Host and device. Global Interrupt Mask (GlblIntrMsk)</description>
1271 <description>Mask the interrupt assertion to the application</description>
1276 <description>Unmask the interrupt assertion to the application.</description>
1283 <description>Mode: Host and device. Burst Length/Type (HBstLen)</description>
1289 <description>1 word or single</description>
1294 <description>4 words or INCR</description>
1299 <description>8 words</description>
1304 <description>16 words or INCR4</description>
1309 <description>32 words</description>
1314 <description>64 words or INCR8</description>
1319 <description>128 words</description>
1324 <description>256 words or INCR16</description>
1329 <description>Others reserved</description>
1336 <description>Mode: Host and device. DMA Enable (DMAEn)</description>
1342 <description>Core operates in Slave mode</description>
1347 <description>Core operates in a DMA mode</description>
1354 … <description>Mode: Host and device. Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)</description>
1360 …<description>DIEPINTn.TxFEmp interrupt indicates that the Non-Periodic TxFIFO is half empty or tha…
1365 …description>GINTSTS.NPTxFEmp interrupt indicates that the Non-Periodic TxFIFO is completely empty …
1372 <description>Mode: Host and Device. Remote Memory Support (RemMemSupp)</description>
1378 <description>Remote Memory Support Feature disabled</description>
1383 <description>Remote Memory Support Feature enabled</description>
1390 …<description>Mode: Host and Device. Notify All DMA Write Transactions (NotiAllDmaWrit)</descriptio…
1396 <description>Unspecified</description>
1401 …description>The core asserts int_dma_req for all the DMA write transactions on the AHB interface a…
1408 <description>Mode: Host and Device. AHB Single Support (AHBSingle)</description>
1414 … <description>The remaining data in the transfer is sent using INCR burst size</description>
1419 … <description>The remaining data in the transfer is sent using Single burst size</description>
1428 <description>USB Configuration Register</description>
1436 <description>Mode: Host and Device. HS/FS Timeout Calibration (TOutCal)</description>
1442 <description>Add 0 PHY clocks</description>
1447 <description>Add 1 PHY clocks</description>
1452 <description>Add 2 PHY clocks</description>
1457 <description>Add 3 PHY clocks</description>
1462 <description>Add 4 PHY clocks</description>
1467 <description>Add 5 PHY clocks</description>
1472 <description>Add 6 PHY clocks</description>
1477 <description>Add 7 PHY clocks</description>
1484 <description>Mode: Host and Device. PHY Interface (PHYIf)</description>
1490 <description>PHY 8bit Mode</description>
1495 <description>PHY 16bit Mode</description>
1502 <description>Mode: Host and Device. ULPI or UTMI+ Select (ULPI_UTMI_Sel)</description>
1509 <description>UTMI+ Interface</description>
1514 <description>ULPI Interface</description>
1521 … <description>Mode: Host and Device. Full-Speed Serial Interface Select (FSIntf)</description>
1528 <description>6-pin unidirectional full-speed serial interface</description>
1533 <description>3-pin bidirectional full-speed serial interface</description>
1540 <description>PHYSel</description>
1547 <description>USB 2.0 high-speed UTMI+ or ULPI PHY is selected</description>
1552 <description>USB 1.1 full-speed serial transceiver is selected</description>
1559 <description>Mode: Device only. USB Turnaround Time (USBTrdTim)</description>
1565 <description>MAC interface is 16-bit UTMI+.</description>
1570 <description>MAC interface is 8-bit UTMI+.</description>
1577 <description>PHY Low-Power Clock Select (PhyLPwrClkSel)</description>
1583 <description>480-MHz Internal PLL clock</description>
1588 <description>48-MHz External Clock</description>
1595 … <description>Mode: Device only. TermSel DLine Pulsing Selection (TermSelDLPulse)</description>
1601 <description>Data line pulsing using utmi_txvalid</description>
1606 <description>Data line pulsing using utmi_termsel</description>
1613 <description>Mode: Host and Device. IC_USB-Capable (IC_USBCap)</description>
1620 <description>IC_USB PHY Interface is not selected</description>
1625 <description>IC_USB PHY Interface is selected</description>
1632 <description>Mode: Device only. Tx End Delay (TxEndDelay)</description>
1638 <description>Normal Mode</description>
1643 <description>Tx End delay</description>
1650 <description>Mode: Host and device. Force Host Mode (ForceHstMode)</description>
1656 <description>Normal Mode</description>
1661 <description>Force Host Mode</description>
1668 <description>Mode:Host and device. Force Device Mode (ForceDevMode)</description>
1674 <description>Normal Mode</description>
1679 <description>Force Device Mode</description>
1686 <description>Mode: Host and device. Corrupt Tx packet (CorruptTxPkt)</description>
1693 <description>Normal Mode</description>
1698 <description>Debug Mode</description>
1707 <description>Reset Register</description>
1715 <description>Mode: Host and Device. Core Soft Reset (CSftRst)</description>
1721 <description>No reset</description>
1726 <description>Resets hclk and phy_clock domains</description>
1733 …<description>Mode: Host and Device. PIU FS Dedicated Controller Soft Reset (PIUFSSftRst)</descript…
1739 <description>No Reset</description>
1744 <description>PIU FS Dedicated Controller Soft Reset</description>
1751 <description>Mode: Host only. Host Frame Counter Reset (FrmCntrRst)</description>
1757 <description>No reset</description>
1762 <description>Host Frame Counter Reset</description>
1769 <description>Mode: Host and Device. RxFIFO Flush (RxFFlsh)</description>
1775 <description>Does not flush the entire RxFIFO</description>
1780 <description>Flushes the entire RxFIFO</description>
1787 <description>Mode: Host and Device. TxFIFO Flush (TxFFlsh)</description>
1793 <description>No Flush</description>
1798 <description>Selectively flushes a single or all transmit FIFOs</description>
1805 <description>Mode: Host and Device. TxFIFO Number (TxFNum)</description>
1811 …description>-Periodic TxFIFO flush in host mode -Periodic TxFIFO 0 flush in device mode when in sh…
1816 …description>-Periodic TxFIFO flush in host mode -Periodic TxFIFO 1 flush in device mode when in sh…
1821 …description>-Periodic TxFIFO 2 flush in device mode when in shared FIFO operation -TXFIFO 2 flush …
1826 …description>-Periodic TxFIFO 3 flush in device mode when in shared FIFO operation -TXFIFO 3 flush …
1831 …description>-Periodic TxFIFO 4 flush in device mode when in shared FIFO operation -TXFIFO 4 flush …
1836 …description>-Periodic TxFIFO 5 flush in device mode when in shared FIFO operation -TXFIFO 5 flush …
1841 …description>-Periodic TxFIFO 6 flush in device mode when in shared FIFO operation -TXFIFO 6 flush …
1846 …description>-Periodic TxFIFO 7 flush in device mode when in shared FIFO operation -TXFIFO 7 flush …
1851 …description>-Periodic TxFIFO 8 flush in device mode when in shared FIFO operation -TXFIFO 8 flush …
1856 …description>-Periodic TxFIFO 9 flush in device mode when in shared FIFO operation -TXFIFO 9 flush …
1861 …description>-Periodic TxFIFO 10 flush in device mode when in shared FIFO operation -TXFIFO 10 flus…
1866 …description>-Periodic TxFIFO 11 flush in device mode when in shared FIFO operation -TXFIFO 11 flus…
1871 …description>-Periodic TxFIFO 12 flush in device mode when in shared FIFO operation -TXFIFO 12 flus…
1876 …description>-Periodic TxFIFO 13 flush in Device mode when in shared FIFO operation -TXFIFO 13 flus…
1881 …description>-Periodic TxFIFO 14 flush in Device mode when in shared FIFO operation -TXFIFO 14 flus…
1886 …description>-Periodic TxFIFO 15 flush in Device mode when in shared FIFO operation - TXFIFO 15 flu…
1891 <description>Flush all the transmit FIFOs in device or host mode</description>
1898 <description>Mode: Host and Device. Core Soft Reset Done (CSftRstDone)</description>
1904 <description>No reset</description>
1909 <description>Core Soft Reset is done</description>
1916 <description>Mode: Host and Device. DMA Request Signal (DMAReq)</description>
1923 <description>No DMA request</description>
1928 <description>DMA request is in progress</description>
1935 <description>Mode: Host and Device. AHB Master Idle (AHBIdle)</description>
1942 <description>Not Idle</description>
1947 <description>AHB Master Idle</description>
1956 <description>Interrupt Register</description>
1964 <description>Mode: Host and Device. Current Mode of Operation (CurMod)</description>
1971 <description>Device mode</description>
1976 <description>Host mode</description>
1983 <description>Mode: Host and Device. Mode Mismatch Interrupt (ModeMis)</description>
1989 <description>No Mode Mismatch Interrupt</description>
1994 <description>Mode Mismatch Interrupt</description>
2001 <description>Mode: Host and Device. OTG Interrupt (OTGInt)</description>
2008 <description>No Interrupt</description>
2013 <description>OTG Interrupt</description>
2020 <description>Mode: Host and Device. Start of (micro)Frame (Sof)</description>
2026 <description>No Start of Frame</description>
2031 <description>Start of Frame</description>
2038 <description>Mode: Host and Device. RxFIFO Non-Empty (RxFLvl)</description>
2045 <description>Rx Fifo is empty</description>
2050 <description>Rx Fifo is not empty</description>
2057 <description>Mode: Host and Device. Non-periodic TxFIFO Empty (NPTxFEmp)</description>
2064 <description>Non-periodic TxFIFO is not empty</description>
2069 <description>Non-periodic TxFIFO is empty</description>
2076 … <description>Mode: Device only. Global IN Non-periodic NAK Effective (GINNakEff)</description>
2083 <description>Global Non-periodic IN NAK not active</description>
2088 <description>Set Global Non-periodic IN NAK bit</description>
2095 <description>Mode: Device only. Global OUT NAK Effective (GOUTNakEff)</description>
2102 <description>Not Active</description>
2107 <description>Global OUT NAK Effective</description>
2114 <description>Mode: Device only. Early Suspend (ErlySusp)</description>
2120 <description>No Idle state detected</description>
2125 <description>3ms of Idle state detected</description>
2132 <description>Mode: Device only. USB Suspend (USBSusp)</description>
2138 <description>Not Active</description>
2143 <description>USB Suspend</description>
2150 <description>Mode: Device only. USB Reset (USBRst)</description>
2156 <description>Not active</description>
2161 <description>USB Reset</description>
2168 <description>Mode: Device only. Enumeration Done (EnumDone)</description>
2174 <description>Not active</description>
2179 <description>Enumeration Done</description>
2186 …<description>Mode: Device only. Isochronous OUT Packet Dropped Interrupt (ISOOutDrop)</description>
2192 <description>Not active</description>
2197 <description>Isochronous OUT Packet Dropped Interrupt</description>
2204 <description>Mode: Device only. End of Periodic Frame Interrupt (EOPF)</description>
2210 <description>Not active</description>
2215 <description>End of Periodic Frame Interrupt</description>
2222 <description>Mode: Device only. Restore Done Interrupt (RstrDoneInt)</description>
2228 <description>Not active</description>
2233 <description>Restore Done Interrupt</description>
2240 <description>Mode: Device only. Endpoint Mismatch Interrupt (EPMis)</description>
2246 <description>Not active</description>
2251 <description>Endpoint Mismatch Interrupt</description>
2258 <description>Mode: Device only. IN Endpoints Interrupt (IEPInt)</description>
2265 <description>Not active</description>
2270 <description>IN Endpoints Interrupt</description>
2277 <description>Mode: Device only. OUT Endpoints Interrupt (OEPInt)</description>
2284 <description>Not active</description>
2289 <description>OUT Endpoints Interrupt</description>
2296 … <description>Mode: Device only. Incomplete Isochronous IN Transfer (incompISOIN)</description>
2302 <description>Not active</description>
2307 <description>Incomplete Isochronous IN Transfer</description>
2314 <description>Incomplete Periodic Transfer (incomplP)</description>
2320 <description>Not active</description>
2325 <description>Incomplete Periodic Transfer</description>
2332 <description>Mode: Device only. Data Fetch Suspended (FetSusp)</description>
2338 <description>Not active</description>
2343 <description>Data Fetch Suspended</description>
2350 <description>Mode: Device only. Reset detected Interrupt (ResetDet)</description>
2356 <description>Not active</description>
2361 <description>Reset detected Interrupt</description>
2368 <description>Mode: Host only. Host Port Interrupt (PrtInt)</description>
2375 <description>Not active</description>
2380 <description>Host Port Interrupt</description>
2387 <description>Mode: Host only. Host Channels Interrupt (HChInt)</description>
2394 <description>Not active</description>
2399 <description>Host Channels Interrupt</description>
2406 … <description>Mode: Host and Device. LPM Transaction Received Interrupt (LPM_Int).</description>
2412 <description>Not Active</description>
2417 <description>LPM Transaction Received Interrupt</description>
2424 … <description>Mode: Host and Device. Connector ID Status Change (ConIDStsChng)</description>
2430 <description>Not Active</description>
2435 <description>Connector ID Status Change</description>
2442 <description>Mode: Host only. Disconnect Detected Interrupt (DisconnInt)</description>
2448 <description>Not active</description>
2453 <description>Disconnect Detected Interrupt</description>
2460 …<description>Mode: Host and Device. Session Request/New Session Detected Interrupt (SessReqInt)</d…
2466 <description>Not active</description>
2471 <description>Session Request New Session Detected Interrupt</description>
2478 …<description>Mode: Host and Device. Resume/Remote Wakeup Detected Interrupt (WkUpInt)</description>
2484 <description>Not active</description>
2489 <description>Resume or Remote Wakeup Detected Interrupt</description>
2498 <description>Interrupt Mask Register</description>
2506 … <description>Mode: Host and Device. Mode Mismatch Interrupt Mask (ModeMisMsk)</description>
2512 <description>Mode Mismatch Interrupt Mask</description>
2517 <description>No Mode Mismatch Interrupt Mask</description>
2524 <description>Mode: Host and Device. OTG Interrupt Mask (OTGIntMsk)</description>
2530 <description>OTG Interrupt Mask</description>
2535 <description>No OTG Interrupt Mask</description>
2542 <description>Mode: Host and Device. Start of (micro)Frame Mask (SofMsk)</description>
2548 <description>Start of Frame Mask</description>
2553 <description>No Start of Frame Mask</description>
2560 … <description>Mode: Host and Device. Receive FIFO Non-Empty Mask (RxFLvlMsk)</description>
2566 <description>Receive FIFO Non-Empty Mask</description>
2571 <description>No Receive FIFO Non-Empty Mask</description>
2578 … <description>Mode: Host and Device. Non-periodic TxFIFO Empty Mask (NPTxFEmpMsk)</description>
2584 <description>Non-periodic TxFIFO Empty Mask</description>
2589 <description>No Non-periodic TxFIFO Empty Mask</description>
2596 …<description>Mode: Device only,. Global Non-periodic IN NAK Effective Mask (GINNakEffMsk)</descrip…
2602 <description>Global Non-periodic IN NAK Effective Mask</description>
2607 <description>No Global Non-periodic IN NAK Effective Mask</description>
2614 … <description>Mode: Device only. Global OUT NAK Effective Mask (GOUTNakEffMsk)</description>
2620 <description>Global OUT NAK Effective Mask</description>
2625 <description>No Global OUT NAK Effective Mask</description>
2632 <description>Mode: Device only. Early Suspend Mask (ErlySuspMsk)</description>
2638 <description>Early Suspend Mask</description>
2643 <description>No Early Suspend Mask</description>
2650 <description>Mode: Device only. USB Suspend Mask (USBSuspMsk)</description>
2656 <description>USB Suspend Mask</description>
2661 <description>No USB Suspend Mask</description>
2668 <description>Mode: Device only. USB Reset Mask (USBRstMsk)</description>
2674 <description>USB Reset Mask</description>
2679 <description>No USB Reset Mask</description>
2686 <description>Mode: Device only. Enumeration Done Mask (EnumDoneMsk)</description>
2692 <description>Enumeration Done Mask</description>
2697 <description>No Enumeration Done Mask</description>
2704 …<description>Mode: Device only. Isochronous OUT Packet Dropped Interrupt Mask (ISOOutDropMsk)</des…
2710 <description>Isochronous OUT Packet Dropped Interrupt Mask</description>
2715 <description>No Isochronous OUT Packet Dropped Interrupt Mask</description>
2722 … <description>Mode: Device only. End of Periodic Frame Interrupt Mask (EOPFMsk)</description>
2728 <description>End of Periodic Frame Interrupt Mask</description>
2733 <description>No End of Periodic Frame Interrupt Mask</description>
2740 … <description>Mode: Host and Device. Restore Done Interrupt Mask (RstrDoneIntMsk)</description>
2746 <description>Restore Done Interrupt Mask</description>
2751 <description>No Restore Done Interrupt Mask</description>
2758 … <description>Mode: Device only. Endpoint Mismatch Interrupt Mask (EPMisMsk)</description>
2764 <description>Endpoint Mismatch Interrupt Mask</description>
2769 <description>No Endpoint Mismatch Interrupt Mask</description>
2776 <description>Mode: Device only. IN Endpoints Interrupt Mask (IEPIntMsk)</description>
2782 <description>IN Endpoints Interrupt Mask</description>
2787 <description>No IN Endpoints Interrupt Mask</description>
2794 <description>Mode: Device only. OUT Endpoints Interrupt Mask (OEPIntMsk)</description>
2800 <description>OUT Endpoints Interrupt Mask</description>
2805 <description>No OUT Endpoints Interrupt Mask</description>
2812 <description>Incomplete Periodic Transfer Mask (incomplPMsk)</description>
2818 …<description>Host mode: Incomplete Periodic Transfer MaskDevice mode: Incomplete Isochronous OUT T…
2823 …<description>Host mode: No Incomplete Periodic Transfer MaskDevice mode: No Incomplete Isochronous…
2830 <description>Mode: Device only. Data Fetch Suspended Mask (FetSuspMsk)</description>
2836 <description>Data Fetch Suspended Mask</description>
2841 <description>No Data Fetch Suspended Mask</description>
2848 … <description>Mode: Device only. Reset detected Interrupt Mask (ResetDetMsk)</description>
2854 <description>Reset detected Interrupt Mask</description>
2859 <description>No Reset detected Interrupt Mask</description>
2866 <description>Mode: Host only. Host Port Interrupt Mask (PrtIntMsk)</description>
2872 <description>Host Port Interrupt Mask</description>
2877 <description>No Host Port Interrupt Mask</description>
2884 <description>Mode: Host only. Host Channels Interrupt Mask (HChIntMsk)</description>
2890 <description>Host Channels Interrupt Mask</description>
2895 <description>No Host Channels Interrupt Mask</description>
2902 … <description>Mode: Host and Device. LPM Transaction Received Interrupt (LPM_Int)</description>
2908 <description>LPM Transaction received interrupt Mask</description>
2913 <description>No LPM Transaction received interrupt Mask</description>
2920 …<description>Mode: Host and Device. Connector ID Status Change Mask (ConIDStsChngMsk)</description>
2926 <description>Connector ID Status Change Mask</description>
2931 <description>No Connector ID Status Change Mask</description>
2938 …<description>Mode: Host and Device. Disconnect Detected Interrupt Mask (DisconnIntMsk)</descriptio…
2944 <description>Disconnect Detected Interrupt Mask</description>
2949 <description>No Disconnect Detected Interrupt Mask</description>
2956 …<description>Mode: Host and Device. Session Request/New Session Detected Interrupt Mask (SessReqIn…
2962 <description>Session Request or New Session Detected Interrupt Mask</description>
2967 … <description>No Session Request or New Session Detected Interrupt Mask</description>
2974 …<description>Mode: Host and Device. Resume/Remote Wakeup Detected Interrupt Mask (WkUpIntMsk)</des…
2980 <description>Resume or Remote Wakeup Detected Interrupt Mask</description>
2985 <description>Unmask Resume Remote Wakeup Detected Interrupt</description>
2994 <description>Receive Status Debug Read Register</description>
3002 <description>Channel Number (ChNum)</description>
3009 <description>Channel or EndPoint 0</description>
3014 <description>Channel or EndPoint 1</description>
3019 <description>Channel or EndPoint 2</description>
3024 <description>Channel or EndPoint 3</description>
3029 <description>Channel or EndPoint 4</description>
3034 <description>Channel or EndPoint 5</description>
3039 <description>Channel or EndPoint 6</description>
3044 <description>Channel or EndPoint 7</description>
3049 <description>Channel or EndPoint 8</description>
3054 <description>Channel or EndPoint 9</description>
3059 <description>Channel or EndPoint 10</description>
3064 <description>Channel or EndPoint 11</description>
3069 <description>Channel or EndPoint 12</description>
3074 <description>Channel or EndPoint 13</description>
3079 <description>Channel or EndPoint 14</description>
3084 <description>Channel or EndPoint 15</description>
3091 <description>Byte Count (BCnt)</description>
3098 <description>Data PID (DPID)</description>
3105 <description>DATA0</description>
3110 <description>DATA2</description>
3115 <description>DATA1</description>
3120 <description>MDATA</description>
3127 … <description>Packet Status (PktSts) indicates the status of the received packet.</description>
3134 <description>Global OUT NAK in device mode (triggers an interrupt)</description>
3139 …<description>IN data packet received in host mode and OUT data packet received in device mode</des…
3144 …<description>IN or OUT transfer completed in both host and device mode (triggers an interrupt)</de…
3149 … <description>SETUP transaction completed in device mode (triggers an interrupt)</description>
3154 <description>Data toggle error (triggers an interrupt) in host mode</description>
3159 <description>SETUP data packet received in device mode</description>
3164 <description>Channel halted in host mode (triggers an interrupt)</description>
3171 <description>Mode: Device only. Frame Number (FN)</description>
3180 <description>Receive Status Read/Pop Register</description>
3188 <description>Channel Number (ChNum)</description>
3195 <description>Channel or EndPoint 0</description>
3200 <description>Channel or EndPoint 1</description>
3205 <description>Channel or EndPoint 2</description>
3210 <description>Channel or EndPoint 3</description>
3215 <description>Channel or EndPoint 4</description>
3220 <description>Channel or EndPoint 5</description>
3225 <description>Channel or EndPoint 6</description>
3230 <description>Channel or EndPoint 7</description>
3235 <description>Channel or EndPoint 8</description>
3240 <description>Channel or EndPoint 9</description>
3245 <description>Channel or EndPoint 10</description>
3250 <description>Channel or EndPoint 11</description>
3255 <description>Channel or EndPoint 12</description>
3260 <description>Channel or EndPoint 13</description>
3265 <description>Channel or EndPoint 14</description>
3270 <description>Channel or EndPoint 15</description>
3277 <description>Byte Count (BCnt)</description>
3284 <description>Data PID (DPID)</description>
3291 <description>DATA0</description>
3296 <description>DATA2</description>
3301 <description>DATA1</description>
3306 <description>MDATA</description>
3313 … <description>Packet Status (PktSts) indicates the status of the received packet.</description>
3320 <description>Global OUT NAK in device mode (triggers an interrupt)</description>
3325 …<description>IN data packet received in host mode and OUT data packet received in device mode</des…
3330 …<description>IN or OUT transfer completed in both host and device mode (triggers an interrupt)</de…
3335 … <description>SETUP transaction completed in device mode (triggers an interrupt)</description>
3340 <description>Data toggle error (triggers an interrupt) in host mode</description>
3347 <description>Mode: Device only. Frame Number (FN)</description>
3356 <description>Receive FIFO Size Register</description>
3364 <description>Mode: Host and Device. RxFIFO Depth (RxFDep)</description>
3372 <description>Non-periodic Transmit FIFO Size Register</description>
3380 <description>Non-periodic Transmit RAM Start Address (NPTxFStAddr)</description>
3386 <description>Mode: Host only. Non-periodic TxFIFO Depth (NPTxFDep)</description>
3394 <description>Non-periodic Transmit FIFO/Queue Status Register</description>
3402 <description>Non-periodic TxFIFO Space Avail (NPTxFSpcAvail)</description>
3409 … <description>Non-periodic Transmit Request Queue Space Available (NPTxQSpcAvail)</description>
3416 <description>Non-periodic Transmit Request Queue is full</description>
3421 <description>1 location available</description>
3426 <description>2 locations available</description>
3431 <description>3 locations available</description>
3436 <description>4 locations available</description>
3441 <description>5 locations available</description>
3446 <description>6 locations available</description>
3451 <description>7 locations available</description>
3456 <description>8 locations available</description>
3463 <description>Top of the Non-periodic Transmit Request Queue (NPTxQTop)</description>
3470 <description>IN/OUT token</description>
3475 <description>Zero-length transmit packet (device IN/host OUT)</description>
3480 <description>PING/CSPLIT token</description>
3485 <description>Channel halt command</description>
3494 <description>General Purpose Input/Output Register</description>
3515 <description>User ID Register</description>
3523 <description>User ID (UserID) Application-programmable ID field.</description>
3531 <description>Synopsys ID Register</description>
3539 <description>Release number of the controller being used currently.</description>
3548 <description>User Hardware Configuration 1 Register</description>
3556 <description>This 32-bit field uses two bits per</description>
3565 <description>User Hardware Configuration 2 Register</description>
3573 <description>Mode of Operation (OtgMode)</description>
3580 <description>HNP- and SRP-Capable OTG (Host and Device)</description>
3585 <description>SRP-Capable OTG (Host and Device)</description>
3590 <description>Non-HNP and Non-SRP Capable OTG (Host and Device)</description>
3595 <description>SRP-Capable Device</description>
3600 <description>Non-OTG Device</description>
3605 <description>SRP-Capable Host</description>
3610 <description>Non-OTG Host</description>
3617 <description>Architecture (OtgArch)</description>
3624 <description>Slave Mode</description>
3629 <description>External DMA Mode</description>
3634 <description>Internal DMA Mode</description>
3641 <description>Point-to-Point (SingPnt)</description>
3648 <description>Multi-point application (hub and split support)</description>
3653 <description>Single-point application (no hub and split support)</description>
3660 <description>High-Speed PHY Interface Type (HSPhyType)</description>
3667 <description>High-Speed interface not supported</description>
3672 <description>High Speed Interface UTMI+ is supported</description>
3677 <description>High Speed Interface ULPI is supported</description>
3682 <description>High Speed Interfaces UTMI+ and ULPI is supported</description>
3689 <description>Full-Speed PHY Interface Type (FSPhyType)</description>
3696 <description>Full-speed interface not supported</description>
3701 <description>Dedicated full-speed interface is supported</description>
3706 <description>FS pins shared with UTMI+ pins is supported</description>
3711 <description>FS pins shared with ULPI pins is supported</description>
3718 <description>Number of Device Endpoints (NumDevEps)</description>
3725 <description>End point 0</description>
3730 <description>End point 1</description>
3735 <description>End point 2</description>
3740 <description>End point 3</description>
3745 <description>End point 4</description>
3750 <description>End point 5</description>
3755 <description>End point 6</description>
3760 <description>End point 7</description>
3765 <description>End point 8</description>
3770 <description>End point 9</description>
3775 <description>End point 10</description>
3780 <description>End point 11</description>
3785 <description>End point 12</description>
3790 <description>End point 13</description>
3795 <description>End point 14</description>
3800 <description>End point 15</description>
3807 <description>Number of Host Channels (NumHstChnl)</description>
3814 <description>Host Channel 1</description>
3819 <description>Host Channel 2</description>
3824 <description>Host Channel 3</description>
3829 <description>Host Channel 4</description>
3834 <description>Host Channel 5</description>
3839 <description>Host Channel 6</description>
3844 <description>Host Channel 7</description>
3849 <description>Host Channel 8</description>
3854 <description>Host Channel 9</description>
3859 <description>Host Channel 10</description>
3864 <description>Host Channel 11</description>
3869 <description>Host Channel 12</description>
3874 <description>Host Channel 13</description>
3879 <description>Host Channel 14</description>
3884 <description>Host Channel 15</description>
3889 <description>Host Channel 16</description>
3896 <description>Periodic OUT Channels Supported in Host Mode (PerioSupport)</description>
3903 <description>Periodic OUT Channels is not supported in Host Mode</description>
3908 <description>Periodic OUT Channels Supported in Host Mode Supported</description>
3915 <description>Dynamic FIFO Sizing Enabled (DynFifoSizing)</description>
3922 <description>Dynamic FIFO Sizing Disabled</description>
3927 <description>Dynamic FIFO Sizing Enabled</description>
3934 <description>Multi Processor Interrupt Enabled (MultiProcIntrpt)</description>
3941 <description>No Multi Processor Interrupt Enabled</description>
3946 <description>Multi Processor Interrupt Enabled</description>
3953 <description>Non-periodic Request Queue Depth (NPTxQDepth)</description>
3960 <description>Queue size 2</description>
3965 <description>Queue size 4</description>
3970 <description>Queue size 8</description>
3977 <description>Host Mode Periodic Request Queue Depth (PTxQDepth)</description>
3984 <description>Queue Depth 2</description>
3989 <description>Queue Depth 4</description>
3994 <description>Queue Depth 8</description>
3999 <description>Queue Depth 16</description>
4006 … <description>Device Mode IN Token Sequence Learning Queue Depth (TknQDepth)</description>
4015 <description>User Hardware Configuration 3 Register</description>
4023 <description>Width of Transfer Size Counters (XferSizeWidth)</description>
4030 <description>Width of Transfer Size Counter 11 bits</description>
4035 <description>Width of Transfer Size Counter 12 bits</description>
4040 <description>Width of Transfer Size Counter 13 bits</description>
4045 <description>Width of Transfer Size Counter 14 bits</description>
4050 <description>Width of Transfer Size Counter 15 bits</description>
4055 <description>Width of Transfer Size Counter 16 bits</description>
4060 <description>Width of Transfer Size Counter 17 bits</description>
4065 <description>Width of Transfer Size Counter 18 bits</description>
4070 <description>Width of Transfer Size Counter 19 bits</description>
4077 <description>Width of Packet Size Counters (PktSizeWidth)</description>
4084 <description>Width of Packet Size Counter 4</description>
4089 <description>Width of Packet Size Counter 5</description>
4094 <description>Width of Packet Size Counter 6</description>
4099 <description>Width of Packet Size Counter 7</description>
4104 <description>Width of Packet Size Counter 8</description>
4109 <description>Width of Packet Size Counter 9</description>
4114 <description>Width of Packet Size Counter 10</description>
4121 <description>OTG Function Enabled (OtgEn)</description>
4128 <description>Not OTG Capable</description>
4133 <description>OTG Capable</description>
4140 <description>I2C Selection (I2CIntSel)</description>
4147 <description>I2C Interface is not available</description>
4152 <description>I2C Interface is available</description>
4159 <description>Vendor Control Interface Support (VndctlSupt)</description>
4166 <description>Vendor Control Interface is not available.</description>
4171 <description>Vendor Control Interface is available.</description>
4178 <description>Optional Features Removed (OptFeature)</description>
4185 <description>Optional features were not Removed</description>
4190 <description>Optional Features have been Removed</description>
4197 <description>Reset Style for Clocked always Blocks in RTL (RstType)</description>
4204 <description>Asynchronous reset is used in the core</description>
4209 <description>Synchronous reset is used in the core</description>
4216 …<description>This bit indicates whether ADP logic is present within or external to the controller<…
4223 <description>ADP logic is not present along with the controller</description>
4228 <description>ADP logic is present along with the controller</description>
4235 <description>HSIC mode specified for Mode of Operation</description>
4242 <description>No HSIC capability</description>
4247 <description>HSIC-capable with shared UTMI PHY interface</description>
4254 … <description>This bit indicates the controller support for Battery Charger.</description>
4261 <description>No Battery Charger Support</description>
4266 <description>Battery Charger Support present</description>
4273 <description>LPM mode specified for Mode of Operation.</description>
4280 <description>LPM disabled</description>
4285 <description>LPM enabled</description>
4292 <description>DFIFO Depth (DfifoDepth - EP_LOC_CNT)</description>
4301 <description>User Hardware Configuration 4 Register</description>
4309 … <description>Number of Device Mode Periodic IN Endpoints (NumDevPerioEps)</description>
4316 <description>Number of Periodic IN EPs is 0</description>
4321 <description>Number of Periodic IN EPs is 1</description>
4326 <description>Number of Periodic IN EPs is 2</description>
4331 <description>Number of Periodic IN EPs is 3</description>
4336 <description>Number of Periodic IN EPs is 4</description>
4341 <description>Number of Periodic IN EPs is 5</description>
4346 <description>Number of Periodic IN EPs is 6</description>
4351 <description>Number of Periodic IN EPs is 7</description>
4356 <description>Number of Periodic IN EPs is 8</description>
4361 <description>Number of Periodic IN EPs is 9</description>
4366 <description>Number of Periodic IN EPs is 10</description>
4371 <description>Number of Periodic IN EPs is 11</description>
4376 <description>Number of Periodic IN EPs is 12</description>
4381 <description>Number of Periodic IN EPs is 13</description>
4386 <description>Number of Periodic IN EPs is 14</description>
4391 <description>Number of Periodic IN EPs is 15</description>
4398 <description>Enable Partial Power Down (PartialPwrDn)</description>
4405 <description>Partial Power Down disabled</description>
4410 <description>Partial Power Down enabled</description>
4417 <description>Minimum AHB Frequency Less Than 60 MHz (AhbFreq)</description>
4424 <description>Minimum AHB Frequency More Than 60 MHz</description>
4429 <description>Minimum AHB Frequency Less Than 60 MHz</description>
4436 <description>Enable Hibernation (Hibernation)</description>
4443 <description>Hibernation feature disabled</description>
4448 <description>Hibernation feature enabled</description>
4455 <description>Enable Hibernation</description>
4462 <description>Extended Hibernation feature not enabled</description>
4467 <description>Extended Hibernation feature enabled</description>
4474 <description>Enhanced LPM Support1 (EnhancedLPMSupt1)</description>
4481 …<description>Reject L1 Request even if Non-Periodic (Bulk/Interrupt) TxFIFO is not empty.</descrip…
4486 …<description>Accept L1 Request even if Non-Periodic (Bulk/Interrupt) TxFIFO is not empty</descript…
4493 <description>Service Interval Flow</description>
4500 <description>Service Interval Flow not supported</description>
4505 <description>Service Interval Flow supported</description>
4512 <description>Interpacket Gap ISOC OUT Worst-case Support (ipgisocSupt)</description>
4519 <description>Interpacket Gap ISOC OUT Worst-case Support is Disabled</description>
4524 … <description>Interpacket Gap ISOC OUT Worst-case Support is Enabled (Default)</description>
4531 <description>Active Clock Gating Support</description>
4538 <description>Unspecified</description>
4543 <description>Active Clock Gating Support</description>
4550 <description>Enhanced LPM Support (EnhancedLPMSupt)</description>
4557 <description>Enhanced LPM Support is enabled</description>
4564 <description>UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width</description>
4571 <description>8 bits</description>
4576 <description>16 bits</description>
4581 <description>8/16 bits, software selectable</description>
4588 <description>Number of Device Mode Control Endpoints in Addition to</description>
4595 <description>End point 0</description>
4600 <description>End point 1</description>
4605 <description>End point 2</description>
4610 <description>End point 3</description>
4615 <description>End point 4</description>
4620 <description>End point 5</description>
4625 <description>End point 6</description>
4630 <description>End point 7</description>
4635 <description>End point 8</description>
4640 <description>End point 9</description>
4645 <description>End point 10</description>
4650 <description>End point 11</description>
4655 <description>End point 12</description>
4660 <description>End point 13</description>
4665 <description>End point 14</description>
4670 <description>End point 15</description>
4677 <description>IDDIG Filter Enable (IddgFltr)</description>
4684 <description>Iddig Filter Disabled</description>
4689 <description>Iddig Filter Enabled</description>
4696 <description>VBUS Valid Filter Enabled (VBusValidFltr)</description>
4703 <description>Vbus Valid Filter Disabled</description>
4708 <description>Vbus Valid Filter Enabled</description>
4715 <description>a_valid Filter Enabled (AValidFltr)</description>
4722 <description>No filter</description>
4727 <description>Filter</description>
4734 <description>b_valid Filter Enabled (BValidFltr)</description>
4741 <description>No Filter</description>
4746 <description>Filter</description>
4753 <description>session_end Filter Enabled (SessEndFltr)</description>
4760 <description>No filter</description>
4765 <description>Filter</description>
4772 <description>Enable Dedicated Transmit FIFO for device IN Endpoints</description>
4779 <description>Dedicated Transmit FIFO Operation not enabled</description>
4784 <description>Dedicated Transmit FIFO Operation enabled</description>
4791 … <description>Number of Device Mode IN Endpoints Including Control Endpoints (INEps)</description>
4798 <description>1 IN Endpoint</description>
4803 <description>2 IN Endpoints</description>
4808 <description>3 IN Endpoints</description>
4813 <description>4 IN Endpoints</description>
4818 <description>5 IN Endpoints</description>
4823 <description>6 IN Endpoints</description>
4828 <description>7 IN Endpoints</description>
4833 <description>8 IN Endpoints</description>
4838 <description>9 IN Endpoints</description>
4843 <description>10 IN Endpoints</description>
4848 <description>11 IN Endpoints</description>
4853 <description>12 IN Endpoints</description>
4858 <description>13 IN Endpoints</description>
4863 <description>14 IN Endpoints</description>
4868 <description>15 IN Endpoints</description>
4873 <description>16 IN Endpoints</description>
4880 <description>Scatter/Gather DMA configuration</description>
4887 <description>Non-Scatter/Gather DMA configuration</description>
4892 <description>Scatter/Gather DMA configuration</description>
4899 <description>Scatter/Gather DMA configuration</description>
4906 <description>Non Dynamic configuration</description>
4911 <description>Dynamic configuration</description>
4920 <description>LPM Config Register</description>
4928 <description>LPM-Capable (LPMCap)</description>
4934 <description>LPM capability is not enabled</description>
4939 <description>LPM capability is enabled</description>
4946 … <description>Mode: Device only. LPM response programmed by application (AppL1Res)</description>
4952 …<description>The core responds with a NYET when an error is detected in either of the LPM token pa…
4957 … <description>The core responds with an ACK only on a successful LPM transaction</description>
4964 <description>Host-Initiated Resume Duration (HIRD)</description>
4970 <description>RemoteWakeEnable (bRemoteWake)</description>
4976 <description>Remote Wakeup is disabled</description>
4981 … <description>In Host or device mode, this field takes the value of remote wake up</description>
4988 <description>Enable utmi_sleep_n (EnblSlpM)</description>
4994 …<description>utmi_sleep_n assertion from the core is not transferred to the external PHY</descript…
4999 …<description>utmi_sleep_n assertion from the core is transferred to the external PHY when utmi_l1_…
5006 <description>BESL/HIRD Threshold (HIRD_Thres)</description>
5012 <description>LPM Response (CoreL1Res)</description>
5019 <description>ERROR : No handshake response</description>
5024 <description>STALL response</description>
5029 <description>NYET response</description>
5034 <description>ACK response</description>
5041 <description>Port Sleep Status (SlpSts)</description>
5048 … <description>In Host or Device mode, this bit indicates core is not in L1</description>
5053 …description>In Host mode, this bit indicates the core transitions to Sleep state as a successful L…
5060 <description>Sleep State Resume OK (L1ResumeOK)</description>
5067 … <description>The application/core cannot start Resume from Sleep state</description>
5072 <description>The application/core can start Resume from Sleep state</description>
5079 <description>LPM Channel Index</description>
5085 <description>Channel 0</description>
5090 <description>Channel 1</description>
5095 <description>Channel 2</description>
5100 <description>Channel 3</description>
5105 <description>Channel 4</description>
5110 <description>Channel 5</description>
5115 <description>Channel 6</description>
5120 <description>Channel 7</description>
5125 <description>Channel 8</description>
5130 <description>Channel 9</description>
5135 <description>Channel 10</description>
5140 <description>Channel 11</description>
5145 <description>Channel 12</description>
5150 <description>Channel 13</description>
5155 <description>Channel 14</description>
5160 <description>Channel15</description>
5167 <description>LPM Retry Count (LPM_Retry_Cnt)</description>
5173 <description>Zero LPM retries</description>
5178 <description>One LPM retry</description>
5183 <description>Two LPM retries</description>
5188 <description>Three LPM retries</description>
5193 <description>Four LPM retries</description>
5198 <description>Five LPM retries</description>
5203 <description>Six LPM retries</description>
5208 <description>Seven LPM retries</description>
5215 <description>Send LPM Transaction (SndLPM)</description>
5221 …<description>In host-only mode: Received the response from the device for the LPM transaction</des…
5226 …<description>In host-only mode: Sending LPM transaction containing EXT and LPM tokens</description>
5233 <description>LPM Retry Count Status (LPM_RetryCnt_Sts)</description>
5240 <description>Zero LPM retries remaining</description>
5245 <description>One LPM retry remaining</description>
5250 <description>Two LPM retries remaining</description>
5255 <description>Three LPM retries remaining</description>
5260 <description>Four LPM retries remaining</description>
5265 <description>Five LPM retries remaining</description>
5270 <description>Six LPM retries remaining</description>
5275 <description>Seven LPM retries remaining</description>
5282 <description>LPM Enable BESL (LPM_EnBESL)</description>
5288 <description>BESL is disabled</description>
5293 <description>BESL is enabled as defined in LPM Errata</description>
5300 <description>LPM Restore Sleep Status (LPM_RestoreSlpSts)</description>
5306 …<description>Puts the core in Shallow Sleep mode based on the BESL value from the Host</descriptio…
5311 … <description>Puts the core in Deep Sleep mode based on the BESL value from the Host</description>
5320 <description>Global Power Down Register</description>
5328 <description>PMU Interrupt Select (PMUIntSel)</description>
5334 <description>Internal DWC_otg_core interrupt is selected</description>
5339 <description>External DWC_otg_pmu interrupt is selected</description>
5346 <description>PMU Active (PMUActv)</description>
5352 <description>Disable PMU module</description>
5357 <description>Enable PMU module</description>
5364 <description>Restore</description>
5370 <description>The controller in normal mode of operation</description>
5375 <description>The controller in Restore mode</description>
5382 <description>Power Down Clamp (PwrDnClmp)</description>
5388 <description>Disable PMU power clamp</description>
5393 <description>Enable PMU power clamp</description>
5400 <description>Power Down ResetN (PwrDnRst_n)</description>
5406 <description>Reset the controller</description>
5411 <description>The controller is in normal operation</description>
5418 <description>Power Down Switch (PwrDnSwtch)</description>
5424 <description>The controller is in ON state</description>
5429 <description>The controller is in OFF state</description>
5436 <description>DisableVBUS</description>
5442 …<description>Host mode:HPRT0.PrtPwr was not programmed to 0, and in Device mode:Session Valid</des…
5447 …<description>Host mode:HPRT0.PrtPwr was programmed to 0 and in Device mode:Session End</descriptio…
5454 <description>Line State Change (LnStsChng)</description>
5460 <description>No LineState change on USB</description>
5465 <description>LineState change on USB</description>
5472 <description>LineStageChangeMsk</description>
5478 <description>No LineStateChange Interrupt Mask</description>
5483 <description>Mask for LineStateChange Interrupt</description>
5490 <description>ResetDetected</description>
5496 <description>Reset not detected</description>
5501 <description>Reset detected</description>
5508 <description>ResetDetMsk</description>
5514 <description>No ResetDetect Interrupt Mask</description>
5519 <description>Mask for ResetDetect Interrupt</description>
5526 <description>DisconnectDetect</description>
5532 <description>Disconnect not detected</description>
5537 <description>Disconnect detected</description>
5544 <description>DisconnectDetectMsk</description>
5550 <description>No DisconnectDetect Interrupt Mask</description>
5555 <description>Mask for DisconnectDetect Interrupt</description>
5562 <description>ConnectDet</description>
5568 <description>Connect not detected</description>
5573 <description>Connect detected</description>
5580 <description>ConnDetMsk</description>
5586 <description>No ConnectDet Interrupt Mask</description>
5591 <description>Mask for ConnectDet Interrupt</description>
5598 <description>SRPDetect</description>
5604 <description>SRP not detected</description>
5609 <description>SRP detected</description>
5616 <description>SRPDetectMsk</description>
5622 <description>No SRPDetect Interrupt Mask</description>
5627 <description>Mask for SRPDetect Interrupt</description>
5634 <description>Status Change Interrupt (StsChngInt)</description>
5640 <description>No Status change</description>
5645 <description>Status change detected</description>
5652 <description>StsChngIntMsk</description>
5658 <description>No Status Change Interrupt Mask</description>
5663 <description>Mask for Status Change Interrupt</description>
5670 <description>LineState</description>
5677 <description>Linestate on USB: DM = 0, DP = 0</description>
5682 <description>Linestate on USB: DM = 0, DP = 1</description>
5687 <description>Linestate on USB: DM = 1, DP = 0</description>
5692 <description>Linestate on USB: Not-defined</description>
5699 …description>This bit indicates the status of the signal IDDIG. The application must read this bit …
5706 <description>Host Mode</description>
5711 <description>Device Mode</description>
5718 <description>B Session Valid (BSessVld)</description>
5725 <description>B_Valid is 0</description>
5730 <description>B_Valid is 1</description>
5737 <description>MultValIdBC</description>
5744 <description>OTG device as B-device</description>
5749 <description>OTG device as B-device, can connect</description>
5754 <description>OTG device as B-device, cannot connect</description>
5759 <description>OTG device as A-device</description>
5764 <description>ID_OTG pin is grounded</description>
5769 <description>OTG device as A-device, RID_A=1 and RID_GND=1</description>
5774 <description>ID pull down when ID_OTG is floating</description>
5779 … <description>OTG device as B-device, can connect, RID_C=1 and RID_FLOAT=1</description>
5784 … <description>OTG device as B-device, cannot connect, RID_B=1 and RID_FLOAT=1</description>
5789 <description>OTG device as A-device</description>
5798 <description>Global DFIFO Configuration Register</description>
5806 <description>GDFIFOCfg</description>
5812 … <description>This field provides the start address of the EP info controller.</description>
5820 <description>Interrupt Mask Register 2</description>
5835 <description>Interrupt Register 2</description>
5850 <description>Host Periodic Transmit FIFO Size Register</description>
5858 <description>Host Periodic TxFIFO Start Address (PTxFStAddr)</description>
5864 <description>Host Periodic TxFIFO Depth (PTxFSize)</description>
5874 … <description>Description collection: Device IN Endpoint Transmit FIFO Size Register</description>
5882 … <description>IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr)</description>
5888 <description>IN Endpoint TxFIFO Depth (INEPnTxFDep)</description>
5896 <description>Host Configuration Register</description>
5904 <description>FS/LS PHY Clock Select (FSLSPclkSel)</description>
5910 <description>PHY clock is running at 30/60 MHz</description>
5915 <description>PHY clock is running at 48 MHz</description>
5920 <description>PHY clock is running at 6 MHz</description>
5927 <description>FS- and LS-Only Support (FSLSSupp)</description>
5933 … <description>HS/FS/LS, based on the maximum speed supported by the connected device</description>
5938 <description>FS/LS-only, even if the connected device can support HS</description>
5945 <description>Enable 32 KHz Suspend mode (Ena32KHzS)</description>
5951 <description>32 KHz Suspend mode disabled</description>
5956 <description>32 KHz Suspend mode enabled</description>
5963 <description>Resume Validation Period (ResValid)</description>
5969 <description>Mode Change Ready Timer Enable (ModeChTimEn)</description>
5975 …description>The Host core waits for either 200 PHY clock cycles or a linestate of SE0 at the end o…
5980 …<description>The Host core waits only for a linestate of SE0 at the end of resume to change the op…
5989 <description>Host Frame Interval Register</description>
5997 <description>Frame Interval (FrInt)</description>
6003 <description>Reload Control (HFIRRldCtrl)</description>
6009 <description>The HFIR cannot be reloaded dynamically</description>
6014 <description>The HFIR can be dynamically reloaded during runtime</description>
6023 <description>Host Frame Number/Frame Time Remaining Register</description>
6031 <description>Frame Number (FrNum)</description>
6038 <description>No SOF is transmitted</description>
6043 <description>SOF is transmitted</description>
6050 <description>Frame Time Remaining (FrRem)</description>
6059 <description>Host All Channels Interrupt Register</description>
6073 <description>Not active</description>
6078 <description>Host Channel Interrupt</description>
6087 <description>Host All Channels Interrupt Mask Register</description>
6095 <description>Channel Interrupt Mask (HAINTMsk)</description>
6101 <description>Unmask Channel interrupt</description>
6106 <description>Mask Channel interrupt</description>
6115 <description>Host Port Control and Status Register</description>
6123 <description>Port Connect Status (PrtConnSts)</description>
6130 <description>No device is attached to the port</description>
6135 <description>A device is attached to the port</description>
6142 <description>Port Connect Detected (PrtConnDet)</description>
6148 <description>No device connection detected</description>
6153 <description>Device connection detected</description>
6160 <description>Port Enable (PrtEna)</description>
6166 <description>Port disabled</description>
6171 <description>Port enabled</description>
6178 <description>Port Enable/Disable Change (PrtEnChng)</description>
6184 <description>Port Enable bit 2 has not changed</description>
6189 <description>Port Enable bit 2 changed</description>
6196 <description>Port Overcurrent Active (PrtOvrCurrAct)</description>
6203 <description>No overcurrent condition</description>
6208 <description>Overcurrent condition</description>
6215 <description>Port Overcurrent Change (PrtOvrCurrChng)</description>
6221 <description>Status of port overcurrent status is not changed</description>
6226 <description>Status of port overcurrent changed</description>
6233 <description>Port Resume (PrtRes)</description>
6239 <description>No resume driven</description>
6244 <description>Resume driven</description>
6251 <description>Port Suspend (PrtSusp)</description>
6257 <description>Port not in Suspend mode</description>
6262 <description>Port in Suspend mode</description>
6269 <description>Port Reset (PrtRst)</description>
6275 <description>Port not in reset</description>
6280 <description>Port in reset</description>
6287 <description>Port Line Status (PrtLnSts)</description>
6294 <description>Logic level of D+</description>
6299 <description>Logic level of D-</description>
6306 <description>Port Power (PrtPwr)</description>
6312 <description>Power off</description>
6317 <description>Power on</description>
6324 <description>Port Test Control (PrtTstCtl)</description>
6330 <description>Test mode disabled</description>
6335 <description>Test_J mode</description>
6340 <description>Test_K mode</description>
6345 <description>Test_SE0_NAK mode</description>
6350 <description>Test_Packet mode</description>
6355 <description>Test_force_Enable</description>
6362 <description>Port Speed (PrtSpd)</description>
6369 <description>High speed</description>
6374 <description>Full speed</description>
6379 <description>Low speed</description>
6390 <description>Unspecified</description>
6396 <description>Description cluster: Host Channel Characteristics Register</description>
6404 <description>Maximum Packet Size (MPS)</description>
6410 <description>Endpoint Number (EPNum)</description>
6416 <description>End point 0</description>
6421 <description>End point 1</description>
6426 <description>End point 2</description>
6431 <description>End point 3</description>
6436 <description>End point 4</description>
6441 <description>End point 5</description>
6446 <description>End point 6</description>
6451 <description>End point 7</description>
6456 <description>End point 8</description>
6461 <description>End point 9</description>
6466 <description>End point 10</description>
6471 <description>End point 11</description>
6476 <description>End point 12</description>
6481 <description>End point 13</description>
6486 <description>End point 14</description>
6491 <description>End point 15</description>
6498 <description>Endpoint Direction (EPDir)</description>
6504 <description>OUT Direction</description>
6509 <description>IN Direction</description>
6516 <description>Low-Speed Device (LSpdDev)</description>
6522 <description>Not Communicating with low speed device</description>
6527 <description>Communicating with low speed device</description>
6534 <description>Endpoint Type (EPType)</description>
6540 <description>Control</description>
6545 <description>Isochronous</description>
6550 <description>Bulk</description>
6555 <description>Interrupt</description>
6562 <description>Multi Count (MC) / Error Count (EC)</description>
6568 <description>1 transaction</description>
6573 … <description>2 transactions to be issued for this endpoint per microframe</description>
6578 … <description>3 transactions to be issued for this endpoint per microframe</description>
6585 <description>Device Address (DevAddr)</description>
6591 <description>Odd Frame (OddFrm)</description>
6597 <description>Even Frame Transfer</description>
6602 <description>Odd Frame Transfer</description>
6609 <description>Channel Disable (ChDis)</description>
6615 <description>Transmit/Recieve normal</description>
6620 <description>Stop transmitting/receiving data on channel</description>
6627 <description>Channel Enable (ChEna)</description>
6633 …description>If Scatter/Gather mode is enabled, indicates that the descriptor structure is not yet …
6638 …description>If Scatter/Gather mode is enabled, indicates that the descriptor structure and data bu…
6647 <description>Description cluster: Host Channel Interrupt Register</description>
6655 <description>Transfer Completed (XferCompl)</description>
6661 <description>Transfer in progress or No Active Transfer</description>
6666 <description>Transfer completed normally without any errors</description>
6673 <description>Channel Halted (ChHltd)</description>
6679 <description>Channel not halted</description>
6684 <description>Channel Halted</description>
6691 <description>AHB Error (AHBErr)</description>
6697 <description>No AHB error</description>
6702 <description>AHB error during AHB read/write</description>
6709 <description>STALL Response Received Interrupt (STALL)</description>
6715 <description>No Stall Response Received Interrupt</description>
6720 <description>Stall Response Received Interrupt</description>
6727 <description>NAK Response Received Interrupt (NAK)</description>
6733 <description>No NAK Response Received Interrupt</description>
6738 <description>NAK Response Received Interrupt</description>
6745 <description>ACK Response Received/Transmitted Interrupt (ACK)</description>
6751 <description>No ACK Response Received or Transmitted Interrupt</description>
6756 <description>ACK Response Received or Transmitted Interrup</description>
6763 <description>NYET Response Received Interrupt (NYET)</description>
6769 <description>No NYET Response Received Interrupt</description>
6774 <description>NYET Response Received Interrupt</description>
6781 <description>Transaction Error (XactErr)</description>
6787 <description>No Transaction Error</description>
6792 <description>Transaction Error</description>
6799 <description>Babble Error (BblErr)</description>
6805 <description>No Babble Error</description>
6810 <description>Babble Error</description>
6817 <description>Frame Overrun (FrmOvrun).</description>
6823 <description>No Frame Overrun</description>
6828 <description>Frame Overrun</description>
6840 <description>No Data Toggle Error</description>
6845 <description>Data Toggle Error</description>
6854 <description>Description cluster: Host Channel Interrupt Mask Register</description>
6867 <description>Transfer Completed Mask</description>
6872 <description>No Transfer Completed Mask</description>
6884 <description>Channel Halted Mask</description>
6889 <description>No Channel Halted Mask</description>
6901 <description>AHB Error Mask</description>
6906 <description>No AHB Error Mask</description>
6918 <description>Mask STALL Response Received Interrupt</description>
6923 <description>No STALL Response Received Interrupt Mask</description>
6935 <description>Mask NAK Response Received Interrupt</description>
6940 <description>No NAK Response Received Interrupt Mask</description>
6952 <description>Mask ACK Response Received/Transmitted Interrupt</description>
6957 <description>No ACK Response Received/Transmitted Interrupt Mask</description>
6969 <description>Mask NYET Response Received Interrupt</description>
6974 <description>No NYET Response Received Interrupt Mask</description>
6986 <description>Mask Transaction Error</description>
6991 <description>No Transaction Error Mask</description>
7003 <description>Mask Babble Error</description>
7008 <description>No Babble Error Mask</description>
7020 <description>Mask Overrun Mask</description>
7025 <description>No Frame Overrun Mask</description>
7037 <description>Mask Data Toggle Error</description>
7042 <description>No Data Toggle Error Mask</description>
7051 <description>Description cluster: Host Channel Transfer Size Register</description>
7059 <description>Non-Scatter/Gather DMA Mode:</description>
7065 <description>Non-Scatter/Gather DMA Mode:</description>
7071 <description>PID (Pid)</description>
7077 <description>DATA0</description>
7082 <description>DATA2</description>
7087 <description>DATA1</description>
7092 <description>MDATA (non-control)/SETUP (control)</description>
7099 <description>Do Ping (DoPng)</description>
7105 <description>No ping protocol</description>
7110 <description>Ping protocol</description>
7119 <description>Description cluster: Host Channel DMA Address Register</description>
7127 <description>In Buffer DMA Mode:</description>
7136 <description>Device Configuration Register</description>
7144 <description>Device Speed (DevSpd)</description>
7150 <description>High speed USB 2.0 PHY clock is 30 MHz or 60 MHz</description>
7155 <description>Full speed USB 2.0 PHY clock is 30 MHz or 60 MHz</description>
7160 <description>Low speed USB 1.1 transceiver clock is 6 MHz</description>
7165 <description>Full speed USB 1.1 transceiver clock is 48 MHz</description>
7172 <description>Non-Zero-Length Status OUT Handshake (NZStsOUTHShk)</description>
7178 …description>Send the received OUT packet to the application (zero-length or non-zero length) and s…
7183 …<description>Send a STALL handshake on a nonzero-length status OUT transaction and do not send the…
7190 <description>Enable 32 KHz Suspend mode (Ena32KHzSusp)</description>
7196 <description>USB 1.1 Full-Speed Serial Transceiver not selected</description>
7201 … <description>USB 1.1 Full-Speed Serial Transceiver Interface selected</description>
7208 <description>Device Address (DevAddr)</description>
7214 <description>Periodic Frame Interval (PerFrInt)</description>
7220 <description>80 percent of the (micro)Frame interval</description>
7225 <description>85 percent of the (micro)Frame interval</description>
7230 <description>90 percent of the (micro)Frame interval</description>
7235 <description>95 percent of the (micro)Frame interval</description>
7242 <description>XCVRDLY</description>
7248 … <description>No delay between xcvr_sel and txvalid during Device chirp</description>
7253 … <description>Enable delay between xcvr_sel and txvalid during Device chirp</description>
7260 <description>Erratic Error Interrupt Mask</description>
7266 <description>Early suspend interrupt is generated on erratic error</description>
7271 <description>Mask early suspend interrupt on erratic error</description>
7278 <description>Worst-Case Inter-Packet Gap ISOC OUT Support (ipgisocSupt)</description>
7284 … <description>Worst-Case Inter-Packet Gap ISOC OUT Support is disabled</description>
7289 <description>Worst-Case Inter-Packet Gap ISOC OUT Support is enabled</description>
7296 <description>Periodic Scheduling Interval (PerSchIntvl)</description>
7302 <description>25 percent of (micro)Frame</description>
7307 <description>50 percent of (micro)Frame</description>
7312 <description>75 percent of (micro)Frame</description>
7319 <description>Resume Validation Period (ResValid)</description>
7327 <description>Device Control Register</description>
7335 <description>Remote Wakeup Signaling (RmtWkUpSig)</description>
7341 <description>Core does not send Remote Wakeup Signaling</description>
7346 <description>Core sends Remote Wakeup Signaling</description>
7353 <description>Soft Disconnect (SftDiscon)</description>
7359 …<description>The core drives the phy_opmode_o signal on the UTMI+ to 2'b00, which generates a devi…
7364 …<description>The core drives the phy_opmode_o signal on the UTMI+ to 2'b01, which generates a devi…
7371 <description>Global Non-periodic IN NAK Status (GNPINNakSts)</description>
7378 …<description>A handshake is sent out based on the data availability in the transmit FIFO</descript…
7383 …<description>A NAK handshake is sent out on all non-periodic IN endpoints, irrespective of the dat…
7390 <description>Global OUT NAK Status (GOUTNakSts)</description>
7397 …<description>A handshake is sent based on the FIFO Status and the NAK and STALL bit settings.</des…
7402 …description>No data is written to the RxFIFO, irrespective of space availability. Sends a NAK hand…
7409 <description>Test Control (TstCtl)</description>
7415 <description>Test mode disabled</description>
7420 <description>Test_J mode</description>
7425 <description>Test_K mode</description>
7430 <description>Test_SE0_NAK mode</description>
7435 <description>Test_Packet mode</description>
7440 <description>Test_force_Enable</description>
7447 <description>Set Global Non-periodic IN NAK (SGNPInNak)</description>
7454 <description>Disable Global Non-periodic IN NAK</description>
7459 <description>Set Global Non-periodic IN NAK</description>
7466 <description>Clear Global Non-periodic IN NAK (CGNPInNak)</description>
7473 <description>Disable Global Non-periodic IN NAK</description>
7478 <description>Clear Global Non-periodic IN NAK</description>
7485 <description>Set Global OUT NAK (SGOUTNak)</description>
7492 <description>Disable Global OUT NAK</description>
7497 <description>Set Global OUT NAK</description>
7504 <description>Clear Global OUT NAK (CGOUTNak)</description>
7511 <description>Disable Clear Global OUT NAK</description>
7516 <description>Clear Global OUT NAK</description>
7523 <description>Power-On Programming Done (PWROnPrgDone)</description>
7529 <description>Power-On Programming not done</description>
7534 <description>Power-On Programming Done</description>
7541 … <description>Ignore Frame Number Feature for Isochronous Endpoints (IgnrFrmNum)</description>
7547 …description>Scatter/Gather DMA Mode: The core transmits the packets only in the frame number in wh…
7552 …description>Scatter/Gather DMA Mode: The core ignores the frame number, sending packets immediatel…
7559 <description>NAK on Babble Error (NakOnBble)</description>
7565 <description>Disable NAK on Babble Error</description>
7570 <description>NAK on Babble Error</description>
7577 <description>DeepSleepBESLReject</description>
7583 <description>Deep Sleep BESL Reject feature is disabled</description>
7588 <description>Deep Sleep BESL Reject feature is enabled</description>
7595 … <description>Service Interval based scheduling for Isochronous IN Endpoints</description>
7601 … <description>The controller behavior depends on DCTL.IgnrFrmNum field.</description>
7606 …<description>Scatter/Gather DMA Mode: The controller can transmit the packets in any frame of the …
7613 … <description>Disable the correction to OpMode/XcvrSel/TermSel on UTMI Interface.</description>
7619 …<description>Opmode, XcvrSel, TermSel are changed by the Device Controller after TxValid goes LOW …
7624 …<description>Opmode, XcvrSel, TermSel are changed by the Device Controller immediately on soft dis…
7631 <description>Disable the correction of TermSel on UTMI Interface.</description>
7637 …<description>Valid Combination of XcvrSel and TermSel is driven by the Device Controller.</descrip…
7642 …<description>Invalid Combination of XcvrSel and TermSel is driven by the Device Controller.</descr…
7651 <description>Device Status Register</description>
7659 <description>Suspend Status (SuspSts)</description>
7666 <description>No suspend state</description>
7671 <description>Suspend state</description>
7678 <description>Enumerated Speed (EnumSpd)</description>
7685 <description>High speed (PHY clock is running at 30 or 60 MHz)</description>
7690 <description>Full speed (PHY clock is running at 30 or 60 MHz)</description>
7695 <description>Low speed (PHY clock is running at 6 MHz)</description>
7700 <description>Full speed (PHY clock is running at 48 MHz)</description>
7707 <description>Erratic Error (ErrticErr)</description>
7714 <description>No Erratic Error</description>
7719 <description>Erratic Error</description>
7726 <description>Frame or Microframe Number of the Received SOF (SOFFN)</description>
7733 <description>Device Line Status (DevLnSts)</description>
7742 <description>Device IN Endpoint Common Interrupt Mask Register</description>
7750 <description>Transfer Completed Interrupt Mask (XferComplMsk)</description>
7756 <description>Mask Transfer Completed Interrupt</description>
7761 <description>No Transfer Completed Interrupt Mask</description>
7768 <description>Endpoint Disabled Interrupt Mask (EPDisbldMsk)</description>
7774 <description>Mask Endpoint Disabled Interrupt</description>
7779 <description>No Endpoint Disabled Interrupt Mask</description>
7786 <description>AHB Error Mask (AHBErrMsk)</description>
7792 <description>Mask AHB Error Interrupt</description>
7797 <description>No AHB Error Interrupt Mask</description>
7804 … <description>Timeout Condition Mask (TimeOUTMsk) (Non-isochronous endpoints)</description>
7810 <description>Mask Timeout Condition Interrupt</description>
7815 <description>No Timeout Condition Interrupt Mask</description>
7822 <description>IN Token Received When TxFIFO Empty Mask (INTknTXFEmpMsk)</description>
7828 <description>Mask IN Token Received When TxFIFO Empty Interrupt</description>
7833 <description>No IN Token Received When TxFIFO Empty Interrupt</description>
7840 <description>IN Token received with EP Mismatch Mask (INTknEPMisMsk)</description>
7846 <description>Mask IN Token received with EP Mismatch Interrupt</description>
7851 <description>No Mask IN Token received with EP Mismatch Interrupt</description>
7858 <description>IN Endpoint NAK Effective Mask (INEPNakEffMsk)</description>
7864 <description>Mask IN Endpoint NAK Effective Interrupt</description>
7869 <description>No IN Endpoint NAK Effective Interrupt Mask</description>
7876 <description>Fifo Underrun Mask (TxfifoUndrnMsk)</description>
7882 <description>Mask Fifo Underrun Interrupt</description>
7887 <description>No Fifo Underrun Interrupt Mask</description>
7894 <description>NAK interrupt Mask (NAKMsk)</description>
7900 <description>Mask NAK Interrupt</description>
7905 <description>No Mask NAK Interrupt</description>
7914 <description>Device OUT Endpoint Common Interrupt Mask Register</description>
7922 <description>Transfer Completed Interrupt Mask (XferComplMsk)</description>
7928 <description>Mask Transfer Completed Interrupt</description>
7933 <description>No Transfer Completed Interrupt Mask</description>
7940 <description>Endpoint Disabled Interrupt Mask (EPDisbldMsk)</description>
7946 <description>Mask Endpoint Disabled Interrupt</description>
7951 <description>No Endpoint Disabled Interrupt Mask</description>
7958 <description>AHB Error (AHBErrMsk)</description>
7964 <description>Mask AHB Error Interrupt</description>
7969 <description>No AHB Error Interrupt Mask</description>
7976 <description>SETUP Phase Done Mask (SetUPMsk)</description>
7982 <description>Mask SETUP Phase Done Interrupt</description>
7987 <description>No SETUP Phase Done Interrupt Mask</description>
7994 … <description>OUT Token Received when Endpoint Disabled Mask (OUTTknEPdisMsk)</description>
8000 … <description>Mask OUT Token Received when Endpoint Disabled Interrupt</description>
8005 … <description>No OUT Token Received when Endpoint Disabled Interrupt Mask</description>
8012 <description>Status Phase Received Mask (StsPhseRcvdMsk)</description>
8018 <description>Status Phase Received Mask</description>
8023 <description>No Status Phase Received Mask</description>
8030 <description>Back-to-Back SETUP Packets Received Mask (Back2BackSETup)</description>
8036 <description>Mask Back-to-Back SETUP Packets Received Interrupt</description>
8041 <description>No Back-to-Back SETUP Packets Received Interrupt Mask</description>
8048 <description>OUT Packet Error Mask (OutPktErrMsk)</description>
8054 <description>Mask OUT Packet Error Interrupt</description>
8059 <description>No OUT Packet Error Interrupt Mask</description>
8066 <description>Babble Error interrupt Mask (BbleErrMsk)</description>
8072 <description>Mask Babble Error Interrupt</description>
8077 <description>No Babble Error Interrupt Mask</description>
8084 <description>NAK interrupt Mask (NAKMsk)</description>
8090 <description>Mask NAK Interrupt</description>
8095 <description>No NAK Interrupt Mask</description>
8102 <description>NYET interrupt Mask (NYETMsk)</description>
8108 <description>Mask NYET Interrupt</description>
8113 <description>No NYET Interrupt Mask</description>
8122 <description>Device All Endpoints Interrupt Register</description>
8130 <description>IN Endpoint 0 Interrupt Bit</description>
8137 <description>No Interrupt</description>
8142 <description>Interrupt is active for IN EP0</description>
8149 <description>IN Endpoint 1 Interrupt Bit</description>
8156 <description>No Interrupt</description>
8161 <description>Interrupt is active for the IN EP</description>
8168 <description>IN Endpoint 2 Interrupt Bit</description>
8175 <description>No Interrupt</description>
8180 <description>Interrupt is active for the IN EP</description>
8187 <description>IN Endpoint 3 Interrupt Bit</description>
8194 <description>No Interrupt</description>
8199 <description>Interrupt is active for the IN EP</description>
8206 <description>IN Endpoint 4 Interrupt Bit</description>
8213 <description>No Interrupt</description>
8218 <description>Interrupt is active for the IN EP</description>
8225 <description>IN Endpoint 5 Interrupt Bit</description>
8232 <description>No Interrupt</description>
8237 <description>Interrupt is active for the IN EP</description>
8244 <description>IN Endpoint 6 Interrupt Bit</description>
8251 <description>No Interrupt</description>
8256 <description>Interrupt is active for the IN EP</description>
8263 <description>IN Endpoint 7 Interrupt Bit</description>
8270 <description>No Interrupt</description>
8275 <description>Interrupt is active for the IN EP</description>
8282 <description>IN Endpoint 8 Interrupt Bit</description>
8289 <description>No Interrupt</description>
8294 <description>Interrupt is active for the IN EP</description>
8301 <description>IN Endpoint 9 Interrupt Bit</description>
8308 <description>No Interrupt</description>
8313 <description>Interrupt is active for the IN EP</description>
8320 <description>IN Endpoint 10 Interrupt Bit</description>
8327 <description>No Interrupt</description>
8332 <description>Interrupt is active for the IN EP</description>
8339 <description>IN Endpoint 11 Interrupt Bit</description>
8346 <description>No Interrupt</description>
8351 <description>Interrupt is active for the IN EP</description>
8358 <description>OUT Endpoint 0 Interrupt Bit</description>
8365 <description>No Interrupt</description>
8370 <description>Interrupt is active for OUT EP0</description>
8377 <description>OUT Endpoint 1 Interrupt Bit</description>
8384 <description>No Interrupt</description>
8389 <description>Interrupt is active for the OUT EP</description>
8396 <description>OUT Endpoint 2 Interrupt Bit</description>
8403 <description>No Interrupt</description>
8408 <description>Interrupt is active for the OUT EP</description>
8415 <description>OUT Endpoint 3 Interrupt Bit</description>
8422 <description>No Interrupt</description>
8427 <description>Interrupt is active for the OUT EP</description>
8434 <description>OUT Endpoint 4 Interrupt Bit</description>
8441 <description>No Interrupt</description>
8446 <description>Interrupt is active for the OUT EP</description>
8453 <description>OUT Endpoint 5 Interrupt Bit</description>
8460 <description>No Interrupt</description>
8465 <description>Interrupt is active for the OUT EP</description>
8472 <description>OUT Endpoint 12 Interrupt Bit</description>
8479 <description>No Interrupt</description>
8484 <description>Interrupt is active for the OUT EP</description>
8491 <description>OUT Endpoint 13 Interrupt Bit</description>
8498 <description>No Interrupt</description>
8503 <description>Interrupt is active for the OUT EP</description>
8510 <description>OUT Endpoint 14 Interrupt Bit</description>
8517 <description>No Interrupt</description>
8522 <description>Interrupt is active for the OUT EP</description>
8529 <description>OUT Endpoint 15 Interrupt Bit</description>
8536 <description>No Interrupt</description>
8541 <description>Interrupt is active for the OUT EP</description>
8550 <description>Device All Endpoints Interrupt Mask Register</description>
8558 <description>IN Endpoint 0 Interrupt mask Bit</description>
8564 <description>Mask IN Endpoint 0 Interrupt</description>
8569 <description>No Interrupt mask</description>
8576 <description>IN Endpoint 1 Interrupt mask Bit</description>
8582 <description>Mask IN Endpoint Interrupt</description>
8587 <description>No Interrupt mask</description>
8594 <description>IN Endpoint 2 Interrupt mask Bit</description>
8600 <description>Mask IN Endpoint Interrupt</description>
8605 <description>No Interrupt mask</description>
8612 <description>IN Endpoint 3 Interrupt mask Bit</description>
8618 <description>Mask IN Endpoint Interrupt</description>
8623 <description>No Interrupt mask</description>
8630 <description>IN Endpoint 4 Interrupt mask Bit</description>
8636 <description>Mask IN Endpoint Interrupt</description>
8641 <description>No Interrupt mask</description>
8648 <description>IN Endpoint 5 Interrupt mask Bit</description>
8654 <description>Mask IN Endpoint Interrupt</description>
8659 <description>No Interrupt mask</description>
8666 <description>IN Endpoint 6 Interrupt mask Bit</description>
8672 <description>Mask IN Endpoint Interrupt</description>
8677 <description>No Interrupt mask</description>
8684 <description>IN Endpoint 7 Interrupt mask Bit</description>
8690 <description>Mask IN Endpoint Interrupt</description>
8695 <description>No Interrupt mask</description>
8702 <description>IN Endpoint 8 Interrupt mask Bit</description>
8708 <description>Mask IN Endpoint Interrupt</description>
8713 <description>No Interrupt mask</description>
8720 <description>IN Endpoint 9 Interrupt mask Bit</description>
8726 <description>Mask IN Endpoint Interrupt</description>
8731 <description>No Interrupt mask</description>
8738 <description>IN Endpoint 10 Interrupt mask Bit</description>
8744 <description>Mask IN Endpoint Interrupt</description>
8749 <description>No Interrupt mask</description>
8756 <description>IN Endpoint 11 Interrupt mask Bit</description>
8762 <description>Mask IN Endpoint Interrupt</description>
8767 <description>No Interrupt mask</description>
8774 <description>OUT Endpoint 0 Interrupt mask Bit</description>
8780 <description>Mask OUT Endpoint 0 Interrupt</description>
8785 <description>No Interrupt mask</description>
8792 <description>OUT Endpoint 1 Interrupt mask Bit</description>
8798 <description>Mask OUT Endpoint Interrupt</description>
8803 <description>No Interrupt mask</description>
8810 <description>OUT Endpoint 2 Interrupt mask Bit</description>
8816 <description>Mask OUT Endpoint Interrupt</description>
8821 <description>No Interrupt mask</description>
8828 <description>OUT Endpoint 3 Interrupt mask Bit</description>
8834 <description>Mask OUT Endpoint Interrupt</description>
8839 <description>No Interrupt mask</description>
8846 <description>OUT Endpoint 4 Interrupt mask Bit</description>
8852 <description>Mask OUT Endpoint Interrupt</description>
8857 <description>No Interrupt mask</description>
8864 <description>OUT Endpoint 5 Interrupt mask Bit</description>
8870 <description>Mask OUT Endpoint Interrupt</description>
8875 <description>No Interrupt mask</description>
8882 <description>OUT Endpoint 12 Interrupt mask Bit</description>
8888 <description>Mask OUT Endpoint Interrupt</description>
8893 <description>No Interrupt mask</description>
8900 <description>OUT Endpoint 13 Interrupt mask Bit</description>
8906 <description>Mask OUT Endpoint Interrupt</description>
8911 <description>No Interrupt mask</description>
8918 <description>OUT Endpoint 14 Interrupt mask Bit</description>
8924 <description>Mask OUT Endpoint Interrupt</description>
8929 <description>No Interrupt mask</description>
8936 <description>OUT Endpoint 15 Interrupt mask Bit</description>
8942 <description>Mask OUT Endpoint Interrupt</description>
8947 <description>No Interrupt mask</description>
8956 <description>Device VBUS Discharge Time Register</description>
8964 <description>Device VBUS Discharge Time (DVBUSDis)</description>
8972 <description>Device VBUS Pulsing Time Register</description>
8980 <description>Device VBUS Pulsing Time (DVBUSPulse)</description>
8988 <description>Device Threshold Control Register</description>
8996 <description>Non-ISO IN Endpoints Threshold Enable. (NonISOThrEn)</description>
9002 <description>No thresholding</description>
9007 <description>Enable thresholding for non-isochronous IN endpoints</description>
9019 <description>No thresholding</description>
9024 <description>Enables thresholding for isochronous IN endpoints</description>
9031 <description>Transmit Threshold Length (TxThrLen)</description>
9037 <description>AHB Threshold Ratio (AHBThrRatio)</description>
9043 <description>AHB threshold = MAC threshold</description>
9048 <description>AHB threshold = MAC threshold /2</description>
9053 <description>AHB threshold = MAC threshold /4</description>
9058 <description>AHB threshold = MAC threshold /8</description>
9065 <description>Receive Threshold Enable (RxThrEn)</description>
9071 <description>Disable thresholding</description>
9076 <description>Enable thresholding in the receive direction</description>
9083 <description>Receive Threshold Length (RxThrLen)</description>
9089 <description>Arbiter Parking Enable (ArbPrkEn)</description>
9095 <description>Disable DMA arbiter parking</description>
9100 <description>Enable DMA arbiter parking for IN endpoints</description>
9109 <description>Device IN Endpoint FIFO Empty Interrupt Mask Register</description>
9117 <description>IN EP Tx FIFO Empty Interrupt Mask Bits (InEpTxfEmpMsk)</description>
9123 <description>Mask IN EP0 Tx FIFO Empty Interrupt</description>
9128 <description>Mask IN EP1 Tx FIFO Empty Interrupt</description>
9133 <description>Mask IN EP2 Tx FIFO Empty Interrupt</description>
9138 <description>Mask IN EP3 Tx FIFO Empty Interrupt</description>
9143 <description>Mask IN EP4 Tx FIFO Empty Interrupt</description>
9148 <description>Mask IN EP5 Tx FIFO Empty Interrupt</description>
9153 <description>Mask IN EP6 Tx FIFO Empty Interrupt</description>
9158 <description>Mask IN EP7 Tx FIFO Empty Interrupt</description>
9163 <description>Mask IN EP8 Tx FIFO Empty Interrupt</description>
9168 <description>Mask IN EP9 Tx FIFO Empty Interrupt</description>
9173 <description>Mask IN EP10 Tx FIFO Empty Interrupt</description>
9178 <description>Mask IN EP11 Tx FIFO Empty Interrupt</description>
9183 <description>Mask IN EP12 Tx FIFO Empty Interrupt</description>
9188 <description>Mask IN EP13 Tx FIFO Empty Interrupt</description>
9193 <description>Mask IN EP14 Tx FIFO Empty Interrupt</description>
9198 <description>Mask IN EP15 Tx FIFO Empty Interrupt</description>
9207 <description>Device Control IN Endpoint 0 Control Register</description>
9215 <description>Maximum Packet Size (MPS)</description>
9221 <description>64 bytes</description>
9226 <description>32 bytes</description>
9231 <description>16 bytes</description>
9236 <description>8 bytes</description>
9243 <description>USB Active Endpoint (USBActEP)</description>
9250 <description>Control endpoint is always active</description>
9257 <description>NAK Status (NAKSts)</description>
9264 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
9269 … <description>The core is transmitting NAK handshakes on this endpoint</description>
9276 <description>Endpoint Type (EPType)</description>
9283 <description>Endpoint Control 0</description>
9290 <description>STALL Handshake (Stall)</description>
9296 <description>No Stall</description>
9301 <description>Stall Handshake</description>
9308 <description>TxFIFO Number (TxFNum)</description>
9314 <description>Tx FIFO 0</description>
9319 <description>Tx FIFO 1</description>
9324 <description>Tx FIFO 2</description>
9329 <description>Tx FIFO 3</description>
9334 <description>Tx FIFO 4</description>
9339 <description>Tx FIFO 5</description>
9344 <description>Tx FIFO 6</description>
9349 <description>Tx FIFO 7</description>
9354 <description>Tx FIFO 8</description>
9359 <description>Tx FIFO 9</description>
9364 <description>Tx FIFO 10</description>
9369 <description>Tx FIFO 11</description>
9374 <description>Tx FIFO 12</description>
9379 <description>Tx FIFO 13</description>
9384 <description>Tx FIFO 14</description>
9389 <description>Tx FIFO 15</description>
9402 <description>No action</description>
9407 <description>Clear NAK</description>
9420 <description>No action</description>
9425 <description>Set NAK</description>
9432 <description>Endpoint Disable (EPDis)</description>
9438 <description>No action</description>
9443 <description>Disabled Endpoint</description>
9450 <description>Endpoint Enable (EPEna)</description>
9456 <description>No action</description>
9461 <description>Enable Endpoint</description>
9470 <description>Device IN Endpoint 0 Interrupt Register</description>
9478 <description>Transfer Completed Interrupt (XferCompl)</description>
9484 <description>No Transfer Complete Interrupt</description>
9489 <description>Transfer Completed Interrupt</description>
9496 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
9502 <description>No Endpoint Disabled Interrupt</description>
9507 <description>Endpoint Disabled Interrupt</description>
9514 <description>AHB Error (AHBErr)</description>
9520 <description>No AHB Error Interrupt</description>
9525 <description>AHB Error interrupt</description>
9532 <description>Timeout Condition (TimeOUT)</description>
9538 <description>No Timeout interrupt</description>
9543 <description>Timeout interrupt</description>
9550 <description>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</description>
9556 <description>No IN Token Received when TxFIFO Empty interrupt</description>
9561 <description>IN Token Received when TxFIFO Empty Interrupt</description>
9568 <description>IN Token Received with EP Mismatch (INTknEPMis)</description>
9574 <description>No IN Token Received with EP Mismatch interrupt</description>
9579 <description>IN Token Received with EP Mismatch interrupt</description>
9586 <description>IN Endpoint NAK Effective (INEPNakEff)</description>
9592 <description>No IN Endpoint NAK Effective interrupt</description>
9597 <description>IN Endpoint NAK Effective interrupt</description>
9604 <description>Transmit FIFO Empty (TxFEmp)</description>
9611 <description>No Transmit FIFO Empty interrupt</description>
9616 <description>Transmit FIFO Empty interrupt</description>
9623 <description>Fifo Underrun (TxfifoUndrn)</description>
9629 <description>No Fifo Underrun interrupt</description>
9634 <description>Fifo Underrun interrupt</description>
9641 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
9647 <description>No BNA interrupt</description>
9652 <description>BNA interrupt</description>
9659 <description>Packet Drop Status (PktDrpSts)</description>
9665 <description>No interrupt</description>
9670 <description>Packet Drop Status</description>
9677 <description>NAK Interrupt (BbleErr)</description>
9683 <description>No interrupt</description>
9688 <description>BbleErr interrupt</description>
9695 <description>NAK Interrupt (NAKInterrupt)</description>
9701 <description>No interrupt</description>
9706 <description>NAK Interrupt</description>
9713 <description>NYET Interrupt (NYETIntrpt)</description>
9719 <description>No interrupt</description>
9724 <description>NYET Interrupt</description>
9733 <description>Device IN Endpoint 0 Transfer Size Register</description>
9741 <description>Transfer Size (XferSize)</description>
9747 <description>Packet Count (PktCnt)</description>
9755 <description>Device IN Endpoint 0 DMA Address Register</description>
9763 <description>DMAAddr</description>
9771 <description>Device IN Endpoint Transmit FIFO Status Register 0</description>
9779 <description>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</description>
9788 <description>Device Control IN Endpoint Control Register</description>
9796 <description>Maximum Packet Size (MPS)</description>
9802 <description>USB Active Endpoint (USBActEP)</description>
9808 <description>Not Active</description>
9813 <description>USB Active Endpoint</description>
9826 <description>DATA0 or Even Frame</description>
9831 <description>DATA1 or Odd Frame</description>
9838 <description>NAK Status (NAKSts)</description>
9845 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
9850 … <description>The core is transmitting NAK handshakes on this endpoint</description>
9857 <description>Endpoint Type (EPType)</description>
9863 <description>Control</description>
9868 <description>Isochronous</description>
9873 <description>Bulk</description>
9878 <description>Interrupt</description>
9885 <description>STALL Handshake (Stall)</description>
9891 <description>STALL All non-active tokens</description>
9896 <description>STALL All Active Tokens</description>
9903 <description>TxFIFO Number (TxFNum)</description>
9909 <description>Tx FIFO 0</description>
9914 <description>Tx FIFO 1</description>
9919 <description>Tx FIFO 2</description>
9924 <description>Tx FIFO 3</description>
9929 <description>Tx FIFO 4</description>
9934 <description>Tx FIFO 5</description>
9939 <description>Tx FIFO 6</description>
9944 <description>Tx FIFO 7</description>
9949 <description>Tx FIFO 8</description>
9954 <description>Tx FIFO 9</description>
9959 <description>Tx FIFO 10</description>
9964 <description>Tx FIFO 11</description>
9969 <description>Tx FIFO 12</description>
9974 <description>Tx FIFO 13</description>
9979 <description>Tx FIFO 14</description>
9984 <description>Tx FIFO 15</description>
9991 <description>Clear NAK (CNAK)</description>
9998 <description>No Clear NAK</description>
10003 <description>Clear NAK</description>
10010 <description>Set NAK (SNAK)</description>
10017 <description>No Set NAK</description>
10022 <description>Set NAK</description>
10029 <description>Set DATA0 PID (SetD0PID)</description>
10036 … <description>Disables Set DATA0 PID or Do not force Even (micro)Frame</description>
10041 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame</descript…
10048 <description>Set DATA1 PID (SetD1PID)</description>
10055 … <description>Disables Set DATA1 PID or Do not force Odd (micro)Frame</description>
10060 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame</descripti…
10067 <description>Endpoint Disable (EPDis)</description>
10073 <description>No Action</description>
10078 <description>Disable Endpoint</description>
10085 <description>Endpoint Enable (EPEna)</description>
10091 <description>No Action</description>
10096 <description>Enable Endpoint</description>
10105 <description>Device IN Endpoint Interrupt Register</description>
10113 <description>Transfer Completed Interrupt (XferCompl)</description>
10119 <description>No Transfer Complete Interrupt</description>
10124 <description>Transfer Complete Interrupt</description>
10131 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
10137 <description>No Endpoint Disabled Interrupt</description>
10142 <description>Endpoint Disabled Interrupt</description>
10149 <description>AHB Error (AHBErr)</description>
10155 <description>No AHB Error Interrupt</description>
10160 <description>AHB Error interrupt</description>
10167 <description>Timeout Condition (TimeOUT)</description>
10173 <description>No Timeout interrupt</description>
10178 <description>Timeout interrupt</description>
10185 <description>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</description>
10191 <description>No IN Token Received interrupt</description>
10196 <description>IN Token Received Interrupt</description>
10203 <description>IN Token Received with EP Mismatch (INTknEPMis)</description>
10209 <description>No IN Token Received with EP Mismatch interrupt</description>
10214 <description>IN Token Received with EP Mismatch interrupt</description>
10221 <description>IN Endpoint NAK Effective (INEPNakEff)</description>
10227 <description>No Endpoint NAK Effective interrupt</description>
10232 <description>IN Endpoint NAK Effective interrupt</description>
10239 <description>Transmit FIFO Empty (TxFEmp)</description>
10246 <description>No Transmit FIFO Empty interrupt</description>
10251 <description>Transmit FIFO Empty interrupt</description>
10258 <description>Fifo Underrun (TxfifoUndrn)</description>
10264 <description>No Tx FIFO Underrun interrupt</description>
10269 <description>TxFIFO Underrun interrupt</description>
10276 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
10282 <description>No BNA interrupt</description>
10287 <description>BNA interrupt</description>
10294 <description>Packet Drop Status (PktDrpSts)</description>
10300 <description>No interrupt</description>
10305 <description>Packet Drop Status interrupt</description>
10312 <description>NAK Interrupt (BbleErr)</description>
10318 <description>No interrupt</description>
10323 <description>BbleErr interrupt</description>
10330 <description>NAK Interrupt (NAKInterrupt)</description>
10336 <description>No NAK interrupt</description>
10341 <description>NAK Interrupt</description>
10348 <description>NYET Interrupt (NYETIntrpt)</description>
10354 <description>No NYET interrupt</description>
10359 <description>NYET Interrupt</description>
10368 <description>Device IN Endpoint Transfer Size Register</description>
10376 <description>Transfer Size (XferSize)</description>
10382 <description>Packet Count (PktCnt)</description>
10388 <description>MC</description>
10394 <description>1 packet</description>
10399 <description>2 packets</description>
10404 <description>3 packets</description>
10413 <description>Device IN Endpoint DMA Address Register</description>
10421 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
10429 <description>Device IN Endpoint Transmit FIFO Status Register</description>
10437 <description>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</description>
10446 <description>Device Control IN Endpoint Control Register</description>
10454 <description>Maximum Packet Size (MPS)</description>
10460 <description>USB Active Endpoint (USBActEP)</description>
10466 <description>Not Active</description>
10471 <description>USB Active Endpoint</description>
10484 <description>DATA0 or Even Frame</description>
10489 <description>DATA1 or Odd Frame</description>
10496 <description>NAK Status (NAKSts)</description>
10503 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
10508 … <description>The core is transmitting NAK handshakes on this endpoint</description>
10515 <description>Endpoint Type (EPType)</description>
10521 <description>Control</description>
10526 <description>Isochronous</description>
10531 <description>Bulk</description>
10536 <description>Interrupt</description>
10543 <description>STALL Handshake (Stall)</description>
10549 <description>STALL All non-active tokens</description>
10554 <description>STALL All Active Tokens</description>
10561 <description>TxFIFO Number (TxFNum)</description>
10567 <description>Tx FIFO 0</description>
10572 <description>Tx FIFO 1</description>
10577 <description>Tx FIFO 2</description>
10582 <description>Tx FIFO 3</description>
10587 <description>Tx FIFO 4</description>
10592 <description>Tx FIFO 5</description>
10597 <description>Tx FIFO 6</description>
10602 <description>Tx FIFO 7</description>
10607 <description>Tx FIFO 8</description>
10612 <description>Tx FIFO 9</description>
10617 <description>Tx FIFO 10</description>
10622 <description>Tx FIFO 11</description>
10627 <description>Tx FIFO 12</description>
10632 <description>Tx FIFO 13</description>
10637 <description>Tx FIFO 14</description>
10642 <description>Tx FIFO 15</description>
10649 <description>Clear NAK (CNAK)</description>
10656 <description>No Clear NAK</description>
10661 <description>Clear NAK</description>
10668 <description>Set NAK (SNAK)</description>
10675 <description>No Set NAK</description>
10680 <description>Set NAK</description>
10687 <description>Set DATA0 PID (SetD0PID)</description>
10694 … <description>Disables Set DATA0 PID or Do not force Even (micro)Frame</description>
10699 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame</descript…
10706 <description>Set DATA1 PID (SetD1PID)</description>
10713 … <description>Disables Set DATA1 PID or Do not force Odd (micro)Frame</description>
10718 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame</descripti…
10725 <description>Endpoint Disable (EPDis)</description>
10731 <description>No Action</description>
10736 <description>Disable Endpoint</description>
10743 <description>Endpoint Enable (EPEna)</description>
10749 <description>No Action</description>
10754 <description>Enable Endpoint</description>
10763 <description>Device IN Endpoint Interrupt Register</description>
10771 <description>Transfer Completed Interrupt (XferCompl)</description>
10777 <description>No Transfer Complete Interrupt</description>
10782 <description>Transfer Complete Interrupt</description>
10789 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
10795 <description>No Endpoint Disabled Interrupt</description>
10800 <description>Endpoint Disabled Interrupt</description>
10807 <description>AHB Error (AHBErr)</description>
10813 <description>No AHB Error Interrupt</description>
10818 <description>AHB Error interrupt</description>
10825 <description>Timeout Condition (TimeOUT)</description>
10831 <description>No Timeout interrupt</description>
10836 <description>Timeout interrupt</description>
10843 <description>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</description>
10849 <description>No IN Token Received interrupt</description>
10854 <description>IN Token Received Interrupt</description>
10861 <description>IN Token Received with EP Mismatch (INTknEPMis)</description>
10867 <description>No IN Token Received with EP Mismatch interrupt</description>
10872 <description>IN Token Received with EP Mismatch interrupt</description>
10879 <description>IN Endpoint NAK Effective (INEPNakEff)</description>
10885 <description>No Endpoint NAK Effective interrupt</description>
10890 <description>IN Endpoint NAK Effective interrupt</description>
10897 <description>Transmit FIFO Empty (TxFEmp)</description>
10904 <description>No Transmit FIFO Empty interrupt</description>
10909 <description>Transmit FIFO Empty interrupt</description>
10916 <description>Fifo Underrun (TxfifoUndrn)</description>
10922 <description>No Tx FIFO Underrun interrupt</description>
10927 <description>TxFIFO Underrun interrupt</description>
10934 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
10940 <description>No BNA interrupt</description>
10945 <description>BNA interrupt</description>
10952 <description>Packet Drop Status (PktDrpSts)</description>
10958 <description>No interrupt</description>
10963 <description>Packet Drop Status interrupt</description>
10970 <description>NAK Interrupt (BbleErr)</description>
10976 <description>No interrupt</description>
10981 <description>BbleErr interrupt</description>
10988 <description>NAK Interrupt (NAKInterrupt)</description>
10994 <description>No NAK interrupt</description>
10999 <description>NAK Interrupt</description>
11006 <description>NYET Interrupt (NYETIntrpt)</description>
11012 <description>No NYET interrupt</description>
11017 <description>NYET Interrupt</description>
11026 <description>Device IN Endpoint Transfer Size Register</description>
11034 <description>Transfer Size (XferSize)</description>
11040 <description>Packet Count (PktCnt)</description>
11046 <description>MC</description>
11052 <description>1 packet</description>
11057 <description>2 packets</description>
11062 <description>3 packets</description>
11071 <description>Device IN Endpoint DMA Address Register</description>
11079 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
11087 <description>Device IN Endpoint Transmit FIFO Status Register</description>
11095 <description>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</description>
11104 <description>Device Control IN Endpoint Control Register</description>
11112 <description>Maximum Packet Size (MPS)</description>
11118 <description>USB Active Endpoint (USBActEP)</description>
11124 <description>Not Active</description>
11129 <description>USB Active Endpoint</description>
11142 <description>DATA0 or Even Frame</description>
11147 <description>DATA1 or Odd Frame</description>
11154 <description>NAK Status (NAKSts)</description>
11161 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
11166 … <description>The core is transmitting NAK handshakes on this endpoint</description>
11173 <description>Endpoint Type (EPType)</description>
11179 <description>Control</description>
11184 <description>Isochronous</description>
11189 <description>Bulk</description>
11194 <description>Interrupt</description>
11201 <description>STALL Handshake (Stall)</description>
11207 <description>STALL All non-active tokens</description>
11212 <description>STALL All Active Tokens</description>
11219 <description>TxFIFO Number (TxFNum)</description>
11225 <description>Tx FIFO 0</description>
11230 <description>Tx FIFO 1</description>
11235 <description>Tx FIFO 2</description>
11240 <description>Tx FIFO 3</description>
11245 <description>Tx FIFO 4</description>
11250 <description>Tx FIFO 5</description>
11255 <description>Tx FIFO 6</description>
11260 <description>Tx FIFO 7</description>
11265 <description>Tx FIFO 8</description>
11270 <description>Tx FIFO 9</description>
11275 <description>Tx FIFO 10</description>
11280 <description>Tx FIFO 11</description>
11285 <description>Tx FIFO 12</description>
11290 <description>Tx FIFO 13</description>
11295 <description>Tx FIFO 14</description>
11300 <description>Tx FIFO 15</description>
11307 <description>Clear NAK (CNAK)</description>
11314 <description>No Clear NAK</description>
11319 <description>Clear NAK</description>
11326 <description>Set NAK (SNAK)</description>
11333 <description>No Set NAK</description>
11338 <description>Set NAK</description>
11345 <description>Set DATA0 PID (SetD0PID)</description>
11352 … <description>Disables Set DATA0 PID or Do not force Even (micro)Frame</description>
11357 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame</descript…
11364 <description>Set DATA1 PID (SetD1PID)</description>
11371 … <description>Disables Set DATA1 PID or Do not force Odd (micro)Frame</description>
11376 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame</descripti…
11383 <description>Endpoint Disable (EPDis)</description>
11389 <description>No Action</description>
11394 <description>Disable Endpoint</description>
11401 <description>Endpoint Enable (EPEna)</description>
11407 <description>No Action</description>
11412 <description>Enable Endpoint</description>
11421 <description>Device IN Endpoint Interrupt Register</description>
11429 <description>Transfer Completed Interrupt (XferCompl)</description>
11435 <description>No Transfer Complete Interrupt</description>
11440 <description>Transfer Complete Interrupt</description>
11447 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
11453 <description>No Endpoint Disabled Interrupt</description>
11458 <description>Endpoint Disabled Interrupt</description>
11465 <description>AHB Error (AHBErr)</description>
11471 <description>No AHB Error Interrupt</description>
11476 <description>AHB Error interrupt</description>
11483 <description>Timeout Condition (TimeOUT)</description>
11489 <description>No Timeout interrupt</description>
11494 <description>Timeout interrupt</description>
11501 <description>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</description>
11507 <description>No IN Token Received interrupt</description>
11512 <description>IN Token Received Interrupt</description>
11519 <description>IN Token Received with EP Mismatch (INTknEPMis)</description>
11525 <description>No IN Token Received with EP Mismatch interrupt</description>
11530 <description>IN Token Received with EP Mismatch interrupt</description>
11537 <description>IN Endpoint NAK Effective (INEPNakEff)</description>
11543 <description>No Endpoint NAK Effective interrupt</description>
11548 <description>IN Endpoint NAK Effective interrupt</description>
11555 <description>Transmit FIFO Empty (TxFEmp)</description>
11562 <description>No Transmit FIFO Empty interrupt</description>
11567 <description>Transmit FIFO Empty interrupt</description>
11574 <description>Fifo Underrun (TxfifoUndrn)</description>
11580 <description>No Tx FIFO Underrun interrupt</description>
11585 <description>TxFIFO Underrun interrupt</description>
11592 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
11598 <description>No BNA interrupt</description>
11603 <description>BNA interrupt</description>
11610 <description>Packet Drop Status (PktDrpSts)</description>
11616 <description>No interrupt</description>
11621 <description>Packet Drop Status interrupt</description>
11628 <description>NAK Interrupt (BbleErr)</description>
11634 <description>No interrupt</description>
11639 <description>BbleErr interrupt</description>
11646 <description>NAK Interrupt (NAKInterrupt)</description>
11652 <description>No NAK interrupt</description>
11657 <description>NAK Interrupt</description>
11664 <description>NYET Interrupt (NYETIntrpt)</description>
11670 <description>No NYET interrupt</description>
11675 <description>NYET Interrupt</description>
11684 <description>Device IN Endpoint Transfer Size Register</description>
11692 <description>Transfer Size (XferSize)</description>
11698 <description>Packet Count (PktCnt)</description>
11704 <description>MC</description>
11710 <description>1 packet</description>
11715 <description>2 packets</description>
11720 <description>3 packets</description>
11729 <description>Device IN Endpoint DMA Address Register</description>
11737 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
11745 <description>Device IN Endpoint Transmit FIFO Status Register</description>
11753 <description>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</description>
11762 <description>Device Control IN Endpoint Control Register</description>
11770 <description>Maximum Packet Size (MPS)</description>
11776 <description>USB Active Endpoint (USBActEP)</description>
11782 <description>Not Active</description>
11787 <description>USB Active Endpoint</description>
11800 <description>DATA0 or Even Frame</description>
11805 <description>DATA1 or Odd Frame</description>
11812 <description>NAK Status (NAKSts)</description>
11819 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
11824 … <description>The core is transmitting NAK handshakes on this endpoint</description>
11831 <description>Endpoint Type (EPType)</description>
11837 <description>Control</description>
11842 <description>Isochronous</description>
11847 <description>Bulk</description>
11852 <description>Interrupt</description>
11859 <description>STALL Handshake (Stall)</description>
11865 <description>STALL All non-active tokens</description>
11870 <description>STALL All Active Tokens</description>
11877 <description>TxFIFO Number (TxFNum)</description>
11883 <description>Tx FIFO 0</description>
11888 <description>Tx FIFO 1</description>
11893 <description>Tx FIFO 2</description>
11898 <description>Tx FIFO 3</description>
11903 <description>Tx FIFO 4</description>
11908 <description>Tx FIFO 5</description>
11913 <description>Tx FIFO 6</description>
11918 <description>Tx FIFO 7</description>
11923 <description>Tx FIFO 8</description>
11928 <description>Tx FIFO 9</description>
11933 <description>Tx FIFO 10</description>
11938 <description>Tx FIFO 11</description>
11943 <description>Tx FIFO 12</description>
11948 <description>Tx FIFO 13</description>
11953 <description>Tx FIFO 14</description>
11958 <description>Tx FIFO 15</description>
11965 <description>Clear NAK (CNAK)</description>
11972 <description>No Clear NAK</description>
11977 <description>Clear NAK</description>
11984 <description>Set NAK (SNAK)</description>
11991 <description>No Set NAK</description>
11996 <description>Set NAK</description>
12003 <description>Set DATA0 PID (SetD0PID)</description>
12010 … <description>Disables Set DATA0 PID or Do not force Even (micro)Frame</description>
12015 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame</descript…
12022 <description>Set DATA1 PID (SetD1PID)</description>
12029 … <description>Disables Set DATA1 PID or Do not force Odd (micro)Frame</description>
12034 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame</descripti…
12041 <description>Endpoint Disable (EPDis)</description>
12047 <description>No Action</description>
12052 <description>Disable Endpoint</description>
12059 <description>Endpoint Enable (EPEna)</description>
12065 <description>No Action</description>
12070 <description>Enable Endpoint</description>
12079 <description>Device IN Endpoint Interrupt Register</description>
12087 <description>Transfer Completed Interrupt (XferCompl)</description>
12093 <description>No Transfer Complete Interrupt</description>
12098 <description>Transfer Complete Interrupt</description>
12105 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
12111 <description>No Endpoint Disabled Interrupt</description>
12116 <description>Endpoint Disabled Interrupt</description>
12123 <description>AHB Error (AHBErr)</description>
12129 <description>No AHB Error Interrupt</description>
12134 <description>AHB Error interrupt</description>
12141 <description>Timeout Condition (TimeOUT)</description>
12147 <description>No Timeout interrupt</description>
12152 <description>Timeout interrupt</description>
12159 <description>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</description>
12165 <description>No IN Token Received interrupt</description>
12170 <description>IN Token Received Interrupt</description>
12177 <description>IN Token Received with EP Mismatch (INTknEPMis)</description>
12183 <description>No IN Token Received with EP Mismatch interrupt</description>
12188 <description>IN Token Received with EP Mismatch interrupt</description>
12195 <description>IN Endpoint NAK Effective (INEPNakEff)</description>
12201 <description>No Endpoint NAK Effective interrupt</description>
12206 <description>IN Endpoint NAK Effective interrupt</description>
12213 <description>Transmit FIFO Empty (TxFEmp)</description>
12220 <description>No Transmit FIFO Empty interrupt</description>
12225 <description>Transmit FIFO Empty interrupt</description>
12232 <description>Fifo Underrun (TxfifoUndrn)</description>
12238 <description>No Tx FIFO Underrun interrupt</description>
12243 <description>TxFIFO Underrun interrupt</description>
12250 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
12256 <description>No BNA interrupt</description>
12261 <description>BNA interrupt</description>
12268 <description>Packet Drop Status (PktDrpSts)</description>
12274 <description>No interrupt</description>
12279 <description>Packet Drop Status interrupt</description>
12286 <description>NAK Interrupt (BbleErr)</description>
12292 <description>No interrupt</description>
12297 <description>BbleErr interrupt</description>
12304 <description>NAK Interrupt (NAKInterrupt)</description>
12310 <description>No NAK interrupt</description>
12315 <description>NAK Interrupt</description>
12322 <description>NYET Interrupt (NYETIntrpt)</description>
12328 <description>No NYET interrupt</description>
12333 <description>NYET Interrupt</description>
12342 <description>Device IN Endpoint Transfer Size Register</description>
12350 <description>Transfer Size (XferSize)</description>
12356 <description>Packet Count (PktCnt)</description>
12362 <description>MC</description>
12368 <description>1 packet</description>
12373 <description>2 packets</description>
12378 <description>3 packets</description>
12387 <description>Device IN Endpoint DMA Address Register</description>
12395 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
12403 <description>Device IN Endpoint Transmit FIFO Status Register</description>
12411 <description>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</description>
12420 <description>Device Control IN Endpoint Control Register</description>
12428 <description>Maximum Packet Size (MPS)</description>
12434 <description>USB Active Endpoint (USBActEP)</description>
12440 <description>Not Active</description>
12445 <description>USB Active Endpoint</description>
12458 <description>DATA0 or Even Frame</description>
12463 <description>DATA1 or Odd Frame</description>
12470 <description>NAK Status (NAKSts)</description>
12477 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
12482 … <description>The core is transmitting NAK handshakes on this endpoint</description>
12489 <description>Endpoint Type (EPType)</description>
12495 <description>Control</description>
12500 <description>Isochronous</description>
12505 <description>Bulk</description>
12510 <description>Interrupt</description>
12517 <description>STALL Handshake (Stall)</description>
12523 <description>STALL All non-active tokens</description>
12528 <description>STALL All Active Tokens</description>
12535 <description>TxFIFO Number (TxFNum)</description>
12541 <description>Tx FIFO 0</description>
12546 <description>Tx FIFO 1</description>
12551 <description>Tx FIFO 2</description>
12556 <description>Tx FIFO 3</description>
12561 <description>Tx FIFO 4</description>
12566 <description>Tx FIFO 5</description>
12571 <description>Tx FIFO 6</description>
12576 <description>Tx FIFO 7</description>
12581 <description>Tx FIFO 8</description>
12586 <description>Tx FIFO 9</description>
12591 <description>Tx FIFO 10</description>
12596 <description>Tx FIFO 11</description>
12601 <description>Tx FIFO 12</description>
12606 <description>Tx FIFO 13</description>
12611 <description>Tx FIFO 14</description>
12616 <description>Tx FIFO 15</description>
12623 <description>Clear NAK (CNAK)</description>
12630 <description>No Clear NAK</description>
12635 <description>Clear NAK</description>
12642 <description>Set NAK (SNAK)</description>
12649 <description>No Set NAK</description>
12654 <description>Set NAK</description>
12661 <description>Set DATA0 PID (SetD0PID)</description>
12668 … <description>Disables Set DATA0 PID or Do not force Even (micro)Frame</description>
12673 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame</descript…
12680 <description>Set DATA1 PID (SetD1PID)</description>
12687 … <description>Disables Set DATA1 PID or Do not force Odd (micro)Frame</description>
12692 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame</descripti…
12699 <description>Endpoint Disable (EPDis)</description>
12705 <description>No Action</description>
12710 <description>Disable Endpoint</description>
12717 <description>Endpoint Enable (EPEna)</description>
12723 <description>No Action</description>
12728 <description>Enable Endpoint</description>
12737 <description>Device IN Endpoint Interrupt Register</description>
12745 <description>Transfer Completed Interrupt (XferCompl)</description>
12751 <description>No Transfer Complete Interrupt</description>
12756 <description>Transfer Complete Interrupt</description>
12763 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
12769 <description>No Endpoint Disabled Interrupt</description>
12774 <description>Endpoint Disabled Interrupt</description>
12781 <description>AHB Error (AHBErr)</description>
12787 <description>No AHB Error Interrupt</description>
12792 <description>AHB Error interrupt</description>
12799 <description>Timeout Condition (TimeOUT)</description>
12805 <description>No Timeout interrupt</description>
12810 <description>Timeout interrupt</description>
12817 <description>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</description>
12823 <description>No IN Token Received interrupt</description>
12828 <description>IN Token Received Interrupt</description>
12835 <description>IN Token Received with EP Mismatch (INTknEPMis)</description>
12841 <description>No IN Token Received with EP Mismatch interrupt</description>
12846 <description>IN Token Received with EP Mismatch interrupt</description>
12853 <description>IN Endpoint NAK Effective (INEPNakEff)</description>
12859 <description>No Endpoint NAK Effective interrupt</description>
12864 <description>IN Endpoint NAK Effective interrupt</description>
12871 <description>Transmit FIFO Empty (TxFEmp)</description>
12878 <description>No Transmit FIFO Empty interrupt</description>
12883 <description>Transmit FIFO Empty interrupt</description>
12890 <description>Fifo Underrun (TxfifoUndrn)</description>
12896 <description>No Tx FIFO Underrun interrupt</description>
12901 <description>TxFIFO Underrun interrupt</description>
12908 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
12914 <description>No BNA interrupt</description>
12919 <description>BNA interrupt</description>
12926 <description>Packet Drop Status (PktDrpSts)</description>
12932 <description>No interrupt</description>
12937 <description>Packet Drop Status interrupt</description>
12944 <description>NAK Interrupt (BbleErr)</description>
12950 <description>No interrupt</description>
12955 <description>BbleErr interrupt</description>
12962 <description>NAK Interrupt (NAKInterrupt)</description>
12968 <description>No NAK interrupt</description>
12973 <description>NAK Interrupt</description>
12980 <description>NYET Interrupt (NYETIntrpt)</description>
12986 <description>No NYET interrupt</description>
12991 <description>NYET Interrupt</description>
13000 <description>Device IN Endpoint Transfer Size Register</description>
13008 <description>Transfer Size (XferSize)</description>
13014 <description>Packet Count (PktCnt)</description>
13020 <description>MC</description>
13026 <description>1 packet</description>
13031 <description>2 packets</description>
13036 <description>3 packets</description>
13045 <description>Device IN Endpoint DMA Address Register</description>
13053 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
13061 <description>Device IN Endpoint Transmit FIFO Status Register</description>
13069 <description>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</description>
13078 <description>Device Control IN Endpoint Control Register</description>
13086 <description>Maximum Packet Size (MPS)</description>
13092 <description>USB Active Endpoint (USBActEP)</description>
13098 <description>Not Active</description>
13103 <description>USB Active Endpoint</description>
13116 <description>DATA0 or Even Frame</description>
13121 <description>DATA1 or Odd Frame</description>
13128 <description>NAK Status (NAKSts)</description>
13135 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
13140 … <description>The core is transmitting NAK handshakes on this endpoint</description>
13147 <description>Endpoint Type (EPType)</description>
13153 <description>Control</description>
13158 <description>Isochronous</description>
13163 <description>Bulk</description>
13168 <description>Interrupt</description>
13175 <description>STALL Handshake (Stall)</description>
13181 <description>STALL All non-active tokens</description>
13186 <description>STALL All Active Tokens</description>
13193 <description>TxFIFO Number (TxFNum)</description>
13199 <description>Tx FIFO 0</description>
13204 <description>Tx FIFO 1</description>
13209 <description>Tx FIFO 2</description>
13214 <description>Tx FIFO 3</description>
13219 <description>Tx FIFO 4</description>
13224 <description>Tx FIFO 5</description>
13229 <description>Tx FIFO 6</description>
13234 <description>Tx FIFO 7</description>
13239 <description>Tx FIFO 8</description>
13244 <description>Tx FIFO 9</description>
13249 <description>Tx FIFO 10</description>
13254 <description>Tx FIFO 11</description>
13259 <description>Tx FIFO 12</description>
13264 <description>Tx FIFO 13</description>
13269 <description>Tx FIFO 14</description>
13274 <description>Tx FIFO 15</description>
13281 <description>Clear NAK (CNAK)</description>
13288 <description>No Clear NAK</description>
13293 <description>Clear NAK</description>
13300 <description>Set NAK (SNAK)</description>
13307 <description>No Set NAK</description>
13312 <description>Set NAK</description>
13319 <description>Set DATA0 PID (SetD0PID)</description>
13326 … <description>Disables Set DATA0 PID or Do not force Even (micro)Frame</description>
13331 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame</descript…
13338 <description>Set DATA1 PID (SetD1PID)</description>
13345 … <description>Disables Set DATA1 PID or Do not force Odd (micro)Frame</description>
13350 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame</descripti…
13357 <description>Endpoint Disable (EPDis)</description>
13363 <description>No Action</description>
13368 <description>Disable Endpoint</description>
13375 <description>Endpoint Enable (EPEna)</description>
13381 <description>No Action</description>
13386 <description>Enable Endpoint</description>
13395 <description>Device IN Endpoint Interrupt Register</description>
13403 <description>Transfer Completed Interrupt (XferCompl)</description>
13409 <description>No Transfer Complete Interrupt</description>
13414 <description>Transfer Complete Interrupt</description>
13421 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
13427 <description>No Endpoint Disabled Interrupt</description>
13432 <description>Endpoint Disabled Interrupt</description>
13439 <description>AHB Error (AHBErr)</description>
13445 <description>No AHB Error Interrupt</description>
13450 <description>AHB Error interrupt</description>
13457 <description>Timeout Condition (TimeOUT)</description>
13463 <description>No Timeout interrupt</description>
13468 <description>Timeout interrupt</description>
13475 <description>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</description>
13481 <description>No IN Token Received interrupt</description>
13486 <description>IN Token Received Interrupt</description>
13493 <description>IN Token Received with EP Mismatch (INTknEPMis)</description>
13499 <description>No IN Token Received with EP Mismatch interrupt</description>
13504 <description>IN Token Received with EP Mismatch interrupt</description>
13511 <description>IN Endpoint NAK Effective (INEPNakEff)</description>
13517 <description>No Endpoint NAK Effective interrupt</description>
13522 <description>IN Endpoint NAK Effective interrupt</description>
13529 <description>Transmit FIFO Empty (TxFEmp)</description>
13536 <description>No Transmit FIFO Empty interrupt</description>
13541 <description>Transmit FIFO Empty interrupt</description>
13548 <description>Fifo Underrun (TxfifoUndrn)</description>
13554 <description>No Tx FIFO Underrun interrupt</description>
13559 <description>TxFIFO Underrun interrupt</description>
13566 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
13572 <description>No BNA interrupt</description>
13577 <description>BNA interrupt</description>
13584 <description>Packet Drop Status (PktDrpSts)</description>
13590 <description>No interrupt</description>
13595 <description>Packet Drop Status interrupt</description>
13602 <description>NAK Interrupt (BbleErr)</description>
13608 <description>No interrupt</description>
13613 <description>BbleErr interrupt</description>
13620 <description>NAK Interrupt (NAKInterrupt)</description>
13626 <description>No NAK interrupt</description>
13631 <description>NAK Interrupt</description>
13638 <description>NYET Interrupt (NYETIntrpt)</description>
13644 <description>No NYET interrupt</description>
13649 <description>NYET Interrupt</description>
13658 <description>Device IN Endpoint Transfer Size Register</description>
13666 <description>Transfer Size (XferSize)</description>
13672 <description>Packet Count (PktCnt)</description>
13678 <description>MC</description>
13684 <description>1 packet</description>
13689 <description>2 packets</description>
13694 <description>3 packets</description>
13703 <description>Device IN Endpoint DMA Address Register</description>
13711 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
13719 <description>Device IN Endpoint Transmit FIFO Status Register</description>
13727 <description>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</description>
13736 <description>Device Control IN Endpoint Control Register</description>
13744 <description>Maximum Packet Size (MPS)</description>
13750 <description>USB Active Endpoint (USBActEP)</description>
13756 <description>Not Active</description>
13761 <description>USB Active Endpoint</description>
13774 <description>DATA0 or Even Frame</description>
13779 <description>DATA1 or Odd Frame</description>
13786 <description>NAK Status (NAKSts)</description>
13793 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
13798 … <description>The core is transmitting NAK handshakes on this endpoint</description>
13805 <description>Endpoint Type (EPType)</description>
13811 <description>Control</description>
13816 <description>Isochronous</description>
13821 <description>Bulk</description>
13826 <description>Interrupt</description>
13833 <description>STALL Handshake (Stall)</description>
13839 <description>STALL All non-active tokens</description>
13844 <description>STALL All Active Tokens</description>
13851 <description>TxFIFO Number (TxFNum)</description>
13857 <description>Tx FIFO 0</description>
13862 <description>Tx FIFO 1</description>
13867 <description>Tx FIFO 2</description>
13872 <description>Tx FIFO 3</description>
13877 <description>Tx FIFO 4</description>
13882 <description>Tx FIFO 5</description>
13887 <description>Tx FIFO 6</description>
13892 <description>Tx FIFO 7</description>
13897 <description>Tx FIFO 8</description>
13902 <description>Tx FIFO 9</description>
13907 <description>Tx FIFO 10</description>
13912 <description>Tx FIFO 11</description>
13917 <description>Tx FIFO 12</description>
13922 <description>Tx FIFO 13</description>
13927 <description>Tx FIFO 14</description>
13932 <description>Tx FIFO 15</description>
13939 <description>Clear NAK (CNAK)</description>
13946 <description>No Clear NAK</description>
13951 <description>Clear NAK</description>
13958 <description>Set NAK (SNAK)</description>
13965 <description>No Set NAK</description>
13970 <description>Set NAK</description>
13977 <description>Set DATA0 PID (SetD0PID)</description>
13984 … <description>Disables Set DATA0 PID or Do not force Even (micro)Frame</description>
13989 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame</descript…
13996 <description>Set DATA1 PID (SetD1PID)</description>
14003 … <description>Disables Set DATA1 PID or Do not force Odd (micro)Frame</description>
14008 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame</descripti…
14015 <description>Endpoint Disable (EPDis)</description>
14021 <description>No Action</description>
14026 <description>Disable Endpoint</description>
14033 <description>Endpoint Enable (EPEna)</description>
14039 <description>No Action</description>
14044 <description>Enable Endpoint</description>
14053 <description>Device IN Endpoint Interrupt Register</description>
14061 <description>Transfer Completed Interrupt (XferCompl)</description>
14067 <description>No Transfer Complete Interrupt</description>
14072 <description>Transfer Complete Interrupt</description>
14079 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
14085 <description>No Endpoint Disabled Interrupt</description>
14090 <description>Endpoint Disabled Interrupt</description>
14097 <description>AHB Error (AHBErr)</description>
14103 <description>No AHB Error Interrupt</description>
14108 <description>AHB Error interrupt</description>
14115 <description>Timeout Condition (TimeOUT)</description>
14121 <description>No Timeout interrupt</description>
14126 <description>Timeout interrupt</description>
14133 <description>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</description>
14139 <description>No IN Token Received interrupt</description>
14144 <description>IN Token Received Interrupt</description>
14151 <description>IN Token Received with EP Mismatch (INTknEPMis)</description>
14157 <description>No IN Token Received with EP Mismatch interrupt</description>
14162 <description>IN Token Received with EP Mismatch interrupt</description>
14169 <description>IN Endpoint NAK Effective (INEPNakEff)</description>
14175 <description>No Endpoint NAK Effective interrupt</description>
14180 <description>IN Endpoint NAK Effective interrupt</description>
14187 <description>Transmit FIFO Empty (TxFEmp)</description>
14194 <description>No Transmit FIFO Empty interrupt</description>
14199 <description>Transmit FIFO Empty interrupt</description>
14206 <description>Fifo Underrun (TxfifoUndrn)</description>
14212 <description>No Tx FIFO Underrun interrupt</description>
14217 <description>TxFIFO Underrun interrupt</description>
14224 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
14230 <description>No BNA interrupt</description>
14235 <description>BNA interrupt</description>
14242 <description>Packet Drop Status (PktDrpSts)</description>
14248 <description>No interrupt</description>
14253 <description>Packet Drop Status interrupt</description>
14260 <description>NAK Interrupt (BbleErr)</description>
14266 <description>No interrupt</description>
14271 <description>BbleErr interrupt</description>
14278 <description>NAK Interrupt (NAKInterrupt)</description>
14284 <description>No NAK interrupt</description>
14289 <description>NAK Interrupt</description>
14296 <description>NYET Interrupt (NYETIntrpt)</description>
14302 <description>No NYET interrupt</description>
14307 <description>NYET Interrupt</description>
14316 <description>Device IN Endpoint Transfer Size Register</description>
14324 <description>Transfer Size (XferSize)</description>
14330 <description>Packet Count (PktCnt)</description>
14336 <description>MC</description>
14342 <description>1 packet</description>
14347 <description>2 packets</description>
14352 <description>3 packets</description>
14361 <description>Device IN Endpoint DMA Address Register</description>
14369 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
14377 <description>Device IN Endpoint Transmit FIFO Status Register</description>
14385 <description>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</description>
14394 <description>Device Control IN Endpoint Control Register</description>
14402 <description>Maximum Packet Size (MPS)</description>
14408 <description>USB Active Endpoint (USBActEP)</description>
14414 <description>Not Active</description>
14419 <description>USB Active Endpoint</description>
14432 <description>DATA0 or Even Frame</description>
14437 <description>DATA1 or Odd Frame</description>
14444 <description>NAK Status (NAKSts)</description>
14451 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
14456 … <description>The core is transmitting NAK handshakes on this endpoint</description>
14463 <description>Endpoint Type (EPType)</description>
14469 <description>Control</description>
14474 <description>Isochronous</description>
14479 <description>Bulk</description>
14484 <description>Interrupt</description>
14491 <description>STALL Handshake (Stall)</description>
14497 <description>STALL All non-active tokens</description>
14502 <description>STALL All Active Tokens</description>
14509 <description>TxFIFO Number (TxFNum)</description>
14515 <description>Tx FIFO 0</description>
14520 <description>Tx FIFO 1</description>
14525 <description>Tx FIFO 2</description>
14530 <description>Tx FIFO 3</description>
14535 <description>Tx FIFO 4</description>
14540 <description>Tx FIFO 5</description>
14545 <description>Tx FIFO 6</description>
14550 <description>Tx FIFO 7</description>
14555 <description>Tx FIFO 8</description>
14560 <description>Tx FIFO 9</description>
14565 <description>Tx FIFO 10</description>
14570 <description>Tx FIFO 11</description>
14575 <description>Tx FIFO 12</description>
14580 <description>Tx FIFO 13</description>
14585 <description>Tx FIFO 14</description>
14590 <description>Tx FIFO 15</description>
14597 <description>Clear NAK (CNAK)</description>
14604 <description>No Clear NAK</description>
14609 <description>Clear NAK</description>
14616 <description>Set NAK (SNAK)</description>
14623 <description>No Set NAK</description>
14628 <description>Set NAK</description>
14635 <description>Set DATA0 PID (SetD0PID)</description>
14642 … <description>Disables Set DATA0 PID or Do not force Even (micro)Frame</description>
14647 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame</descript…
14654 <description>Set DATA1 PID (SetD1PID)</description>
14661 … <description>Disables Set DATA1 PID or Do not force Odd (micro)Frame</description>
14666 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame</descripti…
14673 <description>Endpoint Disable (EPDis)</description>
14679 <description>No Action</description>
14684 <description>Disable Endpoint</description>
14691 <description>Endpoint Enable (EPEna)</description>
14697 <description>No Action</description>
14702 <description>Enable Endpoint</description>
14711 <description>Device IN Endpoint Interrupt Register</description>
14719 <description>Transfer Completed Interrupt (XferCompl)</description>
14725 <description>No Transfer Complete Interrupt</description>
14730 <description>Transfer Complete Interrupt</description>
14737 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
14743 <description>No Endpoint Disabled Interrupt</description>
14748 <description>Endpoint Disabled Interrupt</description>
14755 <description>AHB Error (AHBErr)</description>
14761 <description>No AHB Error Interrupt</description>
14766 <description>AHB Error interrupt</description>
14773 <description>Timeout Condition (TimeOUT)</description>
14779 <description>No Timeout interrupt</description>
14784 <description>Timeout interrupt</description>
14791 <description>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</description>
14797 <description>No IN Token Received interrupt</description>
14802 <description>IN Token Received Interrupt</description>
14809 <description>IN Token Received with EP Mismatch (INTknEPMis)</description>
14815 <description>No IN Token Received with EP Mismatch interrupt</description>
14820 <description>IN Token Received with EP Mismatch interrupt</description>
14827 <description>IN Endpoint NAK Effective (INEPNakEff)</description>
14833 <description>No Endpoint NAK Effective interrupt</description>
14838 <description>IN Endpoint NAK Effective interrupt</description>
14845 <description>Transmit FIFO Empty (TxFEmp)</description>
14852 <description>No Transmit FIFO Empty interrupt</description>
14857 <description>Transmit FIFO Empty interrupt</description>
14864 <description>Fifo Underrun (TxfifoUndrn)</description>
14870 <description>No Tx FIFO Underrun interrupt</description>
14875 <description>TxFIFO Underrun interrupt</description>
14882 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
14888 <description>No BNA interrupt</description>
14893 <description>BNA interrupt</description>
14900 <description>Packet Drop Status (PktDrpSts)</description>
14906 <description>No interrupt</description>
14911 <description>Packet Drop Status interrupt</description>
14918 <description>NAK Interrupt (BbleErr)</description>
14924 <description>No interrupt</description>
14929 <description>BbleErr interrupt</description>
14936 <description>NAK Interrupt (NAKInterrupt)</description>
14942 <description>No NAK interrupt</description>
14947 <description>NAK Interrupt</description>
14954 <description>NYET Interrupt (NYETIntrpt)</description>
14960 <description>No NYET interrupt</description>
14965 <description>NYET Interrupt</description>
14974 <description>Device IN Endpoint Transfer Size Register</description>
14982 <description>Transfer Size (XferSize)</description>
14988 <description>Packet Count (PktCnt)</description>
14994 <description>MC</description>
15000 <description>1 packet</description>
15005 <description>2 packets</description>
15010 <description>3 packets</description>
15019 <description>Device IN Endpoint DMA Address Register</description>
15027 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
15035 <description>Device IN Endpoint Transmit FIFO Status Register</description>
15043 <description>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</description>
15052 <description>Device Control IN Endpoint Control Register</description>
15060 <description>Maximum Packet Size (MPS)</description>
15066 <description>USB Active Endpoint (USBActEP)</description>
15072 <description>Not Active</description>
15077 <description>USB Active Endpoint</description>
15090 <description>DATA0 or Even Frame</description>
15095 <description>DATA1 or Odd Frame</description>
15102 <description>NAK Status (NAKSts)</description>
15109 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
15114 … <description>The core is transmitting NAK handshakes on this endpoint</description>
15121 <description>Endpoint Type (EPType)</description>
15127 <description>Control</description>
15132 <description>Isochronous</description>
15137 <description>Bulk</description>
15142 <description>Interrupt</description>
15149 <description>STALL Handshake (Stall)</description>
15155 <description>STALL All non-active tokens</description>
15160 <description>STALL All Active Tokens</description>
15167 <description>TxFIFO Number (TxFNum)</description>
15173 <description>Tx FIFO 0</description>
15178 <description>Tx FIFO 1</description>
15183 <description>Tx FIFO 2</description>
15188 <description>Tx FIFO 3</description>
15193 <description>Tx FIFO 4</description>
15198 <description>Tx FIFO 5</description>
15203 <description>Tx FIFO 6</description>
15208 <description>Tx FIFO 7</description>
15213 <description>Tx FIFO 8</description>
15218 <description>Tx FIFO 9</description>
15223 <description>Tx FIFO 10</description>
15228 <description>Tx FIFO 11</description>
15233 <description>Tx FIFO 12</description>
15238 <description>Tx FIFO 13</description>
15243 <description>Tx FIFO 14</description>
15248 <description>Tx FIFO 15</description>
15255 <description>Clear NAK (CNAK)</description>
15262 <description>No Clear NAK</description>
15267 <description>Clear NAK</description>
15274 <description>Set NAK (SNAK)</description>
15281 <description>No Set NAK</description>
15286 <description>Set NAK</description>
15293 <description>Set DATA0 PID (SetD0PID)</description>
15300 … <description>Disables Set DATA0 PID or Do not force Even (micro)Frame</description>
15305 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame</descript…
15312 <description>Set DATA1 PID (SetD1PID)</description>
15319 … <description>Disables Set DATA1 PID or Do not force Odd (micro)Frame</description>
15324 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame</descripti…
15331 <description>Endpoint Disable (EPDis)</description>
15337 <description>No Action</description>
15342 <description>Disable Endpoint</description>
15349 <description>Endpoint Enable (EPEna)</description>
15355 <description>No Action</description>
15360 <description>Enable Endpoint</description>
15369 <description>Device IN Endpoint Interrupt Register</description>
15377 <description>Transfer Completed Interrupt (XferCompl)</description>
15383 <description>No Transfer Complete Interrupt</description>
15388 <description>Transfer Complete Interrupt</description>
15395 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
15401 <description>No Endpoint Disabled Interrupt</description>
15406 <description>Endpoint Disabled Interrupt</description>
15413 <description>AHB Error (AHBErr)</description>
15419 <description>No AHB Error Interrupt</description>
15424 <description>AHB Error interrupt</description>
15431 <description>Timeout Condition (TimeOUT)</description>
15437 <description>No Timeout interrupt</description>
15442 <description>Timeout interrupt</description>
15449 <description>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</description>
15455 <description>No IN Token Received interrupt</description>
15460 <description>IN Token Received Interrupt</description>
15467 <description>IN Token Received with EP Mismatch (INTknEPMis)</description>
15473 <description>No IN Token Received with EP Mismatch interrupt</description>
15478 <description>IN Token Received with EP Mismatch interrupt</description>
15485 <description>IN Endpoint NAK Effective (INEPNakEff)</description>
15491 <description>No Endpoint NAK Effective interrupt</description>
15496 <description>IN Endpoint NAK Effective interrupt</description>
15503 <description>Transmit FIFO Empty (TxFEmp)</description>
15510 <description>No Transmit FIFO Empty interrupt</description>
15515 <description>Transmit FIFO Empty interrupt</description>
15522 <description>Fifo Underrun (TxfifoUndrn)</description>
15528 <description>No Tx FIFO Underrun interrupt</description>
15533 <description>TxFIFO Underrun interrupt</description>
15540 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
15546 <description>No BNA interrupt</description>
15551 <description>BNA interrupt</description>
15558 <description>Packet Drop Status (PktDrpSts)</description>
15564 <description>No interrupt</description>
15569 <description>Packet Drop Status interrupt</description>
15576 <description>NAK Interrupt (BbleErr)</description>
15582 <description>No interrupt</description>
15587 <description>BbleErr interrupt</description>
15594 <description>NAK Interrupt (NAKInterrupt)</description>
15600 <description>No NAK interrupt</description>
15605 <description>NAK Interrupt</description>
15612 <description>NYET Interrupt (NYETIntrpt)</description>
15618 <description>No NYET interrupt</description>
15623 <description>NYET Interrupt</description>
15632 <description>Device IN Endpoint Transfer Size Register</description>
15640 <description>Transfer Size (XferSize)</description>
15646 <description>Packet Count (PktCnt)</description>
15652 <description>MC</description>
15658 <description>1 packet</description>
15663 <description>2 packets</description>
15668 <description>3 packets</description>
15677 <description>Device IN Endpoint DMA Address Register</description>
15685 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
15693 <description>Device IN Endpoint Transmit FIFO Status Register</description>
15701 <description>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</description>
15710 <description>Device Control IN Endpoint Control Register</description>
15718 <description>Maximum Packet Size (MPS)</description>
15724 <description>USB Active Endpoint (USBActEP)</description>
15730 <description>Not Active</description>
15735 <description>USB Active Endpoint</description>
15748 <description>DATA0 or Even Frame</description>
15753 <description>DATA1 or Odd Frame</description>
15760 <description>NAK Status (NAKSts)</description>
15767 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
15772 … <description>The core is transmitting NAK handshakes on this endpoint</description>
15779 <description>Endpoint Type (EPType)</description>
15785 <description>Control</description>
15790 <description>Isochronous</description>
15795 <description>Bulk</description>
15800 <description>Interrupt</description>
15807 <description>STALL Handshake (Stall)</description>
15813 <description>STALL All non-active tokens</description>
15818 <description>STALL All Active Tokens</description>
15825 <description>TxFIFO Number (TxFNum)</description>
15831 <description>Tx FIFO 0</description>
15836 <description>Tx FIFO 1</description>
15841 <description>Tx FIFO 2</description>
15846 <description>Tx FIFO 3</description>
15851 <description>Tx FIFO 4</description>
15856 <description>Tx FIFO 5</description>
15861 <description>Tx FIFO 6</description>
15866 <description>Tx FIFO 7</description>
15871 <description>Tx FIFO 8</description>
15876 <description>Tx FIFO 9</description>
15881 <description>Tx FIFO 10</description>
15886 <description>Tx FIFO 11</description>
15891 <description>Tx FIFO 12</description>
15896 <description>Tx FIFO 13</description>
15901 <description>Tx FIFO 14</description>
15906 <description>Tx FIFO 15</description>
15913 <description>Clear NAK (CNAK)</description>
15920 <description>No Clear NAK</description>
15925 <description>Clear NAK</description>
15932 <description>Set NAK (SNAK)</description>
15939 <description>No Set NAK</description>
15944 <description>Set NAK</description>
15951 <description>Set DATA0 PID (SetD0PID)</description>
15958 … <description>Disables Set DATA0 PID or Do not force Even (micro)Frame</description>
15963 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame</descript…
15970 <description>Set DATA1 PID (SetD1PID)</description>
15977 … <description>Disables Set DATA1 PID or Do not force Odd (micro)Frame</description>
15982 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame</descripti…
15989 <description>Endpoint Disable (EPDis)</description>
15995 <description>No Action</description>
16000 <description>Disable Endpoint</description>
16007 <description>Endpoint Enable (EPEna)</description>
16013 <description>No Action</description>
16018 <description>Enable Endpoint</description>
16027 <description>Device IN Endpoint Interrupt Register</description>
16035 <description>Transfer Completed Interrupt (XferCompl)</description>
16041 <description>No Transfer Complete Interrupt</description>
16046 <description>Transfer Complete Interrupt</description>
16053 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
16059 <description>No Endpoint Disabled Interrupt</description>
16064 <description>Endpoint Disabled Interrupt</description>
16071 <description>AHB Error (AHBErr)</description>
16077 <description>No AHB Error Interrupt</description>
16082 <description>AHB Error interrupt</description>
16089 <description>Timeout Condition (TimeOUT)</description>
16095 <description>No Timeout interrupt</description>
16100 <description>Timeout interrupt</description>
16107 <description>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</description>
16113 <description>No IN Token Received interrupt</description>
16118 <description>IN Token Received Interrupt</description>
16125 <description>IN Token Received with EP Mismatch (INTknEPMis)</description>
16131 <description>No IN Token Received with EP Mismatch interrupt</description>
16136 <description>IN Token Received with EP Mismatch interrupt</description>
16143 <description>IN Endpoint NAK Effective (INEPNakEff)</description>
16149 <description>No Endpoint NAK Effective interrupt</description>
16154 <description>IN Endpoint NAK Effective interrupt</description>
16161 <description>Transmit FIFO Empty (TxFEmp)</description>
16168 <description>No Transmit FIFO Empty interrupt</description>
16173 <description>Transmit FIFO Empty interrupt</description>
16180 <description>Fifo Underrun (TxfifoUndrn)</description>
16186 <description>No Tx FIFO Underrun interrupt</description>
16191 <description>TxFIFO Underrun interrupt</description>
16198 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
16204 <description>No BNA interrupt</description>
16209 <description>BNA interrupt</description>
16216 <description>Packet Drop Status (PktDrpSts)</description>
16222 <description>No interrupt</description>
16227 <description>Packet Drop Status interrupt</description>
16234 <description>NAK Interrupt (BbleErr)</description>
16240 <description>No interrupt</description>
16245 <description>BbleErr interrupt</description>
16252 <description>NAK Interrupt (NAKInterrupt)</description>
16258 <description>No NAK interrupt</description>
16263 <description>NAK Interrupt</description>
16270 <description>NYET Interrupt (NYETIntrpt)</description>
16276 <description>No NYET interrupt</description>
16281 <description>NYET Interrupt</description>
16290 <description>Device IN Endpoint Transfer Size Register</description>
16298 <description>Transfer Size (XferSize)</description>
16304 <description>Packet Count (PktCnt)</description>
16310 <description>MC</description>
16316 <description>1 packet</description>
16321 <description>2 packets</description>
16326 <description>3 packets</description>
16335 <description>Device IN Endpoint DMA Address Register</description>
16343 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
16351 <description>Device IN Endpoint Transmit FIFO Status Register</description>
16359 <description>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</description>
16368 <description>Device Control IN Endpoint Control Register</description>
16376 <description>Maximum Packet Size (MPS)</description>
16382 <description>USB Active Endpoint (USBActEP)</description>
16388 <description>Not Active</description>
16393 <description>USB Active Endpoint</description>
16406 <description>DATA0 or Even Frame</description>
16411 <description>DATA1 or Odd Frame</description>
16418 <description>NAK Status (NAKSts)</description>
16425 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
16430 … <description>The core is transmitting NAK handshakes on this endpoint</description>
16437 <description>Endpoint Type (EPType)</description>
16443 <description>Control</description>
16448 <description>Isochronous</description>
16453 <description>Bulk</description>
16458 <description>Interrupt</description>
16465 <description>STALL Handshake (Stall)</description>
16471 <description>STALL All non-active tokens</description>
16476 <description>STALL All Active Tokens</description>
16483 <description>TxFIFO Number (TxFNum)</description>
16489 <description>Tx FIFO 0</description>
16494 <description>Tx FIFO 1</description>
16499 <description>Tx FIFO 2</description>
16504 <description>Tx FIFO 3</description>
16509 <description>Tx FIFO 4</description>
16514 <description>Tx FIFO 5</description>
16519 <description>Tx FIFO 6</description>
16524 <description>Tx FIFO 7</description>
16529 <description>Tx FIFO 8</description>
16534 <description>Tx FIFO 9</description>
16539 <description>Tx FIFO 10</description>
16544 <description>Tx FIFO 11</description>
16549 <description>Tx FIFO 12</description>
16554 <description>Tx FIFO 13</description>
16559 <description>Tx FIFO 14</description>
16564 <description>Tx FIFO 15</description>
16571 <description>Clear NAK (CNAK)</description>
16578 <description>No Clear NAK</description>
16583 <description>Clear NAK</description>
16590 <description>Set NAK (SNAK)</description>
16597 <description>No Set NAK</description>
16602 <description>Set NAK</description>
16609 <description>Set DATA0 PID (SetD0PID)</description>
16616 … <description>Disables Set DATA0 PID or Do not force Even (micro)Frame</description>
16621 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame</descript…
16628 <description>Set DATA1 PID (SetD1PID)</description>
16635 … <description>Disables Set DATA1 PID or Do not force Odd (micro)Frame</description>
16640 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame</descripti…
16647 <description>Endpoint Disable (EPDis)</description>
16653 <description>No Action</description>
16658 <description>Disable Endpoint</description>
16665 <description>Endpoint Enable (EPEna)</description>
16671 <description>No Action</description>
16676 <description>Enable Endpoint</description>
16685 <description>Device IN Endpoint Interrupt Register</description>
16693 <description>Transfer Completed Interrupt (XferCompl)</description>
16699 <description>No Transfer Complete Interrupt</description>
16704 <description>Transfer Complete Interrupt</description>
16711 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
16717 <description>No Endpoint Disabled Interrupt</description>
16722 <description>Endpoint Disabled Interrupt</description>
16729 <description>AHB Error (AHBErr)</description>
16735 <description>No AHB Error Interrupt</description>
16740 <description>AHB Error interrupt</description>
16747 <description>Timeout Condition (TimeOUT)</description>
16753 <description>No Timeout interrupt</description>
16758 <description>Timeout interrupt</description>
16765 <description>IN Token Received When TxFIFO is Empty (INTknTXFEmp)</description>
16771 <description>No IN Token Received interrupt</description>
16776 <description>IN Token Received Interrupt</description>
16783 <description>IN Token Received with EP Mismatch (INTknEPMis)</description>
16789 <description>No IN Token Received with EP Mismatch interrupt</description>
16794 <description>IN Token Received with EP Mismatch interrupt</description>
16801 <description>IN Endpoint NAK Effective (INEPNakEff)</description>
16807 <description>No Endpoint NAK Effective interrupt</description>
16812 <description>IN Endpoint NAK Effective interrupt</description>
16819 <description>Transmit FIFO Empty (TxFEmp)</description>
16826 <description>No Transmit FIFO Empty interrupt</description>
16831 <description>Transmit FIFO Empty interrupt</description>
16838 <description>Fifo Underrun (TxfifoUndrn)</description>
16844 <description>No Tx FIFO Underrun interrupt</description>
16849 <description>TxFIFO Underrun interrupt</description>
16856 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
16862 <description>No BNA interrupt</description>
16867 <description>BNA interrupt</description>
16874 <description>Packet Drop Status (PktDrpSts)</description>
16880 <description>No interrupt</description>
16885 <description>Packet Drop Status interrupt</description>
16892 <description>NAK Interrupt (BbleErr)</description>
16898 <description>No interrupt</description>
16903 <description>BbleErr interrupt</description>
16910 <description>NAK Interrupt (NAKInterrupt)</description>
16916 <description>No NAK interrupt</description>
16921 <description>NAK Interrupt</description>
16928 <description>NYET Interrupt (NYETIntrpt)</description>
16934 <description>No NYET interrupt</description>
16939 <description>NYET Interrupt</description>
16948 <description>Device IN Endpoint Transfer Size Register</description>
16956 <description>Transfer Size (XferSize)</description>
16962 <description>Packet Count (PktCnt)</description>
16968 <description>MC</description>
16974 <description>1 packet</description>
16979 <description>2 packets</description>
16984 <description>3 packets</description>
16993 <description>Device IN Endpoint DMA Address Register</description>
17001 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
17009 <description>Device IN Endpoint Transmit FIFO Status Register</description>
17017 <description>IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)</description>
17026 <description>Device Control OUT Endpoint 0 Control Register</description>
17034 <description>Maximum Packet Size (MPS)</description>
17041 <description>64 bytes</description>
17046 <description>32 bytes</description>
17051 <description>16 bytes</description>
17056 <description>8 bytes</description>
17063 <description>USB Active Endpoint (USBActEP)</description>
17070 <description>USB Active Endpoint 0</description>
17077 <description>NAK Status (NAKSts)</description>
17084 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
17089 … <description>The core is transmitting NAK handshakes on this endpoint</description>
17096 <description>Endpoint Type (EPType)</description>
17103 <description>Endpoint Control 0</description>
17110 <description>STALL Handshake (Stall)</description>
17116 <description>No Stall</description>
17121 <description>Stall Handshake</description>
17128 <description>Clear NAK (CNAK)</description>
17135 <description>No action</description>
17140 <description>Clear NAK</description>
17147 <description>Set NAK (SNAK)</description>
17154 <description>No action</description>
17159 <description>Set NAK</description>
17166 <description>Endpoint Disable (EPDis)</description>
17173 <description>No Endpoint disable</description>
17180 <description>Endpoint Enable (EPEna)</description>
17186 <description>No action</description>
17191 <description>Enable Endpoint</description>
17200 <description>Device OUT Endpoint 0 Interrupt Register</description>
17208 <description>Transfer Completed Interrupt (XferCompl)</description>
17214 <description>No Transfer Complete Interrupt</description>
17219 <description>Transfer Complete Interrupt</description>
17226 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
17232 <description>No Endpoint Disabled Interrupt</description>
17237 <description>Endpoint Disabled Interrupt</description>
17244 <description>AHB Error (AHBErr)</description>
17250 <description>No AHB Error Interrupt</description>
17255 <description>AHB Error interrupt</description>
17262 <description>SETUP Phase Done (SetUp)</description>
17268 <description>No SETUP Phase Done</description>
17273 <description>SETUP Phase Done</description>
17280 <description>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</description>
17286 <description>No OUT Token Received When Endpoint Disabled</description>
17291 <description>OUT Token Received When Endpoint Disabled</description>
17298 <description>Status Phase Received for Control Write (StsPhseRcvd)</description>
17304 <description>No Status Phase Received for Control Write</description>
17309 <description>Status Phase Received for Control Write</description>
17316 <description>Back-to-Back SETUP Packets Received (Back2BackSETup)</description>
17322 <description>No Back-to-Back SETUP Packets Received</description>
17327 <description>Back-to-Back SETUP Packets Received</description>
17334 <description>OUT Packet Error (OutPktErr)</description>
17340 <description>No OUT Packet Error</description>
17345 <description>OUT Packet Error</description>
17352 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
17358 <description>No BNA interrupt</description>
17363 <description>BNA interrupt</description>
17370 <description>Packet Drop Status (PktDrpSts)</description>
17376 <description>No interrupt</description>
17381 <description>Packet Drop Status interrupt</description>
17388 <description>NAK Interrupt (BbleErr)</description>
17394 <description>No BbleErr interrupt</description>
17399 <description>BbleErr interrupt</description>
17406 <description>NAK Interrupt (NAKInterrupt)</description>
17412 <description>No NAK interrupt</description>
17417 <description>NAK Interrupt</description>
17424 <description>NYET Interrupt (NYETIntrpt)</description>
17430 <description>No NYET interrupt</description>
17435 <description>NYET Interrupt</description>
17442 <description>Setup Packet Received</description>
17448 <description>No Setup packet received</description>
17453 <description>Setup packet received</description>
17462 <description>Device OUT Endpoint 0 Transfer Size Register</description>
17470 <description>Transfer Size (XferSize)</description>
17476 <description>Packet Count (PktCnt)</description>
17482 <description>SETUP Packet Count (SUPCnt)</description>
17488 <description>1 packet</description>
17493 <description>2 packets</description>
17498 <description>3 packets</description>
17507 <description>Device OUT Endpoint 0 DMA Address Register</description>
17515 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
17523 <description>Device Control OUT Endpoint Control Register</description>
17531 <description>Maximum Packet Size (MPS)</description>
17537 <description>USB Active Endpoint (USBActEP)</description>
17543 <description>Not Active</description>
17548 <description>USB Active Endpoint</description>
17555 <description>Endpoint Data PID (DPID)</description>
17562 <description>Endpoint Data PID not active</description>
17567 <description>Endpoint Data PID active</description>
17574 <description>NAK Status (NAKSts)</description>
17581 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
17586 … <description>The core is transmitting NAK handshakes on this endpoint</description>
17593 <description>Endpoint Type (EPType)</description>
17599 <description>Control</description>
17604 <description>Isochronous</description>
17609 <description>Bulk</description>
17614 <description>Interrupt</description>
17621 <description>STALL Handshake (Stall)</description>
17627 <description>STALL All non-active tokens</description>
17632 <description>STALL All Active Tokens</description>
17645 <description>No Clear NAK</description>
17650 <description>Clear NAK</description>
17657 <description>Set NAK (SNAK)</description>
17664 <description>No Set NAK</description>
17669 <description>Set NAK</description>
17676 <description>Set DATA0 PID (SetD0PID)</description>
17683 <description>Disables Set DATA0 PID or Do not force Even Frame</description>
17688 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
17695 <description>Set DATA1 PID (SetD1PID)</description>
17702 <description>Disables Set DATA1 PID or Do not force Odd Frame</description>
17707 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
17714 <description>Endpoint Disable (EPDis)</description>
17720 <description>No Action</description>
17725 <description>Disable Endpoint</description>
17732 <description>Endpoint Enable (EPEna)</description>
17738 <description>No Action</description>
17743 <description>Enable Endpoint</description>
17752 <description>Device OUT Endpoint Interrupt Register</description>
17760 <description>Transfer Completed Interrupt (XferCompl)</description>
17766 <description>No Transfer Complete Interrupt</description>
17771 <description>Transfer Complete Interrupt</description>
17778 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
17784 <description>No Endpoint Disabled Interrupt</description>
17789 <description>Endpoint Disabled Interrupt</description>
17796 <description>AHB Error (AHBErr)</description>
17802 <description>No AHB Error Interrupt</description>
17807 <description>AHB Error interrupt</description>
17814 <description>SETUP Phase Done (SetUp)</description>
17820 <description>No SETUP Phase Done</description>
17825 <description>SETUP Phase Done</description>
17832 <description>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</description>
17838 <description>No OUT Token Received When Endpoint Disabled</description>
17843 <description>OUT Token Received When Endpoint Disabled</description>
17850 <description>Status Phase Received for Control Write (StsPhseRcvd)</description>
17856 <description>No Status Phase Received for Control Write</description>
17861 <description>Status Phase Received for Control Write</description>
17868 <description>Back-to-Back SETUP Packets Received (Back2BackSETup)</description>
17874 <description>No Back-to-Back SETUP Packets Received</description>
17879 <description>Back-to-Back SETUP Packets Received</description>
17886 <description>OUT Packet Error (OutPktErr)</description>
17892 <description>No OUT Packet Error</description>
17897 <description>OUT Packet Error</description>
17904 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
17910 <description>No BNA interrupt</description>
17915 <description>BNA interrupt</description>
17922 <description>Packet Drop Status (PktDrpSts)</description>
17928 <description>No interrupt</description>
17933 <description>Packet Drop Status interrupt</description>
17940 <description>NAK Interrupt (BbleErr)</description>
17946 <description>No BbleErr interrupt</description>
17951 <description>BbleErr interrupt</description>
17958 <description>NAK Interrupt (NAKInterrupt)</description>
17964 <description>No NAK interrupt</description>
17969 <description>NAK Interrupt</description>
17976 <description>NYET Interrupt (NYETIntrpt)</description>
17982 <description>No NYET interrupt</description>
17987 <description>NYET Interrupt</description>
17994 <description>Setup Packet Received</description>
18000 <description>No Setup packet received</description>
18005 <description>Setup packet received</description>
18014 <description>Device OUT Endpoint Transfer Size Register</description>
18022 <description>Transfer Size (XferSize)</description>
18028 <description>Packet Count (PktCnt)</description>
18034 <description>RxDPID</description>
18041 <description>DATA0</description>
18046 <description>DATA2 or 1 packet</description>
18051 <description>DATA1 or 2 packets</description>
18056 <description>MDATA or 3 packets</description>
18065 <description>Device OUT Endpoint DMA Address Register</description>
18073 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
18081 <description>Device Control OUT Endpoint Control Register</description>
18089 <description>Maximum Packet Size (MPS)</description>
18095 <description>USB Active Endpoint (USBActEP)</description>
18101 <description>Not Active</description>
18106 <description>USB Active Endpoint</description>
18113 <description>Endpoint Data PID (DPID)</description>
18120 <description>Endpoint Data PID not active</description>
18125 <description>Endpoint Data PID active</description>
18132 <description>NAK Status (NAKSts)</description>
18139 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
18144 … <description>The core is transmitting NAK handshakes on this endpoint</description>
18151 <description>Endpoint Type (EPType)</description>
18157 <description>Control</description>
18162 <description>Isochronous</description>
18167 <description>Bulk</description>
18172 <description>Interrupt</description>
18179 <description>STALL Handshake (Stall)</description>
18185 <description>STALL All non-active tokens</description>
18190 <description>STALL All Active Tokens</description>
18203 <description>No Clear NAK</description>
18208 <description>Clear NAK</description>
18215 <description>Set NAK (SNAK)</description>
18222 <description>No Set NAK</description>
18227 <description>Set NAK</description>
18234 <description>Set DATA0 PID (SetD0PID)</description>
18241 <description>Disables Set DATA0 PID or Do not force Even Frame</description>
18246 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
18253 <description>Set DATA1 PID (SetD1PID)</description>
18260 <description>Disables Set DATA1 PID or Do not force Odd Frame</description>
18265 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
18272 <description>Endpoint Disable (EPDis)</description>
18278 <description>No Action</description>
18283 <description>Disable Endpoint</description>
18290 <description>Endpoint Enable (EPEna)</description>
18296 <description>No Action</description>
18301 <description>Enable Endpoint</description>
18310 <description>Device OUT Endpoint Interrupt Register</description>
18318 <description>Transfer Completed Interrupt (XferCompl)</description>
18324 <description>No Transfer Complete Interrupt</description>
18329 <description>Transfer Complete Interrupt</description>
18336 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
18342 <description>No Endpoint Disabled Interrupt</description>
18347 <description>Endpoint Disabled Interrupt</description>
18354 <description>AHB Error (AHBErr)</description>
18360 <description>No AHB Error Interrupt</description>
18365 <description>AHB Error interrupt</description>
18372 <description>SETUP Phase Done (SetUp)</description>
18378 <description>No SETUP Phase Done</description>
18383 <description>SETUP Phase Done</description>
18390 <description>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</description>
18396 <description>No OUT Token Received When Endpoint Disabled</description>
18401 <description>OUT Token Received When Endpoint Disabled</description>
18408 <description>Status Phase Received for Control Write (StsPhseRcvd)</description>
18414 <description>No Status Phase Received for Control Write</description>
18419 <description>Status Phase Received for Control Write</description>
18426 <description>Back-to-Back SETUP Packets Received (Back2BackSETup)</description>
18432 <description>No Back-to-Back SETUP Packets Received</description>
18437 <description>Back-to-Back SETUP Packets Received</description>
18444 <description>OUT Packet Error (OutPktErr)</description>
18450 <description>No OUT Packet Error</description>
18455 <description>OUT Packet Error</description>
18462 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
18468 <description>No BNA interrupt</description>
18473 <description>BNA interrupt</description>
18480 <description>Packet Drop Status (PktDrpSts)</description>
18486 <description>No interrupt</description>
18491 <description>Packet Drop Status interrupt</description>
18498 <description>NAK Interrupt (BbleErr)</description>
18504 <description>No BbleErr interrupt</description>
18509 <description>BbleErr interrupt</description>
18516 <description>NAK Interrupt (NAKInterrupt)</description>
18522 <description>No NAK interrupt</description>
18527 <description>NAK Interrupt</description>
18534 <description>NYET Interrupt (NYETIntrpt)</description>
18540 <description>No NYET interrupt</description>
18545 <description>NYET Interrupt</description>
18552 <description>Setup Packet Received</description>
18558 <description>No Setup packet received</description>
18563 <description>Setup packet received</description>
18572 <description>Device OUT Endpoint Transfer Size Register</description>
18580 <description>Transfer Size (XferSize)</description>
18586 <description>Packet Count (PktCnt)</description>
18592 <description>RxDPID</description>
18599 <description>DATA0</description>
18604 <description>DATA2 or 1 packet</description>
18609 <description>DATA1 or 2 packets</description>
18614 <description>MDATA or 3 packets</description>
18623 <description>Device OUT Endpoint DMA Address Register</description>
18631 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
18639 <description>Device Control OUT Endpoint Control Register</description>
18647 <description>Maximum Packet Size (MPS)</description>
18653 <description>USB Active Endpoint (USBActEP)</description>
18659 <description>Not Active</description>
18664 <description>USB Active Endpoint</description>
18671 <description>Endpoint Data PID (DPID)</description>
18678 <description>Endpoint Data PID not active</description>
18683 <description>Endpoint Data PID active</description>
18690 <description>NAK Status (NAKSts)</description>
18697 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
18702 … <description>The core is transmitting NAK handshakes on this endpoint</description>
18709 <description>Endpoint Type (EPType)</description>
18715 <description>Control</description>
18720 <description>Isochronous</description>
18725 <description>Bulk</description>
18730 <description>Interrupt</description>
18737 <description>STALL Handshake (Stall)</description>
18743 <description>STALL All non-active tokens</description>
18748 <description>STALL All Active Tokens</description>
18761 <description>No Clear NAK</description>
18766 <description>Clear NAK</description>
18773 <description>Set NAK (SNAK)</description>
18780 <description>No Set NAK</description>
18785 <description>Set NAK</description>
18792 <description>Set DATA0 PID (SetD0PID)</description>
18799 <description>Disables Set DATA0 PID or Do not force Even Frame</description>
18804 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
18811 <description>Set DATA1 PID (SetD1PID)</description>
18818 <description>Disables Set DATA1 PID or Do not force Odd Frame</description>
18823 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
18830 <description>Endpoint Disable (EPDis)</description>
18836 <description>No Action</description>
18841 <description>Disable Endpoint</description>
18848 <description>Endpoint Enable (EPEna)</description>
18854 <description>No Action</description>
18859 <description>Enable Endpoint</description>
18868 <description>Device OUT Endpoint Interrupt Register</description>
18876 <description>Transfer Completed Interrupt (XferCompl)</description>
18882 <description>No Transfer Complete Interrupt</description>
18887 <description>Transfer Complete Interrupt</description>
18894 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
18900 <description>No Endpoint Disabled Interrupt</description>
18905 <description>Endpoint Disabled Interrupt</description>
18912 <description>AHB Error (AHBErr)</description>
18918 <description>No AHB Error Interrupt</description>
18923 <description>AHB Error interrupt</description>
18930 <description>SETUP Phase Done (SetUp)</description>
18936 <description>No SETUP Phase Done</description>
18941 <description>SETUP Phase Done</description>
18948 <description>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</description>
18954 <description>No OUT Token Received When Endpoint Disabled</description>
18959 <description>OUT Token Received When Endpoint Disabled</description>
18966 <description>Status Phase Received for Control Write (StsPhseRcvd)</description>
18972 <description>No Status Phase Received for Control Write</description>
18977 <description>Status Phase Received for Control Write</description>
18984 <description>Back-to-Back SETUP Packets Received (Back2BackSETup)</description>
18990 <description>No Back-to-Back SETUP Packets Received</description>
18995 <description>Back-to-Back SETUP Packets Received</description>
19002 <description>OUT Packet Error (OutPktErr)</description>
19008 <description>No OUT Packet Error</description>
19013 <description>OUT Packet Error</description>
19020 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
19026 <description>No BNA interrupt</description>
19031 <description>BNA interrupt</description>
19038 <description>Packet Drop Status (PktDrpSts)</description>
19044 <description>No interrupt</description>
19049 <description>Packet Drop Status interrupt</description>
19056 <description>NAK Interrupt (BbleErr)</description>
19062 <description>No BbleErr interrupt</description>
19067 <description>BbleErr interrupt</description>
19074 <description>NAK Interrupt (NAKInterrupt)</description>
19080 <description>No NAK interrupt</description>
19085 <description>NAK Interrupt</description>
19092 <description>NYET Interrupt (NYETIntrpt)</description>
19098 <description>No NYET interrupt</description>
19103 <description>NYET Interrupt</description>
19110 <description>Setup Packet Received</description>
19116 <description>No Setup packet received</description>
19121 <description>Setup packet received</description>
19130 <description>Device OUT Endpoint Transfer Size Register</description>
19138 <description>Transfer Size (XferSize)</description>
19144 <description>Packet Count (PktCnt)</description>
19150 <description>RxDPID</description>
19157 <description>DATA0</description>
19162 <description>DATA2 or 1 packet</description>
19167 <description>DATA1 or 2 packets</description>
19172 <description>MDATA or 3 packets</description>
19181 <description>Device OUT Endpoint DMA Address Register</description>
19189 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
19197 <description>Device Control OUT Endpoint Control Register</description>
19205 <description>Maximum Packet Size (MPS)</description>
19211 <description>USB Active Endpoint (USBActEP)</description>
19217 <description>Not Active</description>
19222 <description>USB Active Endpoint</description>
19229 <description>Endpoint Data PID (DPID)</description>
19236 <description>Endpoint Data PID not active</description>
19241 <description>Endpoint Data PID active</description>
19248 <description>NAK Status (NAKSts)</description>
19255 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
19260 … <description>The core is transmitting NAK handshakes on this endpoint</description>
19267 <description>Endpoint Type (EPType)</description>
19273 <description>Control</description>
19278 <description>Isochronous</description>
19283 <description>Bulk</description>
19288 <description>Interrupt</description>
19295 <description>STALL Handshake (Stall)</description>
19301 <description>STALL All non-active tokens</description>
19306 <description>STALL All Active Tokens</description>
19319 <description>No Clear NAK</description>
19324 <description>Clear NAK</description>
19331 <description>Set NAK (SNAK)</description>
19338 <description>No Set NAK</description>
19343 <description>Set NAK</description>
19350 <description>Set DATA0 PID (SetD0PID)</description>
19357 <description>Disables Set DATA0 PID or Do not force Even Frame</description>
19362 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
19369 <description>Set DATA1 PID (SetD1PID)</description>
19376 <description>Disables Set DATA1 PID or Do not force Odd Frame</description>
19381 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
19388 <description>Endpoint Disable (EPDis)</description>
19394 <description>No Action</description>
19399 <description>Disable Endpoint</description>
19406 <description>Endpoint Enable (EPEna)</description>
19412 <description>No Action</description>
19417 <description>Enable Endpoint</description>
19426 <description>Device OUT Endpoint Interrupt Register</description>
19434 <description>Transfer Completed Interrupt (XferCompl)</description>
19440 <description>No Transfer Complete Interrupt</description>
19445 <description>Transfer Complete Interrupt</description>
19452 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
19458 <description>No Endpoint Disabled Interrupt</description>
19463 <description>Endpoint Disabled Interrupt</description>
19470 <description>AHB Error (AHBErr)</description>
19476 <description>No AHB Error Interrupt</description>
19481 <description>AHB Error interrupt</description>
19488 <description>SETUP Phase Done (SetUp)</description>
19494 <description>No SETUP Phase Done</description>
19499 <description>SETUP Phase Done</description>
19506 <description>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</description>
19512 <description>No OUT Token Received When Endpoint Disabled</description>
19517 <description>OUT Token Received When Endpoint Disabled</description>
19524 <description>Status Phase Received for Control Write (StsPhseRcvd)</description>
19530 <description>No Status Phase Received for Control Write</description>
19535 <description>Status Phase Received for Control Write</description>
19542 <description>Back-to-Back SETUP Packets Received (Back2BackSETup)</description>
19548 <description>No Back-to-Back SETUP Packets Received</description>
19553 <description>Back-to-Back SETUP Packets Received</description>
19560 <description>OUT Packet Error (OutPktErr)</description>
19566 <description>No OUT Packet Error</description>
19571 <description>OUT Packet Error</description>
19578 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
19584 <description>No BNA interrupt</description>
19589 <description>BNA interrupt</description>
19596 <description>Packet Drop Status (PktDrpSts)</description>
19602 <description>No interrupt</description>
19607 <description>Packet Drop Status interrupt</description>
19614 <description>NAK Interrupt (BbleErr)</description>
19620 <description>No BbleErr interrupt</description>
19625 <description>BbleErr interrupt</description>
19632 <description>NAK Interrupt (NAKInterrupt)</description>
19638 <description>No NAK interrupt</description>
19643 <description>NAK Interrupt</description>
19650 <description>NYET Interrupt (NYETIntrpt)</description>
19656 <description>No NYET interrupt</description>
19661 <description>NYET Interrupt</description>
19668 <description>Setup Packet Received</description>
19674 <description>No Setup packet received</description>
19679 <description>Setup packet received</description>
19688 <description>Device OUT Endpoint Transfer Size Register</description>
19696 <description>Transfer Size (XferSize)</description>
19702 <description>Packet Count (PktCnt)</description>
19708 <description>RxDPID</description>
19715 <description>DATA0</description>
19720 <description>DATA2 or 1 packet</description>
19725 <description>DATA1 or 2 packets</description>
19730 <description>MDATA or 3 packets</description>
19739 <description>Device OUT Endpoint DMA Address Register</description>
19747 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
19755 <description>Device Control OUT Endpoint Control Register</description>
19763 <description>Maximum Packet Size (MPS)</description>
19769 <description>USB Active Endpoint (USBActEP)</description>
19775 <description>Not Active</description>
19780 <description>USB Active Endpoint</description>
19787 <description>Endpoint Data PID (DPID)</description>
19794 <description>Endpoint Data PID not active</description>
19799 <description>Endpoint Data PID active</description>
19806 <description>NAK Status (NAKSts)</description>
19813 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
19818 … <description>The core is transmitting NAK handshakes on this endpoint</description>
19825 <description>Endpoint Type (EPType)</description>
19831 <description>Control</description>
19836 <description>Isochronous</description>
19841 <description>Bulk</description>
19846 <description>Interrupt</description>
19853 <description>STALL Handshake (Stall)</description>
19859 <description>STALL All non-active tokens</description>
19864 <description>STALL All Active Tokens</description>
19877 <description>No Clear NAK</description>
19882 <description>Clear NAK</description>
19889 <description>Set NAK (SNAK)</description>
19896 <description>No Set NAK</description>
19901 <description>Set NAK</description>
19908 <description>Set DATA0 PID (SetD0PID)</description>
19915 <description>Disables Set DATA0 PID or Do not force Even Frame</description>
19920 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
19927 <description>Set DATA1 PID (SetD1PID)</description>
19934 <description>Disables Set DATA1 PID or Do not force Odd Frame</description>
19939 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
19946 <description>Endpoint Disable (EPDis)</description>
19952 <description>No Action</description>
19957 <description>Disable Endpoint</description>
19964 <description>Endpoint Enable (EPEna)</description>
19970 <description>No Action</description>
19975 <description>Enable Endpoint</description>
19984 <description>Device OUT Endpoint Interrupt Register</description>
19992 <description>Transfer Completed Interrupt (XferCompl)</description>
19998 <description>No Transfer Complete Interrupt</description>
20003 <description>Transfer Complete Interrupt</description>
20010 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
20016 <description>No Endpoint Disabled Interrupt</description>
20021 <description>Endpoint Disabled Interrupt</description>
20028 <description>AHB Error (AHBErr)</description>
20034 <description>No AHB Error Interrupt</description>
20039 <description>AHB Error interrupt</description>
20046 <description>SETUP Phase Done (SetUp)</description>
20052 <description>No SETUP Phase Done</description>
20057 <description>SETUP Phase Done</description>
20064 <description>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</description>
20070 <description>No OUT Token Received When Endpoint Disabled</description>
20075 <description>OUT Token Received When Endpoint Disabled</description>
20082 <description>Status Phase Received for Control Write (StsPhseRcvd)</description>
20088 <description>No Status Phase Received for Control Write</description>
20093 <description>Status Phase Received for Control Write</description>
20100 <description>Back-to-Back SETUP Packets Received (Back2BackSETup)</description>
20106 <description>No Back-to-Back SETUP Packets Received</description>
20111 <description>Back-to-Back SETUP Packets Received</description>
20118 <description>OUT Packet Error (OutPktErr)</description>
20124 <description>No OUT Packet Error</description>
20129 <description>OUT Packet Error</description>
20136 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
20142 <description>No BNA interrupt</description>
20147 <description>BNA interrupt</description>
20154 <description>Packet Drop Status (PktDrpSts)</description>
20160 <description>No interrupt</description>
20165 <description>Packet Drop Status interrupt</description>
20172 <description>NAK Interrupt (BbleErr)</description>
20178 <description>No BbleErr interrupt</description>
20183 <description>BbleErr interrupt</description>
20190 <description>NAK Interrupt (NAKInterrupt)</description>
20196 <description>No NAK interrupt</description>
20201 <description>NAK Interrupt</description>
20208 <description>NYET Interrupt (NYETIntrpt)</description>
20214 <description>No NYET interrupt</description>
20219 <description>NYET Interrupt</description>
20226 <description>Setup Packet Received</description>
20232 <description>No Setup packet received</description>
20237 <description>Setup packet received</description>
20246 <description>Device OUT Endpoint Transfer Size Register</description>
20254 <description>Transfer Size (XferSize)</description>
20260 <description>Packet Count (PktCnt)</description>
20266 <description>RxDPID</description>
20273 <description>DATA0</description>
20278 <description>DATA2 or 1 packet</description>
20283 <description>DATA1 or 2 packets</description>
20288 <description>MDATA or 3 packets</description>
20297 <description>Device OUT Endpoint DMA Address Register</description>
20305 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
20313 <description>Device Control OUT Endpoint Control Register</description>
20321 <description>Maximum Packet Size (MPS)</description>
20327 <description>USB Active Endpoint (USBActEP)</description>
20333 <description>Not Active</description>
20338 <description>USB Active Endpoint</description>
20345 <description>Endpoint Data PID (DPID)</description>
20352 <description>Endpoint Data PID not active</description>
20357 <description>Endpoint Data PID active</description>
20364 <description>NAK Status (NAKSts)</description>
20371 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
20376 … <description>The core is transmitting NAK handshakes on this endpoint</description>
20383 <description>Endpoint Type (EPType)</description>
20389 <description>Control</description>
20394 <description>Isochronous</description>
20399 <description>Bulk</description>
20404 <description>Interrupt</description>
20411 <description>STALL Handshake (Stall)</description>
20417 <description>STALL All non-active tokens</description>
20422 <description>STALL All Active Tokens</description>
20435 <description>No Clear NAK</description>
20440 <description>Clear NAK</description>
20447 <description>Set NAK (SNAK)</description>
20454 <description>No Set NAK</description>
20459 <description>Set NAK</description>
20466 <description>Set DATA0 PID (SetD0PID)</description>
20473 <description>Disables Set DATA0 PID or Do not force Even Frame</description>
20478 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
20485 <description>Set DATA1 PID (SetD1PID)</description>
20492 <description>Disables Set DATA1 PID or Do not force Odd Frame</description>
20497 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
20504 <description>Endpoint Disable (EPDis)</description>
20510 <description>No Action</description>
20515 <description>Disable Endpoint</description>
20522 <description>Endpoint Enable (EPEna)</description>
20528 <description>No Action</description>
20533 <description>Enable Endpoint</description>
20542 <description>Device OUT Endpoint Interrupt Register</description>
20550 <description>Transfer Completed Interrupt (XferCompl)</description>
20556 <description>No Transfer Complete Interrupt</description>
20561 <description>Transfer Complete Interrupt</description>
20568 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
20574 <description>No Endpoint Disabled Interrupt</description>
20579 <description>Endpoint Disabled Interrupt</description>
20586 <description>AHB Error (AHBErr)</description>
20592 <description>No AHB Error Interrupt</description>
20597 <description>AHB Error interrupt</description>
20604 <description>SETUP Phase Done (SetUp)</description>
20610 <description>No SETUP Phase Done</description>
20615 <description>SETUP Phase Done</description>
20622 <description>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</description>
20628 <description>No OUT Token Received When Endpoint Disabled</description>
20633 <description>OUT Token Received When Endpoint Disabled</description>
20640 <description>Status Phase Received for Control Write (StsPhseRcvd)</description>
20646 <description>No Status Phase Received for Control Write</description>
20651 <description>Status Phase Received for Control Write</description>
20658 <description>Back-to-Back SETUP Packets Received (Back2BackSETup)</description>
20664 <description>No Back-to-Back SETUP Packets Received</description>
20669 <description>Back-to-Back SETUP Packets Received</description>
20676 <description>OUT Packet Error (OutPktErr)</description>
20682 <description>No OUT Packet Error</description>
20687 <description>OUT Packet Error</description>
20694 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
20700 <description>No BNA interrupt</description>
20705 <description>BNA interrupt</description>
20712 <description>Packet Drop Status (PktDrpSts)</description>
20718 <description>No interrupt</description>
20723 <description>Packet Drop Status interrupt</description>
20730 <description>NAK Interrupt (BbleErr)</description>
20736 <description>No BbleErr interrupt</description>
20741 <description>BbleErr interrupt</description>
20748 <description>NAK Interrupt (NAKInterrupt)</description>
20754 <description>No NAK interrupt</description>
20759 <description>NAK Interrupt</description>
20766 <description>NYET Interrupt (NYETIntrpt)</description>
20772 <description>No NYET interrupt</description>
20777 <description>NYET Interrupt</description>
20784 <description>Setup Packet Received</description>
20790 <description>No Setup packet received</description>
20795 <description>Setup packet received</description>
20804 <description>Device OUT Endpoint Transfer Size Register</description>
20812 <description>Transfer Size (XferSize)</description>
20818 <description>Packet Count (PktCnt)</description>
20824 <description>RxDPID</description>
20831 <description>DATA0</description>
20836 <description>DATA2 or 1 packet</description>
20841 <description>DATA1 or 2 packets</description>
20846 <description>MDATA or 3 packets</description>
20855 <description>Device OUT Endpoint DMA Address Register</description>
20863 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
20871 <description>Device Control OUT Endpoint Control Register</description>
20879 <description>Maximum Packet Size (MPS)</description>
20885 <description>USB Active Endpoint (USBActEP)</description>
20891 <description>Not Active</description>
20896 <description>USB Active Endpoint</description>
20903 <description>Endpoint Data PID (DPID)</description>
20910 <description>Endpoint Data PID not active</description>
20915 <description>Endpoint Data PID active</description>
20922 <description>NAK Status (NAKSts)</description>
20929 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
20934 … <description>The core is transmitting NAK handshakes on this endpoint</description>
20941 <description>Endpoint Type (EPType)</description>
20947 <description>Control</description>
20952 <description>Isochronous</description>
20957 <description>Bulk</description>
20962 <description>Interrupt</description>
20969 <description>STALL Handshake (Stall)</description>
20975 <description>STALL All non-active tokens</description>
20980 <description>STALL All Active Tokens</description>
20993 <description>No Clear NAK</description>
20998 <description>Clear NAK</description>
21005 <description>Set NAK (SNAK)</description>
21012 <description>No Set NAK</description>
21017 <description>Set NAK</description>
21024 <description>Set DATA0 PID (SetD0PID)</description>
21031 <description>Disables Set DATA0 PID or Do not force Even Frame</description>
21036 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
21043 <description>Set DATA1 PID (SetD1PID)</description>
21050 <description>Disables Set DATA1 PID or Do not force Odd Frame</description>
21055 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
21062 <description>Endpoint Disable (EPDis)</description>
21068 <description>No Action</description>
21073 <description>Disable Endpoint</description>
21080 <description>Endpoint Enable (EPEna)</description>
21086 <description>No Action</description>
21091 <description>Enable Endpoint</description>
21100 <description>Device OUT Endpoint Interrupt Register</description>
21108 <description>Transfer Completed Interrupt (XferCompl)</description>
21114 <description>No Transfer Complete Interrupt</description>
21119 <description>Transfer Complete Interrupt</description>
21126 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
21132 <description>No Endpoint Disabled Interrupt</description>
21137 <description>Endpoint Disabled Interrupt</description>
21144 <description>AHB Error (AHBErr)</description>
21150 <description>No AHB Error Interrupt</description>
21155 <description>AHB Error interrupt</description>
21162 <description>SETUP Phase Done (SetUp)</description>
21168 <description>No SETUP Phase Done</description>
21173 <description>SETUP Phase Done</description>
21180 <description>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</description>
21186 <description>No OUT Token Received When Endpoint Disabled</description>
21191 <description>OUT Token Received When Endpoint Disabled</description>
21198 <description>Status Phase Received for Control Write (StsPhseRcvd)</description>
21204 <description>No Status Phase Received for Control Write</description>
21209 <description>Status Phase Received for Control Write</description>
21216 <description>Back-to-Back SETUP Packets Received (Back2BackSETup)</description>
21222 <description>No Back-to-Back SETUP Packets Received</description>
21227 <description>Back-to-Back SETUP Packets Received</description>
21234 <description>OUT Packet Error (OutPktErr)</description>
21240 <description>No OUT Packet Error</description>
21245 <description>OUT Packet Error</description>
21252 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
21258 <description>No BNA interrupt</description>
21263 <description>BNA interrupt</description>
21270 <description>Packet Drop Status (PktDrpSts)</description>
21276 <description>No interrupt</description>
21281 <description>Packet Drop Status interrupt</description>
21288 <description>NAK Interrupt (BbleErr)</description>
21294 <description>No BbleErr interrupt</description>
21299 <description>BbleErr interrupt</description>
21306 <description>NAK Interrupt (NAKInterrupt)</description>
21312 <description>No NAK interrupt</description>
21317 <description>NAK Interrupt</description>
21324 <description>NYET Interrupt (NYETIntrpt)</description>
21330 <description>No NYET interrupt</description>
21335 <description>NYET Interrupt</description>
21342 <description>Setup Packet Received</description>
21348 <description>No Setup packet received</description>
21353 <description>Setup packet received</description>
21362 <description>Device OUT Endpoint Transfer Size Register</description>
21370 <description>Transfer Size (XferSize)</description>
21376 <description>Packet Count (PktCnt)</description>
21382 <description>RxDPID</description>
21389 <description>DATA0</description>
21394 <description>DATA2 or 1 packet</description>
21399 <description>DATA1 or 2 packets</description>
21404 <description>MDATA or 3 packets</description>
21413 <description>Device OUT Endpoint DMA Address Register</description>
21421 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
21429 <description>Device Control OUT Endpoint Control Register</description>
21437 <description>Maximum Packet Size (MPS)</description>
21443 <description>USB Active Endpoint (USBActEP)</description>
21449 <description>Not Active</description>
21454 <description>USB Active Endpoint</description>
21461 <description>Endpoint Data PID (DPID)</description>
21468 <description>Endpoint Data PID not active</description>
21473 <description>Endpoint Data PID active</description>
21480 <description>NAK Status (NAKSts)</description>
21487 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
21492 … <description>The core is transmitting NAK handshakes on this endpoint</description>
21499 <description>Endpoint Type (EPType)</description>
21505 <description>Control</description>
21510 <description>Isochronous</description>
21515 <description>Bulk</description>
21520 <description>Interrupt</description>
21527 <description>STALL Handshake (Stall)</description>
21533 <description>STALL All non-active tokens</description>
21538 <description>STALL All Active Tokens</description>
21551 <description>No Clear NAK</description>
21556 <description>Clear NAK</description>
21563 <description>Set NAK (SNAK)</description>
21570 <description>No Set NAK</description>
21575 <description>Set NAK</description>
21582 <description>Set DATA0 PID (SetD0PID)</description>
21589 <description>Disables Set DATA0 PID or Do not force Even Frame</description>
21594 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
21601 <description>Set DATA1 PID (SetD1PID)</description>
21608 <description>Disables Set DATA1 PID or Do not force Odd Frame</description>
21613 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
21620 <description>Endpoint Disable (EPDis)</description>
21626 <description>No Action</description>
21631 <description>Disable Endpoint</description>
21638 <description>Endpoint Enable (EPEna)</description>
21644 <description>No Action</description>
21649 <description>Enable Endpoint</description>
21658 <description>Device OUT Endpoint Interrupt Register</description>
21666 <description>Transfer Completed Interrupt (XferCompl)</description>
21672 <description>No Transfer Complete Interrupt</description>
21677 <description>Transfer Complete Interrupt</description>
21684 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
21690 <description>No Endpoint Disabled Interrupt</description>
21695 <description>Endpoint Disabled Interrupt</description>
21702 <description>AHB Error (AHBErr)</description>
21708 <description>No AHB Error Interrupt</description>
21713 <description>AHB Error interrupt</description>
21720 <description>SETUP Phase Done (SetUp)</description>
21726 <description>No SETUP Phase Done</description>
21731 <description>SETUP Phase Done</description>
21738 <description>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</description>
21744 <description>No OUT Token Received When Endpoint Disabled</description>
21749 <description>OUT Token Received When Endpoint Disabled</description>
21756 <description>Status Phase Received for Control Write (StsPhseRcvd)</description>
21762 <description>No Status Phase Received for Control Write</description>
21767 <description>Status Phase Received for Control Write</description>
21774 <description>Back-to-Back SETUP Packets Received (Back2BackSETup)</description>
21780 <description>No Back-to-Back SETUP Packets Received</description>
21785 <description>Back-to-Back SETUP Packets Received</description>
21792 <description>OUT Packet Error (OutPktErr)</description>
21798 <description>No OUT Packet Error</description>
21803 <description>OUT Packet Error</description>
21810 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
21816 <description>No BNA interrupt</description>
21821 <description>BNA interrupt</description>
21828 <description>Packet Drop Status (PktDrpSts)</description>
21834 <description>No interrupt</description>
21839 <description>Packet Drop Status interrupt</description>
21846 <description>NAK Interrupt (BbleErr)</description>
21852 <description>No BbleErr interrupt</description>
21857 <description>BbleErr interrupt</description>
21864 <description>NAK Interrupt (NAKInterrupt)</description>
21870 <description>No NAK interrupt</description>
21875 <description>NAK Interrupt</description>
21882 <description>NYET Interrupt (NYETIntrpt)</description>
21888 <description>No NYET interrupt</description>
21893 <description>NYET Interrupt</description>
21900 <description>Setup Packet Received</description>
21906 <description>No Setup packet received</description>
21911 <description>Setup packet received</description>
21920 <description>Device OUT Endpoint Transfer Size Register</description>
21928 <description>Transfer Size (XferSize)</description>
21934 <description>Packet Count (PktCnt)</description>
21940 <description>RxDPID</description>
21947 <description>DATA0</description>
21952 <description>DATA2 or 1 packet</description>
21957 <description>DATA1 or 2 packets</description>
21962 <description>MDATA or 3 packets</description>
21971 <description>Device OUT Endpoint DMA Address Register</description>
21979 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
21987 <description>Device Control OUT Endpoint Control Register</description>
21995 <description>Maximum Packet Size (MPS)</description>
22001 <description>USB Active Endpoint (USBActEP)</description>
22007 <description>Not Active</description>
22012 <description>USB Active Endpoint</description>
22019 <description>Endpoint Data PID (DPID)</description>
22026 <description>Endpoint Data PID not active</description>
22031 <description>Endpoint Data PID active</description>
22038 <description>NAK Status (NAKSts)</description>
22045 … <description>The core is transmitting non-NAK handshakes based on the FIFO status</description>
22050 … <description>The core is transmitting NAK handshakes on this endpoint</description>
22057 <description>Endpoint Type (EPType)</description>
22063 <description>Control</description>
22068 <description>Isochronous</description>
22073 <description>Bulk</description>
22078 <description>Interrupt</description>
22085 <description>STALL Handshake (Stall)</description>
22091 <description>STALL All non-active tokens</description>
22096 <description>STALL All Active Tokens</description>
22109 <description>No Clear NAK</description>
22114 <description>Clear NAK</description>
22121 <description>Set NAK (SNAK)</description>
22128 <description>No Set NAK</description>
22133 <description>Set NAK</description>
22140 <description>Set DATA0 PID (SetD0PID)</description>
22147 <description>Disables Set DATA0 PID or Do not force Even Frame</description>
22152 …<description>Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
22159 <description>Set DATA1 PID (SetD1PID)</description>
22166 <description>Disables Set DATA1 PID or Do not force Odd Frame</description>
22171 …<description>Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame</descriptio…
22178 <description>Endpoint Disable (EPDis)</description>
22184 <description>No Action</description>
22189 <description>Disable Endpoint</description>
22196 <description>Endpoint Enable (EPEna)</description>
22202 <description>No Action</description>
22207 <description>Enable Endpoint</description>
22216 <description>Device OUT Endpoint Interrupt Register</description>
22224 <description>Transfer Completed Interrupt (XferCompl)</description>
22230 <description>No Transfer Complete Interrupt</description>
22235 <description>Transfer Complete Interrupt</description>
22242 <description>Endpoint Disabled Interrupt (EPDisbld)</description>
22248 <description>No Endpoint Disabled Interrupt</description>
22253 <description>Endpoint Disabled Interrupt</description>
22260 <description>AHB Error (AHBErr)</description>
22266 <description>No AHB Error Interrupt</description>
22271 <description>AHB Error interrupt</description>
22278 <description>SETUP Phase Done (SetUp)</description>
22284 <description>No SETUP Phase Done</description>
22289 <description>SETUP Phase Done</description>
22296 <description>OUT Token Received When Endpoint Disabled (OUTTknEPdis)</description>
22302 <description>No OUT Token Received When Endpoint Disabled</description>
22307 <description>OUT Token Received When Endpoint Disabled</description>
22314 <description>Status Phase Received for Control Write (StsPhseRcvd)</description>
22320 <description>No Status Phase Received for Control Write</description>
22325 <description>Status Phase Received for Control Write</description>
22332 <description>Back-to-Back SETUP Packets Received (Back2BackSETup)</description>
22338 <description>No Back-to-Back SETUP Packets Received</description>
22343 <description>Back-to-Back SETUP Packets Received</description>
22350 <description>OUT Packet Error (OutPktErr)</description>
22356 <description>No OUT Packet Error</description>
22361 <description>OUT Packet Error</description>
22368 <description>BNA (Buffer Not Available) Interrupt (BNAIntr)</description>
22374 <description>No BNA interrupt</description>
22379 <description>BNA interrupt</description>
22386 <description>Packet Drop Status (PktDrpSts)</description>
22392 <description>No interrupt</description>
22397 <description>Packet Drop Status interrupt</description>
22404 <description>NAK Interrupt (BbleErr)</description>
22410 <description>No BbleErr interrupt</description>
22415 <description>BbleErr interrupt</description>
22422 <description>NAK Interrupt (NAKInterrupt)</description>
22428 <description>No NAK interrupt</description>
22433 <description>NAK Interrupt</description>
22440 <description>NYET Interrupt (NYETIntrpt)</description>
22446 <description>No NYET interrupt</description>
22451 <description>NYET Interrupt</description>
22458 <description>Setup Packet Received</description>
22464 <description>No Setup packet received</description>
22469 <description>Setup packet received</description>
22478 <description>Device OUT Endpoint Transfer Size Register</description>
22486 <description>Transfer Size (XferSize)</description>
22492 <description>Packet Count (PktCnt)</description>
22498 <description>RxDPID</description>
22505 <description>DATA0</description>
22510 <description>DATA2 or 1 packet</description>
22515 <description>DATA1 or 2 packets</description>
22520 <description>MDATA or 3 packets</description>
22529 <description>Device OUT Endpoint DMA Address Register</description>
22537 …<description>Holds the start address of the external memory for storing or fetching endpoint</desc…
22545 <description>Power and Clock Gating Control Register</description>
22553 <description>Stop Pclk (StopPclk)</description>
22559 <description>Disable Stop Pclk</description>
22564 <description>Enable Stop Pclk</description>
22571 <description>Gate Hclk (GateHclk)</description>
22577 … <description>Clears this bit when the USB is resumed or a new session starts</description>
22582 …<description>Sets this bit to gate hclk to modules when the USB is suspended or the session is not…
22589 <description>Reset Power-Down Modules (RstPdwnModule)</description>
22595 <description>Power is turned on</description>
22600 <description>Power is turned off</description>
22607 <description>Enable Sleep Clock Gating</description>
22613 <description>The PHY clock is not gated in Sleep state</description>
22618 … <description>The Core internal clock gating is enabled in Sleep state</description>
22625 <description>PHY In Sleep</description>
22632 <description>Phy not in Sleep state</description>
22637 <description>Phy in Sleep state</description>
22644 <description>L1 Deep Sleep</description>
22651 <description>Non Deep Sleep</description>
22656 <description>Deep Sleep</description>
22663 <description>Restore Mode (RestoreMode)</description>
22669 …description>In Host mode,this bit indicates Host-initiated Resume and Reset. In Device mode, this …
22674 …description>In Host mode,this bit indicates Device-initiated Remote Wakeup. In Device mode, this b…
22681 <description>Essential Register Values Restored (EssRegRestored)</description>
22688 <description>Register values of essential registers are not restored</description>
22693 … <description>Register values of essential registers have been restored</description>
22700 <description>Restore Value (RestoreValue)</description>
22708 <description>Global STAR Fix Disable Register</description>
22716 …<description>Disable the STAR fix added for Device controller to go back to low power mode when Ho…
22722 …<description>Device controller goes back into SUSPENDED state when host ignores Remote Wakeup</des…
22727 …<description>Device controller waits indefinitely without entering SUSPENDED state when host ignor…
22734 …<description>Disable the STAR fix added for Device controller to detect lineK and move to RESUMING…
22740 <description>Device controller detects line K and resumes</description>
22745 <description>Device controller does not detect line K and resume</description>
22752 …description>Disable the STAR fix added for Device controller to reject DATA0 for the first Control…
22758 <description>Transaction Error reported when host sends DATA0 PID</description>
22763 … <description>Transaction Error not reported when host sends DATA0 PID</description>
22770 …<description>Disable the STAR fix added for Host controller to flag error for SSPLIT STALL/NYET</d…
22776 … <description>Transaction Error reported when device sends STALL/NYET for SSPLIT</description>
22781 … <description>Transaction Error not reported when device sends STALL/NYET for SSPLIT</description>
22788 …<description>Disable the STAR fix added for Host controller to accept DATA1 PID from device for IS…
22794 …<description>Transaction Error not reported when device sends DATA1 PID for ISOC Split</descriptio…
22799 … <description>Transaction Error reported when device sends DATA1 PID for ISOC Split</description>
22806 …<description>Disable the STAR fix added for Host controller to handle Faulty cable scenarios</desc…
22812 <description>Fix for handling faulty cable enabled</description>
22817 <description>Fix for handling faulty cable disabled</description>
22824 …<description>Disable the STAR fix added for Host controller LS mode IPG increment from 2 LS bit ti…
22830 <description>Host LS mode IPG is 3 LS bit times</description>
22835 <description>Host LS mode IPG is 2 LS bit times</description>
22842 …<description>Disable the STAR fix added for Device controller to transition to IDLE state during F…
22848 … <description>Device controller transitions to IDLE state during FS device disconnect</description>
22853 …<description>Device controller does not transition to IDLE state during FS device disconnect</desc…
22860 …<description>Disable the STAR fix added for Device controller to not start Remote Wakeup signallin…
22866 …<description>Device controller does not start remote wakeup signalling when host resume has alread…
22871 …<description>Device controller is allowed to start remote wakeup signalling when host resume has a…
22878 …<description>Disable the STAR fix added for Device controller to not hang when Remote Wakeup signa…
22884 …<description>Device controller does not hang when remote wakeup signalling clashes with host resum…
22889 …<description>Device controller hangs when remote wakeup signalling clashes with host resume during…
22896 …description>Disable the STAR fix added for Host controller to wait for IPG duration to send next t…
22902 <description>Host controller checks IPG after NAK/STALL for IN token</description>
22907 … <description>Host controller does not check IPG after NAK/STALL for IN token</description>
22914 …description>Disable the STAR fix added for Host controller to increase the gap between utmi_xcvrse…
22920 …<description>Host controller asserts utmi_txvalid at least 2 utmi_clk cycles after utmi_xcvrselect…
22925 …<description>Host controller can assert utmi_txvalid after 1 utmi_clk cycle of utmi_xcvrselect swi…
22932 …description>Disable the STAR fix added for Host controller to increase the preamble transceiver se…
22938 …description>Host controller waits for previous functional register update to complete before switc…
22943 …description>Host controller does not wait for the previous functional register update to complete …
22950 …description>Disable the STAR fix added for Host controller to report transaction error when DATA0 …
22956 …<description>Host controller reports transaction error when DATA0 PID is received for CTRL STATUS …
22961 …<description>Host controller retries the transfer when DATA0 PID is received for CTRL STATUS IN tr…
22968 …<description>Disable the correction to OpMode/XcvrSel/TermSel on UTMI Interface in Host mode.</des…
22974 …<description>Opmode, XcvrSel, TermSel are changed by the Host Controller after TxValid goes LOW (1…
22979 …description>Opmode, XcvrSel, TermSel are changed by the Host Controller without waiting for TxVali…
22986 …<description>Disable the STAR fix added for correcting Opmode and XcvrSel on UTMI Interface when r…
22992 …<description>Valid Combination of Opmode and XcvrSel is driven when reset is detected in suspend s…
22997 …<description>Invalid Combination of Opmode and XcvrSel is driven when reset is detected in suspend…
23004 …<description>Disable the STAR fix added for correcting Txvalid deassertion on UTMI Interface when …
23010 …<description>Txvalid is deasserted during soft disconnect after receiving Txready from the PHY</de…
23015 …<description>Txvalid is deasserted during soft disconnect without waiting for Txready from the PHY…
23022 …<description>Disable the STAR fix added for correcting Host behavior when port is disabled.</descr…
23028 <description>Txvalid is not asserted when port is disabled</description>
23033 <description>Txvalid can be asserted when port is disabled</description>
23044 <description>Unspecified</description>
23052 <description>Description collection: Data FIFO Access Register Map 0</description>
23061 <description>Unspecified</description>
23069 <description>Description collection: Data FIFO Direct Access Register Map</description>
23080 <description>I3CCORE 0</description>
23095 <description>Unspecified</description>
23101 <description>DWC_mipi_i3c control Register</description>
23109 <description>I3C Broadcast Address include</description>
23115 <description>Unspecified</description>
23120 <description>Unspecified</description>
23127 <description>I2C Slave Present</description>
23133 <description>Unspecified</description>
23138 <description>Unspecified</description>
23145 <description>Hot-Join ACK/NACK Control</description>
23151 <description>Unspecified</description>
23156 <description>Unspecified</description>
23163 <description>Idle Count Multiplier</description>
23169 <description>Unspecified</description>
23174 <description>Unspecified</description>
23179 <description>Unspecified</description>
23184 <description>Unspecified</description>
23191 <description>This field is used in Slave mode of operation.</description>
23197 <description>DMA Handshake Interface Enable</description>
23203 <description>The DMA handshake control has no significance.</description>
23208 … <description>Enables the DMA handshake control to interact with external DMA.</description>
23215 <description>DWC_mipi_i3c Abort</description>
23221 <description>DWC_mipi_i3c Resume</description>
23227 <description>Controls whether or not DWC_mipi_i3c is enabled.</description>
23233 <description>Disables the DWC_mipi_i3c controller</description>
23238 <description>Enables the DWC_mipi_i3c controller.</description>
23247 …<description>In the master mode of operation this Register is used to program the Device Dynamic A…
23255 <description>Device Static Address.</description>
23261 <description>Static Address Valid.</description>
23267 <description>Unspecified</description>
23272 <description>Unspecified</description>
23279 <description>Device Dynamic Address.</description>
23285 <description>Dynamic Address Valid</description>
23291 <description>Unspecified</description>
23296 <description>Unspecified</description>
23305 <description>Hardware Capability register</description>
23313 <description>Reflects the IC_DEVICE_ROLE Configurable Parameter.</description>
23320 <description>Master Only</description>
23325 <description>Programmable Master-Slave</description>
23330 <description>Secondary Master</description>
23335 <description>Slave Only</description>
23342 <description>Reflects the IC_SPEED_HDR_DDR Configurable Parameter.</description>
23349 <description>HDR-DDR not supported</description>
23354 <description>HDR-DDR supported</description>
23361 <description>Reflects the IC_SPEED_HDR_TS Configurable Parameter.</description>
23368 <description>HDR-TS not supported</description>
23373 <description>HDR-TS supported</description>
23380 <description>Reflects the IC_CLK_PERIOD Configurable Parameter</description>
23387 <description>Reflects the IC_HDR_TX_CLK_PERIOD Configurable Parameter.</description>
23394 <description>Reflects the IC_HAS_DMA Configurable Parameter.</description>
23401 <description>Reflects the IC_SLV_HJ Configurable Parameter.</description>
23408 <description>Reflects the IC_SLV_IBI Configurable Parameter.</description>
23417 <description>Command Queue Port.</description>
23425 <description>32 bit command</description>
23434 <description>Response Queue Port</description>
23442 <description>32 bit Response</description>
23451 <description>Receive Data Port Register</description>
23459 <description>Receive Data Port.</description>
23468 <description>Transmit Data Port Register</description>
23477 <description>Transmit Data Port</description>
23486 <description>In-Band Interrupt Queue Data Register</description>
23494 <description>In-Band Interrupt Data</description>
23503 <description>In-Band Interrupt Queue Status Register</description>
23512 <description>In-Band Interrupt data length.</description>
23519 <description>IBI Identifier.</description>
23526 … <description>The acknowledge bit of the IBI Received Status (IBISTS) bitfield.</description>
23533 <description>Responded with ACK</description>
23538 <description>Responded with NACK</description>
23547 <description>Queue Threshold Control Register</description>
23555 <description>Command Buffer Empty Threshold Value.</description>
23561 <description>Response Buffer Threshold Value.</description>
23567 <description>In-Band Interrupt Status Threshold Value.</description>
23575 <description>Data Buffer Threshold Control Register</description>
23583 <description>Transmit Buffer Threshold Value</description>
23589 <description>Unspecified</description>
23594 <description>Unspecified</description>
23599 <description>Unspecified</description>
23604 <description>Unspecified</description>
23609 <description>Unspecified</description>
23614 <description>Unspecified</description>
23621 <description>Receive Buffer Threshold Value</description>
23627 <description>Unspecified</description>
23632 <description>Unspecified</description>
23637 <description>Unspecified</description>
23642 <description>Unspecified</description>
23647 <description>Unspecified</description>
23652 <description>Unspecified</description>
23659 <description>Transfer Start Threshold Value</description>
23665 <description>Unspecified</description>
23670 <description>Unspecified</description>
23675 <description>Unspecified</description>
23680 <description>Unspecified</description>
23685 <description>Unspecified</description>
23690 <description>Unspecified</description>
23697 <description>Receive Start Threshold Value</description>
23703 <description>Unspecified</description>
23708 <description>Unspecified</description>
23713 <description>Unspecified</description>
23718 <description>Unspecified</description>
23723 <description>Unspecified</description>
23728 <description>Unspecified</description>
23737 …<description>This Register is used to control whether or not to intimate the application if an IBI…
23745 <description>Notify Rejected Hot-Join Control.</description>
23751 <description>Unspecified</description>
23756 <description>Unspecified</description>
23763 <description>Notify Rejected Master Request Control.</description>
23769 …description>Suppress passing the IBI Status to the IBI FIFO (hence not notifying the application) …
23774 …description>Writes IBI Status to the IBI FIFO (hence notifying the application) when a MR Request …
23781 <description>Notify Rejected Slave Interrupt Request Control.</description>
23787 …description>Suppress passing the IBI Status to the IBI FIFO (hence not notifying the application) …
23792 …description>Writes IBI Status to the IBI FIFO (hence notifying the application) when a Slave Inter…
23801 <description>IBI Master Request Rejection Control Register.</description>
23809 <description>In-band Master Request Reject.</description>
23815 <description>ACK Master Request.</description>
23820 … <description>NACK and send Directed DISEC CCC to disable the interrupting slave.</description>
23829 <description>IBI SIR Request Rejection Control</description>
23837 <description>In-band Slave Interrupt Request Reject</description>
23843 <description>ACK the SIR Request.</description>
23848 <description>NACK and send directed auto disable CCC.</description>
23857 …<description>This Register is used for general software reset and for individual buffer reset.</de…
23865 <description>Core Software Reset.</description>
23871 <description>Command Queue Software Reset</description>
23877 <description>Response Queue Software Reset</description>
23883 <description>Transmit Buffer Software Reset</description>
23889 <description>Receive Buffer Software Reset.</description>
23895 <description>IBI Queue Software Reset.</description>
23901 <description>Bus Reset type</description>
23907 <description>Exit Pattern.</description>
23912 <description>SCL_LOW_RESET Pattern.</description>
23919 <description>Bus Reset.</description>
23927 …<description>This register indicates the status/values of some events/controls that are relavant t…
23935 <description>Slave Interrupt Request Enable.</description>
23942 <description>Master Request Enable.</description>
23949 <description>Hot-Join Interrupt Enable</description>
23955 <description>Activity State Status.</description>
23962 <description>Unspecified</description>
23967 <description>Unspecified</description>
23972 <description>Unspecified</description>
23977 <description>Unspecified</description>
23984 <description>MRL Updated Status.</description>
23990 <description>MWL Updated Status.</description>
23998 <description>Interrupt Status Register</description>
24006 <description>Transmit Buffer Threshold Status</description>
24013 <description>Receive Buffer Threshold Status.</description>
24020 <description>IBI Buffer Threshold Status.</description>
24027 <description>Command Queue Ready.</description>
24034 <description>Response Queue Ready Status.</description>
24041 <description>Transfer Abort Status.</description>
24047 <description>CCC Table Updated Status.</description>
24053 <description>Dynamic Address Assigned Status.</description>
24059 <description>Transfer Error Status.</description>
24065 <description>Define Slave CCC Received Status.</description>
24071 <description>Read Request Received.</description>
24077 <description>IBI status is updated.</description>
24083 …<description>This interrupt is set when the role of the controller changes from being a Master to …
24089 <description>Bus Reset Pattern Generation Done Status.</description>
24097 <description>Interrupt Status Enable Register.</description>
24105 <description>Transmit Buffer Threshold Status Enable.</description>
24111 <description>Receive Buffer Threshold Status Enable</description>
24117 <description>IBI Buffer Threshold Status Enable.</description>
24123 <description>Command Queue Ready Status Enable</description>
24129 <description>Response Queue Ready Status Enable</description>
24135 <description>Transfer Abort Status Enable.</description>
24141 <description>CCC Table Updated Status Enable.</description>
24147 <description>Dynamic Address Assigned Status Enable</description>
24153 <description>Transfer Error Status Enable</description>
24159 <description>Define Slave CCC Received Status Enable</description>
24165 <description>Read Request Received Status Enable</description>
24171 <description>IBI Updated Status Enable</description>
24177 <description>Bus owner Updated Status Enable</description>
24183 <description>Bus Reset Pattern Generation Done Status Enable.</description>
24191 <description>Interrupt Signal Enable Register</description>
24199 <description>Transmit Buffer Threshold Signal Enable</description>
24205 <description>Receive Buffer Threshold Signal Enable</description>
24211 <description>IBI Buffer Threshold Signal Enable</description>
24217 <description>Command Queue Ready Signal Enable</description>
24223 <description>Response Queue Ready Signal Enable</description>
24229 <description>Transfer Abort Signal Enable</description>
24235 <description>CCC Table Updated Signal Enable</description>
24241 <description>Dynamic Address Assigned Signal Enable</description>
24247 <description>Transfer Error Signal Enable</description>
24253 <description>Define Slave CCC Received Signal Enable</description>
24259 <description>Read Request Received Signal Enable</description>
24265 <description>IBI Updated Signal Enable</description>
24271 <description>Bus owner Updated Signal Enable</description>
24277 <description>Bus Reset Pattern Generation Done Signal Enable.</description>
24285 <description>Interrupt Force Enable Register</description>
24293 <description>Transmit Buffer Threshold Force Enable</description>
24300 <description>Receive Buffer Threshold Force Enable</description>
24307 <description>IBI Buffer Threshold Force Enable</description>
24314 <description>Command Queue Ready Force Enable</description>
24321 <description>Response Queue Ready Force Enable</description>
24328 <description>Transfer Abort Force Enable</description>
24335 <description>CCC Table Updated Force Enable</description>
24342 <description>Dynamic Address Assigned Force Enable</description>
24349 <description>Transfer Error Force Enable</description>
24356 <description>Define Slave CCC Received Force Enable</description>
24363 <description>Read Request Received Force Enable</description>
24370 <description>IBI Updated Force Enable</description>
24377 <description>Bus owner Updated Force Enable</description>
24384 <description>Bus Reset Pattern Generation Done Force Enable.</description>
24393 <description>Queue Status Level Register.</description>
24401 <description>Command Queue Empty Locations.</description>
24408 <description>Response Buffer Level Value.</description>
24415 <description>IBI Buffer Level Value.</description>
24422 <description>IBI Buffer Status Count.</description>
24431 <description>Data Buffer Status Level Register.</description>
24439 <description>Transmit Buffer Empty Level Value.</description>
24446 <description>Receive Buffer Level Value.</description>
24455 …<description>The user can get status of the DWC_mipi_i3c Controller from this 32-bit read only reg…
24463 …<description>This bit is used to check the SCL line level to recover from errors and for debugging…
24470 …<description>This bit is used to check the SDA line level to recover from errors and for debugging…
24477 … <description>This Bit is used to check whether the Master is Current Master or not.</description>
24484 <description>Master is not Current Master</description>
24489 <description>Master is Current Master</description>
24496 <description>Transfer Type Status</description>
24503 …<description>Controller is in Idle state, waiting for commands from application or Slave initated …
24508 <description>Broadcast CCC Write Transfer.</description>
24513 <description>Directed CCC Write Transfer.</description>
24518 <description>Directed CCC Read Transfer.</description>
24523 <description>ENTDAA Address Assignment Transfer.</description>
24528 <description>SETDASA Address Assignment Transfer.</description>
24533 <description>Private I3C SDR Write Transfer.</description>
24538 <description>Private I3C SDR Read Transfer.</description>
24543 <description>Private I2C SDR Write Transfer.</description>
24548 <description>Private I2C SDR Read Transfer.</description>
24553 <description>Private HDR Ternary Symbol(TS) Write Transfer.</description>
24558 <description>Private HDR Ternary Symbol(TS) Read Transfer.</description>
24563 <description>Private HDR Double-Data Rate(DDR) Write Transfer.</description>
24568 <description>Private HDR Double-Data Rate(DDR) Read Transfer.</description>
24573 <description>Servicing In-Band Interrupt Transfer.</description>
24578 …<description>Halt state. Controller is in Halt State, waiting for the application to resume throug…
24585 <description>Current Master Transfer State Status.</description>
24592 …<description>Controller is Idle state, waiting for commands from application or Slave initated In-…
24597 <description>START Generation State.</description>
24602 <description>RESTART Generation State.</description>
24607 <description>STOP Genration State.</description>
24612 … <description>START Hold Generation for the Slave Initiated START State.</description>
24617 … <description>Broadcast Write Address Header(7h7E,W) Generation State.</description>
24622 … <description>Broadcast Read Address Header(7h7E,R) Generation State.</description>
24627 <description>Dynamic Address Assignment State.</description>
24632 <description>Slave Address Generation State.</description>
24637 <description>CCC Byte Generation State.</description>
24642 <description>HDR Command Generation State.</description>
24647 <description>Write Data Transfer State.</description>
24652 <description>Read Data Transfer State.</description>
24657 <description>In-Band Interrupt(SIR) Read Data State.</description>
24662 <description>In-Band Interrupt Auto-Disable State</description>
24667 <description>HDR-DDR CRC Data Generation/Receive State.</description>
24672 <description>Clock Extension State.</description>
24677 <description>Halt State.</description>
24684 …<description>This field reflects the Transaction-ID of the current executing command.</description>
24691 …<description>This field reflects whether the Master Controller is in Idle state or not.</descripti…
24698 <description>Unspecified</description>
24703 <description>Unspecified</description>
24712 …<description>The user can get status of the DWC_mipi_i3c Controller from this 32-bit read only reg…
24721 …<description>This bit is used to check the SCL line level to recover from errors and for debugging…
24728 …<description>This bit is used to check the SDA line level to recover from errors and for debugging…
24735 … <description>This Bit is used to check whether the Master is Current Master or not.</description>
24742 <description>Master is not Current Master</description>
24747 <description>Master is Current Master</description>
24754 <description>Transfer Type Status</description>
24761 <description>Controller is in Idle state.</description>
24766 <description>Hot-Join transfer state.</description>
24771 <description>IBI transfer state.</description>
24776 <description>Master write transfer ongoing.</description>
24781 <description>Read data prefetch state.</description>
24786 <description>Master read transfer ongoing.</description>
24791 … <description>Slave controller in Halt State waiting for resume from application.</description>
24798 <description>Current Master Transfer State Status.</description>
24805 …<description>This field reflects the Transaction-ID of the current executing command.</description>
24812 …<description>This field reflects whether the Master Controller is in Idle state or not.</descripti…
24819 <description>Unspecified</description>
24824 <description>Unspecified</description>
24833 <description>Device Operating Status Register.</description>
24841 <description>Pending Interrupt</description>
24848 <description>Protocol Error</description>
24855 <description>Activity Mode</description>
24862 <description>Underflow error</description>
24869 <description>Slave Busy</description>
24876 <description>Overflow Error</description>
24883 <description>Data not ready</description>
24890 <description>Buffer not available</description>
24897 <description>Frame Error</description>
24906 <description>Pointer for Device Address Table</description>
24914 <description>Start Address of Device Address Table.</description>
24921 <description>Depth of Device Address Table</description>
24930 <description>Pointer for Device Characteristics Table</description>
24938 <description>Start Address of Device Characteristics Table.</description>
24945 <description>Depth of Device Characteristics Table</description>
24952 <description>Current index of Device Characteristics Table.</description>
24960 <description>Pointer for Vendor Specific Registers.</description>
24968 <description>Start Address of Vendor specific registers.</description>
24977 <description>I3C MIPI Manufacturer ID Register.</description>
24985 <description>Specifies the Provisional ID Type Selector (PID[32]).</description>
24991 <description>Specifies the MIPI Manufacturer ID.</description>
24999 <description>I3C Normal Provisional ID Register.</description>
25007 … <description>Specifies the additional 12-bit ID of DWC_mipi_i3c device (PID[11:0]).</description>
25013 … <description>This field is used to program the instance ID of the Slave.</description>
25019 <description>Specifies the Part ID of DWC_mipi_i3c device (PID[31:16])</description>
25027 <description>I3C Slave Characteristic Register.</description>
25035 …<description>Max Data Speed Limitation field in Bus Characteristic Register (BCR[0]).</description>
25041 … <description>IBI Request Capable field in Bus Characteristic Register (BCR[1]).</description>
25048 … <description>IBI Payload field in Bus Characteristic Register (BCR[2]).</description>
25055 … <description>Offline Capable field in Bus Characteristic Register (BCR[3]).</description>
25062 … <description>Bridge Identifier field in Bus Characteristic Register (BCR[4]).</description>
25069 …<description>SDR Only or SDR and HDR Capable field in Bus Characteristic Register (BCR[5]).</descr…
25075 … <description>Device Role field in Bus Characteristic Register (BCR[7:6]).</description>
25081 <description>I3C Device Characteristic Value.</description>
25087 <description>I3C Device HDR Capability Register Value.</description>
25096 <description>I3C Max Write/Read Length Register.</description>
25104 <description>I3C Device Max Write Length</description>
25111 <description>I3C Device Max Read Length.</description>
25120 <description>MXDS Maximum Read Turnaround Time.</description>
25128 …<description>Specifies the maximum read turnaround time (in microseconds (us)) of DWC_mipi_i3c Sla…
25137 …<description>The values in this register are returned by the slave as GETACCMST CCC data.</descrip…
25145 …<description>Specifies the Maximum Sustained Data Rate for non-CCC messages sent by Master Device …
25151 <description>12.5MHz</description>
25156 <description>8MHZ</description>
25161 <description>6MHz</description>
25166 <description>4MHz</description>
25171 <description>2MHz</description>
25178 …<description>Specifies the Maximum Sustained Data Rate for non-CCC messages sent by DWC_mipi_i3c S…
25184 <description>12.5MHz</description>
25189 <description>8MHZ</description>
25194 <description>6MHz</description>
25199 <description>4MHz</description>
25204 <description>2MHz</description>
25211 …<description>Specifies the clock to data turnaround time (Tsco parameter) of DWC_mipi_i3c Slave de…
25217 <description>8ns</description>
25222 <description>9ns</description>
25227 <description>10ns</description>
25232 <description>11ns</description>
25237 <description>12ns</description>
25246 <description>This register is used in slave mode of operation.</description>
25254 <description>Slave Interrupt Request</description>
25260 <description>Slave Interrupt Request Control</description>
25266 <description>Send the Assigned Dynamic Address</description>
25273 <description>Master Request</description>
25279 <description>IBI Completion Status</description>
25286 <description>IBI accepted by the Master (ACK response received)</description>
25291 <description>IBI Not Attempted</description>
25300 <description>TSP/TSL Symbol Timing Register</description>
25308 <description>TSP/TSL Symbol Count Value.</description>
25316 <description>Device Control Extended register.</description>
25324 …<description>This bit is used to select the Device Operation Mode before the controller is enabled…
25330 <description>Unspecified</description>
25335 <description>Unspecified</description>
25342 …<description>In Slave mode of operation, this bit serves as a control to ACK/NACK GETACCMST CCC fr…
25348 <description>ACK GETACCMST CCC</description>
25353 <description>NACK GETACCMST CCC</description>
25362 <description>SCL I3C Open Drain Timing Register</description>
25370 <description>I3C Open Drain Low Count.</description>
25376 <description>I3C Open Drain High Count.</description>
25384 <description>SCL I3C Push Pull Timing Register</description>
25392 <description>I3C Push Pull Low Count.</description>
25398 <description>I3C Push Pull High Count.</description>
25406 <description>SCL I2C Fast Mode Timing Register</description>
25414 <description>I2C Fast Mode Low Count</description>
25420 <description>I2C Fast Mode High Count</description>
25428 <description>SCL I2C Fast Mode Plus Timing Register</description>
25436 <description>I2C Fast Mode Plus Low Count</description>
25442 <description>I2C Fast Mode Plus High Count</description>
25450 <description>SCL Extended Low Count Timing Register.</description>
25458 <description>I3C Extended Low Count Register 1</description>
25464 <description>I3C Extended Low Count Register 2</description>
25470 <description>I3C Extended Low Count Register 3</description>
25476 <description>I3C Extended Low Count Register 4</description>
25484 <description>SCL Termination Bit Low Count Timing Register</description>
25492 <description>I3C Read Termination Bit Low count.</description>
25498 <description>I3C HDR Ternary Skew Count.</description>
25506 <description>SDA Hold and Mode Switch Delay Timing Register</description>
25514 …<description>This field controls the hold time (in term of the core clock period) of the transmit …
25522 <description>Bus Free and Available Timing Register</description>
25530 … <description>This register field is used only in Master mode of operation</description>
25536 … <description>This register field is used only in Slave mode of operation</description>
25544 <description>Bus Idle Timing Register</description>
25552 <description>Bus Idle Count Value.</description>
25560 …<description>The SCL Low Master Extended Timeout register is used to define the duration of the SC…
25568 …<description>This count defines the number of core clock periods to count for generation of the SC…
25576 … <description>This register reflects the current release number of DWC_mipi_i3c</description>
25584 <description>Current release number</description>
25593 … <description>This register reflects the current release type of DWC_mipi_i3c.</description>
25601 <description>Current release type</description>
25610 …<description>This register reflects the configured size of the Data Buffer and Queues in DWC_mipi_…
25618 <description>Transmit Data Buffer Size</description>
25625 <description>2 DWORDS</description>
25630 <description>4 DWORDS</description>
25635 <description>8 DWORDS</description>
25640 <description>16 DWORDS</description>
25645 <description>32 DWORDS</description>
25650 <description>64 DWORDS</description>
25657 <description>Receive Data Buffer Size</description>
25664 <description>2 DWORDS</description>
25669 <description>4 DWORDS</description>
25674 <description>8 DWORDS</description>
25679 <description>16 DWORDS</description>
25684 <description>32 DWORDS</description>
25689 <description>64 DWORDS</description>
25696 <description>Command Queue Size</description>
25703 <description>2 DWORDS</description>
25708 <description>4 DWORDS</description>
25713 <description>8 DWORDS</description>
25718 <description>16 DWORDS</description>
25725 <description>Response Queue Size</description>
25732 <description>2 DWORDS</description>
25737 <description>4 DWORDS</description>
25742 <description>8 DWORDS</description>
25747 <description>16 DWORDS</description>
25754 <description>IBI Queue Size</description>
25761 <description>2 DWORDS</description>
25766 <description>4 DWORDS</description>
25771 <description>8 DWORDS</description>
25776 <description>16 DWORDS</description>
25787 <description>Unspecified</description>
25793 …<description>Description cluster: Device Characteristic Table Location-1 of Device [n]</descriptio…
25801 <description>The LSB 32-bit value of Provisional-ID</description>
25810 …<description>Description cluster: Device Characteristic Table Location-2 of Device [n]</descriptio…
25818 <description>The MSB 16-bit value of Provisional-ID</description>
25827 …<description>Description cluster: Device Characteristic Table Location-3 of Device [n]</descriptio…
25835 <description>Device Characteristic Value</description>
25842 <description>Bus Characteristic Value</description>
25851 …<description>Description cluster: Device Characteristic Table Location-4 of Device [n]</descriptio…
25859 <description>Device Dynamic Address assigned.</description>
25871 …<description>Description collection: Secondary Master Device Characteristic Table Location of Devi…
25879 <description>The Dynamic Addr of Device [n]</description>
25886 <description>The DCR TYPE of Device [n]</description>
25893 <description>The BCR TYPE of Device [n]</description>
25900 <description>The Static Addr of Device [n]</description>
25911 <description>Description collection: Device Address Table of Device [n]</description>
25919 <description>Device Static Address.</description>
25925 <description>Device Dynamic Address with parity.</description>
25931 …<description>This field is used to set the Device NACK Retry count for the particular device.</des…
25937 <description>Legacy I2C device or not.</description>
25946 <description>Unspecified</description>
25952 <description>Unspecified</description>
25958 … <description>This register contains the source address of the DMA transfer.</description>
25966 <description>Current Source Address of DMA transfer.</description>
25974 … <description>This register contains the destination address of the DMA transfer.</description>
25982 <description>Current Destination address of DMA transfer.</description>
25990 … <description>This register contains fields that control the DMA transfer.</description>
25998 <description>Interrupt Enable Bit.</description>
26004 <description>Unspecified</description>
26009 <description>Unspecified</description>
26016 <description>Destination Transfer Width.</description>
26022 <description>Unspecified</description>
26027 <description>Unspecified</description>
26032 <description>Unspecified</description>
26037 <description>Unspecified</description>
26042 <description>Unspecified</description>
26047 <description>Unspecified</description>
26052 <description>Unspecified</description>
26057 <description>Unspecified</description>
26064 <description>Reserved field - read-only</description>
26071 <description>Destination Address Increment.</description>
26077 <description>Unspecified</description>
26082 <description>Unspecified</description>
26087 <description>Unspecified</description>
26092 <description>Unspecified</description>
26099 <description>Source Address Increment.</description>
26105 <description>Unspecified</description>
26110 <description>Unspecified</description>
26115 <description>Unspecified</description>
26120 <description>Unspecified</description>
26127 <description>Destination Burst Transaction Length.</description>
26133 <description>Unspecified</description>
26138 <description>Unspecified</description>
26143 <description>Unspecified</description>
26148 <description>Unspecified</description>
26153 <description>Unspecified</description>
26158 <description>Unspecified</description>
26163 <description>Unspecified</description>
26168 <description>Unspecified</description>
26175 <description>Source Burst Transaction Length.</description>
26181 <description>Unspecified</description>
26186 <description>Unspecified</description>
26191 <description>Unspecified</description>
26196 <description>Unspecified</description>
26201 <description>Unspecified</description>
26206 <description>Unspecified</description>
26211 <description>Unspecified</description>
26216 <description>Unspecified</description>
26223 <description>Reserved field - read-only</description>
26230 <description>Destination scatter enable.</description>
26236 <description>Unspecified</description>
26241 <description>Unspecified</description>
26248 <description>Reserved field - read-only</description>
26255 <description>Transfer Type and Flow Control.</description>
26261 <description>Unspecified</description>
26266 <description>Unspecified</description>
26271 <description>Unspecified</description>
26276 <description>Unspecified</description>
26281 <description>Unspecified</description>
26286 <description>Unspecified</description>
26291 <description>Unspecified</description>
26296 <description>Unspecified</description>
26303 <description>Reserved field - read-only</description>
26310 <description>Reserved field - read-only</description>
26317 <description>Reserved field - read-only</description>
26324 <description>Reserved field - read-only</description>
26331 <description>Reserved field - read-only</description>
26340 … <description>This register contains fields that control the DMA transfer.</description>
26348 <description>Block Transfer Size.</description>
26354 <description>Reserved field - read-only</description>
26361 <description>Done bit.</description>
26367 <description>Unspecified</description>
26372 <description>Unspecified</description>
26381 … <description>This register contains fields that configure the DMA transfer.</description>
26389 <description>Reserved field - read-only</description>
26396 <description>Channel Priority.</description>
26402 <description>Unspecified</description>
26407 <description>Unspecified</description>
26412 <description>Unspecified</description>
26417 <description>Unspecified</description>
26422 <description>Unspecified</description>
26427 <description>Unspecified</description>
26432 <description>Unspecified</description>
26437 <description>Unspecified</description>
26444 <description>Channel Suspend.</description>
26450 <description>Unspecified</description>
26455 <description>Unspecified</description>
26462 <description>Channel FIFO status.</description>
26469 <description>Unspecified</description>
26474 <description>Unspecified</description>
26481 <description>Destination Software or Hardware Handshaking Select.</description>
26487 <description>Unspecified</description>
26492 <description>Unspecified</description>
26499 <description>Source Software or Hardware Handshaking Select.</description>
26505 <description>Unspecified</description>
26510 <description>Unspecified</description>
26517 <description>Reserved field - read-only</description>
26524 <description>Reserved field - read-only</description>
26531 <description>Reserved field - read-only</description>
26538 <description>Reserved field - read-only</description>
26545 <description>Destination Handshaking Interface Polarity.</description>
26551 <description>Unspecified</description>
26556 <description>Unspecified</description>
26563 <description>Source Handshaking Interface Polarity.</description>
26569 <description>Unspecified</description>
26574 <description>Unspecified</description>
26581 <description>Maximum AMBA Burst Length.</description>
26587 <description>Reserved field - read-only</description>
26594 <description>Reserved field- read-only</description>
26603 … <description>This register contains fields that configure the DMA transfer.</description>
26611 <description>Flow Control Mode.</description>
26617 <description>Unspecified</description>
26622 <description>Unspecified</description>
26629 <description>FIFO Mode Select.</description>
26635 <description>Unspecified</description>
26640 <description>Unspecified</description>
26647 … <description>Protection Control bits used to drive the AHB HPROT[3:1] bus.</description>
26653 <description>Reserved field- read-only</description>
26660 <description>Reserved field- read-only</description>
26667 <description>Source Hardware Interface.</description>
26673 <description>Reserved field - read-only</description>
26680 <description>Destination hardware interface.</description>
26686 <description>Reserved field - read-only</description>
26693 <description>Reserved field - read-only</description>
26702 <description>Destination Scatter register.</description>
26710 <description>Destination Scatter Interval.</description>
26716 <description>Destination Scatter Count.</description>
26725 <description>Unspecified</description>
26731 … <description>This register contains the source address of the DMA transfer.</description>
26739 <description>Current Source Address of DMA transfer.</description>
26747 … <description>This register contains the destination address of the DMA transfer.</description>
26755 <description>Current Destination address of DMA transfer.</description>
26763 … <description>This register contains fields that control the DMA transfer.</description>
26771 <description>Interrupt Enable Bit.</description>
26777 <description>Unspecified</description>
26782 <description>Unspecified</description>
26789 <description>Reserved field - read-only</description>
26796 <description>Source Transfer Width.</description>
26802 <description>Unspecified</description>
26807 <description>Unspecified</description>
26812 <description>Unspecified</description>
26817 <description>Unspecified</description>
26822 <description>Unspecified</description>
26827 <description>Unspecified</description>
26832 <description>Unspecified</description>
26837 <description>Unspecified</description>
26844 <description>Destination Address Increment.</description>
26850 <description>Unspecified</description>
26855 <description>Unspecified</description>
26860 <description>Unspecified</description>
26865 <description>Unspecified</description>
26872 <description>Source Address Increment.</description>
26878 <description>Unspecified</description>
26883 <description>Unspecified</description>
26888 <description>Unspecified</description>
26893 <description>Unspecified</description>
26900 <description>Destination Burst Transaction Length.</description>
26906 <description>Unspecified</description>
26911 <description>Unspecified</description>
26916 <description>Unspecified</description>
26921 <description>Unspecified</description>
26926 <description>Unspecified</description>
26931 <description>Unspecified</description>
26936 <description>Unspecified</description>
26941 <description>Unspecified</description>
26948 <description>Source Burst Transaction Length.</description>
26954 <description>Unspecified</description>
26959 <description>Unspecified</description>
26964 <description>Unspecified</description>
26969 <description>Unspecified</description>
26974 <description>Unspecified</description>
26979 <description>Unspecified</description>
26984 <description>Unspecified</description>
26989 <description>Unspecified</description>
26996 <description>Source gather enable.</description>
27002 <description>Unspecified</description>
27007 <description>Unspecified</description>
27014 <description>Reserved field - read-only</description>
27021 <description>Reserved field - read-only</description>
27028 <description>Transfer Type and Flow Control.</description>
27034 <description>Unspecified</description>
27039 <description>Unspecified</description>
27044 <description>Unspecified</description>
27049 <description>Unspecified</description>
27054 <description>Unspecified</description>
27059 <description>Unspecified</description>
27064 <description>Unspecified</description>
27069 <description>Unspecified</description>
27076 <description>Reserved field - read-only</description>
27083 <description>Reserved field - read-only</description>
27090 <description>Reserved field - read-only</description>
27097 <description>Reserved field - read-only</description>
27104 <description>Reserved field - read-only</description>
27113 … <description>This register contains fields that control the DMA transfer.</description>
27121 <description>Block Transfer Size.</description>
27127 <description>Reserved field - read-only</description>
27134 <description>Done bit.</description>
27140 <description>Unspecified</description>
27145 <description>Unspecified</description>
27154 … <description>This register contains fields that configure the DMA transfer.</description>
27162 <description>Reserved field - read-only</description>
27169 <description>Channel Priority.</description>
27175 <description>Unspecified</description>
27180 <description>Unspecified</description>
27185 <description>Unspecified</description>
27190 <description>Unspecified</description>
27195 <description>Unspecified</description>
27200 <description>Unspecified</description>
27205 <description>Unspecified</description>
27210 <description>Unspecified</description>
27217 <description>Channel Suspend.</description>
27223 <description>Unspecified</description>
27228 <description>Unspecified</description>
27235 <description>Channel FIFO status.</description>
27242 <description>Unspecified</description>
27247 <description>Unspecified</description>
27254 <description>Destination Software or Hardware Handshaking Select.</description>
27260 <description>Unspecified</description>
27265 <description>Unspecified</description>
27272 <description>Source Software or Hardware Handshaking Select.</description>
27278 <description>Unspecified</description>
27283 <description>Unspecified</description>
27290 <description>Reserved field - read-only</description>
27297 <description>Reserved field - read-only</description>
27304 <description>Reserved field - read-only</description>
27311 <description>Reserved field - read-only</description>
27318 <description>Destination Handshaking Interface Polarity.</description>
27324 <description>Unspecified</description>
27329 <description>Unspecified</description>
27336 <description>Source Handshaking Interface Polarity.</description>
27342 <description>Unspecified</description>
27347 <description>Unspecified</description>
27354 <description>Maximum AMBA Burst Length.</description>
27360 <description>Reserved field - read-only</description>
27367 <description>Reserved field- read-only</description>
27376 … <description>This register contains fields that configure the DMA transfer.</description>
27384 <description>Flow Control Mode.</description>
27390 <description>Unspecified</description>
27395 <description>Unspecified</description>
27402 <description>FIFO Mode Select.</description>
27408 <description>Unspecified</description>
27413 <description>Unspecified</description>
27420 … <description>Protection Control bits used to drive the AHB HPROT[3:1] bus.</description>
27426 <description>Reserved field- read-only</description>
27433 <description>Reserved field- read-only</description>
27440 <description>Source Hardware Interface.</description>
27446 <description>Reserved field - read-only</description>
27453 <description>Destination hardware interface.</description>
27461 <description>Source Gather register</description>
27469 <description>Source Gather Interval.</description>
27475 <description>Source Gather Count.</description>
27484 <description>Unspecified</description>
27490 …<description>Interrupt events are stored in this Raw Interrupt Status register before masking.</de…
27498 <description>Raw Status for IntTfr Interrupt</description>
27504 <description>Unspecified</description>
27509 <description>Unspecified</description>
27518 …<description>Interrupt events are stored in this Raw Interrupt Status register before masking.</de…
27526 <description>Raw Status for IntBlock Interrupt</description>
27532 <description>Unspecified</description>
27537 <description>Unspecified</description>
27546 …<description>Interrupt events are stored in this Raw Interrupt Status register before masking.</de…
27554 <description>Raw Status for IntSrcTran Interrupt</description>
27560 <description>Unspecified</description>
27565 <description>Unspecified</description>
27574 …<description>Interrupt events are stored in this Raw Interrupt Status register before masking.</de…
27582 <description>Raw Status for IntDstTran Interrupt</description>
27588 <description>Unspecified</description>
27593 <description>Unspecified</description>
27602 …<description>Interrupt events are stored in this Raw Interrupt Status register before masking.</de…
27610 <description>Raw Status for IntErr Interrupt</description>
27616 <description>Unspecified</description>
27621 <description>Unspecified</description>
27630 …<description>Channel DMA Transfer complete interrupt event from all channels is stored in this Int…
27638 <description>Status for IntTfr Interrupt</description>
27645 <description>Unspecified</description>
27650 <description>Unspecified</description>
27659 …<description>Channel Block complete interrupt event from all channels is stored in this Interrupt …
27667 <description>Status for IntBlock Interrupt</description>
27674 <description>Unspecified</description>
27679 <description>Unspecified</description>
27688 …description>Channel Source Transaction complete interrupt event from all channels is stored in thi…
27696 <description>Status for IntSrcTran Interrupt</description>
27703 <description>Unspecified</description>
27708 <description>Unspecified</description>
27717 …description>Channel destination transaction complete interrupt event from all channels is stored i…
27725 <description>Status for IntDstTran Interrupt</description>
27732 <description>Unspecified</description>
27737 <description>Unspecified</description>
27746 …<description>Channel Error interrupt event from all channels is stored in this Interrupt Status re…
27754 <description>Status for IntErr Interrupt</description>
27761 <description>Unspecified</description>
27766 <description>Unspecified</description>
27775 …<description>The contents of the Raw Status register RawTfr is masked with the contents of the Mas…
27783 <description>Mask for IntTfr Interrupt</description>
27789 <description>Unspecified</description>
27794 <description>Unspecified</description>
27801 <description>Reserved field - read-only</description>
27808 <description>Interrupt Mask Write Enable</description>
27815 <description>Unspecified</description>
27820 <description>Unspecified</description>
27829 …<description>The contents of the Raw Status register RawBlock is masked with the contents of the M…
27837 <description>Mask for IntBlock Interrupt</description>
27843 <description>Unspecified</description>
27848 <description>Unspecified</description>
27855 <description>Reserved field- read-only</description>
27862 <description>Interrupt Mask Write Enable</description>
27869 <description>Unspecified</description>
27874 <description>Unspecified</description>
27883 …<description>The contents of the Raw Status register RawSrcTran is masked with the contents of the…
27891 <description>Mask for IntSrcTran Interrupt</description>
27897 <description>Unspecified</description>
27902 <description>Unspecified</description>
27909 <description>Reserved field- read-only</description>
27916 <description>Interrupt Mask Write Enable</description>
27923 <description>Unspecified</description>
27928 <description>Unspecified</description>
27937 …<description>The contents of the Raw Status register RawDstTran is masked with the contents of the…
27945 <description>Mask for IntDstTran Interrupt</description>
27951 <description>Unspecified</description>
27956 <description>Unspecified</description>
27963 <description>Reserved field - read-only</description>
27970 <description>Interrupt Mask Write Enable</description>
27977 <description>Unspecified</description>
27982 <description>Unspecified</description>
27991 …<description>The contents of the Raw Status register RawErr is masked with the contents of the Mas…
27999 <description>Mask for IntErr Interrupt</description>
28005 <description>Unspecified</description>
28010 <description>Unspecified</description>
28017 <description>Reserved field- read-only</description>
28024 <description>Interrupt Mask Write Enable</description>
28031 <description>Unspecified</description>
28036 <description>Unspecified</description>
28045 …description>Each bit in the RawTfr and StatusTfr is cleared on the same cycle by writing a 1 to th…
28053 <description>Clear for IntTfr Interrupt</description>
28060 <description>Unspecified</description>
28065 <description>Unspecified</description>
28074 …description>Each bit in the RawBlock and StatusBlock is cleared on the same cycle by writing a 1 t…
28082 <description>Clear for IntBlock Interrupt</description>
28091 …description>Each bit in the RawSrcTran and StatusSrcTran is cleared on the same cycle by writing a…
28099 <description>Clear for IntSrcTran Interrupt</description>
28106 <description>Unspecified</description>
28111 <description>Unspecified</description>
28120 …description>Each bit in the RawDstTran and StatusDstTran is cleared on the same cycle by writing a…
28128 <description>Clear for IntDstTran Interrupt</description>
28135 <description>Unspecified</description>
28140 <description>Unspecified</description>
28149 …description>Each bit in the RawErr and StatusErr is cleared on the same cycle by writing a 1 to th…
28157 <description>Clear for IntErr Interrupt</description>
28164 <description>Unspecified</description>
28169 <description>Unspecified</description>
28178 …description>The contents of each of the five Status registers StatusTfr, StatusBlock, StatusSrcTr…
28186 <description>OR of the contents of StatusTfr register</description>
28193 <description>Unspecified</description>
28198 <description>Unspecified</description>
28205 <description>OR of the contents of StatusBlock register</description>
28212 <description>Unspecified</description>
28217 <description>Unspecified</description>
28224 <description>OR of the contents of StatusSrcTran</description>
28231 <description>Unspecified</description>
28236 <description>Unspecified</description>
28243 <description>OR of the contents of StatusDstTran</description>
28250 <description>Unspecified</description>
28255 <description>Unspecified</description>
28262 <description>OR of the contents of StatusErr</description>
28269 <description>Unspecified</description>
28274 <description>Unspecified</description>
28284 <description>Unspecified</description>
28290 <description>A bit is assigned for each channel in this register.</description>
28298 <description>Source Software Transaction Request</description>
28304 <description>Unspecified</description>
28309 <description>Unspecified</description>
28316 <description>Reserved field - read-only</description>
28323 <description>Source Software Transaction Request write enable</description>
28330 <description>Unspecified</description>
28335 <description>Unspecified</description>
28344 <description>A bit is assigned for each channel in this register.</description>
28352 <description>Destination Software Transaction Request</description>
28358 <description>Unspecified</description>
28363 <description>Unspecified</description>
28370 <description>Reserved field - read-only</description>
28377 <description>Destination Software Transaction Request write enable</description>
28384 <description>Unspecified</description>
28389 <description>Unspecified</description>
28398 <description>A bit is assigned for each channel in this register.</description>
28406 <description>Source Single Transaction Request</description>
28412 <description>Unspecified</description>
28417 <description>Unspecified</description>
28424 <description>Reserved field - read-only</description>
28431 <description>Source Single Transaction Request write enable</description>
28438 <description>Unspecified</description>
28443 <description>Unspecified</description>
28452 <description>A bit is assigned for each channel in this register.</description>
28460 <description>Destination Single Transaction Request</description>
28466 <description>Unspecified</description>
28471 <description>Unspecified</description>
28478 <description>Reserved field - read-only</description>
28485 <description>Destination Single Transaction Request write enable</description>
28492 <description>Unspecified</description>
28497 <description>Unspecified</description>
28506 <description>A bit is assigned for each channel in this register.</description>
28514 <description>Source Last Transaction Request register</description>
28520 <description>Unspecified</description>
28525 <description>Unspecified</description>
28532 <description>Reserved field- read-only</description>
28539 <description>Source Last Transaction Request write enable</description>
28546 <description>Unspecified</description>
28551 <description>Unspecified</description>
28560 <description>A bit is assigned for each channel in this register.</description>
28568 <description>Destination Last Transaction Request</description>
28574 <description>Unspecified</description>
28579 <description>Unspecified</description>
28586 <description>Reserved field - read-only</description>
28593 <description>Source Last Transaction Request write enable</description>
28600 <description>Unspecified</description>
28605 <description>Unspecified</description>
28615 <description>Unspecified</description>
28621 …<description>This register is used to enable the DW_ahb_dmac, which must be done before any channe…
28629 <description>DW_ahb_dmac Enable bit.</description>
28635 <description>Unspecified</description>
28640 <description>Unspecified</description>
28649 <description>This is the DW_ahb_dmac Channel Enable Register.</description>
28657 <description>Channel Enable.</description>
28663 <description>Unspecified</description>
28668 <description>Unspecified</description>
28675 <description>Reserved field - read-only</description>
28682 <description>Channel enable register</description>
28691 …description>This is the DW_ahb_dmac ID register, which is a read-only register that reads back the…
28699 <description>Hardcoded DW_ahb_dmac peripheral ID.</description>
28708 …description>This register is used to put the AHB slave interface into test mode, during which the …
28716 <description>DMA Test register</description>
28722 <description>Unspecified</description>
28727 <description>Unspecified</description>
28736 <description>This register holds the timeout value of Low Power Counter.</description>
28744 … <description>This field holds timeout value of low power counter register.</description>
28752 …description>DMA_COMP_PARAMS_6L is a constant read-only register that contains encoded information …
28760 …<description>The value of this register is derived from the DMAH_CH7_DTW coreConsultant parameter.…
28767 <description>Unspecified</description>
28772 <description>Unspecified</description>
28777 <description>Unspecified</description>
28782 <description>Unspecified</description>
28787 <description>Unspecified</description>
28792 <description>Unspecified</description>
28797 <description>Unspecified</description>
28804 …<description>The value of this register is derived from the DMAH_CH7_STW coreConsultant parameter.…
28811 <description>Unspecified</description>
28816 <description>Unspecified</description>
28821 <description>Unspecified</description>
28826 <description>Unspecified</description>
28831 <description>Unspecified</description>
28836 <description>Unspecified</description>
28841 <description>Unspecified</description>
28848 …<description>The value of this register is derived from the DMAH_CH7_STAT_DST coreConsultant param…
28855 <description>Unspecified</description>
28860 <description>Unspecified</description>
28867 …<description>The value of this register is derived from the DMAH_CH7_STAT_SRC coreConsultant param…
28874 <description>Unspecified</description>
28879 <description>Unspecified</description>
28886 …<description>The value of this register is derived from the DMAH_CH7_DST_SCA_EN coreConsultant par…
28893 <description>Unspecified</description>
28898 <description>Unspecified</description>
28905 …<description>The value of this register is derived from the DMAH_CH7_SRC_GAT_EN coreConsultant par…
28912 <description>Unspecified</description>
28917 <description>Unspecified</description>
28924 …<description>The value of this register is derived from the DMAH_CH7_LOCK_EN coreConsultant parame…
28931 <description>Unspecified</description>
28936 <description>Unspecified</description>
28943 …<description>The value of this register is derived from the DMAH_CH7_MULTI_BLK_EN coreConsultant p…
28950 <description>Unspecified</description>
28955 <description>Unspecified</description>
28962 …<description>The value of this register is derived from the DMAH_CH7_CTL_WB_EN coreConsultant para…
28969 <description>Unspecified</description>
28974 <description>Unspecified</description>
28981 …<description>The value of this register is derived from the DMAH_CH7_HC_LLP coreConsultant paramet…
28988 <description>Unspecified</description>
28993 <description>Unspecified</description>
29000 …<description>The value of this register is derived from the DMAH_CH7_FC coreConsultant parameter.<…
29007 <description>Unspecified</description>
29012 <description>Unspecified</description>
29017 <description>Unspecified</description>
29022 <description>Unspecified</description>
29029 …<description>The value of this register is derived from the DMAH_CH7_MULT_SIZE coreConsultant para…
29036 <description>Unspecified</description>
29041 <description>Unspecified</description>
29046 <description>Unspecified</description>
29051 <description>Unspecified</description>
29056 <description>Unspecified</description>
29061 <description>Unspecified</description>
29066 <description>Unspecified</description>
29073 …<description>The value of this register is derived from the DMAH_CH7_DMS coreConsultant parameter.…
29080 <description>Unspecified</description>
29085 <description>Unspecified</description>
29090 <description>Unspecified</description>
29095 <description>Unspecified</description>
29100 <description>Unspecified</description>
29107 …<description>The value of this register is derived from the DMAH_CH7_LMS coreConsultant parameter.…
29114 <description>Unspecified</description>
29119 <description>Unspecified</description>
29124 <description>Unspecified</description>
29129 <description>Unspecified</description>
29134 <description>Unspecified</description>
29141 …<description>The value of this register is derived from the DMAH_CH7_SMS coreConsultant parameter.…
29148 <description>Unspecified</description>
29153 <description>Unspecified</description>
29158 <description>Unspecified</description>
29163 <description>Unspecified</description>
29168 <description>Unspecified</description>
29175 …<description>The value of this register is derived from the DMAH_CH7_FIFO_DEPTH coreConsultant par…
29182 <description>Unspecified</description>
29187 <description>Unspecified</description>
29192 <description>Unspecified</description>
29197 <description>Unspecified</description>
29202 <description>Unspecified</description>
29207 <description>Unspecified</description>
29216 …description>DMA_COMP_PARAMS_5 is a constant read-only register that contains encoded information a…
29224 …<description>The value of this register is derived from the DMAH_CH6_DTW coreConsultant parameter.…
29231 <description>Unspecified</description>
29236 <description>Unspecified</description>
29241 <description>Unspecified</description>
29246 <description>Unspecified</description>
29251 <description>Unspecified</description>
29256 <description>Unspecified</description>
29261 <description>Unspecified</description>
29268 …<description>The value of this register is derived from the DMAH_CH6_STW coreConsultant parameter.…
29275 <description>Unspecified</description>
29280 <description>Unspecified</description>
29285 <description>Unspecified</description>
29290 <description>Unspecified</description>
29295 <description>Unspecified</description>
29300 <description>Unspecified</description>
29305 <description>Unspecified</description>
29312 …<description>The value of this register is derived from the DMAH_CH6_STAT_DST coreConsultant param…
29319 <description>Unspecified</description>
29324 <description>Unspecified</description>
29331 …<description>The value of this register is derived from the DMAH_CH6_STAT_SRC coreConsultant param…
29338 <description>Unspecified</description>
29343 <description>Unspecified</description>
29350 …<description>The value of this register is derived from the DMAH_CH6_DST_SCA_EN coreConsultant par…
29357 <description>Unspecified</description>
29362 <description>Unspecified</description>
29369 …<description>The value of this register is derived from the CH6_SRC_GAT_EN coreConsultant paramete…
29376 <description>Unspecified</description>
29381 <description>Unspecified</description>
29388 …<description>The value of this register is derived from the DMAH_CH6_LOCK_EN coreConsultant parame…
29395 <description>Unspecified</description>
29400 <description>Unspecified</description>
29407 …<description>The value of this register is derived from the DMAH_CH6_MULTI_BLK_EN coreConsultant p…
29414 <description>Unspecified</description>
29419 <description>Unspecified</description>
29426 …<description>The value of this register is derived from the DMAH_CH6_CTL_WB_EN coreConsultant para…
29433 <description>Unspecified</description>
29438 <description>Unspecified</description>
29445 …<description>The value of this register is derived from the DMAH_CH6_HC_LLP coreConsultant paramet…
29452 <description>Unspecified</description>
29457 <description>Unspecified</description>
29464 …<description>The value of this register is derived from the DMAH_CH6_FC coreConsultant parameter.<…
29471 <description>Unspecified</description>
29476 <description>Unspecified</description>
29481 <description>Unspecified</description>
29486 <description>Unspecified</description>
29493 …<description>The value of this register is derived from the DMAH_CH6_MULT_SIZE coreConsultant para…
29500 <description>Unspecified</description>
29505 <description>Unspecified</description>
29510 <description>Unspecified</description>
29515 <description>Unspecified</description>
29520 <description>Unspecified</description>
29525 <description>Unspecified</description>
29530 <description>Unspecified</description>
29537 …<description>The value of this register is derived from the DMAH_CH6_DMS coreConsultant parameter.…
29544 <description>Unspecified</description>
29549 <description>Unspecified</description>
29554 <description>Unspecified</description>
29559 <description>Unspecified</description>
29564 <description>Unspecified</description>
29571 …<description>The value of this register is derived from the DMAH_CH6_LMS coreConsultant parameter.…
29578 <description>Unspecified</description>
29583 <description>Unspecified</description>
29588 <description>Unspecified</description>
29593 <description>Unspecified</description>
29598 <description>Unspecified</description>
29605 …<description>The value of this register is derived from the DMAH_CH6_SMS coreConsultant parameter.…
29612 <description>Unspecified</description>
29617 <description>Unspecified</description>
29622 <description>Unspecified</description>
29627 <description>Unspecified</description>
29632 <description>Unspecified</description>
29639 …<description>The value of this register is derived from the DMAH_CH6_FIFO_DEPTH coreConsultant par…
29646 <description>Unspecified</description>
29651 <description>Unspecified</description>
29656 <description>Unspecified</description>
29661 <description>Unspecified</description>
29666 <description>Unspecified</description>
29671 <description>Unspecified</description>
29680 …description>DMA_COMP_PARAMS_5 is a constant read-only register that contains encoded information a…
29688 …<description>The value of this register is derived from the DMAH_CH5_DTW coreConsultant parameter.…
29695 <description>Unspecified</description>
29700 <description>Unspecified</description>
29705 <description>Unspecified</description>
29710 <description>Unspecified</description>
29715 <description>Unspecified</description>
29720 <description>Unspecified</description>
29725 <description>Unspecified</description>
29732 …<description>The value of this register is derived from the DMAH_CH5_STW coreConsultant parameter.…
29739 <description>Unspecified</description>
29744 <description>Unspecified</description>
29749 <description>Unspecified</description>
29754 <description>Unspecified</description>
29759 <description>Unspecified</description>
29764 <description>Unspecified</description>
29769 <description>Unspecified</description>
29776 …<description>The value of this register is derived from the DMAH_CH5_STAT_DST coreConsultant param…
29783 <description>Unspecified</description>
29788 <description>Unspecified</description>
29795 …<description>The value of this register is derived from the DMAH_CH5_STAT_SRC coreConsultant param…
29802 <description>Unspecified</description>
29807 <description>Unspecified</description>
29814 …<description>The value of this register is derived from the DMAH_CH5_DST_SCA_EN coreConsultant par…
29821 <description>Unspecified</description>
29826 <description>Unspecified</description>
29833 …<description>The value of this register is derived from the DMAH_CH5_SRC_GAT_EN coreConsultant par…
29840 <description>Unspecified</description>
29845 <description>Unspecified</description>
29852 …<description>The value of this register is derived from the DMAH_CH5_LOCK_EN coreConsultant parame…
29859 <description>Unspecified</description>
29864 <description>Unspecified</description>
29871 …<description>The value of this register is derived from the DMAH_CH5_MULTI_BLK_EN coreConsultant p…
29878 <description>Unspecified</description>
29883 <description>Unspecified</description>
29890 …<description>The value of this register is derived from the DMAH_CH5_CTL_WB_EN coreConsultant para…
29897 <description>Unspecified</description>
29902 <description>Unspecified</description>
29909 …<description>The value of this register is derived from the DMAH_CH5_HC_LLP coreConsultant paramet…
29916 <description>Unspecified</description>
29921 <description>Unspecified</description>
29928 …<description>The value of this register is derived from the DMAH_CH5_FC coreConsultant parameter.<…
29935 <description>Unspecified</description>
29940 <description>Unspecified</description>
29945 <description>Unspecified</description>
29950 <description>Unspecified</description>
29957 …<description>The value of this register is derived from the DMAH_CH5_MULT_SIZE coreConsultant para…
29964 <description>Unspecified</description>
29969 <description>Unspecified</description>
29974 <description>Unspecified</description>
29979 <description>Unspecified</description>
29984 <description>Unspecified</description>
29989 <description>Unspecified</description>
29994 <description>Unspecified</description>
30001 …<description>The value of this register is derived from the DMAH_CH5_DMS coreConsultant parameter.…
30008 <description>Unspecified</description>
30013 <description>Unspecified</description>
30018 <description>Unspecified</description>
30023 <description>Unspecified</description>
30028 <description>Unspecified</description>
30035 …<description>The value of this register is derived from the DMAH_CH5_LMS coreConsultant parameter.…
30042 <description>Unspecified</description>
30047 <description>Unspecified</description>
30052 <description>Unspecified</description>
30057 <description>Unspecified</description>
30062 <description>Unspecified</description>
30069 …<description>The value of this register is derived from the DMAH_CH5_SMS coreConsultant parameter.…
30076 <description>Unspecified</description>
30081 <description>Unspecified</description>
30086 <description>Unspecified</description>
30091 <description>Unspecified</description>
30096 <description>Unspecified</description>
30103 …<description>The value of this register is derived from the DMAH_CH5_FIFO_DEPTH coreConsultant par…
30110 <description>Unspecified</description>
30115 <description>Unspecified</description>
30120 <description>Unspecified</description>
30125 <description>Unspecified</description>
30130 <description>Unspecified</description>
30135 <description>Unspecified</description>
30144 …description>DMA_COMP_PARAMS_4 is a constant read-only register that contains encoded information a…
30152 …<description>The value of this register is derived from the DMAH_CH4_DTW coreConsultant parameter.…
30159 <description>Unspecified</description>
30164 <description>Unspecified</description>
30169 <description>Unspecified</description>
30174 <description>Unspecified</description>
30179 <description>Unspecified</description>
30184 <description>Unspecified</description>
30189 <description>Unspecified</description>
30196 …<description>The value of this register is derived from the DMAH_CH4_STW coreConsultant parameter.…
30203 <description>Unspecified</description>
30208 <description>Unspecified</description>
30213 <description>Unspecified</description>
30218 <description>Unspecified</description>
30223 <description>Unspecified</description>
30228 <description>Unspecified</description>
30233 <description>Unspecified</description>
30240 …<description>The value of this register is derived from the DMAH_CH4_STAT_DST coreConsultant param…
30247 <description>Unspecified</description>
30252 <description>Unspecified</description>
30259 …<description>The value of this register is derived from the DMAH_CH4_STAT_SRC coreConsultant param…
30266 <description>Unspecified</description>
30271 <description>Unspecified</description>
30278 …<description>The value of this register is derived from the DMAH_CH4_DST_SCA_EN coreConsultant par…
30285 <description>Unspecified</description>
30290 <description>Unspecified</description>
30297 …<description>The value of this register is derived from the DMAH_CH4_SRC_GAT_EN coreConsultant par…
30304 <description>Unspecified</description>
30309 <description>Unspecified</description>
30316 …<description>The value of this register is derived from the DMAH_CH4_LOCK_EN coreConsultant parame…
30323 <description>Unspecified</description>
30328 <description>Unspecified</description>
30335 …<description>The value of this register is derived from the DMAH_CH4_MULTI_BLK_EN coreConsultant p…
30342 <description>Unspecified</description>
30347 <description>Unspecified</description>
30354 …<description>The value of this register is derived from the DMAH_CH4_CTL_WB_EN coreConsultant para…
30361 <description>Unspecified</description>
30366 <description>Unspecified</description>
30373 …<description>The value of this register is derived from the DMAH_CH4_HC_LLP coreConsultant paramet…
30380 <description>Unspecified</description>
30385 <description>Unspecified</description>
30392 …<description>The value of this register is derived from the DMAH_CH4_FC coreConsultant parameter.<…
30399 <description>Unspecified</description>
30404 <description>Unspecified</description>
30409 <description>Unspecified</description>
30414 <description>Unspecified</description>
30421 …<description>The value of this register is derived from the DMAH_CH4_MULT_SIZE coreConsultant para…
30428 <description>Unspecified</description>
30433 <description>Unspecified</description>
30438 <description>Unspecified</description>
30443 <description>Unspecified</description>
30448 <description>Unspecified</description>
30453 <description>Unspecified</description>
30458 <description>Unspecified</description>
30465 …<description>The value of this register is derived from the DMAH_CH4_DMS coreConsultant parameter.…
30472 <description>Unspecified</description>
30477 <description>Unspecified</description>
30482 <description>Unspecified</description>
30487 <description>Unspecified</description>
30492 <description>Unspecified</description>
30499 …<description>The value of this register is derived from the DMAH_CH4_LMS coreConsultant parameter.…
30506 <description>Unspecified</description>
30511 <description>Unspecified</description>
30516 <description>Unspecified</description>
30521 <description>Unspecified</description>
30526 <description>Unspecified</description>
30533 …<description>The value of this register is derived from the DMAH_CH4_SMS coreConsultant parameter.…
30540 <description>Unspecified</description>
30545 <description>Unspecified</description>
30550 <description>Unspecified</description>
30555 <description>Unspecified</description>
30560 <description>Unspecified</description>
30567 …<description>The value of this register is derived from the DMAH_CH4_FIFO_DEPTH coreConsultant par…
30574 <description>Unspecified</description>
30579 <description>Unspecified</description>
30584 <description>Unspecified</description>
30589 <description>Unspecified</description>
30594 <description>Unspecified</description>
30599 <description>Unspecified</description>
30608 …description>DMA_COMP_PARAMS_4 is a constant read-only register that contains encoded information a…
30616 …<description>The value of this register is derived from the DMAH_CH3_DTW coreConsultant parameter.…
30623 <description>Unspecified</description>
30628 <description>Unspecified</description>
30633 <description>Unspecified</description>
30638 <description>Unspecified</description>
30643 <description>Unspecified</description>
30648 <description>Unspecified</description>
30653 <description>Unspecified</description>
30660 …<description>The value of this register is derived from the DMAH_CH3_STW coreConsultant parameter.…
30667 <description>Unspecified</description>
30672 <description>Unspecified</description>
30677 <description>Unspecified</description>
30682 <description>Unspecified</description>
30687 <description>Unspecified</description>
30692 <description>Unspecified</description>
30697 <description>Unspecified</description>
30704 …<description>The value of this register is derived from the DMAH_CH3_STAT_DST coreConsultant param…
30711 <description>Unspecified</description>
30716 <description>Unspecified</description>
30723 …<description>The value of this register is derived from the DMAH_CH3_STAT_SRC coreConsultant param…
30730 <description>Unspecified</description>
30735 <description>Unspecified</description>
30742 …<description>The value of this register is derived from the DMAH_CH3_DST_SCA_EN coreConsultant par…
30749 <description>Unspecified</description>
30754 <description>Unspecified</description>
30761 …<description>The value of this register is derived from the DMAH_CH3_SRC_GAT_EN coreConsultant par…
30768 <description>Unspecified</description>
30773 <description>Unspecified</description>
30780 …<description>The value of this register is derived from the DMAH_CH3_LOCK_EN coreConsultant parame…
30787 <description>Unspecified</description>
30792 <description>Unspecified</description>
30799 …<description>The value of this register is derived from the DMAH_CH3_MULTI_BLK_EN coreConsultant p…
30806 <description>Unspecified</description>
30811 <description>Unspecified</description>
30818 …<description>The value of this register is derived from the DMAH_CH3_CTL_WB_EN coreConsultant para…
30825 <description>Unspecified</description>
30830 <description>Unspecified</description>
30837 …<description>The value of this register is derived from the DMAH_CH3_HC_LLP coreConsultant paramet…
30844 <description>Unspecified</description>
30849 <description>Unspecified</description>
30856 …<description>The value of this register is derived from the DMAH_CH3_FC coreConsultant parameter.<…
30863 <description>Unspecified</description>
30868 <description>Unspecified</description>
30873 <description>Unspecified</description>
30878 <description>Unspecified</description>
30885 …<description>The value of this register is derived from the DMAH_CH3_MULT_SIZE coreConsultant para…
30892 <description>Unspecified</description>
30897 <description>Unspecified</description>
30902 <description>Unspecified</description>
30907 <description>Unspecified</description>
30912 <description>Unspecified</description>
30917 <description>Unspecified</description>
30922 <description>Unspecified</description>
30929 …<description>The value of this register is derived from the DMAH_CH3_DMS coreConsultant parameter.…
30936 <description>Unspecified</description>
30941 <description>Unspecified</description>
30946 <description>Unspecified</description>
30951 <description>Unspecified</description>
30956 <description>Unspecified</description>
30963 …<description>The value of this register is derived from the DMAH_CH3_LMS coreConsultant parameter.…
30970 <description>Unspecified</description>
30975 <description>Unspecified</description>
30980 <description>Unspecified</description>
30985 <description>Unspecified</description>
30990 <description>Unspecified</description>
30997 …<description>The value of this register is derived from the DMAH_CH3_SMS coreConsultant parameter.…
31004 <description>Unspecified</description>
31009 <description>Unspecified</description>
31014 <description>Unspecified</description>
31019 <description>Unspecified</description>
31024 <description>Unspecified</description>
31031 …<description>The value of this register is derived from the DMAH_CH3_FIFO_DEPTH coreConsultant par…
31038 <description>Unspecified</description>
31043 <description>Unspecified</description>
31048 <description>Unspecified</description>
31053 <description>Unspecified</description>
31058 <description>Unspecified</description>
31063 <description>Unspecified</description>
31072 …description>DMA_COMP_PARAMS_3 is a constant read-only register that contains encoded information a…
31080 …<description>The value of this register is derived from the DMAH_CH2_DTW coreConsultant parameter.…
31087 <description>Unspecified</description>
31092 <description>Unspecified</description>
31097 <description>Unspecified</description>
31102 <description>Unspecified</description>
31107 <description>Unspecified</description>
31112 <description>Unspecified</description>
31117 <description>Unspecified</description>
31124 …<description>The value of this register is derived from the DMAH_CH2_STW coreConsultant parameter.…
31131 <description>Unspecified</description>
31136 <description>Unspecified</description>
31141 <description>Unspecified</description>
31146 <description>Unspecified</description>
31151 <description>Unspecified</description>
31156 <description>Unspecified</description>
31161 <description>Unspecified</description>
31168 …<description>The value of this register is derived from the DMAH_CH2_STAT_DST coreConsultant param…
31175 <description>Unspecified</description>
31180 <description>Unspecified</description>
31187 …<description>The value of this register is derived from the DMAH_CH2_STAT_SRC coreConsultant param…
31194 <description>Unspecified</description>
31199 <description>Unspecified</description>
31206 …<description>The value of this register is derived from the DMAH_CH2_DST_SCA_EN coreConsultant par…
31213 <description>Unspecified</description>
31218 <description>Unspecified</description>
31225 …<description>The value of this register is derived from the DMAH_CH2_SRC_GAT_EN coreConsultant par…
31232 <description>Unspecified</description>
31237 <description>Unspecified</description>
31244 …<description>The value of this register is derived from the DMAH_CH2_LOCK_EN coreConsultant parame…
31251 <description>Unspecified</description>
31256 <description>Unspecified</description>
31263 …<description>The value of this register is derived from the DMAH_CH2_MULTI_BLK_EN coreConsultant p…
31270 <description>Unspecified</description>
31275 <description>Unspecified</description>
31282 …<description>The value of this register is derived from the DMAH_CH2_CTL_WB_EN coreConsultant para…
31289 <description>Unspecified</description>
31294 <description>Unspecified</description>
31301 …<description>The value of this register is derived from the DMAH_CH2_HC_LLP coreConsultant paramet…
31308 <description>Unspecified</description>
31313 <description>Unspecified</description>
31320 …<description>The value of this register is derived from the DMAH_CH2_FC coreConsultant parameter.<…
31327 <description>Unspecified</description>
31332 <description>Unspecified</description>
31337 <description>Unspecified</description>
31342 <description>Unspecified</description>
31349 …<description>The value of this register is derived from the DMAH_CH2_MULT_SIZE coreConsultant para…
31356 <description>Unspecified</description>
31361 <description>Unspecified</description>
31366 <description>Unspecified</description>
31371 <description>Unspecified</description>
31376 <description>Unspecified</description>
31381 <description>Unspecified</description>
31386 <description>Unspecified</description>
31393 …<description>The value of this register is derived from the DMAH_CH2_DMS coreConsultant parameter.…
31400 <description>Unspecified</description>
31405 <description>Unspecified</description>
31410 <description>Unspecified</description>
31415 <description>Unspecified</description>
31420 <description>Unspecified</description>
31427 …<description>The value of this register is derived from the DMAH_CH2_LMS coreConsultant parameter.…
31434 <description>Unspecified</description>
31439 <description>Unspecified</description>
31444 <description>Unspecified</description>
31449 <description>Unspecified</description>
31454 <description>Unspecified</description>
31461 …<description>The value of this register is derived from the DMAH_CH2_SMS coreConsultant parameter.…
31468 <description>Unspecified</description>
31473 <description>Unspecified</description>
31478 <description>Unspecified</description>
31483 <description>Unspecified</description>
31488 <description>Unspecified</description>
31495 …<description>The value of this register is derived from the DMAH_CH2_FIFO_DEPTH coreConsultant par…
31502 <description>Unspecified</description>
31507 <description>Unspecified</description>
31512 <description>Unspecified</description>
31517 <description>Unspecified</description>
31522 <description>Unspecified</description>
31527 <description>Unspecified</description>
31536 …description>DMA_COMP_PARAMS_3 is a constant read-only register that contains encoded information a…
31544 …<description>The value of this register is derived from the DMAH_CH1_DTW coreConsultant parameter.…
31551 <description>Unspecified</description>
31556 <description>Unspecified</description>
31561 <description>Unspecified</description>
31566 <description>Unspecified</description>
31571 <description>Unspecified</description>
31576 <description>Unspecified</description>
31581 <description>Unspecified</description>
31588 …<description>The value of this register is derived from the DMAH_CH1_STW coreConsultant parameter.…
31595 <description>Unspecified</description>
31600 <description>Unspecified</description>
31605 <description>Unspecified</description>
31610 <description>Unspecified</description>
31615 <description>Unspecified</description>
31620 <description>Unspecified</description>
31625 <description>Unspecified</description>
31632 …<description>The value of this register is derived from the DMAH_CH1_STAT_DST coreConsultant param…
31639 <description>Unspecified</description>
31644 <description>Unspecified</description>
31651 …<description>The value of this register is derived from the DMAH_CH1_STAT_SRC coreConsultant param…
31658 <description>Unspecified</description>
31663 <description>Unspecified</description>
31670 …<description>The value of this register is derived from the DMAH_CH1_DST_SCA_EN coreConsultant par…
31677 <description>Unspecified</description>
31682 <description>Unspecified</description>
31689 …<description>The value of this register is derived from the DMAH_CH1_SRC_GAT_EN coreConsultant par…
31696 <description>Unspecified</description>
31701 <description>Unspecified</description>
31708 …<description>The value of this register is derived from the DMAH_CH1_LOCK_EN coreConsultant parame…
31715 <description>Unspecified</description>
31720 <description>Unspecified</description>
31727 …<description>The value of this register is derived from the DMAH_CH1_MULTI_BLK_EN coreConsultant p…
31734 <description>Unspecified</description>
31739 <description>Unspecified</description>
31746 …<description>The value of this register is derived from the DMAH_CH1_CTL_WB_EN coreConsultant para…
31753 <description>Unspecified</description>
31758 <description>Unspecified</description>
31765 …<description>The value of this register is derived from the DMAH_CH1_HC_LLP coreConsultant paramet…
31772 <description>Unspecified</description>
31777 <description>Unspecified</description>
31784 …<description>The value of this register is derived from the DMAH_CH1_FC coreConsultant parameter.<…
31791 <description>Unspecified</description>
31796 <description>Unspecified</description>
31801 <description>Unspecified</description>
31806 <description>Unspecified</description>
31813 …<description>The value of this register is derived from the DMAH_CH1_MULT_SIZE coreConsultant para…
31820 <description>Unspecified</description>
31825 <description>Unspecified</description>
31830 <description>Unspecified</description>
31835 <description>Unspecified</description>
31840 <description>Unspecified</description>
31845 <description>Unspecified</description>
31850 <description>Unspecified</description>
31857 …<description>The value of this register is derived from the DMAH_CH1_DMS coreConsultant parameter.…
31864 <description>Unspecified</description>
31869 <description>Unspecified</description>
31874 <description>Unspecified</description>
31879 <description>Unspecified</description>
31884 <description>Unspecified</description>
31891 …<description>The value of this register is derived from the DMAH_CH1_LMS coreConsultant parameter.…
31898 <description>Unspecified</description>
31903 <description>Unspecified</description>
31908 <description>Unspecified</description>
31913 <description>Unspecified</description>
31918 <description>Unspecified</description>
31925 …<description>The value of this register is derived from the DMAH_CH1_SMS coreConsultant parameter.…
31932 <description>Unspecified</description>
31937 <description>Unspecified</description>
31942 <description>Unspecified</description>
31947 <description>Unspecified</description>
31952 <description>Unspecified</description>
31959 …<description>The value of this register is derived from the DMAH_CH1_FIFO_DEPTH coreConsultant par…
31966 <description>Unspecified</description>
31971 <description>Unspecified</description>
31976 <description>Unspecified</description>
31981 <description>Unspecified</description>
31986 <description>Unspecified</description>
31991 <description>Unspecified</description>
32000 …<description>DMA_COMP_PARAMS_2 is a constant read-only register that contains encoded information …
32008 …<description>The value of this register is derived from the DMAH_CH0_DTW coreConsultant parameter.…
32015 <description>Unspecified</description>
32020 <description>Unspecified</description>
32025 <description>Unspecified</description>
32030 <description>Unspecified</description>
32035 <description>Unspecified</description>
32040 <description>Unspecified</description>
32045 <description>Unspecified</description>
32052 …<description>The value of this register is derived from the DMAH_CH0_STW coreConsultant parameter.…
32059 <description>Unspecified</description>
32064 <description>Unspecified</description>
32069 <description>Unspecified</description>
32074 <description>Unspecified</description>
32079 <description>Unspecified</description>
32084 <description>Unspecified</description>
32089 <description>Unspecified</description>
32096 …<description>The value of this register is derived from the DMAH_CH0_STAT_DST coreConsultant param…
32103 <description>Unspecified</description>
32108 <description>Unspecified</description>
32115 …<description>The value of this register is derived from the DMAH_CH0_STAT_SRC coreConsultant param…
32122 <description>Unspecified</description>
32127 <description>Unspecified</description>
32134 …<description>The value of this register is derived from the DMAH_CH0_DST_SCA_EN coreConsultant par…
32141 <description>Unspecified</description>
32146 <description>Unspecified</description>
32153 …<description>The value of this register is derived from the DMAH_CH0_SRC_GAT_EN coreConsultant par…
32160 <description>Unspecified</description>
32165 <description>Unspecified</description>
32172 …<description>The value of this register is derived from the DMAH_CH0_LOCK_EN coreConsultant parame…
32179 <description>Unspecified</description>
32184 <description>Unspecified</description>
32191 …<description>The value of this register is derived from the DMAH_CH0_MULTI_BLK_EN coreConsultant p…
32198 <description>Unspecified</description>
32203 <description>Unspecified</description>
32210 …<description>The value of this register is derived from the DMAH_CH0_CTL_WB_EN coreConsultant para…
32217 <description>Unspecified</description>
32222 <description>Unspecified</description>
32229 …<description>The value of this register is derived from the DMAH_CH0_HC_LLP coreConsultant paramet…
32236 <description>Unspecified</description>
32241 <description>Unspecified</description>
32248 …<description>The value of this register is derived from the DMAH_CH0_FC coreConsultant parameter.<…
32255 <description>Unspecified</description>
32260 <description>Unspecified</description>
32265 <description>Unspecified</description>
32270 <description>Unspecified</description>
32277 …<description>The value of this register is derived from the DMAH_CH0_MULT_SIZE coreConsultant para…
32284 <description>Unspecified</description>
32289 <description>Unspecified</description>
32294 <description>Unspecified</description>
32299 <description>Unspecified</description>
32304 <description>Unspecified</description>
32309 <description>Unspecified</description>
32314 <description>Unspecified</description>
32321 …<description>The value of this register is derived from the DMAH_CH0_DMS coreConsultant parameter.…
32328 <description>Unspecified</description>
32333 <description>Unspecified</description>
32338 <description>Unspecified</description>
32343 <description>Unspecified</description>
32348 <description>Unspecified</description>
32355 …<description>The value of this register is derived from the DMAH_CH0_LMS coreConsultant parameter.…
32362 <description>Unspecified</description>
32367 <description>Unspecified</description>
32372 <description>Unspecified</description>
32377 <description>Unspecified</description>
32382 <description>Unspecified</description>
32389 …<description>The value of this register is derived from the DMAH_CH0_SMS coreConsultant parameter.…
32396 <description>Unspecified</description>
32401 <description>Unspecified</description>
32406 <description>Unspecified</description>
32411 <description>Unspecified</description>
32416 <description>Unspecified</description>
32423 …<description>The value of this register is derived from the DMAH_CH0_FIFO_DEPTH coreConsultant par…
32430 <description>Unspecified</description>
32435 <description>Unspecified</description>
32440 <description>Unspecified</description>
32445 <description>Unspecified</description>
32450 <description>Unspecified</description>
32455 <description>Unspecified</description>
32464 …<description>DMA_COMP_PARAMS_2 is a constant read-only register that contains encoded information …
32472 …<description>The values of these bit fields are derived from the DMAH_CH0_MULTI_BLK_TYPE coreConsu…
32479 <description>Unspecified</description>
32484 <description>Unspecified</description>
32489 <description>Unspecified</description>
32494 <description>Unspecified</description>
32499 <description>Unspecified</description>
32504 <description>Unspecified</description>
32509 <description>Unspecified</description>
32514 <description>Unspecified</description>
32519 <description>Unspecified</description>
32526 …<description>The values of these bit fields are derived from the DMAH_CH1_MULTI_BLK_TYPE coreConsu…
32533 <description>Unspecified</description>
32538 <description>Unspecified</description>
32543 <description>Unspecified</description>
32548 <description>Unspecified</description>
32553 <description>Unspecified</description>
32558 <description>Unspecified</description>
32563 <description>Unspecified</description>
32568 <description>Unspecified</description>
32573 <description>Unspecified</description>
32580 …<description>The values of these bit fields are derived from the DMAH_CH2_MULTI_BLK_TYPE coreConsu…
32587 <description>Unspecified</description>
32592 <description>Unspecified</description>
32597 <description>Unspecified</description>
32602 <description>Unspecified</description>
32607 <description>Unspecified</description>
32612 <description>Unspecified</description>
32617 <description>Unspecified</description>
32622 <description>Unspecified</description>
32627 <description>Unspecified</description>
32634 …<description>The values of these bit fields are derived from the DMAH_CH3_MULTI_BLK_TYPE coreConsu…
32641 <description>Unspecified</description>
32646 <description>Unspecified</description>
32651 <description>Unspecified</description>
32656 <description>Unspecified</description>
32661 <description>Unspecified</description>
32666 <description>Unspecified</description>
32671 <description>Unspecified</description>
32676 <description>Unspecified</description>
32681 <description>Unspecified</description>
32688 …<description>The values of these bit fields are derived from the DMAH_CH4_MULTI_BLK_TYPE coreConsu…
32695 <description>Unspecified</description>
32700 <description>Unspecified</description>
32705 <description>Unspecified</description>
32710 <description>Unspecified</description>
32715 <description>Unspecified</description>
32720 <description>Unspecified</description>
32725 <description>Unspecified</description>
32730 <description>Unspecified</description>
32735 <description>Unspecified</description>
32742 …<description>The values of these bit fields are derived from the DMAH_CH5_MULTI_BLK_TYPE coreConsu…
32749 <description>Unspecified</description>
32754 <description>Unspecified</description>
32759 <description>Unspecified</description>
32764 <description>Unspecified</description>
32769 <description>Unspecified</description>
32774 <description>Unspecified</description>
32779 <description>Unspecified</description>
32784 <description>Unspecified</description>
32789 <description>Unspecified</description>
32796 …<description>The values of these bit fields are derived from the DMAH_CH6_MULTI_BLK_TYPE coreConsu…
32803 <description>Unspecified</description>
32808 <description>Unspecified</description>
32813 <description>Unspecified</description>
32818 <description>Unspecified</description>
32823 <description>Unspecified</description>
32828 <description>Unspecified</description>
32833 <description>Unspecified</description>
32838 <description>Unspecified</description>
32843 <description>Unspecified</description>
32850 …<description>The values of these bit fields are derived from the DMAH_CH7_MULTI_BLK_TYPE coreConsu…
32857 <description>Unspecified</description>
32862 <description>Unspecified</description>
32867 <description>Unspecified</description>
32872 <description>Unspecified</description>
32877 <description>Unspecified</description>
32882 <description>Unspecified</description>
32887 <description>Unspecified</description>
32892 <description>Unspecified</description>
32897 <description>Unspecified</description>
32906 …<description>DMA_COMP_PARAMS_1 is a constant read-only register that contains encoded information …
32914 …<description>The values of these bit fields are derived from the DMAH_CH0_MAX_BLK_SIZE coreConsult…
32921 <description>Unspecified</description>
32926 <description>Unspecified</description>
32931 <description>Unspecified</description>
32936 <description>Unspecified</description>
32941 <description>Unspecified</description>
32946 <description>Unspecified</description>
32951 <description>Unspecified</description>
32956 <description>Unspecified</description>
32961 <description>Unspecified</description>
32966 <description>Unspecified</description>
32971 <description>Unspecified</description>
32978 …<description>The values of these bit fields are derived from the DMAH_CH1_MAX_BLK_SIZE coreConsult…
32985 <description>Unspecified</description>
32990 <description>Unspecified</description>
32995 <description>Unspecified</description>
33000 <description>Unspecified</description>
33005 <description>Unspecified</description>
33010 <description>Unspecified</description>
33015 <description>Unspecified</description>
33020 <description>Unspecified</description>
33025 <description>Unspecified</description>
33030 <description>Unspecified</description>
33035 <description>Unspecified</description>
33042 …<description>The values of these bit fields are derived from the DMAH_CH2_MAX_BLK_SIZE coreConsult…
33049 <description>Unspecified</description>
33054 <description>Unspecified</description>
33059 <description>Unspecified</description>
33064 <description>Unspecified</description>
33069 <description>Unspecified</description>
33074 <description>Unspecified</description>
33079 <description>Unspecified</description>
33084 <description>Unspecified</description>
33089 <description>Unspecified</description>
33094 <description>Unspecified</description>
33099 <description>Unspecified</description>
33106 …<description>The values of these bit fields are derived from the DMAH_CH3_MAX_BLK_SIZE coreConsult…
33113 <description>Unspecified</description>
33118 <description>Unspecified</description>
33123 <description>Unspecified</description>
33128 <description>Unspecified</description>
33133 <description>Unspecified</description>
33138 <description>Unspecified</description>
33143 <description>Unspecified</description>
33148 <description>Unspecified</description>
33153 <description>Unspecified</description>
33158 <description>Unspecified</description>
33163 <description>Unspecified</description>
33170 …<description>The values of these bit fields are derived from the DMAH_CH4_MAX_BLK_SIZE coreConsult…
33177 <description>Unspecified</description>
33182 <description>Unspecified</description>
33187 <description>Unspecified</description>
33192 <description>Unspecified</description>
33197 <description>Unspecified</description>
33202 <description>Unspecified</description>
33207 <description>Unspecified</description>
33212 <description>Unspecified</description>
33217 <description>Unspecified</description>
33222 <description>Unspecified</description>
33227 <description>Unspecified</description>
33234 …<description>The values of these bit fields are derived from the DMAH_CH5_MAX_BLK_SIZE coreConsult…
33241 <description>Unspecified</description>
33246 <description>Unspecified</description>
33251 <description>Unspecified</description>
33256 <description>Unspecified</description>
33261 <description>Unspecified</description>
33266 <description>Unspecified</description>
33271 <description>Unspecified</description>
33276 <description>Unspecified</description>
33281 <description>Unspecified</description>
33286 <description>Unspecified</description>
33291 <description>Unspecified</description>
33298 …<description>The values of these bit fields are derived from the DMAH_CH6_MAX_BLK_SIZE coreConsult…
33305 <description>Unspecified</description>
33310 <description>Unspecified</description>
33315 <description>Unspecified</description>
33320 <description>Unspecified</description>
33325 <description>Unspecified</description>
33330 <description>Unspecified</description>
33335 <description>Unspecified</description>
33340 <description>Unspecified</description>
33345 <description>Unspecified</description>
33350 <description>Unspecified</description>
33355 <description>Unspecified</description>
33362 …<description>The values of these bit fields are derived from the DMAH_CH7_MAX_BLK_SIZE coreConsult…
33369 <description>Unspecified</description>
33374 <description>Unspecified</description>
33379 <description>Unspecified</description>
33384 <description>Unspecified</description>
33389 <description>Unspecified</description>
33394 <description>Unspecified</description>
33399 <description>Unspecified</description>
33404 <description>Unspecified</description>
33409 <description>Unspecified</description>
33414 <description>Unspecified</description>
33419 <description>Unspecified</description>
33428 …<description>DMA_COMP_PARAMS_1 is a constant read-only register that contains encoded information …
33436 …<description>The value of this register is derived from the DMAH_BIG_ENDIAN coreConsultant paramet…
33443 <description>Unspecified</description>
33448 <description>Unspecified</description>
33455 …<description>The value of this register is derived from the DMAH_INTR_IO coreConsultant parameter.…
33462 <description>Unspecified</description>
33467 <description>Unspecified</description>
33472 <description>Unspecified</description>
33479 …<description>The value of this register is derived from the DMAH_MABRST coreConsultant parameter.<…
33486 <description>Unspecified</description>
33491 <description>Unspecified</description>
33498 <description>Reserved field- read-only</description>
33505 …<description>The value of this register is derived from the DMAH_NUM_CHANNELS coreConsultant param…
33512 <description>Unspecified</description>
33517 <description>Unspecified</description>
33522 <description>Unspecified</description>
33527 <description>Unspecified</description>
33532 <description>Unspecified</description>
33537 <description>Unspecified</description>
33542 <description>Unspecified</description>
33547 <description>Unspecified</description>
33554 …<description>The value of this register is derived from the DMAH_NUM_MASTER_INT coreConsultant par…
33561 <description>Unspecified</description>
33566 <description>Unspecified</description>
33571 <description>Unspecified</description>
33576 <description>Unspecified</description>
33583 …<description>The value of this register is derived from the DMAH_S_HDATA_WIDTH coreConsultant para…
33590 <description>Unspecified</description>
33595 <description>Unspecified</description>
33600 <description>Unspecified</description>
33605 <description>Unspecified</description>
33612 …<description>The value of this register is derived from the DMAH_M4_HDATA_WIDTH coreConsultant par…
33619 <description>Unspecified</description>
33624 <description>Unspecified</description>
33629 <description>Unspecified</description>
33634 <description>Unspecified</description>
33641 …<description>The value of this register is derived from the DMAH_M3_HDATA_WIDTH coreConsultant par…
33648 <description>Unspecified</description>
33653 <description>Unspecified</description>
33658 <description>Unspecified</description>
33663 <description>Unspecified</description>
33670 …<description>The value of this register is derived from the DMAH_M2_HDATA_WIDTH coreConsultant par…
33677 <description>Unspecified</description>
33682 <description>Unspecified</description>
33687 <description>Unspecified</description>
33692 <description>Unspecified</description>
33699 …<description>The value of this register is derived from the DMAH_M1_HDATA_WIDTH coreConsultant par…
33706 <description>Unspecified</description>
33711 <description>Unspecified</description>
33716 <description>Unspecified</description>
33721 <description>Unspecified</description>
33728 …<description>The value of this register is derived from the DMAH_NUM_HS_INT coreConsultant paramet…
33735 <description>Unspecified</description>
33740 <description>Unspecified</description>
33745 <description>Unspecified</description>
33750 <description>Unspecified</description>
33755 <description>Unspecified</description>
33760 <description>Unspecified</description>
33765 <description>Unspecified</description>
33770 <description>Unspecified</description>
33775 <description>Unspecified</description>
33780 <description>Unspecified</description>
33785 <description>Unspecified</description>
33790 <description>Unspecified</description>
33795 <description>Unspecified</description>
33800 <description>Unspecified</description>
33805 <description>Unspecified</description>
33810 <description>Unspecified</description>
33815 <description>Unspecified</description>
33822 …<description>The value of this register is derived from the DMAH_ADD_ENCODED_PARAMS coreConsultant…
33829 <description>Unspecified</description>
33834 <description>Unspecified</description>
33841 …<description>The value of this register is derived from the DMAH_STATIC_ENDIAN_SELECT coreConsulta…
33850 …<description>This is the DW_ahb_dmac Component Version register, which is a read-only register tha…
33858 <description>DMA Component Type Number = `h44571110.</description>
33867 …description>This is the DW_ahb_dmac Component Version register, which is a read-only register that…
33875 <description>DMA Component Version.</description>
33888 <description>I3CCORE 1</description>
33895 <description>MCAN</description>
33910 <description>Endian Register</description>
33918 <description>Endianness Test Value</description>
33926 <description>Data Bit Timing and Prescaler Register</description>
33934 <description>Data (Re)Synchronization Jump Width</description>
33940 <description>Data time segment after sample point</description>
33946 <description>Data time segment before sample point</description>
33952 <description>Data Bit Rate Prescaler</description>
33958 <description>Transmitter Delay Compensation</description>
33964 <description>Unspecified</description>
33969 <description>Unspecified</description>
33978 <description>Test Register</description>
33986 <description>Loop Back Mode</description>
33992 <description>Loop Back Mode is disabled</description>
33997 <description>Loop Back Mode is enabled</description>
34004 <description>Control of Transmit Pin</description>
34010 … <description>controlled by the CAN Core, updated at the end of the CAN bit time</description>
34015 <description>Sample Point can be monitored at pin m_can_tx</description>
34020 <description>Dominant (0) level at pin m_can_tx</description>
34025 <description>Recessive (1) at pin m_can_tx</description>
34032 <description>Receive Pin</description>
34038 <description>The CAN bus is dominant (m_can_rx = 0)</description>
34043 <description>The CAN bus is recessive (m_can_rx = '1')</description>
34050 <description>Tx Buffer Number Prepared</description>
34056 <description>Prepared Valid</description>
34062 <description>Value of TXBNP not valid</description>
34067 <description>Value of TXBNP valid</description>
34074 <description>Tx Buffer Number Started</description>
34080 <description>Started Valid</description>
34086 <description>Value of TXBNP not valid</description>
34091 <description>Value of TXBNP valid</description>
34100 <description>RAM Watchdog</description>
34108 …<description>Start value of the Message RAM Watchdog Counter. With the reset value of '00' the cou…
34109 disabled.</description>
34115 <description>Actual Message RAM Watchdog Counter Value.</description>
34123 <description>CC Control Register</description>
34131 <description>Initialization</description>
34137 <description>Normal Operation</description>
34142 <description>Initialization is started</description>
34149 <description>Configuration Change Enable</description>
34155 … <description>The CPU has no write access to the protected configuration registers</description>
34160 …<description>The CPU has write access to the protected configuration registers (while CCCR.INIT = …
34167 <description>Restricted Operation Mode</description>
34173 <description>Normal CAN operation</description>
34178 <description>Restricted Operation Mode active</description>
34185 <description>Clock Stop Acknowledge</description>
34191 <description>No clock stop acknowledged</description>
34196 … <description>MCAN may be set in power down by stopping m_can_hclk and m_can_cclk</description>
34203 <description>Clock Stop Request</description>
34209 <description>No clock stop is requested</description>
34214 <description>Clock stop requested.</description>
34221 <description>Bus Monitoring Mode</description>
34227 <description>Bus Monitoring Mode is disabled</description>
34232 <description>Bus Monitoring Mode is enabled</description>
34239 <description>Disable Automatic Retransmission</description>
34245 …<description>Automatic retransmission of messages not transmitted successfully enabled</descriptio…
34250 <description>Automatic retransmission disabled</description>
34257 <description>Test Mode Enable</description>
34263 <description>Normal operation, register TEST holds reset values</description>
34268 <description>Test Mode, write access to register TEST enabled</description>
34275 <description>FD Operation Enable</description>
34281 <description>FD operation disabled</description>
34286 <description>FD operation enabled</description>
34293 <description>Bit Rate Switch Enable</description>
34299 <description>Bit rate switching for transmissions disabled</description>
34304 <description>Bit rate switching for transmissions enabled</description>
34311 <description>Wide Message Marker</description>
34317 <description>8-bit Message Marker used</description>
34322 …<description>16-bit Message Marker used, replacing 16-bit timestamps in Tx Event FIFO</description>
34329 <description>Protocol Exception Handling Disable</description>
34335 <description>Protocol exception handling enabled</description>
34340 <description>Protocol exception handling disabled</description>
34347 <description>Edge Filtering during Bus Integration</description>
34353 <description>Edge filtering disabled</description>
34358 …<description>Two consecutive dominant tq required to detect an edge for hard synchronization</desc…
34365 <description>Transmit Pause</description>
34371 <description>Transmit pause disabled</description>
34376 <description>Transmit pause enabled</description>
34383 <description>Non ISO Operation</description>
34389 <description>CAN FD frame format according to ISO 11898-1:2015</description>
34394 … <description>CAN FD frame format according to Bosch CAN FD Specification V1.0</description>
34403 <description>Nominal Bit Timing and Prescaler Register</description>
34411 <description>Nominal Time segment after sample point</description>
34417 <description>Nominal Time segment before sample point</description>
34423 <description>Nominal Bit Rate Prescaler</description>
34429 <description>Nominal (Re)Synchronization Jump Width</description>
34437 <description>Timestamp Counter Configuration</description>
34445 <description>Timestamp Select</description>
34451 <description>Timestamp counter value always 0x0000</description>
34456 <description>Timestamp counter value incremented according to TCP</description>
34461 <description>External timestamp counter value used</description>
34466 <description>Same as Zero</description>
34473 <description>Timestamp Counter Prescaler</description>
34481 <description>Timestamp Counter Value</description>
34489 <description>Timestamp Counter</description>
34497 <description>Timeout Counter Configuration</description>
34505 <description>Enable Timeout Counter</description>
34511 <description>Timeout Counter disabled</description>
34516 <description>Timeout Counter enabled</description>
34523 <description>Timeout Select</description>
34529 <description>Continuous operation</description>
34534 <description>Timeout controlled by Tx Event FIFO</description>
34539 <description>Timeout controlled by Rx FIFO 0</description>
34544 <description>Timeout controlled by Rx FIFO 1</description>
34551 <description>Timeout Period</description>
34559 <description>Timeout Counter Value</description>
34567 <description>Timeout Counter</description>
34575 <description>Error Counter Register</description>
34583 <description>Transmit Error Counter</description>
34589 <description>Receive Error Counter</description>
34595 <description>Receive Error Passive</description>
34601 … <description>The Receive Error Counter is below the error passive level of 128</description>
34606 … <description>The Receive Error Counter has reached the error passive level of 128</description>
34613 <description>CAN Error Logging</description>
34621 <description>Protocol Status Register</description>
34629 <description>Last Error Code</description>
34635 …<description>No error occurred since LEC has been reset by successful reception or transmission.</…
34640 … <description>More than 5 equal bits in a sequence have occurred in a part of a received message
34641 where this is not allowed.</description>
34646 … <description>A fixed format part of a received frame has the wrong format.</description>
34651 …<description>The message transmitted by the MCAN was not acknowledged by another node.</descriptio…
34656 … <description>During the transmission of a message (with the exception of the arbitration field),
34658 value was dominant.</description>
34663 … <description>During the transmission of a message (or acknowledge bit, or active error flag, or
34668 dominant or continuously disturbed).</description>
34673 … <description>The CRC check sum of a received message was incorrect. The CRC of an incoming
34674 message does not match with the CRC calculated from the received data.</description>
34679 … <description>Any read access to the Protocol Status Register re-initializes the LEC to '7'.
34681 access to the Protocol Status Register.</description>
34688 <description>Activity</description>
34694 <description>Node is synchronizing on CAN communication</description>
34699 <description>Node is neither receiver nor tr ansmitter</description>
34704 <description>Node is operating as receiver</description>
34709 <description>Node is operating as transmitter</description>
34716 <description>Error Passive</description>
34722 …<description>The MCAN is in the Error_Active state. It normally takes part in bus communication and
34723 sends an active error flag when an error has been detected</description>
34728 <description>The MCAN is in the Error_Passive state</description>
34735 <description>Warning Status</description>
34741 … <description>Both error counters are below the Error_Warning limit of 96</description>
34746 … <description>At least one of error counter has reached the Error_Warning limit of 96</description>
34753 <description>Bus_Off Status</description>
34759 <description>The MCAN is not Bus_Off</description>
34764 <description>The MCAN is in Bus_Off state</description>
34771 <description>Data Phase Last Error Code</description>
34777 <description>ESI flag of last received CAN FD Message</description>
34783 … <description>Last received CAN FD message did not ha ve its ESI flag set</description>
34788 <description>Last received CAN FD message had its ESI flag set</description>
34795 <description>BRS flag of last received CAN FD Message</description>
34801 … <description>Last received CAN FD message did not ha ve its BRS flag set</description>
34806 <description>Last received CAN FD message had its BRS flag set</description>
34813 <description>Received a CAN FD Message</description>
34819 …<description>Since this bit was reset by the CPU, no CAN FD message has been received</description>
34824 … <description>Message in CAN FD format with FDF flag set has been received</description>
34831 <description>Protocol Exception Event</description>
34837 … <description>No protocol exception event occurred since last read access</description>
34842 <description>Protocol exception event occurred</description>
34849 <description>Transmitter Delay Compensation Value</description>
34857 <description>Transmitter Delay Compensation Register</description>
34865 <description>Transmitter Delay Compensation Filter Window Length</description>
34871 <description>Transmitter Delay Compensation SSP Offset</description>
34879 <description>Interrupt Register</description>
34887 <description>Rx FIFO 0 New Message</description>
34893 <description>Write '1' to clear interrupt flag</description>
34898 <description>No new message written to Rx FIFO 0</description>
34903 <description>New message written to Rx FIFO 0</description>
34910 <description>Rx FIFO 0 Watermark Reached</description>
34916 <description>Write '1' to clear interrupt flag</description>
34921 <description>Rx FIFO 0 fill level below watermark</description>
34926 <description>Rx FIFO 0 fill level reached watermark</description>
34933 <description>Rx FIFO 0 Full</description>
34939 <description>Write '1' to clear interrupt flag</description>
34944 <description>Rx FIFO 0 not full</description>
34949 <description>Rx FIFO 0 full</description>
34956 <description>Rx FIFO 0 Message Lost</description>
34962 <description>Write '1' to clear interrupt flag</description>
34967 <description>No Rx FIFO 0 message lost</description>
34972 …<description>Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero</descr…
34979 <description>Rx FIFO 1 New Message</description>
34985 <description>Write '1' to clear interrupt flag</description>
34990 <description>No new message written to Rx FIFO 1</description>
34995 <description>New message written to Rx FIFO 1</description>
35002 <description>Rx FIFO 1 Watermark Reached</description>
35008 <description>Write '1' to clear interrupt flag</description>
35013 <description>Rx FIFO 1 fill level below watermark</description>
35018 <description>Rx FIFO 1 fill level reached watermark</description>
35025 <description>Rx FIFO 1 Full</description>
35031 <description>Write '1' to clear interrupt flag</description>
35036 <description>Rx FIFO 1 not full</description>
35041 <description>Rx FIFO 1 full</description>
35048 <description>Rx FIFO 1 Message Lost</description>
35054 <description>Write '1' to clear interrupt flag</description>
35059 <description>No Rx FIFO 1 message lost</description>
35064 …<description>Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero</descr…
35071 <description>High Priority Message</description>
35077 <description>Write '1' to clear interrupt flag</description>
35082 <description>No high priority message received</description>
35087 <description>High priority message received</description>
35094 <description>Transmission Completed</description>
35100 <description>Write '1' to clear interrupt flag</description>
35105 <description>No transmission completed</description>
35110 <description>Transmission completed</description>
35117 <description>Transmission Cancellation Finished</description>
35123 <description>Write '1' to clear interrupt flag</description>
35128 <description>No transmission cancellation finished</description>
35133 <description>Transmission cancellation finished</description>
35140 <description>Tx FIFO Empty</description>
35146 <description>Write '1' to clear interrupt flag</description>
35151 <description>Tx FIFO non-empty</description>
35156 <description>Tx FIFO empty</description>
35163 <description>Tx Event FIFO New Entry</description>
35169 <description>Write '1' to clear interrupt flag</description>
35174 <description>Tx Event FIFO unchanged</description>
35179 <description>Tx Handler wrote Tx Event FIFO element</description>
35186 <description>Tx Event FIFO Watermark Reached</description>
35192 <description>Write '1' to clear interrupt flag</description>
35197 <description>Tx Event FIFO fill level below watermark</description>
35202 <description>Tx Event FIFO fill level reached watermark</description>
35209 <description>Tx Event FIFO Full</description>
35215 <description>Write '1' to clear interrupt flag</description>
35220 <description>Tx Event FIFO not full</description>
35225 <description>Tx Event FIFO full</description>
35232 <description>Tx Event FIFO Element Lost</description>
35238 <description>Write '1' to clear interrupt flag</description>
35243 <description>No Tx Event FIFO element lost</description>
35248 …<description>Tx Event FIFO element lost, also set after wr ite attempt to Tx Event FIFO of siz e z…
35255 <description>Timestamp Wraparound</description>
35261 <description>Write '1' to clear interrupt flag</description>
35266 <description>No timestamp counter wrap-around</description>
35271 <description>Timestamp counter wrapped around</description>
35278 <description>Message RAM Access Failure</description>
35284 <description>Write '1' to clear interrupt flag</description>
35289 <description>No Message RAM access failure occurred</description>
35294 <description>Message RAM access failure occurred</description>
35301 <description>Timeout Occurred</description>
35307 <description>Write '1' to clear interrupt flag</description>
35312 <description>No timeout</description>
35317 <description>Timeout reached</description>
35324 <description>Message stored to Dedicated Rx Buffer</description>
35330 <description>Write '1' to clear interrupt flag</description>
35335 <description>No Rx Buffer updated</description>
35340 <description>At least one received message stored into an Rx Buff er</description>
35347 <description>Bus Error Uncorrected</description>
35353 <description>Write '1' to clear interrupt flag</description>
35358 … <description>No read slave error detected when reading from Message RAM</description>
35363 <description>Read slave error detected</description>
35370 <description>Error Logging Overflow</description>
35376 <description>Write '1' to clear interrupt flag</description>
35381 <description>CAN Error Logging Counter did not overflow</description>
35386 <description>Overflow of CAN Error Logging Counter occurred</description>
35393 <description>Error Passive</description>
35399 <description>Write '1' to clear interrupt flag</description>
35404 <description>Error_Passive status unchanged</description>
35409 <description>Error_Passive status changed</description>
35416 <description>Warning Status</description>
35422 <description>Write '1' to clear interrupt flag</description>
35427 <description>Error_Warning status unchanged</description>
35432 <description>Error_Warning status changed</description>
35439 <description>Bus_Off Status</description>
35445 <description>Write '1' to clear interrupt flag</description>
35450 <description>Bus_Off status unchanged</description>
35455 <description>Bus_Off status changed</description>
35462 <description>Watchdog Interrupt</description>
35468 <description>Write '1' to clear interrupt flag</description>
35473 <description>No Message RAM Watchdog event occurred</description>
35478 <description>Message RAM Watchdog event due to missing READY</description>
35485 … <description>Protocol Error in Arbitration Phase (Nominal Bit Time is used)</description>
35491 <description>Write '1' to clear interrupt flag</description>
35496 <description>No protocol error in arbitration phase</description>
35501 … <description>Protocol error in arbitration phase detected (PSR.LEC ≠ 0,7)</description>
35508 <description>Protocol Error in Data Phase (Data Bit Time is used)</description>
35514 <description>Write '1' to clear interrupt flag</description>
35519 <description>No protocol error in data phase</description>
35524 <description>Protocol error in data phase detected (PSR.DLEC ≠ 0,7)</description>
35531 <description>Access to Reserved Address</description>
35537 <description>Write '1' to clear interrupt flag</description>
35542 <description>No access to reserved address occurred</description>
35547 <description>Access to reserved address occurred</description>
35556 <description>Interrupt Enable</description>
35564 <description>Rx FIFO 0 New Message Interrupt Enable</description>
35570 <description>Interrupt disabled.</description>
35575 <description>Interrupt enabled.</description>
35582 <description>Rx FIFO 0 Watermark Reached Interrupt Enable</description>
35588 <description>Interrupt disabled.</description>
35593 <description>Interrupt enabled.</description>
35600 <description>Rx FIFO 0 Full Interrupt Enable</description>
35606 <description>Interrupt disabled.</description>
35611 <description>Interrupt enabled.</description>
35618 <description>Rx FIFO 0 Message Lost Interrupt Enable</description>
35624 <description>Interrupt disabled.</description>
35629 <description>Interrupt enabled.</description>
35636 <description>Rx FIFO 1 New Message Interrupt Enable</description>
35642 <description>Interrupt disabled.</description>
35647 <description>Interrupt enabled.</description>
35654 <description>Rx FIFO 1 Watermark Reached Interrupt Enable</description>
35660 <description>Interrupt disabled.</description>
35665 <description>Interrupt enabled.</description>
35672 <description>Rx FIFO 1 Full Interrupt Enable</description>
35678 <description>Interrupt disabled.</description>
35683 <description>Interrupt enabled.</description>
35690 <description>Rx FIFO 1 Message Lost Interrupt Enable</description>
35696 <description>Interrupt disabled.</description>
35701 <description>Interrupt enabled.</description>
35708 <description>High Priority Message Interrupt Enable</description>
35714 <description>Interrupt disabled.</description>
35719 <description>Interrupt enabled.</description>
35726 <description>Transmission Completed Interrupt Enable</description>
35732 <description>Interrupt disabled.</description>
35737 <description>Interrupt enabled.</description>
35744 <description>Transmission Cancellation Finished Interrupt Enable</description>
35750 <description>Interrupt disabled.</description>
35755 <description>Interrupt enabled.</description>
35762 <description>Tx FIFO Empty Interrupt Enable</description>
35768 <description>Interrupt disabled.</description>
35773 <description>Interrupt enabled.</description>
35780 <description>Tx Event FIFO New Entry Interrupt Enable</description>
35786 <description>Interrupt disabled.</description>
35791 <description>Interrupt enabled.</description>
35798 <description>Tx Event FIFO Watermark Reached Interrupt Enable</description>
35804 <description>Interrupt disabled.</description>
35809 <description>Interrupt enabled.</description>
35816 <description>Tx Event FIFO Full Interrupt Enable</description>
35822 <description>Interrupt disabled.</description>
35827 <description>Interrupt enabled.</description>
35834 <description>Tx Event FIFO Event Lost Interrupt Enable</description>
35840 <description>Interrupt disabled.</description>
35845 <description>Interrupt enabled.</description>
35852 <description>Timestamp Wraparound Interrupt Enable</description>
35858 <description>Interrupt disabled.</description>
35863 <description>Interrupt enabled.</description>
35870 <description>Message RAM Access Failure Interrupt Enable</description>
35876 <description>Interrupt disabled.</description>
35881 <description>Interrupt enabled.</description>
35888 <description>Timeout Occurred Interrupt Enable</description>
35894 <description>Interrupt disabled.</description>
35899 <description>Interrupt enabled.</description>
35906 <description>Message stored to Dedicated Rx Buffer Interrupt Enable</description>
35912 <description>Interrupt disabled.</description>
35917 <description>Interrupt enabled.</description>
35924 <description>Bus Error Uncorrected Interrupt Enable</description>
35930 <description>Interrupt disabled.</description>
35935 <description>Interrupt enabled.</description>
35942 <description>Error Logging Overflow Interrupt Enable</description>
35948 <description>Interrupt disabled.</description>
35953 <description>Interrupt enabled.</description>
35960 <description>Error Passive Interrupt Enable</description>
35966 <description>Interrupt disabled.</description>
35971 <description>Interrupt enabled.</description>
35978 <description>Warning Status Interrupt Enable</description>
35984 <description>Interrupt disabled.</description>
35989 <description>Interrupt enabled.</description>
35996 <description>Bus_Off Status Interrupt Enable</description>
36002 <description>Interrupt disabled.</description>
36007 <description>Interrupt enabled.</description>
36014 <description>Watchdog Interrupt Enable</description>
36020 <description>Interrupt disabled.</description>
36025 <description>Interrupt enabled.</description>
36032 <description>Protocol Error in Arbitration Phase Enable</description>
36038 <description>Interrupt disabled.</description>
36043 <description>Interrupt enabled.</description>
36050 <description>Protocol Error in Data Phase Enable</description>
36056 <description>Interrupt disabled.</description>
36061 <description>Interrupt enabled.</description>
36068 <description>Access to Reserved Address Enable</description>
36074 <description>Interrupt disabled.</description>
36079 <description>Interrupt enabled.</description>
36088 <description>Interrupt Line Select</description>
36096 <description>Rx FIFO 0 New Message Interrupt Line</description>
36102 <description>Interrupt assigned to interrupt line CORE0.</description>
36107 <description>Interrupt assigned to interrupt line CORE1.</description>
36114 <description>Rx FIFO 0 Watermark Reached Interrupt Line</description>
36120 <description>Interrupt assigned to interrupt line CORE0.</description>
36125 <description>Interrupt assigned to interrupt line CORE1.</description>
36132 <description>Rx FIFO 0 Full Interrupt Line</description>
36138 <description>Interrupt assigned to interrupt line CORE0.</description>
36143 <description>Interrupt assigned to interrupt line CORE1.</description>
36150 <description>Rx FIFO 0 Message Lost Interrupt Line</description>
36156 <description>Interrupt assigned to interrupt line CORE0.</description>
36161 <description>Interrupt assigned to interrupt line CORE1.</description>
36168 <description>Rx FIFO 1 New Message Interrupt Line</description>
36174 <description>Interrupt assigned to interrupt line CORE0.</description>
36179 <description>Interrupt assigned to interrupt line CORE1.</description>
36186 <description>Rx FIFO 1 Watermark Reached Interrupt Line</description>
36192 <description>Interrupt assigned to interrupt line CORE0.</description>
36197 <description>Interrupt assigned to interrupt line CORE1.</description>
36204 <description>Rx FIFO 1 Full Interrupt Line</description>
36210 <description>Interrupt assigned to interrupt line CORE0.</description>
36215 <description>Interrupt assigned to interrupt line CORE1.</description>
36222 <description>Rx FIFO 1 Message Lost Interrupt Line</description>
36228 <description>Interrupt assigned to interrupt line CORE0.</description>
36233 <description>Interrupt assigned to interrupt line CORE1.</description>
36240 <description>High Priority Message Interrupt Line</description>
36246 <description>Interrupt assigned to interrupt line CORE0.</description>
36251 <description>Interrupt assigned to interrupt line CORE1.</description>
36258 <description>Transmission Completed Interrupt Line</description>
36264 <description>Interrupt assigned to interrupt line CORE0.</description>
36269 <description>Interrupt assigned to interrupt line CORE1.</description>
36276 <description>Transmission Cancellation Finished Interrupt Line</description>
36282 <description>Interrupt assigned to interrupt line CORE0.</description>
36287 <description>Interrupt assigned to interrupt line CORE1.</description>
36294 <description>Tx FIFO Empty Interrupt Line</description>
36300 <description>Interrupt assigned to interrupt line CORE0.</description>
36305 <description>Interrupt assigned to interrupt line CORE1.</description>
36312 <description>Tx Event FIFO New Entry Interrupt Line</description>
36318 <description>Interrupt assigned to interrupt line CORE0.</description>
36323 <description>Interrupt assigned to interrupt line CORE1.</description>
36330 <description>Tx Event FIFO Watermark Reached Interrupt Line</description>
36336 <description>Interrupt assigned to interrupt line CORE0.</description>
36341 <description>Interrupt assigned to interrupt line CORE1.</description>
36348 <description>Tx Event FIFO Full Interrupt Line</description>
36354 <description>Interrupt assigned to interrupt line CORE0.</description>
36359 <description>Interrupt assigned to interrupt line CORE1.</description>
36366 <description>Tx Event FIFO Event Lost Interrupt Line</description>
36372 <description>Interrupt assigned to interrupt line CORE0.</description>
36377 <description>Interrupt assigned to interrupt line CORE1.</description>
36384 <description>Timestamp Wraparound Interrupt Line</description>
36390 <description>Interrupt assigned to interrupt line CORE0.</description>
36395 <description>Interrupt assigned to interrupt line CORE1.</description>
36402 <description>Message RAM Access Failure Interrupt Line</description>
36408 <description>Interrupt assigned to interrupt line CORE0.</description>
36413 <description>Interrupt assigned to interrupt line CORE1.</description>
36420 <description>Timeout Occurred Interrupt Line</description>
36426 <description>Interrupt assigned to interrupt line CORE0.</description>
36431 <description>Interrupt assigned to interrupt line CORE1.</description>
36438 <description>Message stored to Dedicated Rx Buffer Interrupt Line</description>
36444 <description>Interrupt assigned to interrupt line CORE0.</description>
36449 <description>Interrupt assigned to interrupt line CORE1.</description>
36456 <description>Bus Error Uncorrected Interrupt Line</description>
36462 <description>Interrupt assigned to interrupt line CORE0.</description>
36467 <description>Interrupt assigned to interrupt line CORE1.</description>
36474 <description>Error Logging Overflow Interrupt Line</description>
36480 <description>Interrupt assigned to interrupt line CORE0.</description>
36485 <description>Interrupt assigned to interrupt line CORE1.</description>
36492 <description>Error Passive Interrupt Line</description>
36498 <description>Interrupt assigned to interrupt line CORE0.</description>
36503 <description>Interrupt assigned to interrupt line CORE1.</description>
36510 <description>Warning Status Interrupt Line</description>
36516 <description>Interrupt assigned to interrupt line CORE0.</description>
36521 <description>Interrupt assigned to interrupt line CORE1.</description>
36528 <description>Bus_Off Status Interrupt Line</description>
36534 <description>Interrupt assigned to interrupt line CORE0.</description>
36539 <description>Interrupt assigned to interrupt line CORE1.</description>
36546 <description>Watchdog Interrupt Line</description>
36552 <description>Interrupt assigned to interrupt line CORE0.</description>
36557 <description>Interrupt assigned to interrupt line CORE1.</description>
36564 <description>Protocol Error in Arbitration Phase Line</description>
36570 <description>Interrupt assigned to interrupt line CORE0.</description>
36575 <description>Interrupt assigned to interrupt line CORE1.</description>
36582 <description>Protocol Error in Data Phase Line</description>
36588 <description>Interrupt assigned to interrupt line CORE0.</description>
36593 <description>Interrupt assigned to interrupt line CORE1.</description>
36600 <description>Access to Reserved Address Line</description>
36606 <description>Interrupt assigned to interrupt line CORE0.</description>
36611 <description>Interrupt assigned to interrupt line CORE1.</description>
36620 <description>Interrupt Line Enable</description>
36628 <description>Enable Interrupt Line 0</description>
36634 <description>Interrupt line CORE0 disabled.</description>
36639 <description>Interrupt line CORE0 enabled.</description>
36646 <description>Enable Interrupt Line 1</description>
36652 <description>Interrupt line CORE1 disabled.</description>
36657 <description>Interrupt line CORE1 enabled.</description>
36666 <description>Global Filter Configuration</description>
36674 <description>Reject Remote Frames Extended</description>
36680 <description>Filter remote frames with 29-bit extended IDs.</description>
36685 <description>Reject all remote frames with 29-bit extended IDs.</description>
36692 <description>Reject Remote Frames Standard</description>
36698 <description>Filter remote frames with 11-bit standard IDs.</description>
36703 <description>Reject all remote frames with 11-bit standard IDs.</description>
36710 <description>Accept Non-matching Frames Extended</description>
36716 <description>Accept in Rx FIFO 0.</description>
36721 <description>Accept in Rx FIFO 1.</description>
36726 <description>Reject in both Rx FIFOs.</description>
36731 <description>Reject in both Rx FIFOs.</description>
36743 <description>Accept in Rx FIFO 0.</description>
36748 <description>Accept in Rx FIFO 1.</description>
36753 <description>Reject in both Rx FIFOs.</description>
36758 <description>Reject in both Rx FIFOs.</description>
36767 <description>Standard ID Filter Configuration</description>
36775 <description>Filter List Standard Start Address</description>
36781 <description>List Size Standard</description>
36789 <description>Extended ID Filter Configuration</description>
36797 <description>Filter List Extended Start Address</description>
36803 <description>List Size Extended</description>
36811 <description>Extended ID AND Mask</description>
36819 <description>Extended ID Mask</description>
36827 <description>High Priority Message Status</description>
36835 <description>Buffer Index</description>
36841 <description>Message Storage Indicator</description>
36847 <description>No FIFO selected.</description>
36852 <description>FIFO message lost.</description>
36857 <description>Message stored in FIFO 0.</description>
36862 <description>Message stored in FIFO 1.</description>
36869 <description>Filter Index</description>
36875 <description>Filter List</description>
36881 <description>Standard Filter List.</description>
36886 <description>Extended Filter List.</description>
36895 <description>New Data 1</description>
36903 <description>New Data</description>
36909 <description>Rx Buffer not updated.</description>
36914 <description>Rx Buffer updated from new message.</description>
36923 <description>New Data 2</description>
36931 <description>New Data</description>
36937 <description>Rx Buffer not updated.</description>
36942 <description>Rx Buffer updated from new message.</description>
36951 <description>Rx FIFO 0 Configuration</description>
36959 <description>Rx FIFO 0 Start Address</description>
36965 <description>Rx FIFO 0 Size</description>
36971 <description>Rx FIFO 0 Watermark</description>
36977 <description>FIFO 0 Operation Mode</description>
36983 <description>FIFO 0 blocking mode.</description>
36988 <description>FIFO 0 overwrite mode.</description>
36997 <description>Rx FIFO 0 Status</description>
37005 <description>Rx FIFO 0 Fill Leve</description>
37011 <description>Rx FIFO 0 Get Index</description>
37017 <description>Rx FIFO 0 Put Index</description>
37023 <description>Rx FIFO 0 Full</description>
37029 <description>Rx FIFO 0 not full.</description>
37034 <description>Rx FIFO 0 full.</description>
37041 <description>Rx FIFO 0 Message Lost</description>
37047 <description>No Rx FIFO 0 message lost.</description>
37052 …<description>Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero.</desc…
37061 <description>Rx FIFO 0 Acknowledge</description>
37069 <description>Rx FIFO 0 Acknowledge Index</description>
37077 <description>Rx Buffer Configuration</description>
37085 <description>Rx Buffer Start Address</description>
37093 <description>Rx FIFO 1 Configuration</description>
37101 <description>Rx FIFO 1 Start Address</description>
37107 <description>Rx FIFO 1 Size</description>
37113 <description>Rx FIFO 1 Watermark</description>
37119 <description>FIFO 1 Operation Mode</description>
37125 <description>FIFO 1 blocking mode</description>
37130 <description>FIFO 1 overwrite mode</description>
37139 <description>Rx FIFO 1 Status</description>
37147 <description>Rx FIFO 1 Fill Level</description>
37153 <description>Rx FIFO 1 Get Index</description>
37159 <description>Rx FIFO 1 Put Index</description>
37165 <description>Rx FIFO 1 Full</description>
37171 <description>Rx FIFO 1 not full</description>
37176 <description>Rx FIFO 1 full</description>
37183 <description>Rx FIFO 1 Message Lost</description>
37189 <description>No Rx FIFO 1 message lost</description>
37194 …<description>Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero</descr…
37201 <description>Debug Message Status</description>
37207 …<description>Idle state, wait for reception of debug messages, DMA request is cleared</description>
37212 <description>Debug message A received</description>
37217 <description>Debug messages A, B received</description>
37222 <description>Debug messages A, B, C received, DMA request is set</description>
37231 <description>Rx FIFO 1 Acknowledge</description>
37239 <description>Rx FIFO 1 Acknowledge Index</description>
37247 <description>Rx Buffer / FIFO Element Size Configuration</description>
37255 <description>Rx FIFO 0 Data Field Size</description>
37261 <description>8 byte data field</description>
37266 <description>12 byte data field</description>
37271 <description>16 byte data field</description>
37276 <description>20 byte data field</description>
37281 <description>24 byte data field</description>
37286 <description>32 byte data field</description>
37291 <description>48 byte data field</description>
37296 <description>64 byte data field</description>
37303 <description>Rx FIFO 1 Data Field Size</description>
37309 <description>8 byte data field</description>
37314 <description>12 byte data field</description>
37319 <description>16 byte data field</description>
37324 <description>20 byte data field</description>
37329 <description>24 byte data field</description>
37334 <description>32 byte data field</description>
37339 <description>48 byte data field</description>
37344 <description>64 byte data field</description>
37351 <description>Rx Buffer Data Field Size</description>
37357 <description>8 byte data field</description>
37362 <description>12 byte data field</description>
37367 <description>16 byte data field</description>
37372 <description>20 byte data field</description>
37377 <description>24 byte data field</description>
37382 <description>32 byte data field</description>
37387 <description>48 byte data field</description>
37392 <description>64 byte data field</description>
37401 <description>Tx Buffer Configuration</description>
37409 <description>Tx Buffers Start Address</description>
37415 <description>Number of Dedicated Transmit Buffers</description>
37421 <description>Transmit FIFO/Queue Size</description>
37427 <description>Tx FIFO/Queue Mode</description>
37433 <description>Tx FIFO operation</description>
37438 <description>Tx Queue operation</description>
37447 <description>Tx FIFO/Queue Status</description>
37455 <description>Tx FIFO Free Level</description>
37461 <description>Tx FIFO Get Index</description>
37467 <description>Tx FIFO/Queue Put Index</description>
37473 <description>Tx FIFO/Queue Full</description>
37479 <description>Tx FIFO/Queue not full</description>
37484 <description>Tx FIFO/Queue full</description>
37493 <description>Tx Buffer Element Size Configuration</description>
37501 <description>Tx Buffer Data Field Size</description>
37507 <description>8 byte data field</description>
37512 <description>12 byte data field</description>
37517 <description>16 byte data field</description>
37522 <description>20 byte data field</description>
37527 <description>24 byte data field</description>
37532 <description>32 byte data field</description>
37537 <description>48 byte data field</description>
37542 <description>64 byte data field</description>
37551 <description>Tx Buffer Request Pending</description>
37559 <description>Transmission Request Pending</description>
37565 <description>No transmission request pending</description>
37570 <description>Transmission request pending</description>
37579 <description>Tx Buffer Add Request</description>
37587 <description>Add Request</description>
37593 <description>No transmission request added</description>
37598 <description>Transmission requested added</description>
37607 <description>Tx Buffer Cancellation Request</description>
37615 <description>Cancellation Request</description>
37621 <description>No cancellation pending</description>
37626 <description>Cancellation pending</description>
37635 <description>Tx Buffer Transmission Occurred</description>
37643 <description>Transmission Occurred</description>
37649 <description>No transmission occurred</description>
37654 <description>Transmission occurred</description>
37663 <description>Tx Buffer Cancellation Finished</description>
37671 <description>Cancellation Finished</description>
37677 <description>No transmit buffer cancellation</description>
37682 <description>Transmit buffer cancellation finished</description>
37691 <description>Tx Buffer Transmission Interrupt Enable</description>
37699 <description>Transmission Interrupt Enable</description>
37705 <description>Transmission interrupt disabled</description>
37710 <description>Transmission interrupt enable</description>
37719 <description>Tx Buffer Cancellation Finished Interrupt Enable</description>
37727 <description>Cancellation Finished Interrupt Enable</description>
37733 <description>Cancellation finished interrupt disabled</description>
37738 <description>Cancellation finished interrupt enabled</description>
37747 <description>Tx Event FIFO Configuration</description>
37755 <description>Event FIFO Start Address</description>
37761 <description>Event FIFO Size</description>
37767 <description>Event FIFO Watermark</description>
37775 <description>Tx Event FIFO Status</description>
37783 <description>Event FIFO Fill Level</description>
37789 <description>Event FIFO Get Index</description>
37795 <description>Event FIFO Put Index</description>
37801 <description>Event FIFO Full</description>
37807 <description>Tx Event FIFO not full</description>
37812 <description>Tx Event FIFO full</description>
37819 <description>Tx Event FIFO Element Lost</description>
37825 <description>No Tx Event FIFO element lost</description>
37830 …<description>Tx Event FIFO element lost, also set after wr ite attempt to Tx Event FIFO of siz e z…
37839 <description>Tx Event FIFO Acknowledge</description>
37847 <description>Event FIFO Acknowledge Index</description>
37857 <description>DMU</description>
37873 <description>DMU Core Release</description>
37881 <description>Core Release</description>
37887 <description>Step of Core Release</description>
37893 <description>Sub-step of Core Release</description>
37899 <description>Time Stamp Year</description>
37905 <description>Time Stamp Month</description>
37911 <description>Time Stamp Day</description>
37919 <description>DMU Internals</description>
37927 <description>TX Service Request line of DMU</description>
37933 <description>No TX DMA service requested</description>
37938 <description>TX DMA Service requested</description>
37945 <description>RX0 Service Request line of DMU</description>
37951 <description>No RX0 DMA service requested</description>
37956 <description>RX0 DMA Service requested</description>
37963 <description>RX1 Service Request line of DMU</description>
37969 <description>No RX1 DMA service requested</description>
37974 <description>RX1 DMA Service requested</description>
37981 <description>TX Event Service Request line of DMU</description>
37987 <description>No TX Event DMA service requested</description>
37992 <description>TX Event DMA Service requested</description>
37999 <description>TX FIFO/Queue Put Index Previous</description>
38005 <description>DMU is enabled</description>
38011 <description>DMU is disabled</description>
38016 <description>DMU is enabled and can process DMA data</description>
38023 <description>Detect Element Handler State</description>
38029 <description>Detect DMU Element Service</description>
38035 … <description>Queueing of DMU Element does not activate interrupt flag</description>
38040 …<description>Queueing of DMU Element will activate interrupt flag when DMUI.EHS = DMUI.DEHS</descr…
38047 <description>Detect DMU Element Service</description>
38053 … <description>Queueing of DMU Element does not activate interrupt flag</description>
38058 …<description>Queueing of DMU Element will activate interrupt flag when DMUI.EHS = DMUI.DEHS</descr…
38065 <description>Detect DMU Element Service</description>
38071 … <description>Queueing of DMU Element does not activate interrupt flag</description>
38076 …<description>Queueing of DMU Element will activate interrupt flag when DMUI.EHS = DMUI.DEHS</descr…
38083 <description>Detect DMU Element Service</description>
38089 … <description>Queueing of DMU Element does not activate interrupt flag</description>
38094 …<description>Queueing of DMU Element will activate interrupt flag when DMUI.EHS = DMUI.DEHS</descr…
38101 <description>Element Handler State</description>
38107 <description>wait for bit MCAN:CCCR.CCE getting zero</description>
38112 <description>wait for Start Address</description>
38117 <description>wait for Trigger Address</description>
38122 <description>wait for transfer of Element word</description>
38127 <description>acknowledge to MCAN</description>
38132 <description>exception recovery</description>
38139 <description>Actual DMU Element Service</description>
38145 <description>DMU Virtual Buffer is currently not served</description>
38150 <description>DMU Virtual Buffer is currently served</description>
38157 <description>Actual DMU Element Service</description>
38163 <description>DMU Virtual Buffer is currently not served</description>
38168 <description>DMU Virtual Buffer is currently served</description>
38175 <description>Actual DMU Element Service</description>
38181 <description>DMU Virtual Buffer is currently not served</description>
38186 <description>DMU Virtual Buffer is currently served</description>
38193 <description>Actual DMU Element Service</description>
38199 <description>DMU Virtual Buffer is currently not served</description>
38204 <description>DMU Virtual Buffer is currently served</description>
38213 <description>DMU Queueing Counter</description>
38221 <description>TX Element Enqueueing Counter</description>
38227 <description>RX0 Element Dequeueing Counter</description>
38233 <description>RX1 Element Dequeueing Counter</description>
38239 <description>TX Event Element Dequeueing Counter</description>
38247 <description>DMU Interrupt Register</description>
38255 <description>TX Element Not Start Address</description>
38261 <description>Write '1' to clear interrupt flag</description>
38266 <description>No illegal write access</description>
38271 …<description>Write to TX Element begins without using start address, exception recovery started.</…
38278 <description>TX Element Illegal Enqueueing</description>
38284 <description>Write '1' to clear interrupt flag</description>
38289 <description>No illegal enqueueing</description>
38294 …<description>Start of enqueueing without request detected, exception recovery started.</descriptio…
38301 <description>TX Element Illegal Access Sequence</description>
38307 <description>Write '1' to clear interrupt flag</description>
38312 <description>No illegal addressing sequence detected</description>
38317 …<description>Accesses are not strictly linear to ascending and consecutive addresses, exception re…
38324 <description>TX Element Illegal DLC</description>
38330 <description>Write '1' to clear interrupt flag</description>
38335 <description>No illegal DLC detected</description>
38340 … <description>DLC exceeds Tx Buffer element size of MCAN, exception recovery started.</description>
38347 <description>TX Element Write After Trigger Address</description>
38353 <description>Write '1' to clear interrupt flag</description>
38358 <description>No write after Trigger Address</description>
38363 <description>Write after Trigger address detected</description>
38370 <description>TX Element Illegal Read</description>
38376 <description>Write '1' to clear interrupt flag</description>
38381 <description>No read access</description>
38386 …<description>Illegal read access to DMU TX Element section detected, exception recovery started.</…
38393 …<description>A successful enqueueing of a Tx message with the DMU TX Element section sets this fla…
38399 <description>Write '1' to clear interrupt flag</description>
38404 <description>No Tx message enqueued</description>
38409 <description>Tx message successfully enqueued</description>
38416 <description>RX0 Element Not Start Address</description>
38422 <description>Write '1' to clear interrupt flag</description>
38427 <description>No illegal read access</description>
38432 …<description>Read from RX0 Element begins without using start address, exception recovery started.…
38439 <description>RX0 Element Illegal Dequeueing</description>
38445 <description>Write '1' to clear interrupt flag</description>
38450 <description>No illegal dequeueing</description>
38455 …<description>Start of dequeueing without request detected, exception recovery started,</descriptio…
38462 <description>RX0 Element Illegal Access Sequence</description>
38468 <description>Write '1' to clear interrupt flag</description>
38473 <description>No illegal addressing sequence detected</description>
38478 …<description>Accesses are not strictly linear to ascending and consecutive addresses, exception re…
38485 <description>RX0 Element Illegal Write</description>
38491 <description>Write '1' to clear interrupt flag</description>
38496 <description>No write access detected</description>
38501 …<description>Illegal write access to DMU RX0 Element detected, exception recovery started.</descri…
38508 <description>RX0 Element Dequeued</description>
38514 <description>Write '1' to clear interrupt flag</description>
38519 <description>No Rx message dequeued</description>
38524 <description>Rx message successfully dequeued</description>
38531 <description>RX0 Element Illegal Overwrite by timestamp</description>
38537 <description>Write '1' to clear interrupt flag</description>
38542 <description>No illegal overwrite detected</description>
38547 … <description>DMU has internally overwritten the last element word of a SYNC message</description>
38554 <description>Bus Error Uncorrected</description>
38560 <description>Write '1' to clear interrupt flag</description>
38565 … <description>No read slave error detected when reading from Message RAM</description>
38570 <description>Read slave error detected</description>
38577 <description>RX1 Element Not Start Address</description>
38583 <description>Write '1' to clear interrupt flag</description>
38588 <description>No illegal read access</description>
38593 …<description>Read from RX1 Element begins without using start address, exception recovery started.…
38600 <description>RX1 Element Illegal Dequeueing</description>
38606 <description>Write '1' to clear interrupt flag</description>
38611 <description>No illegal dequeueing</description>
38616 …<description>Start of dequeueing without request detected, exception recovery started,</descriptio…
38623 <description>RX0 Element Illegal Access Sequence</description>
38629 <description>Write '1' to clear interrupt flag</description>
38634 <description>No illegal addressing sequence detected</description>
38639 …<description>Accesses are not strictly linear to ascending and consecutive addresses, exception re…
38646 <description>RX1 Element Illegal Write</description>
38652 <description>Write '1' to clear interrupt flag</description>
38657 <description>No write access detected</description>
38662 …<description>Illegal write access to DMU RX1 Element detected, exception recovery started.</descri…
38669 <description>RX0 Element Dequeued</description>
38675 <description>Write '1' to clear interrupt flag</description>
38680 <description>No Rx message dequeued</description>
38685 <description>Rx message successfully dequeued</description>
38692 <description>RX1 Element Illegal Overwrite by timestamp</description>
38698 <description>Write '1' to clear interrupt flag</description>
38703 <description>No illegal overwrite detected</description>
38708 … <description>DMU has internally overwritten the last element word of a SYNC message</description>
38715 <description>TX Event Element Not Start Address</description>
38721 <description>Write '1' to clear interrupt flag</description>
38726 <description>No illegal read access</description>
38731 …<description>Read from TX Event Element begins without using start address, exception recovery sta…
38738 <description>TX Event Element Illegal Dequeueing</description>
38744 <description>Write '1' to clear interrupt flag</description>
38749 <description>No illegal dequeueing</description>
38754 …<description>Start of dequeueing without request detected, exception recovery started.</descriptio…
38761 <description>TX Event Element Illegal Access Sequence</description>
38767 <description>Write '1' to clear interrupt flag</description>
38772 <description>No illegal addressing sequence detected</description>
38777 …<description>Accesses are not strictly linear to ascending and consecutive addresses, exception re…
38784 <description>TX Event Element Illegal Write</description>
38790 <description>Write '1' to clear interrupt flag</description>
38795 <description>No write access detected</description>
38800 …<description>Illegal write access to DMU TX Event Element detected, exception recovery started.</d…
38807 <description>TX Event Element Dequeued</description>
38813 <description>Write '1' to clear interrupt flag</description>
38818 <description>No TX Event Element dequeued</description>
38823 <description>TX Event Element successfully dequeued</description>
38830 <description>Debug Trigger</description>
38836 <description>Write '1' to clear interrupt flag</description>
38841 <description>Debug point not reached</description>
38846 <description>Debug point reached</description>
38853 <description>Illegal Access while in Configuration mode</description>
38859 <description>Write '1' to clear interrupt flag</description>
38864 <description>No Illegal Access while CCE mode</description>
38869 <description>Illegal Access while CCE mode</description>
38878 <description>DMU Interrupt Enable</description>
38886 <description>TX Element Not Start Address Enable</description>
38892 <description>Flag does not activate the interrupt line DMU</description>
38897 <description>the interrupt line DMU will be activated</description>
38906 <description>DMU Configuration</description>
38914 <description>Transfer Timestamp</description>
38920 <description>No timestamp will be transferred via DMU Virtual Buffer</description>
38925 …<description>Timestamp of message will be transferred from TSU via DMU Virtual Buffer</description>
38936 <description>System Trace Macrocell data buffer</description>
38953 <description>Unspecified</description>
38961 …description>Description collection: STM extended stimulus port data buffer area for domain n. NonS…
38974 <description>TDDCONF</description>
38988 <description>System power-up request</description>
38996 <description>Activate power-up request</description>
39002 <description>Power-up request not active</description>
39007 <description>Power-up request active</description>
39016 <description>Debug power-up request</description>
39024 <description>Activate power-up request</description>
39030 <description>Power-up request not active</description>
39035 <description>Power-up request active</description>
39044 <description>Trace port trace clock speed</description>
39052 <description>Trace clock speed</description>
39058 <description>Speed 80MHz</description>
39063 <description>Speed 40MHz</description>
39068 <description>Speed 20MHz</description>
39073 <description>Speed 10MHz</description>
39082 …<description>Combined effective system status of both SWJ-DP and TDDCONF registers originated powe…
39090 <description>System powerup request status</description>
39096 <description>Power not requested</description>
39101 <description>Power requested</description>
39108 <description>Debug domain powerup request status</description>
39114 <description>Power not requested</description>
39119 <description>Power requested</description>
39130 <description>System Trace Macrocell</description>
39144 <description>Controls the DMA transfer request mechanism.</description>
39152 …<description>Determines the sensitivity of the DMA request to the current buffer level in the STM<…
39158 <description>Buffer is &lt;25 percent full.</description>
39163 <description>Buffer is &lt;50 percent full.</description>
39168 <description>Buffer is &lt;75 percent full.</description>
39173 <description>Buffer is &lt;100 percent full.</description>
39182 …<description>Indicates the STPv2 master number of hardware event trace. This number is the master …
39190 …<description>The STPv2 master number that hardware event traces should be associated with.</descri…
39198 <description>Indicates the features of the STM.</description>
39206 <description>STMHETER support</description>
39212 <description>The feature is not implemented.</description>
39217 <description>The feature is implemented.</description>
39224 <description>Hardware event error detection support</description>
39230 <description>The feature is not implemented.</description>
39235 <description>The feature is implemented.</description>
39242 <description>STMHEMASTR support</description>
39248 <description>The feature is not implemented.</description>
39253 <description>The feature is implemented.</description>
39260 <description>The number of hardware events supported by the STM</description>
39268 <description>Indicates the features of hardware event tracing in the STM.</description>
39276 <description>The CLASS field identifies the programmers model</description>
39282 <description>Hardware Event Control programmers model</description>
39289 … <description>The CLASSREV field identifies the revision of the programmers model</description>
39295 …<description>The VENDSPEC field identifies any vendor specific modifications or mappings</descript…
39303 <description>Controls the STM settings.</description>
39311 <description>Global STM enable</description>
39317 <description>The STM is disabled.</description>
39322 <description>The STM is enabled.</description>
39329 <description>Enable or disable timestamp bundling.</description>
39335 …description>Time stamps are disabled. Requests for timestamp generation are ignored, and stimulus …
39340 …<description>Time stamps are enabled. If stimulus writes select timestamping, a timestamp is outpu…
39347 <description>STMSYNCR is implemented so this value is Read As One.</description>
39353 <description>The STM Sync feature is disabled.</description>
39358 <description>The STM Sync feature is enabled.</description>
39365 <description>Compression Enable for Stimulus Ports.</description>
39371 …<description>Compression disabled, data transfers are transmitted at the size of the transaction.<…
39376 … <description>Compression enabled, data transfers are compressed to save bandwidth.</description>
39383 …<description>ATB Trace ID. Setting this value to all zeroes might result in Unpredictable tracing.…
39389 <description>STM is busy, for example the STM trace FIFO is not empty.</description>
39395 <description>STM is not busy.</description>
39400 <description>STM is busy.</description>
39409 <description>Used for implementation defined STM controls.</description>
39417 <description>FIFO Auto-flush.</description>
39423 <description>Auto-flush is disabled.</description>
39428 …<description>Auto-flush is enabled. The STM automatically drains all data it has even if the ATB i…
39435 <description>Is ASYNC priority higher than trace?</description>
39441 <description>ASYNC priority is always lower than trace.</description>
39446 … <description>ASYNC priority escalates on second synchronization request.</description>
39453 <description>Controls arbitration between AXI and HW during flush.</description>
39459 …<description>Priority inversion, when AXI flush is finished, HW gets priority until HW flush is do…
39464 … <description>Priority inversion disabled, AXI always has priority over HW.</description>
39471 … <description>Provides override control for architectural clock gate enable.</description>
39477 … <description>No override, clock gate is controlled by the state of STM.</description>
39482 <description>Override, clock is enabled.</description>
39489 <description>Provides override control for the AFREADY output</description>
39495 <description>No override, AFREADY is controlled by the state of STM.</description>
39500 <description>Override, AFREADY is driven HIGH.</description>
39509 <description>Indicates the features of the STM.</description>
39517 <description>Indicates the implemented STM protocol.</description>
39523 <description>STM implements the STPV2 protocol.</description>
39530 <description>Timestamp support.</description>
39536 <description>Absolute timestamps implemented.</description>
39543 <description>Timestamp frequency indication configuration.</description>
39549 <description>STMTSFREQR is read-only.</description>
39554 <description>STMTSFREQR is read-write.</description>
39561 <description>Timestamp force configuration.</description>
39567 <description>STMTSSTIMR bit 0 is read-only.</description>
39572 <description>STMTSSTIMR bit 0 is read-write.</description>
39579 <description>Trace bus support.</description>
39585 <description>Trigger control support.</description>
39591 <description>Timestamp prescale support</description>
39597 <description>Timestamp prescale is not implemented.</description>
39602 <description>Timestamp prescale is implemented.</description>
39609 <description>STMTCSR.HWTEN support</description>
39615 <description>STMTCSR.HWTEN is not implemented</description>
39622 <description>STMTCSR.SYNCEN support</description>
39628 <description>STMTCSR.SYNCEN implemented but always reads as b1</description>
39635 <description>STMTCSR.SWOEN support</description>
39641 <description>STMTCSR.SWOEN not implemented</description>
39650 <description>Indicates the features of the STM.</description>
39658 <description>STMSPTER support.</description>
39664 <description>STMSPTER is implemented.</description>
39671 <description>STMSPER presence.</description>
39677 <description>STMSPER is implemented.</description>
39682 <description>STMSPER is not implemented.</description>
39689 <description>Data compression on stimulus ports support.</description>
39695 …<description>Data compression support is programmable. STMTCSR.COMPEN is implemented.</description>
39702 <description>Timestamp force configuration.</description>
39708 <description>STMSPOVERRIDER and STMSPMOVERRIDER is not implemented.</description>
39713 <description>STMSPOVERRIDER and STMSPMOVERRIDER is implemented.</description>
39720 <description>STMPRIVMASKR support.</description>
39726 <description>STMPRIVMASKR is not implemented.</description>
39733 <description>Stimulus port transaction type support.</description>
39739 … <description>Both invariant timing and guaranteed transactions are supported.</description>
39746 <description>Fundamental data size.</description>
39752 <description>32-bit data.</description>
39759 <description>Stimulus port type support</description>
39765 <description>Only extended stimulus ports are implemented.</description>
39774 <description>Indicates the features of the STM.</description>
39782 <description>The number of stimulus ports masters implemented, minus 1.</description>
39788 <description>Example: 128 masters implemented.</description>
39797 <description>Integration Test for Cross-Trigger Outputs Register.</description>
39805 … <description>Sets the value of the TRIGOUTSPTE output in integration mode.</description>
39811 <description>Drive logic 0 on output.</description>
39816 <description>Drive logic 1 on output.</description>
39823 <description>Sets the value of the TRIGOUTSW output in integration mode.</description>
39829 <description>Drive logic 0 on output.</description>
39834 <description>Drive logic 1 on output.</description>
39841 … <description>Sets the value of the TRIGOUTHETE output in integration mode.</description>
39847 <description>Drive logic 0 on output.</description>
39852 <description>Drive logic 1 on output.</description>
39859 <description>Sets the value of the ASYNCOUT output in integration mode.</description>
39865 <description>Drive logic 0 on output.</description>
39870 <description>Drive logic 1 on output.</description>
39879 <description>Controls the value of the ATDATAM output in integration mode.</description>
39887 <description>Sets the value of the ATDATAM[0].</description>
39893 <description>Drive logic 0 on output.</description>
39898 <description>Drive logic 1 on output.</description>
39905 <description>Sets the value of the ATDATAM[7] output.</description>
39911 <description>Drive logic 0 on output.</description>
39916 <description>Drive logic 1 on output.</description>
39923 <description>Sets the value of the ATDATAM[15].</description>
39929 <description>Drive logic 0 on output.</description>
39934 <description>Drive logic 1 on output.</description>
39941 <description>Sets the value of the ATDATAM[23].</description>
39947 <description>Drive logic 0 on output.</description>
39952 <description>Drive logic 1 on output.</description>
39959 <description>Sets the value of the ATDATAM[31].</description>
39965 <description>Drive logic 0 on output.</description>
39970 <description>Drive logic 1 on output.</description>
39979 <description>Controls the value of the ATDATAM output in integration mode.</description>
39987 <description>Reads the value of the ATREADYM input.</description>
39993 <description>Pin is at logic 0.</description>
39998 <description>Pin is at logic 1.</description>
40005 <description>Reads the value of the AFVALIDM input.</description>
40011 <description>Pin is at logic 0.</description>
40016 <description>Pin is at logic 1.</description>
40025 <description>Controls the value of the ATIDM output in integration mode.</description>
40033 <description>Sets the value of pin 0 of the ATIDM output.</description>
40039 <description>Pin is at logic 0.</description>
40044 <description>Pin is at logic 1.</description>
40051 <description>Sets the value of pin 1 of the ATIDM output.</description>
40057 <description>Pin is at logic 0.</description>
40062 <description>Pin is at logic 1.</description>
40069 <description>Sets the value of pin 2 of the ATIDM output.</description>
40075 <description>Pin is at logic 0.</description>
40080 <description>Pin is at logic 1.</description>
40087 <description>Sets the value of pin 3 of the ATIDM output.</description>
40093 <description>Pin is at logic 0.</description>
40098 <description>Pin is at logic 1.</description>
40105 <description>Sets the value of pin 4 of the ATIDM output.</description>
40111 <description>Pin is at logic 0.</description>
40116 <description>Pin is at logic 1.</description>
40123 <description>Sets the value of pin 5 of the ATIDM output.</description>
40129 <description>Pin is at logic 0.</description>
40134 <description>Pin is at logic 1.</description>
40141 <description>Sets the value of pin 6 of the ATIDM output.</description>
40147 <description>Pin is at logic 0.</description>
40152 <description>Pin is at logic 1.</description>
40161 …<description>Controls the value of the ATVALIDM, AFREADYM, and ATBYTESM outputs in integration mod…
40169 <description>Sets the value of the ATVALIDM output.</description>
40175 <description>Pin is at logic 0.</description>
40180 <description>Pin is at logic 1.</description>
40187 <description>Sets the value of the AFREADYM_W output.</description>
40193 <description>Pin is at logic 0.</description>
40198 <description>Pin is at logic 1.</description>
40205 <description>Sets the value of pin 0 of the ATBYTESM output.</description>
40211 <description>Pin is at logic 0.</description>
40216 <description>Pin is at logic 1.</description>
40223 <description>Sets the value of pin 1 of the ATBYTESM output.</description>
40229 <description>Pin is at logic 0.</description>
40234 <description>Pin is at logic 1.</description>
40243 <description>Used to enable topology detection.
40245 …he component can be directly controlled for integration testing and topology solving.</description>
40253 …description>Enables the component to switch from functional mode to integration mode and back. If …
40259 <description>Integration mode is disabled.</description>
40264 <description>Integration mode is Enabled.</description>
40273 <description>This is used to enable write access to device registers.</description>
40281 …<description>A write of 0xC5ACCE55 enables further write access to this device. Any other write re…
40287 <description>Unlock register interface.</description>
40296 …<description>This indicates the status of the lock control mechanism. This lock prevents accidenta…
40300 … For most components this covers all registers except for the Lock Access Register.</description>
40308 … <description>Indicates that a lock control mechanism exists for this device.</description>
40314 …<description>No lock control mechanism exists, writes to the Lock Access Register are ignored.</de…
40319 <description>Lock control mechanism is present.</description>
40326 <description>Returns the current status of the Lock.</description>
40332 <description>Write access is allowed to this device.</description>
40337 …<description>Write access to the component is blocked. All writes to control registers are ignored…
40344 …<description>Indicates if the Lock Access Register is implemented as 8-bit or 32-bit.</description>
40350 … <description>This component implements a 32-bit Lock Access Register.</description>
40355 … <description>This component implements an 8-bit Lock Access Register.</description>
40364 <description>Indicates the current level of tracing permitted by the system</description>
40372 <description>Non-secure Invasive Debug</description>
40378 <description>The feature is not implemented.</description>
40383 <description>The feature is implemented.</description>
40390 <description>Non-secure Non-Invasive Debug</description>
40396 <description>The feature is not implemented.</description>
40401 <description>The feature is implemented.</description>
40408 <description>Secure Invasive Debug</description>
40414 <description>The feature is not implemented.</description>
40419 <description>The feature is implemented.</description>
40426 <description>Secure Non-Invasive Debug</description>
40432 <description>The feature is not implemented.</description>
40437 <description>The feature is implemented.</description>
40446 <description>Indicates the capabilities of the STM.</description>
40454 … <description>This value indicates the number of stimulus ports implemented.</description>
40460 <description>Maximum 65,536 stimulus ports can be implemented.</description>
40469 <description>Controls the single-shot comparator.</description>
40477 <description>The main type of the component</description>
40483 <description>Peripheral is a trace source.</description>
40490 <description>The sub-type of the component</description>
40496 <description>Peripheral is a stimulus trace source.</description>
40505 <description>Coresight peripheral identification registers.</description>
40513 <description>Coresight peripheral identification registers.</description>
40521 <description>Coresight peripheral identification registers.</description>
40529 <description>Coresight peripheral identification registers.</description>
40537 <description>Coresight peripheral identification registers.</description>
40545 <description>Coresight component identification registers.</description>
40553 <description>Coresight component identification registers.</description>
40561 <description>Coresight component identification registers.</description>
40569 <description>Coresight component identification registers.</description>
40579 <description>Trace Port Interface Unit</description>
40593 …<description>Each bit location is a single port size that is supported on the device.</description>
40601 <description>Indicates whether the TPIU supports port size of 1-bit.</description>
40607 <description>Port size 1 is not supported.</description>
40612 <description>Port size 1 is supported.</description>
40619 <description>Indicates whether the TPIU supports port size of 2-bit.</description>
40625 <description>Port size 2 is not supported.</description>
40630 <description>Port size 2 is supported.</description>
40637 <description>Indicates whether the TPIU supports port size of 3-bit.</description>
40643 <description>Port size 3 is not supported.</description>
40648 <description>Port size 3 is supported.</description>
40655 <description>Indicates whether the TPIU supports port size of 4-bit.</description>
40661 <description>Port size 4 is not supported.</description>
40666 <description>Port size 4 is supported.</description>
40673 <description>Indicates whether the TPIU supports port size of 5-bit.</description>
40679 <description>Port size 5 is not supported.</description>
40684 <description>Port size 5 is supported.</description>
40691 <description>Indicates whether the TPIU supports port size of 6-bit.</description>
40697 <description>Port size 6 is not supported.</description>
40702 <description>Port size 6 is supported.</description>
40709 <description>Indicates whether the TPIU supports port size of 7-bit.</description>
40715 <description>Port size 7 is not supported.</description>
40720 <description>Port size 7 is supported.</description>
40727 <description>Indicates whether the TPIU supports port size of 8-bit.</description>
40733 <description>Port size 8 is not supported.</description>
40738 <description>Port size 8 is supported.</description>
40745 <description>Indicates whether the TPIU supports port size of 9-bit.</description>
40751 <description>Port size 9 is not supported.</description>
40756 <description>Port size 9 is supported.</description>
40763 <description>Indicates whether the TPIU supports port size of 10-bit.</description>
40769 <description>Port size 10 is not supported.</description>
40774 <description>Port size 10 is supported.</description>
40781 <description>Indicates whether the TPIU supports port size of 11-bit.</description>
40787 <description>Port size 11 is not supported.</description>
40792 <description>Port size 11 is supported.</description>
40799 <description>Indicates whether the TPIU supports port size of 12-bit.</description>
40805 <description>Port size 12 is not supported.</description>
40810 <description>Port size 12 is supported.</description>
40817 <description>Indicates whether the TPIU supports port size of 13-bit.</description>
40823 <description>Port size 13 is not supported.</description>
40828 <description>Port size 13 is supported.</description>
40835 <description>Indicates whether the TPIU supports port size of 14-bit.</description>
40841 <description>Port size 14 is not supported.</description>
40846 <description>Port size 14 is supported.</description>
40853 <description>Indicates whether the TPIU supports port size of 15-bit.</description>
40859 <description>Port size 15 is not supported.</description>
40864 <description>Port size 15 is supported.</description>
40871 <description>Indicates whether the TPIU supports port size of 16-bit.</description>
40877 <description>Port size 16 is not supported.</description>
40882 <description>Port size 16 is supported.</description>
40889 <description>Indicates whether the TPIU supports port size of 17-bit.</description>
40895 <description>Port size 17 is not supported.</description>
40900 <description>Port size 17 is supported.</description>
40907 <description>Indicates whether the TPIU supports port size of 18-bit.</description>
40913 <description>Port size 18 is not supported.</description>
40918 <description>Port size 18 is supported.</description>
40925 <description>Indicates whether the TPIU supports port size of 19-bit.</description>
40931 <description>Port size 19 is not supported.</description>
40936 <description>Port size 19 is supported.</description>
40943 <description>Indicates whether the TPIU supports port size of 20-bit.</description>
40949 <description>Port size 20 is not supported.</description>
40954 <description>Port size 20 is supported.</description>
40961 <description>Indicates whether the TPIU supports port size of 21-bit.</description>
40967 <description>Port size 21 is not supported.</description>
40972 <description>Port size 21 is supported.</description>
40979 <description>Indicates whether the TPIU supports port size of 22-bit.</description>
40985 <description>Port size 22 is not supported.</description>
40990 <description>Port size 22 is supported.</description>
40997 <description>Indicates whether the TPIU supports port size of 23-bit.</description>
41003 <description>Port size 23 is not supported.</description>
41008 <description>Port size 23 is supported.</description>
41015 <description>Indicates whether the TPIU supports port size of 24-bit.</description>
41021 <description>Port size 24 is not supported.</description>
41026 <description>Port size 24 is supported.</description>
41033 <description>Indicates whether the TPIU supports port size of 25-bit.</description>
41039 <description>Port size 25 is not supported.</description>
41044 <description>Port size 25 is supported.</description>
41051 <description>Indicates whether the TPIU supports port size of 26-bit.</description>
41057 <description>Port size 26 is not supported.</description>
41062 <description>Port size 26 is supported.</description>
41069 <description>Indicates whether the TPIU supports port size of 27-bit.</description>
41075 <description>Port size 27 is not supported.</description>
41080 <description>Port size 27 is supported.</description>
41087 <description>Indicates whether the TPIU supports port size of 28-bit.</description>
41093 <description>Port size 28 is not supported.</description>
41098 <description>Port size 28 is supported.</description>
41105 <description>Indicates whether the TPIU supports port size of 29-bit.</description>
41111 <description>Port size 29 is not supported.</description>
41116 <description>Port size 29 is supported.</description>
41123 <description>Indicates whether the TPIU supports port size of 30-bit.</description>
41129 <description>Port size 30 is not supported.</description>
41134 <description>Port size 30 is supported.</description>
41141 <description>Indicates whether the TPIU supports port size of 31-bit.</description>
41147 <description>Port size 31 is not supported.</description>
41152 <description>Port size 31 is supported.</description>
41159 <description>Indicates whether the TPIU supports port size of 32-bit.</description>
41165 <description>Port size 32 is not supported.</description>
41170 <description>Port size 32 is supported.</description>
41179 …<description>Each bit location is a single port size. One bit can be set, and indicates the curren…
41187 <description>Indicates which port size is currently selected.</description>
41193 <description>Port size 1 is not selected.</description>
41198 <description>Port size 1 is selected.</description>
41205 <description>Indicates which port size is currently selected.</description>
41211 <description>Port size 2 is not selected.</description>
41216 <description>Port size 2 is selected.</description>
41223 <description>Indicates which port size is currently selected.</description>
41229 <description>Port size 3 is not selected.</description>
41234 <description>Port size 3 is selected.</description>
41241 <description>Indicates which port size is currently selected.</description>
41247 <description>Port size 4 is not selected.</description>
41252 <description>Port size 4 is selected.</description>
41259 <description>Indicates which port size is currently selected.</description>
41265 <description>Port size 5 is not selected.</description>
41270 <description>Port size 5 is selected.</description>
41277 <description>Indicates which port size is currently selected.</description>
41283 <description>Port size 6 is not selected.</description>
41288 <description>Port size 6 is selected.</description>
41295 <description>Indicates which port size is currently selected.</description>
41301 <description>Port size 7 is not selected.</description>
41306 <description>Port size 7 is selected.</description>
41313 <description>Indicates which port size is currently selected.</description>
41319 <description>Port size 8 is not selected.</description>
41324 <description>Port size 8 is selected.</description>
41331 <description>Indicates which port size is currently selected.</description>
41337 <description>Port size 9 is not selected.</description>
41342 <description>Port size 9 is selected.</description>
41349 <description>Indicates which port size is currently selected.</description>
41355 <description>Port size 10 is not selected.</description>
41360 <description>Port size 10 is selected.</description>
41367 <description>Indicates which port size is currently selected.</description>
41373 <description>Port size 11 is not selected.</description>
41378 <description>Port size 11 is selected.</description>
41385 <description>Indicates which port size is currently selected.</description>
41391 <description>Port size 12 is not selected.</description>
41396 <description>Port size 12 is selected.</description>
41403 <description>Indicates which port size is currently selected.</description>
41409 <description>Port size 13 is not selected.</description>
41414 <description>Port size 13 is selected.</description>
41421 <description>Indicates which port size is currently selected.</description>
41427 <description>Port size 14 is not selected.</description>
41432 <description>Port size 14 is selected.</description>
41439 <description>Indicates which port size is currently selected.</description>
41445 <description>Port size 15 is not selected.</description>
41450 <description>Port size 15 is selected.</description>
41457 <description>Indicates which port size is currently selected.</description>
41463 <description>Port size 16 is not selected.</description>
41468 <description>Port size 16 is selected.</description>
41475 <description>Indicates which port size is currently selected.</description>
41481 <description>Port size 17 is not selected.</description>
41486 <description>Port size 17 is selected.</description>
41493 <description>Indicates which port size is currently selected.</description>
41499 <description>Port size 18 is not selected.</description>
41504 <description>Port size 18 is selected.</description>
41511 <description>Indicates which port size is currently selected.</description>
41517 <description>Port size 19 is not selected.</description>
41522 <description>Port size 19 is selected.</description>
41529 <description>Indicates which port size is currently selected.</description>
41535 <description>Port size 20 is not selected.</description>
41540 <description>Port size 20 is selected.</description>
41547 <description>Indicates which port size is currently selected.</description>
41553 <description>Port size 21 is not selected.</description>
41558 <description>Port size 21 is selected.</description>
41565 <description>Indicates which port size is currently selected.</description>
41571 <description>Port size 22 is not selected.</description>
41576 <description>Port size 22 is selected.</description>
41583 <description>Indicates which port size is currently selected.</description>
41589 <description>Port size 23 is not selected.</description>
41594 <description>Port size 23 is selected.</description>
41601 <description>Indicates which port size is currently selected.</description>
41607 <description>Port size 24 is not selected.</description>
41612 <description>Port size 24 is selected.</description>
41619 <description>Indicates which port size is currently selected.</description>
41625 <description>Port size 25 is not selected.</description>
41630 <description>Port size 25 is selected.</description>
41637 <description>Indicates which port size is currently selected.</description>
41643 <description>Port size 26 is not selected.</description>
41648 <description>Port size 26 is selected.</description>
41655 <description>Indicates which port size is currently selected.</description>
41661 <description>Port size 27 is not selected.</description>
41666 <description>Port size 27 is selected.</description>
41673 <description>Indicates which port size is currently selected.</description>
41679 <description>Port size 28 is not selected.</description>
41684 <description>Port size 28 is selected.</description>
41691 <description>Indicates which port size is currently selected.</description>
41697 <description>Port size 29 is not selected.</description>
41702 <description>Port size 29 is selected.</description>
41709 <description>Indicates which port size is currently selected.</description>
41715 <description>Port size 30 is not selected.</description>
41720 <description>Port size 30 is selected.</description>
41727 <description>Indicates which port size is currently selected.</description>
41733 <description>Port size 31 is not selected.</description>
41738 <description>Port size 31 is selected.</description>
41745 <description>Indicates which port size is currently selected.</description>
41751 <description>Port size 32 is not selected.</description>
41756 <description>Port size 32 is selected.</description>
41765 …description>The Supported_trigger_modes register indicates the implemented trigger counter multipl…
41773 …<description>Indicates whether multiplying the trigger counter by 2^(0+1) is supported.</descripti…
41779 … <description>Multiplying the trigger counter by 2^(0+1) is supported.</description>
41784 … <description>Multiplying the trigger counter by 2^(0+1) is supported.</description>
41791 …<description>Indicates whether multiplying the trigger counter by 2^(1+1) is supported.</descripti…
41797 … <description>Multiplying the trigger counter by 2^(1+1) is supported.</description>
41802 … <description>Multiplying the trigger counter by 2^(1+1) is supported.</description>
41809 …<description>Indicates whether multiplying the trigger counter by 2^(2+1) is supported.</descripti…
41815 … <description>Multiplying the trigger counter by 2^(2+1) is supported.</description>
41820 … <description>Multiplying the trigger counter by 2^(2+1) is supported.</description>
41827 …<description>Indicates whether multiplying the trigger counter by 2^(3+1) is supported.</descripti…
41833 … <description>Multiplying the trigger counter by 2^(3+1) is supported.</description>
41838 … <description>Multiplying the trigger counter by 2^(3+1) is supported.</description>
41845 …<description>Indicates whether multiplying the trigger counter by 2^(4+1) is supported.</descripti…
41851 … <description>Multiplying the trigger counter by 2^(4+1) is supported.</description>
41856 … <description>Multiplying the trigger counter by 2^(4+1) is supported.</description>
41863 … <description>Indicates whether an 8-bit wide counter register is implemented.</description>
41869 <description>An 8-bit wide counter register is implemented.</description>
41874 <description>An 8-bit wide counter register is implemented.</description>
41881 <description>A trigger has occurred and the counter has reached 0.</description>
41887 <description>Trigger has not occurred.</description>
41892 <description>Trigger has occurred.</description>
41899 <description>A trigger has occurred but the counter is not at 0.</description>
41905 … <description>Either a trigger has not occurred or the counter is at 0.</description>
41910 <description>A trigger has occurred but the counter is not at 0.</description>
41919 …description>The Trigger_counter_value register enables delaying the indication of triggers to any …
41927 …<description>8-bit counter value for the number of words to be output from the formatter before a …
41935 …<description>The Trigger_multiplier register contains the selectors for the trigger counter multip…
41943 <description>Multiply the Trigger Counter by 2^n.</description>
41949 <description>Multiplier disabled.</description>
41954 <description>Multiplier enabled.</description>
41961 <description>Multiply the Trigger Counter by 2^n.</description>
41967 <description>Multiplier disabled.</description>
41972 <description>Multiplier enabled.</description>
41979 <description>Multiply the Trigger Counter by 2^n.</description>
41985 <description>Multiplier disabled.</description>
41990 <description>Multiplier enabled.</description>
41997 <description>Multiply the Trigger Counter by 2^n.</description>
42003 <description>Multiplier disabled.</description>
42008 <description>Multiplier enabled.</description>
42015 <description>Multiply the Trigger Counter by 2^n.</description>
42021 <description>Multiplier disabled.</description>
42026 <description>Multiplier enabled.</description>
42035 …description>The Supported_test_pattern_modes register provides a set of known bit sequences or pat…
42043 …<description>Indicates whether the walking 1s pattern is supported as output over the trace port.<…
42049 <description>Test pattern is not supported.</description>
42054 <description>Test pattern is supported.</description>
42061 …<description>Indicates whether the walking 0s pattern is supported as output over the trace port.<…
42067 <description>Test pattern is not supported.</description>
42072 <description>Test pattern is supported.</description>
42079 …<description>Indicates whether the AA/55 pattern is supported as output over the trace port.</desc…
42085 <description>Test pattern is not supported.</description>
42090 <description>Test pattern is supported.</description>
42097 …<description>Indicates whether the FF/00 pattern is supported as output over the trace port.</desc…
42103 <description>Test pattern is not supported.</description>
42108 <description>Test pattern is supported.</description>
42115 <description>Indicates whether timed mode is supported.</description>
42121 <description>Mode is not supported.</description>
42126 <description>Mode is supported.</description>
42133 <description>Indicates whether continuous mode is supported.</description>
42139 <description>Mode is not supported.</description>
42144 <description>Mode is supported.</description>
42153 …<description>Current_test_pattern_mode indicates the current test pattern or mode selected.</descr…
42161 …<description>Indicates whether the walking 1s pattern is supported as output over the trace port.<…
42167 <description>Test pattern is disabled.</description>
42172 <description>Test pattern is enabled.</description>
42179 …<description>Indicates whether the walking 0s pattern is supported as output over the trace port.<…
42185 <description>Test pattern is disabled.</description>
42190 <description>Test pattern is enabled.</description>
42197 …<description>Indicates whether the AA/55 pattern is supported as output over the trace port.</desc…
42203 <description>Test pattern is disabled.</description>
42208 <description>Test pattern is enabled.</description>
42215 …<description>Indicates whether the FF/00 pattern is supported as output over the trace port.</desc…
42221 <description>Test pattern is disabled.</description>
42226 <description>Test pattern is enabled.</description>
42233 <description>Indicates whether timed mode is supported.</description>
42239 <description>Mode is disabled.</description>
42244 <description>Mode is enabled.</description>
42251 <description>Indicates whether continuous mode is supported.</description>
42257 <description>Mode is disabled.</description>
42262 <description>Mode is enabled.</description>
42271 …description>The TPRCR register is an 8-bit counter start value that is decremented. A write sets t…
42279 …description>8-bit counter value to indicate the number of traceclkin cycles for which a pattern ru…
42287 …<description>The FFSR register indicates the current status of the formatter and flush features av…
42295 <description>Flush in progress.</description>
42301 <description>A flush is not in progress.</description>
42306 <description>A flush is in progress.</description>
42313 …description>The formatter has received a stop request signal and all trace data and post-amble is …
42319 <description>Formatter has not stopped.</description>
42324 <description>Formatter has stopped.</description>
42331 <description>Indicates whether the TRACECTL pin is available for use.</description>
42337 <description>TRACECTL pin is not present.</description>
42342 <description>TRACECTL pin is present.</description>
42351 …<description>The FFCR register controls the generation of stop, trigger, and flush events.</descri…
42359 …<description>Do not embed triggers into the formatted stream. Trace disable cycles and triggers ar…
42365 <description>The formatting feature is disabled.</description>
42370 <description>The formatting feature is enabled.</description>
42377 …<description>Is embedded in trigger packets and indicates that no cycle is using sync packets.</de…
42383 <description>The formatting feature is disabled.</description>
42388 <description>The formatting feature is enabled.</description>
42395 <description>Enables the use of the flushin connection.</description>
42401 <description>The formatting feature is disabled.</description>
42406 <description>The formatting feature is enabled.</description>
42413 …<description>Initiates a manual flush of data in the system when a trigger event occurs.</descript…
42419 <description>The formatting feature is disabled.</description>
42424 <description>The formatting feature is enabled.</description>
42431 … <description>Generates a flush. This bit is set to 0 when this flush is serviced.</description>
42437 <description>The formatting feature is disabled.</description>
42442 <description>The formatting feature is enabled.</description>
42449 … <description>Generates a flush. This bit is set to 1 when this flush is serviced.</description>
42455 <description>The formatting feature is disabled.</description>
42460 <description>The formatting feature is enabled.</description>
42467 <description>Indicates a trigger when trigin is asserted.</description>
42473 <description>The formatting feature is disabled.</description>
42478 <description>The formatting feature is enabled.</description>
42485 <description>Indicates a trigger on a trigger event.</description>
42491 <description>The formatting feature is disabled.</description>
42496 <description>The formatting feature is enabled.</description>
42503 … <description>Indicates a trigger when flush completion on afreadys is returned.</description>
42509 <description>The formatting feature is disabled.</description>
42514 <description>The formatting feature is enabled.</description>
42521 <description>Forces the FIFO to drain off any part-completed packets.</description>
42527 <description>The formatting feature is disabled.</description>
42532 <description>The formatting feature is enabled.</description>
42539 …<description>Stops the formatter after a trigger event is observed. Reset to disabled or 0.</descr…
42545 <description>The formatting feature is disabled.</description>
42550 <description>The formatting feature is enabled.</description>
42559 …description>The FSCR register enables the frequency of synchronization information to be optimized…
42567 …<description>12-bit counter reload value. Indicates the number of complete frames between full syn…
42575 …description>Two ports can be used as a control and feedback mechanism for any serializers, pin sha…
42583 <description>EXTCTL inputs.</description>
42589 <description>Input EXTCTL0 is low.</description>
42594 <description>Input EXTCTL0 is high.</description>
42601 <description>EXTCTL inputs.</description>
42607 <description>Input EXTCTL1 is low.</description>
42612 <description>Input EXTCTL1 is high.</description>
42619 <description>EXTCTL inputs.</description>
42625 <description>Input EXTCTL2 is low.</description>
42630 <description>Input EXTCTL2 is high.</description>
42637 <description>EXTCTL inputs.</description>
42643 <description>Input EXTCTL3 is low.</description>
42648 <description>Input EXTCTL3 is high.</description>
42655 <description>EXTCTL inputs.</description>
42661 <description>Input EXTCTL4 is low.</description>
42666 <description>Input EXTCTL4 is high.</description>
42673 <description>EXTCTL inputs.</description>
42679 <description>Input EXTCTL5 is low.</description>
42684 <description>Input EXTCTL5 is high.</description>
42691 <description>EXTCTL inputs.</description>
42697 <description>Input EXTCTL6 is low.</description>
42702 <description>Input EXTCTL6 is high.</description>
42709 <description>EXTCTL inputs.</description>
42715 <description>Input EXTCTL7 is low.</description>
42720 <description>Input EXTCTL7 is high.</description>
42729 …description>Two ports can be used as a control and feedback mechanism for any serializers, pin sha…
42737 <description>EXTCTL outputs.</description>
42743 <description>Output EXTCTL0 is low.</description>
42748 <description>Output EXTCTL0 is high.</description>
42755 <description>EXTCTL outputs.</description>
42761 <description>Output EXTCTL1 is low.</description>
42766 <description>Output EXTCTL1 is high.</description>
42773 <description>EXTCTL outputs.</description>
42779 <description>Output EXTCTL2 is low.</description>
42784 <description>Output EXTCTL2 is high.</description>
42791 <description>EXTCTL outputs.</description>
42797 <description>Output EXTCTL3 is low.</description>
42802 <description>Output EXTCTL3 is high.</description>
42809 <description>EXTCTL outputs.</description>
42815 <description>Output EXTCTL4 is low.</description>
42820 <description>Output EXTCTL4 is high.</description>
42827 <description>EXTCTL outputs.</description>
42833 <description>Output EXTCTL5 is low.</description>
42838 <description>Output EXTCTL5 is high.</description>
42845 <description>EXTCTL outputs.</description>
42851 <description>Output EXTCTL6 is low.</description>
42856 <description>Output EXTCTL6 is high.</description>
42863 <description>EXTCTL outputs.</description>
42869 <description>Output EXTCTL7 is low.</description>
42874 <description>Output EXTCTL7 is high.</description>
42883 …<description>The ITTRFLINACK register enables control of the triginack and flushinack outputs from…
42891 <description>Sets the value of triginack.</description>
42897 <description>Pin is logic 0.</description>
42902 <description>Pin is logic 1.</description>
42909 <description>Sets the value of flushinack.</description>
42915 <description>Pin is logic 0.</description>
42920 <description>Pin is logic 1.</description>
42929 …<description>The ITTRFLIN register contains the values of the flushin and trigin inputs to the TPI…
42937 <description>Reads the value of trigin.</description>
42943 <description>Pin is logic 0.</description>
42948 <description>Pin is logic 1.</description>
42955 <description>Reads the value of flushin.</description>
42961 <description>Pin is logic 0.</description>
42966 <description>Pin is logic 1.</description>
42975 …<description>The ITATBDATA0 register contains the value of the atdatas inputs to the TPIU. The val…
42983 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
42989 <description>Pin is logic 0.</description>
42994 <description>Pin is logic 1.</description>
43001 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
43007 <description>Pin is logic 0.</description>
43012 <description>Pin is logic 1.</description>
43019 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
43025 <description>Pin is logic 0.</description>
43030 <description>Pin is logic 1.</description>
43037 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
43043 <description>Pin is logic 0.</description>
43048 <description>Pin is logic 1.</description>
43055 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
43061 <description>Pin is logic 0.</description>
43066 <description>Pin is logic 1.</description>
43075 … <description>Enables control of the atreadys and afvalids outputs of the TPIU.</description>
43083 <description>Sets the value of afvalid.</description>
43089 <description>Pin is logic 0.</description>
43094 <description>Pin is logic 1.</description>
43101 <description>Sets the value of atready.</description>
43107 <description>Pin is logic 0.</description>
43112 <description>Pin is logic 1.</description>
43121 …<description>The ITATBCTR1 register contains the value of the atids input to the TPIU. This is onl…
43129 <description>Reads the value of atids.</description>
43135 <description>Pin is logic 0.</description>
43140 <description>Pin is logic 1.</description>
43149 …<description>The ITATBCTR0 register captures the values of the atvalids, afreadys, and atbytess in…
43150 …ctly in a system, the value of atbytess is only valid when atvalids, bit[0], is HIGH.</description>
43158 <description>Reads the value of atvalids.</description>
43164 <description>Pin is logic 0.</description>
43169 <description>Pin is logic 1.</description>
43176 <description>Reads the value of afreadys.</description>
43182 <description>Pin is logic 0.</description>
43187 <description>Pin is logic 1.</description>
43194 <description>Reads the value of atbytess.</description>
43200 <description>Pin is logic 0.</description>
43205 <description>Pin is logic 1.</description>
43214 <description>Used to enable topology detection.
43216 …he component can be directly controlled for integration testing and topology solving.</description>
43224 …description>Enables the component to switch from functional mode to integration mode and back. If …
43230 <description>Integration mode is disabled.</description>
43235 <description>Integration mode is Enabled.</description>
43244 …<description>Software can use the claim tag to coordinate application and debugger access to trace…
43245 …ster sets bits in the claim tag, and determines the number of claim bits implemented.</description>
43253 <description>Set claim bit 0 and check if bit is implemented or not.</description>
43260 <description>Claim bit 0 is not implemented.</description>
43265 <description>Claim bit 0 is implemented.</description>
43273 <description>Set claim bit 0.</description>
43280 <description>Set claim bit 1 and check if bit is implemented or not.</description>
43287 <description>Claim bit 1 is not implemented.</description>
43292 <description>Claim bit 1 is implemented.</description>
43300 <description>Set claim bit 1.</description>
43307 <description>Set claim bit 2 and check if bit is implemented or not.</description>
43314 <description>Claim bit 2 is not implemented.</description>
43319 <description>Claim bit 2 is implemented.</description>
43327 <description>Set claim bit 2.</description>
43334 <description>Set claim bit 3 and check if bit is implemented or not.</description>
43341 <description>Claim bit 3 is not implemented.</description>
43346 <description>Claim bit 3 is implemented.</description>
43354 <description>Set claim bit 3.</description>
43363 …<description>Software can use the claim tag to coordinate application and debugger access to trace…
43365 …ets the bits in the claim tag to 0 and determines the current value of the claim tag.</description>
43373 <description>Read or clear claim bit 0.</description>
43380 <description>Claim bit 0 is not set.</description>
43385 <description>Claim bit 0 is set.</description>
43393 <description>Clear claim bit 0.</description>
43400 <description>Read or clear claim bit 1.</description>
43407 <description>Claim bit 1 is not set.</description>
43412 <description>Claim bit 1 is set.</description>
43420 <description>Clear claim bit 1.</description>
43427 <description>Read or clear claim bit 2.</description>
43434 <description>Claim bit 2 is not set.</description>
43439 <description>Claim bit 2 is set.</description>
43447 <description>Clear claim bit 2.</description>
43454 <description>Read or clear claim bit 3.</description>
43461 <description>Claim bit 3 is not set.</description>
43466 <description>Claim bit 3 is set.</description>
43474 <description>Clear claim bit 3.</description>
43483 <description>This is used to enable write access to device registers.</description>
43491 …<description>A write of 0xC5ACCE55 enables further write access to this device. Any other write re…
43497 <description>Unlock register interface.</description>
43506 …<description>This indicates the status of the lock control mechanism. This lock prevents accidenta…
43510 … For most components this covers all registers except for the Lock Access Register.</description>
43518 … <description>Indicates that a lock control mechanism exists for this device.</description>
43524 …<description>No lock control mechanism exists, writes to the Lock Access Register are ignored.</de…
43529 <description>Lock control mechanism is present.</description>
43536 <description>Returns the current status of the Lock.</description>
43542 <description>Write access is allowed to this device.</description>
43547 …<description>Write access to the component is blocked. All writes to control registers are ignored…
43554 …<description>Indicates if the Lock Access Register is implemented as 8-bit or 32-bit.</description>
43560 … <description>This component implements a 32-bit Lock Access Register.</description>
43565 … <description>This component implements an 8-bit Lock Access Register.</description>
43574 <description>Indicates the current level of tracing permitted by the system</description>
43582 <description>Non-secure Invasive Debug</description>
43588 <description>The feature is not implemented.</description>
43593 <description>The feature is implemented.</description>
43600 <description>Non-secure Non-Invasive Debug</description>
43606 <description>The feature is not implemented.</description>
43611 <description>The feature is implemented.</description>
43618 <description>Secure Invasive Debug</description>
43624 <description>The feature is not implemented.</description>
43629 <description>The feature is implemented.</description>
43636 <description>Secure Non-Invasive Debug</description>
43642 <description>The feature is not implemented.</description>
43647 <description>The feature is implemented.</description>
43656 <description>Indicates the capabilities of the component.</description>
43664 …<description>Indicates the hidden level of input multiplexing. When non-zero, this value indicates…
43665 …rted, that is, no multiplexing is present. This value helps detect the ATB structure.</description>
43671 <description>Indicates the relationship between atclk and traceclkin.</description>
43677 <description>atclk and traceclkin are synchronous.</description>
43682 <description>atclk and traceclkin are asynchronous.</description>
43689 <description>FIFO size in powers of 2.</description>
43695 <description>FIFO size of 4 entries, that is, 16 bytes.</description>
43702 <description>Indicates whether trace clock plus data is supported.</description>
43708 <description>Trace clock and data is supported.</description>
43713 <description>Trace clock and data is not supported.</description>
43720 …<description>Indicates whether Serial Wire Output, Manchester encoded format, is supported.</descr…
43726 … <description>Serial Wire Output, Manchester encoded format, is not supported.</description>
43731 … <description>Serial Wire Output, Manchester encoded format, is supported.</description>
43738 … <description>Indicates whether Serial Wire Output, UART or NRZ, is supported.</description>
43744 <description>Serial Wire Output, UART or NRZ, is not supported.</description>
43749 <description>Serial Wire Output, UART or NRZ, is supported.</description>
43758 …description>The DEVTYPE register provides a debugger with information about the component when the…
43766 <description>The main type of the component</description>
43772 <description>Peripheral is a trace sink.</description>
43779 <description>The sub-type of the component</description>
43785 … <description>Indicates that this component is a trace port component.</description>
43794 <description>Coresight peripheral identification registers.</description>
43802 <description>Coresight peripheral identification registers.</description>
43810 <description>Coresight peripheral identification registers.</description>
43818 <description>Coresight peripheral identification registers.</description>
43826 <description>Coresight peripheral identification registers.</description>
43834 <description>Coresight component identification registers.</description>
43842 <description>Coresight component identification registers.</description>
43850 <description>Coresight component identification registers.</description>
43858 <description>Coresight component identification registers.</description>
43868 <description>Embedded Trace Buffer</description>
43882 <description>ETB RAM Depth Register</description>
43890 <description>Defines the depth, in words, of the trace RAM.</description>
43898 <description>ETB Status Register</description>
43906 …<description>RAM Full. The flag indicates when the RAM write pointer has wrapped around.</descript…
43912 …description>The Triggered bit is set when a trigger has been observed. This does not indicate that…
43918 …description>The acquisition complete flag indicates that capture has been completed when the forma…
43924 <description>Formatter pipeline empty. All data stored to RAM.</description>
43932 <description>ETB RAM Read Data Register</description>
43940 <description>Data read from the ETB Trace RAM.</description>
43948 <description>ETB RAM Read Pointer Register</description>
43956 …<description>Sets the read pointer used to read entries from the Trace RAM over the APB interface.…
43964 <description>ETB RAM Write Pointer Register</description>
43972 …<description>Sets the write pointer used to write entries from the CoreSight bus into the Trace RA…
43980 <description>ETB Trigger Counter Register</description>
43988 …description>The counter is used as follows:Trace after - The counter is set to a large value, slig…
43996 <description>ETB Control Register</description>
44004 …description>ETB Trace Capture Enable. This is the master enable bit forcing FtStopped HIGH when Tr…
44012 <description>ETB RAM Write Data Register</description>
44020 …description>Data written to the ETB Trace RAM. When trace capture is disabled, the contents of thi…
44028 <description>ETB Formatter and Flush Status Register</description>
44036 …<description>Flush In Progress. This is an indication of the current state of afvalids.</descripti…
44042 …description>Formatter stopped. The formatter has received a stop request signal and all trace data…
44050 <description>ETB Formatter and Flush Control Register</description>
44058 …description>Do not embed Triggers into the formatted stream. Trace disable cycles and triggers are…
44064 …description>Continuous mode in the ETB corresponds to normal mode with the embedding of triggers. …
44070 …<description>Set this bit to enable use of the flushin connection. This is clear on reset.</descri…
44076 …description>Generate flush using Trigger event. Set this bit to cause a flush of data in the syste…
44082 …description>Setting this bit causes a flush to be generated. This is cleared when this flush has b…
44088 <description>Indicate a trigger on trigin being asserted.</description>
44094 <description>Indicate a trigger on a Trigger Event.</description>
44100 … <description>Indicates a trigger on Flush completion (afreadys being returned).</description>
44106 …description>This forces the FIFO to drain off any part-completed packets. Setting this bit enables…
44112 …<description>Stop the formatter after a Trigger Event is observed. Reset to disabled (zero).</desc…
44120 <description>Integration Test Miscellaneous Output Register 0</description>
44128 <description>Set the value of acqcomp.</description>
44134 <description>Set the value of full output port.</description>
44142 <description>Integration Test Trigger In and Flush In Acknowledge Register</description>
44150 <description>Set the value of triginack.</description>
44156 <description>Set the value of flushinack.</description>
44164 <description>Integration Test Trigger In and Flush In Register</description>
44172 <description>Read the value of trigin.</description>
44178 <description>Read the value of flushin.</description>
44186 <description>Integration Test ATB Data Register 0</description>
44194 <description>Read the value of atdatas[0].</description>
44200 <description>Read the value of atdatas[7].</description>
44206 <description>Read the value of atdatas[15].</description>
44212 <description>Read the value of atdatas[23].</description>
44218 <description>Read the value of atdatas[31].</description>
44226 <description>Integration Test ATB Control Register 2</description>
44234 <description>Set the value of atreadys.</description>
44240 <description>Set the value of afvalids.</description>
44248 <description>Integration Test ATB Control Register 1</description>
44256 <description>Read the value of atids.</description>
44264 <description>Integration Test ATB Control Register 0</description>
44272 <description>Read the value of atvalids.</description>
44278 <description>Read the value of afreadys.</description>
44284 <description>Read the value of atbytess.</description>
44292 <description>Integration Mode Control Register</description>
44300 …<description>Allows the component to switch from functional mode to integration mode or back.</des…
44308 <description>Claim Tag Set Register</description>
44316 <description>This claim tag bit is implemented</description>
44324 <description>Claim Tag Clear Register</description>
44332 … <description>The value present reflects the current setting of the Claim Tag.</description>
44340 <description>Lock Access Register</description>
44348 …description>A write of 0xC5ACCE55 enables further write access to this device. A write of any valu…
44356 <description>Lock Status Register</description>
44364 …description>Indicates that a lock control mechanism exists for this device. This bit reads as 0 wh…
44370 …description>Returns the current status of the Lock. This bit reads as 0 when read from an external…
44376 …<description>Indicates if the Lock Access Register (0xFB0) is implemented as 8-bit or 32-bit</desc…
44384 <description>Authentication Status Register</description>
44392 <description>Indicates the security level for non-secure invasive debug</description>
44398 … <description>Indicates the security level for non-secure non-invasive debug</description>
44404 <description>Indicates the security level for secure invasive debug</description>
44410 <description>Indicates the security level for secure non-invasive debug</description>
44418 <description>Device Configuration Register</description>
44426 …<description>When non-zero this value indicates the type/number of ATB multiplexing present on the…
44432 …<description>This bit returns 0 on reads indicating that the ETB RAM operates synchronously to atc…
44440 <description>Device Type Identifier Register</description>
44448 … <description>Major classification grouping for this debug/trace component</description>
44454 <description>Sub-classification within the major category</description>
44462 <description>Peripheral ID4 Register</description>
44470 …<description>JEDEC continuation code indicating the designer of the component (along with the iden…
44476 …description>This is a 4-bit value that indicates the total contiguous size of the memory window us…
44484 <description>Peripheral ID0 Register</description>
44492 …<description>Bits [7:0] of the component's part number. This is selected by the designer of the co…
44500 <description>Peripheral ID1 Register</description>
44508 …<description>Bits [11:8] of the component's part number. This is selected by the designer of the c…
44514 …<description>Bits 3:0 of the JEDEC identity code indicating the designer of the component (along w…
44522 <description>Peripheral ID2 Register</description>
44530 …<description>Bits 6:4 of the JEDEC identity code indicating the designer of the component (along w…
44536 <description>Always set. Indicates that a JEDEC assigned value is used</description>
44542 …description>The Revision field is an incremental value starting at 0x0 for the first design of thi…
44550 <description>Peripheral ID3 Register</description>
44558 …description>Where the component is reusable IP, this value indicates if the customer has modified …
44564 …description>This field indicates minor errata fixes specific to this design, for example metal fix…
44572 <description>Component ID0 Register</description>
44580 <description>Contains bits [7:0] of the component identification</description>
44588 <description>Component ID1 Register</description>
44596 <description>Contains bits [11:8] of the component identification</description>
44602 …<description>Class of the component. E. g. ROM table, CoreSight component etc. Constitutes bits [1…
44610 <description>Component ID2 Register</description>
44618 <description>Contains bits [23:16] of the component identification</description>
44626 <description>Component ID3 Register</description>
44634 <description>Contains bits [31:24] of the component identification</description>
44644 <description>Cross-Trigger Interface control 0</description>
44659 <description>CTI Control register</description>
44667 <description>Enables or disables the CTI.</description>
44673 … <description>All cross-triggering mapping logic functionality is disabled.</description>
44678 … <description>Cross-triggering mapping logic functionality is enabled.</description>
44687 <description>CTI Interrupt Acknowledge register</description>
44695 <description>Acknowledges the ctitrigout 0 output.</description>
44702 <description>Clears the ctitrigout.</description>
44709 <description>Acknowledges the ctitrigout 1 output.</description>
44716 <description>Clears the ctitrigout.</description>
44723 <description>Acknowledges the ctitrigout 2 output.</description>
44730 <description>Clears the ctitrigout.</description>
44737 <description>Acknowledges the ctitrigout 3 output.</description>
44744 <description>Clears the ctitrigout.</description>
44751 <description>Acknowledges the ctitrigout 4 output.</description>
44758 <description>Clears the ctitrigout.</description>
44765 <description>Acknowledges the ctitrigout 5 output.</description>
44772 <description>Clears the ctitrigout.</description>
44779 <description>Acknowledges the ctitrigout 6 output.</description>
44786 <description>Clears the ctitrigout.</description>
44793 <description>Acknowledges the ctitrigout 7 output.</description>
44800 <description>Clears the ctitrigout.</description>
44809 <description>CTI Application Trigger Set register</description>
44817 <description>Application trigger event for channel 0.</description>
44824 <description>Application trigger 0 is inactive.</description>
44829 <description>Application trigger 0 is active.</description>
44837 <description>Generate channel event for channel 0.</description>
44844 <description>Application trigger event for channel 1.</description>
44851 <description>Application trigger 1 is inactive.</description>
44856 <description>Application trigger 1 is active.</description>
44864 <description>Generate channel event for channel 1.</description>
44871 <description>Application trigger event for channel 2.</description>
44878 <description>Application trigger 2 is inactive.</description>
44883 <description>Application trigger 2 is active.</description>
44891 <description>Generate channel event for channel 2.</description>
44898 <description>Application trigger event for channel 3.</description>
44905 <description>Application trigger 3 is inactive.</description>
44910 <description>Application trigger 3 is active.</description>
44918 <description>Generate channel event for channel 3.</description>
44927 <description>CTI Application Trigger Clear register</description>
44935 …<description>Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register f…
44942 <description>Clears the event for channel 0.</description>
44949 …<description>Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register f…
44956 <description>Clears the event for channel 1.</description>
44963 …<description>Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register f…
44970 <description>Clears the event for channel 2.</description>
44977 …<description>Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register f…
44984 <description>Clears the event for channel 3.</description>
44993 <description>CTI Application Pulse register</description>
45001 …description>Setting a bit HIGH generates a channel event pulse for the selected channel. There is …
45008 <description>Generates an event pulse on channel 0.</description>
45015 …description>Setting a bit HIGH generates a channel event pulse for the selected channel. There is …
45022 <description>Generates an event pulse on channel 1.</description>
45029 …description>Setting a bit HIGH generates a channel event pulse for the selected channel. There is …
45036 <description>Generates an event pulse on channel 2.</description>
45043 …description>Setting a bit HIGH generates a channel event pulse for the selected channel. There is …
45050 <description>Generates an event pulse on channel 3.</description>
45061 <description>Description collection: CTI Trigger to Channel Enable register</description>
45069 …<description>Enables a cross trigger event to channel 0 when a ctitrigin input is activated.</desc…
45075 <description>Input trigger n events are ignored by channel 0.</description>
45080 …<description>When an event is received on input trigger n (ctitrigin[n]), generate an event on cha…
45087 …<description>Enables a cross trigger event to channel 1 when a ctitrigin input is activated.</desc…
45093 <description>Input trigger n events are ignored by channel 1.</description>
45098 …<description>When an event is received on input trigger n (ctitrigin[n]), generate an event on cha…
45105 …<description>Enables a cross trigger event to channel 2 when a ctitrigin input is activated.</desc…
45111 <description>Input trigger n events are ignored by channel 2.</description>
45116 …<description>When an event is received on input trigger n (ctitrigin[n]), generate an event on cha…
45123 …<description>Enables a cross trigger event to channel 3 when a ctitrigin input is activated.</desc…
45129 <description>Input trigger n events are ignored by channel 3.</description>
45134 …<description>When an event is received on input trigger n (ctitrigin[n]), generate an event on cha…
45145 <description>Description collection: CTI Channel to Trigger Enable register</description>
45153 …<description>Enables a cross trigger event to ctitrigout when channel 0 is activated.</description>
45159 <description>Channel 0 is ignored by output trigger n.</description>
45164 …<description>When an event occurs on channel 0, generate an event on output event n (ctitrigout[n]…
45171 …<description>Enables a cross trigger event to ctitrigout when channel 1 is activated.</description>
45177 <description>Channel 1 is ignored by output trigger n.</description>
45182 …<description>When an event occurs on channel 1, generate an event on output event n (ctitrigout[n]…
45189 …<description>Enables a cross trigger event to ctitrigout when channel 2 is activated.</description>
45195 <description>Channel 2 is ignored by output trigger n.</description>
45200 …<description>When an event occurs on channel 2, generate an event on output event n (ctitrigout[n]…
45207 …<description>Enables a cross trigger event to ctitrigout when channel 3 is activated.</description>
45213 <description>Channel 3 is ignored by output trigger n.</description>
45218 …<description>When an event occurs on channel 3, generate an event on output event n (ctitrigout[n]…
45227 <description>CTI Trigger In Status register</description>
45235 <description>Shows the status of ctitrigin0 input.</description>
45241 <description>Ctitrigin 0 is active.</description>
45246 <description>Ctitrigin 0 is inactive.</description>
45253 <description>Shows the status of ctitrigin1 input.</description>
45259 <description>Ctitrigin 1 is active.</description>
45264 <description>Ctitrigin 1 is inactive.</description>
45271 <description>Shows the status of ctitrigin2 input.</description>
45277 <description>Ctitrigin 2 is active.</description>
45282 <description>Ctitrigin 2 is inactive.</description>
45289 <description>Shows the status of ctitrigin3 input.</description>
45295 <description>Ctitrigin 3 is active.</description>
45300 <description>Ctitrigin 3 is inactive.</description>
45307 <description>Shows the status of ctitrigin4 input.</description>
45313 <description>Ctitrigin 4 is active.</description>
45318 <description>Ctitrigin 4 is inactive.</description>
45325 <description>Shows the status of ctitrigin5 input.</description>
45331 <description>Ctitrigin 5 is active.</description>
45336 <description>Ctitrigin 5 is inactive.</description>
45343 <description>Shows the status of ctitrigin6 input.</description>
45349 <description>Ctitrigin 6 is active.</description>
45354 <description>Ctitrigin 6 is inactive.</description>
45361 <description>Shows the status of ctitrigin7 input.</description>
45367 <description>Ctitrigin 7 is active.</description>
45372 <description>Ctitrigin 7 is inactive.</description>
45381 <description>CTI Trigger Out Status register</description>
45389 <description>Shows the status of ctitrigout0 output.</description>
45395 <description>Ctitrigout 0 is active.</description>
45400 <description>Ctitrigout 0 is inactive.</description>
45407 <description>Shows the status of ctitrigout1 output.</description>
45413 <description>Ctitrigout 1 is active.</description>
45418 <description>Ctitrigout 1 is inactive.</description>
45425 <description>Shows the status of ctitrigout2 output.</description>
45431 <description>Ctitrigout 2 is active.</description>
45436 <description>Ctitrigout 2 is inactive.</description>
45443 <description>Shows the status of ctitrigout3 output.</description>
45449 <description>Ctitrigout 3 is active.</description>
45454 <description>Ctitrigout 3 is inactive.</description>
45461 <description>Shows the status of ctitrigout4 output.</description>
45467 <description>Ctitrigout 4 is active.</description>
45472 <description>Ctitrigout 4 is inactive.</description>
45479 <description>Shows the status of ctitrigout5 output.</description>
45485 <description>Ctitrigout 5 is active.</description>
45490 <description>Ctitrigout 5 is inactive.</description>
45497 <description>Shows the status of ctitrigout6 output.</description>
45503 <description>Ctitrigout 6 is active.</description>
45508 <description>Ctitrigout 6 is inactive.</description>
45515 <description>Shows the status of ctitrigout7 output.</description>
45521 <description>Ctitrigout 7 is active.</description>
45526 <description>Ctitrigout 7 is inactive.</description>
45535 <description>CTI Channel In Status register</description>
45543 <description>Shows the status of the ctitrigin 0 input.</description>
45549 <description>Ctichin 0 is active.</description>
45554 <description>Ctichin 0 is inactive.</description>
45561 <description>Shows the status of the ctitrigin 1 input.</description>
45567 <description>Ctichin 1 is active.</description>
45572 <description>Ctichin 1 is inactive.</description>
45579 <description>Shows the status of the ctitrigin 2 input.</description>
45585 <description>Ctichin 2 is active.</description>
45590 <description>Ctichin 2 is inactive.</description>
45597 <description>Shows the status of the ctitrigin 3 input.</description>
45603 <description>Ctichin 3 is active.</description>
45608 <description>Ctichin 3 is inactive.</description>
45617 <description>Enable CTI Channel Gate register</description>
45625 <description>Enable ctichout0.</description>
45631 <description>Enable ctichout channel 0 propagation.</description>
45636 <description>Disable ctichout channel 0 propagation.</description>
45643 <description>Enable ctichout1.</description>
45649 <description>Enable ctichout channel 1 propagation.</description>
45654 <description>Disable ctichout channel 1 propagation.</description>
45661 <description>Enable ctichout2.</description>
45667 <description>Enable ctichout channel 2 propagation.</description>
45672 <description>Disable ctichout channel 2 propagation.</description>
45679 <description>Enable ctichout3.</description>
45685 <description>Enable ctichout channel 3 propagation.</description>
45690 <description>Disable ctichout channel 3 propagation.</description>
45699 <description>Device Architecture register</description>
45707 <description>Contains the CTI device architecture.</description>
45715 <description>Device Configuration register</description>
45723 …<description>Indicates the number of multiplexers available on Trigger Inputs and Trigger Outputs …
45724 … The default value of 0b00000 indicates that no multiplexing is present.</description>
45730 <description>Number of ECT triggers available.</description>
45736 <description>Number of ECT channels available.</description>
45744 <description>Device Type Identifier register</description>
45752 …<description>Major classification of the type of the debug component as specified in the Arm Archi…
45753 debug and trace component.</description>
45759 …<description>Indicates that this component allows a debugger to control other components in an Arm…
45766 …<description>Sub-classification of the type of the debug component as specified in the Arm Archite…
45767 the major classification as specified in the MAJOR field.</description>
45773 … <description>Indicates that this component is a sub-triggering component.</description>
45782 <description>Peripheral ID4 Register</description>
45790 …<description>Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the comp…
45796 <description>JEDEC continuation code.</description>
45803 … <description>Always 0b0000. Indicates that the device only occupies 4KB of memory.</description>
45811 <description>Peripheral ID5 register</description>
45819 <description>Peripheral ID6 register</description>
45827 <description>Peripheral ID7 register</description>
45835 <description>Peripheral ID0 Register</description>
45843 …<description>Bits[7:0] of the 12-bit part number of the component. The designer of the component a…
45849 … <description>Indicates bits[7:0] of the part number of the component.</description>
45858 <description>Peripheral ID1 Register</description>
45866 …<description>Bits[11:8] of the 12-bit part number of the component. The designer of the component …
45872 … <description>Indicates bits[11:8] of the part number of the component.</description>
45879 …<description>Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the comp…
45885 <description>Arm. Bits[3:0] of the JEDEC JEP106 Identity Code</description>
45894 <description>Peripheral ID2 Register</description>
45902 …<description>Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the comp…
45908 <description>Arm. Bits[6:4] of the JEDEC JEP106 Identity Code</description>
45915 … <description>Always 1. Indicates that the JEDEC-assigned designer ID is used.</description>
45921 <description>Peripheral revision</description>
45927 <description>This device is at r0p0</description>
45936 <description>Peripheral ID3 Register</description>
45944 …<description>Customer Modified. Indicates whether the customer has modified the behavior of the co…
45945 …ustomers change this value when they make authorized modifications to this component.</description>
45951 … <description>Indicates that the customer has not modified this component.</description>
45958 …<description>Indicates minor errata fixes specific to the revision of the component being used, fo…
45960 …is field if required, for example, by driving it from registers that reset to 0b0000.</description>
45966 … <description>Indicates that there are no errata fixes to this component.</description>
45975 <description>Component ID0 Register</description>
45983 … <description>Preamble[0]. Contains bits[7:0] of the component identification code.</description>
45989 <description>Bits[7:0] of the identification code.</description>
45998 <description>Component ID1 Register</description>
46006 … <description>Preamble[1]. Contains bits[11:8] of the component identification code.</description>
46012 <description>Bits[11:8] of the identification code.</description>
46019 …<description>Class of the component, for example, whether the component is a ROM table or a generi…
46020 Contains bits[15:12] of the component identification code</description>
46026 <description>Indicates that the component is a CoreSight component.</description>
46035 <description>Component ID2 Register</description>
46043 … <description>Preamble[2]. Contains bits[23:16] of the component identification code.</description>
46049 <description>Bits[23:16] of the identification code.</description>
46058 <description>Component ID3 Register</description>
46066 … <description>Preamble[3]. Contains bits[31:24] of the component identification code.</description>
46072 <description>Bits[31:24] of the identification code.</description>
46083 <description>Cross-Trigger Interface control 1</description>
46090 <description>ATB Replicator module 0</description>
46105 …<description>The IDFILTER0 register enables the programming of ID filtering for master port 0.</de…
46113 <description>Enable or disable ID filtering for IDs 0x00_0x0F.</description>
46119 … <description>Transactions with these IDs are passed on to ATB master port 0.</description>
46124 … <description>Transactions with these IDs are discarded by the replicator.</description>
46131 <description>Enable or disable ID filtering for IDs 0x10_0x1F.</description>
46137 … <description>Transactions with these IDs are passed on to ATB master port 0.</description>
46142 … <description>Transactions with these IDs are discarded by the replicator.</description>
46149 <description>Enable or disable ID filtering for IDs 0x20_0x2F.</description>
46155 … <description>Transactions with these IDs are passed on to ATB master port 0.</description>
46160 … <description>Transactions with these IDs are discarded by the replicator.</description>
46167 <description>Enable or disable ID filtering for IDs 0x30_0x3F.</description>
46173 … <description>Transactions with these IDs are passed on to ATB master port 0.</description>
46178 … <description>Transactions with these IDs are discarded by the replicator.</description>
46185 <description>Enable or disable ID filtering for IDs 0x40_0x4F.</description>
46191 … <description>Transactions with these IDs are passed on to ATB master port 0.</description>
46196 … <description>Transactions with these IDs are discarded by the replicator.</description>
46203 <description>Enable or disable ID filtering for IDs 0x50_0x5F.</description>
46209 … <description>Transactions with these IDs are passed on to ATB master port 0.</description>
46214 … <description>Transactions with these IDs are discarded by the replicator.</description>
46221 <description>Enable or disable ID filtering for IDs 0x60_0x6F.</description>
46227 … <description>Transactions with these IDs are passed on to ATB master port 0.</description>
46232 … <description>Transactions with these IDs are discarded by the replicator.</description>
46239 <description>Enable or disable ID filtering for IDs 0x70_0x7F.</description>
46245 … <description>Transactions with these IDs are passed on to ATB master port 0.</description>
46250 … <description>Transactions with these IDs are discarded by the replicator.</description>
46259 …<description>The IDFILTER1 register enables the programming of ID filtering for master port 1.</de…
46267 <description>Enable or disable ID filtering for IDs 0x00_0x0F.</description>
46273 … <description>Transactions with these IDs are passed on to ATB master port 1.</description>
46278 … <description>Transactions with these IDs are discarded by the replicator.</description>
46285 <description>Enable or disable ID filtering for IDs 0x10_0x1F.</description>
46291 … <description>Transactions with these IDs are passed on to ATB master port 1.</description>
46296 … <description>Transactions with these IDs are discarded by the replicator.</description>
46303 <description>Enable or disable ID filtering for IDs 0x20_0x2F.</description>
46309 … <description>Transactions with these IDs are passed on to ATB master port 1.</description>
46314 … <description>Transactions with these IDs are discarded by the replicator.</description>
46321 <description>Enable or disable ID filtering for IDs 0x30_0x3F.</description>
46327 … <description>Transactions with these IDs are passed on to ATB master port 1.</description>
46332 … <description>Transactions with these IDs are discarded by the replicator.</description>
46339 <description>Enable or disable ID filtering for IDs 0x40_0x4F.</description>
46345 … <description>Transactions with these IDs are passed on to ATB master port 1.</description>
46350 … <description>Transactions with these IDs are discarded by the replicator.</description>
46357 <description>Enable or disable ID filtering for IDs 0x50_0x5F.</description>
46363 … <description>Transactions with these IDs are passed on to ATB master port 1.</description>
46368 … <description>Transactions with these IDs are discarded by the replicator.</description>
46375 <description>Enable or disable ID filtering for IDs 0x60_0x6F.</description>
46381 … <description>Transactions with these IDs are passed on to ATB master port 1.</description>
46386 … <description>Transactions with these IDs are discarded by the replicator.</description>
46393 <description>Enable or disable ID filtering for IDs 0x70_0x7F.</description>
46399 … <description>Transactions with these IDs are passed on to ATB master port 1.</description>
46404 … <description>Transactions with these IDs are discarded by the replicator.</description>
46413 …<description>The ITATBCTR1 register returns the value of the atreadym0, atreadym1, and atvalids in…
46421 <description>Reads the value of the atreadym0 input.</description>
46427 <description>Pin is logic 0.</description>
46432 <description>Pin is logic 1.</description>
46439 <description>Reads the value of the atreadym1 input.</description>
46445 <description>Pin is logic 0.</description>
46450 <description>Pin is logic 1.</description>
46457 <description>Reads the value of the atvalids input.</description>
46463 <description>Pin is logic 0.</description>
46468 <description>Pin is logic 1.</description>
46477 …<description>The ITATBCTR0 register controls the value of the atvalidm0, atvalidm1, and atreadys o…
46485 <description>Sets the value of the atvalidm0 output.</description>
46491 <description>Pin is logic 0.</description>
46496 <description>Pin is logic 1.</description>
46503 <description>Sets the value of the atvalidm1 output.</description>
46509 <description>Pin is logic 0.</description>
46514 <description>Pin is logic 1.</description>
46521 <description>Sets the value of the atreadys output.</description>
46527 <description>Pin is logic 0.</description>
46532 <description>Pin is logic 1.</description>
46541 …<description>The ITCTRL register enables the component to switch from a functional mode, which is …
46542 …e directly controlled for the purposes of integration testing and topology detection.</description>
46550 <description>Integration Mode Enable.</description>
46556 <description>Integration mode disabled.</description>
46561 <description>Integration mode enabled.</description>
46570 …<description>Software can use the claim tag to coordinate application and debugger access to trace…
46571 …ster sets bits in the claim tag, and determines the number of claim bits implemented.</description>
46579 <description>Set claim bit 0 and check if bit is implemented or not.</description>
46586 <description>Claim bit 0 is not implemented.</description>
46591 <description>Claim bit 0 is implemented.</description>
46599 <description>Set claim bit 0.</description>
46606 <description>Set claim bit 1 and check if bit is implemented or not.</description>
46613 <description>Claim bit 1 is not implemented.</description>
46618 <description>Claim bit 1 is implemented.</description>
46626 <description>Set claim bit 1.</description>
46633 <description>Set claim bit 2 and check if bit is implemented or not.</description>
46640 <description>Claim bit 2 is not implemented.</description>
46645 <description>Claim bit 2 is implemented.</description>
46653 <description>Set claim bit 2.</description>
46660 <description>Set claim bit 3 and check if bit is implemented or not.</description>
46667 <description>Claim bit 3 is not implemented.</description>
46672 <description>Claim bit 3 is implemented.</description>
46680 <description>Set claim bit 3.</description>
46689 …<description>Software can use the claim tag to coordinate application and debugger access to trace…
46691 …ets the bits in the claim tag to 0 and determines the current value of the claim tag.</description>
46699 <description>Read or clear claim bit 0.</description>
46706 <description>Claim bit 0 is not set.</description>
46711 <description>Claim bit 0 is set.</description>
46719 <description>Clear claim bit 0.</description>
46726 <description>Read or clear claim bit 1.</description>
46733 <description>Claim bit 1 is not set.</description>
46738 <description>Claim bit 1 is set.</description>
46746 <description>Clear claim bit 1.</description>
46753 <description>Read or clear claim bit 2.</description>
46760 <description>Claim bit 2 is not set.</description>
46765 <description>Claim bit 2 is set.</description>
46773 <description>Clear claim bit 2.</description>
46780 <description>Read or clear claim bit 3.</description>
46787 <description>Claim bit 3 is not set.</description>
46792 <description>Claim bit 3 is set.</description>
46800 <description>Clear claim bit 3.</description>
46809 <description>This is used to enable write access to device registers.</description>
46817 …<description>A write of 0xC5ACCE55 enables further write access to this device. Any other write re…
46823 <description>Unlock register interface.</description>
46832 …<description>This indicates the status of the lock control mechanism. This lock prevents accidenta…
46836 … For most components this covers all registers except for the Lock Access Register.</description>
46844 … <description>Indicates that a lock control mechanism exists for this device.</description>
46850 …<description>No lock control mechanism exists, writes to the Lock Access Register are ignored.</de…
46855 <description>Lock control mechanism is present.</description>
46862 <description>Returns the current status of the Lock.</description>
46868 <description>Write access is allowed to this device.</description>
46873 …<description>Write access to the component is blocked. All writes to control registers are ignored…
46880 …<description>Indicates if the Lock Access Register is implemented as 8-bit or 32-bit.</description>
46886 … <description>This component implements a 32-bit Lock Access Register.</description>
46891 … <description>This component implements an 8-bit Lock Access Register.</description>
46900 <description>Indicates the current level of tracing permitted by the system</description>
46908 <description>Non-secure Invasive Debug</description>
46914 <description>The feature is not implemented.</description>
46919 <description>The feature is implemented.</description>
46926 <description>Non-secure Non-Invasive Debug</description>
46932 <description>The feature is not implemented.</description>
46937 <description>The feature is implemented.</description>
46944 <description>Secure Invasive Debug</description>
46950 <description>The feature is not implemented.</description>
46955 <description>The feature is implemented.</description>
46962 <description>Secure Non-Invasive Debug</description>
46968 <description>The feature is not implemented.</description>
46973 <description>The feature is implemented.</description>
46982 <description>Indicates the capabilities of the component.</description>
46990 <description>Indicates the number of master ports implemented.</description>
46998 …description>The DEVTYPE register provides a debugger with information about the component when the…
47006 <description>The main type of the component</description>
47012 … <description>Indicates that this component has ATB inputs and outputs.</description>
47019 <description>The sub-type of the component</description>
47025 …<description>Indicates that this component replicates trace from a single source to multiple targe…
47034 <description>Coresight peripheral identification registers.</description>
47042 <description>Coresight peripheral identification registers.</description>
47050 <description>Coresight peripheral identification registers.</description>
47058 <description>Coresight peripheral identification registers.</description>
47066 <description>Coresight peripheral identification registers.</description>
47074 <description>Coresight component identification registers.</description>
47082 <description>Coresight component identification registers.</description>
47090 <description>Coresight component identification registers.</description>
47098 <description>Coresight component identification registers.</description>
47108 <description>ATB Replicator module 1</description>
47115 <description>ATB Replicator module 2</description>
47122 <description>ATB Replicator module 3</description>
47129 <description>ATB funnel module 0</description>
47144 …<description>The IDFILTER0 register enables the programming of ID filtering for master port 0.</de…
47152 <description>Enable slave port 0.</description>
47158 …<description>Slave port disabled. This excludes the port from the priority selection scheme.</desc…
47163 <description>Slave port enabled.</description>
47170 <description>Enable slave port 1.</description>
47176 …<description>Slave port disabled. This excludes the port from the priority selection scheme.</desc…
47181 <description>Slave port enabled.</description>
47188 <description>Enable slave port 2.</description>
47194 …<description>Slave port disabled. This excludes the port from the priority selection scheme.</desc…
47199 <description>Slave port enabled.</description>
47206 <description>Enable slave port 3.</description>
47212 …<description>Slave port disabled. This excludes the port from the priority selection scheme.</desc…
47217 <description>Slave port enabled.</description>
47224 <description>Enable slave port 4.</description>
47230 …<description>Slave port disabled. This excludes the port from the priority selection scheme.</desc…
47235 <description>Slave port enabled.</description>
47242 <description>Enable slave port 5.</description>
47248 …<description>Slave port disabled. This excludes the port from the priority selection scheme.</desc…
47253 <description>Slave port enabled.</description>
47260 <description>Enable slave port 6.</description>
47266 …<description>Slave port disabled. This excludes the port from the priority selection scheme.</desc…
47271 <description>Slave port enabled.</description>
47278 <description>Enable slave port 7.</description>
47284 …<description>Slave port disabled. This excludes the port from the priority selection scheme.</desc…
47289 <description>Slave port enabled.</description>
47296 …<description>Hold Time. The formatting scheme can become inefficient when fast switching occurs, a…
47299 …hat can be entered is 0b1110 and this equates to 15 transactions. 0b1111 is reserved.</description>
47307 …description>The Priority_Ctrl_Reg register defines the order in which inputs are selected. Each 3-…
47315 <description>Priority value of port number 0.</description>
47321 <description>Priority value of port number 1.</description>
47327 <description>Priority value of port number 2.</description>
47333 <description>Priority value of port number 3.</description>
47339 <description>Priority value of port number 4.</description>
47345 <description>Priority value of port number 5.</description>
47351 <description>Priority value of port number 6.</description>
47357 <description>Priority value of port number 7.</description>
47365 …<description>The ITATBDATA0 register performs different functions depending on whether the access …
47373 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47379 <description>Pin is logic 0.</description>
47384 <description>Pin is logic 1.</description>
47391 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47397 <description>Pin is logic 0.</description>
47402 <description>Pin is logic 1.</description>
47409 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47415 <description>Pin is logic 0.</description>
47420 <description>Pin is logic 1.</description>
47427 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47433 <description>Pin is logic 0.</description>
47438 <description>Pin is logic 1.</description>
47445 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47451 <description>Pin is logic 0.</description>
47456 <description>Pin is logic 1.</description>
47463 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47469 <description>Pin is logic 0.</description>
47474 <description>Pin is logic 1.</description>
47481 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47487 <description>Pin is logic 0.</description>
47492 <description>Pin is logic 1.</description>
47499 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47505 <description>Pin is logic 0.</description>
47510 <description>Pin is logic 1.</description>
47517 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47523 <description>Pin is logic 0.</description>
47528 <description>Pin is logic 1.</description>
47535 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47541 <description>Pin is logic 0.</description>
47546 <description>Pin is logic 1.</description>
47553 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47559 <description>Pin is logic 0.</description>
47564 <description>Pin is logic 1.</description>
47571 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47577 <description>Pin is logic 0.</description>
47582 <description>Pin is logic 1.</description>
47589 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47595 <description>Pin is logic 0.</description>
47600 <description>Pin is logic 1.</description>
47607 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47613 <description>Pin is logic 0.</description>
47618 <description>Pin is logic 1.</description>
47625 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47631 <description>Pin is logic 0.</description>
47636 <description>Pin is logic 1.</description>
47643 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47649 <description>Pin is logic 0.</description>
47654 <description>Pin is logic 1.</description>
47661 …description>A read access returns the value of a pin on atdatas_x of the enabled port. A write acc…
47667 <description>Pin is logic 0.</description>
47672 <description>Pin is logic 1.</description>
47681 …<description>The ITATBCTR2 register performs different functions depending on whether the access i…
47689 <description>A read access returns the value of atreadym.
47690 …s outputs the data to afvalids[n], where the value of the CTRLREG at 0x000 defines n.</description>
47696 <description>Pin is logic 0.</description>
47701 <description>Pin is logic 1.</description>
47708 <description>A read access returns the value of afvalidm.
47709 …s outputs the data to atreadys[n], where the value of the CTRLREG at 0x000 defines n.</description>
47715 <description>Pin is logic 0.</description>
47720 <description>Pin is logic 1.</description>
47729 …<description>The ITATBCTR1 register performs different functions depending on whether the access i…
47737 …<description>A read returns the value of the atids[n] signals, where the value of the Control Regi…
47738 A write outputs the value to the atidm port.</description>
47744 <description>Pin is logic 0.</description>
47749 <description>Pin is logic 1.</description>
47758 …<description>The ITATBCTR0 register performs different functions depending on whether the access i…
47766 …<description>A read returns the value of the atvalids[n] signal, where the value of the CTRLREG at…
47767 A write outputs the value to atvalidm.</description>
47773 <description>Pin is logic 0.</description>
47778 <description>Pin is logic 1.</description>
47785 …<description>A read returns the value of the afreadys[n] signal, where the value of the Ctrl_Reg a…
47786 A write outputs the value to afreadym.</description>
47792 <description>Pin is logic 0.</description>
47797 <description>Pin is logic 1.</description>
47804 …<description>A read returns the value of the atbytess[n] signal, where the value of the Ctrl_Reg a…
47805 A write outputs the value to atbytesm.</description>
47811 <description>Pin is logic 0.</description>
47816 <description>Pin is logic 1.</description>
47825 …<description>The ITCTRL register enables the component to switch from a functional mode, which is …
47826 …e directly controlled for the purposes of integration testing and topology detection.</description>
47834 <description>Integration Mode Enable.</description>
47840 <description>Integration mode disabled.</description>
47845 <description>Integration mode enabled.</description>
47854 …<description>Software can use the claim tag to coordinate application and debugger access to trace…
47855 …ster sets bits in the claim tag, and determines the number of claim bits implemented.</description>
47863 <description>Set claim bit 0 and check if bit is implemented or not.</description>
47870 <description>Claim bit 0 is not implemented.</description>
47875 <description>Claim bit 0 is implemented.</description>
47883 <description>Set claim bit 0.</description>
47890 <description>Set claim bit 1 and check if bit is implemented or not.</description>
47897 <description>Claim bit 1 is not implemented.</description>
47902 <description>Claim bit 1 is implemented.</description>
47910 <description>Set claim bit 1.</description>
47917 <description>Set claim bit 2 and check if bit is implemented or not.</description>
47924 <description>Claim bit 2 is not implemented.</description>
47929 <description>Claim bit 2 is implemented.</description>
47937 <description>Set claim bit 2.</description>
47944 <description>Set claim bit 3 and check if bit is implemented or not.</description>
47951 <description>Claim bit 3 is not implemented.</description>
47956 <description>Claim bit 3 is implemented.</description>
47964 <description>Set claim bit 3.</description>
47973 …<description>Software can use the claim tag to coordinate application and debugger access to trace…
47975 …ets the bits in the claim tag to 0 and determines the current value of the claim tag.</description>
47983 <description>Read or clear claim bit 0.</description>
47990 <description>Claim bit 0 is not set.</description>
47995 <description>Claim bit 0 is set.</description>
48003 <description>Clear claim bit 0.</description>
48010 <description>Read or clear claim bit 1.</description>
48017 <description>Claim bit 1 is not set.</description>
48022 <description>Claim bit 1 is set.</description>
48030 <description>Clear claim bit 1.</description>
48037 <description>Read or clear claim bit 2.</description>
48044 <description>Claim bit 2 is not set.</description>
48049 <description>Claim bit 2 is set.</description>
48057 <description>Clear claim bit 2.</description>
48064 <description>Read or clear claim bit 3.</description>
48071 <description>Claim bit 3 is not set.</description>
48076 <description>Claim bit 3 is set.</description>
48084 <description>Clear claim bit 3.</description>
48093 <description>This is used to enable write access to device registers.</description>
48101 …<description>A write of 0xC5ACCE55 enables further write access to this device. Any other write re…
48107 <description>Unlock register interface.</description>
48116 …<description>This indicates the status of the lock control mechanism. This lock prevents accidenta…
48120 … For most components this covers all registers except for the Lock Access Register.</description>
48128 … <description>Indicates that a lock control mechanism exists for this device.</description>
48134 …<description>No lock control mechanism exists, writes to the Lock Access Register are ignored.</de…
48139 <description>Lock control mechanism is present.</description>
48146 <description>Returns the current status of the Lock.</description>
48152 <description>Write access is allowed to this device.</description>
48157 …<description>Write access to the component is blocked. All writes to control registers are ignored…
48164 …<description>Indicates if the Lock Access Register is implemented as 8-bit or 32-bit.</description>
48170 … <description>This component implements a 32-bit Lock Access Register.</description>
48175 … <description>This component implements an 8-bit Lock Access Register.</description>
48184 <description>Indicates the current level of tracing permitted by the system</description>
48192 <description>Non-secure Invasive Debug</description>
48198 <description>The feature is not implemented.</description>
48203 <description>The feature is implemented.</description>
48210 <description>Non-secure Non-Invasive Debug</description>
48216 <description>The feature is not implemented.</description>
48221 <description>The feature is implemented.</description>
48228 <description>Secure Invasive Debug</description>
48234 <description>The feature is not implemented.</description>
48239 <description>The feature is implemented.</description>
48246 <description>Secure Non-Invasive Debug</description>
48252 <description>The feature is not implemented.</description>
48257 <description>The feature is implemented.</description>
48266 <description>Indicates the capabilities of the component.</description>
48274 …<description>Indicates the number of input ports connected. 0x0 and 0x1 are illegal values.</descr…
48282 …description>The DEVTYPE register provides a debugger with information about the component when the…
48290 <description>The main type of the component</description>
48296 … <description>Indicates that this component has ATB inputs and outputs.</description>
48303 <description>The sub-type of the component</description>
48309 … <description>This component arbitrates ATB inputs mapping to ATB outputs.</description>
48318 <description>Coresight peripheral identification registers.</description>
48326 <description>Coresight peripheral identification registers.</description>
48334 <description>Coresight peripheral identification registers.</description>
48342 <description>Coresight peripheral identification registers.</description>
48350 <description>Coresight peripheral identification registers.</description>
48358 <description>Coresight component identification registers.</description>
48366 <description>Coresight component identification registers.</description>
48374 <description>Coresight component identification registers.</description>
48382 <description>Coresight component identification registers.</description>
48392 <description>ATB funnel module 1</description>
48399 <description>ATB funnel module 2</description>
48406 <description>ATB funnel module 3</description>
48413 <description>Granular Power Requester</description>
48427 <description>Debug Power Request Register</description>
48435 <description>Bit 0 of the cpwrupreq output port.</description>
48441 <description>Bit 1 of the cpwrupreq output port.</description>
48447 <description>Bit 2 of the cpwrupreq output port.</description>
48453 <description>Bit 3 of the cpwrupreq output port.</description>
48459 <description>Bit 4 of the cpwrupreq output port.</description>
48465 <description>Bit 5 of the cpwrupreq output port.</description>
48471 <description>Bit 6 of the cpwrupreq output port.</description>
48477 <description>Bit 7 of the cpwrupreq output port.</description>
48483 <description>Bit 8 of the cpwrupreq output port.</description>
48491 <description>Debug Power Acknowledge Register</description>
48499 <description>Bit 0 of the cpwrupack input port.</description>
48505 <description>Bit 1 of the cpwrupack input port.</description>
48511 <description>Bit 2 of the cpwrupack input port.</description>
48517 <description>Bit 3 of the cpwrupack input port.</description>
48523 <description>Bit 4 of the cpwrupack input port.</description>
48529 <description>Bit 5 of the cpwrupack input port.</description>
48535 <description>Bit 6 of the cpwrupack input port.</description>
48541 <description>Bit 7 of the cpwrupack input port.</description>
48547 <description>Bit 8 of the cpwrupack input port.</description>
48555 <description>Integration Mode Control Register</description>
48563 …<description>When you read this register, CXGPR returns a zero because no integration functionalit…
48571 <description>Claim Tag Set Register</description>
48579 …description>On Read for each bit 1 means claim tag bit implemented. On Write for each bit 0 has no…
48587 <description>Claim Tag Clear Register</description>
48595 … <description>The value present reflects the present value of the Claim Tag.</description>
48603 <description>Lock Access Register</description>
48611 …description>When you write 0xC5ACCE55, subsequent write operations to this device are enabled. Any…
48619 <description>Lock Status Register</description>
48627 … <description>Indicates that a lock control mechanism is present in this device.</description>
48633 <description>Returns the present lock status of the device.</description>
48639 … <description>Indicates that the Lock Access Register is implemented as 32-bit.</description>
48647 <description>Authentication Status Register</description>
48655 <description>Indicates the security level for Non-Secure Invasive Debug.</description>
48661 … <description>Indicates the security level for Non-Secure Non-Invasive Debug.</description>
48667 <description>Indicates the security level for Secure Invasive Debug.</description>
48673 <description>Indicates the security level for Secure Non-Invasive Debug.</description>
48681 <description>Device Architecture Register</description>
48689 <description>Indicates the architecture of the component.</description>
48695 <description>Indicates the revision of the architecture.</description>
48701 <description>Indicates whether the DEVARCH register is present.</description>
48707 …description>Indicates the JEP106 code pf the architect who specifies the architecture of the compo…
48715 <description>Device Configuration Register</description>
48723 …description>The value present in this field indicates the number of CPWRUP master interfaces avail…
48731 <description>Device Type Identifier Register</description>
48739 …description>Major classification of the type of the debug component as specified in the CoreSight …
48745 …description>Sub-classification of the type of the debug component as specified in the CoreSight Ar…
48753 <description>Peripheral ID4 Register</description>
48761 …description>This is the JEDEC JEP106 continuation code. This code along with, bits[6:4] of the ide…
48767 …description>This is a 4-bit value that indicates the total contiguous size in powers of two of the…
48775 <description>Peripheral ID0 Register</description>
48783 …<description>Bits [7:0] of the components 12 bit part number. The designer of the component assig…
48791 <description>Peripheral ID1 Register</description>
48799 …<description>Bits[11:8] of the components 12 bit part number. The designer of the component assig…
48805 …description>Bits[3:0] of the JEDEC JEP106 identity code. This code, along with bits[6:4] of the id…
48813 <description>Peripheral ID2 Register</description>
48821 …description>Bits[6:4] of the JEDEC JEP106 identity code. This code, along with bits[3:0] of the id…
48827 … <description>Always set. Indicates if the JEDEC assigned designer ID is used.</description>
48833 …description>An incremental value starting from 0x0 for the first revision of this component. This …
48841 <description>Peripheral ID3 Register</description>
48849 …description>Indicates if the customer modified the behavior of the component. In most cases, this …
48855 …description>Indicates minor errata fixes specific to the revision of the component being used, for…
48863 <description>Component ID0 Register</description>
48871 <description>Contains bits[7:0] of the component identification code.</description>
48879 <description>Component ID1 Register</description>
48887 <description>Contains bits [11:8] of the component identification</description>
48893 …description>Class of the component, for example, if the component is a ROM table or a generic Core…
48901 <description>Component ID2 Register</description>
48909 <description>Contains bits [23:16] of the component identification</description>
48917 <description>Component ID3 Register</description>
48925 <description>Contains bits [31:24] of the component identification</description>
48935 <description>VPR CLIC registers</description>
49076 <description>Unspecified</description>
49082 <description>CLIC configuration.</description>
49090 <description>Selective interrupt hardware vectoring.</description>
49096 <description>Selective interrupt hardware vectoring is implemented</description>
49103 <description>Interrupt level encoding.</description>
49109 <description>8 bits = interrupt levels encoded in eight bits</description>
49116 <description>Interrupt privilege mode.</description>
49122 <description>All interrupts are M-mode only</description>
49131 <description>CLIC information.</description>
49139 <description>Maximum number of interrupts supported.</description>
49145 <description>Version</description>
49151 <description>Number of maximum interrupt triggers supported</description>
49161 … <description>Description collection: Interrupt control register for IRQ number [n].</description>
49169 <description>Interrupt Pending bit.</description>
49175 <description>Interrupt not pending</description>
49180 <description>Interrupt pending</description>
49187 <description>Read as 0, write ignored.</description>
49194 <description>Interrupt enable bit.</description>
49200 <description>Interrupt disabled</description>
49205 <description>Interrupt enabled</description>
49212 <description>Read as 0, write ignored.</description>
49219 <description>Selective Hardware Vectoring.</description>
49226 <description>Hardware vectored</description>
49233 <description>Trigger type and polarity for each interrupt input.</description>
49240 <description>Interrupts are edge-triggered</description>
49247 <description>Privilege mode.</description>
49254 <description>Machine mode</description>
49261 <description>Interrupt priority level</description>
49267 <description>Priority level 0</description>
49272 <description>Priority level 1</description>
49277 <description>Priority level 2</description>
49282 <description>Priority level 3</description>
49294 <description>VTIM CSR registers</description>
49310 <description>Unused.</description>
49319 <description>GPIO Tasks and Events</description>
49345 …description>Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on…
49353 …<description>Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in C…
49359 <description>Trigger task</description>
49370 …<description>Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action o…
49378 …<description>Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high.…
49384 <description>Trigger task</description>
49395 …<description>Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action o…
49403 …<description>Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low.<…
49409 <description>Trigger task</description>
49420 <description>Description collection: Subscribe configuration for task OUT[n]</description>
49428 <description>DPPI channel that task OUT[n] will subscribe to</description>
49439 <description>Disable subscription</description>
49444 <description>Enable subscription</description>
49455 <description>Description collection: Subscribe configuration for task SET[n]</description>
49463 <description>DPPI channel that task SET[n] will subscribe to</description>
49474 <description>Disable subscription</description>
49479 <description>Enable subscription</description>
49490 <description>Description collection: Subscribe configuration for task CLR[n]</description>
49498 <description>DPPI channel that task CLR[n] will subscribe to</description>
49509 <description>Disable subscription</description>
49514 <description>Enable subscription</description>
49525 … <description>Description collection: Event from pin specified in CONFIG[n].PSEL</description>
49533 <description>Event from pin specified in CONFIG[n].PSEL</description>
49539 <description>Event not generated</description>
49544 <description>Event generated</description>
49555 <description>Peripheral events.</description>
49561 <description>Description cluster: Non-secure port event from owner n</description>
49570 <description>Non-secure port event from owner n</description>
49576 <description>Event not generated</description>
49581 <description>Event generated</description>
49590 <description>Description cluster: Secure port event from owner n</description>
49599 <description>Secure port event from owner n</description>
49605 <description>Event not generated</description>
49610 <description>Event generated</description>
49622 <description>Description collection: Publish configuration for event IN[n]</description>
49630 <description>DPPI channel that event IN[n] will publish to</description>
49641 <description>Disable publishing</description>
49646 <description>Enable publishing</description>
49657 <description>Publish configuration for events</description>
49663 … <description>Description cluster: Publish configuration for event PORT[n].NONSECURE</description>
49672 <description>DPPI channel that event PORT[n].NONSECURE will publish to</description>
49683 <description>Disable publishing</description>
49688 <description>Enable publishing</description>
49697 … <description>Description cluster: Publish configuration for event PORT[n].SECURE</description>
49706 <description>DPPI channel that event PORT[n].SECURE will publish to</description>
49717 <description>Disable publishing</description>
49722 <description>Enable publishing</description>
49732 <description>Enable interrupt</description>
49740 <description>Write '1' to enable interrupt for event IN[0]</description>
49747 <description>Read: Disabled</description>
49752 <description>Read: Enabled</description>
49760 <description>Enable</description>
49767 <description>Write '1' to enable interrupt for event IN[1]</description>
49774 <description>Read: Disabled</description>
49779 <description>Read: Enabled</description>
49787 <description>Enable</description>
49794 <description>Write '1' to enable interrupt for event IN[2]</description>
49801 <description>Read: Disabled</description>
49806 <description>Read: Enabled</description>
49814 <description>Enable</description>
49821 <description>Write '1' to enable interrupt for event IN[3]</description>
49828 <description>Read: Disabled</description>
49833 <description>Read: Enabled</description>
49841 <description>Enable</description>
49848 <description>Write '1' to enable interrupt for event IN[4]</description>
49855 <description>Read: Disabled</description>
49860 <description>Read: Enabled</description>
49868 <description>Enable</description>
49875 <description>Write '1' to enable interrupt for event IN[5]</description>
49882 <description>Read: Disabled</description>
49887 <description>Read: Enabled</description>
49895 <description>Enable</description>
49902 <description>Write '1' to enable interrupt for event IN[6]</description>
49909 <description>Read: Disabled</description>
49914 <description>Read: Enabled</description>
49922 <description>Enable</description>
49929 <description>Write '1' to enable interrupt for event IN[7]</description>
49936 <description>Read: Disabled</description>
49941 <description>Read: Enabled</description>
49949 <description>Enable</description>
49956 <description>Write '1' to enable interrupt for event PORT0NONSECURE</description>
49963 <description>Read: Disabled</description>
49968 <description>Read: Enabled</description>
49976 <description>Enable</description>
49983 <description>Write '1' to enable interrupt for event PORT0SECURE</description>
49990 <description>Read: Disabled</description>
49995 <description>Read: Enabled</description>
50003 <description>Enable</description>
50010 <description>Write '1' to enable interrupt for event PORT1NONSECURE</description>
50017 <description>Read: Disabled</description>
50022 <description>Read: Enabled</description>
50030 <description>Enable</description>
50037 <description>Write '1' to enable interrupt for event PORT1SECURE</description>
50044 <description>Read: Disabled</description>
50049 <description>Read: Enabled</description>
50057 <description>Enable</description>
50064 <description>Write '1' to enable interrupt for event PORT2NONSECURE</description>
50071 <description>Read: Disabled</description>
50076 <description>Read: Enabled</description>
50084 <description>Enable</description>
50091 <description>Write '1' to enable interrupt for event PORT2SECURE</description>
50098 <description>Read: Disabled</description>
50103 <description>Read: Enabled</description>
50111 <description>Enable</description>
50118 <description>Write '1' to enable interrupt for event PORT3NONSECURE</description>
50125 <description>Read: Disabled</description>
50130 <description>Read: Enabled</description>
50138 <description>Enable</description>
50145 <description>Write '1' to enable interrupt for event PORT3SECURE</description>
50152 <description>Read: Disabled</description>
50157 <description>Read: Enabled</description>
50165 <description>Enable</description>
50174 <description>Disable interrupt</description>
50182 <description>Write '1' to disable interrupt for event IN[0]</description>
50189 <description>Read: Disabled</description>
50194 <description>Read: Enabled</description>
50202 <description>Disable</description>
50209 <description>Write '1' to disable interrupt for event IN[1]</description>
50216 <description>Read: Disabled</description>
50221 <description>Read: Enabled</description>
50229 <description>Disable</description>
50236 <description>Write '1' to disable interrupt for event IN[2]</description>
50243 <description>Read: Disabled</description>
50248 <description>Read: Enabled</description>
50256 <description>Disable</description>
50263 <description>Write '1' to disable interrupt for event IN[3]</description>
50270 <description>Read: Disabled</description>
50275 <description>Read: Enabled</description>
50283 <description>Disable</description>
50290 <description>Write '1' to disable interrupt for event IN[4]</description>
50297 <description>Read: Disabled</description>
50302 <description>Read: Enabled</description>
50310 <description>Disable</description>
50317 <description>Write '1' to disable interrupt for event IN[5]</description>
50324 <description>Read: Disabled</description>
50329 <description>Read: Enabled</description>
50337 <description>Disable</description>
50344 <description>Write '1' to disable interrupt for event IN[6]</description>
50351 <description>Read: Disabled</description>
50356 <description>Read: Enabled</description>
50364 <description>Disable</description>
50371 <description>Write '1' to disable interrupt for event IN[7]</description>
50378 <description>Read: Disabled</description>
50383 <description>Read: Enabled</description>
50391 <description>Disable</description>
50398 <description>Write '1' to disable interrupt for event PORT0NONSECURE</description>
50405 <description>Read: Disabled</description>
50410 <description>Read: Enabled</description>
50418 <description>Disable</description>
50425 <description>Write '1' to disable interrupt for event PORT0SECURE</description>
50432 <description>Read: Disabled</description>
50437 <description>Read: Enabled</description>
50445 <description>Disable</description>
50452 <description>Write '1' to disable interrupt for event PORT1NONSECURE</description>
50459 <description>Read: Disabled</description>
50464 <description>Read: Enabled</description>
50472 <description>Disable</description>
50479 <description>Write '1' to disable interrupt for event PORT1SECURE</description>
50486 <description>Read: Disabled</description>
50491 <description>Read: Enabled</description>
50499 <description>Disable</description>
50506 <description>Write '1' to disable interrupt for event PORT2NONSECURE</description>
50513 <description>Read: Disabled</description>
50518 <description>Read: Enabled</description>
50526 <description>Disable</description>
50533 <description>Write '1' to disable interrupt for event PORT2SECURE</description>
50540 <description>Read: Disabled</description>
50545 <description>Read: Enabled</description>
50553 <description>Disable</description>
50560 <description>Write '1' to disable interrupt for event PORT3NONSECURE</description>
50567 <description>Read: Disabled</description>
50572 <description>Read: Enabled</description>
50580 <description>Disable</description>
50587 <description>Write '1' to disable interrupt for event PORT3SECURE</description>
50594 <description>Read: Disabled</description>
50599 <description>Read: Enabled</description>
50607 <description>Disable</description>
50616 <description>Enable interrupt</description>
50624 <description>Write '1' to enable interrupt for event IN[0]</description>
50631 <description>Read: Disabled</description>
50636 <description>Read: Enabled</description>
50644 <description>Enable</description>
50651 <description>Write '1' to enable interrupt for event IN[1]</description>
50658 <description>Read: Disabled</description>
50663 <description>Read: Enabled</description>
50671 <description>Enable</description>
50678 <description>Write '1' to enable interrupt for event IN[2]</description>
50685 <description>Read: Disabled</description>
50690 <description>Read: Enabled</description>
50698 <description>Enable</description>
50705 <description>Write '1' to enable interrupt for event IN[3]</description>
50712 <description>Read: Disabled</description>
50717 <description>Read: Enabled</description>
50725 <description>Enable</description>
50732 <description>Write '1' to enable interrupt for event IN[4]</description>
50739 <description>Read: Disabled</description>
50744 <description>Read: Enabled</description>
50752 <description>Enable</description>
50759 <description>Write '1' to enable interrupt for event IN[5]</description>
50766 <description>Read: Disabled</description>
50771 <description>Read: Enabled</description>
50779 <description>Enable</description>
50786 <description>Write '1' to enable interrupt for event IN[6]</description>
50793 <description>Read: Disabled</description>
50798 <description>Read: Enabled</description>
50806 <description>Enable</description>
50813 <description>Write '1' to enable interrupt for event IN[7]</description>
50820 <description>Read: Disabled</description>
50825 <description>Read: Enabled</description>
50833 <description>Enable</description>
50840 <description>Write '1' to enable interrupt for event PORT0NONSECURE</description>
50847 <description>Read: Disabled</description>
50852 <description>Read: Enabled</description>
50860 <description>Enable</description>
50867 <description>Write '1' to enable interrupt for event PORT0SECURE</description>
50874 <description>Read: Disabled</description>
50879 <description>Read: Enabled</description>
50887 <description>Enable</description>
50894 <description>Write '1' to enable interrupt for event PORT1NONSECURE</description>
50901 <description>Read: Disabled</description>
50906 <description>Read: Enabled</description>
50914 <description>Enable</description>
50921 <description>Write '1' to enable interrupt for event PORT1SECURE</description>
50928 <description>Read: Disabled</description>
50933 <description>Read: Enabled</description>
50941 <description>Enable</description>
50948 <description>Write '1' to enable interrupt for event PORT2NONSECURE</description>
50955 <description>Read: Disabled</description>
50960 <description>Read: Enabled</description>
50968 <description>Enable</description>
50975 <description>Write '1' to enable interrupt for event PORT2SECURE</description>
50982 <description>Read: Disabled</description>
50987 <description>Read: Enabled</description>
50995 <description>Enable</description>
51002 <description>Write '1' to enable interrupt for event PORT3NONSECURE</description>
51009 <description>Read: Disabled</description>
51014 <description>Read: Enabled</description>
51022 <description>Enable</description>
51029 <description>Write '1' to enable interrupt for event PORT3SECURE</description>
51036 <description>Read: Disabled</description>
51041 <description>Read: Enabled</description>
51049 <description>Enable</description>
51058 <description>Disable interrupt</description>
51066 <description>Write '1' to disable interrupt for event IN[0]</description>
51073 <description>Read: Disabled</description>
51078 <description>Read: Enabled</description>
51086 <description>Disable</description>
51093 <description>Write '1' to disable interrupt for event IN[1]</description>
51100 <description>Read: Disabled</description>
51105 <description>Read: Enabled</description>
51113 <description>Disable</description>
51120 <description>Write '1' to disable interrupt for event IN[2]</description>
51127 <description>Read: Disabled</description>
51132 <description>Read: Enabled</description>
51140 <description>Disable</description>
51147 <description>Write '1' to disable interrupt for event IN[3]</description>
51154 <description>Read: Disabled</description>
51159 <description>Read: Enabled</description>
51167 <description>Disable</description>
51174 <description>Write '1' to disable interrupt for event IN[4]</description>
51181 <description>Read: Disabled</description>
51186 <description>Read: Enabled</description>
51194 <description>Disable</description>
51201 <description>Write '1' to disable interrupt for event IN[5]</description>
51208 <description>Read: Disabled</description>
51213 <description>Read: Enabled</description>
51221 <description>Disable</description>
51228 <description>Write '1' to disable interrupt for event IN[6]</description>
51235 <description>Read: Disabled</description>
51240 <description>Read: Enabled</description>
51248 <description>Disable</description>
51255 <description>Write '1' to disable interrupt for event IN[7]</description>
51262 <description>Read: Disabled</description>
51267 <description>Read: Enabled</description>
51275 <description>Disable</description>
51282 <description>Write '1' to disable interrupt for event PORT0NONSECURE</description>
51289 <description>Read: Disabled</description>
51294 <description>Read: Enabled</description>
51302 <description>Disable</description>
51309 <description>Write '1' to disable interrupt for event PORT0SECURE</description>
51316 <description>Read: Disabled</description>
51321 <description>Read: Enabled</description>
51329 <description>Disable</description>
51336 <description>Write '1' to disable interrupt for event PORT1NONSECURE</description>
51343 <description>Read: Disabled</description>
51348 <description>Read: Enabled</description>
51356 <description>Disable</description>
51363 <description>Write '1' to disable interrupt for event PORT1SECURE</description>
51370 <description>Read: Disabled</description>
51375 <description>Read: Enabled</description>
51383 <description>Disable</description>
51390 <description>Write '1' to disable interrupt for event PORT2NONSECURE</description>
51397 <description>Read: Disabled</description>
51402 <description>Read: Enabled</description>
51410 <description>Disable</description>
51417 <description>Write '1' to disable interrupt for event PORT2SECURE</description>
51424 <description>Read: Disabled</description>
51429 <description>Read: Enabled</description>
51437 <description>Disable</description>
51444 <description>Write '1' to disable interrupt for event PORT3NONSECURE</description>
51451 <description>Read: Disabled</description>
51456 <description>Read: Enabled</description>
51464 <description>Disable</description>
51471 <description>Write '1' to disable interrupt for event PORT3SECURE</description>
51478 <description>Read: Disabled</description>
51483 <description>Read: Enabled</description>
51491 <description>Disable</description>
51500 …<description>Latency selection for Event mode (MODE=Event) with rising or falling edge detection o…
51509 <description>Latency setting</description>
51515 <description>Low power setting</description>
51520 <description>Low latency setting</description>
51531 …<description>Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] …
51539 <description>Mode</description>
51545 …<description>Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module.</descripti…
51550 <description>Event mode</description>
51555 <description>Task mode</description>
51562 …<description>GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event</descrip…
51568 <description>Port number</description>
51574 …description>When In task mode: Operation to be performed on output when OUT[n] task is triggered. …
51580 …<description>Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on…
51585 …<description>Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edg…
51590 …<description>Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling …
51595 …<description>Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin.…
51602 …<description>When in task mode: Initial value of the output when the GPIOTE channel is configured.…
51608 … <description>Task mode: Initial value of pin before task triggering is low</description>
51613 … <description>Task mode: Initial value of pin before task triggering is high</description>
51624 <description>Global Real-time counter</description>
51653 … <description>Description collection: Capture the counter value to CC[n] register</description>
51661 <description>Capture the counter value to CC[n] register</description>
51667 <description>Trigger task</description>
51676 <description>Start the PWM</description>
51684 <description>Start the PWM</description>
51690 <description>Trigger task</description>
51699 <description>Stop the PWM</description>
51707 <description>Stop the PWM</description>
51713 <description>Trigger task</description>
51724 … <description>Description collection: Subscribe configuration for task CAPTURE[n]</description>
51732 <description>DPPI channel that task CAPTURE[n] will subscribe to</description>
51743 <description>Disable subscription</description>
51748 <description>Enable subscription</description>
51759 <description>Description collection: Compare event on CC[n] match</description>
51767 <description>Compare event on CC[n] match</description>
51773 <description>Event not generated</description>
51778 <description>Event generated</description>
51787 … <description>The GRTC low frequency timer is synchronized with the SYSCOUNTER</description>
51795 … <description>The GRTC low frequency timer is synchronized with the SYSCOUNTER</description>
51801 <description>Event not generated</description>
51806 <description>Event generated</description>
51815 <description>Event on end of each PWM period</description>
51823 <description>Event on end of each PWM period</description>
51829 <description>Event not generated</description>
51834 <description>Event generated</description>
51845 … <description>Description collection: Publish configuration for event COMPARE[n]</description>
51853 <description>DPPI channel that event COMPARE[n] will publish to</description>
51864 <description>Disable publishing</description>
51869 <description>Enable publishing</description>
51878 <description>Shortcuts between local events and tasks</description>
51886 <description>Enable or disable interrupt</description>
51894 <description>Enable or disable interrupt for event COMPARE[0]</description>
51900 <description>Disable</description>
51905 <description>Enable</description>
51912 <description>Enable or disable interrupt for event COMPARE[1]</description>
51918 <description>Disable</description>
51923 <description>Enable</description>
51930 <description>Enable or disable interrupt for event COMPARE[2]</description>
51936 <description>Disable</description>
51941 <description>Enable</description>
51948 <description>Enable or disable interrupt for event COMPARE[3]</description>
51954 <description>Disable</description>
51959 <description>Enable</description>
51966 <description>Enable or disable interrupt for event COMPARE[4]</description>
51972 <description>Disable</description>
51977 <description>Enable</description>
51984 <description>Enable or disable interrupt for event COMPARE[5]</description>
51990 <description>Disable</description>
51995 <description>Enable</description>
52002 <description>Enable or disable interrupt for event COMPARE[6]</description>
52008 <description>Disable</description>
52013 <description>Enable</description>
52020 <description>Enable or disable interrupt for event COMPARE[7]</description>
52026 <description>Disable</description>
52031 <description>Enable</description>
52038 <description>Enable or disable interrupt for event COMPARE[8]</description>
52044 <description>Disable</description>
52049 <description>Enable</description>
52056 <description>Enable or disable interrupt for event COMPARE[9]</description>
52062 <description>Disable</description>
52067 <description>Enable</description>
52074 <description>Enable or disable interrupt for event COMPARE[10]</description>
52080 <description>Disable</description>
52085 <description>Enable</description>
52092 <description>Enable or disable interrupt for event COMPARE[11]</description>
52098 <description>Disable</description>
52103 <description>Enable</description>
52110 <description>Enable or disable interrupt for event COMPARE[12]</description>
52116 <description>Disable</description>
52121 <description>Enable</description>
52128 <description>Enable or disable interrupt for event COMPARE[13]</description>
52134 <description>Disable</description>
52139 <description>Enable</description>
52146 <description>Enable or disable interrupt for event COMPARE[14]</description>
52152 <description>Disable</description>
52157 <description>Enable</description>
52164 <description>Enable or disable interrupt for event COMPARE[15]</description>
52170 <description>Disable</description>
52175 <description>Enable</description>
52182 <description>Enable or disable interrupt for event RTCOMPARESYNC</description>
52188 <description>Disable</description>
52193 <description>Enable</description>
52200 <description>Enable or disable interrupt for event PWMPERIODEND</description>
52206 <description>Disable</description>
52211 <description>Enable</description>
52220 <description>Enable interrupt</description>
52228 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
52235 <description>Read: Disabled</description>
52240 <description>Read: Enabled</description>
52248 <description>Enable</description>
52255 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
52262 <description>Read: Disabled</description>
52267 <description>Read: Enabled</description>
52275 <description>Enable</description>
52282 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
52289 <description>Read: Disabled</description>
52294 <description>Read: Enabled</description>
52302 <description>Enable</description>
52309 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
52316 <description>Read: Disabled</description>
52321 <description>Read: Enabled</description>
52329 <description>Enable</description>
52336 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
52343 <description>Read: Disabled</description>
52348 <description>Read: Enabled</description>
52356 <description>Enable</description>
52363 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
52370 <description>Read: Disabled</description>
52375 <description>Read: Enabled</description>
52383 <description>Enable</description>
52390 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
52397 <description>Read: Disabled</description>
52402 <description>Read: Enabled</description>
52410 <description>Enable</description>
52417 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
52424 <description>Read: Disabled</description>
52429 <description>Read: Enabled</description>
52437 <description>Enable</description>
52444 <description>Write '1' to enable interrupt for event COMPARE[8]</description>
52451 <description>Read: Disabled</description>
52456 <description>Read: Enabled</description>
52464 <description>Enable</description>
52471 <description>Write '1' to enable interrupt for event COMPARE[9]</description>
52478 <description>Read: Disabled</description>
52483 <description>Read: Enabled</description>
52491 <description>Enable</description>
52498 <description>Write '1' to enable interrupt for event COMPARE[10]</description>
52505 <description>Read: Disabled</description>
52510 <description>Read: Enabled</description>
52518 <description>Enable</description>
52525 <description>Write '1' to enable interrupt for event COMPARE[11]</description>
52532 <description>Read: Disabled</description>
52537 <description>Read: Enabled</description>
52545 <description>Enable</description>
52552 <description>Write '1' to enable interrupt for event COMPARE[12]</description>
52559 <description>Read: Disabled</description>
52564 <description>Read: Enabled</description>
52572 <description>Enable</description>
52579 <description>Write '1' to enable interrupt for event COMPARE[13]</description>
52586 <description>Read: Disabled</description>
52591 <description>Read: Enabled</description>
52599 <description>Enable</description>
52606 <description>Write '1' to enable interrupt for event COMPARE[14]</description>
52613 <description>Read: Disabled</description>
52618 <description>Read: Enabled</description>
52626 <description>Enable</description>
52633 <description>Write '1' to enable interrupt for event COMPARE[15]</description>
52640 <description>Read: Disabled</description>
52645 <description>Read: Enabled</description>
52653 <description>Enable</description>
52660 <description>Write '1' to enable interrupt for event RTCOMPARESYNC</description>
52667 <description>Read: Disabled</description>
52672 <description>Read: Enabled</description>
52680 <description>Enable</description>
52687 <description>Write '1' to enable interrupt for event PWMPERIODEND</description>
52694 <description>Read: Disabled</description>
52699 <description>Read: Enabled</description>
52707 <description>Enable</description>
52716 <description>Disable interrupt</description>
52724 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
52731 <description>Read: Disabled</description>
52736 <description>Read: Enabled</description>
52744 <description>Disable</description>
52751 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
52758 <description>Read: Disabled</description>
52763 <description>Read: Enabled</description>
52771 <description>Disable</description>
52778 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
52785 <description>Read: Disabled</description>
52790 <description>Read: Enabled</description>
52798 <description>Disable</description>
52805 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
52812 <description>Read: Disabled</description>
52817 <description>Read: Enabled</description>
52825 <description>Disable</description>
52832 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
52839 <description>Read: Disabled</description>
52844 <description>Read: Enabled</description>
52852 <description>Disable</description>
52859 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
52866 <description>Read: Disabled</description>
52871 <description>Read: Enabled</description>
52879 <description>Disable</description>
52886 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
52893 <description>Read: Disabled</description>
52898 <description>Read: Enabled</description>
52906 <description>Disable</description>
52913 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
52920 <description>Read: Disabled</description>
52925 <description>Read: Enabled</description>
52933 <description>Disable</description>
52940 <description>Write '1' to disable interrupt for event COMPARE[8]</description>
52947 <description>Read: Disabled</description>
52952 <description>Read: Enabled</description>
52960 <description>Disable</description>
52967 <description>Write '1' to disable interrupt for event COMPARE[9]</description>
52974 <description>Read: Disabled</description>
52979 <description>Read: Enabled</description>
52987 <description>Disable</description>
52994 <description>Write '1' to disable interrupt for event COMPARE[10]</description>
53001 <description>Read: Disabled</description>
53006 <description>Read: Enabled</description>
53014 <description>Disable</description>
53021 <description>Write '1' to disable interrupt for event COMPARE[11]</description>
53028 <description>Read: Disabled</description>
53033 <description>Read: Enabled</description>
53041 <description>Disable</description>
53048 <description>Write '1' to disable interrupt for event COMPARE[12]</description>
53055 <description>Read: Disabled</description>
53060 <description>Read: Enabled</description>
53068 <description>Disable</description>
53075 <description>Write '1' to disable interrupt for event COMPARE[13]</description>
53082 <description>Read: Disabled</description>
53087 <description>Read: Enabled</description>
53095 <description>Disable</description>
53102 <description>Write '1' to disable interrupt for event COMPARE[14]</description>
53109 <description>Read: Disabled</description>
53114 <description>Read: Enabled</description>
53122 <description>Disable</description>
53129 <description>Write '1' to disable interrupt for event COMPARE[15]</description>
53136 <description>Read: Disabled</description>
53141 <description>Read: Enabled</description>
53149 <description>Disable</description>
53156 <description>Write '1' to disable interrupt for event RTCOMPARESYNC</description>
53163 <description>Read: Disabled</description>
53168 <description>Read: Enabled</description>
53176 <description>Disable</description>
53183 <description>Write '1' to disable interrupt for event PWMPERIODEND</description>
53190 <description>Read: Disabled</description>
53195 <description>Read: Enabled</description>
53203 <description>Disable</description>
53212 <description>Pending interrupts</description>
53220 <description>Read pending status of interrupt for event COMPARE[0]</description>
53227 <description>Read: Not pending</description>
53232 <description>Read: Pending</description>
53239 <description>Read pending status of interrupt for event COMPARE[1]</description>
53246 <description>Read: Not pending</description>
53251 <description>Read: Pending</description>
53258 <description>Read pending status of interrupt for event COMPARE[2]</description>
53265 <description>Read: Not pending</description>
53270 <description>Read: Pending</description>
53277 <description>Read pending status of interrupt for event COMPARE[3]</description>
53284 <description>Read: Not pending</description>
53289 <description>Read: Pending</description>
53296 <description>Read pending status of interrupt for event COMPARE[4]</description>
53303 <description>Read: Not pending</description>
53308 <description>Read: Pending</description>
53315 <description>Read pending status of interrupt for event COMPARE[5]</description>
53322 <description>Read: Not pending</description>
53327 <description>Read: Pending</description>
53334 <description>Read pending status of interrupt for event COMPARE[6]</description>
53341 <description>Read: Not pending</description>
53346 <description>Read: Pending</description>
53353 <description>Read pending status of interrupt for event COMPARE[7]</description>
53360 <description>Read: Not pending</description>
53365 <description>Read: Pending</description>
53372 <description>Read pending status of interrupt for event COMPARE[8]</description>
53379 <description>Read: Not pending</description>
53384 <description>Read: Pending</description>
53391 <description>Read pending status of interrupt for event COMPARE[9]</description>
53398 <description>Read: Not pending</description>
53403 <description>Read: Pending</description>
53410 <description>Read pending status of interrupt for event COMPARE[10]</description>
53417 <description>Read: Not pending</description>
53422 <description>Read: Pending</description>
53429 <description>Read pending status of interrupt for event COMPARE[11]</description>
53436 <description>Read: Not pending</description>
53441 <description>Read: Pending</description>
53448 <description>Read pending status of interrupt for event COMPARE[12]</description>
53455 <description>Read: Not pending</description>
53460 <description>Read: Pending</description>
53467 <description>Read pending status of interrupt for event COMPARE[13]</description>
53474 <description>Read: Not pending</description>
53479 <description>Read: Pending</description>
53486 <description>Read pending status of interrupt for event COMPARE[14]</description>
53493 <description>Read: Not pending</description>
53498 <description>Read: Pending</description>
53505 <description>Read pending status of interrupt for event COMPARE[15]</description>
53512 <description>Read: Not pending</description>
53517 <description>Read: Pending</description>
53524 <description>Read pending status of interrupt for event RTCOMPARESYNC</description>
53531 <description>Read: Not pending</description>
53536 <description>Read: Pending</description>
53543 <description>Read pending status of interrupt for event PWMPERIODEND</description>
53550 <description>Read: Not pending</description>
53555 <description>Read: Pending</description>
53564 <description>Enable or disable interrupt</description>
53572 <description>Enable or disable interrupt for event COMPARE[0]</description>
53578 <description>Disable</description>
53583 <description>Enable</description>
53590 <description>Enable or disable interrupt for event COMPARE[1]</description>
53596 <description>Disable</description>
53601 <description>Enable</description>
53608 <description>Enable or disable interrupt for event COMPARE[2]</description>
53614 <description>Disable</description>
53619 <description>Enable</description>
53626 <description>Enable or disable interrupt for event COMPARE[3]</description>
53632 <description>Disable</description>
53637 <description>Enable</description>
53644 <description>Enable or disable interrupt for event COMPARE[4]</description>
53650 <description>Disable</description>
53655 <description>Enable</description>
53662 <description>Enable or disable interrupt for event COMPARE[5]</description>
53668 <description>Disable</description>
53673 <description>Enable</description>
53680 <description>Enable or disable interrupt for event COMPARE[6]</description>
53686 <description>Disable</description>
53691 <description>Enable</description>
53698 <description>Enable or disable interrupt for event COMPARE[7]</description>
53704 <description>Disable</description>
53709 <description>Enable</description>
53716 <description>Enable or disable interrupt for event COMPARE[8]</description>
53722 <description>Disable</description>
53727 <description>Enable</description>
53734 <description>Enable or disable interrupt for event COMPARE[9]</description>
53740 <description>Disable</description>
53745 <description>Enable</description>
53752 <description>Enable or disable interrupt for event COMPARE[10]</description>
53758 <description>Disable</description>
53763 <description>Enable</description>
53770 <description>Enable or disable interrupt for event COMPARE[11]</description>
53776 <description>Disable</description>
53781 <description>Enable</description>
53788 <description>Enable or disable interrupt for event COMPARE[12]</description>
53794 <description>Disable</description>
53799 <description>Enable</description>
53806 <description>Enable or disable interrupt for event COMPARE[13]</description>
53812 <description>Disable</description>
53817 <description>Enable</description>
53824 <description>Enable or disable interrupt for event COMPARE[14]</description>
53830 <description>Disable</description>
53835 <description>Enable</description>
53842 <description>Enable or disable interrupt for event COMPARE[15]</description>
53848 <description>Disable</description>
53853 <description>Enable</description>
53860 <description>Enable or disable interrupt for event RTCOMPARESYNC</description>
53866 <description>Disable</description>
53871 <description>Enable</description>
53878 <description>Enable or disable interrupt for event PWMPERIODEND</description>
53884 <description>Disable</description>
53889 <description>Enable</description>
53898 <description>Enable interrupt</description>
53906 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
53913 <description>Read: Disabled</description>
53918 <description>Read: Enabled</description>
53926 <description>Enable</description>
53933 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
53940 <description>Read: Disabled</description>
53945 <description>Read: Enabled</description>
53953 <description>Enable</description>
53960 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
53967 <description>Read: Disabled</description>
53972 <description>Read: Enabled</description>
53980 <description>Enable</description>
53987 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
53994 <description>Read: Disabled</description>
53999 <description>Read: Enabled</description>
54007 <description>Enable</description>
54014 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
54021 <description>Read: Disabled</description>
54026 <description>Read: Enabled</description>
54034 <description>Enable</description>
54041 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
54048 <description>Read: Disabled</description>
54053 <description>Read: Enabled</description>
54061 <description>Enable</description>
54068 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
54075 <description>Read: Disabled</description>
54080 <description>Read: Enabled</description>
54088 <description>Enable</description>
54095 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
54102 <description>Read: Disabled</description>
54107 <description>Read: Enabled</description>
54115 <description>Enable</description>
54122 <description>Write '1' to enable interrupt for event COMPARE[8]</description>
54129 <description>Read: Disabled</description>
54134 <description>Read: Enabled</description>
54142 <description>Enable</description>
54149 <description>Write '1' to enable interrupt for event COMPARE[9]</description>
54156 <description>Read: Disabled</description>
54161 <description>Read: Enabled</description>
54169 <description>Enable</description>
54176 <description>Write '1' to enable interrupt for event COMPARE[10]</description>
54183 <description>Read: Disabled</description>
54188 <description>Read: Enabled</description>
54196 <description>Enable</description>
54203 <description>Write '1' to enable interrupt for event COMPARE[11]</description>
54210 <description>Read: Disabled</description>
54215 <description>Read: Enabled</description>
54223 <description>Enable</description>
54230 <description>Write '1' to enable interrupt for event COMPARE[12]</description>
54237 <description>Read: Disabled</description>
54242 <description>Read: Enabled</description>
54250 <description>Enable</description>
54257 <description>Write '1' to enable interrupt for event COMPARE[13]</description>
54264 <description>Read: Disabled</description>
54269 <description>Read: Enabled</description>
54277 <description>Enable</description>
54284 <description>Write '1' to enable interrupt for event COMPARE[14]</description>
54291 <description>Read: Disabled</description>
54296 <description>Read: Enabled</description>
54304 <description>Enable</description>
54311 <description>Write '1' to enable interrupt for event COMPARE[15]</description>
54318 <description>Read: Disabled</description>
54323 <description>Read: Enabled</description>
54331 <description>Enable</description>
54338 <description>Write '1' to enable interrupt for event RTCOMPARESYNC</description>
54345 <description>Read: Disabled</description>
54350 <description>Read: Enabled</description>
54358 <description>Enable</description>
54365 <description>Write '1' to enable interrupt for event PWMPERIODEND</description>
54372 <description>Read: Disabled</description>
54377 <description>Read: Enabled</description>
54385 <description>Enable</description>
54394 <description>Disable interrupt</description>
54402 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
54409 <description>Read: Disabled</description>
54414 <description>Read: Enabled</description>
54422 <description>Disable</description>
54429 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
54436 <description>Read: Disabled</description>
54441 <description>Read: Enabled</description>
54449 <description>Disable</description>
54456 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
54463 <description>Read: Disabled</description>
54468 <description>Read: Enabled</description>
54476 <description>Disable</description>
54483 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
54490 <description>Read: Disabled</description>
54495 <description>Read: Enabled</description>
54503 <description>Disable</description>
54510 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
54517 <description>Read: Disabled</description>
54522 <description>Read: Enabled</description>
54530 <description>Disable</description>
54537 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
54544 <description>Read: Disabled</description>
54549 <description>Read: Enabled</description>
54557 <description>Disable</description>
54564 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
54571 <description>Read: Disabled</description>
54576 <description>Read: Enabled</description>
54584 <description>Disable</description>
54591 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
54598 <description>Read: Disabled</description>
54603 <description>Read: Enabled</description>
54611 <description>Disable</description>
54618 <description>Write '1' to disable interrupt for event COMPARE[8]</description>
54625 <description>Read: Disabled</description>
54630 <description>Read: Enabled</description>
54638 <description>Disable</description>
54645 <description>Write '1' to disable interrupt for event COMPARE[9]</description>
54652 <description>Read: Disabled</description>
54657 <description>Read: Enabled</description>
54665 <description>Disable</description>
54672 <description>Write '1' to disable interrupt for event COMPARE[10]</description>
54679 <description>Read: Disabled</description>
54684 <description>Read: Enabled</description>
54692 <description>Disable</description>
54699 <description>Write '1' to disable interrupt for event COMPARE[11]</description>
54706 <description>Read: Disabled</description>
54711 <description>Read: Enabled</description>
54719 <description>Disable</description>
54726 <description>Write '1' to disable interrupt for event COMPARE[12]</description>
54733 <description>Read: Disabled</description>
54738 <description>Read: Enabled</description>
54746 <description>Disable</description>
54753 <description>Write '1' to disable interrupt for event COMPARE[13]</description>
54760 <description>Read: Disabled</description>
54765 <description>Read: Enabled</description>
54773 <description>Disable</description>
54780 <description>Write '1' to disable interrupt for event COMPARE[14]</description>
54787 <description>Read: Disabled</description>
54792 <description>Read: Enabled</description>
54800 <description>Disable</description>
54807 <description>Write '1' to disable interrupt for event COMPARE[15]</description>
54814 <description>Read: Disabled</description>
54819 <description>Read: Enabled</description>
54827 <description>Disable</description>
54834 <description>Write '1' to disable interrupt for event RTCOMPARESYNC</description>
54841 <description>Read: Disabled</description>
54846 <description>Read: Enabled</description>
54854 <description>Disable</description>
54861 <description>Write '1' to disable interrupt for event PWMPERIODEND</description>
54868 <description>Read: Disabled</description>
54873 <description>Read: Enabled</description>
54881 <description>Disable</description>
54890 <description>Pending interrupts</description>
54898 <description>Read pending status of interrupt for event COMPARE[0]</description>
54905 <description>Read: Not pending</description>
54910 <description>Read: Pending</description>
54917 <description>Read pending status of interrupt for event COMPARE[1]</description>
54924 <description>Read: Not pending</description>
54929 <description>Read: Pending</description>
54936 <description>Read pending status of interrupt for event COMPARE[2]</description>
54943 <description>Read: Not pending</description>
54948 <description>Read: Pending</description>
54955 <description>Read pending status of interrupt for event COMPARE[3]</description>
54962 <description>Read: Not pending</description>
54967 <description>Read: Pending</description>
54974 <description>Read pending status of interrupt for event COMPARE[4]</description>
54981 <description>Read: Not pending</description>
54986 <description>Read: Pending</description>
54993 <description>Read pending status of interrupt for event COMPARE[5]</description>
55000 <description>Read: Not pending</description>
55005 <description>Read: Pending</description>
55012 <description>Read pending status of interrupt for event COMPARE[6]</description>
55019 <description>Read: Not pending</description>
55024 <description>Read: Pending</description>
55031 <description>Read pending status of interrupt for event COMPARE[7]</description>
55038 <description>Read: Not pending</description>
55043 <description>Read: Pending</description>
55050 <description>Read pending status of interrupt for event COMPARE[8]</description>
55057 <description>Read: Not pending</description>
55062 <description>Read: Pending</description>
55069 <description>Read pending status of interrupt for event COMPARE[9]</description>
55076 <description>Read: Not pending</description>
55081 <description>Read: Pending</description>
55088 <description>Read pending status of interrupt for event COMPARE[10]</description>
55095 <description>Read: Not pending</description>
55100 <description>Read: Pending</description>
55107 <description>Read pending status of interrupt for event COMPARE[11]</description>
55114 <description>Read: Not pending</description>
55119 <description>Read: Pending</description>
55126 <description>Read pending status of interrupt for event COMPARE[12]</description>
55133 <description>Read: Not pending</description>
55138 <description>Read: Pending</description>
55145 <description>Read pending status of interrupt for event COMPARE[13]</description>
55152 <description>Read: Not pending</description>
55157 <description>Read: Pending</description>
55164 <description>Read pending status of interrupt for event COMPARE[14]</description>
55171 <description>Read: Not pending</description>
55176 <description>Read: Pending</description>
55183 <description>Read pending status of interrupt for event COMPARE[15]</description>
55190 <description>Read: Not pending</description>
55195 <description>Read: Pending</description>
55202 <description>Read pending status of interrupt for event RTCOMPARESYNC</description>
55209 <description>Read: Not pending</description>
55214 <description>Read: Pending</description>
55221 <description>Read pending status of interrupt for event PWMPERIODEND</description>
55228 <description>Read: Not pending</description>
55233 <description>Read: Pending</description>
55242 <description>Enable or disable interrupt</description>
55250 <description>Enable or disable interrupt for event COMPARE[0]</description>
55256 <description>Disable</description>
55261 <description>Enable</description>
55268 <description>Enable or disable interrupt for event COMPARE[1]</description>
55274 <description>Disable</description>
55279 <description>Enable</description>
55286 <description>Enable or disable interrupt for event COMPARE[2]</description>
55292 <description>Disable</description>
55297 <description>Enable</description>
55304 <description>Enable or disable interrupt for event COMPARE[3]</description>
55310 <description>Disable</description>
55315 <description>Enable</description>
55322 <description>Enable or disable interrupt for event COMPARE[4]</description>
55328 <description>Disable</description>
55333 <description>Enable</description>
55340 <description>Enable or disable interrupt for event COMPARE[5]</description>
55346 <description>Disable</description>
55351 <description>Enable</description>
55358 <description>Enable or disable interrupt for event COMPARE[6]</description>
55364 <description>Disable</description>
55369 <description>Enable</description>
55376 <description>Enable or disable interrupt for event COMPARE[7]</description>
55382 <description>Disable</description>
55387 <description>Enable</description>
55394 <description>Enable or disable interrupt for event COMPARE[8]</description>
55400 <description>Disable</description>
55405 <description>Enable</description>
55412 <description>Enable or disable interrupt for event COMPARE[9]</description>
55418 <description>Disable</description>
55423 <description>Enable</description>
55430 <description>Enable or disable interrupt for event COMPARE[10]</description>
55436 <description>Disable</description>
55441 <description>Enable</description>
55448 <description>Enable or disable interrupt for event COMPARE[11]</description>
55454 <description>Disable</description>
55459 <description>Enable</description>
55466 <description>Enable or disable interrupt for event COMPARE[12]</description>
55472 <description>Disable</description>
55477 <description>Enable</description>
55484 <description>Enable or disable interrupt for event COMPARE[13]</description>
55490 <description>Disable</description>
55495 <description>Enable</description>
55502 <description>Enable or disable interrupt for event COMPARE[14]</description>
55508 <description>Disable</description>
55513 <description>Enable</description>
55520 <description>Enable or disable interrupt for event COMPARE[15]</description>
55526 <description>Disable</description>
55531 <description>Enable</description>
55538 <description>Enable or disable interrupt for event RTCOMPARESYNC</description>
55544 <description>Disable</description>
55549 <description>Enable</description>
55556 <description>Enable or disable interrupt for event PWMPERIODEND</description>
55562 <description>Disable</description>
55567 <description>Enable</description>
55576 <description>Enable interrupt</description>
55584 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
55591 <description>Read: Disabled</description>
55596 <description>Read: Enabled</description>
55604 <description>Enable</description>
55611 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
55618 <description>Read: Disabled</description>
55623 <description>Read: Enabled</description>
55631 <description>Enable</description>
55638 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
55645 <description>Read: Disabled</description>
55650 <description>Read: Enabled</description>
55658 <description>Enable</description>
55665 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
55672 <description>Read: Disabled</description>
55677 <description>Read: Enabled</description>
55685 <description>Enable</description>
55692 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
55699 <description>Read: Disabled</description>
55704 <description>Read: Enabled</description>
55712 <description>Enable</description>
55719 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
55726 <description>Read: Disabled</description>
55731 <description>Read: Enabled</description>
55739 <description>Enable</description>
55746 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
55753 <description>Read: Disabled</description>
55758 <description>Read: Enabled</description>
55766 <description>Enable</description>
55773 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
55780 <description>Read: Disabled</description>
55785 <description>Read: Enabled</description>
55793 <description>Enable</description>
55800 <description>Write '1' to enable interrupt for event COMPARE[8]</description>
55807 <description>Read: Disabled</description>
55812 <description>Read: Enabled</description>
55820 <description>Enable</description>
55827 <description>Write '1' to enable interrupt for event COMPARE[9]</description>
55834 <description>Read: Disabled</description>
55839 <description>Read: Enabled</description>
55847 <description>Enable</description>
55854 <description>Write '1' to enable interrupt for event COMPARE[10]</description>
55861 <description>Read: Disabled</description>
55866 <description>Read: Enabled</description>
55874 <description>Enable</description>
55881 <description>Write '1' to enable interrupt for event COMPARE[11]</description>
55888 <description>Read: Disabled</description>
55893 <description>Read: Enabled</description>
55901 <description>Enable</description>
55908 <description>Write '1' to enable interrupt for event COMPARE[12]</description>
55915 <description>Read: Disabled</description>
55920 <description>Read: Enabled</description>
55928 <description>Enable</description>
55935 <description>Write '1' to enable interrupt for event COMPARE[13]</description>
55942 <description>Read: Disabled</description>
55947 <description>Read: Enabled</description>
55955 <description>Enable</description>
55962 <description>Write '1' to enable interrupt for event COMPARE[14]</description>
55969 <description>Read: Disabled</description>
55974 <description>Read: Enabled</description>
55982 <description>Enable</description>
55989 <description>Write '1' to enable interrupt for event COMPARE[15]</description>
55996 <description>Read: Disabled</description>
56001 <description>Read: Enabled</description>
56009 <description>Enable</description>
56016 <description>Write '1' to enable interrupt for event RTCOMPARESYNC</description>
56023 <description>Read: Disabled</description>
56028 <description>Read: Enabled</description>
56036 <description>Enable</description>
56043 <description>Write '1' to enable interrupt for event PWMPERIODEND</description>
56050 <description>Read: Disabled</description>
56055 <description>Read: Enabled</description>
56063 <description>Enable</description>
56072 <description>Disable interrupt</description>
56080 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
56087 <description>Read: Disabled</description>
56092 <description>Read: Enabled</description>
56100 <description>Disable</description>
56107 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
56114 <description>Read: Disabled</description>
56119 <description>Read: Enabled</description>
56127 <description>Disable</description>
56134 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
56141 <description>Read: Disabled</description>
56146 <description>Read: Enabled</description>
56154 <description>Disable</description>
56161 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
56168 <description>Read: Disabled</description>
56173 <description>Read: Enabled</description>
56181 <description>Disable</description>
56188 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
56195 <description>Read: Disabled</description>
56200 <description>Read: Enabled</description>
56208 <description>Disable</description>
56215 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
56222 <description>Read: Disabled</description>
56227 <description>Read: Enabled</description>
56235 <description>Disable</description>
56242 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
56249 <description>Read: Disabled</description>
56254 <description>Read: Enabled</description>
56262 <description>Disable</description>
56269 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
56276 <description>Read: Disabled</description>
56281 <description>Read: Enabled</description>
56289 <description>Disable</description>
56296 <description>Write '1' to disable interrupt for event COMPARE[8]</description>
56303 <description>Read: Disabled</description>
56308 <description>Read: Enabled</description>
56316 <description>Disable</description>
56323 <description>Write '1' to disable interrupt for event COMPARE[9]</description>
56330 <description>Read: Disabled</description>
56335 <description>Read: Enabled</description>
56343 <description>Disable</description>
56350 <description>Write '1' to disable interrupt for event COMPARE[10]</description>
56357 <description>Read: Disabled</description>
56362 <description>Read: Enabled</description>
56370 <description>Disable</description>
56377 <description>Write '1' to disable interrupt for event COMPARE[11]</description>
56384 <description>Read: Disabled</description>
56389 <description>Read: Enabled</description>
56397 <description>Disable</description>
56404 <description>Write '1' to disable interrupt for event COMPARE[12]</description>
56411 <description>Read: Disabled</description>
56416 <description>Read: Enabled</description>
56424 <description>Disable</description>
56431 <description>Write '1' to disable interrupt for event COMPARE[13]</description>
56438 <description>Read: Disabled</description>
56443 <description>Read: Enabled</description>
56451 <description>Disable</description>
56458 <description>Write '1' to disable interrupt for event COMPARE[14]</description>
56465 <description>Read: Disabled</description>
56470 <description>Read: Enabled</description>
56478 <description>Disable</description>
56485 <description>Write '1' to disable interrupt for event COMPARE[15]</description>
56492 <description>Read: Disabled</description>
56497 <description>Read: Enabled</description>
56505 <description>Disable</description>
56512 <description>Write '1' to disable interrupt for event RTCOMPARESYNC</description>
56519 <description>Read: Disabled</description>
56524 <description>Read: Enabled</description>
56532 <description>Disable</description>
56539 <description>Write '1' to disable interrupt for event PWMPERIODEND</description>
56546 <description>Read: Disabled</description>
56551 <description>Read: Enabled</description>
56559 <description>Disable</description>
56568 <description>Pending interrupts</description>
56576 <description>Read pending status of interrupt for event COMPARE[0]</description>
56583 <description>Read: Not pending</description>
56588 <description>Read: Pending</description>
56595 <description>Read pending status of interrupt for event COMPARE[1]</description>
56602 <description>Read: Not pending</description>
56607 <description>Read: Pending</description>
56614 <description>Read pending status of interrupt for event COMPARE[2]</description>
56621 <description>Read: Not pending</description>
56626 <description>Read: Pending</description>
56633 <description>Read pending status of interrupt for event COMPARE[3]</description>
56640 <description>Read: Not pending</description>
56645 <description>Read: Pending</description>
56652 <description>Read pending status of interrupt for event COMPARE[4]</description>
56659 <description>Read: Not pending</description>
56664 <description>Read: Pending</description>
56671 <description>Read pending status of interrupt for event COMPARE[5]</description>
56678 <description>Read: Not pending</description>
56683 <description>Read: Pending</description>
56690 <description>Read pending status of interrupt for event COMPARE[6]</description>
56697 <description>Read: Not pending</description>
56702 <description>Read: Pending</description>
56709 <description>Read pending status of interrupt for event COMPARE[7]</description>
56716 <description>Read: Not pending</description>
56721 <description>Read: Pending</description>
56728 <description>Read pending status of interrupt for event COMPARE[8]</description>
56735 <description>Read: Not pending</description>
56740 <description>Read: Pending</description>
56747 <description>Read pending status of interrupt for event COMPARE[9]</description>
56754 <description>Read: Not pending</description>
56759 <description>Read: Pending</description>
56766 <description>Read pending status of interrupt for event COMPARE[10]</description>
56773 <description>Read: Not pending</description>
56778 <description>Read: Pending</description>
56785 <description>Read pending status of interrupt for event COMPARE[11]</description>
56792 <description>Read: Not pending</description>
56797 <description>Read: Pending</description>
56804 <description>Read pending status of interrupt for event COMPARE[12]</description>
56811 <description>Read: Not pending</description>
56816 <description>Read: Pending</description>
56823 <description>Read pending status of interrupt for event COMPARE[13]</description>
56830 <description>Read: Not pending</description>
56835 <description>Read: Pending</description>
56842 <description>Read pending status of interrupt for event COMPARE[14]</description>
56849 <description>Read: Not pending</description>
56854 <description>Read: Pending</description>
56861 <description>Read pending status of interrupt for event COMPARE[15]</description>
56868 <description>Read: Not pending</description>
56873 <description>Read: Pending</description>
56880 <description>Read pending status of interrupt for event RTCOMPARESYNC</description>
56887 <description>Read: Not pending</description>
56892 <description>Read: Pending</description>
56899 <description>Read pending status of interrupt for event PWMPERIODEND</description>
56906 <description>Read: Not pending</description>
56911 <description>Read: Pending</description>
56920 <description>Enable or disable interrupt</description>
56928 <description>Enable or disable interrupt for event COMPARE[0]</description>
56934 <description>Disable</description>
56939 <description>Enable</description>
56946 <description>Enable or disable interrupt for event COMPARE[1]</description>
56952 <description>Disable</description>
56957 <description>Enable</description>
56964 <description>Enable or disable interrupt for event COMPARE[2]</description>
56970 <description>Disable</description>
56975 <description>Enable</description>
56982 <description>Enable or disable interrupt for event COMPARE[3]</description>
56988 <description>Disable</description>
56993 <description>Enable</description>
57000 <description>Enable or disable interrupt for event COMPARE[4]</description>
57006 <description>Disable</description>
57011 <description>Enable</description>
57018 <description>Enable or disable interrupt for event COMPARE[5]</description>
57024 <description>Disable</description>
57029 <description>Enable</description>
57036 <description>Enable or disable interrupt for event COMPARE[6]</description>
57042 <description>Disable</description>
57047 <description>Enable</description>
57054 <description>Enable or disable interrupt for event COMPARE[7]</description>
57060 <description>Disable</description>
57065 <description>Enable</description>
57072 <description>Enable or disable interrupt for event COMPARE[8]</description>
57078 <description>Disable</description>
57083 <description>Enable</description>
57090 <description>Enable or disable interrupt for event COMPARE[9]</description>
57096 <description>Disable</description>
57101 <description>Enable</description>
57108 <description>Enable or disable interrupt for event COMPARE[10]</description>
57114 <description>Disable</description>
57119 <description>Enable</description>
57126 <description>Enable or disable interrupt for event COMPARE[11]</description>
57132 <description>Disable</description>
57137 <description>Enable</description>
57144 <description>Enable or disable interrupt for event COMPARE[12]</description>
57150 <description>Disable</description>
57155 <description>Enable</description>
57162 <description>Enable or disable interrupt for event COMPARE[13]</description>
57168 <description>Disable</description>
57173 <description>Enable</description>
57180 <description>Enable or disable interrupt for event COMPARE[14]</description>
57186 <description>Disable</description>
57191 <description>Enable</description>
57198 <description>Enable or disable interrupt for event COMPARE[15]</description>
57204 <description>Disable</description>
57209 <description>Enable</description>
57216 <description>Enable or disable interrupt for event RTCOMPARESYNC</description>
57222 <description>Disable</description>
57227 <description>Enable</description>
57234 <description>Enable or disable interrupt for event PWMPERIODEND</description>
57240 <description>Disable</description>
57245 <description>Enable</description>
57254 <description>Enable interrupt</description>
57262 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
57269 <description>Read: Disabled</description>
57274 <description>Read: Enabled</description>
57282 <description>Enable</description>
57289 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
57296 <description>Read: Disabled</description>
57301 <description>Read: Enabled</description>
57309 <description>Enable</description>
57316 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
57323 <description>Read: Disabled</description>
57328 <description>Read: Enabled</description>
57336 <description>Enable</description>
57343 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
57350 <description>Read: Disabled</description>
57355 <description>Read: Enabled</description>
57363 <description>Enable</description>
57370 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
57377 <description>Read: Disabled</description>
57382 <description>Read: Enabled</description>
57390 <description>Enable</description>
57397 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
57404 <description>Read: Disabled</description>
57409 <description>Read: Enabled</description>
57417 <description>Enable</description>
57424 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
57431 <description>Read: Disabled</description>
57436 <description>Read: Enabled</description>
57444 <description>Enable</description>
57451 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
57458 <description>Read: Disabled</description>
57463 <description>Read: Enabled</description>
57471 <description>Enable</description>
57478 <description>Write '1' to enable interrupt for event COMPARE[8]</description>
57485 <description>Read: Disabled</description>
57490 <description>Read: Enabled</description>
57498 <description>Enable</description>
57505 <description>Write '1' to enable interrupt for event COMPARE[9]</description>
57512 <description>Read: Disabled</description>
57517 <description>Read: Enabled</description>
57525 <description>Enable</description>
57532 <description>Write '1' to enable interrupt for event COMPARE[10]</description>
57539 <description>Read: Disabled</description>
57544 <description>Read: Enabled</description>
57552 <description>Enable</description>
57559 <description>Write '1' to enable interrupt for event COMPARE[11]</description>
57566 <description>Read: Disabled</description>
57571 <description>Read: Enabled</description>
57579 <description>Enable</description>
57586 <description>Write '1' to enable interrupt for event COMPARE[12]</description>
57593 <description>Read: Disabled</description>
57598 <description>Read: Enabled</description>
57606 <description>Enable</description>
57613 <description>Write '1' to enable interrupt for event COMPARE[13]</description>
57620 <description>Read: Disabled</description>
57625 <description>Read: Enabled</description>
57633 <description>Enable</description>
57640 <description>Write '1' to enable interrupt for event COMPARE[14]</description>
57647 <description>Read: Disabled</description>
57652 <description>Read: Enabled</description>
57660 <description>Enable</description>
57667 <description>Write '1' to enable interrupt for event COMPARE[15]</description>
57674 <description>Read: Disabled</description>
57679 <description>Read: Enabled</description>
57687 <description>Enable</description>
57694 <description>Write '1' to enable interrupt for event RTCOMPARESYNC</description>
57701 <description>Read: Disabled</description>
57706 <description>Read: Enabled</description>
57714 <description>Enable</description>
57721 <description>Write '1' to enable interrupt for event PWMPERIODEND</description>
57728 <description>Read: Disabled</description>
57733 <description>Read: Enabled</description>
57741 <description>Enable</description>
57750 <description>Disable interrupt</description>
57758 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
57765 <description>Read: Disabled</description>
57770 <description>Read: Enabled</description>
57778 <description>Disable</description>
57785 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
57792 <description>Read: Disabled</description>
57797 <description>Read: Enabled</description>
57805 <description>Disable</description>
57812 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
57819 <description>Read: Disabled</description>
57824 <description>Read: Enabled</description>
57832 <description>Disable</description>
57839 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
57846 <description>Read: Disabled</description>
57851 <description>Read: Enabled</description>
57859 <description>Disable</description>
57866 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
57873 <description>Read: Disabled</description>
57878 <description>Read: Enabled</description>
57886 <description>Disable</description>
57893 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
57900 <description>Read: Disabled</description>
57905 <description>Read: Enabled</description>
57913 <description>Disable</description>
57920 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
57927 <description>Read: Disabled</description>
57932 <description>Read: Enabled</description>
57940 <description>Disable</description>
57947 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
57954 <description>Read: Disabled</description>
57959 <description>Read: Enabled</description>
57967 <description>Disable</description>
57974 <description>Write '1' to disable interrupt for event COMPARE[8]</description>
57981 <description>Read: Disabled</description>
57986 <description>Read: Enabled</description>
57994 <description>Disable</description>
58001 <description>Write '1' to disable interrupt for event COMPARE[9]</description>
58008 <description>Read: Disabled</description>
58013 <description>Read: Enabled</description>
58021 <description>Disable</description>
58028 <description>Write '1' to disable interrupt for event COMPARE[10]</description>
58035 <description>Read: Disabled</description>
58040 <description>Read: Enabled</description>
58048 <description>Disable</description>
58055 <description>Write '1' to disable interrupt for event COMPARE[11]</description>
58062 <description>Read: Disabled</description>
58067 <description>Read: Enabled</description>
58075 <description>Disable</description>
58082 <description>Write '1' to disable interrupt for event COMPARE[12]</description>
58089 <description>Read: Disabled</description>
58094 <description>Read: Enabled</description>
58102 <description>Disable</description>
58109 <description>Write '1' to disable interrupt for event COMPARE[13]</description>
58116 <description>Read: Disabled</description>
58121 <description>Read: Enabled</description>
58129 <description>Disable</description>
58136 <description>Write '1' to disable interrupt for event COMPARE[14]</description>
58143 <description>Read: Disabled</description>
58148 <description>Read: Enabled</description>
58156 <description>Disable</description>
58163 <description>Write '1' to disable interrupt for event COMPARE[15]</description>
58170 <description>Read: Disabled</description>
58175 <description>Read: Enabled</description>
58183 <description>Disable</description>
58190 <description>Write '1' to disable interrupt for event RTCOMPARESYNC</description>
58197 <description>Read: Disabled</description>
58202 <description>Read: Enabled</description>
58210 <description>Disable</description>
58217 <description>Write '1' to disable interrupt for event PWMPERIODEND</description>
58224 <description>Read: Disabled</description>
58229 <description>Read: Enabled</description>
58237 <description>Disable</description>
58246 <description>Pending interrupts</description>
58254 <description>Read pending status of interrupt for event COMPARE[0]</description>
58261 <description>Read: Not pending</description>
58266 <description>Read: Pending</description>
58273 <description>Read pending status of interrupt for event COMPARE[1]</description>
58280 <description>Read: Not pending</description>
58285 <description>Read: Pending</description>
58292 <description>Read pending status of interrupt for event COMPARE[2]</description>
58299 <description>Read: Not pending</description>
58304 <description>Read: Pending</description>
58311 <description>Read pending status of interrupt for event COMPARE[3]</description>
58318 <description>Read: Not pending</description>
58323 <description>Read: Pending</description>
58330 <description>Read pending status of interrupt for event COMPARE[4]</description>
58337 <description>Read: Not pending</description>
58342 <description>Read: Pending</description>
58349 <description>Read pending status of interrupt for event COMPARE[5]</description>
58356 <description>Read: Not pending</description>
58361 <description>Read: Pending</description>
58368 <description>Read pending status of interrupt for event COMPARE[6]</description>
58375 <description>Read: Not pending</description>
58380 <description>Read: Pending</description>
58387 <description>Read pending status of interrupt for event COMPARE[7]</description>
58394 <description>Read: Not pending</description>
58399 <description>Read: Pending</description>
58406 <description>Read pending status of interrupt for event COMPARE[8]</description>
58413 <description>Read: Not pending</description>
58418 <description>Read: Pending</description>
58425 <description>Read pending status of interrupt for event COMPARE[9]</description>
58432 <description>Read: Not pending</description>
58437 <description>Read: Pending</description>
58444 <description>Read pending status of interrupt for event COMPARE[10]</description>
58451 <description>Read: Not pending</description>
58456 <description>Read: Pending</description>
58463 <description>Read pending status of interrupt for event COMPARE[11]</description>
58470 <description>Read: Not pending</description>
58475 <description>Read: Pending</description>
58482 <description>Read pending status of interrupt for event COMPARE[12]</description>
58489 <description>Read: Not pending</description>
58494 <description>Read: Pending</description>
58501 <description>Read pending status of interrupt for event COMPARE[13]</description>
58508 <description>Read: Not pending</description>
58513 <description>Read: Pending</description>
58520 <description>Read pending status of interrupt for event COMPARE[14]</description>
58527 <description>Read: Not pending</description>
58532 <description>Read: Pending</description>
58539 <description>Read pending status of interrupt for event COMPARE[15]</description>
58546 <description>Read: Not pending</description>
58551 <description>Read: Pending</description>
58558 <description>Read pending status of interrupt for event RTCOMPARESYNC</description>
58565 <description>Read: Not pending</description>
58570 <description>Read: Pending</description>
58577 <description>Read pending status of interrupt for event PWMPERIODEND</description>
58584 <description>Read: Not pending</description>
58589 <description>Read: Pending</description>
58598 <description>Enable or disable interrupt</description>
58606 <description>Enable or disable interrupt for event COMPARE[0]</description>
58612 <description>Disable</description>
58617 <description>Enable</description>
58624 <description>Enable or disable interrupt for event COMPARE[1]</description>
58630 <description>Disable</description>
58635 <description>Enable</description>
58642 <description>Enable or disable interrupt for event COMPARE[2]</description>
58648 <description>Disable</description>
58653 <description>Enable</description>
58660 <description>Enable or disable interrupt for event COMPARE[3]</description>
58666 <description>Disable</description>
58671 <description>Enable</description>
58678 <description>Enable or disable interrupt for event COMPARE[4]</description>
58684 <description>Disable</description>
58689 <description>Enable</description>
58696 <description>Enable or disable interrupt for event COMPARE[5]</description>
58702 <description>Disable</description>
58707 <description>Enable</description>
58714 <description>Enable or disable interrupt for event COMPARE[6]</description>
58720 <description>Disable</description>
58725 <description>Enable</description>
58732 <description>Enable or disable interrupt for event COMPARE[7]</description>
58738 <description>Disable</description>
58743 <description>Enable</description>
58750 <description>Enable or disable interrupt for event COMPARE[8]</description>
58756 <description>Disable</description>
58761 <description>Enable</description>
58768 <description>Enable or disable interrupt for event COMPARE[9]</description>
58774 <description>Disable</description>
58779 <description>Enable</description>
58786 <description>Enable or disable interrupt for event COMPARE[10]</description>
58792 <description>Disable</description>
58797 <description>Enable</description>
58804 <description>Enable or disable interrupt for event COMPARE[11]</description>
58810 <description>Disable</description>
58815 <description>Enable</description>
58822 <description>Enable or disable interrupt for event COMPARE[12]</description>
58828 <description>Disable</description>
58833 <description>Enable</description>
58840 <description>Enable or disable interrupt for event COMPARE[13]</description>
58846 <description>Disable</description>
58851 <description>Enable</description>
58858 <description>Enable or disable interrupt for event COMPARE[14]</description>
58864 <description>Disable</description>
58869 <description>Enable</description>
58876 <description>Enable or disable interrupt for event COMPARE[15]</description>
58882 <description>Disable</description>
58887 <description>Enable</description>
58894 <description>Enable or disable interrupt for event RTCOMPARESYNC</description>
58900 <description>Disable</description>
58905 <description>Enable</description>
58912 <description>Enable or disable interrupt for event PWMPERIODEND</description>
58918 <description>Disable</description>
58923 <description>Enable</description>
58932 <description>Enable interrupt</description>
58940 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
58947 <description>Read: Disabled</description>
58952 <description>Read: Enabled</description>
58960 <description>Enable</description>
58967 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
58974 <description>Read: Disabled</description>
58979 <description>Read: Enabled</description>
58987 <description>Enable</description>
58994 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
59001 <description>Read: Disabled</description>
59006 <description>Read: Enabled</description>
59014 <description>Enable</description>
59021 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
59028 <description>Read: Disabled</description>
59033 <description>Read: Enabled</description>
59041 <description>Enable</description>
59048 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
59055 <description>Read: Disabled</description>
59060 <description>Read: Enabled</description>
59068 <description>Enable</description>
59075 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
59082 <description>Read: Disabled</description>
59087 <description>Read: Enabled</description>
59095 <description>Enable</description>
59102 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
59109 <description>Read: Disabled</description>
59114 <description>Read: Enabled</description>
59122 <description>Enable</description>
59129 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
59136 <description>Read: Disabled</description>
59141 <description>Read: Enabled</description>
59149 <description>Enable</description>
59156 <description>Write '1' to enable interrupt for event COMPARE[8]</description>
59163 <description>Read: Disabled</description>
59168 <description>Read: Enabled</description>
59176 <description>Enable</description>
59183 <description>Write '1' to enable interrupt for event COMPARE[9]</description>
59190 <description>Read: Disabled</description>
59195 <description>Read: Enabled</description>
59203 <description>Enable</description>
59210 <description>Write '1' to enable interrupt for event COMPARE[10]</description>
59217 <description>Read: Disabled</description>
59222 <description>Read: Enabled</description>
59230 <description>Enable</description>
59237 <description>Write '1' to enable interrupt for event COMPARE[11]</description>
59244 <description>Read: Disabled</description>
59249 <description>Read: Enabled</description>
59257 <description>Enable</description>
59264 <description>Write '1' to enable interrupt for event COMPARE[12]</description>
59271 <description>Read: Disabled</description>
59276 <description>Read: Enabled</description>
59284 <description>Enable</description>
59291 <description>Write '1' to enable interrupt for event COMPARE[13]</description>
59298 <description>Read: Disabled</description>
59303 <description>Read: Enabled</description>
59311 <description>Enable</description>
59318 <description>Write '1' to enable interrupt for event COMPARE[14]</description>
59325 <description>Read: Disabled</description>
59330 <description>Read: Enabled</description>
59338 <description>Enable</description>
59345 <description>Write '1' to enable interrupt for event COMPARE[15]</description>
59352 <description>Read: Disabled</description>
59357 <description>Read: Enabled</description>
59365 <description>Enable</description>
59372 <description>Write '1' to enable interrupt for event RTCOMPARESYNC</description>
59379 <description>Read: Disabled</description>
59384 <description>Read: Enabled</description>
59392 <description>Enable</description>
59399 <description>Write '1' to enable interrupt for event PWMPERIODEND</description>
59406 <description>Read: Disabled</description>
59411 <description>Read: Enabled</description>
59419 <description>Enable</description>
59428 <description>Disable interrupt</description>
59436 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
59443 <description>Read: Disabled</description>
59448 <description>Read: Enabled</description>
59456 <description>Disable</description>
59463 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
59470 <description>Read: Disabled</description>
59475 <description>Read: Enabled</description>
59483 <description>Disable</description>
59490 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
59497 <description>Read: Disabled</description>
59502 <description>Read: Enabled</description>
59510 <description>Disable</description>
59517 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
59524 <description>Read: Disabled</description>
59529 <description>Read: Enabled</description>
59537 <description>Disable</description>
59544 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
59551 <description>Read: Disabled</description>
59556 <description>Read: Enabled</description>
59564 <description>Disable</description>
59571 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
59578 <description>Read: Disabled</description>
59583 <description>Read: Enabled</description>
59591 <description>Disable</description>
59598 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
59605 <description>Read: Disabled</description>
59610 <description>Read: Enabled</description>
59618 <description>Disable</description>
59625 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
59632 <description>Read: Disabled</description>
59637 <description>Read: Enabled</description>
59645 <description>Disable</description>
59652 <description>Write '1' to disable interrupt for event COMPARE[8]</description>
59659 <description>Read: Disabled</description>
59664 <description>Read: Enabled</description>
59672 <description>Disable</description>
59679 <description>Write '1' to disable interrupt for event COMPARE[9]</description>
59686 <description>Read: Disabled</description>
59691 <description>Read: Enabled</description>
59699 <description>Disable</description>
59706 <description>Write '1' to disable interrupt for event COMPARE[10]</description>
59713 <description>Read: Disabled</description>
59718 <description>Read: Enabled</description>
59726 <description>Disable</description>
59733 <description>Write '1' to disable interrupt for event COMPARE[11]</description>
59740 <description>Read: Disabled</description>
59745 <description>Read: Enabled</description>
59753 <description>Disable</description>
59760 <description>Write '1' to disable interrupt for event COMPARE[12]</description>
59767 <description>Read: Disabled</description>
59772 <description>Read: Enabled</description>
59780 <description>Disable</description>
59787 <description>Write '1' to disable interrupt for event COMPARE[13]</description>
59794 <description>Read: Disabled</description>
59799 <description>Read: Enabled</description>
59807 <description>Disable</description>
59814 <description>Write '1' to disable interrupt for event COMPARE[14]</description>
59821 <description>Read: Disabled</description>
59826 <description>Read: Enabled</description>
59834 <description>Disable</description>
59841 <description>Write '1' to disable interrupt for event COMPARE[15]</description>
59848 <description>Read: Disabled</description>
59853 <description>Read: Enabled</description>
59861 <description>Disable</description>
59868 <description>Write '1' to disable interrupt for event RTCOMPARESYNC</description>
59875 <description>Read: Disabled</description>
59880 <description>Read: Enabled</description>
59888 <description>Disable</description>
59895 <description>Write '1' to disable interrupt for event PWMPERIODEND</description>
59902 <description>Read: Disabled</description>
59907 <description>Read: Enabled</description>
59915 <description>Disable</description>
59924 <description>Pending interrupts</description>
59932 <description>Read pending status of interrupt for event COMPARE[0]</description>
59939 <description>Read: Not pending</description>
59944 <description>Read: Pending</description>
59951 <description>Read pending status of interrupt for event COMPARE[1]</description>
59958 <description>Read: Not pending</description>
59963 <description>Read: Pending</description>
59970 <description>Read pending status of interrupt for event COMPARE[2]</description>
59977 <description>Read: Not pending</description>
59982 <description>Read: Pending</description>
59989 <description>Read pending status of interrupt for event COMPARE[3]</description>
59996 <description>Read: Not pending</description>
60001 <description>Read: Pending</description>
60008 <description>Read pending status of interrupt for event COMPARE[4]</description>
60015 <description>Read: Not pending</description>
60020 <description>Read: Pending</description>
60027 <description>Read pending status of interrupt for event COMPARE[5]</description>
60034 <description>Read: Not pending</description>
60039 <description>Read: Pending</description>
60046 <description>Read pending status of interrupt for event COMPARE[6]</description>
60053 <description>Read: Not pending</description>
60058 <description>Read: Pending</description>
60065 <description>Read pending status of interrupt for event COMPARE[7]</description>
60072 <description>Read: Not pending</description>
60077 <description>Read: Pending</description>
60084 <description>Read pending status of interrupt for event COMPARE[8]</description>
60091 <description>Read: Not pending</description>
60096 <description>Read: Pending</description>
60103 <description>Read pending status of interrupt for event COMPARE[9]</description>
60110 <description>Read: Not pending</description>
60115 <description>Read: Pending</description>
60122 <description>Read pending status of interrupt for event COMPARE[10]</description>
60129 <description>Read: Not pending</description>
60134 <description>Read: Pending</description>
60141 <description>Read pending status of interrupt for event COMPARE[11]</description>
60148 <description>Read: Not pending</description>
60153 <description>Read: Pending</description>
60160 <description>Read pending status of interrupt for event COMPARE[12]</description>
60167 <description>Read: Not pending</description>
60172 <description>Read: Pending</description>
60179 <description>Read pending status of interrupt for event COMPARE[13]</description>
60186 <description>Read: Not pending</description>
60191 <description>Read: Pending</description>
60198 <description>Read pending status of interrupt for event COMPARE[14]</description>
60205 <description>Read: Not pending</description>
60210 <description>Read: Pending</description>
60217 <description>Read pending status of interrupt for event COMPARE[15]</description>
60224 <description>Read: Not pending</description>
60229 <description>Read: Pending</description>
60236 <description>Read pending status of interrupt for event RTCOMPARESYNC</description>
60243 <description>Read: Not pending</description>
60248 <description>Read: Pending</description>
60255 <description>Read pending status of interrupt for event PWMPERIODEND</description>
60262 <description>Read: Not pending</description>
60267 <description>Read: Pending</description>
60276 <description>Enable or disable interrupt</description>
60284 <description>Enable or disable interrupt for event COMPARE[0]</description>
60290 <description>Disable</description>
60295 <description>Enable</description>
60302 <description>Enable or disable interrupt for event COMPARE[1]</description>
60308 <description>Disable</description>
60313 <description>Enable</description>
60320 <description>Enable or disable interrupt for event COMPARE[2]</description>
60326 <description>Disable</description>
60331 <description>Enable</description>
60338 <description>Enable or disable interrupt for event COMPARE[3]</description>
60344 <description>Disable</description>
60349 <description>Enable</description>
60356 <description>Enable or disable interrupt for event COMPARE[4]</description>
60362 <description>Disable</description>
60367 <description>Enable</description>
60374 <description>Enable or disable interrupt for event COMPARE[5]</description>
60380 <description>Disable</description>
60385 <description>Enable</description>
60392 <description>Enable or disable interrupt for event COMPARE[6]</description>
60398 <description>Disable</description>
60403 <description>Enable</description>
60410 <description>Enable or disable interrupt for event COMPARE[7]</description>
60416 <description>Disable</description>
60421 <description>Enable</description>
60428 <description>Enable or disable interrupt for event COMPARE[8]</description>
60434 <description>Disable</description>
60439 <description>Enable</description>
60446 <description>Enable or disable interrupt for event COMPARE[9]</description>
60452 <description>Disable</description>
60457 <description>Enable</description>
60464 <description>Enable or disable interrupt for event COMPARE[10]</description>
60470 <description>Disable</description>
60475 <description>Enable</description>
60482 <description>Enable or disable interrupt for event COMPARE[11]</description>
60488 <description>Disable</description>
60493 <description>Enable</description>
60500 <description>Enable or disable interrupt for event COMPARE[12]</description>
60506 <description>Disable</description>
60511 <description>Enable</description>
60518 <description>Enable or disable interrupt for event COMPARE[13]</description>
60524 <description>Disable</description>
60529 <description>Enable</description>
60536 <description>Enable or disable interrupt for event COMPARE[14]</description>
60542 <description>Disable</description>
60547 <description>Enable</description>
60554 <description>Enable or disable interrupt for event COMPARE[15]</description>
60560 <description>Disable</description>
60565 <description>Enable</description>
60572 <description>Enable or disable interrupt for event RTCOMPARESYNC</description>
60578 <description>Disable</description>
60583 <description>Enable</description>
60590 <description>Enable or disable interrupt for event PWMPERIODEND</description>
60596 <description>Disable</description>
60601 <description>Enable</description>
60610 <description>Enable interrupt</description>
60618 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
60625 <description>Read: Disabled</description>
60630 <description>Read: Enabled</description>
60638 <description>Enable</description>
60645 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
60652 <description>Read: Disabled</description>
60657 <description>Read: Enabled</description>
60665 <description>Enable</description>
60672 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
60679 <description>Read: Disabled</description>
60684 <description>Read: Enabled</description>
60692 <description>Enable</description>
60699 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
60706 <description>Read: Disabled</description>
60711 <description>Read: Enabled</description>
60719 <description>Enable</description>
60726 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
60733 <description>Read: Disabled</description>
60738 <description>Read: Enabled</description>
60746 <description>Enable</description>
60753 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
60760 <description>Read: Disabled</description>
60765 <description>Read: Enabled</description>
60773 <description>Enable</description>
60780 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
60787 <description>Read: Disabled</description>
60792 <description>Read: Enabled</description>
60800 <description>Enable</description>
60807 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
60814 <description>Read: Disabled</description>
60819 <description>Read: Enabled</description>
60827 <description>Enable</description>
60834 <description>Write '1' to enable interrupt for event COMPARE[8]</description>
60841 <description>Read: Disabled</description>
60846 <description>Read: Enabled</description>
60854 <description>Enable</description>
60861 <description>Write '1' to enable interrupt for event COMPARE[9]</description>
60868 <description>Read: Disabled</description>
60873 <description>Read: Enabled</description>
60881 <description>Enable</description>
60888 <description>Write '1' to enable interrupt for event COMPARE[10]</description>
60895 <description>Read: Disabled</description>
60900 <description>Read: Enabled</description>
60908 <description>Enable</description>
60915 <description>Write '1' to enable interrupt for event COMPARE[11]</description>
60922 <description>Read: Disabled</description>
60927 <description>Read: Enabled</description>
60935 <description>Enable</description>
60942 <description>Write '1' to enable interrupt for event COMPARE[12]</description>
60949 <description>Read: Disabled</description>
60954 <description>Read: Enabled</description>
60962 <description>Enable</description>
60969 <description>Write '1' to enable interrupt for event COMPARE[13]</description>
60976 <description>Read: Disabled</description>
60981 <description>Read: Enabled</description>
60989 <description>Enable</description>
60996 <description>Write '1' to enable interrupt for event COMPARE[14]</description>
61003 <description>Read: Disabled</description>
61008 <description>Read: Enabled</description>
61016 <description>Enable</description>
61023 <description>Write '1' to enable interrupt for event COMPARE[15]</description>
61030 <description>Read: Disabled</description>
61035 <description>Read: Enabled</description>
61043 <description>Enable</description>
61050 <description>Write '1' to enable interrupt for event RTCOMPARESYNC</description>
61057 <description>Read: Disabled</description>
61062 <description>Read: Enabled</description>
61070 <description>Enable</description>
61077 <description>Write '1' to enable interrupt for event PWMPERIODEND</description>
61084 <description>Read: Disabled</description>
61089 <description>Read: Enabled</description>
61097 <description>Enable</description>
61106 <description>Disable interrupt</description>
61114 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
61121 <description>Read: Disabled</description>
61126 <description>Read: Enabled</description>
61134 <description>Disable</description>
61141 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
61148 <description>Read: Disabled</description>
61153 <description>Read: Enabled</description>
61161 <description>Disable</description>
61168 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
61175 <description>Read: Disabled</description>
61180 <description>Read: Enabled</description>
61188 <description>Disable</description>
61195 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
61202 <description>Read: Disabled</description>
61207 <description>Read: Enabled</description>
61215 <description>Disable</description>
61222 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
61229 <description>Read: Disabled</description>
61234 <description>Read: Enabled</description>
61242 <description>Disable</description>
61249 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
61256 <description>Read: Disabled</description>
61261 <description>Read: Enabled</description>
61269 <description>Disable</description>
61276 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
61283 <description>Read: Disabled</description>
61288 <description>Read: Enabled</description>
61296 <description>Disable</description>
61303 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
61310 <description>Read: Disabled</description>
61315 <description>Read: Enabled</description>
61323 <description>Disable</description>
61330 <description>Write '1' to disable interrupt for event COMPARE[8]</description>
61337 <description>Read: Disabled</description>
61342 <description>Read: Enabled</description>
61350 <description>Disable</description>
61357 <description>Write '1' to disable interrupt for event COMPARE[9]</description>
61364 <description>Read: Disabled</description>
61369 <description>Read: Enabled</description>
61377 <description>Disable</description>
61384 <description>Write '1' to disable interrupt for event COMPARE[10]</description>
61391 <description>Read: Disabled</description>
61396 <description>Read: Enabled</description>
61404 <description>Disable</description>
61411 <description>Write '1' to disable interrupt for event COMPARE[11]</description>
61418 <description>Read: Disabled</description>
61423 <description>Read: Enabled</description>
61431 <description>Disable</description>
61438 <description>Write '1' to disable interrupt for event COMPARE[12]</description>
61445 <description>Read: Disabled</description>
61450 <description>Read: Enabled</description>
61458 <description>Disable</description>
61465 <description>Write '1' to disable interrupt for event COMPARE[13]</description>
61472 <description>Read: Disabled</description>
61477 <description>Read: Enabled</description>
61485 <description>Disable</description>
61492 <description>Write '1' to disable interrupt for event COMPARE[14]</description>
61499 <description>Read: Disabled</description>
61504 <description>Read: Enabled</description>
61512 <description>Disable</description>
61519 <description>Write '1' to disable interrupt for event COMPARE[15]</description>
61526 <description>Read: Disabled</description>
61531 <description>Read: Enabled</description>
61539 <description>Disable</description>
61546 <description>Write '1' to disable interrupt for event RTCOMPARESYNC</description>
61553 <description>Read: Disabled</description>
61558 <description>Read: Enabled</description>
61566 <description>Disable</description>
61573 <description>Write '1' to disable interrupt for event PWMPERIODEND</description>
61580 <description>Read: Disabled</description>
61585 <description>Read: Enabled</description>
61593 <description>Disable</description>
61602 <description>Pending interrupts</description>
61610 <description>Read pending status of interrupt for event COMPARE[0]</description>
61617 <description>Read: Not pending</description>
61622 <description>Read: Pending</description>
61629 <description>Read pending status of interrupt for event COMPARE[1]</description>
61636 <description>Read: Not pending</description>
61641 <description>Read: Pending</description>
61648 <description>Read pending status of interrupt for event COMPARE[2]</description>
61655 <description>Read: Not pending</description>
61660 <description>Read: Pending</description>
61667 <description>Read pending status of interrupt for event COMPARE[3]</description>
61674 <description>Read: Not pending</description>
61679 <description>Read: Pending</description>
61686 <description>Read pending status of interrupt for event COMPARE[4]</description>
61693 <description>Read: Not pending</description>
61698 <description>Read: Pending</description>
61705 <description>Read pending status of interrupt for event COMPARE[5]</description>
61712 <description>Read: Not pending</description>
61717 <description>Read: Pending</description>
61724 <description>Read pending status of interrupt for event COMPARE[6]</description>
61731 <description>Read: Not pending</description>
61736 <description>Read: Pending</description>
61743 <description>Read pending status of interrupt for event COMPARE[7]</description>
61750 <description>Read: Not pending</description>
61755 <description>Read: Pending</description>
61762 <description>Read pending status of interrupt for event COMPARE[8]</description>
61769 <description>Read: Not pending</description>
61774 <description>Read: Pending</description>
61781 <description>Read pending status of interrupt for event COMPARE[9]</description>
61788 <description>Read: Not pending</description>
61793 <description>Read: Pending</description>
61800 <description>Read pending status of interrupt for event COMPARE[10]</description>
61807 <description>Read: Not pending</description>
61812 <description>Read: Pending</description>
61819 <description>Read pending status of interrupt for event COMPARE[11]</description>
61826 <description>Read: Not pending</description>
61831 <description>Read: Pending</description>
61838 <description>Read pending status of interrupt for event COMPARE[12]</description>
61845 <description>Read: Not pending</description>
61850 <description>Read: Pending</description>
61857 <description>Read pending status of interrupt for event COMPARE[13]</description>
61864 <description>Read: Not pending</description>
61869 <description>Read: Pending</description>
61876 <description>Read pending status of interrupt for event COMPARE[14]</description>
61883 <description>Read: Not pending</description>
61888 <description>Read: Pending</description>
61895 <description>Read pending status of interrupt for event COMPARE[15]</description>
61902 <description>Read: Not pending</description>
61907 <description>Read: Pending</description>
61914 <description>Read pending status of interrupt for event RTCOMPARESYNC</description>
61921 <description>Read: Not pending</description>
61926 <description>Read: Pending</description>
61933 <description>Read pending status of interrupt for event PWMPERIODEND</description>
61940 <description>Read: Not pending</description>
61945 <description>Read: Pending</description>
61954 <description>Enable or disable interrupt</description>
61962 <description>Enable or disable interrupt for event COMPARE[0]</description>
61968 <description>Disable</description>
61973 <description>Enable</description>
61980 <description>Enable or disable interrupt for event COMPARE[1]</description>
61986 <description>Disable</description>
61991 <description>Enable</description>
61998 <description>Enable or disable interrupt for event COMPARE[2]</description>
62004 <description>Disable</description>
62009 <description>Enable</description>
62016 <description>Enable or disable interrupt for event COMPARE[3]</description>
62022 <description>Disable</description>
62027 <description>Enable</description>
62034 <description>Enable or disable interrupt for event COMPARE[4]</description>
62040 <description>Disable</description>
62045 <description>Enable</description>
62052 <description>Enable or disable interrupt for event COMPARE[5]</description>
62058 <description>Disable</description>
62063 <description>Enable</description>
62070 <description>Enable or disable interrupt for event COMPARE[6]</description>
62076 <description>Disable</description>
62081 <description>Enable</description>
62088 <description>Enable or disable interrupt for event COMPARE[7]</description>
62094 <description>Disable</description>
62099 <description>Enable</description>
62106 <description>Enable or disable interrupt for event COMPARE[8]</description>
62112 <description>Disable</description>
62117 <description>Enable</description>
62124 <description>Enable or disable interrupt for event COMPARE[9]</description>
62130 <description>Disable</description>
62135 <description>Enable</description>
62142 <description>Enable or disable interrupt for event COMPARE[10]</description>
62148 <description>Disable</description>
62153 <description>Enable</description>
62160 <description>Enable or disable interrupt for event COMPARE[11]</description>
62166 <description>Disable</description>
62171 <description>Enable</description>
62178 <description>Enable or disable interrupt for event COMPARE[12]</description>
62184 <description>Disable</description>
62189 <description>Enable</description>
62196 <description>Enable or disable interrupt for event COMPARE[13]</description>
62202 <description>Disable</description>
62207 <description>Enable</description>
62214 <description>Enable or disable interrupt for event COMPARE[14]</description>
62220 <description>Disable</description>
62225 <description>Enable</description>
62232 <description>Enable or disable interrupt for event COMPARE[15]</description>
62238 <description>Disable</description>
62243 <description>Enable</description>
62250 <description>Enable or disable interrupt for event RTCOMPARESYNC</description>
62256 <description>Disable</description>
62261 <description>Enable</description>
62268 <description>Enable or disable interrupt for event PWMPERIODEND</description>
62274 <description>Disable</description>
62279 <description>Enable</description>
62288 <description>Enable interrupt</description>
62296 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
62303 <description>Read: Disabled</description>
62308 <description>Read: Enabled</description>
62316 <description>Enable</description>
62323 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
62330 <description>Read: Disabled</description>
62335 <description>Read: Enabled</description>
62343 <description>Enable</description>
62350 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
62357 <description>Read: Disabled</description>
62362 <description>Read: Enabled</description>
62370 <description>Enable</description>
62377 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
62384 <description>Read: Disabled</description>
62389 <description>Read: Enabled</description>
62397 <description>Enable</description>
62404 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
62411 <description>Read: Disabled</description>
62416 <description>Read: Enabled</description>
62424 <description>Enable</description>
62431 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
62438 <description>Read: Disabled</description>
62443 <description>Read: Enabled</description>
62451 <description>Enable</description>
62458 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
62465 <description>Read: Disabled</description>
62470 <description>Read: Enabled</description>
62478 <description>Enable</description>
62485 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
62492 <description>Read: Disabled</description>
62497 <description>Read: Enabled</description>
62505 <description>Enable</description>
62512 <description>Write '1' to enable interrupt for event COMPARE[8]</description>
62519 <description>Read: Disabled</description>
62524 <description>Read: Enabled</description>
62532 <description>Enable</description>
62539 <description>Write '1' to enable interrupt for event COMPARE[9]</description>
62546 <description>Read: Disabled</description>
62551 <description>Read: Enabled</description>
62559 <description>Enable</description>
62566 <description>Write '1' to enable interrupt for event COMPARE[10]</description>
62573 <description>Read: Disabled</description>
62578 <description>Read: Enabled</description>
62586 <description>Enable</description>
62593 <description>Write '1' to enable interrupt for event COMPARE[11]</description>
62600 <description>Read: Disabled</description>
62605 <description>Read: Enabled</description>
62613 <description>Enable</description>
62620 <description>Write '1' to enable interrupt for event COMPARE[12]</description>
62627 <description>Read: Disabled</description>
62632 <description>Read: Enabled</description>
62640 <description>Enable</description>
62647 <description>Write '1' to enable interrupt for event COMPARE[13]</description>
62654 <description>Read: Disabled</description>
62659 <description>Read: Enabled</description>
62667 <description>Enable</description>
62674 <description>Write '1' to enable interrupt for event COMPARE[14]</description>
62681 <description>Read: Disabled</description>
62686 <description>Read: Enabled</description>
62694 <description>Enable</description>
62701 <description>Write '1' to enable interrupt for event COMPARE[15]</description>
62708 <description>Read: Disabled</description>
62713 <description>Read: Enabled</description>
62721 <description>Enable</description>
62728 <description>Write '1' to enable interrupt for event RTCOMPARESYNC</description>
62735 <description>Read: Disabled</description>
62740 <description>Read: Enabled</description>
62748 <description>Enable</description>
62755 <description>Write '1' to enable interrupt for event PWMPERIODEND</description>
62762 <description>Read: Disabled</description>
62767 <description>Read: Enabled</description>
62775 <description>Enable</description>
62784 <description>Disable interrupt</description>
62792 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
62799 <description>Read: Disabled</description>
62804 <description>Read: Enabled</description>
62812 <description>Disable</description>
62819 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
62826 <description>Read: Disabled</description>
62831 <description>Read: Enabled</description>
62839 <description>Disable</description>
62846 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
62853 <description>Read: Disabled</description>
62858 <description>Read: Enabled</description>
62866 <description>Disable</description>
62873 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
62880 <description>Read: Disabled</description>
62885 <description>Read: Enabled</description>
62893 <description>Disable</description>
62900 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
62907 <description>Read: Disabled</description>
62912 <description>Read: Enabled</description>
62920 <description>Disable</description>
62927 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
62934 <description>Read: Disabled</description>
62939 <description>Read: Enabled</description>
62947 <description>Disable</description>
62954 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
62961 <description>Read: Disabled</description>
62966 <description>Read: Enabled</description>
62974 <description>Disable</description>
62981 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
62988 <description>Read: Disabled</description>
62993 <description>Read: Enabled</description>
63001 <description>Disable</description>
63008 <description>Write '1' to disable interrupt for event COMPARE[8]</description>
63015 <description>Read: Disabled</description>
63020 <description>Read: Enabled</description>
63028 <description>Disable</description>
63035 <description>Write '1' to disable interrupt for event COMPARE[9]</description>
63042 <description>Read: Disabled</description>
63047 <description>Read: Enabled</description>
63055 <description>Disable</description>
63062 <description>Write '1' to disable interrupt for event COMPARE[10]</description>
63069 <description>Read: Disabled</description>
63074 <description>Read: Enabled</description>
63082 <description>Disable</description>
63089 <description>Write '1' to disable interrupt for event COMPARE[11]</description>
63096 <description>Read: Disabled</description>
63101 <description>Read: Enabled</description>
63109 <description>Disable</description>
63116 <description>Write '1' to disable interrupt for event COMPARE[12]</description>
63123 <description>Read: Disabled</description>
63128 <description>Read: Enabled</description>
63136 <description>Disable</description>
63143 <description>Write '1' to disable interrupt for event COMPARE[13]</description>
63150 <description>Read: Disabled</description>
63155 <description>Read: Enabled</description>
63163 <description>Disable</description>
63170 <description>Write '1' to disable interrupt for event COMPARE[14]</description>
63177 <description>Read: Disabled</description>
63182 <description>Read: Enabled</description>
63190 <description>Disable</description>
63197 <description>Write '1' to disable interrupt for event COMPARE[15]</description>
63204 <description>Read: Disabled</description>
63209 <description>Read: Enabled</description>
63217 <description>Disable</description>
63224 <description>Write '1' to disable interrupt for event RTCOMPARESYNC</description>
63231 <description>Read: Disabled</description>
63236 <description>Read: Enabled</description>
63244 <description>Disable</description>
63251 <description>Write '1' to disable interrupt for event PWMPERIODEND</description>
63258 <description>Read: Disabled</description>
63263 <description>Read: Enabled</description>
63271 <description>Disable</description>
63280 <description>Pending interrupts</description>
63288 <description>Read pending status of interrupt for event COMPARE[0]</description>
63295 <description>Read: Not pending</description>
63300 <description>Read: Pending</description>
63307 <description>Read pending status of interrupt for event COMPARE[1]</description>
63314 <description>Read: Not pending</description>
63319 <description>Read: Pending</description>
63326 <description>Read pending status of interrupt for event COMPARE[2]</description>
63333 <description>Read: Not pending</description>
63338 <description>Read: Pending</description>
63345 <description>Read pending status of interrupt for event COMPARE[3]</description>
63352 <description>Read: Not pending</description>
63357 <description>Read: Pending</description>
63364 <description>Read pending status of interrupt for event COMPARE[4]</description>
63371 <description>Read: Not pending</description>
63376 <description>Read: Pending</description>
63383 <description>Read pending status of interrupt for event COMPARE[5]</description>
63390 <description>Read: Not pending</description>
63395 <description>Read: Pending</description>
63402 <description>Read pending status of interrupt for event COMPARE[6]</description>
63409 <description>Read: Not pending</description>
63414 <description>Read: Pending</description>
63421 <description>Read pending status of interrupt for event COMPARE[7]</description>
63428 <description>Read: Not pending</description>
63433 <description>Read: Pending</description>
63440 <description>Read pending status of interrupt for event COMPARE[8]</description>
63447 <description>Read: Not pending</description>
63452 <description>Read: Pending</description>
63459 <description>Read pending status of interrupt for event COMPARE[9]</description>
63466 <description>Read: Not pending</description>
63471 <description>Read: Pending</description>
63478 <description>Read pending status of interrupt for event COMPARE[10]</description>
63485 <description>Read: Not pending</description>
63490 <description>Read: Pending</description>
63497 <description>Read pending status of interrupt for event COMPARE[11]</description>
63504 <description>Read: Not pending</description>
63509 <description>Read: Pending</description>
63516 <description>Read pending status of interrupt for event COMPARE[12]</description>
63523 <description>Read: Not pending</description>
63528 <description>Read: Pending</description>
63535 <description>Read pending status of interrupt for event COMPARE[13]</description>
63542 <description>Read: Not pending</description>
63547 <description>Read: Pending</description>
63554 <description>Read pending status of interrupt for event COMPARE[14]</description>
63561 <description>Read: Not pending</description>
63566 <description>Read: Pending</description>
63573 <description>Read pending status of interrupt for event COMPARE[15]</description>
63580 <description>Read: Not pending</description>
63585 <description>Read: Pending</description>
63592 <description>Read pending status of interrupt for event RTCOMPARESYNC</description>
63599 <description>Read: Not pending</description>
63604 <description>Read: Pending</description>
63611 <description>Read pending status of interrupt for event PWMPERIODEND</description>
63618 <description>Read: Not pending</description>
63623 <description>Read: Pending</description>
63632 <description>Enable or disable interrupt</description>
63640 <description>Enable or disable interrupt for event COMPARE[0]</description>
63646 <description>Disable</description>
63651 <description>Enable</description>
63658 <description>Enable or disable interrupt for event COMPARE[1]</description>
63664 <description>Disable</description>
63669 <description>Enable</description>
63676 <description>Enable or disable interrupt for event COMPARE[2]</description>
63682 <description>Disable</description>
63687 <description>Enable</description>
63694 <description>Enable or disable interrupt for event COMPARE[3]</description>
63700 <description>Disable</description>
63705 <description>Enable</description>
63712 <description>Enable or disable interrupt for event COMPARE[4]</description>
63718 <description>Disable</description>
63723 <description>Enable</description>
63730 <description>Enable or disable interrupt for event COMPARE[5]</description>
63736 <description>Disable</description>
63741 <description>Enable</description>
63748 <description>Enable or disable interrupt for event COMPARE[6]</description>
63754 <description>Disable</description>
63759 <description>Enable</description>
63766 <description>Enable or disable interrupt for event COMPARE[7]</description>
63772 <description>Disable</description>
63777 <description>Enable</description>
63784 <description>Enable or disable interrupt for event COMPARE[8]</description>
63790 <description>Disable</description>
63795 <description>Enable</description>
63802 <description>Enable or disable interrupt for event COMPARE[9]</description>
63808 <description>Disable</description>
63813 <description>Enable</description>
63820 <description>Enable or disable interrupt for event COMPARE[10]</description>
63826 <description>Disable</description>
63831 <description>Enable</description>
63838 <description>Enable or disable interrupt for event COMPARE[11]</description>
63844 <description>Disable</description>
63849 <description>Enable</description>
63856 <description>Enable or disable interrupt for event COMPARE[12]</description>
63862 <description>Disable</description>
63867 <description>Enable</description>
63874 <description>Enable or disable interrupt for event COMPARE[13]</description>
63880 <description>Disable</description>
63885 <description>Enable</description>
63892 <description>Enable or disable interrupt for event COMPARE[14]</description>
63898 <description>Disable</description>
63903 <description>Enable</description>
63910 <description>Enable or disable interrupt for event COMPARE[15]</description>
63916 <description>Disable</description>
63921 <description>Enable</description>
63928 <description>Enable or disable interrupt for event RTCOMPARESYNC</description>
63934 <description>Disable</description>
63939 <description>Enable</description>
63946 <description>Enable or disable interrupt for event PWMPERIODEND</description>
63952 <description>Disable</description>
63957 <description>Enable</description>
63966 <description>Enable interrupt</description>
63974 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
63981 <description>Read: Disabled</description>
63986 <description>Read: Enabled</description>
63994 <description>Enable</description>
64001 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
64008 <description>Read: Disabled</description>
64013 <description>Read: Enabled</description>
64021 <description>Enable</description>
64028 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
64035 <description>Read: Disabled</description>
64040 <description>Read: Enabled</description>
64048 <description>Enable</description>
64055 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
64062 <description>Read: Disabled</description>
64067 <description>Read: Enabled</description>
64075 <description>Enable</description>
64082 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
64089 <description>Read: Disabled</description>
64094 <description>Read: Enabled</description>
64102 <description>Enable</description>
64109 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
64116 <description>Read: Disabled</description>
64121 <description>Read: Enabled</description>
64129 <description>Enable</description>
64136 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
64143 <description>Read: Disabled</description>
64148 <description>Read: Enabled</description>
64156 <description>Enable</description>
64163 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
64170 <description>Read: Disabled</description>
64175 <description>Read: Enabled</description>
64183 <description>Enable</description>
64190 <description>Write '1' to enable interrupt for event COMPARE[8]</description>
64197 <description>Read: Disabled</description>
64202 <description>Read: Enabled</description>
64210 <description>Enable</description>
64217 <description>Write '1' to enable interrupt for event COMPARE[9]</description>
64224 <description>Read: Disabled</description>
64229 <description>Read: Enabled</description>
64237 <description>Enable</description>
64244 <description>Write '1' to enable interrupt for event COMPARE[10]</description>
64251 <description>Read: Disabled</description>
64256 <description>Read: Enabled</description>
64264 <description>Enable</description>
64271 <description>Write '1' to enable interrupt for event COMPARE[11]</description>
64278 <description>Read: Disabled</description>
64283 <description>Read: Enabled</description>
64291 <description>Enable</description>
64298 <description>Write '1' to enable interrupt for event COMPARE[12]</description>
64305 <description>Read: Disabled</description>
64310 <description>Read: Enabled</description>
64318 <description>Enable</description>
64325 <description>Write '1' to enable interrupt for event COMPARE[13]</description>
64332 <description>Read: Disabled</description>
64337 <description>Read: Enabled</description>
64345 <description>Enable</description>
64352 <description>Write '1' to enable interrupt for event COMPARE[14]</description>
64359 <description>Read: Disabled</description>
64364 <description>Read: Enabled</description>
64372 <description>Enable</description>
64379 <description>Write '1' to enable interrupt for event COMPARE[15]</description>
64386 <description>Read: Disabled</description>
64391 <description>Read: Enabled</description>
64399 <description>Enable</description>
64406 <description>Write '1' to enable interrupt for event RTCOMPARESYNC</description>
64413 <description>Read: Disabled</description>
64418 <description>Read: Enabled</description>
64426 <description>Enable</description>
64433 <description>Write '1' to enable interrupt for event PWMPERIODEND</description>
64440 <description>Read: Disabled</description>
64445 <description>Read: Enabled</description>
64453 <description>Enable</description>
64462 <description>Disable interrupt</description>
64470 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
64477 <description>Read: Disabled</description>
64482 <description>Read: Enabled</description>
64490 <description>Disable</description>
64497 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
64504 <description>Read: Disabled</description>
64509 <description>Read: Enabled</description>
64517 <description>Disable</description>
64524 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
64531 <description>Read: Disabled</description>
64536 <description>Read: Enabled</description>
64544 <description>Disable</description>
64551 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
64558 <description>Read: Disabled</description>
64563 <description>Read: Enabled</description>
64571 <description>Disable</description>
64578 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
64585 <description>Read: Disabled</description>
64590 <description>Read: Enabled</description>
64598 <description>Disable</description>
64605 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
64612 <description>Read: Disabled</description>
64617 <description>Read: Enabled</description>
64625 <description>Disable</description>
64632 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
64639 <description>Read: Disabled</description>
64644 <description>Read: Enabled</description>
64652 <description>Disable</description>
64659 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
64666 <description>Read: Disabled</description>
64671 <description>Read: Enabled</description>
64679 <description>Disable</description>
64686 <description>Write '1' to disable interrupt for event COMPARE[8]</description>
64693 <description>Read: Disabled</description>
64698 <description>Read: Enabled</description>
64706 <description>Disable</description>
64713 <description>Write '1' to disable interrupt for event COMPARE[9]</description>
64720 <description>Read: Disabled</description>
64725 <description>Read: Enabled</description>
64733 <description>Disable</description>
64740 <description>Write '1' to disable interrupt for event COMPARE[10]</description>
64747 <description>Read: Disabled</description>
64752 <description>Read: Enabled</description>
64760 <description>Disable</description>
64767 <description>Write '1' to disable interrupt for event COMPARE[11]</description>
64774 <description>Read: Disabled</description>
64779 <description>Read: Enabled</description>
64787 <description>Disable</description>
64794 <description>Write '1' to disable interrupt for event COMPARE[12]</description>
64801 <description>Read: Disabled</description>
64806 <description>Read: Enabled</description>
64814 <description>Disable</description>
64821 <description>Write '1' to disable interrupt for event COMPARE[13]</description>
64828 <description>Read: Disabled</description>
64833 <description>Read: Enabled</description>
64841 <description>Disable</description>
64848 <description>Write '1' to disable interrupt for event COMPARE[14]</description>
64855 <description>Read: Disabled</description>
64860 <description>Read: Enabled</description>
64868 <description>Disable</description>
64875 <description>Write '1' to disable interrupt for event COMPARE[15]</description>
64882 <description>Read: Disabled</description>
64887 <description>Read: Enabled</description>
64895 <description>Disable</description>
64902 <description>Write '1' to disable interrupt for event RTCOMPARESYNC</description>
64909 <description>Read: Disabled</description>
64914 <description>Read: Enabled</description>
64922 <description>Disable</description>
64929 <description>Write '1' to disable interrupt for event PWMPERIODEND</description>
64936 <description>Read: Disabled</description>
64941 <description>Read: Enabled</description>
64949 <description>Disable</description>
64958 <description>Pending interrupts</description>
64966 <description>Read pending status of interrupt for event COMPARE[0]</description>
64973 <description>Read: Not pending</description>
64978 <description>Read: Pending</description>
64985 <description>Read pending status of interrupt for event COMPARE[1]</description>
64992 <description>Read: Not pending</description>
64997 <description>Read: Pending</description>
65004 <description>Read pending status of interrupt for event COMPARE[2]</description>
65011 <description>Read: Not pending</description>
65016 <description>Read: Pending</description>
65023 <description>Read pending status of interrupt for event COMPARE[3]</description>
65030 <description>Read: Not pending</description>
65035 <description>Read: Pending</description>
65042 <description>Read pending status of interrupt for event COMPARE[4]</description>
65049 <description>Read: Not pending</description>
65054 <description>Read: Pending</description>
65061 <description>Read pending status of interrupt for event COMPARE[5]</description>
65068 <description>Read: Not pending</description>
65073 <description>Read: Pending</description>
65080 <description>Read pending status of interrupt for event COMPARE[6]</description>
65087 <description>Read: Not pending</description>
65092 <description>Read: Pending</description>
65099 <description>Read pending status of interrupt for event COMPARE[7]</description>
65106 <description>Read: Not pending</description>
65111 <description>Read: Pending</description>
65118 <description>Read pending status of interrupt for event COMPARE[8]</description>
65125 <description>Read: Not pending</description>
65130 <description>Read: Pending</description>
65137 <description>Read pending status of interrupt for event COMPARE[9]</description>
65144 <description>Read: Not pending</description>
65149 <description>Read: Pending</description>
65156 <description>Read pending status of interrupt for event COMPARE[10]</description>
65163 <description>Read: Not pending</description>
65168 <description>Read: Pending</description>
65175 <description>Read pending status of interrupt for event COMPARE[11]</description>
65182 <description>Read: Not pending</description>
65187 <description>Read: Pending</description>
65194 <description>Read pending status of interrupt for event COMPARE[12]</description>
65201 <description>Read: Not pending</description>
65206 <description>Read: Pending</description>
65213 <description>Read pending status of interrupt for event COMPARE[13]</description>
65220 <description>Read: Not pending</description>
65225 <description>Read: Pending</description>
65232 <description>Read pending status of interrupt for event COMPARE[14]</description>
65239 <description>Read: Not pending</description>
65244 <description>Read: Pending</description>
65251 <description>Read pending status of interrupt for event COMPARE[15]</description>
65258 <description>Read: Not pending</description>
65263 <description>Read: Pending</description>
65270 <description>Read pending status of interrupt for event RTCOMPARESYNC</description>
65277 <description>Read: Not pending</description>
65282 <description>Read: Pending</description>
65289 <description>Read pending status of interrupt for event PWMPERIODEND</description>
65296 <description>Read: Not pending</description>
65301 <description>Read: Pending</description>
65310 <description>Enable or disable interrupt</description>
65318 <description>Enable or disable interrupt for event COMPARE[0]</description>
65324 <description>Disable</description>
65329 <description>Enable</description>
65336 <description>Enable or disable interrupt for event COMPARE[1]</description>
65342 <description>Disable</description>
65347 <description>Enable</description>
65354 <description>Enable or disable interrupt for event COMPARE[2]</description>
65360 <description>Disable</description>
65365 <description>Enable</description>
65372 <description>Enable or disable interrupt for event COMPARE[3]</description>
65378 <description>Disable</description>
65383 <description>Enable</description>
65390 <description>Enable or disable interrupt for event COMPARE[4]</description>
65396 <description>Disable</description>
65401 <description>Enable</description>
65408 <description>Enable or disable interrupt for event COMPARE[5]</description>
65414 <description>Disable</description>
65419 <description>Enable</description>
65426 <description>Enable or disable interrupt for event COMPARE[6]</description>
65432 <description>Disable</description>
65437 <description>Enable</description>
65444 <description>Enable or disable interrupt for event COMPARE[7]</description>
65450 <description>Disable</description>
65455 <description>Enable</description>
65462 <description>Enable or disable interrupt for event COMPARE[8]</description>
65468 <description>Disable</description>
65473 <description>Enable</description>
65480 <description>Enable or disable interrupt for event COMPARE[9]</description>
65486 <description>Disable</description>
65491 <description>Enable</description>
65498 <description>Enable or disable interrupt for event COMPARE[10]</description>
65504 <description>Disable</description>
65509 <description>Enable</description>
65516 <description>Enable or disable interrupt for event COMPARE[11]</description>
65522 <description>Disable</description>
65527 <description>Enable</description>
65534 <description>Enable or disable interrupt for event COMPARE[12]</description>
65540 <description>Disable</description>
65545 <description>Enable</description>
65552 <description>Enable or disable interrupt for event COMPARE[13]</description>
65558 <description>Disable</description>
65563 <description>Enable</description>
65570 <description>Enable or disable interrupt for event COMPARE[14]</description>
65576 <description>Disable</description>
65581 <description>Enable</description>
65588 <description>Enable or disable interrupt for event COMPARE[15]</description>
65594 <description>Disable</description>
65599 <description>Enable</description>
65606 <description>Enable or disable interrupt for event RTCOMPARESYNC</description>
65612 <description>Disable</description>
65617 <description>Enable</description>
65624 <description>Enable or disable interrupt for event PWMPERIODEND</description>
65630 <description>Disable</description>
65635 <description>Enable</description>
65644 <description>Enable interrupt</description>
65652 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
65659 <description>Read: Disabled</description>
65664 <description>Read: Enabled</description>
65672 <description>Enable</description>
65679 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
65686 <description>Read: Disabled</description>
65691 <description>Read: Enabled</description>
65699 <description>Enable</description>
65706 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
65713 <description>Read: Disabled</description>
65718 <description>Read: Enabled</description>
65726 <description>Enable</description>
65733 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
65740 <description>Read: Disabled</description>
65745 <description>Read: Enabled</description>
65753 <description>Enable</description>
65760 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
65767 <description>Read: Disabled</description>
65772 <description>Read: Enabled</description>
65780 <description>Enable</description>
65787 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
65794 <description>Read: Disabled</description>
65799 <description>Read: Enabled</description>
65807 <description>Enable</description>
65814 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
65821 <description>Read: Disabled</description>
65826 <description>Read: Enabled</description>
65834 <description>Enable</description>
65841 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
65848 <description>Read: Disabled</description>
65853 <description>Read: Enabled</description>
65861 <description>Enable</description>
65868 <description>Write '1' to enable interrupt for event COMPARE[8]</description>
65875 <description>Read: Disabled</description>
65880 <description>Read: Enabled</description>
65888 <description>Enable</description>
65895 <description>Write '1' to enable interrupt for event COMPARE[9]</description>
65902 <description>Read: Disabled</description>
65907 <description>Read: Enabled</description>
65915 <description>Enable</description>
65922 <description>Write '1' to enable interrupt for event COMPARE[10]</description>
65929 <description>Read: Disabled</description>
65934 <description>Read: Enabled</description>
65942 <description>Enable</description>
65949 <description>Write '1' to enable interrupt for event COMPARE[11]</description>
65956 <description>Read: Disabled</description>
65961 <description>Read: Enabled</description>
65969 <description>Enable</description>
65976 <description>Write '1' to enable interrupt for event COMPARE[12]</description>
65983 <description>Read: Disabled</description>
65988 <description>Read: Enabled</description>
65996 <description>Enable</description>
66003 <description>Write '1' to enable interrupt for event COMPARE[13]</description>
66010 <description>Read: Disabled</description>
66015 <description>Read: Enabled</description>
66023 <description>Enable</description>
66030 <description>Write '1' to enable interrupt for event COMPARE[14]</description>
66037 <description>Read: Disabled</description>
66042 <description>Read: Enabled</description>
66050 <description>Enable</description>
66057 <description>Write '1' to enable interrupt for event COMPARE[15]</description>
66064 <description>Read: Disabled</description>
66069 <description>Read: Enabled</description>
66077 <description>Enable</description>
66084 <description>Write '1' to enable interrupt for event RTCOMPARESYNC</description>
66091 <description>Read: Disabled</description>
66096 <description>Read: Enabled</description>
66104 <description>Enable</description>
66111 <description>Write '1' to enable interrupt for event PWMPERIODEND</description>
66118 <description>Read: Disabled</description>
66123 <description>Read: Enabled</description>
66131 <description>Enable</description>
66140 <description>Disable interrupt</description>
66148 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
66155 <description>Read: Disabled</description>
66160 <description>Read: Enabled</description>
66168 <description>Disable</description>
66175 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
66182 <description>Read: Disabled</description>
66187 <description>Read: Enabled</description>
66195 <description>Disable</description>
66202 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
66209 <description>Read: Disabled</description>
66214 <description>Read: Enabled</description>
66222 <description>Disable</description>
66229 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
66236 <description>Read: Disabled</description>
66241 <description>Read: Enabled</description>
66249 <description>Disable</description>
66256 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
66263 <description>Read: Disabled</description>
66268 <description>Read: Enabled</description>
66276 <description>Disable</description>
66283 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
66290 <description>Read: Disabled</description>
66295 <description>Read: Enabled</description>
66303 <description>Disable</description>
66310 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
66317 <description>Read: Disabled</description>
66322 <description>Read: Enabled</description>
66330 <description>Disable</description>
66337 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
66344 <description>Read: Disabled</description>
66349 <description>Read: Enabled</description>
66357 <description>Disable</description>
66364 <description>Write '1' to disable interrupt for event COMPARE[8]</description>
66371 <description>Read: Disabled</description>
66376 <description>Read: Enabled</description>
66384 <description>Disable</description>
66391 <description>Write '1' to disable interrupt for event COMPARE[9]</description>
66398 <description>Read: Disabled</description>
66403 <description>Read: Enabled</description>
66411 <description>Disable</description>
66418 <description>Write '1' to disable interrupt for event COMPARE[10]</description>
66425 <description>Read: Disabled</description>
66430 <description>Read: Enabled</description>
66438 <description>Disable</description>
66445 <description>Write '1' to disable interrupt for event COMPARE[11]</description>
66452 <description>Read: Disabled</description>
66457 <description>Read: Enabled</description>
66465 <description>Disable</description>
66472 <description>Write '1' to disable interrupt for event COMPARE[12]</description>
66479 <description>Read: Disabled</description>
66484 <description>Read: Enabled</description>
66492 <description>Disable</description>
66499 <description>Write '1' to disable interrupt for event COMPARE[13]</description>
66506 <description>Read: Disabled</description>
66511 <description>Read: Enabled</description>
66519 <description>Disable</description>
66526 <description>Write '1' to disable interrupt for event COMPARE[14]</description>
66533 <description>Read: Disabled</description>
66538 <description>Read: Enabled</description>
66546 <description>Disable</description>
66553 <description>Write '1' to disable interrupt for event COMPARE[15]</description>
66560 <description>Read: Disabled</description>
66565 <description>Read: Enabled</description>
66573 <description>Disable</description>
66580 <description>Write '1' to disable interrupt for event RTCOMPARESYNC</description>
66587 <description>Read: Disabled</description>
66592 <description>Read: Enabled</description>
66600 <description>Disable</description>
66607 <description>Write '1' to disable interrupt for event PWMPERIODEND</description>
66614 <description>Read: Disabled</description>
66619 <description>Read: Enabled</description>
66627 <description>Disable</description>
66636 <description>Pending interrupts</description>
66644 <description>Read pending status of interrupt for event COMPARE[0]</description>
66651 <description>Read: Not pending</description>
66656 <description>Read: Pending</description>
66663 <description>Read pending status of interrupt for event COMPARE[1]</description>
66670 <description>Read: Not pending</description>
66675 <description>Read: Pending</description>
66682 <description>Read pending status of interrupt for event COMPARE[2]</description>
66689 <description>Read: Not pending</description>
66694 <description>Read: Pending</description>
66701 <description>Read pending status of interrupt for event COMPARE[3]</description>
66708 <description>Read: Not pending</description>
66713 <description>Read: Pending</description>
66720 <description>Read pending status of interrupt for event COMPARE[4]</description>
66727 <description>Read: Not pending</description>
66732 <description>Read: Pending</description>
66739 <description>Read pending status of interrupt for event COMPARE[5]</description>
66746 <description>Read: Not pending</description>
66751 <description>Read: Pending</description>
66758 <description>Read pending status of interrupt for event COMPARE[6]</description>
66765 <description>Read: Not pending</description>
66770 <description>Read: Pending</description>
66777 <description>Read pending status of interrupt for event COMPARE[7]</description>
66784 <description>Read: Not pending</description>
66789 <description>Read: Pending</description>
66796 <description>Read pending status of interrupt for event COMPARE[8]</description>
66803 <description>Read: Not pending</description>
66808 <description>Read: Pending</description>
66815 <description>Read pending status of interrupt for event COMPARE[9]</description>
66822 <description>Read: Not pending</description>
66827 <description>Read: Pending</description>
66834 <description>Read pending status of interrupt for event COMPARE[10]</description>
66841 <description>Read: Not pending</description>
66846 <description>Read: Pending</description>
66853 <description>Read pending status of interrupt for event COMPARE[11]</description>
66860 <description>Read: Not pending</description>
66865 <description>Read: Pending</description>
66872 <description>Read pending status of interrupt for event COMPARE[12]</description>
66879 <description>Read: Not pending</description>
66884 <description>Read: Pending</description>
66891 <description>Read pending status of interrupt for event COMPARE[13]</description>
66898 <description>Read: Not pending</description>
66903 <description>Read: Pending</description>
66910 <description>Read pending status of interrupt for event COMPARE[14]</description>
66917 <description>Read: Not pending</description>
66922 <description>Read: Pending</description>
66929 <description>Read pending status of interrupt for event COMPARE[15]</description>
66936 <description>Read: Not pending</description>
66941 <description>Read: Pending</description>
66948 <description>Read pending status of interrupt for event RTCOMPARESYNC</description>
66955 <description>Read: Not pending</description>
66960 <description>Read: Pending</description>
66967 <description>Read pending status of interrupt for event PWMPERIODEND</description>
66974 <description>Read: Not pending</description>
66979 <description>Read: Pending</description>
66988 <description>Enable or disable interrupt</description>
66996 <description>Enable or disable interrupt for event COMPARE[0]</description>
67002 <description>Disable</description>
67007 <description>Enable</description>
67014 <description>Enable or disable interrupt for event COMPARE[1]</description>
67020 <description>Disable</description>
67025 <description>Enable</description>
67032 <description>Enable or disable interrupt for event COMPARE[2]</description>
67038 <description>Disable</description>
67043 <description>Enable</description>
67050 <description>Enable or disable interrupt for event COMPARE[3]</description>
67056 <description>Disable</description>
67061 <description>Enable</description>
67068 <description>Enable or disable interrupt for event COMPARE[4]</description>
67074 <description>Disable</description>
67079 <description>Enable</description>
67086 <description>Enable or disable interrupt for event COMPARE[5]</description>
67092 <description>Disable</description>
67097 <description>Enable</description>
67104 <description>Enable or disable interrupt for event COMPARE[6]</description>
67110 <description>Disable</description>
67115 <description>Enable</description>
67122 <description>Enable or disable interrupt for event COMPARE[7]</description>
67128 <description>Disable</description>
67133 <description>Enable</description>
67140 <description>Enable or disable interrupt for event COMPARE[8]</description>
67146 <description>Disable</description>
67151 <description>Enable</description>
67158 <description>Enable or disable interrupt for event COMPARE[9]</description>
67164 <description>Disable</description>
67169 <description>Enable</description>
67176 <description>Enable or disable interrupt for event COMPARE[10]</description>
67182 <description>Disable</description>
67187 <description>Enable</description>
67194 <description>Enable or disable interrupt for event COMPARE[11]</description>
67200 <description>Disable</description>
67205 <description>Enable</description>
67212 <description>Enable or disable interrupt for event COMPARE[12]</description>
67218 <description>Disable</description>
67223 <description>Enable</description>
67230 <description>Enable or disable interrupt for event COMPARE[13]</description>
67236 <description>Disable</description>
67241 <description>Enable</description>
67248 <description>Enable or disable interrupt for event COMPARE[14]</description>
67254 <description>Disable</description>
67259 <description>Enable</description>
67266 <description>Enable or disable interrupt for event COMPARE[15]</description>
67272 <description>Disable</description>
67277 <description>Enable</description>
67284 <description>Enable or disable interrupt for event RTCOMPARESYNC</description>
67290 <description>Disable</description>
67295 <description>Enable</description>
67302 <description>Enable or disable interrupt for event PWMPERIODEND</description>
67308 <description>Disable</description>
67313 <description>Enable</description>
67322 <description>Enable interrupt</description>
67330 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
67337 <description>Read: Disabled</description>
67342 <description>Read: Enabled</description>
67350 <description>Enable</description>
67357 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
67364 <description>Read: Disabled</description>
67369 <description>Read: Enabled</description>
67377 <description>Enable</description>
67384 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
67391 <description>Read: Disabled</description>
67396 <description>Read: Enabled</description>
67404 <description>Enable</description>
67411 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
67418 <description>Read: Disabled</description>
67423 <description>Read: Enabled</description>
67431 <description>Enable</description>
67438 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
67445 <description>Read: Disabled</description>
67450 <description>Read: Enabled</description>
67458 <description>Enable</description>
67465 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
67472 <description>Read: Disabled</description>
67477 <description>Read: Enabled</description>
67485 <description>Enable</description>
67492 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
67499 <description>Read: Disabled</description>
67504 <description>Read: Enabled</description>
67512 <description>Enable</description>
67519 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
67526 <description>Read: Disabled</description>
67531 <description>Read: Enabled</description>
67539 <description>Enable</description>
67546 <description>Write '1' to enable interrupt for event COMPARE[8]</description>
67553 <description>Read: Disabled</description>
67558 <description>Read: Enabled</description>
67566 <description>Enable</description>
67573 <description>Write '1' to enable interrupt for event COMPARE[9]</description>
67580 <description>Read: Disabled</description>
67585 <description>Read: Enabled</description>
67593 <description>Enable</description>
67600 <description>Write '1' to enable interrupt for event COMPARE[10]</description>
67607 <description>Read: Disabled</description>
67612 <description>Read: Enabled</description>
67620 <description>Enable</description>
67627 <description>Write '1' to enable interrupt for event COMPARE[11]</description>
67634 <description>Read: Disabled</description>
67639 <description>Read: Enabled</description>
67647 <description>Enable</description>
67654 <description>Write '1' to enable interrupt for event COMPARE[12]</description>
67661 <description>Read: Disabled</description>
67666 <description>Read: Enabled</description>
67674 <description>Enable</description>
67681 <description>Write '1' to enable interrupt for event COMPARE[13]</description>
67688 <description>Read: Disabled</description>
67693 <description>Read: Enabled</description>
67701 <description>Enable</description>
67708 <description>Write '1' to enable interrupt for event COMPARE[14]</description>
67715 <description>Read: Disabled</description>
67720 <description>Read: Enabled</description>
67728 <description>Enable</description>
67735 <description>Write '1' to enable interrupt for event COMPARE[15]</description>
67742 <description>Read: Disabled</description>
67747 <description>Read: Enabled</description>
67755 <description>Enable</description>
67762 <description>Write '1' to enable interrupt for event RTCOMPARESYNC</description>
67769 <description>Read: Disabled</description>
67774 <description>Read: Enabled</description>
67782 <description>Enable</description>
67789 <description>Write '1' to enable interrupt for event PWMPERIODEND</description>
67796 <description>Read: Disabled</description>
67801 <description>Read: Enabled</description>
67809 <description>Enable</description>
67818 <description>Disable interrupt</description>
67826 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
67833 <description>Read: Disabled</description>
67838 <description>Read: Enabled</description>
67846 <description>Disable</description>
67853 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
67860 <description>Read: Disabled</description>
67865 <description>Read: Enabled</description>
67873 <description>Disable</description>
67880 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
67887 <description>Read: Disabled</description>
67892 <description>Read: Enabled</description>
67900 <description>Disable</description>
67907 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
67914 <description>Read: Disabled</description>
67919 <description>Read: Enabled</description>
67927 <description>Disable</description>
67934 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
67941 <description>Read: Disabled</description>
67946 <description>Read: Enabled</description>
67954 <description>Disable</description>
67961 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
67968 <description>Read: Disabled</description>
67973 <description>Read: Enabled</description>
67981 <description>Disable</description>
67988 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
67995 <description>Read: Disabled</description>
68000 <description>Read: Enabled</description>
68008 <description>Disable</description>
68015 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
68022 <description>Read: Disabled</description>
68027 <description>Read: Enabled</description>
68035 <description>Disable</description>
68042 <description>Write '1' to disable interrupt for event COMPARE[8]</description>
68049 <description>Read: Disabled</description>
68054 <description>Read: Enabled</description>
68062 <description>Disable</description>
68069 <description>Write '1' to disable interrupt for event COMPARE[9]</description>
68076 <description>Read: Disabled</description>
68081 <description>Read: Enabled</description>
68089 <description>Disable</description>
68096 <description>Write '1' to disable interrupt for event COMPARE[10]</description>
68103 <description>Read: Disabled</description>
68108 <description>Read: Enabled</description>
68116 <description>Disable</description>
68123 <description>Write '1' to disable interrupt for event COMPARE[11]</description>
68130 <description>Read: Disabled</description>
68135 <description>Read: Enabled</description>
68143 <description>Disable</description>
68150 <description>Write '1' to disable interrupt for event COMPARE[12]</description>
68157 <description>Read: Disabled</description>
68162 <description>Read: Enabled</description>
68170 <description>Disable</description>
68177 <description>Write '1' to disable interrupt for event COMPARE[13]</description>
68184 <description>Read: Disabled</description>
68189 <description>Read: Enabled</description>
68197 <description>Disable</description>
68204 <description>Write '1' to disable interrupt for event COMPARE[14]</description>
68211 <description>Read: Disabled</description>
68216 <description>Read: Enabled</description>
68224 <description>Disable</description>
68231 <description>Write '1' to disable interrupt for event COMPARE[15]</description>
68238 <description>Read: Disabled</description>
68243 <description>Read: Enabled</description>
68251 <description>Disable</description>
68258 <description>Write '1' to disable interrupt for event RTCOMPARESYNC</description>
68265 <description>Read: Disabled</description>
68270 <description>Read: Enabled</description>
68278 <description>Disable</description>
68285 <description>Write '1' to disable interrupt for event PWMPERIODEND</description>
68292 <description>Read: Disabled</description>
68297 <description>Read: Enabled</description>
68305 <description>Disable</description>
68314 <description>Pending interrupts</description>
68322 <description>Read pending status of interrupt for event COMPARE[0]</description>
68329 <description>Read: Not pending</description>
68334 <description>Read: Pending</description>
68341 <description>Read pending status of interrupt for event COMPARE[1]</description>
68348 <description>Read: Not pending</description>
68353 <description>Read: Pending</description>
68360 <description>Read pending status of interrupt for event COMPARE[2]</description>
68367 <description>Read: Not pending</description>
68372 <description>Read: Pending</description>
68379 <description>Read pending status of interrupt for event COMPARE[3]</description>
68386 <description>Read: Not pending</description>
68391 <description>Read: Pending</description>
68398 <description>Read pending status of interrupt for event COMPARE[4]</description>
68405 <description>Read: Not pending</description>
68410 <description>Read: Pending</description>
68417 <description>Read pending status of interrupt for event COMPARE[5]</description>
68424 <description>Read: Not pending</description>
68429 <description>Read: Pending</description>
68436 <description>Read pending status of interrupt for event COMPARE[6]</description>
68443 <description>Read: Not pending</description>
68448 <description>Read: Pending</description>
68455 <description>Read pending status of interrupt for event COMPARE[7]</description>
68462 <description>Read: Not pending</description>
68467 <description>Read: Pending</description>
68474 <description>Read pending status of interrupt for event COMPARE[8]</description>
68481 <description>Read: Not pending</description>
68486 <description>Read: Pending</description>
68493 <description>Read pending status of interrupt for event COMPARE[9]</description>
68500 <description>Read: Not pending</description>
68505 <description>Read: Pending</description>
68512 <description>Read pending status of interrupt for event COMPARE[10]</description>
68519 <description>Read: Not pending</description>
68524 <description>Read: Pending</description>
68531 <description>Read pending status of interrupt for event COMPARE[11]</description>
68538 <description>Read: Not pending</description>
68543 <description>Read: Pending</description>
68550 <description>Read pending status of interrupt for event COMPARE[12]</description>
68557 <description>Read: Not pending</description>
68562 <description>Read: Pending</description>
68569 <description>Read pending status of interrupt for event COMPARE[13]</description>
68576 <description>Read: Not pending</description>
68581 <description>Read: Pending</description>
68588 <description>Read pending status of interrupt for event COMPARE[14]</description>
68595 <description>Read: Not pending</description>
68600 <description>Read: Pending</description>
68607 <description>Read pending status of interrupt for event COMPARE[15]</description>
68614 <description>Read: Not pending</description>
68619 <description>Read: Pending</description>
68626 <description>Read pending status of interrupt for event RTCOMPARESYNC</description>
68633 <description>Read: Not pending</description>
68638 <description>Read: Pending</description>
68645 <description>Read pending status of interrupt for event PWMPERIODEND</description>
68652 <description>Read: Not pending</description>
68657 <description>Read: Pending</description>
68666 <description>Enable or disable interrupt</description>
68674 <description>Enable or disable interrupt for event COMPARE[0]</description>
68680 <description>Disable</description>
68685 <description>Enable</description>
68692 <description>Enable or disable interrupt for event COMPARE[1]</description>
68698 <description>Disable</description>
68703 <description>Enable</description>
68710 <description>Enable or disable interrupt for event COMPARE[2]</description>
68716 <description>Disable</description>
68721 <description>Enable</description>
68728 <description>Enable or disable interrupt for event COMPARE[3]</description>
68734 <description>Disable</description>
68739 <description>Enable</description>
68746 <description>Enable or disable interrupt for event COMPARE[4]</description>
68752 <description>Disable</description>
68757 <description>Enable</description>
68764 <description>Enable or disable interrupt for event COMPARE[5]</description>
68770 <description>Disable</description>
68775 <description>Enable</description>
68782 <description>Enable or disable interrupt for event COMPARE[6]</description>
68788 <description>Disable</description>
68793 <description>Enable</description>
68800 <description>Enable or disable interrupt for event COMPARE[7]</description>
68806 <description>Disable</description>
68811 <description>Enable</description>
68818 <description>Enable or disable interrupt for event COMPARE[8]</description>
68824 <description>Disable</description>
68829 <description>Enable</description>
68836 <description>Enable or disable interrupt for event COMPARE[9]</description>
68842 <description>Disable</description>
68847 <description>Enable</description>
68854 <description>Enable or disable interrupt for event COMPARE[10]</description>
68860 <description>Disable</description>
68865 <description>Enable</description>
68872 <description>Enable or disable interrupt for event COMPARE[11]</description>
68878 <description>Disable</description>
68883 <description>Enable</description>
68890 <description>Enable or disable interrupt for event COMPARE[12]</description>
68896 <description>Disable</description>
68901 <description>Enable</description>
68908 <description>Enable or disable interrupt for event COMPARE[13]</description>
68914 <description>Disable</description>
68919 <description>Enable</description>
68926 <description>Enable or disable interrupt for event COMPARE[14]</description>
68932 <description>Disable</description>
68937 <description>Enable</description>
68944 <description>Enable or disable interrupt for event COMPARE[15]</description>
68950 <description>Disable</description>
68955 <description>Enable</description>
68962 <description>Enable or disable interrupt for event RTCOMPARESYNC</description>
68968 <description>Disable</description>
68973 <description>Enable</description>
68980 <description>Enable or disable interrupt for event PWMPERIODEND</description>
68986 <description>Disable</description>
68991 <description>Enable</description>
69000 <description>Enable interrupt</description>
69008 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
69015 <description>Read: Disabled</description>
69020 <description>Read: Enabled</description>
69028 <description>Enable</description>
69035 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
69042 <description>Read: Disabled</description>
69047 <description>Read: Enabled</description>
69055 <description>Enable</description>
69062 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
69069 <description>Read: Disabled</description>
69074 <description>Read: Enabled</description>
69082 <description>Enable</description>
69089 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
69096 <description>Read: Disabled</description>
69101 <description>Read: Enabled</description>
69109 <description>Enable</description>
69116 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
69123 <description>Read: Disabled</description>
69128 <description>Read: Enabled</description>
69136 <description>Enable</description>
69143 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
69150 <description>Read: Disabled</description>
69155 <description>Read: Enabled</description>
69163 <description>Enable</description>
69170 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
69177 <description>Read: Disabled</description>
69182 <description>Read: Enabled</description>
69190 <description>Enable</description>
69197 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
69204 <description>Read: Disabled</description>
69209 <description>Read: Enabled</description>
69217 <description>Enable</description>
69224 <description>Write '1' to enable interrupt for event COMPARE[8]</description>
69231 <description>Read: Disabled</description>
69236 <description>Read: Enabled</description>
69244 <description>Enable</description>
69251 <description>Write '1' to enable interrupt for event COMPARE[9]</description>
69258 <description>Read: Disabled</description>
69263 <description>Read: Enabled</description>
69271 <description>Enable</description>
69278 <description>Write '1' to enable interrupt for event COMPARE[10]</description>
69285 <description>Read: Disabled</description>
69290 <description>Read: Enabled</description>
69298 <description>Enable</description>
69305 <description>Write '1' to enable interrupt for event COMPARE[11]</description>
69312 <description>Read: Disabled</description>
69317 <description>Read: Enabled</description>
69325 <description>Enable</description>
69332 <description>Write '1' to enable interrupt for event COMPARE[12]</description>
69339 <description>Read: Disabled</description>
69344 <description>Read: Enabled</description>
69352 <description>Enable</description>
69359 <description>Write '1' to enable interrupt for event COMPARE[13]</description>
69366 <description>Read: Disabled</description>
69371 <description>Read: Enabled</description>
69379 <description>Enable</description>
69386 <description>Write '1' to enable interrupt for event COMPARE[14]</description>
69393 <description>Read: Disabled</description>
69398 <description>Read: Enabled</description>
69406 <description>Enable</description>
69413 <description>Write '1' to enable interrupt for event COMPARE[15]</description>
69420 <description>Read: Disabled</description>
69425 <description>Read: Enabled</description>
69433 <description>Enable</description>
69440 <description>Write '1' to enable interrupt for event RTCOMPARESYNC</description>
69447 <description>Read: Disabled</description>
69452 <description>Read: Enabled</description>
69460 <description>Enable</description>
69467 <description>Write '1' to enable interrupt for event PWMPERIODEND</description>
69474 <description>Read: Disabled</description>
69479 <description>Read: Enabled</description>
69487 <description>Enable</description>
69496 <description>Disable interrupt</description>
69504 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
69511 <description>Read: Disabled</description>
69516 <description>Read: Enabled</description>
69524 <description>Disable</description>
69531 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
69538 <description>Read: Disabled</description>
69543 <description>Read: Enabled</description>
69551 <description>Disable</description>
69558 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
69565 <description>Read: Disabled</description>
69570 <description>Read: Enabled</description>
69578 <description>Disable</description>
69585 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
69592 <description>Read: Disabled</description>
69597 <description>Read: Enabled</description>
69605 <description>Disable</description>
69612 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
69619 <description>Read: Disabled</description>
69624 <description>Read: Enabled</description>
69632 <description>Disable</description>
69639 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
69646 <description>Read: Disabled</description>
69651 <description>Read: Enabled</description>
69659 <description>Disable</description>
69666 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
69673 <description>Read: Disabled</description>
69678 <description>Read: Enabled</description>
69686 <description>Disable</description>
69693 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
69700 <description>Read: Disabled</description>
69705 <description>Read: Enabled</description>
69713 <description>Disable</description>
69720 <description>Write '1' to disable interrupt for event COMPARE[8]</description>
69727 <description>Read: Disabled</description>
69732 <description>Read: Enabled</description>
69740 <description>Disable</description>
69747 <description>Write '1' to disable interrupt for event COMPARE[9]</description>
69754 <description>Read: Disabled</description>
69759 <description>Read: Enabled</description>
69767 <description>Disable</description>
69774 <description>Write '1' to disable interrupt for event COMPARE[10]</description>
69781 <description>Read: Disabled</description>
69786 <description>Read: Enabled</description>
69794 <description>Disable</description>
69801 <description>Write '1' to disable interrupt for event COMPARE[11]</description>
69808 <description>Read: Disabled</description>
69813 <description>Read: Enabled</description>
69821 <description>Disable</description>
69828 <description>Write '1' to disable interrupt for event COMPARE[12]</description>
69835 <description>Read: Disabled</description>
69840 <description>Read: Enabled</description>
69848 <description>Disable</description>
69855 <description>Write '1' to disable interrupt for event COMPARE[13]</description>
69862 <description>Read: Disabled</description>
69867 <description>Read: Enabled</description>
69875 <description>Disable</description>
69882 <description>Write '1' to disable interrupt for event COMPARE[14]</description>
69889 <description>Read: Disabled</description>
69894 <description>Read: Enabled</description>
69902 <description>Disable</description>
69909 <description>Write '1' to disable interrupt for event COMPARE[15]</description>
69916 <description>Read: Disabled</description>
69921 <description>Read: Enabled</description>
69929 <description>Disable</description>
69936 <description>Write '1' to disable interrupt for event RTCOMPARESYNC</description>
69943 <description>Read: Disabled</description>
69948 <description>Read: Enabled</description>
69956 <description>Disable</description>
69963 <description>Write '1' to disable interrupt for event PWMPERIODEND</description>
69970 <description>Read: Disabled</description>
69975 <description>Read: Enabled</description>
69983 <description>Disable</description>
69992 <description>Pending interrupts</description>
70000 <description>Read pending status of interrupt for event COMPARE[0]</description>
70007 <description>Read: Not pending</description>
70012 <description>Read: Pending</description>
70019 <description>Read pending status of interrupt for event COMPARE[1]</description>
70026 <description>Read: Not pending</description>
70031 <description>Read: Pending</description>
70038 <description>Read pending status of interrupt for event COMPARE[2]</description>
70045 <description>Read: Not pending</description>
70050 <description>Read: Pending</description>
70057 <description>Read pending status of interrupt for event COMPARE[3]</description>
70064 <description>Read: Not pending</description>
70069 <description>Read: Pending</description>
70076 <description>Read pending status of interrupt for event COMPARE[4]</description>
70083 <description>Read: Not pending</description>
70088 <description>Read: Pending</description>
70095 <description>Read pending status of interrupt for event COMPARE[5]</description>
70102 <description>Read: Not pending</description>
70107 <description>Read: Pending</description>
70114 <description>Read pending status of interrupt for event COMPARE[6]</description>
70121 <description>Read: Not pending</description>
70126 <description>Read: Pending</description>
70133 <description>Read pending status of interrupt for event COMPARE[7]</description>
70140 <description>Read: Not pending</description>
70145 <description>Read: Pending</description>
70152 <description>Read pending status of interrupt for event COMPARE[8]</description>
70159 <description>Read: Not pending</description>
70164 <description>Read: Pending</description>
70171 <description>Read pending status of interrupt for event COMPARE[9]</description>
70178 <description>Read: Not pending</description>
70183 <description>Read: Pending</description>
70190 <description>Read pending status of interrupt for event COMPARE[10]</description>
70197 <description>Read: Not pending</description>
70202 <description>Read: Pending</description>
70209 <description>Read pending status of interrupt for event COMPARE[11]</description>
70216 <description>Read: Not pending</description>
70221 <description>Read: Pending</description>
70228 <description>Read pending status of interrupt for event COMPARE[12]</description>
70235 <description>Read: Not pending</description>
70240 <description>Read: Pending</description>
70247 <description>Read pending status of interrupt for event COMPARE[13]</description>
70254 <description>Read: Not pending</description>
70259 <description>Read: Pending</description>
70266 <description>Read pending status of interrupt for event COMPARE[14]</description>
70273 <description>Read: Not pending</description>
70278 <description>Read: Pending</description>
70285 <description>Read pending status of interrupt for event COMPARE[15]</description>
70292 <description>Read: Not pending</description>
70297 <description>Read: Pending</description>
70304 <description>Read pending status of interrupt for event RTCOMPARESYNC</description>
70311 <description>Read: Not pending</description>
70316 <description>Read: Pending</description>
70323 <description>Read pending status of interrupt for event PWMPERIODEND</description>
70330 <description>Read: Not pending</description>
70335 <description>Read: Pending</description>
70344 <description>Enable or disable event routing</description>
70352 <description>Enable or disable event routing for event PWMPERIODEND</description>
70358 <description>Disable</description>
70363 <description>Enable</description>
70372 <description>Enable event routing</description>
70380 <description>Write '1' to enable event routing for event PWMPERIODEND</description>
70387 <description>Read: Disabled</description>
70392 <description>Read: Enabled</description>
70400 <description>Enable</description>
70409 <description>Disable event routing</description>
70417 <description>Write '1' to disable event routing for event PWMPERIODEND</description>
70424 <description>Read: Disabled</description>
70429 <description>Read: Enabled</description>
70437 <description>Disable</description>
70446 <description>Counter mode selection</description>
70454 <description>Automatic enable to keep the SYSCOUNTER active.</description>
70460 <description>Default configuration to keep the SYSCOUNTER active.</description>
70465 …<description>In addition to the above mode, any local CPU that is not sleeping keep the SYSCOUNTER…
70472 <description>Enable the SYSCOUNTER</description>
70478 <description>SYSCOUNTER disabled</description>
70483 <description>SYSCOUNTER enabled</description>
70494 <description>Unspecified</description>
70500 …<description>Description cluster: The lower 32-bits of Capture/Compare register CC[n]</description>
70508 <description>Capture/Compare low value in 1 us</description>
70516 …<description>Description cluster: The higher 32-bits of Capture/Compare register CC[n]</descriptio…
70524 <description>Capture/Compare high value in 1 us</description>
70532 …<description>Description cluster: Count to add to CC[n] when this register is written.</descriptio…
70540 <description>Count to add to CC[n]</description>
70546 <description>Configure the Capture/Compare register</description>
70552 <description>Adds SYSCOUNTER value.</description>
70557 <description>Adds CC value.</description>
70566 <description>Description cluster: Configure Capture/Compare register CC[n]</description>
70574 <description>Configure the Capture/Compare register</description>
70580 <description>Capture/Compare register CC[n] Disabled.</description>
70585 <description>Capture/Compare register CC[n] enabled.</description>
70595 … <description>Timeout after all CPUs gone into sleep state to stop the SYSCOUNTER</description>
70603 <description>Number of 32Ki cycles</description>
70611 … <description>Count to add to CC[0] when the event EVENTS_COMPARE[0] triggers.</description>
70619 <description>Count to add to CC[0]</description>
70627 <description>PWM configuration.</description>
70635 <description>The PWM compare value</description>
70643 <description>Configuration of clock output</description>
70651 <description>Enable 32Ki clock output on pin</description>
70657 <description>Disabled</description>
70662 <description>Enabled</description>
70669 <description>Enable fast clock output on pin</description>
70675 <description>Disabled</description>
70680 <description>Enabled</description>
70689 <description>Clock Configuration</description>
70697 <description>Fast clock divisor value of clock output</description>
70703 <description>GRTC LFCLK clock source selection</description>
70710 <description>GRTC LFCLK clock source is LFXO</description>
70715 <description>GRTC LFCLK clock source is system LFCLK</description>
70720 <description>GRTC LFCLK clock source is LFLPRC</description>
70731 <description>Unspecified</description>
70737 … <description>Description cluster: The lower 32-bits of the SYSCOUNTER for index [n]</description>
70745 <description>The lower 32-bits of the SYSCOUNTER value.</description>
70753 … <description>Description cluster: The higher 20-bits of the SYSCOUNTER for index [n]</description>
70761 <description>The higher 20-bits of the SYSCOUNTER value.</description>
70767 <description>SYSCOUNTER busy status</description>
70773 <description>SYSCOUNTER is ready for read</description>
70778 …<description>SYSCOUNTER is busy, so not ready for read (value returned in the VALUE field of this …
70785 <description>The SYSCOUNTERL overflow indication after reading it.</description>
70791 <description>SYSCOUNTERL is not overflown</description>
70796 <description>SYSCOUNTERL overflown</description>
70805 …<description>Description cluster: Request to keep the SYSCOUNTER in the active state and prevent g…
70813 <description>Keep SYSCOUNTER in active state</description>
70819 <description>Allow SYSCOUNTER to go to sleep</description>
70824 <description>Keep SYSCOUNTER active</description>
70836 <description>Trace buffer monitor</description>
70854 <description>Start counter</description>
70862 <description>Start counter</description>
70868 <description>Trigger task</description>
70877 <description>Stop counter, clear counter value</description>
70885 <description>Stop counter, clear counter value</description>
70891 <description>Trigger task</description>
70900 <description>Save current counter value to COUNTSNAPSHOT</description>
70908 <description>Save current counter value to COUNTSNAPSHOT</description>
70914 <description>Trigger task</description>
70923 <description>Counter value equals half-full</description>
70931 <description>Counter value equals half-full</description>
70937 <description>Event not generated</description>
70942 <description>Event generated</description>
70951 <description>Counter value equals full</description>
70959 <description>Counter value equals full</description>
70965 <description>Event not generated</description>
70970 <description>Event generated</description>
70979 <description>Counter value saved to COUNTSNAPSHOT due to flush</description>
70987 <description>Counter value saved to COUNTSNAPSHOT due to flush</description>
70993 <description>Event not generated</description>
70998 <description>Event generated</description>
71007 <description>Enable or disable interrupt</description>
71015 <description>Enable or disable interrupt for event HALFFULL</description>
71021 <description>Disable</description>
71026 <description>Enable</description>
71033 <description>Enable or disable interrupt for event FULL</description>
71039 <description>Disable</description>
71044 <description>Enable</description>
71051 <description>Enable or disable interrupt for event FLUSH</description>
71057 <description>Disable</description>
71062 <description>Enable</description>
71071 <description>Enable interrupt</description>
71079 <description>Write '1' to enable interrupt for event HALFFULL</description>
71086 <description>Read: Disabled</description>
71091 <description>Read: Enabled</description>
71099 <description>Enable</description>
71106 <description>Write '1' to enable interrupt for event FULL</description>
71113 <description>Read: Disabled</description>
71118 <description>Read: Enabled</description>
71126 <description>Enable</description>
71133 <description>Write '1' to enable interrupt for event FLUSH</description>
71140 <description>Read: Disabled</description>
71145 <description>Read: Enabled</description>
71153 <description>Enable</description>
71162 <description>Disable interrupt</description>
71170 <description>Write '1' to disable interrupt for event HALFFULL</description>
71177 <description>Read: Disabled</description>
71182 <description>Read: Enabled</description>
71190 <description>Disable</description>
71197 <description>Write '1' to disable interrupt for event FULL</description>
71204 <description>Read: Disabled</description>
71209 <description>Read: Enabled</description>
71217 <description>Disable</description>
71224 <description>Write '1' to disable interrupt for event FLUSH</description>
71231 <description>Read: Disabled</description>
71236 <description>Read: Enabled</description>
71244 <description>Disable</description>
71253 <description>Pending interrupts</description>
71261 <description>Read pending status of interrupt for event HALFFULL</description>
71268 <description>Read: Not pending</description>
71273 <description>Read: Pending</description>
71280 <description>Read pending status of interrupt for event FULL</description>
71287 <description>Read: Not pending</description>
71292 <description>Read: Pending</description>
71299 <description>Read pending status of interrupt for event FLUSH</description>
71306 <description>Read: Not pending</description>
71311 <description>Read: Pending</description>
71320 <description>System RAM trace buffer total size in bytes</description>
71328 …<description>Must only be configured in STOP mode. Must be programmed to multiple of 16 bytes to m…
71330 maximum value 0x1000 i.e. 4096 bytes.</description>
71336 <description>0 bytes</description>
71341 <description>16 bytes</description>
71346 <description>4096 bytes</description>
71355 <description>Counter current value</description>
71363 …<description>Counter current value. Only writable when counter is in stopped state. Writing when n…
71364 state will generate a bus fault.</description>
71372 <description>Copy of the current COUNT value</description>
71380 … <description>TASKS_FLUSH will copy the current COUNT value to this register.</description>
71390 <description>USBHS</description>
71408 <description>Start the USB peripheral.</description>
71416 <description>Start the USB peripheral.</description>
71422 <description>Trigger task</description>
71431 <description>Stop the USB peripheral</description>
71439 <description>Stop the USB peripheral</description>
71445 <description>Trigger task</description>
71454 <description>Subscribe configuration for task START</description>
71462 <description>DPPI channel that task START will subscribe to</description>
71473 <description>Disable subscription</description>
71478 <description>Enable subscription</description>
71487 <description>Subscribe configuration for task STOP</description>
71495 <description>DPPI channel that task STOP will subscribe to</description>
71506 <description>Disable subscription</description>
71511 <description>Enable subscription</description>
71520 <description>Event indicating that interrupt triggered at USBHS core</description>
71528 <description>Event indicating that interrupt triggered at USBHS core</description>
71534 <description>Event not generated</description>
71539 <description>Event generated</description>
71548 <description>Publish configuration for event CORE</description>
71556 <description>DPPI channel that event CORE will publish to</description>
71567 <description>Disable publishing</description>
71572 <description>Enable publishing</description>
71581 <description>Enable interrupt</description>
71589 <description>Write '1' to enable interrupt for event CORE</description>
71596 <description>Read: Disabled</description>
71601 <description>Read: Enabled</description>
71609 <description>Enable</description>
71618 <description>Disable interrupt</description>
71626 <description>Write '1' to disable interrupt for event CORE</description>
71633 <description>Read: Disabled</description>
71638 <description>Read: Enabled</description>
71646 <description>Disable</description>
71655 <description>Pending interrupts</description>
71663 <description>Read pending status of interrupt for event CORE</description>
71670 <description>Read: Not pending</description>
71675 <description>Read: Pending</description>
71684 <description>Enable USB peripheral.</description>
71692 <description>Enable USB Controller</description>
71698 <description>USB Controller disabled.</description>
71703 <description>USB Controller enabled.</description>
71710 <description>Enable USB PHY</description>
71716 <description>USB PHY disabled.</description>
71721 <description>USB PHY enabled.</description>
71730 <description>Unspecified</description>
71736 <description>USB PHY parameter overrides</description>
71744 <description>PLL Integral Path Tune</description>
71750 <description>PLL Proportional Path Tune</description>
71756 <description>Disconnect Threshold Adjustment</description>
71762 <description>Squelch Threshold Adjustment</description>
71768 <description>Data Detect Voltage Adjustment</description>
71774 <description>Transmitter High-Speed Crossover Adjustment</description>
71780 <description>FS/LS Source Impedance Adjustment</description>
71786 <description>HS DC Voltage Level Adjustment</description>
71792 <description>HS Transmitter Rise/Fall Time Adjustment</description>
71798 <description>USB Source Impedance Adjustment</description>
71804 <description>HS Transmitter Pre-Emphasis Current Control</description>
71810 <description>HS Transmitter Pre-Emphasis Duration Control</description>
71818 <description>USB PHY clock configurations</description>
71826 <description>Select reference clock frequency</description>
71832 <description>Reference clock is 19.2MHz.</description>
71837 <description>Reference clock is 20MHz.</description>
71842 <description>Reference clock is 24MHz.</description>
71847 <description>Reference clock is 50MHz.</description>
71854 <description>PLL bandwidth adjustment</description>
71860 <description>PLL bandwidth adjustment disabled.</description>
71865 <description>PLL bandwidth adjustment enabled.</description>
71872 <description>Common block power down control</description>
71878 …<description>The REFCLOCK_LOGIC,bias and PLL blocks are powered in sleep or suspend mode.</descrip…
71883 …<description>The REFCLOCK_LOGIC, bias and PLL blocks are powered down in suspend mode and bias and…
71884 blocks are powered down in sleep mode.</description>
71893 … <description>Values that are used to override the input signals to the PHY.</description>
71901 <description>This field controls the pull-down resistor on D+</description>
71907 <description>The pull-down resistor on D+ is enabled</description>
71912 <description>The pull-down resistor on D+ is disabled</description>
71919 <description>This field controls the pull-down resistor on D-</description>
71925 <description>The pull-down resistor on D+ is enabled</description>
71930 <description>The pull-down resistor on D+ is disabled</description>
71947 <description>External Memory Interface</description>
71965 <description>Start operation.</description>
71973 <description>Start operation.</description>
71979 <description>Trigger task</description>
71988 <description>Stop operation.</description>
71996 <description>Stop operation.</description>
72002 <description>Trigger task</description>
72011 <description>Event indicating that interrupt triggered at EXMIF core</description>
72019 <description>Event indicating that interrupt triggered at EXMIF core</description>
72025 <description>Event not generated</description>
72030 <description>Event generated</description>
72039 …<description>Event indicating that the START task is completed and the EXMIF has started.</descrip…
72047 …<description>Event indicating that the START task is completed and the EXMIF has started.</descrip…
72053 <description>Event not generated</description>
72058 <description>Event generated</description>
72067 <description>Enable or disable interrupt</description>
72075 <description>Enable or disable interrupt for event CORE</description>
72081 <description>Disable</description>
72086 <description>Enable</description>
72093 <description>Enable or disable interrupt for event STARTED</description>
72099 <description>Disable</description>
72104 <description>Enable</description>
72113 <description>Enable interrupt</description>
72121 <description>Write '1' to enable interrupt for event CORE</description>
72128 <description>Read: Disabled</description>
72133 <description>Read: Enabled</description>
72141 <description>Enable</description>
72148 <description>Write '1' to enable interrupt for event STARTED</description>
72155 <description>Read: Disabled</description>
72160 <description>Read: Enabled</description>
72168 <description>Enable</description>
72177 <description>Disable interrupt</description>
72185 <description>Write '1' to disable interrupt for event CORE</description>
72192 <description>Read: Disabled</description>
72197 <description>Read: Enabled</description>
72205 <description>Disable</description>
72212 <description>Write '1' to disable interrupt for event STARTED</description>
72219 <description>Read: Disabled</description>
72224 <description>Read: Enabled</description>
72232 <description>Disable</description>
72241 <description>Pending interrupts</description>
72249 <description>Read pending status of interrupt for event CORE</description>
72256 <description>Read: Not pending</description>
72261 <description>Read: Pending</description>
72268 <description>Read pending status of interrupt for event STARTED</description>
72275 <description>Read: Not pending</description>
72280 <description>Read: Pending</description>
72289 <description>Configuration for external memory device 1.</description>
72295 <description>Address offset for external memory device 1.</description>
72303 <description>External memory Offset.</description>
72311 <description>Upper address range for external memory device 1.</description>
72319 <description>Upper limit address.</description>
72327 <description>Enable or disable external memory access.</description>
72335 … <description>Enable or disable external memory access from AXI interface.</description>
72341 <description>Disable external memory.</description>
72346 <description>Enable external memory.</description>
72356 <description>Configuration for external memory device 2.</description>
72363 <description>Address offset for external memory device 2.</description>
72371 <description>External memory Offset.</description>
72379 <description>Upper address range for external memory device 2.</description>
72387 <description>Upper limit address.</description>
72395 <description>Enable or disable external memory access.</description>
72403 … <description>Enable or disable external memory access from AXI interface.</description>
72409 <description>Disable external memory.</description>
72414 <description>Enable external memory.</description>
72424 <description>Unspecified</description>
72431 … <description>Enable or disable locked APB access to serial memory controller.</description>
72439 <description>Enable or disable locked APB access to SSI.</description>
72445 <description>Disable locked APB access.</description>
72450 <description>Enable locked APB access.</description>
72459 <description>Reset the external memory.</description>
72472 <description>Reset is cleared.</description>
72477 <description>Reset is set.</description>
72487 <description>Unspecified</description>
72493 <description>Unspecified</description>
72499 <description>This register controls the serial data transfer.</description>
72507 <description>Data Frame Size.</description>
72513 <description>Unspecified</description>
72518 <description>Unspecified</description>
72523 <description>Unspecified</description>
72528 <description>Unspecified</description>
72533 <description>Unspecified</description>
72538 <description>Unspecified</description>
72543 <description>Unspecified</description>
72548 <description>Unspecified</description>
72553 <description>Unspecified</description>
72558 <description>Unspecified</description>
72563 <description>Unspecified</description>
72568 <description>Unspecified</description>
72573 <description>Unspecified</description>
72578 <description>Unspecified</description>
72583 <description>Unspecified</description>
72588 <description>Unspecified</description>
72593 <description>Unspecified</description>
72598 <description>Unspecified</description>
72603 <description>Unspecified</description>
72608 <description>Unspecified</description>
72613 <description>Unspecified</description>
72618 <description>Unspecified</description>
72623 <description>Unspecified</description>
72628 <description>Unspecified</description>
72633 <description>Unspecified</description>
72638 <description>Unspecified</description>
72643 <description>Unspecified</description>
72648 <description>Unspecified</description>
72653 <description>Unspecified</description>
72658 <description>Unspecified</description>
72663 <description>Unspecified</description>
72668 <description>Unspecified</description>
72675 <description>Frame Format.</description>
72681 <description>Unspecified</description>
72686 <description>Unspecified</description>
72691 <description>Unspecified</description>
72698 <description>Serial Clock Phase.</description>
72704 <description>Unspecified</description>
72709 <description>Unspecified</description>
72716 <description>Serial Clock Polarity.</description>
72722 <description>Unspecified</description>
72727 <description>Unspecified</description>
72734 <description>Transfer Mode.</description>
72740 <description>Unspecified</description>
72745 <description>Unspecified</description>
72750 <description>Unspecified</description>
72755 <description>Unspecified</description>
72762 <description>Slave Output Enable.</description>
72768 <description>Unspecified</description>
72773 <description>Unspecified</description>
72780 <description>Shift Register Loop.</description>
72786 <description>Unspecified</description>
72791 <description>Unspecified</description>
72798 <description>Slave Select Toggle Enable.</description>
72804 <description>Unspecified</description>
72809 <description>Unspecified</description>
72816 <description>Control Frame Size.</description>
72822 <description>Unspecified</description>
72827 <description>Unspecified</description>
72832 <description>Unspecified</description>
72837 <description>Unspecified</description>
72842 <description>Unspecified</description>
72847 <description>Unspecified</description>
72852 <description>Unspecified</description>
72857 <description>Unspecified</description>
72862 <description>Unspecified</description>
72867 <description>Unspecified</description>
72872 <description>Unspecified</description>
72877 <description>Unspecified</description>
72882 <description>Unspecified</description>
72887 <description>Unspecified</description>
72892 <description>Unspecified</description>
72897 <description>Unspecified</description>
72904 <description>SPI Frame Format</description>
72910 <description>Unspecified</description>
72915 <description>Unspecified</description>
72920 <description>Unspecified</description>
72925 <description>Unspecified</description>
72932 <description>SPI Hyperbus Frame format enable.</description>
72938 <description>Unspecified</description>
72943 <description>Unspecified</description>
72950 <description>Enable Dynamic wait states in SPI mode of operation.</description>
72957 <description>Unspecified</description>
72962 <description>Unspecified</description>
72969 … <description>This field selects if DWC_ssi is working in Master or Slave mode</description>
72976 <description>Unspecified</description>
72981 <description>Unspecified</description>
72990 …<description>This register exists only when the DWC_ssi is configured as a master device.</descrip…
72998 <description>Number of Data Frames.</description>
73006 <description>This register enables and disables the DWC_ssi.</description>
73014 <description>SSI Enable.</description>
73020 <description>Unspecified</description>
73025 <description>Unspecified</description>
73034 …<description>This register controls the direction of the data word for the half-duplex Microwire s…
73042 <description>Microwire Transfer Mode.</description>
73048 <description>Unspecified</description>
73053 <description>Unspecified</description>
73060 <description>Microwire Control.</description>
73066 <description>Unspecified</description>
73071 <description>Unspecified</description>
73078 <description>Microwire Handshaking.</description>
73084 <description>Unspecified</description>
73089 <description>Unspecified</description>
73098 …<description>This register is valid only when the DWC_ssi is configured as a master device.</descr…
73106 <description>Slave Select Enable Flag.</description>
73112 <description>Unspecified</description>
73117 <description>Unspecified</description>
73126 …<description>This register is valid only when the DWC_ssi is configured as a master device.</descr…
73134 <description>SSI Clock Divider.</description>
73142 …<description>This register controls the threshold value for the transmit FIFO memory..</descriptio…
73150 <description>Transmit FIFO Threshold.</description>
73156 <description>Transfer start FIFO level.</description>
73164 …<description>This register controls the threshold value for the receive FIFO memory..</description>
73172 <description>Receive FIFO Threshold.</description>
73180 …<description>This register contains the number of valid data entries in the transmit FIFO memory.<…
73188 <description>Transmit FIFO Level.</description>
73197 …<description>This register contains the number of valid data entries in the receive FIFO memory.</…
73205 <description>Receive FIFO Level.</description>
73214 …description>This is a read-only register used to indicate the current transfer status, FIFO status…
73222 <description>SSI Busy Flag.</description>
73229 <description>Unspecified</description>
73234 <description>Unspecified</description>
73241 <description>Transmit FIFO Not Full.</description>
73248 <description>Unspecified</description>
73253 <description>Unspecified</description>
73260 <description>Transmit FIFO Empty.</description>
73267 <description>Unspecified</description>
73272 <description>Unspecified</description>
73279 <description>Receive FIFO Not Empty.</description>
73286 <description>Unspecified</description>
73291 <description>Unspecified</description>
73298 <description>Receive FIFO Full.</description>
73305 <description>Unspecified</description>
73310 <description>Unspecified</description>
73317 <description>Transmission Error.</description>
73324 <description>Unspecified</description>
73329 <description>Unspecified</description>
73336 <description>Data Collision Error.</description>
73343 <description>Unspecified</description>
73348 <description>Unspecified</description>
73357 …<description>This read/write register masks or enables all interrupts generated by the DWC_ssi.</d…
73365 <description>Transmit FIFO Empty Interrupt Mask</description>
73371 <description>Unspecified</description>
73376 <description>Unspecified</description>
73383 <description>Transmit FIFO Overflow Interrupt Mask</description>
73389 <description>Unspecified</description>
73394 <description>Unspecified</description>
73401 <description>Receive FIFO Underflow Interrupt Mask</description>
73407 <description>Unspecified</description>
73412 <description>Unspecified</description>
73419 <description>Receive FIFO Overflow Interrupt Mask</description>
73425 <description>Unspecified</description>
73430 <description>Unspecified</description>
73437 <description>Receive FIFO Full Interrupt Mask</description>
73443 <description>ssi_rxf_intr interrupt is masked</description>
73448 <description>ssi_rxf_intr interrupt is not masked</description>
73455 <description>Multi-Master Contention Interrupt Mask.</description>
73461 <description>Unspecified</description>
73466 <description>Unspecified</description>
73473 <description>XIP Receive FIFO Overflow Interrupt Mask</description>
73479 <description>Unspecified</description>
73484 <description>Unspecified</description>
73491 <description>Transmit FIFO Underflow Interrupt Mask</description>
73497 <description>Unspecified</description>
73502 <description>Unspecified</description>
73509 <description>SSI Done Interrupt Mask</description>
73516 <description>Unspecified</description>
73521 <description>Unspecified</description>
73530 …<description>This register reports the status of the DWC_ssi interrupts after they have been maske…
73538 <description>Transmit FIFO Empty Interrupt Status</description>
73545 <description>Unspecified</description>
73550 <description>Unspecified</description>
73557 <description>Transmit FIFO Overflow Interrupt Status</description>
73564 <description>Unspecified</description>
73569 <description>Unspecified</description>
73576 <description>Receive FIFO Underflow Interrupt Status</description>
73583 <description>Unspecified</description>
73588 <description>Unspecified</description>
73595 <description>Receive FIFO Overflow Interrupt Status</description>
73602 <description>Unspecified</description>
73607 <description>Unspecified</description>
73614 <description>Receive FIFO Full Interrupt Status</description>
73621 <description>Unspecified</description>
73626 <description>Unspecified</description>
73633 <description>Multi-Master Contention Interrupt Status.</description>
73640 <description>Unspecified</description>
73645 <description>Unspecified</description>
73652 <description>XIP Receive FIFO Overflow Interrupt Status</description>
73659 <description>Unspecified</description>
73664 <description>Unspecified</description>
73671 <description>Transmit FIFO Underflow Interrupt Status</description>
73678 <description>Unspecified</description>
73683 <description>Unspecified</description>
73690 <description>SSI Done Interrupt Status</description>
73697 <description>Unspecified</description>
73702 <description>Unspecified</description>
73711 <description>Raw Interrupt Status Register</description>
73719 <description>Transmit FIFO Empty Raw Interrupt Status</description>
73726 <description>Unspecified</description>
73731 <description>Unspecified</description>
73738 <description>Transmit FIFO Overflow Raw Interrupt Status</description>
73745 <description>Unspecified</description>
73750 <description>Unspecified</description>
73757 <description>Receive FIFO Underflow Raw Interrupt Status</description>
73764 <description>Unspecified</description>
73769 <description>Unspecified</description>
73776 <description>Receive FIFO Overflow Raw Interrupt Status</description>
73783 <description>Unspecified</description>
73788 <description>Unspecified</description>
73795 <description>Receive FIFO Full Raw Interrupt Status</description>
73802 <description>Unspecified</description>
73807 <description>Unspecified</description>
73814 <description>Multi-Master Contention Raw Interrupt Status.</description>
73821 <description>Unspecified</description>
73826 <description>Unspecified</description>
73833 <description>XIP Receive FIFO Overflow Raw Interrupt Status</description>
73840 <description>Unspecified</description>
73845 <description>Unspecified</description>
73852 <description>Transmit FIFO Underflow Interrupt Raw Status</description>
73859 <description>Unspecified</description>
73864 <description>Unspecified</description>
73871 <description>SSI Done Interrupt Raw Status</description>
73878 <description>Unspecified</description>
73883 <description>Unspecified</description>
73892 <description>Transmit FIFO Error Interrupt Clear Register</description>
73900 <description>Clear Transmit FIFO Overflow/Underflow Interrupt.</description>
73909 <description>Receive FIFO Overflow Interrupt Clear Register</description>
73917 <description>Clear Receive FIFO Overflow Interrupt.</description>
73926 <description>Receive FIFO Underflow Interrupt Clear Register</description>
73934 <description>Clear Receive FIFO Underflow Interrupt.</description>
73943 <description>Multi-Master Interrupt Clear Register</description>
73951 <description>Clear Multi-Master Contention Interrupt.</description>
73960 <description>Interrupt Clear Register</description>
73968 <description>Clear Interrupts.</description>
73977 …description>This register contains the peripherals identification code, which is written into the …
73985 <description>Identification code.</description>
73994 … <description>This read-only register stores the specific DWC_ssi component version.</description>
74002 … <description>Contains the hex representation of the Synopsys component version.</description>
74013 …<description>Description collection: The DWC_ssi data register is a 32-bit read/write buffer for t…
74021 <description>Data Register.</description>
74029 …<description>This register is only valid when the DWC_ssi is configured with rxd sample delay logi…
74037 <description>Receive Data (rxd) Sample Delay.</description>
74043 <description>Receive Data (rxd) Sampling Edge.</description>
74051 …<description>This register is used to control the serial data transfer in enhanced SPI mode of ope…
74059 <description>Address and instruction transfer format.</description>
74065 <description>Unspecified</description>
74070 <description>Unspecified</description>
74075 <description>Unspecified</description>
74080 <description>Unspecified</description>
74087 <description>This bit defines Length of Address to be transmitted.</description>
74093 <description>Unspecified</description>
74098 <description>Unspecified</description>
74103 <description>Unspecified</description>
74108 <description>Unspecified</description>
74113 <description>Unspecified</description>
74118 <description>Unspecified</description>
74123 <description>Unspecified</description>
74128 <description>Unspecified</description>
74133 <description>Unspecified</description>
74138 <description>Unspecified</description>
74143 <description>Unspecified</description>
74148 <description>Unspecified</description>
74153 <description>Unspecified</description>
74158 <description>Unspecified</description>
74163 <description>Unspecified</description>
74168 <description>Unspecified</description>
74175 <description>Mode bits enable in XIP mode.</description>
74182 <description>Dual/Quad/Octal mode instruction length in bits.</description>
74188 <description>Unspecified</description>
74193 <description>Unspecified</description>
74198 <description>Unspecified</description>
74203 <description>Unspecified</description>
74210 …<description>Wait cycles in Dual/Quad/Octal mode between control frames transmit and data receptio…
74216 <description>SPI DDR Enable bit.</description>
74222 <description>Instruction DDR Enable bit.</description>
74228 <description>Read data strobe enable bit.</description>
74234 <description>Fix DFS for XIP transfers.</description>
74241 <description>XIP instruction enable bit.</description>
74248 <description>Enable continuous transfer in XIP mode.</description>
74255 <description>SPI data mask enable bit.</description>
74261 …<description>Enable rxds signaling during address and command phase of Hyperbus transfer.</descrip…
74267 <description>XIP Mode bits length.</description>
74274 <description>Unspecified</description>
74279 <description>Unspecified</description>
74284 <description>Unspecified</description>
74289 <description>Unspecified</description>
74296 <description>Enables XIP pre-fetch functionality in DWC_ssi.</description>
74303 <description>Enables clock stretching capability in SPI transfers.</description>
74311 … <description>This Register is valid only when SSIC_HAS_DDR is equal to 1.</description>
74319 …<description>TXD Drive edge register which decided the driving edge of transmit data.</description>
74327 …<description>This register carries the mode bits which are sent in the XIP mode of operation after…
74335 … <description>XIP mode bits to be sent after address phase of XIP transfer.</description>
74344 <description>Unspecified</description>
74350 <description>This Register is valid only when SSIC_XIP_EN is equal to 1.</description>
74358 <description>XIP INCR transfer opcode.</description>
74366 <description>This Register is valid only when SSIC_XIP_EN is equal to 1.</description>
74374 <description>XIP WRAP transfer opcode.</description>
74382 … <description>This Register is valid only when SSIC_CONCURRENT_XIP_EN is equal to 1.</description>
74390 <description>SPI Frame Format</description>
74396 <description>Unspecified</description>
74401 <description>Unspecified</description>
74406 <description>Unspecified</description>
74411 <description>Unspecified</description>
74418 <description>Address and instruction transfer format.</description>
74424 <description>Unspecified</description>
74429 <description>Unspecified</description>
74434 <description>Unspecified</description>
74439 <description>Unspecified</description>
74446 <description>This bit defines Length of Address to be transmitted.</description>
74452 <description>Unspecified</description>
74457 <description>Unspecified</description>
74462 <description>Unspecified</description>
74467 <description>Unspecified</description>
74472 <description>Unspecified</description>
74477 <description>Unspecified</description>
74482 <description>Unspecified</description>
74487 <description>Unspecified</description>
74492 <description>Unspecified</description>
74497 <description>Unspecified</description>
74502 <description>Unspecified</description>
74507 <description>Unspecified</description>
74512 <description>Unspecified</description>
74517 <description>Unspecified</description>
74522 <description>Unspecified</description>
74527 <description>Unspecified</description>
74534 <description>Dual/Quad/Octal mode instruction length in bits.</description>
74540 <description>Unspecified</description>
74545 <description>Unspecified</description>
74550 <description>Unspecified</description>
74555 <description>Unspecified</description>
74562 <description>Mode bits enable in XIP mode.</description>
74568 …<description>Wait cycles in Dual/Quad/Octal mode between control frames transmit and data receptio…
74574 <description>Fix DFS for XIP transfers.</description>
74580 <description>SPI DDR Enable bit.</description>
74586 <description>Instruction DDR Enable bit.</description>
74592 <description>Read data strobe enable bit.</description>
74598 <description>XIP instruction enable bit.</description>
74604 <description>Enable continuous transfer in XIP mode.</description>
74611 <description>SPI Hyperbus Frame format enable for XIP transfers.</description>
74617 …<description>Enable rxds signaling during address and command phase of Hyperbus transfer.</descrip…
74623 <description>XIP Mode bits length.</description>
74629 <description>Unspecified</description>
74634 <description>Unspecified</description>
74639 <description>Unspecified</description>
74644 <description>Unspecified</description>
74651 <description>Enables XIP pre-fetch functionality in DWC_ssi.</description>
74659 <description>XIP Receive FIFO Overflow Interrupt Clear Register</description>
74667 <description>Clear XIP Receive FIFO Overflow Interrupt.</description>
74676 …<description>This Register is valid only when both SSIC_XIP_WRITE_REG_EN is set to 1.</description>
74684 <description>XIP Write INCR transfer opcode.</description>
74690 <description>Reserved bits - Read Only</description>
74699 …<description>This Register is valid only when both SSIC_XIP_WRITE_REG_EN is set to 1.</description>
74707 <description>XIP Write WRAP transfer opcode.</description>
74713 <description>Reserved bits - Read Only</description>
74722 … <description>This Register is valid only when SSIC_XIP_WRITE_REG_EN is equal to 1.</description>
74730 <description>SPI Frame Format</description>
74736 <description>Unspecified</description>
74741 <description>Unspecified</description>
74746 <description>Unspecified</description>
74751 <description>Unspecified</description>
74758 <description>Address and instruction transfer format.</description>
74764 <description>Unspecified</description>
74769 <description>Unspecified</description>
74774 <description>Unspecified</description>
74779 <description>Unspecified</description>
74786 <description>This bit defines Length of Address to be transmitted.</description>
74792 <description>Unspecified</description>
74797 <description>Unspecified</description>
74802 <description>Unspecified</description>
74807 <description>Unspecified</description>
74812 <description>Unspecified</description>
74817 <description>Unspecified</description>
74822 <description>Unspecified</description>
74827 <description>Unspecified</description>
74832 <description>Unspecified</description>
74839 <description>Dual/Quad/Octal mode instruction length in bits.</description>
74845 <description>Unspecified</description>
74850 <description>Unspecified</description>
74855 <description>Unspecified</description>
74860 <description>Unspecified</description>
74867 <description>SPI DDR Enable bit.</description>
74873 <description>Instruction DDR Enable bit.</description>
74879 … <description>SPI Hyperbus Frame format enable for XIP Write transfers.</description>
74885 …<description>Enable rxds signaling during address and command phase of Hyperbus transfer.</descrip…
74891 <description>Reserved bits - Read Only</description>
74898 …<description>Wait cycles in Dual/Quad/Octal mode between control frames transmit and data receptio…
74904 <description>Reserved bits - Read Only</description>
74917 <description>BELLBOARD public registers</description>
74935 <description>Description collection: Task TRIGGER[n]</description>
74943 <description>Task TRIGGER[n]</description>
74949 <description>Trigger task</description>
74960 <description>AUXPLL</description>
74975 <description>Start the AUXPLL</description>
74983 <description>Start the AUXPLL</description>
74989 <description>Trigger task</description>
74998 <description>Stop the AUXPLL</description>
75006 <description>Stop the AUXPLL</description>
75012 <description>Trigger task</description>
75021 <description>Change fine frequency</description>
75029 <description>Change fine frequency</description>
75035 <description>Trigger task</description>
75044 <description>Change base frequency</description>
75052 <description>Change base frequency</description>
75058 <description>Trigger task</description>
75067 <description>Start automated frequency increment</description>
75075 <description>Start automated frequency increment</description>
75081 <description>Trigger task</description>
75090 <description>Stop automated frequency increment</description>
75098 <description>Stop automated frequency increment</description>
75104 <description>Trigger task</description>
75113 <description>AUXPLL started</description>
75121 <description>AUXPLL started</description>
75127 <description>Event not generated</description>
75132 <description>Event generated</description>
75141 <description>AUXPLL stopped</description>
75149 <description>AUXPLL stopped</description>
75155 <description>Event not generated</description>
75160 <description>Event generated</description>
75169 <description>AUXPLL locked</description>
75177 <description>AUXPLL locked</description>
75183 <description>Event not generated</description>
75188 <description>Event generated</description>
75197 <description>Enable or disable interrupt</description>
75205 <description>Enable or disable interrupt for event STARTED</description>
75211 <description>Disable</description>
75216 <description>Enable</description>
75223 <description>Enable or disable interrupt for event STOPPED</description>
75229 <description>Disable</description>
75234 <description>Enable</description>
75241 <description>Enable or disable interrupt for event LOCKED</description>
75247 <description>Disable</description>
75252 <description>Enable</description>
75261 <description>Enable interrupt</description>
75269 <description>Write '1' to enable interrupt for event STARTED</description>
75276 <description>Read: Disabled</description>
75281 <description>Read: Enabled</description>
75289 <description>Enable</description>
75296 <description>Write '1' to enable interrupt for event STOPPED</description>
75303 <description>Read: Disabled</description>
75308 <description>Read: Enabled</description>
75316 <description>Enable</description>
75323 <description>Write '1' to enable interrupt for event LOCKED</description>
75330 <description>Read: Disabled</description>
75335 <description>Read: Enabled</description>
75343 <description>Enable</description>
75352 <description>Disable interrupt</description>
75360 <description>Write '1' to disable interrupt for event STARTED</description>
75367 <description>Read: Disabled</description>
75372 <description>Read: Enabled</description>
75380 <description>Disable</description>
75387 <description>Write '1' to disable interrupt for event STOPPED</description>
75394 <description>Read: Disabled</description>
75399 <description>Read: Enabled</description>
75407 <description>Disable</description>
75414 <description>Write '1' to disable interrupt for event LOCKED</description>
75421 <description>Read: Disabled</description>
75426 <description>Read: Enabled</description>
75434 <description>Disable</description>
75443 <description>Pending interrupts</description>
75451 <description>Read pending status of interrupt for event STARTED</description>
75458 <description>Read: Not pending</description>
75463 <description>Read: Pending</description>
75470 <description>Read pending status of interrupt for event STOPPED</description>
75477 <description>Read: Not pending</description>
75482 <description>Read: Pending</description>
75489 <description>Read pending status of interrupt for event LOCKED</description>
75496 <description>Read: Not pending</description>
75501 <description>Read: Pending</description>
75510 <description>Status of AUXPLL</description>
75518 <description>AUXPLL mode</description>
75524 <description>Freerunning mode</description>
75529 <description>Locked mode</description>
75536 <description>AUXPLL running status</description>
75542 <description>PLL not running</description>
75547 <description>PLL running</description>
75554 <description>Actual fractional PLL divider ratio</description>
75562 <description>Unspecified</description>
75568 <description>AUXPLL configuration</description>
75576 <description>Output buffer drive strength selection</description>
75582 <description>Lowest drive strength</description>
75587 <description>Highest drive strength</description>
75594 <description>Constant current tune for ring oscillator</description>
75600 <description>Minimum current</description>
75605 <description>Default current for audio and USB</description>
75610 <description>Maximum current</description>
75617 <description>Turn off sigma delta modulation</description>
75623 <description>Sigma Delta Modulator enabled</description>
75628 <description>Sigma Delta Modulator disabled</description>
75635 <description>Turn off dither in sigma delta modulator</description>
75641 <description>Dither enabled</description>
75646 <description>Dither disabled</description>
75653 <description>Loop divider base settings</description>
75659 <description>Low range divider setting</description>
75664 <description>Mid range divider setting</description>
75669 <description>High range divider setting</description>
75674 <description>Maximum static divider setting</description>
75684 <description>Unspecified</description>
75690 <description>Ring oscillator core process corner tuning</description>
75698 <description>Tuning value</description>
75704 <description>Highest frequency</description>
75709 <description>Default center frequency for audio and USB</description>
75714 <description>Lowest frequency</description>
75724 <description>Unspecified</description>
75730 <description>AUXPLL frequency selection</description>
75738 <description>Set fractional PLL divider ratio</description>
75744 <description>Division ratio of 4</description>
75749 <description>Division ratio for audio 44.1kHz frequency family</description>
75754 <description>Division ratio for USB PHY 24MHz clock</description>
75759 <description>Division ratio for audio 48kHz frequency family</description>
75764 <description>Division ratio of 5</description>
75773 <description>Frequency increment</description>
75781 <description>Signed 8-bit frequency increment, applied to FREQUENCY</description>
75789 <description>Frequency increment period in 1 us steps</description>
75797 <description>Frequency increment period</description>
75805 <description>AUXPLL output prescaler</description>
75813 <description>Prescaler ratio</description>
75819 … <description>Divider disabled. Bypassed external clock still supported</description>
75824 <description>Divide by 1</description>
75829 <description>Divide by 2</description>
75834 <description>Divide by 3</description>
75839 <description>Divide by 4</description>
75844 <description>Divide by 6</description>
75849 <description>Divide by 8</description>
75854 <description>Divide by 12</description>
75859 <description>Divide by 16</description>
75868 <description>Freerunning mode control</description>
75876 <description>Freerunning mode control</description>
75882 <description>Automatically handled by the AUXPLL peripheral</description>
75887 <description>Keep AUXPLL in freerunning mode</description>
75892 <description>Keep AUXPLL in locked mode</description>
75902 <description>Enable LOCK for mirrored registers</description>
75910 <description>Lock for mirrored registers</description>
75916 <description>Lock disabled</description>
75921 <description>Lock enabled</description>
75932 <description>VPR peripheral registers</description>
75949 <description>Description collection: VPR task [n] register</description>
75957 <description>VPR task [n] register</description>
75963 <description>Trigger task</description>
75974 <description>IPCT APB registers 0</description>
75996 …<description>Description collection: Trigger event on IPCT source channel n if there are no active…
76004 …<description>Trigger event on IPCT source channel n if there are no active signals present on that…
76010 <description>Trigger task</description>
76021 …<description>Description collection: Flush IPCT sink channel n. Any pending IPCT signal on that ch…
76023 configuring the SHORTS register accordingly.</description>
76031 <description>Flush IPCT sink channel n. Any pending IPCT signal on that channel will
76033 configuring the SHORTS register accordingly.</description>
76039 <description>Trigger task</description>
76050 … <description>Description collection: Subscribe configuration for task SEND[n]</description>
76058 <description>DPPI channel that task SEND[n] will subscribe to</description>
76069 <description>Disable subscription</description>
76074 <description>Enable subscription</description>
76085 … <description>Description collection: Subscribe configuration for task FLUSH[n]</description>
76093 <description>DPPI channel that task FLUSH[n] will subscribe to</description>
76104 <description>Disable subscription</description>
76109 <description>Enable subscription</description>
76120 <description>Description collection: Event received on IPCT sink channel n</description>
76128 <description>Event received on IPCT sink channel n</description>
76134 <description>Event not generated</description>
76139 <description>Event generated</description>
76150 … <description>Description collection: Event received when hardware handshake of SEND task for IPCT
76152 on that channel.</description>
76160 <description>Event received when hardware handshake of SEND task for IPCT
76162 on that channel.</description>
76168 <description>Event not generated</description>
76173 <description>Event generated</description>
76184 … <description>Description collection: Publish configuration for event RECEIVE[n]</description>
76192 <description>DPPI channel that event RECEIVE[n] will publish to</description>
76203 <description>Disable publishing</description>
76208 <description>Enable publishing</description>
76219 … <description>Description collection: Publish configuration for event READY[n]</description>
76227 <description>DPPI channel that event READY[n] will publish to</description>
76238 <description>Disable publishing</description>
76243 <description>Enable publishing</description>
76252 <description>Shortcuts between local events and tasks</description>
76260 <description>Shortcut between event RECEIVE[0] and task FLUSH[0]</description>
76266 <description>Disable shortcut</description>
76271 <description>Enable shortcut</description>
76278 <description>Shortcut between event RECEIVE[1] and task FLUSH[1]</description>
76284 <description>Disable shortcut</description>
76289 <description>Enable shortcut</description>
76296 <description>Shortcut between event RECEIVE[2] and task FLUSH[2]</description>
76302 <description>Disable shortcut</description>
76307 <description>Enable shortcut</description>
76314 <description>Shortcut between event RECEIVE[3] and task FLUSH[3]</description>
76320 <description>Disable shortcut</description>
76325 <description>Enable shortcut</description>
76332 <description>Shortcut between event RECEIVE[4] and task FLUSH[4]</description>
76338 <description>Disable shortcut</description>
76343 <description>Enable shortcut</description>
76350 <description>Shortcut between event RECEIVE[5] and task FLUSH[5]</description>
76356 <description>Disable shortcut</description>
76361 <description>Enable shortcut</description>
76368 <description>Shortcut between event RECEIVE[6] and task FLUSH[6]</description>
76374 <description>Disable shortcut</description>
76379 <description>Enable shortcut</description>
76386 <description>Shortcut between event RECEIVE[7] and task FLUSH[7]</description>
76392 <description>Disable shortcut</description>
76397 <description>Enable shortcut</description>
76406 <description>Enable or disable interrupt</description>
76414 <description>Enable or disable interrupt for event RECEIVE[0]</description>
76420 <description>Disable</description>
76425 <description>Enable</description>
76432 <description>Enable or disable interrupt for event RECEIVE[1]</description>
76438 <description>Disable</description>
76443 <description>Enable</description>
76450 <description>Enable or disable interrupt for event RECEIVE[2]</description>
76456 <description>Disable</description>
76461 <description>Enable</description>
76468 <description>Enable or disable interrupt for event RECEIVE[3]</description>
76474 <description>Disable</description>
76479 <description>Enable</description>
76486 <description>Enable or disable interrupt for event RECEIVE[4]</description>
76492 <description>Disable</description>
76497 <description>Enable</description>
76504 <description>Enable or disable interrupt for event RECEIVE[5]</description>
76510 <description>Disable</description>
76515 <description>Enable</description>
76522 <description>Enable or disable interrupt for event RECEIVE[6]</description>
76528 <description>Disable</description>
76533 <description>Enable</description>
76540 <description>Enable or disable interrupt for event RECEIVE[7]</description>
76546 <description>Disable</description>
76551 <description>Enable</description>
76558 <description>Enable or disable interrupt for event READY[0]</description>
76564 <description>Disable</description>
76569 <description>Enable</description>
76576 <description>Enable or disable interrupt for event READY[1]</description>
76582 <description>Disable</description>
76587 <description>Enable</description>
76594 <description>Enable or disable interrupt for event READY[2]</description>
76600 <description>Disable</description>
76605 <description>Enable</description>
76612 <description>Enable or disable interrupt for event READY[3]</description>
76618 <description>Disable</description>
76623 <description>Enable</description>
76630 <description>Enable or disable interrupt for event READY[4]</description>
76636 <description>Disable</description>
76641 <description>Enable</description>
76648 <description>Enable or disable interrupt for event READY[5]</description>
76654 <description>Disable</description>
76659 <description>Enable</description>
76666 <description>Enable or disable interrupt for event READY[6]</description>
76672 <description>Disable</description>
76677 <description>Enable</description>
76684 <description>Enable or disable interrupt for event READY[7]</description>
76690 <description>Disable</description>
76695 <description>Enable</description>
76704 <description>Enable interrupt</description>
76712 <description>Write '1' to enable interrupt for event RECEIVE[0]</description>
76719 <description>Read: Disabled</description>
76724 <description>Read: Enabled</description>
76732 <description>Enable</description>
76739 <description>Write '1' to enable interrupt for event RECEIVE[1]</description>
76746 <description>Read: Disabled</description>
76751 <description>Read: Enabled</description>
76759 <description>Enable</description>
76766 <description>Write '1' to enable interrupt for event RECEIVE[2]</description>
76773 <description>Read: Disabled</description>
76778 <description>Read: Enabled</description>
76786 <description>Enable</description>
76793 <description>Write '1' to enable interrupt for event RECEIVE[3]</description>
76800 <description>Read: Disabled</description>
76805 <description>Read: Enabled</description>
76813 <description>Enable</description>
76820 <description>Write '1' to enable interrupt for event RECEIVE[4]</description>
76827 <description>Read: Disabled</description>
76832 <description>Read: Enabled</description>
76840 <description>Enable</description>
76847 <description>Write '1' to enable interrupt for event RECEIVE[5]</description>
76854 <description>Read: Disabled</description>
76859 <description>Read: Enabled</description>
76867 <description>Enable</description>
76874 <description>Write '1' to enable interrupt for event RECEIVE[6]</description>
76881 <description>Read: Disabled</description>
76886 <description>Read: Enabled</description>
76894 <description>Enable</description>
76901 <description>Write '1' to enable interrupt for event RECEIVE[7]</description>
76908 <description>Read: Disabled</description>
76913 <description>Read: Enabled</description>
76921 <description>Enable</description>
76928 <description>Write '1' to enable interrupt for event READY[0]</description>
76935 <description>Read: Disabled</description>
76940 <description>Read: Enabled</description>
76948 <description>Enable</description>
76955 <description>Write '1' to enable interrupt for event READY[1]</description>
76962 <description>Read: Disabled</description>
76967 <description>Read: Enabled</description>
76975 <description>Enable</description>
76982 <description>Write '1' to enable interrupt for event READY[2]</description>
76989 <description>Read: Disabled</description>
76994 <description>Read: Enabled</description>
77002 <description>Enable</description>
77009 <description>Write '1' to enable interrupt for event READY[3]</description>
77016 <description>Read: Disabled</description>
77021 <description>Read: Enabled</description>
77029 <description>Enable</description>
77036 <description>Write '1' to enable interrupt for event READY[4]</description>
77043 <description>Read: Disabled</description>
77048 <description>Read: Enabled</description>
77056 <description>Enable</description>
77063 <description>Write '1' to enable interrupt for event READY[5]</description>
77070 <description>Read: Disabled</description>
77075 <description>Read: Enabled</description>
77083 <description>Enable</description>
77090 <description>Write '1' to enable interrupt for event READY[6]</description>
77097 <description>Read: Disabled</description>
77102 <description>Read: Enabled</description>
77110 <description>Enable</description>
77117 <description>Write '1' to enable interrupt for event READY[7]</description>
77124 <description>Read: Disabled</description>
77129 <description>Read: Enabled</description>
77137 <description>Enable</description>
77146 <description>Disable interrupt</description>
77154 <description>Write '1' to disable interrupt for event RECEIVE[0]</description>
77161 <description>Read: Disabled</description>
77166 <description>Read: Enabled</description>
77174 <description>Disable</description>
77181 <description>Write '1' to disable interrupt for event RECEIVE[1]</description>
77188 <description>Read: Disabled</description>
77193 <description>Read: Enabled</description>
77201 <description>Disable</description>
77208 <description>Write '1' to disable interrupt for event RECEIVE[2]</description>
77215 <description>Read: Disabled</description>
77220 <description>Read: Enabled</description>
77228 <description>Disable</description>
77235 <description>Write '1' to disable interrupt for event RECEIVE[3]</description>
77242 <description>Read: Disabled</description>
77247 <description>Read: Enabled</description>
77255 <description>Disable</description>
77262 <description>Write '1' to disable interrupt for event RECEIVE[4]</description>
77269 <description>Read: Disabled</description>
77274 <description>Read: Enabled</description>
77282 <description>Disable</description>
77289 <description>Write '1' to disable interrupt for event RECEIVE[5]</description>
77296 <description>Read: Disabled</description>
77301 <description>Read: Enabled</description>
77309 <description>Disable</description>
77316 <description>Write '1' to disable interrupt for event RECEIVE[6]</description>
77323 <description>Read: Disabled</description>
77328 <description>Read: Enabled</description>
77336 <description>Disable</description>
77343 <description>Write '1' to disable interrupt for event RECEIVE[7]</description>
77350 <description>Read: Disabled</description>
77355 <description>Read: Enabled</description>
77363 <description>Disable</description>
77370 <description>Write '1' to disable interrupt for event READY[0]</description>
77377 <description>Read: Disabled</description>
77382 <description>Read: Enabled</description>
77390 <description>Disable</description>
77397 <description>Write '1' to disable interrupt for event READY[1]</description>
77404 <description>Read: Disabled</description>
77409 <description>Read: Enabled</description>
77417 <description>Disable</description>
77424 <description>Write '1' to disable interrupt for event READY[2]</description>
77431 <description>Read: Disabled</description>
77436 <description>Read: Enabled</description>
77444 <description>Disable</description>
77451 <description>Write '1' to disable interrupt for event READY[3]</description>
77458 <description>Read: Disabled</description>
77463 <description>Read: Enabled</description>
77471 <description>Disable</description>
77478 <description>Write '1' to disable interrupt for event READY[4]</description>
77485 <description>Read: Disabled</description>
77490 <description>Read: Enabled</description>
77498 <description>Disable</description>
77505 <description>Write '1' to disable interrupt for event READY[5]</description>
77512 <description>Read: Disabled</description>
77517 <description>Read: Enabled</description>
77525 <description>Disable</description>
77532 <description>Write '1' to disable interrupt for event READY[6]</description>
77539 <description>Read: Disabled</description>
77544 <description>Read: Enabled</description>
77552 <description>Disable</description>
77559 <description>Write '1' to disable interrupt for event READY[7]</description>
77566 <description>Read: Disabled</description>
77571 <description>Read: Enabled</description>
77579 <description>Disable</description>
77588 <description>Pending interrupts</description>
77596 <description>Read pending status of interrupt for event RECEIVE[0]</description>
77603 <description>Read: Not pending</description>
77608 <description>Read: Pending</description>
77615 <description>Read pending status of interrupt for event RECEIVE[1]</description>
77622 <description>Read: Not pending</description>
77627 <description>Read: Pending</description>
77634 <description>Read pending status of interrupt for event RECEIVE[2]</description>
77641 <description>Read: Not pending</description>
77646 <description>Read: Pending</description>
77653 <description>Read pending status of interrupt for event RECEIVE[3]</description>
77660 <description>Read: Not pending</description>
77665 <description>Read: Pending</description>
77672 <description>Read pending status of interrupt for event RECEIVE[4]</description>
77679 <description>Read: Not pending</description>
77684 <description>Read: Pending</description>
77691 <description>Read pending status of interrupt for event RECEIVE[5]</description>
77698 <description>Read: Not pending</description>
77703 <description>Read: Pending</description>
77710 <description>Read pending status of interrupt for event RECEIVE[6]</description>
77717 <description>Read: Not pending</description>
77722 <description>Read: Pending</description>
77729 <description>Read pending status of interrupt for event RECEIVE[7]</description>
77736 <description>Read: Not pending</description>
77741 <description>Read: Pending</description>
77748 <description>Read pending status of interrupt for event READY[0]</description>
77755 <description>Read: Not pending</description>
77760 <description>Read: Pending</description>
77767 <description>Read pending status of interrupt for event READY[1]</description>
77774 <description>Read: Not pending</description>
77779 <description>Read: Pending</description>
77786 <description>Read pending status of interrupt for event READY[2]</description>
77793 <description>Read: Not pending</description>
77798 <description>Read: Pending</description>
77805 <description>Read pending status of interrupt for event READY[3]</description>
77812 <description>Read: Not pending</description>
77817 <description>Read: Pending</description>
77824 <description>Read pending status of interrupt for event READY[4]</description>
77831 <description>Read: Not pending</description>
77836 <description>Read: Pending</description>
77843 <description>Read pending status of interrupt for event READY[5]</description>
77850 <description>Read: Not pending</description>
77855 <description>Read: Pending</description>
77862 <description>Read pending status of interrupt for event READY[6]</description>
77869 <description>Read: Not pending</description>
77874 <description>Read: Pending</description>
77881 <description>Read pending status of interrupt for event READY[7]</description>
77888 <description>Read: Not pending</description>
77893 <description>Read: Pending</description>
77902 <description>Unspecified</description>
77908 <description>Overflow status for SEND tasks Write 0 to clear</description>
77916 <description>Overflow status for SEND[0] task</description>
77922 <description>Task overflow has happened</description>
77927 <description>Task overflow has not happened</description>
77934 <description>Overflow status for SEND[1] task</description>
77940 <description>Task overflow has happened</description>
77945 <description>Task overflow has not happened</description>
77952 <description>Overflow status for SEND[2] task</description>
77958 <description>Task overflow has happened</description>
77963 <description>Task overflow has not happened</description>
77970 <description>Overflow status for SEND[3] task</description>
77976 <description>Task overflow has happened</description>
77981 <description>Task overflow has not happened</description>
77988 <description>Overflow status for SEND[4] task</description>
77994 <description>Task overflow has happened</description>
77999 <description>Task overflow has not happened</description>
78006 <description>Overflow status for SEND[5] task</description>
78012 <description>Task overflow has happened</description>
78017 <description>Task overflow has not happened</description>
78024 <description>Overflow status for SEND[6] task</description>
78030 <description>Task overflow has happened</description>
78035 <description>Task overflow has not happened</description>
78042 <description>Overflow status for SEND[7] task</description>
78048 <description>Task overflow has happened</description>
78053 <description>Task overflow has not happened</description>
78065 <description>MUTEX 0</description>
78082 <description>Description collection: Mutex register</description>
78090 <description>Mutex register n</description>
78096 <description>Mutex n is in unlocked state</description>
78101 <description>Mutex n is in locked state</description>
78112 <description>I3C 0</description>
78131 <description>Event indicating that interrupt triggered at I3C core</description>
78139 <description>Event indicating that interrupt triggered at I3C core</description>
78145 <description>Event not generated</description>
78150 <description>Event generated</description>
78159 <description>Event indicating that interrupt triggered at I3C DMA</description>
78167 <description>Event indicating that interrupt triggered at I3C DMA</description>
78173 <description>Event not generated</description>
78178 <description>Event generated</description>
78187 <description>Enable or disable interrupt</description>
78195 <description>Enable or disable interrupt for event CORE</description>
78201 <description>Disable</description>
78206 <description>Enable</description>
78213 <description>Enable or disable interrupt for event DMA</description>
78219 <description>Disable</description>
78224 <description>Enable</description>
78233 <description>Enable interrupt</description>
78241 <description>Write '1' to enable interrupt for event CORE</description>
78248 <description>Read: Disabled</description>
78253 <description>Read: Enabled</description>
78261 <description>Enable</description>
78268 <description>Write '1' to enable interrupt for event DMA</description>
78275 <description>Read: Disabled</description>
78280 <description>Read: Enabled</description>
78288 <description>Enable</description>
78297 <description>Disable interrupt</description>
78305 <description>Write '1' to disable interrupt for event CORE</description>
78312 <description>Read: Disabled</description>
78317 <description>Read: Enabled</description>
78325 <description>Disable</description>
78332 <description>Write '1' to disable interrupt for event DMA</description>
78339 <description>Read: Disabled</description>
78344 <description>Read: Enabled</description>
78352 <description>Disable</description>
78361 <description>Pending interrupts</description>
78369 <description>Read pending status of interrupt for event CORE</description>
78376 <description>Read: Not pending</description>
78381 <description>Read: Pending</description>
78388 <description>Read pending status of interrupt for event DMA</description>
78395 <description>Read: Not pending</description>
78400 <description>Read: Pending</description>
78409 <description>Enable I3C peripheral.</description>
78417 <description>Enable</description>
78423 <description>I3C peripheral disabled.</description>
78428 <description>I3C peripheral enabled.</description>
78437 <description>Unspecified</description>
78443 <description>Start offset of recovered clock</description>
78451 <description>Value</description>
78459 …<description>Maximum cycle ratio between SDA/SCL and CDR (clock and data recovery) clock</descript…
78467 <description>Value</description>
78475 <description>Maximum skew between SCL and SCL in CDR clock cycles</description>
78483 <description>Value</description>
78492 <description>I3C slave interface 0</description>
78500 <description>I2C or I3C mode select signal</description>
78506 <description>Unspecified</description>
78511 <description>Unspecified</description>
78518 <description>Slave activity mode for GETSTATUS CCC</description>
78524 <description>Pending interrupt information for GETSTATUS CCC</description>
78530 <description>Slave static address valid</description>
78536 <description>Unspecified</description>
78541 <description>Unspecified</description>
78548 <description>Slave static address</description>
78554 <description>Slave maximum read data rate</description>
78560 <description>Slave maximum write write rate</description>
78566 <description>Slave maximum clock data turnaround time</description>
78572 <description>Device Characteristic Register value</description>
78580 <description>I3C slave interface 1</description>
78588 <description>Slave wakeup signal</description>
78595 <description>Unspecified</description>
78600 <description>Unspecified</description>
78609 <description>Slave Device Provisioned ID 0</description>
78617 <description>Additional Meaning</description>
78623 <description>Instance ID</description>
78629 <description>Part ID</description>
78637 <description>Slave Device Provisioned ID 1</description>
78645 <description>Provisional ID Type Selector</description>
78651 <description>MIPI Manufacturer ID</description>
78659 …<description>Enable or disable the SDA high-keeper used for Master-to-Slave and Slave-to-Master bu…
78667 <description>Enable or disable the SDA high-keeper</description>
78673 <description>High-keeper disabled.</description>
78678 <description>High-keeper enabled.</description>
78687 …<description>Enable or disable the SCL high-keeper used for Master-to-Slave and Slave-to-Master bu…
78695 <description>Enable or disable the SCL high-keeper</description>
78701 <description>High-keeper disabled.</description>
78706 <description>High-keeper enabled.</description>
78717 <description>VPR peripheral registers 0</description>
78738 <description>Description collection: VPR task [n] register</description>
78746 <description>VPR task [n] register</description>
78752 <description>Trigger task</description>
78763 …<description>Description collection: Subscribe configuration for task TASKS_TRIGGER[n]</descriptio…
78771 <description>Subscription enable bit</description>
78777 <description>Disable subscription</description>
78782 <description>Enable subscription</description>
78793 <description>Description collection: VPR event [n] register</description>
78801 <description>VPR event [n] register</description>
78807 <description>Event not generated</description>
78812 <description>Event generated</description>
78823 …<description>Description collection: Publish configuration for event EVENTS_TRIGGERED[n]</descript…
78831 <description>Publication enable bit</description>
78837 <description>Disable publishing</description>
78842 <description>Enable publishing</description>
78851 <description>Enable or disable interrupt</description>
78859 <description>Enable or disable interrupt for event TRIGGERED[0]</description>
78865 <description>Disable</description>
78870 <description>Enable</description>
78877 <description>Enable or disable interrupt for event TRIGGERED[1]</description>
78883 <description>Disable</description>
78888 <description>Enable</description>
78895 <description>Enable or disable interrupt for event TRIGGERED[2]</description>
78901 <description>Disable</description>
78906 <description>Enable</description>
78913 <description>Enable or disable interrupt for event TRIGGERED[3]</description>
78919 <description>Disable</description>
78924 <description>Enable</description>
78931 <description>Enable or disable interrupt for event TRIGGERED[4]</description>
78937 <description>Disable</description>
78942 <description>Enable</description>
78949 <description>Enable or disable interrupt for event TRIGGERED[5]</description>
78955 <description>Disable</description>
78960 <description>Enable</description>
78967 <description>Enable or disable interrupt for event TRIGGERED[6]</description>
78973 <description>Disable</description>
78978 <description>Enable</description>
78985 <description>Enable or disable interrupt for event TRIGGERED[7]</description>
78991 <description>Disable</description>
78996 <description>Enable</description>
79003 <description>Enable or disable interrupt for event TRIGGERED[8]</description>
79009 <description>Disable</description>
79014 <description>Enable</description>
79021 <description>Enable or disable interrupt for event TRIGGERED[9]</description>
79027 <description>Disable</description>
79032 <description>Enable</description>
79039 <description>Enable or disable interrupt for event TRIGGERED[10]</description>
79045 <description>Disable</description>
79050 <description>Enable</description>
79057 <description>Enable or disable interrupt for event TRIGGERED[11]</description>
79063 <description>Disable</description>
79068 <description>Enable</description>
79075 <description>Enable or disable interrupt for event TRIGGERED[12]</description>
79081 <description>Disable</description>
79086 <description>Enable</description>
79093 <description>Enable or disable interrupt for event TRIGGERED[13]</description>
79099 <description>Disable</description>
79104 <description>Enable</description>
79111 <description>Enable or disable interrupt for event TRIGGERED[14]</description>
79117 <description>Disable</description>
79122 <description>Enable</description>
79129 <description>Enable or disable interrupt for event TRIGGERED[15]</description>
79135 <description>Disable</description>
79140 <description>Enable</description>
79147 <description>Enable or disable interrupt for event TRIGGERED[16]</description>
79153 <description>Disable</description>
79158 <description>Enable</description>
79165 <description>Enable or disable interrupt for event TRIGGERED[17]</description>
79171 <description>Disable</description>
79176 <description>Enable</description>
79183 <description>Enable or disable interrupt for event TRIGGERED[18]</description>
79189 <description>Disable</description>
79194 <description>Enable</description>
79201 <description>Enable or disable interrupt for event TRIGGERED[19]</description>
79207 <description>Disable</description>
79212 <description>Enable</description>
79219 <description>Enable or disable interrupt for event TRIGGERED[20]</description>
79225 <description>Disable</description>
79230 <description>Enable</description>
79237 <description>Enable or disable interrupt for event TRIGGERED[21]</description>
79243 <description>Disable</description>
79248 <description>Enable</description>
79255 <description>Enable or disable interrupt for event TRIGGERED[22]</description>
79261 <description>Disable</description>
79266 <description>Enable</description>
79273 <description>Enable or disable interrupt for event TRIGGERED[23]</description>
79279 <description>Disable</description>
79284 <description>Enable</description>
79291 <description>Enable or disable interrupt for event TRIGGERED[24]</description>
79297 <description>Disable</description>
79302 <description>Enable</description>
79309 <description>Enable or disable interrupt for event TRIGGERED[25]</description>
79315 <description>Disable</description>
79320 <description>Enable</description>
79327 <description>Enable or disable interrupt for event TRIGGERED[26]</description>
79333 <description>Disable</description>
79338 <description>Enable</description>
79345 <description>Enable or disable interrupt for event TRIGGERED[27]</description>
79351 <description>Disable</description>
79356 <description>Enable</description>
79363 <description>Enable or disable interrupt for event TRIGGERED[28]</description>
79369 <description>Disable</description>
79374 <description>Enable</description>
79381 <description>Enable or disable interrupt for event TRIGGERED[29]</description>
79387 <description>Disable</description>
79392 <description>Enable</description>
79399 <description>Enable or disable interrupt for event TRIGGERED[30]</description>
79405 <description>Disable</description>
79410 <description>Enable</description>
79417 <description>Enable or disable interrupt for event TRIGGERED[31]</description>
79423 <description>Disable</description>
79428 <description>Enable</description>
79437 <description>Enable interrupt</description>
79445 <description>Write '1' to enable interrupt for event TRIGGERED[0]</description>
79452 <description>Read: Disabled</description>
79457 <description>Read: Enabled</description>
79465 <description>Enable</description>
79472 <description>Write '1' to enable interrupt for event TRIGGERED[1]</description>
79479 <description>Read: Disabled</description>
79484 <description>Read: Enabled</description>
79492 <description>Enable</description>
79499 <description>Write '1' to enable interrupt for event TRIGGERED[2]</description>
79506 <description>Read: Disabled</description>
79511 <description>Read: Enabled</description>
79519 <description>Enable</description>
79526 <description>Write '1' to enable interrupt for event TRIGGERED[3]</description>
79533 <description>Read: Disabled</description>
79538 <description>Read: Enabled</description>
79546 <description>Enable</description>
79553 <description>Write '1' to enable interrupt for event TRIGGERED[4]</description>
79560 <description>Read: Disabled</description>
79565 <description>Read: Enabled</description>
79573 <description>Enable</description>
79580 <description>Write '1' to enable interrupt for event TRIGGERED[5]</description>
79587 <description>Read: Disabled</description>
79592 <description>Read: Enabled</description>
79600 <description>Enable</description>
79607 <description>Write '1' to enable interrupt for event TRIGGERED[6]</description>
79614 <description>Read: Disabled</description>
79619 <description>Read: Enabled</description>
79627 <description>Enable</description>
79634 <description>Write '1' to enable interrupt for event TRIGGERED[7]</description>
79641 <description>Read: Disabled</description>
79646 <description>Read: Enabled</description>
79654 <description>Enable</description>
79661 <description>Write '1' to enable interrupt for event TRIGGERED[8]</description>
79668 <description>Read: Disabled</description>
79673 <description>Read: Enabled</description>
79681 <description>Enable</description>
79688 <description>Write '1' to enable interrupt for event TRIGGERED[9]</description>
79695 <description>Read: Disabled</description>
79700 <description>Read: Enabled</description>
79708 <description>Enable</description>
79715 <description>Write '1' to enable interrupt for event TRIGGERED[10]</description>
79722 <description>Read: Disabled</description>
79727 <description>Read: Enabled</description>
79735 <description>Enable</description>
79742 <description>Write '1' to enable interrupt for event TRIGGERED[11]</description>
79749 <description>Read: Disabled</description>
79754 <description>Read: Enabled</description>
79762 <description>Enable</description>
79769 <description>Write '1' to enable interrupt for event TRIGGERED[12]</description>
79776 <description>Read: Disabled</description>
79781 <description>Read: Enabled</description>
79789 <description>Enable</description>
79796 <description>Write '1' to enable interrupt for event TRIGGERED[13]</description>
79803 <description>Read: Disabled</description>
79808 <description>Read: Enabled</description>
79816 <description>Enable</description>
79823 <description>Write '1' to enable interrupt for event TRIGGERED[14]</description>
79830 <description>Read: Disabled</description>
79835 <description>Read: Enabled</description>
79843 <description>Enable</description>
79850 <description>Write '1' to enable interrupt for event TRIGGERED[15]</description>
79857 <description>Read: Disabled</description>
79862 <description>Read: Enabled</description>
79870 <description>Enable</description>
79877 <description>Write '1' to enable interrupt for event TRIGGERED[16]</description>
79884 <description>Read: Disabled</description>
79889 <description>Read: Enabled</description>
79897 <description>Enable</description>
79904 <description>Write '1' to enable interrupt for event TRIGGERED[17]</description>
79911 <description>Read: Disabled</description>
79916 <description>Read: Enabled</description>
79924 <description>Enable</description>
79931 <description>Write '1' to enable interrupt for event TRIGGERED[18]</description>
79938 <description>Read: Disabled</description>
79943 <description>Read: Enabled</description>
79951 <description>Enable</description>
79958 <description>Write '1' to enable interrupt for event TRIGGERED[19]</description>
79965 <description>Read: Disabled</description>
79970 <description>Read: Enabled</description>
79978 <description>Enable</description>
79985 <description>Write '1' to enable interrupt for event TRIGGERED[20]</description>
79992 <description>Read: Disabled</description>
79997 <description>Read: Enabled</description>
80005 <description>Enable</description>
80012 <description>Write '1' to enable interrupt for event TRIGGERED[21]</description>
80019 <description>Read: Disabled</description>
80024 <description>Read: Enabled</description>
80032 <description>Enable</description>
80039 <description>Write '1' to enable interrupt for event TRIGGERED[22]</description>
80046 <description>Read: Disabled</description>
80051 <description>Read: Enabled</description>
80059 <description>Enable</description>
80066 <description>Write '1' to enable interrupt for event TRIGGERED[23]</description>
80073 <description>Read: Disabled</description>
80078 <description>Read: Enabled</description>
80086 <description>Enable</description>
80093 <description>Write '1' to enable interrupt for event TRIGGERED[24]</description>
80100 <description>Read: Disabled</description>
80105 <description>Read: Enabled</description>
80113 <description>Enable</description>
80120 <description>Write '1' to enable interrupt for event TRIGGERED[25]</description>
80127 <description>Read: Disabled</description>
80132 <description>Read: Enabled</description>
80140 <description>Enable</description>
80147 <description>Write '1' to enable interrupt for event TRIGGERED[26]</description>
80154 <description>Read: Disabled</description>
80159 <description>Read: Enabled</description>
80167 <description>Enable</description>
80174 <description>Write '1' to enable interrupt for event TRIGGERED[27]</description>
80181 <description>Read: Disabled</description>
80186 <description>Read: Enabled</description>
80194 <description>Enable</description>
80201 <description>Write '1' to enable interrupt for event TRIGGERED[28]</description>
80208 <description>Read: Disabled</description>
80213 <description>Read: Enabled</description>
80221 <description>Enable</description>
80228 <description>Write '1' to enable interrupt for event TRIGGERED[29]</description>
80235 <description>Read: Disabled</description>
80240 <description>Read: Enabled</description>
80248 <description>Enable</description>
80255 <description>Write '1' to enable interrupt for event TRIGGERED[30]</description>
80262 <description>Read: Disabled</description>
80267 <description>Read: Enabled</description>
80275 <description>Enable</description>
80282 <description>Write '1' to enable interrupt for event TRIGGERED[31]</description>
80289 <description>Read: Disabled</description>
80294 <description>Read: Enabled</description>
80302 <description>Enable</description>
80311 <description>Disable interrupt</description>
80319 <description>Write '1' to disable interrupt for event TRIGGERED[0]</description>
80326 <description>Read: Disabled</description>
80331 <description>Read: Enabled</description>
80339 <description>Disable</description>
80346 <description>Write '1' to disable interrupt for event TRIGGERED[1]</description>
80353 <description>Read: Disabled</description>
80358 <description>Read: Enabled</description>
80366 <description>Disable</description>
80373 <description>Write '1' to disable interrupt for event TRIGGERED[2]</description>
80380 <description>Read: Disabled</description>
80385 <description>Read: Enabled</description>
80393 <description>Disable</description>
80400 <description>Write '1' to disable interrupt for event TRIGGERED[3]</description>
80407 <description>Read: Disabled</description>
80412 <description>Read: Enabled</description>
80420 <description>Disable</description>
80427 <description>Write '1' to disable interrupt for event TRIGGERED[4]</description>
80434 <description>Read: Disabled</description>
80439 <description>Read: Enabled</description>
80447 <description>Disable</description>
80454 <description>Write '1' to disable interrupt for event TRIGGERED[5]</description>
80461 <description>Read: Disabled</description>
80466 <description>Read: Enabled</description>
80474 <description>Disable</description>
80481 <description>Write '1' to disable interrupt for event TRIGGERED[6]</description>
80488 <description>Read: Disabled</description>
80493 <description>Read: Enabled</description>
80501 <description>Disable</description>
80508 <description>Write '1' to disable interrupt for event TRIGGERED[7]</description>
80515 <description>Read: Disabled</description>
80520 <description>Read: Enabled</description>
80528 <description>Disable</description>
80535 <description>Write '1' to disable interrupt for event TRIGGERED[8]</description>
80542 <description>Read: Disabled</description>
80547 <description>Read: Enabled</description>
80555 <description>Disable</description>
80562 <description>Write '1' to disable interrupt for event TRIGGERED[9]</description>
80569 <description>Read: Disabled</description>
80574 <description>Read: Enabled</description>
80582 <description>Disable</description>
80589 <description>Write '1' to disable interrupt for event TRIGGERED[10]</description>
80596 <description>Read: Disabled</description>
80601 <description>Read: Enabled</description>
80609 <description>Disable</description>
80616 <description>Write '1' to disable interrupt for event TRIGGERED[11]</description>
80623 <description>Read: Disabled</description>
80628 <description>Read: Enabled</description>
80636 <description>Disable</description>
80643 <description>Write '1' to disable interrupt for event TRIGGERED[12]</description>
80650 <description>Read: Disabled</description>
80655 <description>Read: Enabled</description>
80663 <description>Disable</description>
80670 <description>Write '1' to disable interrupt for event TRIGGERED[13]</description>
80677 <description>Read: Disabled</description>
80682 <description>Read: Enabled</description>
80690 <description>Disable</description>
80697 <description>Write '1' to disable interrupt for event TRIGGERED[14]</description>
80704 <description>Read: Disabled</description>
80709 <description>Read: Enabled</description>
80717 <description>Disable</description>
80724 <description>Write '1' to disable interrupt for event TRIGGERED[15]</description>
80731 <description>Read: Disabled</description>
80736 <description>Read: Enabled</description>
80744 <description>Disable</description>
80751 <description>Write '1' to disable interrupt for event TRIGGERED[16]</description>
80758 <description>Read: Disabled</description>
80763 <description>Read: Enabled</description>
80771 <description>Disable</description>
80778 <description>Write '1' to disable interrupt for event TRIGGERED[17]</description>
80785 <description>Read: Disabled</description>
80790 <description>Read: Enabled</description>
80798 <description>Disable</description>
80805 <description>Write '1' to disable interrupt for event TRIGGERED[18]</description>
80812 <description>Read: Disabled</description>
80817 <description>Read: Enabled</description>
80825 <description>Disable</description>
80832 <description>Write '1' to disable interrupt for event TRIGGERED[19]</description>
80839 <description>Read: Disabled</description>
80844 <description>Read: Enabled</description>
80852 <description>Disable</description>
80859 <description>Write '1' to disable interrupt for event TRIGGERED[20]</description>
80866 <description>Read: Disabled</description>
80871 <description>Read: Enabled</description>
80879 <description>Disable</description>
80886 <description>Write '1' to disable interrupt for event TRIGGERED[21]</description>
80893 <description>Read: Disabled</description>
80898 <description>Read: Enabled</description>
80906 <description>Disable</description>
80913 <description>Write '1' to disable interrupt for event TRIGGERED[22]</description>
80920 <description>Read: Disabled</description>
80925 <description>Read: Enabled</description>
80933 <description>Disable</description>
80940 <description>Write '1' to disable interrupt for event TRIGGERED[23]</description>
80947 <description>Read: Disabled</description>
80952 <description>Read: Enabled</description>
80960 <description>Disable</description>
80967 <description>Write '1' to disable interrupt for event TRIGGERED[24]</description>
80974 <description>Read: Disabled</description>
80979 <description>Read: Enabled</description>
80987 <description>Disable</description>
80994 <description>Write '1' to disable interrupt for event TRIGGERED[25]</description>
81001 <description>Read: Disabled</description>
81006 <description>Read: Enabled</description>
81014 <description>Disable</description>
81021 <description>Write '1' to disable interrupt for event TRIGGERED[26]</description>
81028 <description>Read: Disabled</description>
81033 <description>Read: Enabled</description>
81041 <description>Disable</description>
81048 <description>Write '1' to disable interrupt for event TRIGGERED[27]</description>
81055 <description>Read: Disabled</description>
81060 <description>Read: Enabled</description>
81068 <description>Disable</description>
81075 <description>Write '1' to disable interrupt for event TRIGGERED[28]</description>
81082 <description>Read: Disabled</description>
81087 <description>Read: Enabled</description>
81095 <description>Disable</description>
81102 <description>Write '1' to disable interrupt for event TRIGGERED[29]</description>
81109 <description>Read: Disabled</description>
81114 <description>Read: Enabled</description>
81122 <description>Disable</description>
81129 <description>Write '1' to disable interrupt for event TRIGGERED[30]</description>
81136 <description>Read: Disabled</description>
81141 <description>Read: Enabled</description>
81149 <description>Disable</description>
81156 <description>Write '1' to disable interrupt for event TRIGGERED[31]</description>
81163 <description>Read: Disabled</description>
81168 <description>Read: Enabled</description>
81176 <description>Disable</description>
81185 <description>Pending interrupts</description>
81193 <description>Read pending status of interrupt for event TRIGGERED[0]</description>
81200 <description>Read: Not pending</description>
81205 <description>Read: Pending</description>
81212 <description>Read pending status of interrupt for event TRIGGERED[1]</description>
81219 <description>Read: Not pending</description>
81224 <description>Read: Pending</description>
81231 <description>Read pending status of interrupt for event TRIGGERED[2]</description>
81238 <description>Read: Not pending</description>
81243 <description>Read: Pending</description>
81250 <description>Read pending status of interrupt for event TRIGGERED[3]</description>
81257 <description>Read: Not pending</description>
81262 <description>Read: Pending</description>
81269 <description>Read pending status of interrupt for event TRIGGERED[4]</description>
81276 <description>Read: Not pending</description>
81281 <description>Read: Pending</description>
81288 <description>Read pending status of interrupt for event TRIGGERED[5]</description>
81295 <description>Read: Not pending</description>
81300 <description>Read: Pending</description>
81307 <description>Read pending status of interrupt for event TRIGGERED[6]</description>
81314 <description>Read: Not pending</description>
81319 <description>Read: Pending</description>
81326 <description>Read pending status of interrupt for event TRIGGERED[7]</description>
81333 <description>Read: Not pending</description>
81338 <description>Read: Pending</description>
81345 <description>Read pending status of interrupt for event TRIGGERED[8]</description>
81352 <description>Read: Not pending</description>
81357 <description>Read: Pending</description>
81364 <description>Read pending status of interrupt for event TRIGGERED[9]</description>
81371 <description>Read: Not pending</description>
81376 <description>Read: Pending</description>
81383 <description>Read pending status of interrupt for event TRIGGERED[10]</description>
81390 <description>Read: Not pending</description>
81395 <description>Read: Pending</description>
81402 <description>Read pending status of interrupt for event TRIGGERED[11]</description>
81409 <description>Read: Not pending</description>
81414 <description>Read: Pending</description>
81421 <description>Read pending status of interrupt for event TRIGGERED[12]</description>
81428 <description>Read: Not pending</description>
81433 <description>Read: Pending</description>
81440 <description>Read pending status of interrupt for event TRIGGERED[13]</description>
81447 <description>Read: Not pending</description>
81452 <description>Read: Pending</description>
81459 <description>Read pending status of interrupt for event TRIGGERED[14]</description>
81466 <description>Read: Not pending</description>
81471 <description>Read: Pending</description>
81478 <description>Read pending status of interrupt for event TRIGGERED[15]</description>
81485 <description>Read: Not pending</description>
81490 <description>Read: Pending</description>
81497 <description>Read pending status of interrupt for event TRIGGERED[16]</description>
81504 <description>Read: Not pending</description>
81509 <description>Read: Pending</description>
81516 <description>Read pending status of interrupt for event TRIGGERED[17]</description>
81523 <description>Read: Not pending</description>
81528 <description>Read: Pending</description>
81535 <description>Read pending status of interrupt for event TRIGGERED[18]</description>
81542 <description>Read: Not pending</description>
81547 <description>Read: Pending</description>
81554 <description>Read pending status of interrupt for event TRIGGERED[19]</description>
81561 <description>Read: Not pending</description>
81566 <description>Read: Pending</description>
81573 <description>Read pending status of interrupt for event TRIGGERED[20]</description>
81580 <description>Read: Not pending</description>
81585 <description>Read: Pending</description>
81592 <description>Read pending status of interrupt for event TRIGGERED[21]</description>
81599 <description>Read: Not pending</description>
81604 <description>Read: Pending</description>
81611 <description>Read pending status of interrupt for event TRIGGERED[22]</description>
81618 <description>Read: Not pending</description>
81623 <description>Read: Pending</description>
81630 <description>Read pending status of interrupt for event TRIGGERED[23]</description>
81637 <description>Read: Not pending</description>
81642 <description>Read: Pending</description>
81649 <description>Read pending status of interrupt for event TRIGGERED[24]</description>
81656 <description>Read: Not pending</description>
81661 <description>Read: Pending</description>
81668 <description>Read pending status of interrupt for event TRIGGERED[25]</description>
81675 <description>Read: Not pending</description>
81680 <description>Read: Pending</description>
81687 <description>Read pending status of interrupt for event TRIGGERED[26]</description>
81694 <description>Read: Not pending</description>
81699 <description>Read: Pending</description>
81706 <description>Read pending status of interrupt for event TRIGGERED[27]</description>
81713 <description>Read: Not pending</description>
81718 <description>Read: Pending</description>
81725 <description>Read pending status of interrupt for event TRIGGERED[28]</description>
81732 <description>Read: Not pending</description>
81737 <description>Read: Pending</description>
81744 <description>Read pending status of interrupt for event TRIGGERED[29]</description>
81751 <description>Read: Not pending</description>
81756 <description>Read: Pending</description>
81763 <description>Read pending status of interrupt for event TRIGGERED[30]</description>
81770 <description>Read: Not pending</description>
81775 <description>Read: Pending</description>
81782 <description>Read pending status of interrupt for event TRIGGERED[31]</description>
81789 <description>Read: Not pending</description>
81794 <description>Read: Pending</description>
81803 <description>Unspecified</description>
81809 <description>Abstract Data 0. Read/write data for argument 0</description>
81817 <description>Abstract Data 0</description>
81825 <description>Abstract Data 1. Read/write data for argument 1</description>
81833 <description>Abstract Data 1</description>
81841 <description>Debug Module Control</description>
81849 <description>Reset signal for the debug module.</description>
81855 <description>Reset the debug module itself</description>
81860 <description>Normal operation</description>
81867 <description>Reset signal output from the debug module to the system.</description>
81873 <description>Reset inactive</description>
81878 <description>Reset active</description>
81885 <description>Clear the halt on reset request.</description>
81892 <description>No operation when written 0.</description>
81897 <description>Clears the halt on reset request</description>
81904 <description>Set the halt on reset request.</description>
81911 <description>No operation when written 0.</description>
81916 <description>Sets the halt on reset request</description>
81923 <description>The high 10 bits of hartsel.</description>
81930 <description>The low 10 bits of hartsel.</description>
81937 <description>Definition of currently selected harts.</description>
81944 <description>Single hart selected.</description>
81949 <description>Multiple harts selected</description>
81956 <description>Clear the havereset.</description>
81963 <description>No operation when written 0.</description>
81968 <description>Clears the havereset for selected harts.</description>
81975 <description>Reset harts.</description>
81981 <description>Reset de-asserted.</description>
81986 <description>Reset asserted.</description>
81993 <description>Resume currently selected harts.</description>
82000 <description>No operation when written 0.</description>
82005 <description>Currently selected harts resumed.</description>
82012 <description>Halt currently selected harts.</description>
82019 … <description>Clears halt request bit for all currently selected harts.</description>
82024 <description>Currently selected harts halted.</description>
82033 <description>Debug Module Status</description>
82041 <description>Version of the debug module.</description>
82047 <description>Debug module not present.</description>
82052 …<description>There is a Debug Module and it conforms to version 0.11 of this specifcation.</descri…
82057 …<description>There is a Debug Module and it conforms to version 0.13 of this specifcation.</descri…
82062 …<description>There is a Debug Module but it does not conform to any available version of the spec.…
82069 <description>Configuration string.</description>
82075 …<description>The confstrptr0..confstrptr3 holds information which is not relevant to the configura…
82080 …<description>The confstrptr0..confstrptr3 holds the address of the configuration string.</descript…
82087 <description>Halt-on-reset support status.</description>
82093 <description>Halt-on-reset is supported.</description>
82098 <description>Halt-on-reset is not supported.</description>
82105 <description>Authentication busy status.</description>
82111 <description>The authentication module is ready.</description>
82116 <description>The authentication module is busy.</description>
82123 <description>Authentication status.</description>
82129 … <description>Authentication required before using the debug module.</description>
82134 <description>Authentication passed.</description>
82141 <description>Any currently selected harts halted status.</description>
82147 <description>None of the currently selected harts halted.</description>
82152 <description>Any of the currently selected harts halted.</description>
82159 <description>All currently selected harts halted status.</description>
82165 <description>Not all of the currently selected harts halted.</description>
82170 <description>All of the currently selected harts halted.</description>
82177 <description>Any currently selected harts running status.</description>
82183 <description>None of the currently selected harts running.</description>
82188 <description>Any of the currently selected harts running.</description>
82195 <description>All currently selected harts running status.</description>
82201 <description>Not all of the currently selected harts running.</description>
82206 <description>All of the currently selected harts running.</description>
82213 <description>Any currently selected harts unavailable status.</description>
82219 <description>None of the currently selected harts unavailable.</description>
82224 <description>Any of the currently selected harts unavailable.</description>
82231 <description>All currently selected harts unavailable status.</description>
82237 <description>Not all of the currently selected harts unavailable.</description>
82242 <description>All of the currently selected harts unavailable.</description>
82249 <description>Any currently selected harts nonexistent status.</description>
82255 <description>None of the currently selected harts nonexistent.</description>
82260 <description>Any of the currently selected harts nonexistent.</description>
82267 <description>All currently selected harts nonexistent status.</description>
82273 <description>Not all of the currently selected harts nonexistent.</description>
82278 <description>All of the currently selected harts nonexistent.</description>
82285 … <description>Any currently selected harts acknowledged last resume request.</description>
82291 … <description>None of the currently selected harts acknowledged last resume request.</description>
82296 … <description>Any of the currently selected harts acknowledged last resume request.</description>
82303 <description>All currently selected harts acknowledged last resume</description>
82309 …<description>Not all of the currently selected harts acknowledged last resume request.</descriptio…
82314 … <description>All of the currently selected harts acknowledged last resume request.</description>
82321 …<description>Any currently selected harts have been reset and reset is not acknowledged.</descript…
82327 …<description>None of the currently selected harts have been reset and reset is not acknowledget.</…
82332 …<description>Any of the currently selected harts have been reset and reset is not acknowledge.</de…
82339 …<description>All currently selected harts have been reset and reset is not acknowledge</descriptio…
82345 …<description>Not all of the currently selected harts have been reset and reset is not acknowledge.…
82350 …<description>All of the currently selected harts have been reset and reset is not acknowledge.</de…
82357 …<description>Implicit ebreak instruction at the non-existent word immediately after the Program Bu…
82363 <description>No implicit ebreak instruction.</description>
82368 <description>Implicit ebreak instruction.</description>
82377 <description>Hart Information</description>
82385 <description>Data Address</description>
82392 <description>Data Size</description>
82399 <description>Data Access</description>
82406 <description>The data registers are shadowed in the hart
82408 corresponds to a single argument.</description>
82413 <description>The data registers are shadowed in the hart's
82415 the memory map.</description>
82422 <description>Number of dscratch registers</description>
82431 <description>Halt Summary 1</description>
82439 <description>Halt Summary 1</description>
82448 <description>Hart Array Window Select</description>
82456 …<description>The high bits of this field may be tied to 0, depending on how large the array mask r…
82457 … E.g. on a system with 48 harts only bit 0 of this field may actually be writable.</description>
82466 <description>Hart Array Window</description>
82474 <description>Mask data.</description>
82482 <description>Abstract Control and Status</description>
82490 …<description>Number of data registers that are implemented as part of the abstract command interfa…
82497 <description>Command error when the abstract command fails.</description>
82503 <description>No error.</description>
82508 <description>An abstract command was executing while command,
82510 or written. This status is only written if cmderr contains 0</description>
82515 <description>The requested command is notsupported,
82516 regardless of whether the hart is running or not.</description>
82521 <description>An exception occurred while executing the
82522 command (e.g. while executing theProgram Buffer).</description>
82527 <description>The abstract command couldn't execute
82528 … because the hart wasn't in the required state (running/halted). or unavailable.</description>
82533 <description>The abstract command failed due to abus
82534 error (e.g. alignment, access size, or timeout).</description>
82539 <description>The command failed for another reason.</description>
82546 <description>Abstract command execution status.</description>
82553 <description>Not busy.</description>
82558 <description>An abstract command is currently being executed.
82559 …t as soon as command is written, and is not cleared until that command has completed.</description>
82566 … <description>Size of the Program Buffer, in 32-bit words. Valid sizes are 0 - 1.</description>
82575 <description>Abstract command</description>
82583 …<description>This Field is interpreted in a command specific manner, described for each abstract c…
82589 … <description>The type determines the overall functionality of this abstract command.</description>
82595 <description>Register Access Command</description>
82600 <description>Quick Access Command</description>
82605 <description>Memory Access Command</description>
82614 <description>Abstract Command Autoexec</description>
82622 …<description>When a bit in this field is 1, read or write accesses to the corresponding data word …
82623 command in command to be executed again.</description>
82630 …<description>When a bit in this field is 1, read or write accesses to the corresponding progbuf wo…
82631 the command in command to be executed again.</description>
82642 <description>Description collection: Configuration String Pointer [n]</description>
82650 <description>Address</description>
82659 <description>Next Debug Module</description>
82667 <description>Address</description>
82678 <description>Description collection: Program Buffer [n]</description>
82686 <description>Data</description>
82695 <description>Authentication Data</description>
82703 <description>Data</description>
82712 <description>Halt Summary 2</description>
82720 <description>Halt Summary 2</description>
82729 <description>Halt Summary 3</description>
82737 <description>Halt Summary 3</description>
82746 <description>System Bus Addres 127:96</description>
82754 <description>Accesses bits 127:96 of the physical address in
82756 wide).</description>
82765 <description>System Bus Access Control and Status</description>
82779 <description>8-bit system bus accesses are supported.</description>
82792 <description>16-bit system bus accesses are supported.</description>
82805 <description>32-bit system bus accesses are supported.</description>
82818 <description>64-bit system bus accesses are supported.</description>
82831 <description>128-bit system bus accesses are supported.</description>
82838 …<description>Width of system bus addresses in bits. (0 indicates there is no bus access support.)<…
82851 <description>There was no bus error.</description>
82856 <description>There was a timeout.</description>
82861 <description>A bad address was accessed.</description>
82866 <description>There was an alignment error.</description>
82871 <description>An access of unsupported size was requested.</description>
82876 <description>Other.</description>
82889 <description>Every read from sbdata0 automatically
82890 triggers a system bus read at the (possibly autoincremented) address.</description>
82903 <description>sbaddress is incremented by the access
82904 size (in bytes) selected in sbaccess after every system bus access.</description>
82917 <description>8-bit.</description>
82922 <description>16-bit.</description>
82927 <description>32-bit.</description>
82932 <description>64-bit.</description>
82937 <description>128-bit.</description>
82950 <description>Every write to sbaddress0 automatically
82951 triggers a system bus read at the new address.</description>
82964 <description>System bus master is not busy.</description>
82969 <description>System bus master is busy.</description>
82982 <description>No error.</description>
82987 <description>Debugger access attempted while one in progress.</description>
83000 <description>The System Bus interface conforms to mainline
83001 … drafts of thia RISC-V External Debug Support spec older than 1 January, 2018.</description>
83006 …<description>The System Bus interface conforms to RISC-V External Debug Support version 0.14.0-DRA…
83007 Other values are reserved for future versions.</description>
83016 <description>System Bus Addres 31:0</description>
83024 <description>Accesses bits 31:0 of the physical address in
83025 sbaddress.</description>
83034 <description>System Bus Addres 63:32</description>
83042 <description>Accesses bits 63:32 of the physical address in
83044 wide).</description>
83053 <description>System Bus Addres 95:64</description>
83061 <description>Accesses bits 95:64 of the physical address in
83063 wide).</description>
83072 <description>System Bus Data 31:0</description>
83080 <description>Accesses bits 31:0 of sbdata</description>
83089 <description>System Bus Data 63:32</description>
83097 <description>Accesses bits 63:32 of sbdata (if the system bus
83098 is that wide).</description>
83107 <description>System Bus Data 95:64</description>
83115 <description>Accesses bits 95:64 of sbdata (if the system bus
83116 is that wide).</description>
83125 <description>System Bus Data 127:96</description>
83133 <description>Accesses bits 127:96 of sbdata (if the system bus
83134 is that wide).</description>
83143 <description>Halt summary 0</description>
83151 <description>Halt summary 0</description>
83161 <description>State of the CPU after a core reset</description>
83169 <description>Controls CPU running state after a core reset.</description>
83175 …<description>CPU stopped. If this is the CPU state after a core reset, setting this bit will chang…
83180 …description>CPU running. If this is the CPU state after a core reset, clearing this bit will chang…
83189 <description>Initial value of the PC at CPU start.</description>
83197 <description>Initial value of the PC at CPU start.</description>
83207 <description>Controller Area Network</description>
83226 <description>Start the CAN peripheral.</description>
83234 <description>Start the CAN peripheral.</description>
83240 <description>Trigger task</description>
83249 <description>Request to stop the CAN peripheral</description>
83257 <description>Request to stop the CAN peripheral</description>
83263 <description>Trigger task</description>
83272 <description>Stop the CAN peripheral</description>
83280 <description>Stop the CAN peripheral</description>
83286 <description>Trigger task</description>
83297 …<description>Description collection: Event indicating that interrupt n triggered at CAN core</desc…
83305 <description>Event indicating that interrupt n triggered at CAN core</description>
83311 <description>Event not generated</description>
83316 <description>Event generated</description>
83325 <description>Event indicating that interrupt triggered at CAN DMU</description>
83333 <description>Event indicating that interrupt triggered at CAN DMU</description>
83339 <description>Event not generated</description>
83344 <description>Event generated</description>
83353 <description>Event indicating that interrupt triggered at CAN DMA</description>
83361 <description>Event indicating that interrupt triggered at CAN DMA</description>
83367 <description>Event not generated</description>
83372 <description>Event generated</description>
83381 <description>Event indicating that the CAN is ready to be stopped</description>
83389 <description>Event indicating that the CAN is ready to be stopped</description>
83395 <description>Event not generated</description>
83400 <description>Event generated</description>
83409 <description>Shortcuts between local events and tasks</description>
83417 <description>Shortcut between event READYFORSTOP and task STOP</description>
83423 <description>Disable shortcut</description>
83428 <description>Enable shortcut</description>
83437 <description>Enable or disable interrupt</description>
83445 <description>Enable or disable interrupt for event CORE[0]</description>
83451 <description>Disable</description>
83456 <description>Enable</description>
83463 <description>Enable or disable interrupt for event CORE[1]</description>
83469 <description>Disable</description>
83474 <description>Enable</description>
83481 <description>Enable or disable interrupt for event DMU</description>
83487 <description>Disable</description>
83492 <description>Enable</description>
83499 <description>Enable or disable interrupt for event DMA</description>
83505 <description>Disable</description>
83510 <description>Enable</description>
83517 <description>Enable or disable interrupt for event READYFORSTOP</description>
83523 <description>Disable</description>
83528 <description>Enable</description>
83537 <description>Enable interrupt</description>
83545 <description>Write '1' to enable interrupt for event CORE[0]</description>
83552 <description>Read: Disabled</description>
83557 <description>Read: Enabled</description>
83565 <description>Enable</description>
83572 <description>Write '1' to enable interrupt for event CORE[1]</description>
83579 <description>Read: Disabled</description>
83584 <description>Read: Enabled</description>
83592 <description>Enable</description>
83599 <description>Write '1' to enable interrupt for event DMU</description>
83606 <description>Read: Disabled</description>
83611 <description>Read: Enabled</description>
83619 <description>Enable</description>
83626 <description>Write '1' to enable interrupt for event DMA</description>
83633 <description>Read: Disabled</description>
83638 <description>Read: Enabled</description>
83646 <description>Enable</description>
83653 <description>Write '1' to enable interrupt for event READYFORSTOP</description>
83660 <description>Read: Disabled</description>
83665 <description>Read: Enabled</description>
83673 <description>Enable</description>
83682 <description>Disable interrupt</description>
83690 <description>Write '1' to disable interrupt for event CORE[0]</description>
83697 <description>Read: Disabled</description>
83702 <description>Read: Enabled</description>
83710 <description>Disable</description>
83717 <description>Write '1' to disable interrupt for event CORE[1]</description>
83724 <description>Read: Disabled</description>
83729 <description>Read: Enabled</description>
83737 <description>Disable</description>
83744 <description>Write '1' to disable interrupt for event DMU</description>
83751 <description>Read: Disabled</description>
83756 <description>Read: Enabled</description>
83764 <description>Disable</description>
83771 <description>Write '1' to disable interrupt for event DMA</description>
83778 <description>Read: Disabled</description>
83783 <description>Read: Enabled</description>
83791 <description>Disable</description>
83798 <description>Write '1' to disable interrupt for event READYFORSTOP</description>
83805 <description>Read: Disabled</description>
83810 <description>Read: Enabled</description>
83818 <description>Disable</description>
83827 <description>Pending interrupts</description>
83835 <description>Read pending status of interrupt for event CORE[0]</description>
83842 <description>Read: Not pending</description>
83847 <description>Read: Pending</description>
83854 <description>Read pending status of interrupt for event CORE[1]</description>
83861 <description>Read: Not pending</description>
83866 <description>Read: Pending</description>
83873 <description>Read pending status of interrupt for event DMU</description>
83880 <description>Read: Not pending</description>
83885 <description>Read: Pending</description>
83892 <description>Read pending status of interrupt for event DMA</description>
83899 <description>Read: Not pending</description>
83904 <description>Read: Pending</description>
83911 <description>Read pending status of interrupt for event READYFORSTOP</description>
83918 <description>Read: Not pending</description>
83923 <description>Read: Pending</description>
83934 …description>MVDMA performs direct-memory-accesses between memories. Data is transferred according …
83953 <description>Pause operation.</description>
83961 <description>Pause operation.</description>
83967 <description>Trigger task</description>
83976 <description>Reset operation.</description>
83984 <description>Reset operation.</description>
83990 <description>Trigger task</description>
84001 …<description>Description collection: Start operation of job list n. Base address for successive TA…
84009 …<description>Start operation of job list n. Base address for successive TASKS_STARTs.</description>
84015 <description>Trigger task</description>
84026 … <description>Description collection: Subscribe configuration for task START[n]</description>
84034 <description>DPPI channel that task START[n] will subscribe to</description>
84045 <description>Disable subscription</description>
84050 <description>Enable subscription</description>
84059 … <description>Event indicating that Sink data descriptor list has been completed.</description>
84067 … <description>Event indicating that Sink data descriptor list has been completed.</description>
84073 <description>Event not generated</description>
84078 <description>Event generated</description>
84087 <description>Event indicating that the source list processing has started.</description>
84095 … <description>Event indicating that the source list processing has started.</description>
84101 <description>Event not generated</description>
84106 <description>Event generated</description>
84115 <description>Event indicating that the data transfer has been paused.</description>
84123 <description>Event indicating that the data transfer has been paused.</description>
84129 <description>Event not generated</description>
84134 <description>Event generated</description>
84143 <description>Event indicating that the peripheral has been reset.</description>
84151 <description>Event indicating that the peripheral has been reset.</description>
84157 <description>Event not generated</description>
84162 <description>Event generated</description>
84171 <description>Peripheral events.</description>
84177 …<description>Event indicating that a bus error has been received on the Source channel.</descripti…
84185 …<description>Event indicating that a bus error has been received on the Source channel.</descripti…
84191 <description>Event not generated</description>
84196 <description>Event generated</description>
84205 …<description>Event indicating that a job on the Source channel with EVENT_ENABLE active has been p…
84213 …<description>Event indicating that a job on the Source channel with EVENT_ENABLE active has been p…
84219 <description>Event not generated</description>
84224 <description>Event generated</description>
84234 <description>Peripheral events.</description>
84240 …<description>Event indicating that a bus error has been received on the Sink channel.</description>
84248 …<description>Event indicating that a bus error has been received on the Sink channel.</description>
84254 <description>Event not generated</description>
84259 <description>Event generated</description>
84268 …<description>Event indicating that a job on the Sink channel with EVENT_ENABLE active has been pro…
84276 …<description>Event indicating that a job on the Sink channel with EVENT_ENABLE active has been pro…
84282 <description>Event not generated</description>
84287 <description>Event generated</description>
84299 …description>Description collection: Event indicating that the operation started by the task START[…
84307 …description>Event indicating that the operation started by the task START[n] has been completed. B…
84313 <description>Event not generated</description>
84318 <description>Event generated</description>
84327 <description>Publish configuration for event END</description>
84335 <description>DPPI channel that event END will publish to</description>
84346 <description>Disable publishing</description>
84351 <description>Enable publishing</description>
84360 <description>Publish configuration for events</description>
84366 <description>Publish configuration for event SOURCE.SELECTJOBDONE</description>
84374 … <description>DPPI channel that event SOURCE.SELECTJOBDONE will publish to</description>
84385 <description>Disable publishing</description>
84390 <description>Enable publishing</description>
84400 <description>Publish configuration for events</description>
84406 <description>Publish configuration for event SINK.SELECTJOBDONE</description>
84414 … <description>DPPI channel that event SINK.SELECTJOBDONE will publish to</description>
84425 <description>Disable publishing</description>
84430 <description>Enable publishing</description>
84442 … <description>Description collection: Publish configuration for event COMPLETED[n]</description>
84450 <description>DPPI channel that event COMPLETED[n] will publish to</description>
84461 <description>Disable publishing</description>
84466 <description>Enable publishing</description>
84475 <description>Enable or disable interrupt</description>
84483 <description>Enable or disable interrupt for event END</description>
84489 <description>Disable</description>
84494 <description>Enable</description>
84501 <description>Enable or disable interrupt for event STARTED</description>
84507 <description>Disable</description>
84512 <description>Enable</description>
84519 <description>Enable or disable interrupt for event PAUSED</description>
84525 <description>Disable</description>
84530 <description>Enable</description>
84537 <description>Enable or disable interrupt for event RESET</description>
84543 <description>Disable</description>
84548 <description>Enable</description>
84555 <description>Enable or disable interrupt for event SOURCEBUSERROR</description>
84561 <description>Disable</description>
84566 <description>Enable</description>
84573 <description>Enable or disable interrupt for event SOURCESELECTJOBDONE</description>
84579 <description>Disable</description>
84584 <description>Enable</description>
84591 <description>Enable or disable interrupt for event SINKBUSERROR</description>
84597 <description>Disable</description>
84602 <description>Enable</description>
84609 <description>Enable or disable interrupt for event SINKSELECTJOBDONE</description>
84615 <description>Disable</description>
84620 <description>Enable</description>
84627 <description>Enable or disable interrupt for event COMPLETED[0]</description>
84633 <description>Disable</description>
84638 <description>Enable</description>
84645 <description>Enable or disable interrupt for event COMPLETED[1]</description>
84651 <description>Disable</description>
84656 <description>Enable</description>
84663 <description>Enable or disable interrupt for event COMPLETED[2]</description>
84669 <description>Disable</description>
84674 <description>Enable</description>
84681 <description>Enable or disable interrupt for event COMPLETED[3]</description>
84687 <description>Disable</description>
84692 <description>Enable</description>
84699 <description>Enable or disable interrupt for event COMPLETED[4]</description>
84705 <description>Disable</description>
84710 <description>Enable</description>
84717 <description>Enable or disable interrupt for event COMPLETED[5]</description>
84723 <description>Disable</description>
84728 <description>Enable</description>
84735 <description>Enable or disable interrupt for event COMPLETED[6]</description>
84741 <description>Disable</description>
84746 <description>Enable</description>
84753 <description>Enable or disable interrupt for event COMPLETED[7]</description>
84759 <description>Disable</description>
84764 <description>Enable</description>
84773 <description>Enable interrupt</description>
84781 <description>Write '1' to enable interrupt for event END</description>
84788 <description>Read: Disabled</description>
84793 <description>Read: Enabled</description>
84801 <description>Enable</description>
84808 <description>Write '1' to enable interrupt for event STARTED</description>
84815 <description>Read: Disabled</description>
84820 <description>Read: Enabled</description>
84828 <description>Enable</description>
84835 <description>Write '1' to enable interrupt for event PAUSED</description>
84842 <description>Read: Disabled</description>
84847 <description>Read: Enabled</description>
84855 <description>Enable</description>
84862 <description>Write '1' to enable interrupt for event RESET</description>
84869 <description>Read: Disabled</description>
84874 <description>Read: Enabled</description>
84882 <description>Enable</description>
84889 <description>Write '1' to enable interrupt for event SOURCEBUSERROR</description>
84896 <description>Read: Disabled</description>
84901 <description>Read: Enabled</description>
84909 <description>Enable</description>
84916 <description>Write '1' to enable interrupt for event SOURCESELECTJOBDONE</description>
84923 <description>Read: Disabled</description>
84928 <description>Read: Enabled</description>
84936 <description>Enable</description>
84943 <description>Write '1' to enable interrupt for event SINKBUSERROR</description>
84950 <description>Read: Disabled</description>
84955 <description>Read: Enabled</description>
84963 <description>Enable</description>
84970 <description>Write '1' to enable interrupt for event SINKSELECTJOBDONE</description>
84977 <description>Read: Disabled</description>
84982 <description>Read: Enabled</description>
84990 <description>Enable</description>
84997 <description>Write '1' to enable interrupt for event COMPLETED[0]</description>
85004 <description>Read: Disabled</description>
85009 <description>Read: Enabled</description>
85017 <description>Enable</description>
85024 <description>Write '1' to enable interrupt for event COMPLETED[1]</description>
85031 <description>Read: Disabled</description>
85036 <description>Read: Enabled</description>
85044 <description>Enable</description>
85051 <description>Write '1' to enable interrupt for event COMPLETED[2]</description>
85058 <description>Read: Disabled</description>
85063 <description>Read: Enabled</description>
85071 <description>Enable</description>
85078 <description>Write '1' to enable interrupt for event COMPLETED[3]</description>
85085 <description>Read: Disabled</description>
85090 <description>Read: Enabled</description>
85098 <description>Enable</description>
85105 <description>Write '1' to enable interrupt for event COMPLETED[4]</description>
85112 <description>Read: Disabled</description>
85117 <description>Read: Enabled</description>
85125 <description>Enable</description>
85132 <description>Write '1' to enable interrupt for event COMPLETED[5]</description>
85139 <description>Read: Disabled</description>
85144 <description>Read: Enabled</description>
85152 <description>Enable</description>
85159 <description>Write '1' to enable interrupt for event COMPLETED[6]</description>
85166 <description>Read: Disabled</description>
85171 <description>Read: Enabled</description>
85179 <description>Enable</description>
85186 <description>Write '1' to enable interrupt for event COMPLETED[7]</description>
85193 <description>Read: Disabled</description>
85198 <description>Read: Enabled</description>
85206 <description>Enable</description>
85215 <description>Disable interrupt</description>
85223 <description>Write '1' to disable interrupt for event END</description>
85230 <description>Read: Disabled</description>
85235 <description>Read: Enabled</description>
85243 <description>Disable</description>
85250 <description>Write '1' to disable interrupt for event STARTED</description>
85257 <description>Read: Disabled</description>
85262 <description>Read: Enabled</description>
85270 <description>Disable</description>
85277 <description>Write '1' to disable interrupt for event PAUSED</description>
85284 <description>Read: Disabled</description>
85289 <description>Read: Enabled</description>
85297 <description>Disable</description>
85304 <description>Write '1' to disable interrupt for event RESET</description>
85311 <description>Read: Disabled</description>
85316 <description>Read: Enabled</description>
85324 <description>Disable</description>
85331 <description>Write '1' to disable interrupt for event SOURCEBUSERROR</description>
85338 <description>Read: Disabled</description>
85343 <description>Read: Enabled</description>
85351 <description>Disable</description>
85358 … <description>Write '1' to disable interrupt for event SOURCESELECTJOBDONE</description>
85365 <description>Read: Disabled</description>
85370 <description>Read: Enabled</description>
85378 <description>Disable</description>
85385 <description>Write '1' to disable interrupt for event SINKBUSERROR</description>
85392 <description>Read: Disabled</description>
85397 <description>Read: Enabled</description>
85405 <description>Disable</description>
85412 <description>Write '1' to disable interrupt for event SINKSELECTJOBDONE</description>
85419 <description>Read: Disabled</description>
85424 <description>Read: Enabled</description>
85432 <description>Disable</description>
85439 <description>Write '1' to disable interrupt for event COMPLETED[0]</description>
85446 <description>Read: Disabled</description>
85451 <description>Read: Enabled</description>
85459 <description>Disable</description>
85466 <description>Write '1' to disable interrupt for event COMPLETED[1]</description>
85473 <description>Read: Disabled</description>
85478 <description>Read: Enabled</description>
85486 <description>Disable</description>
85493 <description>Write '1' to disable interrupt for event COMPLETED[2]</description>
85500 <description>Read: Disabled</description>
85505 <description>Read: Enabled</description>
85513 <description>Disable</description>
85520 <description>Write '1' to disable interrupt for event COMPLETED[3]</description>
85527 <description>Read: Disabled</description>
85532 <description>Read: Enabled</description>
85540 <description>Disable</description>
85547 <description>Write '1' to disable interrupt for event COMPLETED[4]</description>
85554 <description>Read: Disabled</description>
85559 <description>Read: Enabled</description>
85567 <description>Disable</description>
85574 <description>Write '1' to disable interrupt for event COMPLETED[5]</description>
85581 <description>Read: Disabled</description>
85586 <description>Read: Enabled</description>
85594 <description>Disable</description>
85601 <description>Write '1' to disable interrupt for event COMPLETED[6]</description>
85608 <description>Read: Disabled</description>
85613 <description>Read: Enabled</description>
85621 <description>Disable</description>
85628 <description>Write '1' to disable interrupt for event COMPLETED[7]</description>
85635 <description>Read: Disabled</description>
85640 <description>Read: Enabled</description>
85648 <description>Disable</description>
85657 <description>Pending interrupts</description>
85665 <description>Read pending status of interrupt for event END</description>
85672 <description>Read: Not pending</description>
85677 <description>Read: Pending</description>
85684 <description>Read pending status of interrupt for event STARTED</description>
85691 <description>Read: Not pending</description>
85696 <description>Read: Pending</description>
85703 <description>Read pending status of interrupt for event PAUSED</description>
85710 <description>Read: Not pending</description>
85715 <description>Read: Pending</description>
85722 <description>Read pending status of interrupt for event RESET</description>
85729 <description>Read: Not pending</description>
85734 <description>Read: Pending</description>
85741 <description>Read pending status of interrupt for event SOURCEBUSERROR</description>
85748 <description>Read: Not pending</description>
85753 <description>Read: Pending</description>
85760 … <description>Read pending status of interrupt for event SOURCESELECTJOBDONE</description>
85767 <description>Read: Not pending</description>
85772 <description>Read: Pending</description>
85779 <description>Read pending status of interrupt for event SINKBUSERROR</description>
85786 <description>Read: Not pending</description>
85791 <description>Read: Pending</description>
85798 … <description>Read pending status of interrupt for event SINKSELECTJOBDONE</description>
85805 <description>Read: Not pending</description>
85810 <description>Read: Pending</description>
85817 <description>Read pending status of interrupt for event COMPLETED[0]</description>
85824 <description>Read: Not pending</description>
85829 <description>Read: Pending</description>
85836 <description>Read pending status of interrupt for event COMPLETED[1]</description>
85843 <description>Read: Not pending</description>
85848 <description>Read: Pending</description>
85855 <description>Read pending status of interrupt for event COMPLETED[2]</description>
85862 <description>Read: Not pending</description>
85867 <description>Read: Pending</description>
85874 <description>Read pending status of interrupt for event COMPLETED[3]</description>
85881 <description>Read: Not pending</description>
85886 <description>Read: Pending</description>
85893 <description>Read pending status of interrupt for event COMPLETED[4]</description>
85900 <description>Read: Not pending</description>
85905 <description>Read: Pending</description>
85912 <description>Read pending status of interrupt for event COMPLETED[5]</description>
85919 <description>Read: Not pending</description>
85924 <description>Read: Pending</description>
85931 <description>Read pending status of interrupt for event COMPLETED[6]</description>
85938 <description>Read: Not pending</description>
85943 <description>Read: Pending</description>
85950 <description>Read pending status of interrupt for event COMPLETED[7]</description>
85957 <description>Read: Not pending</description>
85962 <description>Read: Pending</description>
85971 <description>MVDMA status registers.</description>
85977 <description>CRC checksum calculation result</description>
85985 <description>Result</description>
85993 …<description>Status of intermediate fifo: empty, not empty and full information available.</descri…
86001 <description>Result</description>
86007 <description>Fifo is empty.</description>
86012 <description>Fifo contains data.</description>
86017 <description>Fifo is full.</description>
86026 <description>Status of DMA transfer.</description>
86034 <description>DMA activity</description>
86040 <description>DMA is in IDLE state.</description>
86045 <description>Data being transferred.</description>
86055 <description>MVDMA configuration registers.</description>
86061 <description>Configure MVDMA mode of operation.</description>
86074 …<description>Registers SOURCE.LISTPTR and SINK.LISTPTR contain start address of a single job list.…
86079 …<description>Registers SOURCE.LISTPTR and SINK.LISTPTR contain start address of a list of job list…
86089 <description>Source channel configuration and status.</description>
86095 …<description>Start address of Source job list or list of job list pointers, depending on value of …
86103 <description>Source job descriptor list address.</description>
86111 <description>Source bus error status.</description>
86119 <description>Bus error type</description>
86125 <description>There are no errors.</description>
86130 …<description>Error related to memory when reading joblist, or error related to memory/register whe…
86135 …<description>Error related to the joblist address when reading joblist, or error related to addres…
86144 …description>Latest address being accessed on the Source channel.If a bus error occurs, these regis…
86152 <description>Source address</description>
86160 …<description>Number of completed jobs in the current Source descriptor list. This resets to 0 when…
86168 <description>Source job count</description>
86177 <description>Sink channel configuration and status.</description>
86183 …<description>Start address of Sink job list or list of job list pointers, depending on value of CO…
86191 <description>Sink descriptor list address.</description>
86199 <description>Sink bus error status.</description>
86207 <description>Bus error type</description>
86213 <description>There are no errors.</description>
86218 <description>Error related to memory when reading joblist.</description>
86223 … <description>Error related to the joblist address when reading joblist.</description>
86228 <description>Error related to memory/register when writing data.</description>
86233 … <description>Error related to the memory/register address when writing data.</description>
86242 …description>Latest address being accessed on the Sink channel. If a bus error occurs, these regist…
86250 <description>Sink address</description>
86258 …<description>Number of completed jobs in the current Sink descriptor list. This resets to 0 when a…
86266 <description>Sink job count</description>
86277 <description>RAM Controller</description>
86292 <description>Waitstates for read operations.</description>
86300 <description>Number of waitstates for a read from the RAM.</description>
86310 <description>I3C 1</description>
86321 <description>Distributed programmable peripheral interconnect controller 0</description>
86339 <description>Channel group tasks</description>
86345 <description>Description cluster: Enable channel group n</description>
86353 <description>Enable channel group n</description>
86359 <description>Trigger task</description>
86368 <description>Description cluster: Disable channel group n</description>
86376 <description>Disable channel group n</description>
86382 <description>Trigger task</description>
86394 <description>Subscribe configuration for tasks</description>
86400 … <description>Description cluster: Subscribe configuration for task CHG[n].EN</description>
86408 <description>DPPI channel that task CHG[n].EN will subscribe to</description>
86419 <description>Disable subscription</description>
86424 <description>Enable subscription</description>
86433 … <description>Description cluster: Subscribe configuration for task CHG[n].DIS</description>
86441 <description>DPPI channel that task CHG[n].DIS will subscribe to</description>
86452 <description>Disable subscription</description>
86457 <description>Enable subscription</description>
86467 <description>Channel enable register</description>
86475 <description>Enable or disable channel 0</description>
86481 <description>Disable channel</description>
86486 <description>Enable channel</description>
86493 <description>Enable or disable channel 1</description>
86499 <description>Disable channel</description>
86504 <description>Enable channel</description>
86511 <description>Enable or disable channel 2</description>
86517 <description>Disable channel</description>
86522 <description>Enable channel</description>
86529 <description>Enable or disable channel 3</description>
86535 <description>Disable channel</description>
86540 <description>Enable channel</description>
86547 <description>Enable or disable channel 4</description>
86553 <description>Disable channel</description>
86558 <description>Enable channel</description>
86565 <description>Enable or disable channel 5</description>
86571 <description>Disable channel</description>
86576 <description>Enable channel</description>
86583 <description>Enable or disable channel 6</description>
86589 <description>Disable channel</description>
86594 <description>Enable channel</description>
86601 <description>Enable or disable channel 7</description>
86607 <description>Disable channel</description>
86612 <description>Enable channel</description>
86619 <description>Enable or disable channel 8</description>
86625 <description>Disable channel</description>
86630 <description>Enable channel</description>
86637 <description>Enable or disable channel 9</description>
86643 <description>Disable channel</description>
86648 <description>Enable channel</description>
86655 <description>Enable or disable channel 10</description>
86661 <description>Disable channel</description>
86666 <description>Enable channel</description>
86673 <description>Enable or disable channel 11</description>
86679 <description>Disable channel</description>
86684 <description>Enable channel</description>
86691 <description>Enable or disable channel 12</description>
86697 <description>Disable channel</description>
86702 <description>Enable channel</description>
86709 <description>Enable or disable channel 13</description>
86715 <description>Disable channel</description>
86720 <description>Enable channel</description>
86727 <description>Enable or disable channel 14</description>
86733 <description>Disable channel</description>
86738 <description>Enable channel</description>
86745 <description>Enable or disable channel 15</description>
86751 <description>Disable channel</description>
86756 <description>Enable channel</description>
86763 <description>Enable or disable channel 16</description>
86769 <description>Disable channel</description>
86774 <description>Enable channel</description>
86781 <description>Enable or disable channel 17</description>
86787 <description>Disable channel</description>
86792 <description>Enable channel</description>
86799 <description>Enable or disable channel 18</description>
86805 <description>Disable channel</description>
86810 <description>Enable channel</description>
86817 <description>Enable or disable channel 19</description>
86823 <description>Disable channel</description>
86828 <description>Enable channel</description>
86835 <description>Enable or disable channel 20</description>
86841 <description>Disable channel</description>
86846 <description>Enable channel</description>
86853 <description>Enable or disable channel 21</description>
86859 <description>Disable channel</description>
86864 <description>Enable channel</description>
86871 <description>Enable or disable channel 22</description>
86877 <description>Disable channel</description>
86882 <description>Enable channel</description>
86889 <description>Enable or disable channel 23</description>
86895 <description>Disable channel</description>
86900 <description>Enable channel</description>
86907 <description>Enable or disable channel 24</description>
86913 <description>Disable channel</description>
86918 <description>Enable channel</description>
86925 <description>Enable or disable channel 25</description>
86931 <description>Disable channel</description>
86936 <description>Enable channel</description>
86943 <description>Enable or disable channel 26</description>
86949 <description>Disable channel</description>
86954 <description>Enable channel</description>
86961 <description>Enable or disable channel 27</description>
86967 <description>Disable channel</description>
86972 <description>Enable channel</description>
86979 <description>Enable or disable channel 28</description>
86985 <description>Disable channel</description>
86990 <description>Enable channel</description>
86997 <description>Enable or disable channel 29</description>
87003 <description>Disable channel</description>
87008 <description>Enable channel</description>
87015 <description>Enable or disable channel 30</description>
87021 <description>Disable channel</description>
87026 <description>Enable channel</description>
87033 <description>Enable or disable channel 31</description>
87039 <description>Disable channel</description>
87044 <description>Enable channel</description>
87053 <description>Channel enable set register</description>
87062 <description>Channel 0 enable set register. Writing 0 has no effect.</description>
87069 <description>Read: Channel disabled</description>
87074 <description>Read: Channel enabled</description>
87082 <description>Write: Enable channel</description>
87089 <description>Channel 1 enable set register. Writing 0 has no effect.</description>
87096 <description>Read: Channel disabled</description>
87101 <description>Read: Channel enabled</description>
87109 <description>Write: Enable channel</description>
87116 <description>Channel 2 enable set register. Writing 0 has no effect.</description>
87123 <description>Read: Channel disabled</description>
87128 <description>Read: Channel enabled</description>
87136 <description>Write: Enable channel</description>
87143 <description>Channel 3 enable set register. Writing 0 has no effect.</description>
87150 <description>Read: Channel disabled</description>
87155 <description>Read: Channel enabled</description>
87163 <description>Write: Enable channel</description>
87170 <description>Channel 4 enable set register. Writing 0 has no effect.</description>
87177 <description>Read: Channel disabled</description>
87182 <description>Read: Channel enabled</description>
87190 <description>Write: Enable channel</description>
87197 <description>Channel 5 enable set register. Writing 0 has no effect.</description>
87204 <description>Read: Channel disabled</description>
87209 <description>Read: Channel enabled</description>
87217 <description>Write: Enable channel</description>
87224 <description>Channel 6 enable set register. Writing 0 has no effect.</description>
87231 <description>Read: Channel disabled</description>
87236 <description>Read: Channel enabled</description>
87244 <description>Write: Enable channel</description>
87251 <description>Channel 7 enable set register. Writing 0 has no effect.</description>
87258 <description>Read: Channel disabled</description>
87263 <description>Read: Channel enabled</description>
87271 <description>Write: Enable channel</description>
87278 <description>Channel 8 enable set register. Writing 0 has no effect.</description>
87285 <description>Read: Channel disabled</description>
87290 <description>Read: Channel enabled</description>
87298 <description>Write: Enable channel</description>
87305 <description>Channel 9 enable set register. Writing 0 has no effect.</description>
87312 <description>Read: Channel disabled</description>
87317 <description>Read: Channel enabled</description>
87325 <description>Write: Enable channel</description>
87332 <description>Channel 10 enable set register. Writing 0 has no effect.</description>
87339 <description>Read: Channel disabled</description>
87344 <description>Read: Channel enabled</description>
87352 <description>Write: Enable channel</description>
87359 <description>Channel 11 enable set register. Writing 0 has no effect.</description>
87366 <description>Read: Channel disabled</description>
87371 <description>Read: Channel enabled</description>
87379 <description>Write: Enable channel</description>
87386 <description>Channel 12 enable set register. Writing 0 has no effect.</description>
87393 <description>Read: Channel disabled</description>
87398 <description>Read: Channel enabled</description>
87406 <description>Write: Enable channel</description>
87413 <description>Channel 13 enable set register. Writing 0 has no effect.</description>
87420 <description>Read: Channel disabled</description>
87425 <description>Read: Channel enabled</description>
87433 <description>Write: Enable channel</description>
87440 <description>Channel 14 enable set register. Writing 0 has no effect.</description>
87447 <description>Read: Channel disabled</description>
87452 <description>Read: Channel enabled</description>
87460 <description>Write: Enable channel</description>
87467 <description>Channel 15 enable set register. Writing 0 has no effect.</description>
87474 <description>Read: Channel disabled</description>
87479 <description>Read: Channel enabled</description>
87487 <description>Write: Enable channel</description>
87494 <description>Channel 16 enable set register. Writing 0 has no effect.</description>
87501 <description>Read: Channel disabled</description>
87506 <description>Read: Channel enabled</description>
87514 <description>Write: Enable channel</description>
87521 <description>Channel 17 enable set register. Writing 0 has no effect.</description>
87528 <description>Read: Channel disabled</description>
87533 <description>Read: Channel enabled</description>
87541 <description>Write: Enable channel</description>
87548 <description>Channel 18 enable set register. Writing 0 has no effect.</description>
87555 <description>Read: Channel disabled</description>
87560 <description>Read: Channel enabled</description>
87568 <description>Write: Enable channel</description>
87575 <description>Channel 19 enable set register. Writing 0 has no effect.</description>
87582 <description>Read: Channel disabled</description>
87587 <description>Read: Channel enabled</description>
87595 <description>Write: Enable channel</description>
87602 <description>Channel 20 enable set register. Writing 0 has no effect.</description>
87609 <description>Read: Channel disabled</description>
87614 <description>Read: Channel enabled</description>
87622 <description>Write: Enable channel</description>
87629 <description>Channel 21 enable set register. Writing 0 has no effect.</description>
87636 <description>Read: Channel disabled</description>
87641 <description>Read: Channel enabled</description>
87649 <description>Write: Enable channel</description>
87656 <description>Channel 22 enable set register. Writing 0 has no effect.</description>
87663 <description>Read: Channel disabled</description>
87668 <description>Read: Channel enabled</description>
87676 <description>Write: Enable channel</description>
87683 <description>Channel 23 enable set register. Writing 0 has no effect.</description>
87690 <description>Read: Channel disabled</description>
87695 <description>Read: Channel enabled</description>
87703 <description>Write: Enable channel</description>
87710 <description>Channel 24 enable set register. Writing 0 has no effect.</description>
87717 <description>Read: Channel disabled</description>
87722 <description>Read: Channel enabled</description>
87730 <description>Write: Enable channel</description>
87737 <description>Channel 25 enable set register. Writing 0 has no effect.</description>
87744 <description>Read: Channel disabled</description>
87749 <description>Read: Channel enabled</description>
87757 <description>Write: Enable channel</description>
87764 <description>Channel 26 enable set register. Writing 0 has no effect.</description>
87771 <description>Read: Channel disabled</description>
87776 <description>Read: Channel enabled</description>
87784 <description>Write: Enable channel</description>
87791 <description>Channel 27 enable set register. Writing 0 has no effect.</description>
87798 <description>Read: Channel disabled</description>
87803 <description>Read: Channel enabled</description>
87811 <description>Write: Enable channel</description>
87818 <description>Channel 28 enable set register. Writing 0 has no effect.</description>
87825 <description>Read: Channel disabled</description>
87830 <description>Read: Channel enabled</description>
87838 <description>Write: Enable channel</description>
87845 <description>Channel 29 enable set register. Writing 0 has no effect.</description>
87852 <description>Read: Channel disabled</description>
87857 <description>Read: Channel enabled</description>
87865 <description>Write: Enable channel</description>
87872 <description>Channel 30 enable set register. Writing 0 has no effect.</description>
87879 <description>Read: Channel disabled</description>
87884 <description>Read: Channel enabled</description>
87892 <description>Write: Enable channel</description>
87899 <description>Channel 31 enable set register. Writing 0 has no effect.</description>
87906 <description>Read: Channel disabled</description>
87911 <description>Read: Channel enabled</description>
87919 <description>Write: Enable channel</description>
87928 <description>Channel enable clear register</description>
87937 <description>Channel 0 enable clear register. Writing 0 has no effect.</description>
87944 <description>Read: Channel disabled</description>
87949 <description>Read: Channel enabled</description>
87957 <description>Write: Disable channel</description>
87964 <description>Channel 1 enable clear register. Writing 0 has no effect.</description>
87971 <description>Read: Channel disabled</description>
87976 <description>Read: Channel enabled</description>
87984 <description>Write: Disable channel</description>
87991 <description>Channel 2 enable clear register. Writing 0 has no effect.</description>
87998 <description>Read: Channel disabled</description>
88003 <description>Read: Channel enabled</description>
88011 <description>Write: Disable channel</description>
88018 <description>Channel 3 enable clear register. Writing 0 has no effect.</description>
88025 <description>Read: Channel disabled</description>
88030 <description>Read: Channel enabled</description>
88038 <description>Write: Disable channel</description>
88045 <description>Channel 4 enable clear register. Writing 0 has no effect.</description>
88052 <description>Read: Channel disabled</description>
88057 <description>Read: Channel enabled</description>
88065 <description>Write: Disable channel</description>
88072 <description>Channel 5 enable clear register. Writing 0 has no effect.</description>
88079 <description>Read: Channel disabled</description>
88084 <description>Read: Channel enabled</description>
88092 <description>Write: Disable channel</description>
88099 <description>Channel 6 enable clear register. Writing 0 has no effect.</description>
88106 <description>Read: Channel disabled</description>
88111 <description>Read: Channel enabled</description>
88119 <description>Write: Disable channel</description>
88126 <description>Channel 7 enable clear register. Writing 0 has no effect.</description>
88133 <description>Read: Channel disabled</description>
88138 <description>Read: Channel enabled</description>
88146 <description>Write: Disable channel</description>
88153 <description>Channel 8 enable clear register. Writing 0 has no effect.</description>
88160 <description>Read: Channel disabled</description>
88165 <description>Read: Channel enabled</description>
88173 <description>Write: Disable channel</description>
88180 <description>Channel 9 enable clear register. Writing 0 has no effect.</description>
88187 <description>Read: Channel disabled</description>
88192 <description>Read: Channel enabled</description>
88200 <description>Write: Disable channel</description>
88207 <description>Channel 10 enable clear register. Writing 0 has no effect.</description>
88214 <description>Read: Channel disabled</description>
88219 <description>Read: Channel enabled</description>
88227 <description>Write: Disable channel</description>
88234 <description>Channel 11 enable clear register. Writing 0 has no effect.</description>
88241 <description>Read: Channel disabled</description>
88246 <description>Read: Channel enabled</description>
88254 <description>Write: Disable channel</description>
88261 <description>Channel 12 enable clear register. Writing 0 has no effect.</description>
88268 <description>Read: Channel disabled</description>
88273 <description>Read: Channel enabled</description>
88281 <description>Write: Disable channel</description>
88288 <description>Channel 13 enable clear register. Writing 0 has no effect.</description>
88295 <description>Read: Channel disabled</description>
88300 <description>Read: Channel enabled</description>
88308 <description>Write: Disable channel</description>
88315 <description>Channel 14 enable clear register. Writing 0 has no effect.</description>
88322 <description>Read: Channel disabled</description>
88327 <description>Read: Channel enabled</description>
88335 <description>Write: Disable channel</description>
88342 <description>Channel 15 enable clear register. Writing 0 has no effect.</description>
88349 <description>Read: Channel disabled</description>
88354 <description>Read: Channel enabled</description>
88362 <description>Write: Disable channel</description>
88369 <description>Channel 16 enable clear register. Writing 0 has no effect.</description>
88376 <description>Read: Channel disabled</description>
88381 <description>Read: Channel enabled</description>
88389 <description>Write: Disable channel</description>
88396 <description>Channel 17 enable clear register. Writing 0 has no effect.</description>
88403 <description>Read: Channel disabled</description>
88408 <description>Read: Channel enabled</description>
88416 <description>Write: Disable channel</description>
88423 <description>Channel 18 enable clear register. Writing 0 has no effect.</description>
88430 <description>Read: Channel disabled</description>
88435 <description>Read: Channel enabled</description>
88443 <description>Write: Disable channel</description>
88450 <description>Channel 19 enable clear register. Writing 0 has no effect.</description>
88457 <description>Read: Channel disabled</description>
88462 <description>Read: Channel enabled</description>
88470 <description>Write: Disable channel</description>
88477 <description>Channel 20 enable clear register. Writing 0 has no effect.</description>
88484 <description>Read: Channel disabled</description>
88489 <description>Read: Channel enabled</description>
88497 <description>Write: Disable channel</description>
88504 <description>Channel 21 enable clear register. Writing 0 has no effect.</description>
88511 <description>Read: Channel disabled</description>
88516 <description>Read: Channel enabled</description>
88524 <description>Write: Disable channel</description>
88531 <description>Channel 22 enable clear register. Writing 0 has no effect.</description>
88538 <description>Read: Channel disabled</description>
88543 <description>Read: Channel enabled</description>
88551 <description>Write: Disable channel</description>
88558 <description>Channel 23 enable clear register. Writing 0 has no effect.</description>
88565 <description>Read: Channel disabled</description>
88570 <description>Read: Channel enabled</description>
88578 <description>Write: Disable channel</description>
88585 <description>Channel 24 enable clear register. Writing 0 has no effect.</description>
88592 <description>Read: Channel disabled</description>
88597 <description>Read: Channel enabled</description>
88605 <description>Write: Disable channel</description>
88612 <description>Channel 25 enable clear register. Writing 0 has no effect.</description>
88619 <description>Read: Channel disabled</description>
88624 <description>Read: Channel enabled</description>
88632 <description>Write: Disable channel</description>
88639 <description>Channel 26 enable clear register. Writing 0 has no effect.</description>
88646 <description>Read: Channel disabled</description>
88651 <description>Read: Channel enabled</description>
88659 <description>Write: Disable channel</description>
88666 <description>Channel 27 enable clear register. Writing 0 has no effect.</description>
88673 <description>Read: Channel disabled</description>
88678 <description>Read: Channel enabled</description>
88686 <description>Write: Disable channel</description>
88693 <description>Channel 28 enable clear register. Writing 0 has no effect.</description>
88700 <description>Read: Channel disabled</description>
88705 <description>Read: Channel enabled</description>
88713 <description>Write: Disable channel</description>
88720 <description>Channel 29 enable clear register. Writing 0 has no effect.</description>
88727 <description>Read: Channel disabled</description>
88732 <description>Read: Channel enabled</description>
88740 <description>Write: Disable channel</description>
88747 <description>Channel 30 enable clear register. Writing 0 has no effect.</description>
88754 <description>Read: Channel disabled</description>
88759 <description>Read: Channel enabled</description>
88767 <description>Write: Disable channel</description>
88774 <description>Channel 31 enable clear register. Writing 0 has no effect.</description>
88781 <description>Read: Channel disabled</description>
88786 <description>Read: Channel enabled</description>
88794 <description>Write: Disable channel</description>
88805 …description>Description collection: Channel group n Note: Writes to this register are ignored if e…
88813 <description>Include or exclude channel 0</description>
88819 <description>Exclude</description>
88824 <description>Include</description>
88831 <description>Include or exclude channel 1</description>
88837 <description>Exclude</description>
88842 <description>Include</description>
88849 <description>Include or exclude channel 2</description>
88855 <description>Exclude</description>
88860 <description>Include</description>
88867 <description>Include or exclude channel 3</description>
88873 <description>Exclude</description>
88878 <description>Include</description>
88885 <description>Include or exclude channel 4</description>
88891 <description>Exclude</description>
88896 <description>Include</description>
88903 <description>Include or exclude channel 5</description>
88909 <description>Exclude</description>
88914 <description>Include</description>
88921 <description>Include or exclude channel 6</description>
88927 <description>Exclude</description>
88932 <description>Include</description>
88939 <description>Include or exclude channel 7</description>
88945 <description>Exclude</description>
88950 <description>Include</description>
88957 <description>Include or exclude channel 8</description>
88963 <description>Exclude</description>
88968 <description>Include</description>
88975 <description>Include or exclude channel 9</description>
88981 <description>Exclude</description>
88986 <description>Include</description>
88993 <description>Include or exclude channel 10</description>
88999 <description>Exclude</description>
89004 <description>Include</description>
89011 <description>Include or exclude channel 11</description>
89017 <description>Exclude</description>
89022 <description>Include</description>
89029 <description>Include or exclude channel 12</description>
89035 <description>Exclude</description>
89040 <description>Include</description>
89047 <description>Include or exclude channel 13</description>
89053 <description>Exclude</description>
89058 <description>Include</description>
89065 <description>Include or exclude channel 14</description>
89071 <description>Exclude</description>
89076 <description>Include</description>
89083 <description>Include or exclude channel 15</description>
89089 <description>Exclude</description>
89094 <description>Include</description>
89101 <description>Include or exclude channel 16</description>
89107 <description>Exclude</description>
89112 <description>Include</description>
89119 <description>Include or exclude channel 17</description>
89125 <description>Exclude</description>
89130 <description>Include</description>
89137 <description>Include or exclude channel 18</description>
89143 <description>Exclude</description>
89148 <description>Include</description>
89155 <description>Include or exclude channel 19</description>
89161 <description>Exclude</description>
89166 <description>Include</description>
89173 <description>Include or exclude channel 20</description>
89179 <description>Exclude</description>
89184 <description>Include</description>
89191 <description>Include or exclude channel 21</description>
89197 <description>Exclude</description>
89202 <description>Include</description>
89209 <description>Include or exclude channel 22</description>
89215 <description>Exclude</description>
89220 <description>Include</description>
89227 <description>Include or exclude channel 23</description>
89233 <description>Exclude</description>
89238 <description>Include</description>
89245 <description>Include or exclude channel 24</description>
89251 <description>Exclude</description>
89256 <description>Include</description>
89263 <description>Include or exclude channel 25</description>
89269 <description>Exclude</description>
89274 <description>Include</description>
89281 <description>Include or exclude channel 26</description>
89287 <description>Exclude</description>
89292 <description>Include</description>
89299 <description>Include or exclude channel 27</description>
89305 <description>Exclude</description>
89310 <description>Include</description>
89317 <description>Include or exclude channel 28</description>
89323 <description>Exclude</description>
89328 <description>Include</description>
89335 <description>Include or exclude channel 29</description>
89341 <description>Exclude</description>
89346 <description>Include</description>
89353 <description>Include or exclude channel 30</description>
89359 <description>Exclude</description>
89364 <description>Include</description>
89371 <description>Include or exclude channel 31</description>
89377 <description>Exclude</description>
89382 <description>Include</description>
89393 <description>Timer/Counter 0</description>
89412 <description>Start Timer</description>
89420 <description>Start Timer</description>
89426 <description>Trigger task</description>
89435 <description>Stop Timer</description>
89443 <description>Stop Timer</description>
89449 <description>Trigger task</description>
89458 <description>Increment Timer (Counter mode only)</description>
89466 <description>Increment Timer (Counter mode only)</description>
89472 <description>Trigger task</description>
89481 <description>Clear time</description>
89489 <description>Clear time</description>
89495 <description>Trigger task</description>
89506 <description>Description collection: Capture Timer value to CC[n] register</description>
89514 <description>Capture Timer value to CC[n] register</description>
89520 <description>Trigger task</description>
89529 <description>Subscribe configuration for task START</description>
89537 <description>DPPI channel that task START will subscribe to</description>
89548 <description>Disable subscription</description>
89553 <description>Enable subscription</description>
89562 <description>Subscribe configuration for task STOP</description>
89570 <description>DPPI channel that task STOP will subscribe to</description>
89581 <description>Disable subscription</description>
89586 <description>Enable subscription</description>
89595 <description>Subscribe configuration for task COUNT</description>
89603 <description>DPPI channel that task COUNT will subscribe to</description>
89614 <description>Disable subscription</description>
89619 <description>Enable subscription</description>
89628 <description>Subscribe configuration for task CLEAR</description>
89636 <description>DPPI channel that task CLEAR will subscribe to</description>
89647 <description>Disable subscription</description>
89652 <description>Enable subscription</description>
89663 … <description>Description collection: Subscribe configuration for task CAPTURE[n]</description>
89671 <description>DPPI channel that task CAPTURE[n] will subscribe to</description>
89682 <description>Disable subscription</description>
89687 <description>Enable subscription</description>
89698 <description>Description collection: Compare event on CC[n] match</description>
89706 <description>Compare event on CC[n] match</description>
89712 <description>Event not generated</description>
89717 <description>Event generated</description>
89728 … <description>Description collection: Publish configuration for event COMPARE[n]</description>
89736 <description>DPPI channel that event COMPARE[n] will publish to</description>
89747 <description>Disable publishing</description>
89752 <description>Enable publishing</description>
89761 <description>Shortcuts between local events and tasks</description>
89769 <description>Shortcut between event COMPARE[0] and task CLEAR</description>
89775 <description>Disable shortcut</description>
89780 <description>Enable shortcut</description>
89787 <description>Shortcut between event COMPARE[1] and task CLEAR</description>
89793 <description>Disable shortcut</description>
89798 <description>Enable shortcut</description>
89805 <description>Shortcut between event COMPARE[2] and task CLEAR</description>
89811 <description>Disable shortcut</description>
89816 <description>Enable shortcut</description>
89823 <description>Shortcut between event COMPARE[3] and task CLEAR</description>
89829 <description>Disable shortcut</description>
89834 <description>Enable shortcut</description>
89841 <description>Shortcut between event COMPARE[4] and task CLEAR</description>
89847 <description>Disable shortcut</description>
89852 <description>Enable shortcut</description>
89859 <description>Shortcut between event COMPARE[5] and task CLEAR</description>
89865 <description>Disable shortcut</description>
89870 <description>Enable shortcut</description>
89877 <description>Shortcut between event COMPARE[6] and task CLEAR</description>
89883 <description>Disable shortcut</description>
89888 <description>Enable shortcut</description>
89895 <description>Shortcut between event COMPARE[7] and task CLEAR</description>
89901 <description>Disable shortcut</description>
89906 <description>Enable shortcut</description>
89913 <description>Shortcut between event COMPARE[0] and task STOP</description>
89919 <description>Disable shortcut</description>
89924 <description>Enable shortcut</description>
89931 <description>Shortcut between event COMPARE[1] and task STOP</description>
89937 <description>Disable shortcut</description>
89942 <description>Enable shortcut</description>
89949 <description>Shortcut between event COMPARE[2] and task STOP</description>
89955 <description>Disable shortcut</description>
89960 <description>Enable shortcut</description>
89967 <description>Shortcut between event COMPARE[3] and task STOP</description>
89973 <description>Disable shortcut</description>
89978 <description>Enable shortcut</description>
89985 <description>Shortcut between event COMPARE[4] and task STOP</description>
89991 <description>Disable shortcut</description>
89996 <description>Enable shortcut</description>
90003 <description>Shortcut between event COMPARE[5] and task STOP</description>
90009 <description>Disable shortcut</description>
90014 <description>Enable shortcut</description>
90021 <description>Shortcut between event COMPARE[6] and task STOP</description>
90027 <description>Disable shortcut</description>
90032 <description>Enable shortcut</description>
90039 <description>Shortcut between event COMPARE[7] and task STOP</description>
90045 <description>Disable shortcut</description>
90050 <description>Enable shortcut</description>
90059 <description>Enable or disable interrupt</description>
90067 <description>Enable or disable interrupt for event COMPARE[0]</description>
90073 <description>Disable</description>
90078 <description>Enable</description>
90085 <description>Enable or disable interrupt for event COMPARE[1]</description>
90091 <description>Disable</description>
90096 <description>Enable</description>
90103 <description>Enable or disable interrupt for event COMPARE[2]</description>
90109 <description>Disable</description>
90114 <description>Enable</description>
90121 <description>Enable or disable interrupt for event COMPARE[3]</description>
90127 <description>Disable</description>
90132 <description>Enable</description>
90139 <description>Enable or disable interrupt for event COMPARE[4]</description>
90145 <description>Disable</description>
90150 <description>Enable</description>
90157 <description>Enable or disable interrupt for event COMPARE[5]</description>
90163 <description>Disable</description>
90168 <description>Enable</description>
90175 <description>Enable or disable interrupt for event COMPARE[6]</description>
90181 <description>Disable</description>
90186 <description>Enable</description>
90193 <description>Enable or disable interrupt for event COMPARE[7]</description>
90199 <description>Disable</description>
90204 <description>Enable</description>
90213 <description>Enable interrupt</description>
90221 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
90228 <description>Read: Disabled</description>
90233 <description>Read: Enabled</description>
90241 <description>Enable</description>
90248 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
90255 <description>Read: Disabled</description>
90260 <description>Read: Enabled</description>
90268 <description>Enable</description>
90275 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
90282 <description>Read: Disabled</description>
90287 <description>Read: Enabled</description>
90295 <description>Enable</description>
90302 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
90309 <description>Read: Disabled</description>
90314 <description>Read: Enabled</description>
90322 <description>Enable</description>
90329 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
90336 <description>Read: Disabled</description>
90341 <description>Read: Enabled</description>
90349 <description>Enable</description>
90356 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
90363 <description>Read: Disabled</description>
90368 <description>Read: Enabled</description>
90376 <description>Enable</description>
90383 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
90390 <description>Read: Disabled</description>
90395 <description>Read: Enabled</description>
90403 <description>Enable</description>
90410 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
90417 <description>Read: Disabled</description>
90422 <description>Read: Enabled</description>
90430 <description>Enable</description>
90439 <description>Disable interrupt</description>
90447 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
90454 <description>Read: Disabled</description>
90459 <description>Read: Enabled</description>
90467 <description>Disable</description>
90474 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
90481 <description>Read: Disabled</description>
90486 <description>Read: Enabled</description>
90494 <description>Disable</description>
90501 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
90508 <description>Read: Disabled</description>
90513 <description>Read: Enabled</description>
90521 <description>Disable</description>
90528 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
90535 <description>Read: Disabled</description>
90540 <description>Read: Enabled</description>
90548 <description>Disable</description>
90555 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
90562 <description>Read: Disabled</description>
90567 <description>Read: Enabled</description>
90575 <description>Disable</description>
90582 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
90589 <description>Read: Disabled</description>
90594 <description>Read: Enabled</description>
90602 <description>Disable</description>
90609 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
90616 <description>Read: Disabled</description>
90621 <description>Read: Enabled</description>
90629 <description>Disable</description>
90636 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
90643 <description>Read: Disabled</description>
90648 <description>Read: Enabled</description>
90656 <description>Disable</description>
90665 <description>Timer mode selection</description>
90673 <description>Timer mode</description>
90679 <description>Select Timer mode</description>
90684 <description>Deprecated enumerator - Select Counter mode</description>
90689 <description>Select Low Power Counter mode</description>
90698 <description>Configure the number of bits used by the TIMER</description>
90706 <description>Timer bit width</description>
90712 <description>16 bit timer bit width</description>
90717 <description>8 bit timer bit width</description>
90722 <description>24 bit timer bit width</description>
90727 <description>32 bit timer bit width</description>
90736 <description>Timer prescaler register</description>
90744 <description>Prescaler value</description>
90754 <description>Description collection: Capture/Compare register n</description>
90762 <description>Capture/Compare value</description>
90772 …<description>Description collection: Enable one-shot operation for Capture/Compare channel n</desc…
90780 <description>Enable one-shot operation</description>
90786 <description>Disable one-shot operation</description>
90791 <description>Enable one-shot operation</description>
90802 <description>Timer/Counter 1</description>
90813 <description>Pulse width modulation unit 0</description>
90832 …<description>Stops PWM pulse generation on all channels at the end of current PWM period, and stop…
90840 …<description>Stops PWM pulse generation on all channels at the end of current PWM period, and stop…
90846 <description>Trigger task</description>
90855 …description>Steps by one value in the current sequence on all enabled channels if DECODER.MODE=Nex…
90863 …description>Steps by one value in the current sequence on all enabled channels if DECODER.MODE=Nex…
90869 <description>Trigger task</description>
90878 <description>Peripheral tasks.</description>
90886 <description>Peripheral tasks.</description>
90892 …description>Description cluster: Starts operation using easyDMA to load the values. See peripheral…
90900 …<description>Starts operation using easyDMA to load the values. See peripheral description for ope…
90906 <description>Trigger task</description>
90915 …<description>Description cluster: Stops operation using easyDMA. This does not trigger an END even…
90923 … <description>Stops operation using easyDMA. This does not trigger an END event.</description>
90929 <description>Trigger task</description>
90940 <description>Subscribe configuration for task STOP</description>
90948 <description>DPPI channel that task STOP will subscribe to</description>
90959 <description>Disable subscription</description>
90964 <description>Enable subscription</description>
90973 <description>Subscribe configuration for task NEXTSTEP</description>
90981 <description>DPPI channel that task NEXTSTEP will subscribe to</description>
90992 <description>Disable subscription</description>
90997 <description>Enable subscription</description>
91006 <description>Subscribe configuration for tasks</description>
91014 <description>Subscribe configuration for tasks</description>
91020 <description>Description cluster: Subscribe configuration for task START</description>
91028 <description>DPPI channel that task START will subscribe to</description>
91039 <description>Disable subscription</description>
91044 <description>Enable subscription</description>
91053 <description>Description cluster: Subscribe configuration for task STOP</description>
91061 <description>DPPI channel that task STOP will subscribe to</description>
91072 <description>Disable subscription</description>
91077 <description>Enable subscription</description>
91088 … <description>Response to STOP task, emitted when PWM pulses are no longer generated</description>
91096 … <description>Response to STOP task, emitted when PWM pulses are no longer generated</description>
91102 <description>Event not generated</description>
91107 <description>Event generated</description>
91118 <description>Description collection: First PWM period started on sequence n</description>
91126 <description>First PWM period started on sequence n</description>
91132 <description>Event not generated</description>
91137 <description>Event generated</description>
91148 …<description>Description collection: Emitted at end of every sequence n, when last value from RAM …
91156 …<description>Emitted at end of every sequence n, when last value from RAM has been applied to wave…
91162 <description>Event not generated</description>
91167 <description>Event generated</description>
91176 <description>Emitted at the end of each PWM period</description>
91184 <description>Emitted at the end of each PWM period</description>
91190 <description>Event not generated</description>
91195 <description>Event generated</description>
91204 …<description>Concatenated sequences have been played the amount of times defined in LOOP.CNT</desc…
91212 …<description>Concatenated sequences have been played the amount of times defined in LOOP.CNT</desc…
91218 <description>Event not generated</description>
91223 <description>Event generated</description>
91232 …<description>Emitted when retrieving from RAM does not complete in time for the PWM module</descri…
91240 …<description>Emitted when retrieving from RAM does not complete in time for the PWM module</descri…
91246 <description>Event not generated</description>
91251 <description>Event generated</description>
91260 <description>Peripheral events.</description>
91268 <description>Peripheral events.</description>
91274 …<description>Description cluster: Generated after all MAXCNT bytes have been transferred</descript…
91282 <description>Generated after all MAXCNT bytes have been transferred</description>
91288 <description>Event not generated</description>
91293 <description>Event generated</description>
91302 …description>Description cluster: Generated when EasyDMA has buffered the .PTR and .MAXCNT register…
91310 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
91316 <description>Event not generated</description>
91321 <description>Event generated</description>
91330 … <description>Description cluster: An error occured during the bus transfer.</description>
91338 <description>An error occured during the bus transfer.</description>
91344 <description>Event not generated</description>
91349 <description>Event generated</description>
91362 …<description>Description collection: This event is generated when the compare matches for the comp…
91370 …<description>This event is generated when the compare matches for the compare channel [n].</descri…
91376 <description>Event not generated</description>
91381 <description>Event generated</description>
91390 <description>Publish configuration for event STOPPED</description>
91398 <description>DPPI channel that event STOPPED will publish to</description>
91409 <description>Disable publishing</description>
91414 <description>Enable publishing</description>
91425 … <description>Description collection: Publish configuration for event SEQSTARTED[n]</description>
91433 <description>DPPI channel that event SEQSTARTED[n] will publish to</description>
91444 <description>Disable publishing</description>
91449 <description>Enable publishing</description>
91460 … <description>Description collection: Publish configuration for event SEQEND[n]</description>
91468 <description>DPPI channel that event SEQEND[n] will publish to</description>
91479 <description>Disable publishing</description>
91484 <description>Enable publishing</description>
91493 <description>Publish configuration for event PWMPERIODEND</description>
91501 <description>DPPI channel that event PWMPERIODEND will publish to</description>
91512 <description>Disable publishing</description>
91517 <description>Enable publishing</description>
91526 <description>Publish configuration for event LOOPSDONE</description>
91534 <description>DPPI channel that event LOOPSDONE will publish to</description>
91545 <description>Disable publishing</description>
91550 <description>Enable publishing</description>
91559 <description>Publish configuration for event RAMUNDERFLOW</description>
91567 <description>DPPI channel that event RAMUNDERFLOW will publish to</description>
91578 <description>Disable publishing</description>
91583 <description>Enable publishing</description>
91592 <description>Publish configuration for events</description>
91600 <description>Publish configuration for events</description>
91606 <description>Description cluster: Publish configuration for event END</description>
91614 <description>DPPI channel that event END will publish to</description>
91625 <description>Disable publishing</description>
91630 <description>Enable publishing</description>
91639 <description>Description cluster: Publish configuration for event READY</description>
91647 <description>DPPI channel that event READY will publish to</description>
91658 <description>Disable publishing</description>
91663 <description>Enable publishing</description>
91672 … <description>Description cluster: Publish configuration for event BUSERROR</description>
91680 <description>DPPI channel that event BUSERROR will publish to</description>
91691 <description>Disable publishing</description>
91696 <description>Enable publishing</description>
91709 … <description>Description collection: Publish configuration for event COMPAREMATCH[n]</description>
91717 <description>DPPI channel that event COMPAREMATCH[n] will publish to</description>
91728 <description>Disable publishing</description>
91733 <description>Enable publishing</description>
91742 <description>Shortcuts between local events and tasks</description>
91750 <description>Shortcut between event SEQEND[n] and task STOP</description>
91756 <description>Disable shortcut</description>
91761 <description>Enable shortcut</description>
91768 <description>Shortcut between event SEQEND[n] and task STOP</description>
91774 <description>Disable shortcut</description>
91779 <description>Enable shortcut</description>
91786 <description>Shortcut between event LOOPSDONE and task DMA.SEQ[n].START</description>
91792 <description>Disable shortcut</description>
91797 <description>Enable shortcut</description>
91804 <description>Shortcut between event LOOPSDONE and task DMA.SEQ[n].START</description>
91810 <description>Disable shortcut</description>
91815 <description>Enable shortcut</description>
91822 <description>Shortcut between event LOOPSDONE and task STOP</description>
91828 <description>Disable shortcut</description>
91833 <description>Enable shortcut</description>
91840 <description>Shortcut between event RAMUNDERFLOW and task STOP</description>
91846 <description>Disable shortcut</description>
91851 <description>Enable shortcut</description>
91858 <description>Shortcut between event DMA.SEQ[n].BUSERROR and task STOP</description>
91864 <description>Disable shortcut</description>
91869 <description>Enable shortcut</description>
91876 <description>Shortcut between event DMA.SEQ[n].BUSERROR and task STOP</description>
91882 <description>Disable shortcut</description>
91887 <description>Enable shortcut</description>
91896 <description>Enable or disable interrupt</description>
91904 <description>Enable or disable interrupt for event STOPPED</description>
91910 <description>Disable</description>
91915 <description>Enable</description>
91922 <description>Enable or disable interrupt for event SEQSTARTED[0]</description>
91928 <description>Disable</description>
91933 <description>Enable</description>
91940 <description>Enable or disable interrupt for event SEQSTARTED[1]</description>
91946 <description>Disable</description>
91951 <description>Enable</description>
91958 <description>Enable or disable interrupt for event SEQEND[0]</description>
91964 <description>Disable</description>
91969 <description>Enable</description>
91976 <description>Enable or disable interrupt for event SEQEND[1]</description>
91982 <description>Disable</description>
91987 <description>Enable</description>
91994 <description>Enable or disable interrupt for event PWMPERIODEND</description>
92000 <description>Disable</description>
92005 <description>Enable</description>
92012 <description>Enable or disable interrupt for event LOOPSDONE</description>
92018 <description>Disable</description>
92023 <description>Enable</description>
92030 <description>Enable or disable interrupt for event RAMUNDERFLOW</description>
92036 <description>Disable</description>
92041 <description>Enable</description>
92048 <description>Enable or disable interrupt for event DMASEQ0END</description>
92054 <description>Disable</description>
92059 <description>Enable</description>
92066 <description>Enable or disable interrupt for event DMASEQ0READY</description>
92072 <description>Disable</description>
92077 <description>Enable</description>
92084 <description>Enable or disable interrupt for event DMASEQ0BUSERROR</description>
92090 <description>Disable</description>
92095 <description>Enable</description>
92102 <description>Enable or disable interrupt for event DMASEQ1END</description>
92108 <description>Disable</description>
92113 <description>Enable</description>
92120 <description>Enable or disable interrupt for event DMASEQ1READY</description>
92126 <description>Disable</description>
92131 <description>Enable</description>
92138 <description>Enable or disable interrupt for event DMASEQ1BUSERROR</description>
92144 <description>Disable</description>
92149 <description>Enable</description>
92156 <description>Enable or disable interrupt for event COMPAREMATCH[0]</description>
92162 <description>Disable</description>
92167 <description>Enable</description>
92174 <description>Enable or disable interrupt for event COMPAREMATCH[1]</description>
92180 <description>Disable</description>
92185 <description>Enable</description>
92192 <description>Enable or disable interrupt for event COMPAREMATCH[2]</description>
92198 <description>Disable</description>
92203 <description>Enable</description>
92210 <description>Enable or disable interrupt for event COMPAREMATCH[3]</description>
92216 <description>Disable</description>
92221 <description>Enable</description>
92230 <description>Enable interrupt</description>
92238 <description>Write '1' to enable interrupt for event STOPPED</description>
92245 <description>Read: Disabled</description>
92250 <description>Read: Enabled</description>
92258 <description>Enable</description>
92265 <description>Write '1' to enable interrupt for event SEQSTARTED[0]</description>
92272 <description>Read: Disabled</description>
92277 <description>Read: Enabled</description>
92285 <description>Enable</description>
92292 <description>Write '1' to enable interrupt for event SEQSTARTED[1]</description>
92299 <description>Read: Disabled</description>
92304 <description>Read: Enabled</description>
92312 <description>Enable</description>
92319 <description>Write '1' to enable interrupt for event SEQEND[0]</description>
92326 <description>Read: Disabled</description>
92331 <description>Read: Enabled</description>
92339 <description>Enable</description>
92346 <description>Write '1' to enable interrupt for event SEQEND[1]</description>
92353 <description>Read: Disabled</description>
92358 <description>Read: Enabled</description>
92366 <description>Enable</description>
92373 <description>Write '1' to enable interrupt for event PWMPERIODEND</description>
92380 <description>Read: Disabled</description>
92385 <description>Read: Enabled</description>
92393 <description>Enable</description>
92400 <description>Write '1' to enable interrupt for event LOOPSDONE</description>
92407 <description>Read: Disabled</description>
92412 <description>Read: Enabled</description>
92420 <description>Enable</description>
92427 <description>Write '1' to enable interrupt for event RAMUNDERFLOW</description>
92434 <description>Read: Disabled</description>
92439 <description>Read: Enabled</description>
92447 <description>Enable</description>
92454 <description>Write '1' to enable interrupt for event DMASEQ0END</description>
92461 <description>Read: Disabled</description>
92466 <description>Read: Enabled</description>
92474 <description>Enable</description>
92481 <description>Write '1' to enable interrupt for event DMASEQ0READY</description>
92488 <description>Read: Disabled</description>
92493 <description>Read: Enabled</description>
92501 <description>Enable</description>
92508 <description>Write '1' to enable interrupt for event DMASEQ0BUSERROR</description>
92515 <description>Read: Disabled</description>
92520 <description>Read: Enabled</description>
92528 <description>Enable</description>
92535 <description>Write '1' to enable interrupt for event DMASEQ1END</description>
92542 <description>Read: Disabled</description>
92547 <description>Read: Enabled</description>
92555 <description>Enable</description>
92562 <description>Write '1' to enable interrupt for event DMASEQ1READY</description>
92569 <description>Read: Disabled</description>
92574 <description>Read: Enabled</description>
92582 <description>Enable</description>
92589 <description>Write '1' to enable interrupt for event DMASEQ1BUSERROR</description>
92596 <description>Read: Disabled</description>
92601 <description>Read: Enabled</description>
92609 <description>Enable</description>
92616 <description>Write '1' to enable interrupt for event COMPAREMATCH[0]</description>
92623 <description>Read: Disabled</description>
92628 <description>Read: Enabled</description>
92636 <description>Enable</description>
92643 <description>Write '1' to enable interrupt for event COMPAREMATCH[1]</description>
92650 <description>Read: Disabled</description>
92655 <description>Read: Enabled</description>
92663 <description>Enable</description>
92670 <description>Write '1' to enable interrupt for event COMPAREMATCH[2]</description>
92677 <description>Read: Disabled</description>
92682 <description>Read: Enabled</description>
92690 <description>Enable</description>
92697 <description>Write '1' to enable interrupt for event COMPAREMATCH[3]</description>
92704 <description>Read: Disabled</description>
92709 <description>Read: Enabled</description>
92717 <description>Enable</description>
92726 <description>Disable interrupt</description>
92734 <description>Write '1' to disable interrupt for event STOPPED</description>
92741 <description>Read: Disabled</description>
92746 <description>Read: Enabled</description>
92754 <description>Disable</description>
92761 <description>Write '1' to disable interrupt for event SEQSTARTED[0]</description>
92768 <description>Read: Disabled</description>
92773 <description>Read: Enabled</description>
92781 <description>Disable</description>
92788 <description>Write '1' to disable interrupt for event SEQSTARTED[1]</description>
92795 <description>Read: Disabled</description>
92800 <description>Read: Enabled</description>
92808 <description>Disable</description>
92815 <description>Write '1' to disable interrupt for event SEQEND[0]</description>
92822 <description>Read: Disabled</description>
92827 <description>Read: Enabled</description>
92835 <description>Disable</description>
92842 <description>Write '1' to disable interrupt for event SEQEND[1]</description>
92849 <description>Read: Disabled</description>
92854 <description>Read: Enabled</description>
92862 <description>Disable</description>
92869 <description>Write '1' to disable interrupt for event PWMPERIODEND</description>
92876 <description>Read: Disabled</description>
92881 <description>Read: Enabled</description>
92889 <description>Disable</description>
92896 <description>Write '1' to disable interrupt for event LOOPSDONE</description>
92903 <description>Read: Disabled</description>
92908 <description>Read: Enabled</description>
92916 <description>Disable</description>
92923 <description>Write '1' to disable interrupt for event RAMUNDERFLOW</description>
92930 <description>Read: Disabled</description>
92935 <description>Read: Enabled</description>
92943 <description>Disable</description>
92950 <description>Write '1' to disable interrupt for event DMASEQ0END</description>
92957 <description>Read: Disabled</description>
92962 <description>Read: Enabled</description>
92970 <description>Disable</description>
92977 <description>Write '1' to disable interrupt for event DMASEQ0READY</description>
92984 <description>Read: Disabled</description>
92989 <description>Read: Enabled</description>
92997 <description>Disable</description>
93004 <description>Write '1' to disable interrupt for event DMASEQ0BUSERROR</description>
93011 <description>Read: Disabled</description>
93016 <description>Read: Enabled</description>
93024 <description>Disable</description>
93031 <description>Write '1' to disable interrupt for event DMASEQ1END</description>
93038 <description>Read: Disabled</description>
93043 <description>Read: Enabled</description>
93051 <description>Disable</description>
93058 <description>Write '1' to disable interrupt for event DMASEQ1READY</description>
93065 <description>Read: Disabled</description>
93070 <description>Read: Enabled</description>
93078 <description>Disable</description>
93085 <description>Write '1' to disable interrupt for event DMASEQ1BUSERROR</description>
93092 <description>Read: Disabled</description>
93097 <description>Read: Enabled</description>
93105 <description>Disable</description>
93112 <description>Write '1' to disable interrupt for event COMPAREMATCH[0]</description>
93119 <description>Read: Disabled</description>
93124 <description>Read: Enabled</description>
93132 <description>Disable</description>
93139 <description>Write '1' to disable interrupt for event COMPAREMATCH[1]</description>
93146 <description>Read: Disabled</description>
93151 <description>Read: Enabled</description>
93159 <description>Disable</description>
93166 <description>Write '1' to disable interrupt for event COMPAREMATCH[2]</description>
93173 <description>Read: Disabled</description>
93178 <description>Read: Enabled</description>
93186 <description>Disable</description>
93193 <description>Write '1' to disable interrupt for event COMPAREMATCH[3]</description>
93200 <description>Read: Disabled</description>
93205 <description>Read: Enabled</description>
93213 <description>Disable</description>
93222 <description>Pending interrupts</description>
93230 <description>Read pending status of interrupt for event STOPPED</description>
93237 <description>Read: Not pending</description>
93242 <description>Read: Pending</description>
93249 <description>Read pending status of interrupt for event SEQSTARTED[0]</description>
93256 <description>Read: Not pending</description>
93261 <description>Read: Pending</description>
93268 <description>Read pending status of interrupt for event SEQSTARTED[1]</description>
93275 <description>Read: Not pending</description>
93280 <description>Read: Pending</description>
93287 <description>Read pending status of interrupt for event SEQEND[0]</description>
93294 <description>Read: Not pending</description>
93299 <description>Read: Pending</description>
93306 <description>Read pending status of interrupt for event SEQEND[1]</description>
93313 <description>Read: Not pending</description>
93318 <description>Read: Pending</description>
93325 <description>Read pending status of interrupt for event PWMPERIODEND</description>
93332 <description>Read: Not pending</description>
93337 <description>Read: Pending</description>
93344 <description>Read pending status of interrupt for event LOOPSDONE</description>
93351 <description>Read: Not pending</description>
93356 <description>Read: Pending</description>
93363 <description>Read pending status of interrupt for event RAMUNDERFLOW</description>
93370 <description>Read: Not pending</description>
93375 <description>Read: Pending</description>
93382 <description>Read pending status of interrupt for event DMASEQ0END</description>
93389 <description>Read: Not pending</description>
93394 <description>Read: Pending</description>
93401 <description>Read pending status of interrupt for event DMASEQ0READY</description>
93408 <description>Read: Not pending</description>
93413 <description>Read: Pending</description>
93420 <description>Read pending status of interrupt for event DMASEQ0BUSERROR</description>
93427 <description>Read: Not pending</description>
93432 <description>Read: Pending</description>
93439 <description>Read pending status of interrupt for event DMASEQ1END</description>
93446 <description>Read: Not pending</description>
93451 <description>Read: Pending</description>
93458 <description>Read pending status of interrupt for event DMASEQ1READY</description>
93465 <description>Read: Not pending</description>
93470 <description>Read: Pending</description>
93477 <description>Read pending status of interrupt for event DMASEQ1BUSERROR</description>
93484 <description>Read: Not pending</description>
93489 <description>Read: Pending</description>
93496 <description>Read pending status of interrupt for event COMPAREMATCH[0]</description>
93503 <description>Read: Not pending</description>
93508 <description>Read: Pending</description>
93515 <description>Read pending status of interrupt for event COMPAREMATCH[1]</description>
93522 <description>Read: Not pending</description>
93527 <description>Read: Pending</description>
93534 <description>Read pending status of interrupt for event COMPAREMATCH[2]</description>
93541 <description>Read: Not pending</description>
93546 <description>Read: Pending</description>
93553 <description>Read pending status of interrupt for event COMPAREMATCH[3]</description>
93560 <description>Read: Not pending</description>
93565 <description>Read: Pending</description>
93574 <description>PWM module enable register</description>
93582 <description>Enable or disable PWM module</description>
93588 <description>Disabled</description>
93593 <description>Enable</description>
93602 <description>Selects operating mode of the wave counter</description>
93610 <description>Selects up mode or up-and-down mode for the counter</description>
93616 <description>Up counter, edge-aligned PWM duty cycle</description>
93621 <description>Up and down counter, center-aligned PWM duty cycle</description>
93630 <description>Value up to which the pulse generator counter counts</description>
93638 …description>Value up to which the pulse generator counter counts. This register is ignored when DE…
93646 <description>Configuration for PWM_CLK</description>
93654 <description>Prescaler of PWM_CLK</description>
93660 <description>Divide by 1 (16 MHz)</description>
93665 <description>Divide by 2 (8 MHz)</description>
93670 <description>Divide by 4 (4 MHz)</description>
93675 <description>Divide by 8 (2 MHz)</description>
93680 <description>Divide by 16 (1 MHz)</description>
93685 <description>Divide by 32 (500 kHz)</description>
93690 <description>Divide by 64 (250 kHz)</description>
93695 <description>Divide by 128 (125 kHz)</description>
93704 <description>Configuration of the decoder</description>
93712 … <description>How a sequence is read from RAM and spread to the compare register</description>
93718 <description>1st half word (16-bit) used in all PWM channels 0..3</description>
93723 … <description>1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3</description>
93728 … <description>1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3</description>
93733 … <description>1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP</description>
93740 <description>Selects source for advancing the active sequence</description>
93746 … <description>SEQ[n].REFRESH is used to determine loading internal compare registers</description>
93751 …<description>NEXTSTEP task causes a new value to be loaded to internal compare registers</descript…
93760 <description>Number of playbacks of a loop</description>
93768 <description>Number of playbacks of pattern cycles</description>
93774 <description>Looping disabled (stop at the end of the sequence)</description>
93783 <description>Configure the output value on the PWM channel during idle</description>
93791 <description>Idle output value for PWM channel [0]</description>
93797 <description>Idle output value for PWM channel [1]</description>
93803 <description>Idle output value for PWM channel [2]</description>
93809 <description>Idle output value for PWM channel [3]</description>
93819 <description>Unspecified</description>
93825 …<description>Description cluster: Number of additional PWM periods between samples loaded into com…
93833 …<description>Number of additional PWM periods between samples loaded into compare register (load e…
93839 <description>Update every PWM period</description>
93848 <description>Description cluster: Time added after the sequence</description>
93856 <description>Time added after the sequence in PWM periods</description>
93865 <description>Unspecified</description>
93873 <description>Description collection: Output pin select for PWM channel n</description>
93881 <description>Pin number</description>
93887 <description>Port number</description>
93893 <description>Connection</description>
93899 <description>Disconnect</description>
93904 <description>Connect</description>
93914 <description>Unspecified</description>
93922 <description>Unspecified</description>
93928 <description>Description cluster: RAM buffer start address</description>
93936 …<description>RAM buffer start address for this EasyDMA channel. This address is a word aligned Dat…
93944 … <description>Description cluster: Maximum number of bytes in channel buffer</description>
93952 <description>Maximum number of bytes in channel buffer</description>
93960 …<description>Description cluster: Number of bytes transferred in the last transaction, updated aft…
93968 …<description>Number of bytes transferred in the last transaction. In case of NACK error, includes …
93976 …<description>Description cluster: Number of bytes transferred in the current transaction</descript…
93984 …<description>Number of bytes transferred in the current transaction. Continuously updated.</descri…
93992 …<description>Description cluster: Terminate the transaction if a BUSERROR event is detected.</desc…
94005 <description>Disable</description>
94010 <description>Enable</description>
94019 …<description>Description cluster: Address of transaction that generated the last BUSERROR event.</…
94038 <description>SPI Slave 0</description>
94057 <description>Acquire SPI semaphore</description>
94065 <description>Acquire SPI semaphore</description>
94071 <description>Trigger task</description>
94080 <description>Release SPI semaphore, enabling the SPI slave to acquire it</description>
94088 <description>Release SPI semaphore, enabling the SPI slave to acquire it</description>
94094 <description>Trigger task</description>
94103 <description>Peripheral tasks.</description>
94109 <description>Peripheral tasks.</description>
94117 …<description>Description collection: Enables the MATCH[n] event by setting the ENABLE[n] bit in th…
94125 …<description>Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register.</desc…
94131 <description>Trigger task</description>
94142 …<description>Description collection: Disables the MATCH[n] event by clearing the ENABLE[n] bit in …
94150 …<description>Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register.</de…
94156 <description>Trigger task</description>
94167 <description>Subscribe configuration for task ACQUIRE</description>
94175 <description>DPPI channel that task ACQUIRE will subscribe to</description>
94186 <description>Disable subscription</description>
94191 <description>Enable subscription</description>
94200 <description>Subscribe configuration for task RELEASE</description>
94208 <description>DPPI channel that task RELEASE will subscribe to</description>
94219 <description>Disable subscription</description>
94224 <description>Enable subscription</description>
94233 <description>Subscribe configuration for tasks</description>
94239 <description>Subscribe configuration for tasks</description>
94247 … <description>Description collection: Subscribe configuration for task ENABLEMATCH[n]</description>
94255 <description>DPPI channel that task ENABLEMATCH[n] will subscribe to</description>
94266 <description>Disable subscription</description>
94271 <description>Enable subscription</description>
94282 …<description>Description collection: Subscribe configuration for task DISABLEMATCH[n]</description>
94290 … <description>DPPI channel that task DISABLEMATCH[n] will subscribe to</description>
94301 <description>Disable subscription</description>
94306 <description>Enable subscription</description>
94317 <description>Granted transaction completed</description>
94325 <description>Granted transaction completed</description>
94331 <description>Event not generated</description>
94336 <description>Event generated</description>
94345 <description>Semaphore acquired</description>
94353 <description>Semaphore acquired</description>
94359 <description>Event not generated</description>
94364 <description>Event generated</description>
94373 <description>Peripheral events.</description>
94379 <description>Peripheral events.</description>
94385 <description>Generated after all MAXCNT bytes have been transferred</description>
94393 <description>Generated after all MAXCNT bytes have been transferred</description>
94399 <description>Event not generated</description>
94404 <description>Event generated</description>
94413 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
94421 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
94427 <description>Event not generated</description>
94432 <description>Event generated</description>
94441 <description>An error occured during the bus transfer.</description>
94449 <description>An error occured during the bus transfer.</description>
94455 <description>Event not generated</description>
94460 <description>Event generated</description>
94471 … <description>Description collection: Pattern match is detected on the DMA data bus.</description>
94479 <description>Pattern match is detected on the DMA data bus.</description>
94485 <description>Event not generated</description>
94490 <description>Event generated</description>
94500 <description>Peripheral events.</description>
94506 <description>Generated after all MAXCNT bytes have been transferred</description>
94514 <description>Generated after all MAXCNT bytes have been transferred</description>
94520 <description>Event not generated</description>
94525 <description>Event generated</description>
94534 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
94542 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
94548 <description>Event not generated</description>
94553 <description>Event generated</description>
94562 <description>An error occured during the bus transfer.</description>
94570 <description>An error occured during the bus transfer.</description>
94576 <description>Event not generated</description>
94581 <description>Event generated</description>
94592 <description>Publish configuration for event END</description>
94600 <description>DPPI channel that event END will publish to</description>
94611 <description>Disable publishing</description>
94616 <description>Enable publishing</description>
94625 <description>Publish configuration for event ACQUIRED</description>
94633 <description>DPPI channel that event ACQUIRED will publish to</description>
94644 <description>Disable publishing</description>
94649 <description>Enable publishing</description>
94658 <description>Publish configuration for events</description>
94664 <description>Publish configuration for events</description>
94670 <description>Publish configuration for event END</description>
94678 <description>DPPI channel that event END will publish to</description>
94689 <description>Disable publishing</description>
94694 <description>Enable publishing</description>
94703 <description>Publish configuration for event READY</description>
94711 <description>DPPI channel that event READY will publish to</description>
94722 <description>Disable publishing</description>
94727 <description>Enable publishing</description>
94736 <description>Publish configuration for event BUSERROR</description>
94744 <description>DPPI channel that event BUSERROR will publish to</description>
94755 <description>Disable publishing</description>
94760 <description>Enable publishing</description>
94771 … <description>Description collection: Publish configuration for event MATCH[n]</description>
94779 <description>DPPI channel that event MATCH[n] will publish to</description>
94790 <description>Disable publishing</description>
94795 <description>Enable publishing</description>
94805 <description>Publish configuration for events</description>
94811 <description>Publish configuration for event END</description>
94819 <description>DPPI channel that event END will publish to</description>
94830 <description>Disable publishing</description>
94835 <description>Enable publishing</description>
94844 <description>Publish configuration for event READY</description>
94852 <description>DPPI channel that event READY will publish to</description>
94863 <description>Disable publishing</description>
94868 <description>Enable publishing</description>
94877 <description>Publish configuration for event BUSERROR</description>
94885 <description>DPPI channel that event BUSERROR will publish to</description>
94896 <description>Disable publishing</description>
94901 <description>Enable publishing</description>
94912 <description>Shortcuts between local events and tasks</description>
94920 <description>Shortcut between event END and task ACQUIRE</description>
94926 <description>Disable shortcut</description>
94931 <description>Enable shortcut</description>
94938 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows daisy-ch…
94944 <description>Disable shortcut</description>
94949 <description>Enable shortcut</description>
94956 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows daisy-ch…
94962 <description>Disable shortcut</description>
94967 <description>Enable shortcut</description>
94974 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows daisy-ch…
94980 <description>Disable shortcut</description>
94985 <description>Enable shortcut</description>
94992 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows daisy-ch…
94998 <description>Disable shortcut</description>
95003 <description>Enable shortcut</description>
95010 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
95016 <description>Disable shortcut</description>
95021 <description>Enable shortcut</description>
95028 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
95034 <description>Disable shortcut</description>
95039 <description>Enable shortcut</description>
95046 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
95052 <description>Disable shortcut</description>
95057 <description>Enable shortcut</description>
95064 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
95070 <description>Disable shortcut</description>
95075 <description>Enable shortcut</description>
95084 <description>Enable interrupt</description>
95092 <description>Write '1' to enable interrupt for event END</description>
95099 <description>Read: Disabled</description>
95104 <description>Read: Enabled</description>
95112 <description>Enable</description>
95119 <description>Write '1' to enable interrupt for event ACQUIRED</description>
95126 <description>Read: Disabled</description>
95131 <description>Read: Enabled</description>
95139 <description>Enable</description>
95146 <description>Write '1' to enable interrupt for event DMARXEND</description>
95153 <description>Read: Disabled</description>
95158 <description>Read: Enabled</description>
95166 <description>Enable</description>
95173 <description>Write '1' to enable interrupt for event DMARXREADY</description>
95180 <description>Read: Disabled</description>
95185 <description>Read: Enabled</description>
95193 <description>Enable</description>
95200 <description>Write '1' to enable interrupt for event DMARXBUSERROR</description>
95207 <description>Read: Disabled</description>
95212 <description>Read: Enabled</description>
95220 <description>Enable</description>
95227 <description>Write '1' to enable interrupt for event DMARXMATCH[0]</description>
95234 <description>Read: Disabled</description>
95239 <description>Read: Enabled</description>
95247 <description>Enable</description>
95254 <description>Write '1' to enable interrupt for event DMARXMATCH[1]</description>
95261 <description>Read: Disabled</description>
95266 <description>Read: Enabled</description>
95274 <description>Enable</description>
95281 <description>Write '1' to enable interrupt for event DMARXMATCH[2]</description>
95288 <description>Read: Disabled</description>
95293 <description>Read: Enabled</description>
95301 <description>Enable</description>
95308 <description>Write '1' to enable interrupt for event DMARXMATCH[3]</description>
95315 <description>Read: Disabled</description>
95320 <description>Read: Enabled</description>
95328 <description>Enable</description>
95335 <description>Write '1' to enable interrupt for event DMATXEND</description>
95342 <description>Read: Disabled</description>
95347 <description>Read: Enabled</description>
95355 <description>Enable</description>
95362 <description>Write '1' to enable interrupt for event DMATXREADY</description>
95369 <description>Read: Disabled</description>
95374 <description>Read: Enabled</description>
95382 <description>Enable</description>
95389 <description>Write '1' to enable interrupt for event DMATXBUSERROR</description>
95396 <description>Read: Disabled</description>
95401 <description>Read: Enabled</description>
95409 <description>Enable</description>
95418 <description>Disable interrupt</description>
95426 <description>Write '1' to disable interrupt for event END</description>
95433 <description>Read: Disabled</description>
95438 <description>Read: Enabled</description>
95446 <description>Disable</description>
95453 <description>Write '1' to disable interrupt for event ACQUIRED</description>
95460 <description>Read: Disabled</description>
95465 <description>Read: Enabled</description>
95473 <description>Disable</description>
95480 <description>Write '1' to disable interrupt for event DMARXEND</description>
95487 <description>Read: Disabled</description>
95492 <description>Read: Enabled</description>
95500 <description>Disable</description>
95507 <description>Write '1' to disable interrupt for event DMARXREADY</description>
95514 <description>Read: Disabled</description>
95519 <description>Read: Enabled</description>
95527 <description>Disable</description>
95534 <description>Write '1' to disable interrupt for event DMARXBUSERROR</description>
95541 <description>Read: Disabled</description>
95546 <description>Read: Enabled</description>
95554 <description>Disable</description>
95561 <description>Write '1' to disable interrupt for event DMARXMATCH[0]</description>
95568 <description>Read: Disabled</description>
95573 <description>Read: Enabled</description>
95581 <description>Disable</description>
95588 <description>Write '1' to disable interrupt for event DMARXMATCH[1]</description>
95595 <description>Read: Disabled</description>
95600 <description>Read: Enabled</description>
95608 <description>Disable</description>
95615 <description>Write '1' to disable interrupt for event DMARXMATCH[2]</description>
95622 <description>Read: Disabled</description>
95627 <description>Read: Enabled</description>
95635 <description>Disable</description>
95642 <description>Write '1' to disable interrupt for event DMARXMATCH[3]</description>
95649 <description>Read: Disabled</description>
95654 <description>Read: Enabled</description>
95662 <description>Disable</description>
95669 <description>Write '1' to disable interrupt for event DMATXEND</description>
95676 <description>Read: Disabled</description>
95681 <description>Read: Enabled</description>
95689 <description>Disable</description>
95696 <description>Write '1' to disable interrupt for event DMATXREADY</description>
95703 <description>Read: Disabled</description>
95708 <description>Read: Enabled</description>
95716 <description>Disable</description>
95723 <description>Write '1' to disable interrupt for event DMATXBUSERROR</description>
95730 <description>Read: Disabled</description>
95735 <description>Read: Enabled</description>
95743 <description>Disable</description>
95752 <description>Semaphore status register</description>
95760 <description>Semaphore status</description>
95766 <description>Semaphore is free</description>
95771 <description>Semaphore is assigned to CPU</description>
95776 <description>Semaphore is assigned to SPI slave</description>
95781 … <description>Semaphore is assigned to SPI but a handover to the CPU is pending</description>
95790 <description>Status from last transaction</description>
95798 <description>TX buffer over-read detected, and prevented</description>
95805 <description>Read: error not present</description>
95810 <description>Read: error present</description>
95818 <description>Write: clear error on writing '1'</description>
95825 <description>RX buffer overflow detected, and prevented</description>
95832 <description>Read: error not present</description>
95837 <description>Read: error present</description>
95845 <description>Write: clear error on writing '1'</description>
95854 <description>Enable SPI slave</description>
95862 <description>Enable or disable SPI slave</description>
95868 <description>Disable SPI slave</description>
95873 <description>Enable SPI slave</description>
95882 <description>Configuration register</description>
95890 <description>Bit order</description>
95896 <description>Most significant bit shifted out first</description>
95901 <description>Least significant bit shifted out first</description>
95908 <description>Serial clock (SCK) phase</description>
95914 … <description>Sample on leading edge of clock, shift serial data on trailing edge</description>
95919 … <description>Sample on trailing edge of clock, shift serial data on leading edge</description>
95926 <description>Serial clock (SCK) polarity</description>
95932 <description>Active high</description>
95937 <description>Active low</description>
95946 …<description>Default character. Character clocked out in case of an ignored transaction.</descript…
95954 …<description>Default character. Character clocked out in case of an ignored transaction.</descript…
95962 <description>Over-read character</description>
95970 …<description>Over-read character. Character clocked out after an over-read of the transmit buffer.…
95978 <description>Unspecified</description>
95984 <description>Pin select for SCK</description>
95992 <description>Pin number</description>
95998 <description>Port number</description>
96004 <description>Connection</description>
96010 <description>Disconnect</description>
96015 <description>Connect</description>
96024 <description>Pin select for MISO signal</description>
96032 <description>Pin number</description>
96038 <description>Port number</description>
96044 <description>Connection</description>
96050 <description>Disconnect</description>
96055 <description>Connect</description>
96064 <description>Pin select for MOSI signal</description>
96072 <description>Pin number</description>
96078 <description>Port number</description>
96084 <description>Connection</description>
96090 <description>Disconnect</description>
96095 <description>Connect</description>
96104 <description>Pin select for CSN signal</description>
96112 <description>Pin number</description>
96118 <description>Port number</description>
96124 <description>Connection</description>
96130 <description>Disconnect</description>
96135 <description>Connect</description>
96145 <description>Unspecified</description>
96151 <description>Unspecified</description>
96157 <description>RAM buffer start address</description>
96165 …<description>RAM buffer start address for this EasyDMA channel. This address is a word aligned Dat…
96173 <description>Maximum number of bytes in channel buffer</description>
96181 <description>Maximum number of bytes in channel buffer</description>
96189 …<description>Number of bytes transferred in the last transaction, updated after the END event. Als…
96197 …<description>Number of bytes transferred in the last transaction. In case of NACK error, includes …
96205 <description>Number of bytes transferred in the current transaction</description>
96213 …<description>Number of bytes transferred in the current transaction. Continuously updated.</descri…
96221 <description>EasyDMA list type</description>
96229 <description>List type</description>
96235 <description>Disable EasyDMA list</description>
96240 <description>Use array list</description>
96249 <description>Terminate the transaction if a BUSERROR event is detected.</description>
96262 <description>Disable</description>
96267 <description>Enable</description>
96276 … <description>Address of transaction that generated the last BUSERROR event.</description>
96291 … <description>Registers to control the behavior of the pattern matcher engine</description>
96297 <description>Configure individual match events</description>
96305 <description>Enable match filter 0</description>
96311 <description>Match filter disabled</description>
96316 <description>Match filter enabled</description>
96323 <description>Enable match filter 1</description>
96329 <description>Match filter disabled</description>
96334 <description>Match filter enabled</description>
96341 <description>Enable match filter 2</description>
96347 <description>Match filter disabled</description>
96352 <description>Match filter enabled</description>
96359 <description>Enable match filter 3</description>
96365 <description>Match filter disabled</description>
96370 <description>Match filter enabled</description>
96377 <description>Configure match filter 0 as one-shot or sticky</description>
96383 <description>Match filter stays enabled until disabled by task</description>
96388 … <description>Match filter stays enabled until next data word is received</description>
96395 <description>Configure match filter 1 as one-shot or sticky</description>
96401 <description>Match filter stays enabled until disabled by task</description>
96406 … <description>Match filter stays enabled until next data word is received</description>
96413 <description>Configure match filter 2 as one-shot or sticky</description>
96419 <description>Match filter stays enabled until disabled by task</description>
96424 … <description>Match filter stays enabled until next data word is received</description>
96431 <description>Configure match filter 3 as one-shot or sticky</description>
96437 <description>Match filter stays enabled until disabled by task</description>
96442 … <description>Match filter stays enabled until next data word is received</description>
96453 …<description>Description collection: The data to look for - any match will trigger the MATCH[n] ev…
96461 <description>Data to look for</description>
96471 <description>Unspecified</description>
96477 <description>RAM buffer start address</description>
96485 …<description>RAM buffer start address for this EasyDMA channel. This address is a word aligned Dat…
96493 <description>Maximum number of bytes in channel buffer</description>
96501 <description>Maximum number of bytes in channel buffer</description>
96509 …<description>Number of bytes transferred in the last transaction, updated after the END event. Als…
96517 …<description>Number of bytes transferred in the last transaction. In case of NACK error, includes …
96525 <description>Number of bytes transferred in the current transaction</description>
96533 …<description>Number of bytes transferred in the current transaction. Continuously updated.</descri…
96541 <description>EasyDMA list type</description>
96549 <description>List type</description>
96555 <description>Disable EasyDMA list</description>
96560 <description>Use array list</description>
96569 <description>Terminate the transaction if a BUSERROR event is detected.</description>
96582 <description>Disable</description>
96587 <description>Enable</description>
96596 … <description>Address of transaction that generated the last BUSERROR event.</description>
96615 <description>Serial Peripheral Interface Master with EasyDMA 0</description>
96634 <description>Start SPI transaction</description>
96642 <description>Start SPI transaction</description>
96648 <description>Trigger task</description>
96657 <description>Stop SPI transaction</description>
96665 <description>Stop SPI transaction</description>
96671 <description>Trigger task</description>
96680 <description>Suspend SPI transaction</description>
96688 <description>Suspend SPI transaction</description>
96694 <description>Trigger task</description>
96703 <description>Resume SPI transaction</description>
96711 <description>Resume SPI transaction</description>
96717 <description>Trigger task</description>
96726 <description>Peripheral tasks.</description>
96732 <description>Peripheral tasks.</description>
96740 …<description>Description collection: Enables the MATCH[n] event by setting the ENABLE[n] bit in th…
96748 …<description>Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register.</desc…
96754 <description>Trigger task</description>
96765 …<description>Description collection: Disables the MATCH[n] event by clearing the ENABLE[n] bit in …
96773 …<description>Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register.</de…
96779 <description>Trigger task</description>
96790 <description>Subscribe configuration for task START</description>
96798 <description>DPPI channel that task START will subscribe to</description>
96809 <description>Disable subscription</description>
96814 <description>Enable subscription</description>
96823 <description>Subscribe configuration for task STOP</description>
96831 <description>DPPI channel that task STOP will subscribe to</description>
96842 <description>Disable subscription</description>
96847 <description>Enable subscription</description>
96856 <description>Subscribe configuration for task SUSPEND</description>
96864 <description>DPPI channel that task SUSPEND will subscribe to</description>
96875 <description>Disable subscription</description>
96880 <description>Enable subscription</description>
96889 <description>Subscribe configuration for task RESUME</description>
96897 <description>DPPI channel that task RESUME will subscribe to</description>
96908 <description>Disable subscription</description>
96913 <description>Enable subscription</description>
96922 <description>Subscribe configuration for tasks</description>
96928 <description>Subscribe configuration for tasks</description>
96936 … <description>Description collection: Subscribe configuration for task ENABLEMATCH[n]</description>
96944 <description>DPPI channel that task ENABLEMATCH[n] will subscribe to</description>
96955 <description>Disable subscription</description>
96960 <description>Enable subscription</description>
96971 …<description>Description collection: Subscribe configuration for task DISABLEMATCH[n]</description>
96979 … <description>DPPI channel that task DISABLEMATCH[n] will subscribe to</description>
96990 <description>Disable subscription</description>
96995 <description>Enable subscription</description>
97006 <description>SPI transaction has started</description>
97014 <description>SPI transaction has started</description>
97020 <description>Event not generated</description>
97025 <description>Event generated</description>
97034 <description>SPI transaction has stopped</description>
97042 <description>SPI transaction has stopped</description>
97048 <description>Event not generated</description>
97053 <description>Event generated</description>
97062 <description>End of RXD buffer and TXD buffer reached</description>
97070 <description>End of RXD buffer and TXD buffer reached</description>
97076 <description>Event not generated</description>
97081 <description>Event generated</description>
97090 <description>Peripheral events.</description>
97096 <description>Peripheral events.</description>
97102 <description>Generated after all MAXCNT bytes have been transferred</description>
97110 <description>Generated after all MAXCNT bytes have been transferred</description>
97116 <description>Event not generated</description>
97121 <description>Event generated</description>
97130 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
97138 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
97144 <description>Event not generated</description>
97149 <description>Event generated</description>
97158 <description>An error occured during the bus transfer.</description>
97166 <description>An error occured during the bus transfer.</description>
97172 <description>Event not generated</description>
97177 <description>Event generated</description>
97188 … <description>Description collection: Pattern match is detected on the DMA data bus.</description>
97196 <description>Pattern match is detected on the DMA data bus.</description>
97202 <description>Event not generated</description>
97207 <description>Event generated</description>
97217 <description>Peripheral events.</description>
97223 <description>Generated after all MAXCNT bytes have been transferred</description>
97231 <description>Generated after all MAXCNT bytes have been transferred</description>
97237 <description>Event not generated</description>
97242 <description>Event generated</description>
97251 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
97259 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
97265 <description>Event not generated</description>
97270 <description>Event generated</description>
97279 <description>An error occured during the bus transfer.</description>
97287 <description>An error occured during the bus transfer.</description>
97293 <description>Event not generated</description>
97298 <description>Event generated</description>
97309 <description>Publish configuration for event STARTED</description>
97317 <description>DPPI channel that event STARTED will publish to</description>
97328 <description>Disable publishing</description>
97333 <description>Enable publishing</description>
97342 <description>Publish configuration for event STOPPED</description>
97350 <description>DPPI channel that event STOPPED will publish to</description>
97361 <description>Disable publishing</description>
97366 <description>Enable publishing</description>
97375 <description>Publish configuration for event END</description>
97383 <description>DPPI channel that event END will publish to</description>
97394 <description>Disable publishing</description>
97399 <description>Enable publishing</description>
97408 <description>Publish configuration for events</description>
97414 <description>Publish configuration for events</description>
97420 <description>Publish configuration for event END</description>
97428 <description>DPPI channel that event END will publish to</description>
97439 <description>Disable publishing</description>
97444 <description>Enable publishing</description>
97453 <description>Publish configuration for event READY</description>
97461 <description>DPPI channel that event READY will publish to</description>
97472 <description>Disable publishing</description>
97477 <description>Enable publishing</description>
97486 <description>Publish configuration for event BUSERROR</description>
97494 <description>DPPI channel that event BUSERROR will publish to</description>
97505 <description>Disable publishing</description>
97510 <description>Enable publishing</description>
97521 … <description>Description collection: Publish configuration for event MATCH[n]</description>
97529 <description>DPPI channel that event MATCH[n] will publish to</description>
97540 <description>Disable publishing</description>
97545 <description>Enable publishing</description>
97555 <description>Publish configuration for events</description>
97561 <description>Publish configuration for event END</description>
97569 <description>DPPI channel that event END will publish to</description>
97580 <description>Disable publishing</description>
97585 <description>Enable publishing</description>
97594 <description>Publish configuration for event READY</description>
97602 <description>DPPI channel that event READY will publish to</description>
97613 <description>Disable publishing</description>
97618 <description>Enable publishing</description>
97627 <description>Publish configuration for event BUSERROR</description>
97635 <description>DPPI channel that event BUSERROR will publish to</description>
97646 <description>Disable publishing</description>
97651 <description>Enable publishing</description>
97662 <description>Shortcuts between local events and tasks</description>
97670 <description>Shortcut between event END and task START</description>
97676 <description>Disable shortcut</description>
97681 <description>Enable shortcut</description>
97688 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows daisy-ch…
97694 <description>Disable shortcut</description>
97699 <description>Enable shortcut</description>
97706 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows daisy-ch…
97712 <description>Disable shortcut</description>
97717 <description>Enable shortcut</description>
97724 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows daisy-ch…
97730 <description>Disable shortcut</description>
97735 <description>Enable shortcut</description>
97742 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows daisy-ch…
97748 <description>Disable shortcut</description>
97753 <description>Enable shortcut</description>
97760 … <description>Shortcut between event DMA.RX.MATCH[0] and task DMA.RX.DISABLEMATCH[0]</description>
97766 <description>Disable shortcut</description>
97771 <description>Enable shortcut</description>
97778 … <description>Shortcut between event DMA.RX.MATCH[1] and task DMA.RX.DISABLEMATCH[1]</description>
97784 <description>Disable shortcut</description>
97789 <description>Enable shortcut</description>
97796 … <description>Shortcut between event DMA.RX.MATCH[2] and task DMA.RX.DISABLEMATCH[2]</description>
97802 <description>Disable shortcut</description>
97807 <description>Enable shortcut</description>
97814 … <description>Shortcut between event DMA.RX.MATCH[3] and task DMA.RX.DISABLEMATCH[3]</description>
97820 <description>Disable shortcut</description>
97825 <description>Enable shortcut</description>
97834 <description>Enable interrupt</description>
97842 <description>Write '1' to enable interrupt for event STARTED</description>
97849 <description>Read: Disabled</description>
97854 <description>Read: Enabled</description>
97862 <description>Enable</description>
97869 <description>Write '1' to enable interrupt for event STOPPED</description>
97876 <description>Read: Disabled</description>
97881 <description>Read: Enabled</description>
97889 <description>Enable</description>
97896 <description>Write '1' to enable interrupt for event END</description>
97903 <description>Read: Disabled</description>
97908 <description>Read: Enabled</description>
97916 <description>Enable</description>
97923 <description>Write '1' to enable interrupt for event DMARXEND</description>
97930 <description>Read: Disabled</description>
97935 <description>Read: Enabled</description>
97943 <description>Enable</description>
97950 <description>Write '1' to enable interrupt for event DMARXREADY</description>
97957 <description>Read: Disabled</description>
97962 <description>Read: Enabled</description>
97970 <description>Enable</description>
97977 <description>Write '1' to enable interrupt for event DMARXBUSERROR</description>
97984 <description>Read: Disabled</description>
97989 <description>Read: Enabled</description>
97997 <description>Enable</description>
98004 <description>Write '1' to enable interrupt for event DMARXMATCH[0]</description>
98011 <description>Read: Disabled</description>
98016 <description>Read: Enabled</description>
98024 <description>Enable</description>
98031 <description>Write '1' to enable interrupt for event DMARXMATCH[1]</description>
98038 <description>Read: Disabled</description>
98043 <description>Read: Enabled</description>
98051 <description>Enable</description>
98058 <description>Write '1' to enable interrupt for event DMARXMATCH[2]</description>
98065 <description>Read: Disabled</description>
98070 <description>Read: Enabled</description>
98078 <description>Enable</description>
98085 <description>Write '1' to enable interrupt for event DMARXMATCH[3]</description>
98092 <description>Read: Disabled</description>
98097 <description>Read: Enabled</description>
98105 <description>Enable</description>
98112 <description>Write '1' to enable interrupt for event DMATXEND</description>
98119 <description>Read: Disabled</description>
98124 <description>Read: Enabled</description>
98132 <description>Enable</description>
98139 <description>Write '1' to enable interrupt for event DMATXREADY</description>
98146 <description>Read: Disabled</description>
98151 <description>Read: Enabled</description>
98159 <description>Enable</description>
98166 <description>Write '1' to enable interrupt for event DMATXBUSERROR</description>
98173 <description>Read: Disabled</description>
98178 <description>Read: Enabled</description>
98186 <description>Enable</description>
98195 <description>Disable interrupt</description>
98203 <description>Write '1' to disable interrupt for event STARTED</description>
98210 <description>Read: Disabled</description>
98215 <description>Read: Enabled</description>
98223 <description>Disable</description>
98230 <description>Write '1' to disable interrupt for event STOPPED</description>
98237 <description>Read: Disabled</description>
98242 <description>Read: Enabled</description>
98250 <description>Disable</description>
98257 <description>Write '1' to disable interrupt for event END</description>
98264 <description>Read: Disabled</description>
98269 <description>Read: Enabled</description>
98277 <description>Disable</description>
98284 <description>Write '1' to disable interrupt for event DMARXEND</description>
98291 <description>Read: Disabled</description>
98296 <description>Read: Enabled</description>
98304 <description>Disable</description>
98311 <description>Write '1' to disable interrupt for event DMARXREADY</description>
98318 <description>Read: Disabled</description>
98323 <description>Read: Enabled</description>
98331 <description>Disable</description>
98338 <description>Write '1' to disable interrupt for event DMARXBUSERROR</description>
98345 <description>Read: Disabled</description>
98350 <description>Read: Enabled</description>
98358 <description>Disable</description>
98365 <description>Write '1' to disable interrupt for event DMARXMATCH[0]</description>
98372 <description>Read: Disabled</description>
98377 <description>Read: Enabled</description>
98385 <description>Disable</description>
98392 <description>Write '1' to disable interrupt for event DMARXMATCH[1]</description>
98399 <description>Read: Disabled</description>
98404 <description>Read: Enabled</description>
98412 <description>Disable</description>
98419 <description>Write '1' to disable interrupt for event DMARXMATCH[2]</description>
98426 <description>Read: Disabled</description>
98431 <description>Read: Enabled</description>
98439 <description>Disable</description>
98446 <description>Write '1' to disable interrupt for event DMARXMATCH[3]</description>
98453 <description>Read: Disabled</description>
98458 <description>Read: Enabled</description>
98466 <description>Disable</description>
98473 <description>Write '1' to disable interrupt for event DMATXEND</description>
98480 <description>Read: Disabled</description>
98485 <description>Read: Enabled</description>
98493 <description>Disable</description>
98500 <description>Write '1' to disable interrupt for event DMATXREADY</description>
98507 <description>Read: Disabled</description>
98512 <description>Read: Enabled</description>
98520 <description>Disable</description>
98527 <description>Write '1' to disable interrupt for event DMATXBUSERROR</description>
98534 <description>Read: Disabled</description>
98539 <description>Read: Enabled</description>
98547 <description>Disable</description>
98556 <description>Enable SPIM</description>
98564 <description>Enable or disable SPIM</description>
98570 <description>Disable SPIM</description>
98575 <description>Enable SPIM</description>
98584 <description>The prescaler is used to set the SPI frequency.</description>
98592 <description>Core clock to SCK divisor</description>
98600 <description>Configuration register</description>
98608 <description>Bit order</description>
98614 <description>Most significant bit shifted out first</description>
98619 <description>Least significant bit shifted out first</description>
98626 <description>Serial clock (SCK) phase</description>
98632 … <description>Sample on leading edge of clock, shift serial data on trailing edge</description>
98637 … <description>Sample on trailing edge of clock, shift serial data on leading edge</description>
98644 <description>Serial clock (SCK) polarity</description>
98650 <description>Active high</description>
98655 <description>Active low</description>
98664 …description>Stall status for EasyDMA RAM accesses. The fields in this register are set to STALL by…
98672 <description>Stall status for EasyDMA RAM reads</description>
98678 <description>No stall</description>
98683 <description>A stall has occurred</description>
98692 <description>Unspecified</description>
98698 <description>Sample delay for input serial data on MISO</description>
98706 …description>Sample delay for input serial data on MISO. The value specifies the number of SPIM cor…
98714 …description>Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, t…
98722 …description>Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, t…
98731 <description>DCX configuration</description>
98739 …description>This register specifies the number of command bytes preceding the data bytes. The PSEL…
98747 <description>Polarity of CSN output</description>
98755 <description>Polarity of CSN output</description>
98761 <description>Active low (idle state high)</description>
98766 <description>Active high (idle state low)</description>
98775 …<description>Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MA…
98783 …<description>Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MA…
98791 <description>Unspecified</description>
98797 <description>Pin select for SCK</description>
98805 <description>Pin number</description>
98811 <description>Port number</description>
98817 <description>Connection</description>
98823 <description>Disconnect</description>
98828 <description>Connect</description>
98837 <description>Pin select for MOSI signal</description>
98845 <description>Pin number</description>
98851 <description>Port number</description>
98857 <description>Connection</description>
98863 <description>Disconnect</description>
98868 <description>Connect</description>
98877 <description>Pin select for MISO signal</description>
98885 <description>Pin number</description>
98891 <description>Port number</description>
98897 <description>Connection</description>
98903 <description>Disconnect</description>
98908 <description>Connect</description>
98917 <description>Pin select for DCX signal</description>
98925 <description>Pin number</description>
98931 <description>Port number</description>
98937 <description>Connection</description>
98943 <description>Disconnect</description>
98948 <description>Connect</description>
98957 <description>Pin select for CSN</description>
98965 <description>Pin number</description>
98971 <description>Port number</description>
98977 <description>Connection</description>
98983 <description>Disconnect</description>
98988 <description>Connect</description>
98998 <description>Unspecified</description>
99004 <description>Unspecified</description>
99010 <description>RAM buffer start address</description>
99018 …<description>RAM buffer start address for this EasyDMA channel. This address is a word aligned Dat…
99026 <description>Maximum number of bytes in channel buffer</description>
99034 <description>Maximum number of bytes in channel buffer</description>
99042 …<description>Number of bytes transferred in the last transaction, updated after the END event. Als…
99050 …<description>Number of bytes transferred in the last transaction. In case of NACK error, includes …
99058 <description>Number of bytes transferred in the current transaction</description>
99066 …<description>Number of bytes transferred in the current transaction. Continuously updated.</descri…
99074 <description>EasyDMA list type</description>
99082 <description>List type</description>
99088 <description>Disable EasyDMA list</description>
99093 <description>Use array list</description>
99102 <description>Terminate the transaction if a BUSERROR event is detected.</description>
99115 <description>Disable</description>
99120 <description>Enable</description>
99129 … <description>Address of transaction that generated the last BUSERROR event.</description>
99144 … <description>Registers to control the behavior of the pattern matcher engine</description>
99150 <description>Configure individual match events</description>
99158 <description>Enable match filter 0</description>
99164 <description>Match filter disabled</description>
99169 <description>Match filter enabled</description>
99176 <description>Enable match filter 1</description>
99182 <description>Match filter disabled</description>
99187 <description>Match filter enabled</description>
99194 <description>Enable match filter 2</description>
99200 <description>Match filter disabled</description>
99205 <description>Match filter enabled</description>
99212 <description>Enable match filter 3</description>
99218 <description>Match filter disabled</description>
99223 <description>Match filter enabled</description>
99230 <description>Configure match filter 0 as one-shot or sticky</description>
99236 <description>Match filter stays enabled until disabled by task</description>
99241 … <description>Match filter stays enabled until next data word is received</description>
99248 <description>Configure match filter 1 as one-shot or sticky</description>
99254 <description>Match filter stays enabled until disabled by task</description>
99259 … <description>Match filter stays enabled until next data word is received</description>
99266 <description>Configure match filter 2 as one-shot or sticky</description>
99272 <description>Match filter stays enabled until disabled by task</description>
99277 … <description>Match filter stays enabled until next data word is received</description>
99284 <description>Configure match filter 3 as one-shot or sticky</description>
99290 <description>Match filter stays enabled until disabled by task</description>
99295 … <description>Match filter stays enabled until next data word is received</description>
99306 …<description>Description collection: The data to look for - any match will trigger the MATCH[n] ev…
99314 <description>Data to look for</description>
99324 <description>Unspecified</description>
99330 <description>RAM buffer start address</description>
99338 …<description>RAM buffer start address for this EasyDMA channel. This address is a word aligned Dat…
99346 <description>Maximum number of bytes in channel buffer</description>
99354 <description>Maximum number of bytes in channel buffer</description>
99362 …<description>Number of bytes transferred in the last transaction, updated after the END event. Als…
99370 …<description>Number of bytes transferred in the last transaction. In case of NACK error, includes …
99378 <description>Number of bytes transferred in the current transaction</description>
99386 …<description>Number of bytes transferred in the current transaction. Continuously updated.</descri…
99394 <description>EasyDMA list type</description>
99402 <description>List type</description>
99408 <description>Disable EasyDMA list</description>
99413 <description>Use array list</description>
99422 <description>Terminate the transaction if a BUSERROR event is detected.</description>
99435 <description>Disable</description>
99440 <description>Enable</description>
99449 … <description>Address of transaction that generated the last BUSERROR event.</description>
99468 <description>UART with EasyDMA 0</description>
99488 <description>Flush RX FIFO into RX buffer</description>
99496 <description>Flush RX FIFO into RX buffer</description>
99502 <description>Trigger task</description>
99511 <description>Peripheral tasks.</description>
99517 <description>Peripheral tasks.</description>
99523 …<description>Starts operation using easyDMA to load the values. See peripheral description for ope…
99531 …<description>Starts operation using easyDMA to load the values. See peripheral description for ope…
99537 <description>Trigger task</description>
99546 … <description>Stops operation using easyDMA. This does not trigger an END event.</description>
99554 … <description>Stops operation using easyDMA. This does not trigger an END event.</description>
99560 <description>Trigger task</description>
99571 …<description>Description collection: Enables the MATCH[n] event by setting the ENABLE[n] bit in th…
99579 …<description>Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register.</desc…
99585 <description>Trigger task</description>
99596 …<description>Description collection: Disables the MATCH[n] event by clearing the ENABLE[n] bit in …
99604 …<description>Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register.</de…
99610 <description>Trigger task</description>
99620 <description>Peripheral tasks.</description>
99626 …<description>Starts operation using easyDMA to load the values. See peripheral description for ope…
99634 …<description>Starts operation using easyDMA to load the values. See peripheral description for ope…
99640 <description>Trigger task</description>
99649 … <description>Stops operation using easyDMA. This does not trigger an END event.</description>
99657 … <description>Stops operation using easyDMA. This does not trigger an END event.</description>
99663 <description>Trigger task</description>
99674 <description>Subscribe configuration for task FLUSHRX</description>
99682 <description>DPPI channel that task FLUSHRX will subscribe to</description>
99693 <description>Disable subscription</description>
99698 <description>Enable subscription</description>
99707 <description>Subscribe configuration for tasks</description>
99713 <description>Subscribe configuration for tasks</description>
99719 <description>Subscribe configuration for task START</description>
99727 <description>DPPI channel that task START will subscribe to</description>
99738 <description>Disable subscription</description>
99743 <description>Enable subscription</description>
99752 <description>Subscribe configuration for task STOP</description>
99760 <description>DPPI channel that task STOP will subscribe to</description>
99771 <description>Disable subscription</description>
99776 <description>Enable subscription</description>
99787 … <description>Description collection: Subscribe configuration for task ENABLEMATCH[n]</description>
99795 <description>DPPI channel that task ENABLEMATCH[n] will subscribe to</description>
99806 <description>Disable subscription</description>
99811 <description>Enable subscription</description>
99822 …<description>Description collection: Subscribe configuration for task DISABLEMATCH[n]</description>
99830 … <description>DPPI channel that task DISABLEMATCH[n] will subscribe to</description>
99841 <description>Disable subscription</description>
99846 <description>Enable subscription</description>
99856 <description>Subscribe configuration for tasks</description>
99862 <description>Subscribe configuration for task START</description>
99870 <description>DPPI channel that task START will subscribe to</description>
99881 <description>Disable subscription</description>
99886 <description>Enable subscription</description>
99895 <description>Subscribe configuration for task STOP</description>
99903 <description>DPPI channel that task STOP will subscribe to</description>
99914 <description>Disable subscription</description>
99919 <description>Enable subscription</description>
99930 <description>CTS is activated (set low). Clear To Send.</description>
99938 <description>CTS is activated (set low). Clear To Send.</description>
99944 <description>Event not generated</description>
99949 <description>Event generated</description>
99958 <description>CTS is deactivated (set high). Not Clear To Send.</description>
99966 <description>CTS is deactivated (set high). Not Clear To Send.</description>
99972 <description>Event not generated</description>
99977 <description>Event generated</description>
99986 <description>Data sent from TXD</description>
99994 <description>Data sent from TXD</description>
100000 <description>Event not generated</description>
100005 <description>Event generated</description>
100014 … <description>Data received in RXD (but potentially not yet transferred to Data RAM)</description>
100022 … <description>Data received in RXD (but potentially not yet transferred to Data RAM)</description>
100028 <description>Event not generated</description>
100033 <description>Event generated</description>
100042 <description>Error detected</description>
100050 <description>Error detected</description>
100056 <description>Event not generated</description>
100061 <description>Event generated</description>
100070 <description>Receiver timeout</description>
100078 <description>Receiver timeout</description>
100084 <description>Event not generated</description>
100089 <description>Event generated</description>
100098 <description>Transmitter stopped</description>
100106 <description>Transmitter stopped</description>
100112 <description>Event not generated</description>
100117 <description>Event generated</description>
100126 <description>Peripheral events.</description>
100132 <description>Peripheral events.</description>
100138 <description>Generated after all MAXCNT bytes have been transferred</description>
100146 <description>Generated after all MAXCNT bytes have been transferred</description>
100152 <description>Event not generated</description>
100157 <description>Event generated</description>
100166 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
100174 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
100180 <description>Event not generated</description>
100185 <description>Event generated</description>
100194 <description>An error occured during the bus transfer.</description>
100202 <description>An error occured during the bus transfer.</description>
100208 <description>Event not generated</description>
100213 <description>Event generated</description>
100224 … <description>Description collection: Pattern match is detected on the DMA data bus.</description>
100232 <description>Pattern match is detected on the DMA data bus.</description>
100238 <description>Event not generated</description>
100243 <description>Event generated</description>
100253 <description>Peripheral events.</description>
100259 <description>Generated after all MAXCNT bytes have been transferred</description>
100267 <description>Generated after all MAXCNT bytes have been transferred</description>
100273 <description>Event not generated</description>
100278 <description>Event generated</description>
100287 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
100295 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
100301 <description>Event not generated</description>
100306 <description>Event generated</description>
100315 <description>An error occured during the bus transfer.</description>
100323 <description>An error occured during the bus transfer.</description>
100329 <description>Event not generated</description>
100334 <description>Event generated</description>
100345 <description>Timed out due to bus being idle while receiving data.</description>
100353 <description>Timed out due to bus being idle while receiving data.</description>
100359 <description>Event not generated</description>
100364 <description>Event generated</description>
100373 <description>Publish configuration for event CTS</description>
100381 <description>DPPI channel that event CTS will publish to</description>
100392 <description>Disable publishing</description>
100397 <description>Enable publishing</description>
100406 <description>Publish configuration for event NCTS</description>
100414 <description>DPPI channel that event NCTS will publish to</description>
100425 <description>Disable publishing</description>
100430 <description>Enable publishing</description>
100439 <description>Publish configuration for event TXDRDY</description>
100447 <description>DPPI channel that event TXDRDY will publish to</description>
100458 <description>Disable publishing</description>
100463 <description>Enable publishing</description>
100472 <description>Publish configuration for event RXDRDY</description>
100480 <description>DPPI channel that event RXDRDY will publish to</description>
100491 <description>Disable publishing</description>
100496 <description>Enable publishing</description>
100505 <description>Publish configuration for event ERROR</description>
100513 <description>DPPI channel that event ERROR will publish to</description>
100524 <description>Disable publishing</description>
100529 <description>Enable publishing</description>
100538 <description>Publish configuration for event RXTO</description>
100546 <description>DPPI channel that event RXTO will publish to</description>
100557 <description>Disable publishing</description>
100562 <description>Enable publishing</description>
100571 <description>Publish configuration for event TXSTOPPED</description>
100579 <description>DPPI channel that event TXSTOPPED will publish to</description>
100590 <description>Disable publishing</description>
100595 <description>Enable publishing</description>
100604 <description>Publish configuration for events</description>
100610 <description>Publish configuration for events</description>
100616 <description>Publish configuration for event END</description>
100624 <description>DPPI channel that event END will publish to</description>
100635 <description>Disable publishing</description>
100640 <description>Enable publishing</description>
100649 <description>Publish configuration for event READY</description>
100657 <description>DPPI channel that event READY will publish to</description>
100668 <description>Disable publishing</description>
100673 <description>Enable publishing</description>
100682 <description>Publish configuration for event BUSERROR</description>
100690 <description>DPPI channel that event BUSERROR will publish to</description>
100701 <description>Disable publishing</description>
100706 <description>Enable publishing</description>
100717 … <description>Description collection: Publish configuration for event MATCH[n]</description>
100725 <description>DPPI channel that event MATCH[n] will publish to</description>
100736 <description>Disable publishing</description>
100741 <description>Enable publishing</description>
100751 <description>Publish configuration for events</description>
100757 <description>Publish configuration for event END</description>
100765 <description>DPPI channel that event END will publish to</description>
100776 <description>Disable publishing</description>
100781 <description>Enable publishing</description>
100790 <description>Publish configuration for event READY</description>
100798 <description>DPPI channel that event READY will publish to</description>
100809 <description>Disable publishing</description>
100814 <description>Enable publishing</description>
100823 <description>Publish configuration for event BUSERROR</description>
100831 <description>DPPI channel that event BUSERROR will publish to</description>
100842 <description>Disable publishing</description>
100847 <description>Enable publishing</description>
100858 <description>Publish configuration for event FRAMETIMEOUT</description>
100866 <description>DPPI channel that event FRAMETIMEOUT will publish to</description>
100877 <description>Disable publishing</description>
100882 <description>Enable publishing</description>
100891 <description>Shortcuts between local events and tasks</description>
100899 <description>Shortcut between event DMA.RX.END and task DMA.RX.START</description>
100905 <description>Disable shortcut</description>
100910 <description>Enable shortcut</description>
100917 <description>Shortcut between event DMA.RX.END and task DMA.RX.STOP</description>
100923 <description>Disable shortcut</description>
100928 <description>Enable shortcut</description>
100935 <description>Shortcut between event DMA.TX.END and task DMA.TX.STOP</description>
100941 <description>Disable shortcut</description>
100946 <description>Enable shortcut</description>
100953 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows daisy-ch…
100959 <description>Disable shortcut</description>
100964 <description>Enable shortcut</description>
100971 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows daisy-ch…
100977 <description>Disable shortcut</description>
100982 <description>Enable shortcut</description>
100989 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows daisy-ch…
100995 <description>Disable shortcut</description>
101000 <description>Enable shortcut</description>
101007 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows daisy-ch…
101013 <description>Disable shortcut</description>
101018 <description>Enable shortcut</description>
101025 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
101031 <description>Disable shortcut</description>
101036 <description>Enable shortcut</description>
101043 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
101049 <description>Disable shortcut</description>
101054 <description>Enable shortcut</description>
101061 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
101067 <description>Disable shortcut</description>
101072 <description>Enable shortcut</description>
101079 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
101085 <description>Disable shortcut</description>
101090 <description>Enable shortcut</description>
101097 <description>Shortcut between event FRAMETIMEOUT and task DMA.RX.STOP</description>
101103 <description>Disable shortcut</description>
101108 <description>Enable shortcut</description>
101117 <description>Enable or disable interrupt</description>
101125 <description>Enable or disable interrupt for event CTS</description>
101131 <description>Disable</description>
101136 <description>Enable</description>
101143 <description>Enable or disable interrupt for event NCTS</description>
101149 <description>Disable</description>
101154 <description>Enable</description>
101161 <description>Enable or disable interrupt for event TXDRDY</description>
101167 <description>Disable</description>
101172 <description>Enable</description>
101179 <description>Enable or disable interrupt for event RXDRDY</description>
101185 <description>Disable</description>
101190 <description>Enable</description>
101197 <description>Enable or disable interrupt for event ERROR</description>
101203 <description>Disable</description>
101208 <description>Enable</description>
101215 <description>Enable or disable interrupt for event RXTO</description>
101221 <description>Disable</description>
101226 <description>Enable</description>
101233 <description>Enable or disable interrupt for event TXSTOPPED</description>
101239 <description>Disable</description>
101244 <description>Enable</description>
101251 <description>Enable or disable interrupt for event DMARXEND</description>
101257 <description>Disable</description>
101262 <description>Enable</description>
101269 <description>Enable or disable interrupt for event DMARXREADY</description>
101275 <description>Disable</description>
101280 <description>Enable</description>
101287 <description>Enable or disable interrupt for event DMARXBUSERROR</description>
101293 <description>Disable</description>
101298 <description>Enable</description>
101305 <description>Enable or disable interrupt for event DMARXMATCH[0]</description>
101311 <description>Disable</description>
101316 <description>Enable</description>
101323 <description>Enable or disable interrupt for event DMARXMATCH[1]</description>
101329 <description>Disable</description>
101334 <description>Enable</description>
101341 <description>Enable or disable interrupt for event DMARXMATCH[2]</description>
101347 <description>Disable</description>
101352 <description>Enable</description>
101359 <description>Enable or disable interrupt for event DMARXMATCH[3]</description>
101365 <description>Disable</description>
101370 <description>Enable</description>
101377 <description>Enable or disable interrupt for event DMATXEND</description>
101383 <description>Disable</description>
101388 <description>Enable</description>
101395 <description>Enable or disable interrupt for event DMATXREADY</description>
101401 <description>Disable</description>
101406 <description>Enable</description>
101413 <description>Enable or disable interrupt for event DMATXBUSERROR</description>
101419 <description>Disable</description>
101424 <description>Enable</description>
101431 <description>Enable or disable interrupt for event FRAMETIMEOUT</description>
101437 <description>Disable</description>
101442 <description>Enable</description>
101451 <description>Enable interrupt</description>
101459 <description>Write '1' to enable interrupt for event CTS</description>
101466 <description>Read: Disabled</description>
101471 <description>Read: Enabled</description>
101479 <description>Enable</description>
101486 <description>Write '1' to enable interrupt for event NCTS</description>
101493 <description>Read: Disabled</description>
101498 <description>Read: Enabled</description>
101506 <description>Enable</description>
101513 <description>Write '1' to enable interrupt for event TXDRDY</description>
101520 <description>Read: Disabled</description>
101525 <description>Read: Enabled</description>
101533 <description>Enable</description>
101540 <description>Write '1' to enable interrupt for event RXDRDY</description>
101547 <description>Read: Disabled</description>
101552 <description>Read: Enabled</description>
101560 <description>Enable</description>
101567 <description>Write '1' to enable interrupt for event ERROR</description>
101574 <description>Read: Disabled</description>
101579 <description>Read: Enabled</description>
101587 <description>Enable</description>
101594 <description>Write '1' to enable interrupt for event RXTO</description>
101601 <description>Read: Disabled</description>
101606 <description>Read: Enabled</description>
101614 <description>Enable</description>
101621 <description>Write '1' to enable interrupt for event TXSTOPPED</description>
101628 <description>Read: Disabled</description>
101633 <description>Read: Enabled</description>
101641 <description>Enable</description>
101648 <description>Write '1' to enable interrupt for event DMARXEND</description>
101655 <description>Read: Disabled</description>
101660 <description>Read: Enabled</description>
101668 <description>Enable</description>
101675 <description>Write '1' to enable interrupt for event DMARXREADY</description>
101682 <description>Read: Disabled</description>
101687 <description>Read: Enabled</description>
101695 <description>Enable</description>
101702 <description>Write '1' to enable interrupt for event DMARXBUSERROR</description>
101709 <description>Read: Disabled</description>
101714 <description>Read: Enabled</description>
101722 <description>Enable</description>
101729 <description>Write '1' to enable interrupt for event DMARXMATCH[0]</description>
101736 <description>Read: Disabled</description>
101741 <description>Read: Enabled</description>
101749 <description>Enable</description>
101756 <description>Write '1' to enable interrupt for event DMARXMATCH[1]</description>
101763 <description>Read: Disabled</description>
101768 <description>Read: Enabled</description>
101776 <description>Enable</description>
101783 <description>Write '1' to enable interrupt for event DMARXMATCH[2]</description>
101790 <description>Read: Disabled</description>
101795 <description>Read: Enabled</description>
101803 <description>Enable</description>
101810 <description>Write '1' to enable interrupt for event DMARXMATCH[3]</description>
101817 <description>Read: Disabled</description>
101822 <description>Read: Enabled</description>
101830 <description>Enable</description>
101837 <description>Write '1' to enable interrupt for event DMATXEND</description>
101844 <description>Read: Disabled</description>
101849 <description>Read: Enabled</description>
101857 <description>Enable</description>
101864 <description>Write '1' to enable interrupt for event DMATXREADY</description>
101871 <description>Read: Disabled</description>
101876 <description>Read: Enabled</description>
101884 <description>Enable</description>
101891 <description>Write '1' to enable interrupt for event DMATXBUSERROR</description>
101898 <description>Read: Disabled</description>
101903 <description>Read: Enabled</description>
101911 <description>Enable</description>
101918 <description>Write '1' to enable interrupt for event FRAMETIMEOUT</description>
101925 <description>Read: Disabled</description>
101930 <description>Read: Enabled</description>
101938 <description>Enable</description>
101947 <description>Disable interrupt</description>
101955 <description>Write '1' to disable interrupt for event CTS</description>
101962 <description>Read: Disabled</description>
101967 <description>Read: Enabled</description>
101975 <description>Disable</description>
101982 <description>Write '1' to disable interrupt for event NCTS</description>
101989 <description>Read: Disabled</description>
101994 <description>Read: Enabled</description>
102002 <description>Disable</description>
102009 <description>Write '1' to disable interrupt for event TXDRDY</description>
102016 <description>Read: Disabled</description>
102021 <description>Read: Enabled</description>
102029 <description>Disable</description>
102036 <description>Write '1' to disable interrupt for event RXDRDY</description>
102043 <description>Read: Disabled</description>
102048 <description>Read: Enabled</description>
102056 <description>Disable</description>
102063 <description>Write '1' to disable interrupt for event ERROR</description>
102070 <description>Read: Disabled</description>
102075 <description>Read: Enabled</description>
102083 <description>Disable</description>
102090 <description>Write '1' to disable interrupt for event RXTO</description>
102097 <description>Read: Disabled</description>
102102 <description>Read: Enabled</description>
102110 <description>Disable</description>
102117 <description>Write '1' to disable interrupt for event TXSTOPPED</description>
102124 <description>Read: Disabled</description>
102129 <description>Read: Enabled</description>
102137 <description>Disable</description>
102144 <description>Write '1' to disable interrupt for event DMARXEND</description>
102151 <description>Read: Disabled</description>
102156 <description>Read: Enabled</description>
102164 <description>Disable</description>
102171 <description>Write '1' to disable interrupt for event DMARXREADY</description>
102178 <description>Read: Disabled</description>
102183 <description>Read: Enabled</description>
102191 <description>Disable</description>
102198 <description>Write '1' to disable interrupt for event DMARXBUSERROR</description>
102205 <description>Read: Disabled</description>
102210 <description>Read: Enabled</description>
102218 <description>Disable</description>
102225 <description>Write '1' to disable interrupt for event DMARXMATCH[0]</description>
102232 <description>Read: Disabled</description>
102237 <description>Read: Enabled</description>
102245 <description>Disable</description>
102252 <description>Write '1' to disable interrupt for event DMARXMATCH[1]</description>
102259 <description>Read: Disabled</description>
102264 <description>Read: Enabled</description>
102272 <description>Disable</description>
102279 <description>Write '1' to disable interrupt for event DMARXMATCH[2]</description>
102286 <description>Read: Disabled</description>
102291 <description>Read: Enabled</description>
102299 <description>Disable</description>
102306 <description>Write '1' to disable interrupt for event DMARXMATCH[3]</description>
102313 <description>Read: Disabled</description>
102318 <description>Read: Enabled</description>
102326 <description>Disable</description>
102333 <description>Write '1' to disable interrupt for event DMATXEND</description>
102340 <description>Read: Disabled</description>
102345 <description>Read: Enabled</description>
102353 <description>Disable</description>
102360 <description>Write '1' to disable interrupt for event DMATXREADY</description>
102367 <description>Read: Disabled</description>
102372 <description>Read: Enabled</description>
102380 <description>Disable</description>
102387 <description>Write '1' to disable interrupt for event DMATXBUSERROR</description>
102394 <description>Read: Disabled</description>
102399 <description>Read: Enabled</description>
102407 <description>Disable</description>
102414 <description>Write '1' to disable interrupt for event FRAMETIMEOUT</description>
102421 <description>Read: Disabled</description>
102426 <description>Read: Enabled</description>
102434 <description>Disable</description>
102443 <description>Error source</description>
102452 <description>Overrun error</description>
102459 <description>Read: error not present</description>
102464 <description>Read: error present</description>
102471 <description>Parity error</description>
102478 <description>Read: error not present</description>
102483 <description>Read: error present</description>
102490 <description>Framing error occurred</description>
102497 <description>Read: error not present</description>
102502 <description>Read: error present</description>
102509 <description>Break condition</description>
102516 <description>Read: error not present</description>
102521 <description>Read: error present</description>
102530 <description>Enable UART</description>
102538 <description>Enable or disable UARTE</description>
102544 <description>Disable UARTE</description>
102549 <description>Enable UARTE</description>
102558 <description>Baud rate. Accuracy depends on the HFCLK source selected.</description>
102566 <description>Baud rate</description>
102572 …<description>1200 baud (actual rate: 1205) when UARTE has 16 MHz peripheral clock frequency</descr…
102577 …<description>2400 baud (actual rate: 2396) when UARTE has 16 MHz peripheral clock frequency</descr…
102582 …<description>4800 baud (actual rate: 4808) when UARTE has 16 MHz peripheral clock frequency</descr…
102587 …<description>9600 baud (actual rate: 9598) when UARTE has 16 MHz peripheral clock frequency</descr…
102592 …<description>14400 baud (actual rate: 14401) when UARTE has 16 MHz peripheral clock frequency</des…
102597 …<description>19200 baud (actual rate: 19208) when UARTE has 16 MHz peripheral clock frequency</des…
102602 …<description>28800 baud (actual rate: 28777) when UARTE has 16 MHz peripheral clock frequency</des…
102607 … <description>31250 baud when UARTE has 16 MHz peripheral clock frequency</description>
102612 …<description>38400 baud (actual rate: 38369) when UARTE has 16 MHz peripheral clock frequency</des…
102617 …<description>56000 baud (actual rate: 55944) when UARTE has 16 MHz peripheral clock frequency</des…
102622 …<description>57600 baud (actual rate: 57554) when UARTE has 16 MHz peripheral clock frequency</des…
102627 …<description>76800 baud (actual rate: 76923) when UARTE has 16 MHz peripheral clock frequency</des…
102632 …<description>115200 baud (actual rate: 115108) when UARTE has 16 MHz peripheral clock frequency</d…
102637 …<description>230400 baud (actual rate: 231884) when UARTE has 16 MHz peripheral clock frequency</d…
102642 … <description>250000 baud when UARTE has 16 MHz peripheral clock frequency</description>
102647 …<description>460800 baud (actual rate: 457143) when UARTE has 16 MHz peripheral clock frequency</d…
102652 …<description>921600 baud (actual rate: 941176) when UARTE has 16 MHz peripheral clock frequency</d…
102657 … <description>1 megabaud when UARTE has 16 MHz peripheral clock frequency</description>
102666 …<description>Configuration of parity, hardware flow control, framesize, and packet timeout.</descr…
102674 <description>Hardware flow control</description>
102680 <description>Disabled</description>
102685 <description>Enabled</description>
102692 <description>Parity</description>
102698 <description>Exclude parity bit</description>
102703 <description>Include even parity bit</description>
102710 <description>Stop bits</description>
102716 <description>One stop bit</description>
102721 <description>Two stop bits</description>
102728 <description>Even or odd parity type</description>
102734 <description>Even parity</description>
102739 <description>Odd parity</description>
102746 <description>Set the data frame size</description>
102752 … <description>9 bit data frame size. 9th bit is treated as address bit.</description>
102757 <description>8 bit data frame size.</description>
102762 <description>7 bit data frame size.</description>
102767 <description>6 bit data frame size.</description>
102772 <description>5 bit data frame size.</description>
102777 <description>4 bit data frame size.</description>
102784 …<description>Select if data is trimmed from MSB or LSB end when the data frame size is less than 8…
102790 <description>Data is trimmed from MSB end.</description>
102795 <description>Data is trimmed from LSB end.</description>
102802 <description>Enable packet timeout.</description>
102808 <description>Packet timeout is disabled.</description>
102813 <description>Packet timeout is enabled.</description>
102818 <description>Packet timeout is disabled.</description>
102823 <description>Packet timeout is enabled.</description>
102832 … <description>Set the address of the UARTE for RX when used in 9 bit data frame mode.</description>
102840 <description>Set address</description>
102848 … <description>Set the number of UARTE bits to count before triggering packet timeout.</description>
102856 <description>Number of UARTE bits before timeout.</description>
102864 <description>Unspecified</description>
102870 <description>Pin select for TXD signal</description>
102878 <description>Pin number</description>
102884 <description>Port number</description>
102890 <description>Connection</description>
102896 <description>Disconnect</description>
102901 <description>Connect</description>
102910 <description>Pin select for CTS signal</description>
102918 <description>Pin number</description>
102924 <description>Port number</description>
102930 <description>Connection</description>
102936 <description>Disconnect</description>
102941 <description>Connect</description>
102950 <description>Pin select for RXD signal</description>
102958 <description>Pin number</description>
102964 <description>Port number</description>
102970 <description>Connection</description>
102976 <description>Disconnect</description>
102981 <description>Connect</description>
102990 <description>Pin select for RTS signal</description>
102998 <description>Pin number</description>
103004 <description>Port number</description>
103010 <description>Connection</description>
103016 <description>Disconnect</description>
103021 <description>Connect</description>
103031 <description>Unspecified</description>
103037 <description>Unspecified</description>
103043 <description>RAM buffer start address</description>
103051 …<description>RAM buffer start address for this EasyDMA channel. This address is a word aligned Dat…
103059 <description>Maximum number of bytes in channel buffer</description>
103067 <description>Maximum number of bytes in channel buffer</description>
103075 …<description>Number of bytes transferred in the last transaction, updated after the END event. Als…
103083 …<description>Number of bytes transferred in the last transaction. In case of NACK error, includes …
103091 <description>Number of bytes transferred in the current transaction</description>
103099 …<description>Number of bytes transferred in the current transaction. Continuously updated.</descri…
103107 <description>EasyDMA list type</description>
103115 <description>List type</description>
103121 <description>Disable EasyDMA list</description>
103126 <description>Use array list</description>
103135 <description>Terminate the transaction if a BUSERROR event is detected.</description>
103148 <description>Disable</description>
103153 <description>Enable</description>
103162 … <description>Address of transaction that generated the last BUSERROR event.</description>
103177 … <description>Registers to control the behavior of the pattern matcher engine</description>
103183 <description>Configure individual match events</description>
103191 <description>Enable match filter 0</description>
103197 <description>Match filter disabled</description>
103202 <description>Match filter enabled</description>
103209 <description>Enable match filter 1</description>
103215 <description>Match filter disabled</description>
103220 <description>Match filter enabled</description>
103227 <description>Enable match filter 2</description>
103233 <description>Match filter disabled</description>
103238 <description>Match filter enabled</description>
103245 <description>Enable match filter 3</description>
103251 <description>Match filter disabled</description>
103256 <description>Match filter enabled</description>
103263 <description>Configure match filter 0 as one-shot or continous</description>
103269 <description>Match filter stays enabled until disabled by task</description>
103274 … <description>Match filter stays enabled until next data word is received</description>
103281 <description>Configure match filter 1 as one-shot or continous</description>
103287 <description>Match filter stays enabled until disabled by task</description>
103292 … <description>Match filter stays enabled until next data word is received</description>
103299 <description>Configure match filter 2 as one-shot or continous</description>
103305 <description>Match filter stays enabled until disabled by task</description>
103310 … <description>Match filter stays enabled until next data word is received</description>
103317 <description>Configure match filter 3 as one-shot or continous</description>
103323 <description>Match filter stays enabled until disabled by task</description>
103328 … <description>Match filter stays enabled until next data word is received</description>
103339 …<description>Description collection: The data to look for - any match will trigger the MATCH[n] ev…
103347 <description>Data to look for</description>
103357 <description>Unspecified</description>
103363 <description>RAM buffer start address</description>
103371 …<description>RAM buffer start address for this EasyDMA channel. This address is a word aligned Dat…
103379 <description>Maximum number of bytes in channel buffer</description>
103387 <description>Maximum number of bytes in channel buffer</description>
103395 …<description>Number of bytes transferred in the last transaction, updated after the END event. Als…
103403 …<description>Number of bytes transferred in the last transaction. In case of NACK error, includes …
103411 <description>Number of bytes transferred in the current transaction</description>
103419 …<description>Number of bytes transferred in the current transaction. Continuously updated.</descri…
103427 <description>EasyDMA list type</description>
103435 <description>List type</description>
103441 <description>Disable EasyDMA list</description>
103446 <description>Use array list</description>
103455 <description>Terminate the transaction if a BUSERROR event is detected.</description>
103468 <description>Disable</description>
103473 <description>Enable</description>
103482 … <description>Address of transaction that generated the last BUSERROR event.</description>
103501 <description>Serial Peripheral Interface Master with EasyDMA 1</description>
103512 <description>VPR peripheral registers 1</description>
103523 <description>IPCT APB registers 1</description>
103535 <description>Distributed programmable peripheral interconnect controller 1</description>
103543 <description>MUTEX 1</description>
103550 <description>Real-time counter 0</description>
103569 <description>Start RTC counter</description>
103577 <description>Start RTC counter</description>
103583 <description>Trigger task</description>
103592 <description>Stop RTC counter</description>
103600 <description>Stop RTC counter</description>
103606 <description>Trigger task</description>
103615 <description>Clear RTC counter</description>
103623 <description>Clear RTC counter</description>
103629 <description>Trigger task</description>
103638 <description>Set counter to: maximum value - 0xF</description>
103646 <description>Set counter to: maximum value - 0xF</description>
103652 <description>Trigger task</description>
103663 <description>Description collection: Capture RTC counter to CC[n] register</description>
103671 <description>Capture RTC counter to CC[n] register</description>
103677 <description>Trigger task</description>
103686 <description>Subscribe configuration for task START</description>
103694 <description>DPPI channel that task START will subscribe to</description>
103705 <description>Disable subscription</description>
103710 <description>Enable subscription</description>
103719 <description>Subscribe configuration for task STOP</description>
103727 <description>DPPI channel that task STOP will subscribe to</description>
103738 <description>Disable subscription</description>
103743 <description>Enable subscription</description>
103752 <description>Subscribe configuration for task CLEAR</description>
103760 <description>DPPI channel that task CLEAR will subscribe to</description>
103771 <description>Disable subscription</description>
103776 <description>Enable subscription</description>
103785 <description>Subscribe configuration for task TRIGOVRFLW</description>
103793 <description>DPPI channel that task TRIGOVRFLW will subscribe to</description>
103804 <description>Disable subscription</description>
103809 <description>Enable subscription</description>
103820 … <description>Description collection: Subscribe configuration for task CAPTURE[n]</description>
103828 <description>DPPI channel that task CAPTURE[n] will subscribe to</description>
103839 <description>Disable subscription</description>
103844 <description>Enable subscription</description>
103853 <description>Event on counter increment</description>
103861 <description>Event on counter increment</description>
103867 <description>Event not generated</description>
103872 <description>Event generated</description>
103881 <description>Event on counter overflow</description>
103889 <description>Event on counter overflow</description>
103895 <description>Event not generated</description>
103900 <description>Event generated</description>
103911 <description>Description collection: Compare event on CC[n] match</description>
103919 <description>Compare event on CC[n] match</description>
103925 <description>Event not generated</description>
103930 <description>Event generated</description>
103939 <description>Publish configuration for event TICK</description>
103947 <description>DPPI channel that event TICK will publish to</description>
103958 <description>Disable publishing</description>
103963 <description>Enable publishing</description>
103972 <description>Publish configuration for event OVRFLW</description>
103980 <description>DPPI channel that event OVRFLW will publish to</description>
103991 <description>Disable publishing</description>
103996 <description>Enable publishing</description>
104007 … <description>Description collection: Publish configuration for event COMPARE[n]</description>
104015 <description>DPPI channel that event COMPARE[n] will publish to</description>
104026 <description>Disable publishing</description>
104031 <description>Enable publishing</description>
104040 <description>Shortcuts between local events and tasks</description>
104048 <description>Shortcut between event COMPARE[0] and task CLEAR</description>
104054 <description>Disable shortcut</description>
104059 <description>Enable shortcut</description>
104066 <description>Shortcut between event COMPARE[1] and task CLEAR</description>
104072 <description>Disable shortcut</description>
104077 <description>Enable shortcut</description>
104084 <description>Shortcut between event COMPARE[2] and task CLEAR</description>
104090 <description>Disable shortcut</description>
104095 <description>Enable shortcut</description>
104102 <description>Shortcut between event COMPARE[3] and task CLEAR</description>
104108 <description>Disable shortcut</description>
104113 <description>Enable shortcut</description>
104120 <description>Shortcut between event COMPARE[4] and task CLEAR</description>
104126 <description>Disable shortcut</description>
104131 <description>Enable shortcut</description>
104138 <description>Shortcut between event COMPARE[5] and task CLEAR</description>
104144 <description>Disable shortcut</description>
104149 <description>Enable shortcut</description>
104156 <description>Shortcut between event COMPARE[6] and task CLEAR</description>
104162 <description>Disable shortcut</description>
104167 <description>Enable shortcut</description>
104174 <description>Shortcut between event COMPARE[7] and task CLEAR</description>
104180 <description>Disable shortcut</description>
104185 <description>Enable shortcut</description>
104194 <description>Enable interrupt</description>
104202 <description>Write '1' to enable interrupt for event TICK</description>
104209 <description>Read: Disabled</description>
104214 <description>Read: Enabled</description>
104222 <description>Enable</description>
104229 <description>Write '1' to enable interrupt for event OVRFLW</description>
104236 <description>Read: Disabled</description>
104241 <description>Read: Enabled</description>
104249 <description>Enable</description>
104256 <description>Write '1' to enable interrupt for event COMPARE[0]</description>
104263 <description>Read: Disabled</description>
104268 <description>Read: Enabled</description>
104276 <description>Enable</description>
104283 <description>Write '1' to enable interrupt for event COMPARE[1]</description>
104290 <description>Read: Disabled</description>
104295 <description>Read: Enabled</description>
104303 <description>Enable</description>
104310 <description>Write '1' to enable interrupt for event COMPARE[2]</description>
104317 <description>Read: Disabled</description>
104322 <description>Read: Enabled</description>
104330 <description>Enable</description>
104337 <description>Write '1' to enable interrupt for event COMPARE[3]</description>
104344 <description>Read: Disabled</description>
104349 <description>Read: Enabled</description>
104357 <description>Enable</description>
104364 <description>Write '1' to enable interrupt for event COMPARE[4]</description>
104371 <description>Read: Disabled</description>
104376 <description>Read: Enabled</description>
104384 <description>Enable</description>
104391 <description>Write '1' to enable interrupt for event COMPARE[5]</description>
104398 <description>Read: Disabled</description>
104403 <description>Read: Enabled</description>
104411 <description>Enable</description>
104418 <description>Write '1' to enable interrupt for event COMPARE[6]</description>
104425 <description>Read: Disabled</description>
104430 <description>Read: Enabled</description>
104438 <description>Enable</description>
104445 <description>Write '1' to enable interrupt for event COMPARE[7]</description>
104452 <description>Read: Disabled</description>
104457 <description>Read: Enabled</description>
104465 <description>Enable</description>
104474 <description>Disable interrupt</description>
104482 <description>Write '1' to disable interrupt for event TICK</description>
104489 <description>Read: Disabled</description>
104494 <description>Read: Enabled</description>
104502 <description>Disable</description>
104509 <description>Write '1' to disable interrupt for event OVRFLW</description>
104516 <description>Read: Disabled</description>
104521 <description>Read: Enabled</description>
104529 <description>Disable</description>
104536 <description>Write '1' to disable interrupt for event COMPARE[0]</description>
104543 <description>Read: Disabled</description>
104548 <description>Read: Enabled</description>
104556 <description>Disable</description>
104563 <description>Write '1' to disable interrupt for event COMPARE[1]</description>
104570 <description>Read: Disabled</description>
104575 <description>Read: Enabled</description>
104583 <description>Disable</description>
104590 <description>Write '1' to disable interrupt for event COMPARE[2]</description>
104597 <description>Read: Disabled</description>
104602 <description>Read: Enabled</description>
104610 <description>Disable</description>
104617 <description>Write '1' to disable interrupt for event COMPARE[3]</description>
104624 <description>Read: Disabled</description>
104629 <description>Read: Enabled</description>
104637 <description>Disable</description>
104644 <description>Write '1' to disable interrupt for event COMPARE[4]</description>
104651 <description>Read: Disabled</description>
104656 <description>Read: Enabled</description>
104664 <description>Disable</description>
104671 <description>Write '1' to disable interrupt for event COMPARE[5]</description>
104678 <description>Read: Disabled</description>
104683 <description>Read: Enabled</description>
104691 <description>Disable</description>
104698 <description>Write '1' to disable interrupt for event COMPARE[6]</description>
104705 <description>Read: Disabled</description>
104710 <description>Read: Enabled</description>
104718 <description>Disable</description>
104725 <description>Write '1' to disable interrupt for event COMPARE[7]</description>
104732 <description>Read: Disabled</description>
104737 <description>Read: Enabled</description>
104745 <description>Disable</description>
104754 <description>Enable or disable event routing</description>
104762 <description>Enable or disable event routing for event TICK</description>
104768 <description>Disable</description>
104773 <description>Enable</description>
104780 <description>Enable or disable event routing for event OVRFLW</description>
104786 <description>Disable</description>
104791 <description>Enable</description>
104798 <description>Enable or disable event routing for event COMPARE[0]</description>
104804 <description>Disable</description>
104809 <description>Enable</description>
104816 <description>Enable or disable event routing for event COMPARE[1]</description>
104822 <description>Disable</description>
104827 <description>Enable</description>
104834 <description>Enable or disable event routing for event COMPARE[2]</description>
104840 <description>Disable</description>
104845 <description>Enable</description>
104852 <description>Enable or disable event routing for event COMPARE[3]</description>
104858 <description>Disable</description>
104863 <description>Enable</description>
104870 <description>Enable or disable event routing for event COMPARE[4]</description>
104876 <description>Disable</description>
104881 <description>Enable</description>
104888 <description>Enable or disable event routing for event COMPARE[5]</description>
104894 <description>Disable</description>
104899 <description>Enable</description>
104906 <description>Enable or disable event routing for event COMPARE[6]</description>
104912 <description>Disable</description>
104917 <description>Enable</description>
104924 <description>Enable or disable event routing for event COMPARE[7]</description>
104930 <description>Disable</description>
104935 <description>Enable</description>
104944 <description>Enable event routing</description>
104952 <description>Write '1' to enable event routing for event TICK</description>
104959 <description>Read: Disabled</description>
104964 <description>Read: Enabled</description>
104972 <description>Enable</description>
104979 <description>Write '1' to enable event routing for event OVRFLW</description>
104986 <description>Read: Disabled</description>
104991 <description>Read: Enabled</description>
104999 <description>Enable</description>
105006 <description>Write '1' to enable event routing for event COMPARE[0]</description>
105013 <description>Read: Disabled</description>
105018 <description>Read: Enabled</description>
105026 <description>Enable</description>
105033 <description>Write '1' to enable event routing for event COMPARE[1]</description>
105040 <description>Read: Disabled</description>
105045 <description>Read: Enabled</description>
105053 <description>Enable</description>
105060 <description>Write '1' to enable event routing for event COMPARE[2]</description>
105067 <description>Read: Disabled</description>
105072 <description>Read: Enabled</description>
105080 <description>Enable</description>
105087 <description>Write '1' to enable event routing for event COMPARE[3]</description>
105094 <description>Read: Disabled</description>
105099 <description>Read: Enabled</description>
105107 <description>Enable</description>
105114 <description>Write '1' to enable event routing for event COMPARE[4]</description>
105121 <description>Read: Disabled</description>
105126 <description>Read: Enabled</description>
105134 <description>Enable</description>
105141 <description>Write '1' to enable event routing for event COMPARE[5]</description>
105148 <description>Read: Disabled</description>
105153 <description>Read: Enabled</description>
105161 <description>Enable</description>
105168 <description>Write '1' to enable event routing for event COMPARE[6]</description>
105175 <description>Read: Disabled</description>
105180 <description>Read: Enabled</description>
105188 <description>Enable</description>
105195 <description>Write '1' to enable event routing for event COMPARE[7]</description>
105202 <description>Read: Disabled</description>
105207 <description>Read: Enabled</description>
105215 <description>Enable</description>
105224 <description>Disable event routing</description>
105232 <description>Write '1' to disable event routing for event TICK</description>
105239 <description>Read: Disabled</description>
105244 <description>Read: Enabled</description>
105252 <description>Disable</description>
105259 <description>Write '1' to disable event routing for event OVRFLW</description>
105266 <description>Read: Disabled</description>
105271 <description>Read: Enabled</description>
105279 <description>Disable</description>
105286 <description>Write '1' to disable event routing for event COMPARE[0]</description>
105293 <description>Read: Disabled</description>
105298 <description>Read: Enabled</description>
105306 <description>Disable</description>
105313 <description>Write '1' to disable event routing for event COMPARE[1]</description>
105320 <description>Read: Disabled</description>
105325 <description>Read: Enabled</description>
105333 <description>Disable</description>
105340 <description>Write '1' to disable event routing for event COMPARE[2]</description>
105347 <description>Read: Disabled</description>
105352 <description>Read: Enabled</description>
105360 <description>Disable</description>
105367 <description>Write '1' to disable event routing for event COMPARE[3]</description>
105374 <description>Read: Disabled</description>
105379 <description>Read: Enabled</description>
105387 <description>Disable</description>
105394 <description>Write '1' to disable event routing for event COMPARE[4]</description>
105401 <description>Read: Disabled</description>
105406 <description>Read: Enabled</description>
105414 <description>Disable</description>
105421 <description>Write '1' to disable event routing for event COMPARE[5]</description>
105428 <description>Read: Disabled</description>
105433 <description>Read: Enabled</description>
105441 <description>Disable</description>
105448 <description>Write '1' to disable event routing for event COMPARE[6]</description>
105455 <description>Read: Disabled</description>
105460 <description>Read: Enabled</description>
105468 <description>Disable</description>
105475 <description>Write '1' to disable event routing for event COMPARE[7]</description>
105482 <description>Read: Disabled</description>
105487 <description>Read: Enabled</description>
105495 <description>Disable</description>
105504 <description>Current counter value</description>
105512 <description>Counter value</description>
105520 …<description>12-bit prescaler for counter frequency (32768 / (PRESCALER + 1)). Must be written whe…
105528 <description>Prescaler value</description>
105538 <description>Description collection: Compare register n</description>
105546 <description>Compare value</description>
105556 <description>Real-time counter 1</description>
105567 <description>Watchdog Timer 0</description>
105586 <description>Start WDT</description>
105594 <description>Start WDT</description>
105600 <description>Trigger task</description>
105609 <description>Stop WDT</description>
105617 <description>Stop WDT</description>
105623 <description>Trigger task</description>
105632 <description>Subscribe configuration for task START</description>
105640 <description>DPPI channel that task START will subscribe to</description>
105651 <description>Disable subscription</description>
105656 <description>Enable subscription</description>
105665 <description>Subscribe configuration for task STOP</description>
105673 <description>DPPI channel that task STOP will subscribe to</description>
105684 <description>Disable subscription</description>
105689 <description>Enable subscription</description>
105698 <description>Watchdog timeout</description>
105706 <description>Watchdog timeout</description>
105712 <description>Event not generated</description>
105717 <description>Event generated</description>
105726 <description>Watchdog stopped</description>
105734 <description>Watchdog stopped</description>
105740 <description>Event not generated</description>
105745 <description>Event generated</description>
105754 <description>Publish configuration for event TIMEOUT</description>
105762 <description>DPPI channel that event TIMEOUT will publish to</description>
105773 <description>Disable publishing</description>
105778 <description>Enable publishing</description>
105787 <description>Publish configuration for event STOPPED</description>
105795 <description>DPPI channel that event STOPPED will publish to</description>
105806 <description>Disable publishing</description>
105811 <description>Enable publishing</description>
105820 <description>Enable or disable interrupt</description>
105828 <description>Enable or disable interrupt for event TIMEOUT</description>
105834 <description>Disable</description>
105839 <description>Enable</description>
105846 <description>Enable or disable interrupt for event STOPPED</description>
105852 <description>Disable</description>
105857 <description>Enable</description>
105866 <description>Enable interrupt</description>
105874 <description>Write '1' to enable interrupt for event TIMEOUT</description>
105881 <description>Read: Disabled</description>
105886 <description>Read: Enabled</description>
105894 <description>Enable</description>
105901 <description>Write '1' to enable interrupt for event STOPPED</description>
105908 <description>Read: Disabled</description>
105913 <description>Read: Enabled</description>
105921 <description>Enable</description>
105930 <description>Disable interrupt</description>
105938 <description>Write '1' to disable interrupt for event TIMEOUT</description>
105945 <description>Read: Disabled</description>
105950 <description>Read: Enabled</description>
105958 <description>Disable</description>
105965 <description>Write '1' to disable interrupt for event STOPPED</description>
105972 <description>Read: Disabled</description>
105977 <description>Read: Enabled</description>
105985 <description>Disable</description>
105994 <description>Enable or disable interrupt</description>
106002 <description>Enable or disable interrupt for event TIMEOUT</description>
106008 <description>Disable</description>
106013 <description>Enable</description>
106020 <description>Enable or disable interrupt for event STOPPED</description>
106026 <description>Disable</description>
106031 <description>Enable</description>
106040 <description>Enable interrupt</description>
106048 <description>Write '1' to enable interrupt for event TIMEOUT</description>
106055 <description>Read: Disabled</description>
106060 <description>Read: Enabled</description>
106068 <description>Enable</description>
106075 <description>Write '1' to enable interrupt for event STOPPED</description>
106082 <description>Read: Disabled</description>
106087 <description>Read: Enabled</description>
106095 <description>Enable</description>
106104 <description>Disable interrupt</description>
106112 <description>Write '1' to disable interrupt for event TIMEOUT</description>
106119 <description>Read: Disabled</description>
106124 <description>Read: Enabled</description>
106132 <description>Disable</description>
106139 <description>Write '1' to disable interrupt for event STOPPED</description>
106146 <description>Read: Disabled</description>
106151 <description>Read: Enabled</description>
106159 <description>Disable</description>
106168 <description>Run status</description>
106176 <description>Indicates whether or not WDT is running</description>
106182 <description>Watchdog is not running</description>
106187 <description>Watchdog is running</description>
106196 <description>Request status</description>
106204 <description>Request status for RR[0] register</description>
106210 … <description>RR[0] register is not enabled, or are already requesting reload</description>
106215 … <description>RR[0] register is enabled, and are not yet requesting reload</description>
106222 <description>Request status for RR[1] register</description>
106228 … <description>RR[1] register is not enabled, or are already requesting reload</description>
106233 … <description>RR[1] register is enabled, and are not yet requesting reload</description>
106240 <description>Request status for RR[2] register</description>
106246 … <description>RR[2] register is not enabled, or are already requesting reload</description>
106251 … <description>RR[2] register is enabled, and are not yet requesting reload</description>
106258 <description>Request status for RR[3] register</description>
106264 … <description>RR[3] register is not enabled, or are already requesting reload</description>
106269 … <description>RR[3] register is enabled, and are not yet requesting reload</description>
106276 <description>Request status for RR[4] register</description>
106282 … <description>RR[4] register is not enabled, or are already requesting reload</description>
106287 … <description>RR[4] register is enabled, and are not yet requesting reload</description>
106294 <description>Request status for RR[5] register</description>
106300 … <description>RR[5] register is not enabled, or are already requesting reload</description>
106305 … <description>RR[5] register is enabled, and are not yet requesting reload</description>
106312 <description>Request status for RR[6] register</description>
106318 … <description>RR[6] register is not enabled, or are already requesting reload</description>
106323 … <description>RR[6] register is enabled, and are not yet requesting reload</description>
106330 <description>Request status for RR[7] register</description>
106336 … <description>RR[7] register is not enabled, or are already requesting reload</description>
106341 … <description>RR[7] register is enabled, and are not yet requesting reload</description>
106350 <description>Counter reload value</description>
106358 … <description>Counter reload value in number of cycles of the 32.768 kHz clock</description>
106366 <description>Enable register for reload request registers</description>
106374 <description>Enable or disable RR[0] register</description>
106380 <description>Disable RR[0] register</description>
106385 <description>Enable RR[0] register</description>
106392 <description>Enable or disable RR[1] register</description>
106398 <description>Disable RR[1] register</description>
106403 <description>Enable RR[1] register</description>
106410 <description>Enable or disable RR[2] register</description>
106416 <description>Disable RR[2] register</description>
106421 <description>Enable RR[2] register</description>
106428 <description>Enable or disable RR[3] register</description>
106434 <description>Disable RR[3] register</description>
106439 <description>Enable RR[3] register</description>
106446 <description>Enable or disable RR[4] register</description>
106452 <description>Disable RR[4] register</description>
106457 <description>Enable RR[4] register</description>
106464 <description>Enable or disable RR[5] register</description>
106470 <description>Disable RR[5] register</description>
106475 <description>Enable RR[5] register</description>
106482 <description>Enable or disable RR[6] register</description>
106488 <description>Disable RR[6] register</description>
106493 <description>Enable RR[6] register</description>
106500 <description>Enable or disable RR[7] register</description>
106506 <description>Disable RR[7] register</description>
106511 <description>Enable RR[7] register</description>
106520 <description>Configuration register</description>
106528 …<description>Configure WDT to either be paused, or kept running, while the CPU is sleeping</descri…
106534 <description>Pause WDT while the CPU is sleeping</description>
106539 <description>Keep WDT running while the CPU is sleeping</description>
106546 …<description>Configure WDT to either be paused, or kept running, while the CPU is halted by the de…
106552 <description>Pause WDT while the CPU is halted by the debugger</description>
106557 … <description>Keep WDT running while the CPU is halted by the debugger</description>
106564 <description>Allow stopping WDT</description>
106570 <description>Do not allow stopping WDT</description>
106575 <description>Allow stopping WDT</description>
106584 <description>Task stop enable</description>
106592 <description>Allow stopping WDT</description>
106598 <description>Value to allow stopping WDT</description>
106609 <description>Description collection: Reload request n</description>
106617 <description>Reload request register</description>
106623 <description>Value to request a reload of the watchdog timer</description>
106634 <description>Watchdog Timer 1</description>
106645 <description>Event generator unit</description>
106666 …<description>Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event…
106674 … <description>Trigger n for triggering the corresponding TRIGGERED[n] event</description>
106680 <description>Trigger task</description>
106691 … <description>Description collection: Subscribe configuration for task TRIGGER[n]</description>
106699 <description>DPPI channel that task TRIGGER[n] will subscribe to</description>
106710 <description>Disable subscription</description>
106715 <description>Enable subscription</description>
106726 …<description>Description collection: Event number n generated by triggering the corresponding TRIG…
106734 …<description>Event number n generated by triggering the corresponding TRIGGER[n] task</description>
106740 <description>Event not generated</description>
106745 <description>Event generated</description>
106756 … <description>Description collection: Publish configuration for event TRIGGERED[n]</description>
106764 <description>DPPI channel that event TRIGGERED[n] will publish to</description>
106775 <description>Disable publishing</description>
106780 <description>Enable publishing</description>
106789 <description>Enable or disable interrupt</description>
106797 <description>Enable or disable interrupt for event TRIGGERED[0]</description>
106803 <description>Disable</description>
106808 <description>Enable</description>
106815 <description>Enable or disable interrupt for event TRIGGERED[1]</description>
106821 <description>Disable</description>
106826 <description>Enable</description>
106833 <description>Enable or disable interrupt for event TRIGGERED[2]</description>
106839 <description>Disable</description>
106844 <description>Enable</description>
106851 <description>Enable or disable interrupt for event TRIGGERED[3]</description>
106857 <description>Disable</description>
106862 <description>Enable</description>
106869 <description>Enable or disable interrupt for event TRIGGERED[4]</description>
106875 <description>Disable</description>
106880 <description>Enable</description>
106887 <description>Enable or disable interrupt for event TRIGGERED[5]</description>
106893 <description>Disable</description>
106898 <description>Enable</description>
106905 <description>Enable or disable interrupt for event TRIGGERED[6]</description>
106911 <description>Disable</description>
106916 <description>Enable</description>
106923 <description>Enable or disable interrupt for event TRIGGERED[7]</description>
106929 <description>Disable</description>
106934 <description>Enable</description>
106941 <description>Enable or disable interrupt for event TRIGGERED[8]</description>
106947 <description>Disable</description>
106952 <description>Enable</description>
106959 <description>Enable or disable interrupt for event TRIGGERED[9]</description>
106965 <description>Disable</description>
106970 <description>Enable</description>
106977 <description>Enable or disable interrupt for event TRIGGERED[10]</description>
106983 <description>Disable</description>
106988 <description>Enable</description>
106995 <description>Enable or disable interrupt for event TRIGGERED[11]</description>
107001 <description>Disable</description>
107006 <description>Enable</description>
107013 <description>Enable or disable interrupt for event TRIGGERED[12]</description>
107019 <description>Disable</description>
107024 <description>Enable</description>
107031 <description>Enable or disable interrupt for event TRIGGERED[13]</description>
107037 <description>Disable</description>
107042 <description>Enable</description>
107049 <description>Enable or disable interrupt for event TRIGGERED[14]</description>
107055 <description>Disable</description>
107060 <description>Enable</description>
107067 <description>Enable or disable interrupt for event TRIGGERED[15]</description>
107073 <description>Disable</description>
107078 <description>Enable</description>
107087 <description>Enable interrupt</description>
107095 <description>Write '1' to enable interrupt for event TRIGGERED[0]</description>
107102 <description>Read: Disabled</description>
107107 <description>Read: Enabled</description>
107115 <description>Enable</description>
107122 <description>Write '1' to enable interrupt for event TRIGGERED[1]</description>
107129 <description>Read: Disabled</description>
107134 <description>Read: Enabled</description>
107142 <description>Enable</description>
107149 <description>Write '1' to enable interrupt for event TRIGGERED[2]</description>
107156 <description>Read: Disabled</description>
107161 <description>Read: Enabled</description>
107169 <description>Enable</description>
107176 <description>Write '1' to enable interrupt for event TRIGGERED[3]</description>
107183 <description>Read: Disabled</description>
107188 <description>Read: Enabled</description>
107196 <description>Enable</description>
107203 <description>Write '1' to enable interrupt for event TRIGGERED[4]</description>
107210 <description>Read: Disabled</description>
107215 <description>Read: Enabled</description>
107223 <description>Enable</description>
107230 <description>Write '1' to enable interrupt for event TRIGGERED[5]</description>
107237 <description>Read: Disabled</description>
107242 <description>Read: Enabled</description>
107250 <description>Enable</description>
107257 <description>Write '1' to enable interrupt for event TRIGGERED[6]</description>
107264 <description>Read: Disabled</description>
107269 <description>Read: Enabled</description>
107277 <description>Enable</description>
107284 <description>Write '1' to enable interrupt for event TRIGGERED[7]</description>
107291 <description>Read: Disabled</description>
107296 <description>Read: Enabled</description>
107304 <description>Enable</description>
107311 <description>Write '1' to enable interrupt for event TRIGGERED[8]</description>
107318 <description>Read: Disabled</description>
107323 <description>Read: Enabled</description>
107331 <description>Enable</description>
107338 <description>Write '1' to enable interrupt for event TRIGGERED[9]</description>
107345 <description>Read: Disabled</description>
107350 <description>Read: Enabled</description>
107358 <description>Enable</description>
107365 <description>Write '1' to enable interrupt for event TRIGGERED[10]</description>
107372 <description>Read: Disabled</description>
107377 <description>Read: Enabled</description>
107385 <description>Enable</description>
107392 <description>Write '1' to enable interrupt for event TRIGGERED[11]</description>
107399 <description>Read: Disabled</description>
107404 <description>Read: Enabled</description>
107412 <description>Enable</description>
107419 <description>Write '1' to enable interrupt for event TRIGGERED[12]</description>
107426 <description>Read: Disabled</description>
107431 <description>Read: Enabled</description>
107439 <description>Enable</description>
107446 <description>Write '1' to enable interrupt for event TRIGGERED[13]</description>
107453 <description>Read: Disabled</description>
107458 <description>Read: Enabled</description>
107466 <description>Enable</description>
107473 <description>Write '1' to enable interrupt for event TRIGGERED[14]</description>
107480 <description>Read: Disabled</description>
107485 <description>Read: Enabled</description>
107493 <description>Enable</description>
107500 <description>Write '1' to enable interrupt for event TRIGGERED[15]</description>
107507 <description>Read: Disabled</description>
107512 <description>Read: Enabled</description>
107520 <description>Enable</description>
107529 <description>Disable interrupt</description>
107537 <description>Write '1' to disable interrupt for event TRIGGERED[0]</description>
107544 <description>Read: Disabled</description>
107549 <description>Read: Enabled</description>
107557 <description>Disable</description>
107564 <description>Write '1' to disable interrupt for event TRIGGERED[1]</description>
107571 <description>Read: Disabled</description>
107576 <description>Read: Enabled</description>
107584 <description>Disable</description>
107591 <description>Write '1' to disable interrupt for event TRIGGERED[2]</description>
107598 <description>Read: Disabled</description>
107603 <description>Read: Enabled</description>
107611 <description>Disable</description>
107618 <description>Write '1' to disable interrupt for event TRIGGERED[3]</description>
107625 <description>Read: Disabled</description>
107630 <description>Read: Enabled</description>
107638 <description>Disable</description>
107645 <description>Write '1' to disable interrupt for event TRIGGERED[4]</description>
107652 <description>Read: Disabled</description>
107657 <description>Read: Enabled</description>
107665 <description>Disable</description>
107672 <description>Write '1' to disable interrupt for event TRIGGERED[5]</description>
107679 <description>Read: Disabled</description>
107684 <description>Read: Enabled</description>
107692 <description>Disable</description>
107699 <description>Write '1' to disable interrupt for event TRIGGERED[6]</description>
107706 <description>Read: Disabled</description>
107711 <description>Read: Enabled</description>
107719 <description>Disable</description>
107726 <description>Write '1' to disable interrupt for event TRIGGERED[7]</description>
107733 <description>Read: Disabled</description>
107738 <description>Read: Enabled</description>
107746 <description>Disable</description>
107753 <description>Write '1' to disable interrupt for event TRIGGERED[8]</description>
107760 <description>Read: Disabled</description>
107765 <description>Read: Enabled</description>
107773 <description>Disable</description>
107780 <description>Write '1' to disable interrupt for event TRIGGERED[9]</description>
107787 <description>Read: Disabled</description>
107792 <description>Read: Enabled</description>
107800 <description>Disable</description>
107807 <description>Write '1' to disable interrupt for event TRIGGERED[10]</description>
107814 <description>Read: Disabled</description>
107819 <description>Read: Enabled</description>
107827 <description>Disable</description>
107834 <description>Write '1' to disable interrupt for event TRIGGERED[11]</description>
107841 <description>Read: Disabled</description>
107846 <description>Read: Enabled</description>
107854 <description>Disable</description>
107861 <description>Write '1' to disable interrupt for event TRIGGERED[12]</description>
107868 <description>Read: Disabled</description>
107873 <description>Read: Enabled</description>
107881 <description>Disable</description>
107888 <description>Write '1' to disable interrupt for event TRIGGERED[13]</description>
107895 <description>Read: Disabled</description>
107900 <description>Read: Enabled</description>
107908 <description>Disable</description>
107915 <description>Write '1' to disable interrupt for event TRIGGERED[14]</description>
107922 <description>Read: Disabled</description>
107927 <description>Read: Enabled</description>
107935 <description>Disable</description>
107942 <description>Write '1' to disable interrupt for event TRIGGERED[15]</description>
107949 <description>Read: Disabled</description>
107954 <description>Read: Enabled</description>
107962 <description>Disable</description>
107971 <description>Pending interrupts</description>
107979 <description>Read pending status of interrupt for event TRIGGERED[0]</description>
107986 <description>Read: Not pending</description>
107991 <description>Read: Pending</description>
107998 <description>Read pending status of interrupt for event TRIGGERED[1]</description>
108005 <description>Read: Not pending</description>
108010 <description>Read: Pending</description>
108017 <description>Read pending status of interrupt for event TRIGGERED[2]</description>
108024 <description>Read: Not pending</description>
108029 <description>Read: Pending</description>
108036 <description>Read pending status of interrupt for event TRIGGERED[3]</description>
108043 <description>Read: Not pending</description>
108048 <description>Read: Pending</description>
108055 <description>Read pending status of interrupt for event TRIGGERED[4]</description>
108062 <description>Read: Not pending</description>
108067 <description>Read: Pending</description>
108074 <description>Read pending status of interrupt for event TRIGGERED[5]</description>
108081 <description>Read: Not pending</description>
108086 <description>Read: Pending</description>
108093 <description>Read pending status of interrupt for event TRIGGERED[6]</description>
108100 <description>Read: Not pending</description>
108105 <description>Read: Pending</description>
108112 <description>Read pending status of interrupt for event TRIGGERED[7]</description>
108119 <description>Read: Not pending</description>
108124 <description>Read: Pending</description>
108131 <description>Read pending status of interrupt for event TRIGGERED[8]</description>
108138 <description>Read: Not pending</description>
108143 <description>Read: Pending</description>
108150 <description>Read pending status of interrupt for event TRIGGERED[9]</description>
108157 <description>Read: Not pending</description>
108162 <description>Read: Pending</description>
108169 <description>Read pending status of interrupt for event TRIGGERED[10]</description>
108176 <description>Read: Not pending</description>
108181 <description>Read: Pending</description>
108188 <description>Read pending status of interrupt for event TRIGGERED[11]</description>
108195 <description>Read: Not pending</description>
108200 <description>Read: Pending</description>
108207 <description>Read pending status of interrupt for event TRIGGERED[12]</description>
108214 <description>Read: Not pending</description>
108219 <description>Read: Pending</description>
108226 <description>Read pending status of interrupt for event TRIGGERED[13]</description>
108233 <description>Read: Not pending</description>
108238 <description>Read: Pending</description>
108245 <description>Read pending status of interrupt for event TRIGGERED[14]</description>
108252 <description>Read: Not pending</description>
108257 <description>Read: Pending</description>
108264 <description>Read pending status of interrupt for event TRIGGERED[15]</description>
108271 <description>Read: Not pending</description>
108276 <description>Read: Pending</description>
108287 <description>GPIO Port 0</description>
108303 <description>Write GPIO port</description>
108311 <description>Pin 0</description>
108317 <description>Pin driver is low</description>
108322 <description>Pin driver is high</description>
108329 <description>Pin 1</description>
108335 <description>Pin driver is low</description>
108340 <description>Pin driver is high</description>
108347 <description>Pin 2</description>
108353 <description>Pin driver is low</description>
108358 <description>Pin driver is high</description>
108365 <description>Pin 3</description>
108371 <description>Pin driver is low</description>
108376 <description>Pin driver is high</description>
108383 <description>Pin 4</description>
108389 <description>Pin driver is low</description>
108394 <description>Pin driver is high</description>
108401 <description>Pin 5</description>
108407 <description>Pin driver is low</description>
108412 <description>Pin driver is high</description>
108419 <description>Pin 6</description>
108425 <description>Pin driver is low</description>
108430 <description>Pin driver is high</description>
108437 <description>Pin 7</description>
108443 <description>Pin driver is low</description>
108448 <description>Pin driver is high</description>
108455 <description>Pin 8</description>
108461 <description>Pin driver is low</description>
108466 <description>Pin driver is high</description>
108473 <description>Pin 9</description>
108479 <description>Pin driver is low</description>
108484 <description>Pin driver is high</description>
108491 <description>Pin 10</description>
108497 <description>Pin driver is low</description>
108502 <description>Pin driver is high</description>
108509 <description>Pin 11</description>
108515 <description>Pin driver is low</description>
108520 <description>Pin driver is high</description>
108527 <description>Pin 12</description>
108533 <description>Pin driver is low</description>
108538 <description>Pin driver is high</description>
108545 <description>Pin 13</description>
108551 <description>Pin driver is low</description>
108556 <description>Pin driver is high</description>
108563 <description>Pin 14</description>
108569 <description>Pin driver is low</description>
108574 <description>Pin driver is high</description>
108581 <description>Pin 15</description>
108587 <description>Pin driver is low</description>
108592 <description>Pin driver is high</description>
108599 <description>Pin 16</description>
108605 <description>Pin driver is low</description>
108610 <description>Pin driver is high</description>
108617 <description>Pin 17</description>
108623 <description>Pin driver is low</description>
108628 <description>Pin driver is high</description>
108635 <description>Pin 18</description>
108641 <description>Pin driver is low</description>
108646 <description>Pin driver is high</description>
108653 <description>Pin 19</description>
108659 <description>Pin driver is low</description>
108664 <description>Pin driver is high</description>
108671 <description>Pin 20</description>
108677 <description>Pin driver is low</description>
108682 <description>Pin driver is high</description>
108689 <description>Pin 21</description>
108695 <description>Pin driver is low</description>
108700 <description>Pin driver is high</description>
108707 <description>Pin 22</description>
108713 <description>Pin driver is low</description>
108718 <description>Pin driver is high</description>
108725 <description>Pin 23</description>
108731 <description>Pin driver is low</description>
108736 <description>Pin driver is high</description>
108743 <description>Pin 24</description>
108749 <description>Pin driver is low</description>
108754 <description>Pin driver is high</description>
108761 <description>Pin 25</description>
108767 <description>Pin driver is low</description>
108772 <description>Pin driver is high</description>
108779 <description>Pin 26</description>
108785 <description>Pin driver is low</description>
108790 <description>Pin driver is high</description>
108797 <description>Pin 27</description>
108803 <description>Pin driver is low</description>
108808 <description>Pin driver is high</description>
108815 <description>Pin 28</description>
108821 <description>Pin driver is low</description>
108826 <description>Pin driver is high</description>
108833 <description>Pin 29</description>
108839 <description>Pin driver is low</description>
108844 <description>Pin driver is high</description>
108851 <description>Pin 30</description>
108857 <description>Pin driver is low</description>
108862 <description>Pin driver is high</description>
108869 <description>Pin 31</description>
108875 <description>Pin driver is low</description>
108880 <description>Pin driver is high</description>
108889 <description>Set individual bits in GPIO port</description>
108898 <description>Pin 0</description>
108905 <description>Read: pin driver is low</description>
108910 <description>Read: pin driver is high</description>
108918 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
108925 <description>Pin 1</description>
108932 <description>Read: pin driver is low</description>
108937 <description>Read: pin driver is high</description>
108945 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
108952 <description>Pin 2</description>
108959 <description>Read: pin driver is low</description>
108964 <description>Read: pin driver is high</description>
108972 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
108979 <description>Pin 3</description>
108986 <description>Read: pin driver is low</description>
108991 <description>Read: pin driver is high</description>
108999 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109006 <description>Pin 4</description>
109013 <description>Read: pin driver is low</description>
109018 <description>Read: pin driver is high</description>
109026 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109033 <description>Pin 5</description>
109040 <description>Read: pin driver is low</description>
109045 <description>Read: pin driver is high</description>
109053 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109060 <description>Pin 6</description>
109067 <description>Read: pin driver is low</description>
109072 <description>Read: pin driver is high</description>
109080 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109087 <description>Pin 7</description>
109094 <description>Read: pin driver is low</description>
109099 <description>Read: pin driver is high</description>
109107 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109114 <description>Pin 8</description>
109121 <description>Read: pin driver is low</description>
109126 <description>Read: pin driver is high</description>
109134 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109141 <description>Pin 9</description>
109148 <description>Read: pin driver is low</description>
109153 <description>Read: pin driver is high</description>
109161 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109168 <description>Pin 10</description>
109175 <description>Read: pin driver is low</description>
109180 <description>Read: pin driver is high</description>
109188 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109195 <description>Pin 11</description>
109202 <description>Read: pin driver is low</description>
109207 <description>Read: pin driver is high</description>
109215 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109222 <description>Pin 12</description>
109229 <description>Read: pin driver is low</description>
109234 <description>Read: pin driver is high</description>
109242 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109249 <description>Pin 13</description>
109256 <description>Read: pin driver is low</description>
109261 <description>Read: pin driver is high</description>
109269 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109276 <description>Pin 14</description>
109283 <description>Read: pin driver is low</description>
109288 <description>Read: pin driver is high</description>
109296 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109303 <description>Pin 15</description>
109310 <description>Read: pin driver is low</description>
109315 <description>Read: pin driver is high</description>
109323 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109330 <description>Pin 16</description>
109337 <description>Read: pin driver is low</description>
109342 <description>Read: pin driver is high</description>
109350 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109357 <description>Pin 17</description>
109364 <description>Read: pin driver is low</description>
109369 <description>Read: pin driver is high</description>
109377 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109384 <description>Pin 18</description>
109391 <description>Read: pin driver is low</description>
109396 <description>Read: pin driver is high</description>
109404 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109411 <description>Pin 19</description>
109418 <description>Read: pin driver is low</description>
109423 <description>Read: pin driver is high</description>
109431 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109438 <description>Pin 20</description>
109445 <description>Read: pin driver is low</description>
109450 <description>Read: pin driver is high</description>
109458 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109465 <description>Pin 21</description>
109472 <description>Read: pin driver is low</description>
109477 <description>Read: pin driver is high</description>
109485 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109492 <description>Pin 22</description>
109499 <description>Read: pin driver is low</description>
109504 <description>Read: pin driver is high</description>
109512 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109519 <description>Pin 23</description>
109526 <description>Read: pin driver is low</description>
109531 <description>Read: pin driver is high</description>
109539 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109546 <description>Pin 24</description>
109553 <description>Read: pin driver is low</description>
109558 <description>Read: pin driver is high</description>
109566 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109573 <description>Pin 25</description>
109580 <description>Read: pin driver is low</description>
109585 <description>Read: pin driver is high</description>
109593 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109600 <description>Pin 26</description>
109607 <description>Read: pin driver is low</description>
109612 <description>Read: pin driver is high</description>
109620 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109627 <description>Pin 27</description>
109634 <description>Read: pin driver is low</description>
109639 <description>Read: pin driver is high</description>
109647 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109654 <description>Pin 28</description>
109661 <description>Read: pin driver is low</description>
109666 <description>Read: pin driver is high</description>
109674 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109681 <description>Pin 29</description>
109688 <description>Read: pin driver is low</description>
109693 <description>Read: pin driver is high</description>
109701 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109708 <description>Pin 30</description>
109715 <description>Read: pin driver is low</description>
109720 <description>Read: pin driver is high</description>
109728 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109735 <description>Pin 31</description>
109742 <description>Read: pin driver is low</description>
109747 <description>Read: pin driver is high</description>
109755 … <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
109764 <description>Clear individual bits in GPIO port</description>
109773 <description>Pin 0</description>
109780 <description>Read: pin driver is low</description>
109785 <description>Read: pin driver is high</description>
109793 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
109800 <description>Pin 1</description>
109807 <description>Read: pin driver is low</description>
109812 <description>Read: pin driver is high</description>
109820 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
109827 <description>Pin 2</description>
109834 <description>Read: pin driver is low</description>
109839 <description>Read: pin driver is high</description>
109847 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
109854 <description>Pin 3</description>
109861 <description>Read: pin driver is low</description>
109866 <description>Read: pin driver is high</description>
109874 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
109881 <description>Pin 4</description>
109888 <description>Read: pin driver is low</description>
109893 <description>Read: pin driver is high</description>
109901 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
109908 <description>Pin 5</description>
109915 <description>Read: pin driver is low</description>
109920 <description>Read: pin driver is high</description>
109928 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
109935 <description>Pin 6</description>
109942 <description>Read: pin driver is low</description>
109947 <description>Read: pin driver is high</description>
109955 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
109962 <description>Pin 7</description>
109969 <description>Read: pin driver is low</description>
109974 <description>Read: pin driver is high</description>
109982 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
109989 <description>Pin 8</description>
109996 <description>Read: pin driver is low</description>
110001 <description>Read: pin driver is high</description>
110009 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110016 <description>Pin 9</description>
110023 <description>Read: pin driver is low</description>
110028 <description>Read: pin driver is high</description>
110036 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110043 <description>Pin 10</description>
110050 <description>Read: pin driver is low</description>
110055 <description>Read: pin driver is high</description>
110063 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110070 <description>Pin 11</description>
110077 <description>Read: pin driver is low</description>
110082 <description>Read: pin driver is high</description>
110090 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110097 <description>Pin 12</description>
110104 <description>Read: pin driver is low</description>
110109 <description>Read: pin driver is high</description>
110117 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110124 <description>Pin 13</description>
110131 <description>Read: pin driver is low</description>
110136 <description>Read: pin driver is high</description>
110144 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110151 <description>Pin 14</description>
110158 <description>Read: pin driver is low</description>
110163 <description>Read: pin driver is high</description>
110171 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110178 <description>Pin 15</description>
110185 <description>Read: pin driver is low</description>
110190 <description>Read: pin driver is high</description>
110198 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110205 <description>Pin 16</description>
110212 <description>Read: pin driver is low</description>
110217 <description>Read: pin driver is high</description>
110225 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110232 <description>Pin 17</description>
110239 <description>Read: pin driver is low</description>
110244 <description>Read: pin driver is high</description>
110252 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110259 <description>Pin 18</description>
110266 <description>Read: pin driver is low</description>
110271 <description>Read: pin driver is high</description>
110279 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110286 <description>Pin 19</description>
110293 <description>Read: pin driver is low</description>
110298 <description>Read: pin driver is high</description>
110306 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110313 <description>Pin 20</description>
110320 <description>Read: pin driver is low</description>
110325 <description>Read: pin driver is high</description>
110333 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110340 <description>Pin 21</description>
110347 <description>Read: pin driver is low</description>
110352 <description>Read: pin driver is high</description>
110360 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110367 <description>Pin 22</description>
110374 <description>Read: pin driver is low</description>
110379 <description>Read: pin driver is high</description>
110387 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110394 <description>Pin 23</description>
110401 <description>Read: pin driver is low</description>
110406 <description>Read: pin driver is high</description>
110414 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110421 <description>Pin 24</description>
110428 <description>Read: pin driver is low</description>
110433 <description>Read: pin driver is high</description>
110441 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110448 <description>Pin 25</description>
110455 <description>Read: pin driver is low</description>
110460 <description>Read: pin driver is high</description>
110468 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110475 <description>Pin 26</description>
110482 <description>Read: pin driver is low</description>
110487 <description>Read: pin driver is high</description>
110495 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110502 <description>Pin 27</description>
110509 <description>Read: pin driver is low</description>
110514 <description>Read: pin driver is high</description>
110522 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110529 <description>Pin 28</description>
110536 <description>Read: pin driver is low</description>
110541 <description>Read: pin driver is high</description>
110549 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110556 <description>Pin 29</description>
110563 <description>Read: pin driver is low</description>
110568 <description>Read: pin driver is high</description>
110576 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110583 <description>Pin 30</description>
110590 <description>Read: pin driver is low</description>
110595 <description>Read: pin driver is high</description>
110603 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110610 <description>Pin 31</description>
110617 <description>Read: pin driver is low</description>
110622 <description>Read: pin driver is high</description>
110630 … <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
110639 <description>Read GPIO port</description>
110647 <description>Pin 0</description>
110653 <description>Pin input is low</description>
110658 <description>Pin input is high</description>
110665 <description>Pin 1</description>
110671 <description>Pin input is low</description>
110676 <description>Pin input is high</description>
110683 <description>Pin 2</description>
110689 <description>Pin input is low</description>
110694 <description>Pin input is high</description>
110701 <description>Pin 3</description>
110707 <description>Pin input is low</description>
110712 <description>Pin input is high</description>
110719 <description>Pin 4</description>
110725 <description>Pin input is low</description>
110730 <description>Pin input is high</description>
110737 <description>Pin 5</description>
110743 <description>Pin input is low</description>
110748 <description>Pin input is high</description>
110755 <description>Pin 6</description>
110761 <description>Pin input is low</description>
110766 <description>Pin input is high</description>
110773 <description>Pin 7</description>
110779 <description>Pin input is low</description>
110784 <description>Pin input is high</description>
110791 <description>Pin 8</description>
110797 <description>Pin input is low</description>
110802 <description>Pin input is high</description>
110809 <description>Pin 9</description>
110815 <description>Pin input is low</description>
110820 <description>Pin input is high</description>
110827 <description>Pin 10</description>
110833 <description>Pin input is low</description>
110838 <description>Pin input is high</description>
110845 <description>Pin 11</description>
110851 <description>Pin input is low</description>
110856 <description>Pin input is high</description>
110863 <description>Pin 12</description>
110869 <description>Pin input is low</description>
110874 <description>Pin input is high</description>
110881 <description>Pin 13</description>
110887 <description>Pin input is low</description>
110892 <description>Pin input is high</description>
110899 <description>Pin 14</description>
110905 <description>Pin input is low</description>
110910 <description>Pin input is high</description>
110917 <description>Pin 15</description>
110923 <description>Pin input is low</description>
110928 <description>Pin input is high</description>
110935 <description>Pin 16</description>
110941 <description>Pin input is low</description>
110946 <description>Pin input is high</description>
110953 <description>Pin 17</description>
110959 <description>Pin input is low</description>
110964 <description>Pin input is high</description>
110971 <description>Pin 18</description>
110977 <description>Pin input is low</description>
110982 <description>Pin input is high</description>
110989 <description>Pin 19</description>
110995 <description>Pin input is low</description>
111000 <description>Pin input is high</description>
111007 <description>Pin 20</description>
111013 <description>Pin input is low</description>
111018 <description>Pin input is high</description>
111025 <description>Pin 21</description>
111031 <description>Pin input is low</description>
111036 <description>Pin input is high</description>
111043 <description>Pin 22</description>
111049 <description>Pin input is low</description>
111054 <description>Pin input is high</description>
111061 <description>Pin 23</description>
111067 <description>Pin input is low</description>
111072 <description>Pin input is high</description>
111079 <description>Pin 24</description>
111085 <description>Pin input is low</description>
111090 <description>Pin input is high</description>
111097 <description>Pin 25</description>
111103 <description>Pin input is low</description>
111108 <description>Pin input is high</description>
111115 <description>Pin 26</description>
111121 <description>Pin input is low</description>
111126 <description>Pin input is high</description>
111133 <description>Pin 27</description>
111139 <description>Pin input is low</description>
111144 <description>Pin input is high</description>
111151 <description>Pin 28</description>
111157 <description>Pin input is low</description>
111162 <description>Pin input is high</description>
111169 <description>Pin 29</description>
111175 <description>Pin input is low</description>
111180 <description>Pin input is high</description>
111187 <description>Pin 30</description>
111193 <description>Pin input is low</description>
111198 <description>Pin input is high</description>
111205 <description>Pin 31</description>
111211 <description>Pin input is low</description>
111216 <description>Pin input is high</description>
111225 <description>Direction of GPIO pins</description>
111233 <description>Pin 0</description>
111239 <description>Pin set as input</description>
111244 <description>Pin set as output</description>
111251 <description>Pin 1</description>
111257 <description>Pin set as input</description>
111262 <description>Pin set as output</description>
111269 <description>Pin 2</description>
111275 <description>Pin set as input</description>
111280 <description>Pin set as output</description>
111287 <description>Pin 3</description>
111293 <description>Pin set as input</description>
111298 <description>Pin set as output</description>
111305 <description>Pin 4</description>
111311 <description>Pin set as input</description>
111316 <description>Pin set as output</description>
111323 <description>Pin 5</description>
111329 <description>Pin set as input</description>
111334 <description>Pin set as output</description>
111341 <description>Pin 6</description>
111347 <description>Pin set as input</description>
111352 <description>Pin set as output</description>
111359 <description>Pin 7</description>
111365 <description>Pin set as input</description>
111370 <description>Pin set as output</description>
111377 <description>Pin 8</description>
111383 <description>Pin set as input</description>
111388 <description>Pin set as output</description>
111395 <description>Pin 9</description>
111401 <description>Pin set as input</description>
111406 <description>Pin set as output</description>
111413 <description>Pin 10</description>
111419 <description>Pin set as input</description>
111424 <description>Pin set as output</description>
111431 <description>Pin 11</description>
111437 <description>Pin set as input</description>
111442 <description>Pin set as output</description>
111449 <description>Pin 12</description>
111455 <description>Pin set as input</description>
111460 <description>Pin set as output</description>
111467 <description>Pin 13</description>
111473 <description>Pin set as input</description>
111478 <description>Pin set as output</description>
111485 <description>Pin 14</description>
111491 <description>Pin set as input</description>
111496 <description>Pin set as output</description>
111503 <description>Pin 15</description>
111509 <description>Pin set as input</description>
111514 <description>Pin set as output</description>
111521 <description>Pin 16</description>
111527 <description>Pin set as input</description>
111532 <description>Pin set as output</description>
111539 <description>Pin 17</description>
111545 <description>Pin set as input</description>
111550 <description>Pin set as output</description>
111557 <description>Pin 18</description>
111563 <description>Pin set as input</description>
111568 <description>Pin set as output</description>
111575 <description>Pin 19</description>
111581 <description>Pin set as input</description>
111586 <description>Pin set as output</description>
111593 <description>Pin 20</description>
111599 <description>Pin set as input</description>
111604 <description>Pin set as output</description>
111611 <description>Pin 21</description>
111617 <description>Pin set as input</description>
111622 <description>Pin set as output</description>
111629 <description>Pin 22</description>
111635 <description>Pin set as input</description>
111640 <description>Pin set as output</description>
111647 <description>Pin 23</description>
111653 <description>Pin set as input</description>
111658 <description>Pin set as output</description>
111665 <description>Pin 24</description>
111671 <description>Pin set as input</description>
111676 <description>Pin set as output</description>
111683 <description>Pin 25</description>
111689 <description>Pin set as input</description>
111694 <description>Pin set as output</description>
111701 <description>Pin 26</description>
111707 <description>Pin set as input</description>
111712 <description>Pin set as output</description>
111719 <description>Pin 27</description>
111725 <description>Pin set as input</description>
111730 <description>Pin set as output</description>
111737 <description>Pin 28</description>
111743 <description>Pin set as input</description>
111748 <description>Pin set as output</description>
111755 <description>Pin 29</description>
111761 <description>Pin set as input</description>
111766 <description>Pin set as output</description>
111773 <description>Pin 30</description>
111779 <description>Pin set as input</description>
111784 <description>Pin set as output</description>
111791 <description>Pin 31</description>
111797 <description>Pin set as input</description>
111802 <description>Pin set as output</description>
111811 <description>DIR set register</description>
111820 <description>Set as output pin 0</description>
111827 <description>Read: pin set as input</description>
111832 <description>Read: pin set as output</description>
111840 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
111847 <description>Set as output pin 1</description>
111854 <description>Read: pin set as input</description>
111859 <description>Read: pin set as output</description>
111867 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
111874 <description>Set as output pin 2</description>
111881 <description>Read: pin set as input</description>
111886 <description>Read: pin set as output</description>
111894 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
111901 <description>Set as output pin 3</description>
111908 <description>Read: pin set as input</description>
111913 <description>Read: pin set as output</description>
111921 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
111928 <description>Set as output pin 4</description>
111935 <description>Read: pin set as input</description>
111940 <description>Read: pin set as output</description>
111948 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
111955 <description>Set as output pin 5</description>
111962 <description>Read: pin set as input</description>
111967 <description>Read: pin set as output</description>
111975 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
111982 <description>Set as output pin 6</description>
111989 <description>Read: pin set as input</description>
111994 <description>Read: pin set as output</description>
112002 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112009 <description>Set as output pin 7</description>
112016 <description>Read: pin set as input</description>
112021 <description>Read: pin set as output</description>
112029 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112036 <description>Set as output pin 8</description>
112043 <description>Read: pin set as input</description>
112048 <description>Read: pin set as output</description>
112056 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112063 <description>Set as output pin 9</description>
112070 <description>Read: pin set as input</description>
112075 <description>Read: pin set as output</description>
112083 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112090 <description>Set as output pin 10</description>
112097 <description>Read: pin set as input</description>
112102 <description>Read: pin set as output</description>
112110 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112117 <description>Set as output pin 11</description>
112124 <description>Read: pin set as input</description>
112129 <description>Read: pin set as output</description>
112137 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112144 <description>Set as output pin 12</description>
112151 <description>Read: pin set as input</description>
112156 <description>Read: pin set as output</description>
112164 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112171 <description>Set as output pin 13</description>
112178 <description>Read: pin set as input</description>
112183 <description>Read: pin set as output</description>
112191 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112198 <description>Set as output pin 14</description>
112205 <description>Read: pin set as input</description>
112210 <description>Read: pin set as output</description>
112218 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112225 <description>Set as output pin 15</description>
112232 <description>Read: pin set as input</description>
112237 <description>Read: pin set as output</description>
112245 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112252 <description>Set as output pin 16</description>
112259 <description>Read: pin set as input</description>
112264 <description>Read: pin set as output</description>
112272 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112279 <description>Set as output pin 17</description>
112286 <description>Read: pin set as input</description>
112291 <description>Read: pin set as output</description>
112299 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112306 <description>Set as output pin 18</description>
112313 <description>Read: pin set as input</description>
112318 <description>Read: pin set as output</description>
112326 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112333 <description>Set as output pin 19</description>
112340 <description>Read: pin set as input</description>
112345 <description>Read: pin set as output</description>
112353 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112360 <description>Set as output pin 20</description>
112367 <description>Read: pin set as input</description>
112372 <description>Read: pin set as output</description>
112380 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112387 <description>Set as output pin 21</description>
112394 <description>Read: pin set as input</description>
112399 <description>Read: pin set as output</description>
112407 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112414 <description>Set as output pin 22</description>
112421 <description>Read: pin set as input</description>
112426 <description>Read: pin set as output</description>
112434 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112441 <description>Set as output pin 23</description>
112448 <description>Read: pin set as input</description>
112453 <description>Read: pin set as output</description>
112461 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112468 <description>Set as output pin 24</description>
112475 <description>Read: pin set as input</description>
112480 <description>Read: pin set as output</description>
112488 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112495 <description>Set as output pin 25</description>
112502 <description>Read: pin set as input</description>
112507 <description>Read: pin set as output</description>
112515 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112522 <description>Set as output pin 26</description>
112529 <description>Read: pin set as input</description>
112534 <description>Read: pin set as output</description>
112542 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112549 <description>Set as output pin 27</description>
112556 <description>Read: pin set as input</description>
112561 <description>Read: pin set as output</description>
112569 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112576 <description>Set as output pin 28</description>
112583 <description>Read: pin set as input</description>
112588 <description>Read: pin set as output</description>
112596 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112603 <description>Set as output pin 29</description>
112610 <description>Read: pin set as input</description>
112615 <description>Read: pin set as output</description>
112623 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112630 <description>Set as output pin 30</description>
112637 <description>Read: pin set as input</description>
112642 <description>Read: pin set as output</description>
112650 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112657 <description>Set as output pin 31</description>
112664 <description>Read: pin set as input</description>
112669 <description>Read: pin set as output</description>
112677 … <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
112686 <description>DIR clear register</description>
112695 <description>Set as input pin 0</description>
112702 <description>Read: pin set as input</description>
112707 <description>Read: pin set as output</description>
112715 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
112722 <description>Set as input pin 1</description>
112729 <description>Read: pin set as input</description>
112734 <description>Read: pin set as output</description>
112742 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
112749 <description>Set as input pin 2</description>
112756 <description>Read: pin set as input</description>
112761 <description>Read: pin set as output</description>
112769 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
112776 <description>Set as input pin 3</description>
112783 <description>Read: pin set as input</description>
112788 <description>Read: pin set as output</description>
112796 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
112803 <description>Set as input pin 4</description>
112810 <description>Read: pin set as input</description>
112815 <description>Read: pin set as output</description>
112823 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
112830 <description>Set as input pin 5</description>
112837 <description>Read: pin set as input</description>
112842 <description>Read: pin set as output</description>
112850 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
112857 <description>Set as input pin 6</description>
112864 <description>Read: pin set as input</description>
112869 <description>Read: pin set as output</description>
112877 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
112884 <description>Set as input pin 7</description>
112891 <description>Read: pin set as input</description>
112896 <description>Read: pin set as output</description>
112904 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
112911 <description>Set as input pin 8</description>
112918 <description>Read: pin set as input</description>
112923 <description>Read: pin set as output</description>
112931 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
112938 <description>Set as input pin 9</description>
112945 <description>Read: pin set as input</description>
112950 <description>Read: pin set as output</description>
112958 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
112965 <description>Set as input pin 10</description>
112972 <description>Read: pin set as input</description>
112977 <description>Read: pin set as output</description>
112985 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
112992 <description>Set as input pin 11</description>
112999 <description>Read: pin set as input</description>
113004 <description>Read: pin set as output</description>
113012 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
113019 <description>Set as input pin 12</description>
113026 <description>Read: pin set as input</description>
113031 <description>Read: pin set as output</description>
113039 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
113046 <description>Set as input pin 13</description>
113053 <description>Read: pin set as input</description>
113058 <description>Read: pin set as output</description>
113066 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
113073 <description>Set as input pin 14</description>
113080 <description>Read: pin set as input</description>
113085 <description>Read: pin set as output</description>
113093 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
113100 <description>Set as input pin 15</description>
113107 <description>Read: pin set as input</description>
113112 <description>Read: pin set as output</description>
113120 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
113127 <description>Set as input pin 16</description>
113134 <description>Read: pin set as input</description>
113139 <description>Read: pin set as output</description>
113147 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
113154 <description>Set as input pin 17</description>
113161 <description>Read: pin set as input</description>
113166 <description>Read: pin set as output</description>
113174 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
113181 <description>Set as input pin 18</description>
113188 <description>Read: pin set as input</description>
113193 <description>Read: pin set as output</description>
113201 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
113208 <description>Set as input pin 19</description>
113215 <description>Read: pin set as input</description>
113220 <description>Read: pin set as output</description>
113228 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
113235 <description>Set as input pin 20</description>
113242 <description>Read: pin set as input</description>
113247 <description>Read: pin set as output</description>
113255 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
113262 <description>Set as input pin 21</description>
113269 <description>Read: pin set as input</description>
113274 <description>Read: pin set as output</description>
113282 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
113289 <description>Set as input pin 22</description>
113296 <description>Read: pin set as input</description>
113301 <description>Read: pin set as output</description>
113309 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
113316 <description>Set as input pin 23</description>
113323 <description>Read: pin set as input</description>
113328 <description>Read: pin set as output</description>
113336 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
113343 <description>Set as input pin 24</description>
113350 <description>Read: pin set as input</description>
113355 <description>Read: pin set as output</description>
113363 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
113370 <description>Set as input pin 25</description>
113377 <description>Read: pin set as input</description>
113382 <description>Read: pin set as output</description>
113390 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
113397 <description>Set as input pin 26</description>
113404 <description>Read: pin set as input</description>
113409 <description>Read: pin set as output</description>
113417 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
113424 <description>Set as input pin 27</description>
113431 <description>Read: pin set as input</description>
113436 <description>Read: pin set as output</description>
113444 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
113451 <description>Set as input pin 28</description>
113458 <description>Read: pin set as input</description>
113463 <description>Read: pin set as output</description>
113471 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
113478 <description>Set as input pin 29</description>
113485 <description>Read: pin set as input</description>
113490 <description>Read: pin set as output</description>
113498 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
113505 <description>Set as input pin 30</description>
113512 <description>Read: pin set as input</description>
113517 <description>Read: pin set as output</description>
113525 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
113532 <description>Set as input pin 31</description>
113539 <description>Read: pin set as input</description>
113544 <description>Read: pin set as output</description>
113552 … <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
113561 …<description>Latch register indicating what GPIO pins that have met the criteria set in the PIN_CN…
113569 …<description>Status on whether PIN0 has met criteria set in PIN_CNF[0].SENSE register. Write '1' t…
113575 <description>Criteria has not been met</description>
113580 <description>Criteria has been met</description>
113587 …<description>Status on whether PIN1 has met criteria set in PIN_CNF[1].SENSE register. Write '1' t…
113593 <description>Criteria has not been met</description>
113598 <description>Criteria has been met</description>
113605 …<description>Status on whether PIN2 has met criteria set in PIN_CNF[2].SENSE register. Write '1' t…
113611 <description>Criteria has not been met</description>
113616 <description>Criteria has been met</description>
113623 …<description>Status on whether PIN3 has met criteria set in PIN_CNF[3].SENSE register. Write '1' t…
113629 <description>Criteria has not been met</description>
113634 <description>Criteria has been met</description>
113641 …<description>Status on whether PIN4 has met criteria set in PIN_CNF[4].SENSE register. Write '1' t…
113647 <description>Criteria has not been met</description>
113652 <description>Criteria has been met</description>
113659 …<description>Status on whether PIN5 has met criteria set in PIN_CNF[5].SENSE register. Write '1' t…
113665 <description>Criteria has not been met</description>
113670 <description>Criteria has been met</description>
113677 …<description>Status on whether PIN6 has met criteria set in PIN_CNF[6].SENSE register. Write '1' t…
113683 <description>Criteria has not been met</description>
113688 <description>Criteria has been met</description>
113695 …<description>Status on whether PIN7 has met criteria set in PIN_CNF[7].SENSE register. Write '1' t…
113701 <description>Criteria has not been met</description>
113706 <description>Criteria has been met</description>
113713 …<description>Status on whether PIN8 has met criteria set in PIN_CNF[8].SENSE register. Write '1' t…
113719 <description>Criteria has not been met</description>
113724 <description>Criteria has been met</description>
113731 …<description>Status on whether PIN9 has met criteria set in PIN_CNF[9].SENSE register. Write '1' t…
113737 <description>Criteria has not been met</description>
113742 <description>Criteria has been met</description>
113749 …<description>Status on whether PIN10 has met criteria set in PIN_CNF[10].SENSE register. Write '1'…
113755 <description>Criteria has not been met</description>
113760 <description>Criteria has been met</description>
113767 …<description>Status on whether PIN11 has met criteria set in PIN_CNF[11].SENSE register. Write '1'…
113773 <description>Criteria has not been met</description>
113778 <description>Criteria has been met</description>
113785 …<description>Status on whether PIN12 has met criteria set in PIN_CNF[12].SENSE register. Write '1'…
113791 <description>Criteria has not been met</description>
113796 <description>Criteria has been met</description>
113803 …<description>Status on whether PIN13 has met criteria set in PIN_CNF[13].SENSE register. Write '1'…
113809 <description>Criteria has not been met</description>
113814 <description>Criteria has been met</description>
113821 …<description>Status on whether PIN14 has met criteria set in PIN_CNF[14].SENSE register. Write '1'…
113827 <description>Criteria has not been met</description>
113832 <description>Criteria has been met</description>
113839 …<description>Status on whether PIN15 has met criteria set in PIN_CNF[15].SENSE register. Write '1'…
113845 <description>Criteria has not been met</description>
113850 <description>Criteria has been met</description>
113857 …<description>Status on whether PIN16 has met criteria set in PIN_CNF[16].SENSE register. Write '1'…
113863 <description>Criteria has not been met</description>
113868 <description>Criteria has been met</description>
113875 …<description>Status on whether PIN17 has met criteria set in PIN_CNF[17].SENSE register. Write '1'…
113881 <description>Criteria has not been met</description>
113886 <description>Criteria has been met</description>
113893 …<description>Status on whether PIN18 has met criteria set in PIN_CNF[18].SENSE register. Write '1'…
113899 <description>Criteria has not been met</description>
113904 <description>Criteria has been met</description>
113911 …<description>Status on whether PIN19 has met criteria set in PIN_CNF[19].SENSE register. Write '1'…
113917 <description>Criteria has not been met</description>
113922 <description>Criteria has been met</description>
113929 …<description>Status on whether PIN20 has met criteria set in PIN_CNF[20].SENSE register. Write '1'…
113935 <description>Criteria has not been met</description>
113940 <description>Criteria has been met</description>
113947 …<description>Status on whether PIN21 has met criteria set in PIN_CNF[21].SENSE register. Write '1'…
113953 <description>Criteria has not been met</description>
113958 <description>Criteria has been met</description>
113965 …<description>Status on whether PIN22 has met criteria set in PIN_CNF[22].SENSE register. Write '1'…
113971 <description>Criteria has not been met</description>
113976 <description>Criteria has been met</description>
113983 …<description>Status on whether PIN23 has met criteria set in PIN_CNF[23].SENSE register. Write '1'…
113989 <description>Criteria has not been met</description>
113994 <description>Criteria has been met</description>
114001 …<description>Status on whether PIN24 has met criteria set in PIN_CNF[24].SENSE register. Write '1'…
114007 <description>Criteria has not been met</description>
114012 <description>Criteria has been met</description>
114019 …<description>Status on whether PIN25 has met criteria set in PIN_CNF[25].SENSE register. Write '1'…
114025 <description>Criteria has not been met</description>
114030 <description>Criteria has been met</description>
114037 …<description>Status on whether PIN26 has met criteria set in PIN_CNF[26].SENSE register. Write '1'…
114043 <description>Criteria has not been met</description>
114048 <description>Criteria has been met</description>
114055 …<description>Status on whether PIN27 has met criteria set in PIN_CNF[27].SENSE register. Write '1'…
114061 <description>Criteria has not been met</description>
114066 <description>Criteria has been met</description>
114073 …<description>Status on whether PIN28 has met criteria set in PIN_CNF[28].SENSE register. Write '1'…
114079 <description>Criteria has not been met</description>
114084 <description>Criteria has been met</description>
114091 …<description>Status on whether PIN29 has met criteria set in PIN_CNF[29].SENSE register. Write '1'…
114097 <description>Criteria has not been met</description>
114102 <description>Criteria has been met</description>
114109 …<description>Status on whether PIN30 has met criteria set in PIN_CNF[30].SENSE register. Write '1'…
114115 <description>Criteria has not been met</description>
114120 <description>Criteria has been met</description>
114127 …<description>Status on whether PIN31 has met criteria set in PIN_CNF[31].SENSE register. Write '1'…
114133 <description>Criteria has not been met</description>
114138 <description>Criteria has been met</description>
114147 <description>Select between default DETECT signal behavior and LDETECT mode</description>
114156 … <description>Select between default DETECT signal behavior and LDETECT mode</description>
114162 <description>DETECT directly connected to PIN DETECT signals</description>
114167 <description>Use the latched LDETECT behavior</description>
114176 <description>Unspecified</description>
114182 <description>Drive control for impedance matching of the pins in this port</description>
114191 <description>Enable 50 ohms impedance to the pins in this port</description>
114197 <description>Disabled</description>
114202 <description>Enable</description>
114209 <description>Enable 100 ohms impedance to the pins in this port</description>
114215 <description>Disabled</description>
114220 <description>Enable</description>
114227 <description>Enable 200 ohms impedance to the pins in this port</description>
114233 <description>Disabled</description>
114238 <description>Enable</description>
114245 <description>Enable 400 ohms impedance to the pins in this port</description>
114251 <description>Disabled</description>
114256 <description>Enable</description>
114263 <description>Enable 800 ohms impedance to the pins in this port</description>
114269 <description>Disabled</description>
114274 <description>Enable</description>
114281 <description>Enable 1600 ohms impedance to the pins in this port</description>
114287 <description>Disabled</description>
114292 <description>Enable</description>
114302 …<description>RETAIN of each individual GPIO pin. Pins with their RETAIN bit set keep their state i…
114305 all its state including the output value, DIR and PORTCNF settings.</description>
114313 <description>Pin 0</description>
114319 <description>Pin not retained</description>
114324 <description>Pin retained</description>
114331 <description>Pin 1</description>
114337 <description>Pin not retained</description>
114342 <description>Pin retained</description>
114349 <description>Pin 2</description>
114355 <description>Pin not retained</description>
114360 <description>Pin retained</description>
114367 <description>Pin 3</description>
114373 <description>Pin not retained</description>
114378 <description>Pin retained</description>
114385 <description>Pin 4</description>
114391 <description>Pin not retained</description>
114396 <description>Pin retained</description>
114403 <description>Pin 5</description>
114409 <description>Pin not retained</description>
114414 <description>Pin retained</description>
114421 <description>Pin 6</description>
114427 <description>Pin not retained</description>
114432 <description>Pin retained</description>
114439 <description>Pin 7</description>
114445 <description>Pin not retained</description>
114450 <description>Pin retained</description>
114457 <description>Pin 8</description>
114463 <description>Pin not retained</description>
114468 <description>Pin retained</description>
114475 <description>Pin 9</description>
114481 <description>Pin not retained</description>
114486 <description>Pin retained</description>
114493 <description>Pin 10</description>
114499 <description>Pin not retained</description>
114504 <description>Pin retained</description>
114511 <description>Pin 11</description>
114517 <description>Pin not retained</description>
114522 <description>Pin retained</description>
114529 <description>Pin 12</description>
114535 <description>Pin not retained</description>
114540 <description>Pin retained</description>
114547 <description>Pin 13</description>
114553 <description>Pin not retained</description>
114558 <description>Pin retained</description>
114565 <description>Pin 14</description>
114571 <description>Pin not retained</description>
114576 <description>Pin retained</description>
114583 <description>Pin 15</description>
114589 <description>Pin not retained</description>
114594 <description>Pin retained</description>
114601 <description>Pin 16</description>
114607 <description>Pin not retained</description>
114612 <description>Pin retained</description>
114619 <description>Pin 17</description>
114625 <description>Pin not retained</description>
114630 <description>Pin retained</description>
114637 <description>Pin 18</description>
114643 <description>Pin not retained</description>
114648 <description>Pin retained</description>
114655 <description>Pin 19</description>
114661 <description>Pin not retained</description>
114666 <description>Pin retained</description>
114673 <description>Pin 20</description>
114679 <description>Pin not retained</description>
114684 <description>Pin retained</description>
114691 <description>Pin 21</description>
114697 <description>Pin not retained</description>
114702 <description>Pin retained</description>
114709 <description>Pin 22</description>
114715 <description>Pin not retained</description>
114720 <description>Pin retained</description>
114727 <description>Pin 23</description>
114733 <description>Pin not retained</description>
114738 <description>Pin retained</description>
114745 <description>Pin 24</description>
114751 <description>Pin not retained</description>
114756 <description>Pin retained</description>
114763 <description>Pin 25</description>
114769 <description>Pin not retained</description>
114774 <description>Pin retained</description>
114781 <description>Pin 26</description>
114787 <description>Pin not retained</description>
114792 <description>Pin retained</description>
114799 <description>Pin 27</description>
114805 <description>Pin not retained</description>
114810 <description>Pin retained</description>
114817 <description>Pin 28</description>
114823 <description>Pin not retained</description>
114828 <description>Pin retained</description>
114835 <description>Pin 29</description>
114841 <description>Pin not retained</description>
114846 <description>Pin retained</description>
114853 <description>Pin 30</description>
114859 <description>Pin not retained</description>
114864 <description>Pin retained</description>
114871 <description>Pin 31</description>
114877 <description>Pin not retained</description>
114882 <description>Pin retained</description>
114891 <description>Set RETAIN for individual GPIO pins</description>
114900 <description>Set RETAIN for pin 0</description>
114907 <description>Read: pin not retained</description>
114912 <description>Read: pin retained</description>
114920 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
114927 <description>Set RETAIN for pin 1</description>
114934 <description>Read: pin not retained</description>
114939 <description>Read: pin retained</description>
114947 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
114954 <description>Set RETAIN for pin 2</description>
114961 <description>Read: pin not retained</description>
114966 <description>Read: pin retained</description>
114974 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
114981 <description>Set RETAIN for pin 3</description>
114988 <description>Read: pin not retained</description>
114993 <description>Read: pin retained</description>
115001 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115008 <description>Set RETAIN for pin 4</description>
115015 <description>Read: pin not retained</description>
115020 <description>Read: pin retained</description>
115028 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115035 <description>Set RETAIN for pin 5</description>
115042 <description>Read: pin not retained</description>
115047 <description>Read: pin retained</description>
115055 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115062 <description>Set RETAIN for pin 6</description>
115069 <description>Read: pin not retained</description>
115074 <description>Read: pin retained</description>
115082 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115089 <description>Set RETAIN for pin 7</description>
115096 <description>Read: pin not retained</description>
115101 <description>Read: pin retained</description>
115109 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115116 <description>Set RETAIN for pin 8</description>
115123 <description>Read: pin not retained</description>
115128 <description>Read: pin retained</description>
115136 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115143 <description>Set RETAIN for pin 9</description>
115150 <description>Read: pin not retained</description>
115155 <description>Read: pin retained</description>
115163 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115170 <description>Set RETAIN for pin 10</description>
115177 <description>Read: pin not retained</description>
115182 <description>Read: pin retained</description>
115190 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115197 <description>Set RETAIN for pin 11</description>
115204 <description>Read: pin not retained</description>
115209 <description>Read: pin retained</description>
115217 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115224 <description>Set RETAIN for pin 12</description>
115231 <description>Read: pin not retained</description>
115236 <description>Read: pin retained</description>
115244 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115251 <description>Set RETAIN for pin 13</description>
115258 <description>Read: pin not retained</description>
115263 <description>Read: pin retained</description>
115271 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115278 <description>Set RETAIN for pin 14</description>
115285 <description>Read: pin not retained</description>
115290 <description>Read: pin retained</description>
115298 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115305 <description>Set RETAIN for pin 15</description>
115312 <description>Read: pin not retained</description>
115317 <description>Read: pin retained</description>
115325 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115332 <description>Set RETAIN for pin 16</description>
115339 <description>Read: pin not retained</description>
115344 <description>Read: pin retained</description>
115352 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115359 <description>Set RETAIN for pin 17</description>
115366 <description>Read: pin not retained</description>
115371 <description>Read: pin retained</description>
115379 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115386 <description>Set RETAIN for pin 18</description>
115393 <description>Read: pin not retained</description>
115398 <description>Read: pin retained</description>
115406 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115413 <description>Set RETAIN for pin 19</description>
115420 <description>Read: pin not retained</description>
115425 <description>Read: pin retained</description>
115433 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115440 <description>Set RETAIN for pin 20</description>
115447 <description>Read: pin not retained</description>
115452 <description>Read: pin retained</description>
115460 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115467 <description>Set RETAIN for pin 21</description>
115474 <description>Read: pin not retained</description>
115479 <description>Read: pin retained</description>
115487 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115494 <description>Set RETAIN for pin 22</description>
115501 <description>Read: pin not retained</description>
115506 <description>Read: pin retained</description>
115514 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115521 <description>Set RETAIN for pin 23</description>
115528 <description>Read: pin not retained</description>
115533 <description>Read: pin retained</description>
115541 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115548 <description>Set RETAIN for pin 24</description>
115555 <description>Read: pin not retained</description>
115560 <description>Read: pin retained</description>
115568 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115575 <description>Set RETAIN for pin 25</description>
115582 <description>Read: pin not retained</description>
115587 <description>Read: pin retained</description>
115595 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115602 <description>Set RETAIN for pin 26</description>
115609 <description>Read: pin not retained</description>
115614 <description>Read: pin retained</description>
115622 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115629 <description>Set RETAIN for pin 27</description>
115636 <description>Read: pin not retained</description>
115641 <description>Read: pin retained</description>
115649 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115656 <description>Set RETAIN for pin 28</description>
115663 <description>Read: pin not retained</description>
115668 <description>Read: pin retained</description>
115676 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115683 <description>Set RETAIN for pin 29</description>
115690 <description>Read: pin not retained</description>
115695 <description>Read: pin retained</description>
115703 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115710 <description>Set RETAIN for pin 30</description>
115717 <description>Read: pin not retained</description>
115722 <description>Read: pin retained</description>
115730 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115737 <description>Set RETAIN for pin 31</description>
115744 <description>Read: pin not retained</description>
115749 <description>Read: pin retained</description>
115757 … <description>Write: writing a '1' sets pin to retained; writing a '0' has no effect</description>
115766 <description>Clear RETAIN for individual GPIO pins</description>
115775 <description>Clear RETAIN for pin 0</description>
115782 <description>Read: pin not retained</description>
115787 <description>Read: pin retained</description>
115795 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
115802 <description>Clear RETAIN for pin 1</description>
115809 <description>Read: pin not retained</description>
115814 <description>Read: pin retained</description>
115822 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
115829 <description>Clear RETAIN for pin 2</description>
115836 <description>Read: pin not retained</description>
115841 <description>Read: pin retained</description>
115849 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
115856 <description>Clear RETAIN for pin 3</description>
115863 <description>Read: pin not retained</description>
115868 <description>Read: pin retained</description>
115876 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
115883 <description>Clear RETAIN for pin 4</description>
115890 <description>Read: pin not retained</description>
115895 <description>Read: pin retained</description>
115903 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
115910 <description>Clear RETAIN for pin 5</description>
115917 <description>Read: pin not retained</description>
115922 <description>Read: pin retained</description>
115930 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
115937 <description>Clear RETAIN for pin 6</description>
115944 <description>Read: pin not retained</description>
115949 <description>Read: pin retained</description>
115957 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
115964 <description>Clear RETAIN for pin 7</description>
115971 <description>Read: pin not retained</description>
115976 <description>Read: pin retained</description>
115984 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
115991 <description>Clear RETAIN for pin 8</description>
115998 <description>Read: pin not retained</description>
116003 <description>Read: pin retained</description>
116011 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116018 <description>Clear RETAIN for pin 9</description>
116025 <description>Read: pin not retained</description>
116030 <description>Read: pin retained</description>
116038 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116045 <description>Clear RETAIN for pin 10</description>
116052 <description>Read: pin not retained</description>
116057 <description>Read: pin retained</description>
116065 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116072 <description>Clear RETAIN for pin 11</description>
116079 <description>Read: pin not retained</description>
116084 <description>Read: pin retained</description>
116092 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116099 <description>Clear RETAIN for pin 12</description>
116106 <description>Read: pin not retained</description>
116111 <description>Read: pin retained</description>
116119 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116126 <description>Clear RETAIN for pin 13</description>
116133 <description>Read: pin not retained</description>
116138 <description>Read: pin retained</description>
116146 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116153 <description>Clear RETAIN for pin 14</description>
116160 <description>Read: pin not retained</description>
116165 <description>Read: pin retained</description>
116173 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116180 <description>Clear RETAIN for pin 15</description>
116187 <description>Read: pin not retained</description>
116192 <description>Read: pin retained</description>
116200 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116207 <description>Clear RETAIN for pin 16</description>
116214 <description>Read: pin not retained</description>
116219 <description>Read: pin retained</description>
116227 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116234 <description>Clear RETAIN for pin 17</description>
116241 <description>Read: pin not retained</description>
116246 <description>Read: pin retained</description>
116254 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116261 <description>Clear RETAIN for pin 18</description>
116268 <description>Read: pin not retained</description>
116273 <description>Read: pin retained</description>
116281 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116288 <description>Clear RETAIN for pin 19</description>
116295 <description>Read: pin not retained</description>
116300 <description>Read: pin retained</description>
116308 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116315 <description>Clear RETAIN for pin 20</description>
116322 <description>Read: pin not retained</description>
116327 <description>Read: pin retained</description>
116335 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116342 <description>Clear RETAIN for pin 21</description>
116349 <description>Read: pin not retained</description>
116354 <description>Read: pin retained</description>
116362 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116369 <description>Clear RETAIN for pin 22</description>
116376 <description>Read: pin not retained</description>
116381 <description>Read: pin retained</description>
116389 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116396 <description>Clear RETAIN for pin 23</description>
116403 <description>Read: pin not retained</description>
116408 <description>Read: pin retained</description>
116416 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116423 <description>Clear RETAIN for pin 24</description>
116430 <description>Read: pin not retained</description>
116435 <description>Read: pin retained</description>
116443 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116450 <description>Clear RETAIN for pin 25</description>
116457 <description>Read: pin not retained</description>
116462 <description>Read: pin retained</description>
116470 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116477 <description>Clear RETAIN for pin 26</description>
116484 <description>Read: pin not retained</description>
116489 <description>Read: pin retained</description>
116497 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116504 <description>Clear RETAIN for pin 27</description>
116511 <description>Read: pin not retained</description>
116516 <description>Read: pin retained</description>
116524 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116531 <description>Clear RETAIN for pin 28</description>
116538 <description>Read: pin not retained</description>
116543 <description>Read: pin retained</description>
116551 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116558 <description>Clear RETAIN for pin 29</description>
116565 <description>Read: pin not retained</description>
116570 <description>Read: pin retained</description>
116578 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116585 <description>Clear RETAIN for pin 30</description>
116592 <description>Read: pin not retained</description>
116597 <description>Read: pin retained</description>
116605 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116612 <description>Clear RETAIN for pin 31</description>
116619 <description>Read: pin not retained</description>
116624 <description>Read: pin retained</description>
116632 …<description>Write: writing a '1' sets pin to not retain; writing a '0' has no effect</description>
116643 <description>Description collection: Pin n configuration of GPIO pin</description>
116651 <description>Pin direction. Same physical register as DIR register</description>
116657 <description>Configure pin as an input pin</description>
116662 <description>Configure pin as an output pin</description>
116669 <description>Connect or disconnect input buffer</description>
116675 <description>Connect input buffer</description>
116680 <description>Disconnect input buffer</description>
116687 <description>Pull configuration</description>
116693 <description>No pull</description>
116698 <description>Pull down on pin</description>
116703 <description>Pull up on pin</description>
116710 <description>Drive configuration for '0'</description>
116716 <description>Standard '0'</description>
116721 <description>High drive '0'</description>
116726 <description>Disconnect '0'(normally used for wired-or connections)</description>
116731 <description>Extra high drive '0'</description>
116738 <description>Drive configuration for '1'</description>
116744 <description>Standard '1'</description>
116749 <description>High drive '1'</description>
116754 <description>Disconnect '1'(normally used for wired-or connections)</description>
116759 <description>Extra high drive '1'</description>
116766 <description>Pin sensing mechanism</description>
116772 <description>Disabled</description>
116777 <description>Sense for high level</description>
116782 <description>Sense for low level</description>
116789 <description>Enable clock on the pin.</description>
116795 <description>Clock disabled</description>
116800 <description>Clock enabled</description>
116811 <description>GPIO Port 1</description>
116819 <description>GPIO Port 2</description>
116827 <description>GPIO Port 3</description>
116835 <description>GPIO Port 4</description>
116843 <description>GPIO Port 5</description>
116851 <description>Distributed programmable peripheral interconnect controller 2</description>
116859 <description>Analog to Digital Converter</description>
116877 <description>Start the ADC and prepare the result buffer in RAM</description>
116885 <description>Start the ADC and prepare the result buffer in RAM</description>
116891 <description>Trigger task</description>
116900 …description>Take one ADC sample, if scan is enabled all channels are sampled. This task requires t…
116908 …description>Take one ADC sample, if scan is enabled all channels are sampled. This task requires t…
116914 <description>Trigger task</description>
116923 <description>Stop the ADC and terminate any on-going conversion</description>
116931 <description>Stop the ADC and terminate any on-going conversion</description>
116937 <description>Trigger task</description>
116946 <description>Starts offset auto-calibration</description>
116954 <description>Starts offset auto-calibration</description>
116960 <description>Trigger task</description>
116969 <description>Subscribe configuration for task START</description>
116977 <description>DPPI channel that task START will subscribe to</description>
116988 <description>Disable subscription</description>
116993 <description>Enable subscription</description>
117002 <description>Subscribe configuration for task SAMPLE</description>
117010 <description>DPPI channel that task SAMPLE will subscribe to</description>
117021 <description>Disable subscription</description>
117026 <description>Enable subscription</description>
117035 <description>Subscribe configuration for task STOP</description>
117043 <description>DPPI channel that task STOP will subscribe to</description>
117054 <description>Disable subscription</description>
117059 <description>Enable subscription</description>
117068 <description>Subscribe configuration for task CALIBRATEOFFSET</description>
117076 <description>DPPI channel that task CALIBRATEOFFSET will subscribe to</description>
117087 <description>Disable subscription</description>
117092 <description>Enable subscription</description>
117101 <description>The ADC has started</description>
117109 <description>The ADC has started</description>
117115 <description>Event not generated</description>
117120 <description>Event generated</description>
117129 <description>The ADC has filled up the Result buffer</description>
117137 <description>The ADC has filled up the Result buffer</description>
117143 <description>Event not generated</description>
117148 <description>Event generated</description>
117157 …description>A conversion task has been completed. Depending on the mode, multiple conversions migh…
117165 …description>A conversion task has been completed. Depending on the mode, multiple conversions migh…
117171 <description>Event not generated</description>
117176 <description>Event generated</description>
117185 <description>A result is ready to get transferred to RAM.</description>
117193 <description>A result is ready to get transferred to RAM.</description>
117199 <description>Event not generated</description>
117204 <description>Event generated</description>
117213 <description>Calibration is complete</description>
117221 <description>Calibration is complete</description>
117227 <description>Event not generated</description>
117232 <description>Event generated</description>
117241 <description>The ADC has stopped</description>
117249 <description>The ADC has stopped</description>
117255 <description>Event not generated</description>
117260 <description>Event generated</description>
117271 <description>Peripheral events.</description>
117277 … <description>Description cluster: Last results is equal or above CH[n].LIMIT.HIGH</description>
117285 <description>Last results is equal or above CH[n].LIMIT.HIGH</description>
117291 <description>Event not generated</description>
117296 <description>Event generated</description>
117305 … <description>Description cluster: Last results is equal or below CH[n].LIMIT.LOW</description>
117313 <description>Last results is equal or below CH[n].LIMIT.LOW</description>
117319 <description>Event not generated</description>
117324 <description>Event generated</description>
117334 <description>Publish configuration for event STARTED</description>
117342 <description>DPPI channel that event STARTED will publish to</description>
117353 <description>Disable publishing</description>
117358 <description>Enable publishing</description>
117367 <description>Publish configuration for event END</description>
117375 <description>DPPI channel that event END will publish to</description>
117386 <description>Disable publishing</description>
117391 <description>Enable publishing</description>
117400 <description>Publish configuration for event DONE</description>
117408 <description>DPPI channel that event DONE will publish to</description>
117419 <description>Disable publishing</description>
117424 <description>Enable publishing</description>
117433 <description>Publish configuration for event RESULTDONE</description>
117441 <description>DPPI channel that event RESULTDONE will publish to</description>
117452 <description>Disable publishing</description>
117457 <description>Enable publishing</description>
117466 <description>Publish configuration for event CALIBRATEDONE</description>
117474 <description>DPPI channel that event CALIBRATEDONE will publish to</description>
117485 <description>Disable publishing</description>
117490 <description>Enable publishing</description>
117499 <description>Publish configuration for event STOPPED</description>
117507 <description>DPPI channel that event STOPPED will publish to</description>
117518 <description>Disable publishing</description>
117523 <description>Enable publishing</description>
117534 <description>Publish configuration for events</description>
117540 … <description>Description cluster: Publish configuration for event CH[n].LIMITH</description>
117548 <description>DPPI channel that event CH[n].LIMITH will publish to</description>
117559 <description>Disable publishing</description>
117564 <description>Enable publishing</description>
117573 … <description>Description cluster: Publish configuration for event CH[n].LIMITL</description>
117581 <description>DPPI channel that event CH[n].LIMITL will publish to</description>
117592 <description>Disable publishing</description>
117597 <description>Enable publishing</description>
117607 <description>Enable or disable interrupt</description>
117615 <description>Enable or disable interrupt for event STARTED</description>
117621 <description>Disable</description>
117626 <description>Enable</description>
117633 <description>Enable or disable interrupt for event END</description>
117639 <description>Disable</description>
117644 <description>Enable</description>
117651 <description>Enable or disable interrupt for event DONE</description>
117657 <description>Disable</description>
117662 <description>Enable</description>
117669 <description>Enable or disable interrupt for event RESULTDONE</description>
117675 <description>Disable</description>
117680 <description>Enable</description>
117687 <description>Enable or disable interrupt for event CALIBRATEDONE</description>
117693 <description>Disable</description>
117698 <description>Enable</description>
117705 <description>Enable or disable interrupt for event STOPPED</description>
117711 <description>Disable</description>
117716 <description>Enable</description>
117723 <description>Enable or disable interrupt for event CH0LIMITH</description>
117729 <description>Disable</description>
117734 <description>Enable</description>
117741 <description>Enable or disable interrupt for event CH0LIMITL</description>
117747 <description>Disable</description>
117752 <description>Enable</description>
117759 <description>Enable or disable interrupt for event CH1LIMITH</description>
117765 <description>Disable</description>
117770 <description>Enable</description>
117777 <description>Enable or disable interrupt for event CH1LIMITL</description>
117783 <description>Disable</description>
117788 <description>Enable</description>
117795 <description>Enable or disable interrupt for event CH2LIMITH</description>
117801 <description>Disable</description>
117806 <description>Enable</description>
117813 <description>Enable or disable interrupt for event CH2LIMITL</description>
117819 <description>Disable</description>
117824 <description>Enable</description>
117831 <description>Enable or disable interrupt for event CH3LIMITH</description>
117837 <description>Disable</description>
117842 <description>Enable</description>
117849 <description>Enable or disable interrupt for event CH3LIMITL</description>
117855 <description>Disable</description>
117860 <description>Enable</description>
117867 <description>Enable or disable interrupt for event CH4LIMITH</description>
117873 <description>Disable</description>
117878 <description>Enable</description>
117885 <description>Enable or disable interrupt for event CH4LIMITL</description>
117891 <description>Disable</description>
117896 <description>Enable</description>
117903 <description>Enable or disable interrupt for event CH5LIMITH</description>
117909 <description>Disable</description>
117914 <description>Enable</description>
117921 <description>Enable or disable interrupt for event CH5LIMITL</description>
117927 <description>Disable</description>
117932 <description>Enable</description>
117939 <description>Enable or disable interrupt for event CH6LIMITH</description>
117945 <description>Disable</description>
117950 <description>Enable</description>
117957 <description>Enable or disable interrupt for event CH6LIMITL</description>
117963 <description>Disable</description>
117968 <description>Enable</description>
117975 <description>Enable or disable interrupt for event CH7LIMITH</description>
117981 <description>Disable</description>
117986 <description>Enable</description>
117993 <description>Enable or disable interrupt for event CH7LIMITL</description>
117999 <description>Disable</description>
118004 <description>Enable</description>
118013 <description>Enable interrupt</description>
118021 <description>Write '1' to enable interrupt for event STARTED</description>
118028 <description>Read: Disabled</description>
118033 <description>Read: Enabled</description>
118041 <description>Enable</description>
118048 <description>Write '1' to enable interrupt for event END</description>
118055 <description>Read: Disabled</description>
118060 <description>Read: Enabled</description>
118068 <description>Enable</description>
118075 <description>Write '1' to enable interrupt for event DONE</description>
118082 <description>Read: Disabled</description>
118087 <description>Read: Enabled</description>
118095 <description>Enable</description>
118102 <description>Write '1' to enable interrupt for event RESULTDONE</description>
118109 <description>Read: Disabled</description>
118114 <description>Read: Enabled</description>
118122 <description>Enable</description>
118129 <description>Write '1' to enable interrupt for event CALIBRATEDONE</description>
118136 <description>Read: Disabled</description>
118141 <description>Read: Enabled</description>
118149 <description>Enable</description>
118156 <description>Write '1' to enable interrupt for event STOPPED</description>
118163 <description>Read: Disabled</description>
118168 <description>Read: Enabled</description>
118176 <description>Enable</description>
118183 <description>Write '1' to enable interrupt for event CH0LIMITH</description>
118190 <description>Read: Disabled</description>
118195 <description>Read: Enabled</description>
118203 <description>Enable</description>
118210 <description>Write '1' to enable interrupt for event CH0LIMITL</description>
118217 <description>Read: Disabled</description>
118222 <description>Read: Enabled</description>
118230 <description>Enable</description>
118237 <description>Write '1' to enable interrupt for event CH1LIMITH</description>
118244 <description>Read: Disabled</description>
118249 <description>Read: Enabled</description>
118257 <description>Enable</description>
118264 <description>Write '1' to enable interrupt for event CH1LIMITL</description>
118271 <description>Read: Disabled</description>
118276 <description>Read: Enabled</description>
118284 <description>Enable</description>
118291 <description>Write '1' to enable interrupt for event CH2LIMITH</description>
118298 <description>Read: Disabled</description>
118303 <description>Read: Enabled</description>
118311 <description>Enable</description>
118318 <description>Write '1' to enable interrupt for event CH2LIMITL</description>
118325 <description>Read: Disabled</description>
118330 <description>Read: Enabled</description>
118338 <description>Enable</description>
118345 <description>Write '1' to enable interrupt for event CH3LIMITH</description>
118352 <description>Read: Disabled</description>
118357 <description>Read: Enabled</description>
118365 <description>Enable</description>
118372 <description>Write '1' to enable interrupt for event CH3LIMITL</description>
118379 <description>Read: Disabled</description>
118384 <description>Read: Enabled</description>
118392 <description>Enable</description>
118399 <description>Write '1' to enable interrupt for event CH4LIMITH</description>
118406 <description>Read: Disabled</description>
118411 <description>Read: Enabled</description>
118419 <description>Enable</description>
118426 <description>Write '1' to enable interrupt for event CH4LIMITL</description>
118433 <description>Read: Disabled</description>
118438 <description>Read: Enabled</description>
118446 <description>Enable</description>
118453 <description>Write '1' to enable interrupt for event CH5LIMITH</description>
118460 <description>Read: Disabled</description>
118465 <description>Read: Enabled</description>
118473 <description>Enable</description>
118480 <description>Write '1' to enable interrupt for event CH5LIMITL</description>
118487 <description>Read: Disabled</description>
118492 <description>Read: Enabled</description>
118500 <description>Enable</description>
118507 <description>Write '1' to enable interrupt for event CH6LIMITH</description>
118514 <description>Read: Disabled</description>
118519 <description>Read: Enabled</description>
118527 <description>Enable</description>
118534 <description>Write '1' to enable interrupt for event CH6LIMITL</description>
118541 <description>Read: Disabled</description>
118546 <description>Read: Enabled</description>
118554 <description>Enable</description>
118561 <description>Write '1' to enable interrupt for event CH7LIMITH</description>
118568 <description>Read: Disabled</description>
118573 <description>Read: Enabled</description>
118581 <description>Enable</description>
118588 <description>Write '1' to enable interrupt for event CH7LIMITL</description>
118595 <description>Read: Disabled</description>
118600 <description>Read: Enabled</description>
118608 <description>Enable</description>
118617 <description>Disable interrupt</description>
118625 <description>Write '1' to disable interrupt for event STARTED</description>
118632 <description>Read: Disabled</description>
118637 <description>Read: Enabled</description>
118645 <description>Disable</description>
118652 <description>Write '1' to disable interrupt for event END</description>
118659 <description>Read: Disabled</description>
118664 <description>Read: Enabled</description>
118672 <description>Disable</description>
118679 <description>Write '1' to disable interrupt for event DONE</description>
118686 <description>Read: Disabled</description>
118691 <description>Read: Enabled</description>
118699 <description>Disable</description>
118706 <description>Write '1' to disable interrupt for event RESULTDONE</description>
118713 <description>Read: Disabled</description>
118718 <description>Read: Enabled</description>
118726 <description>Disable</description>
118733 <description>Write '1' to disable interrupt for event CALIBRATEDONE</description>
118740 <description>Read: Disabled</description>
118745 <description>Read: Enabled</description>
118753 <description>Disable</description>
118760 <description>Write '1' to disable interrupt for event STOPPED</description>
118767 <description>Read: Disabled</description>
118772 <description>Read: Enabled</description>
118780 <description>Disable</description>
118787 <description>Write '1' to disable interrupt for event CH0LIMITH</description>
118794 <description>Read: Disabled</description>
118799 <description>Read: Enabled</description>
118807 <description>Disable</description>
118814 <description>Write '1' to disable interrupt for event CH0LIMITL</description>
118821 <description>Read: Disabled</description>
118826 <description>Read: Enabled</description>
118834 <description>Disable</description>
118841 <description>Write '1' to disable interrupt for event CH1LIMITH</description>
118848 <description>Read: Disabled</description>
118853 <description>Read: Enabled</description>
118861 <description>Disable</description>
118868 <description>Write '1' to disable interrupt for event CH1LIMITL</description>
118875 <description>Read: Disabled</description>
118880 <description>Read: Enabled</description>
118888 <description>Disable</description>
118895 <description>Write '1' to disable interrupt for event CH2LIMITH</description>
118902 <description>Read: Disabled</description>
118907 <description>Read: Enabled</description>
118915 <description>Disable</description>
118922 <description>Write '1' to disable interrupt for event CH2LIMITL</description>
118929 <description>Read: Disabled</description>
118934 <description>Read: Enabled</description>
118942 <description>Disable</description>
118949 <description>Write '1' to disable interrupt for event CH3LIMITH</description>
118956 <description>Read: Disabled</description>
118961 <description>Read: Enabled</description>
118969 <description>Disable</description>
118976 <description>Write '1' to disable interrupt for event CH3LIMITL</description>
118983 <description>Read: Disabled</description>
118988 <description>Read: Enabled</description>
118996 <description>Disable</description>
119003 <description>Write '1' to disable interrupt for event CH4LIMITH</description>
119010 <description>Read: Disabled</description>
119015 <description>Read: Enabled</description>
119023 <description>Disable</description>
119030 <description>Write '1' to disable interrupt for event CH4LIMITL</description>
119037 <description>Read: Disabled</description>
119042 <description>Read: Enabled</description>
119050 <description>Disable</description>
119057 <description>Write '1' to disable interrupt for event CH5LIMITH</description>
119064 <description>Read: Disabled</description>
119069 <description>Read: Enabled</description>
119077 <description>Disable</description>
119084 <description>Write '1' to disable interrupt for event CH5LIMITL</description>
119091 <description>Read: Disabled</description>
119096 <description>Read: Enabled</description>
119104 <description>Disable</description>
119111 <description>Write '1' to disable interrupt for event CH6LIMITH</description>
119118 <description>Read: Disabled</description>
119123 <description>Read: Enabled</description>
119131 <description>Disable</description>
119138 <description>Write '1' to disable interrupt for event CH6LIMITL</description>
119145 <description>Read: Disabled</description>
119150 <description>Read: Enabled</description>
119158 <description>Disable</description>
119165 <description>Write '1' to disable interrupt for event CH7LIMITH</description>
119172 <description>Read: Disabled</description>
119177 <description>Read: Enabled</description>
119185 <description>Disable</description>
119192 <description>Write '1' to disable interrupt for event CH7LIMITL</description>
119199 <description>Read: Disabled</description>
119204 <description>Read: Enabled</description>
119212 <description>Disable</description>
119221 <description>Status</description>
119229 <description>Status</description>
119235 <description>ADC is ready. No on-going conversion.</description>
119240 <description>ADC is busy. Single conversion in progress.</description>
119249 <description>Unspecified</description>
119257 <description>Description collection: Linearity calibration coefficient</description>
119265 <description>value</description>
119274 <description>Enable or disable ADC</description>
119282 <description>Enable or disable ADC</description>
119288 <description>Disable ADC</description>
119293 <description>Enable ADC</description>
119304 <description>Unspecified</description>
119310 <description>Description cluster: Input positive pin selection for CH[n]</description>
119318 <description>GPIO pin selection.</description>
119324 <description>GPIO port selection</description>
119330 <description>Connection</description>
119336 <description>Not connected</description>
119341 <description>Select analog input</description>
119350 <description>Description cluster: Input negative pin selection for CH[n]</description>
119358 <description>GPIO pin selection.</description>
119364 <description>GPIO Port selection</description>
119370 <description>Connection</description>
119376 <description>Not connected</description>
119381 <description>Select analog input</description>
119390 <description>Description cluster: Input configuration for CH[n]</description>
119398 <description>Gain control</description>
119404 <description>2/3</description>
119409 <description>1</description>
119414 <description>2</description>
119419 <description>4</description>
119424 <description>1/2</description>
119431 <description>Enable burst mode</description>
119437 <description>Burst mode is disabled (normal operation)</description>
119442 …<description>Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, …
119449 <description>Reference control</description>
119455 <description>Internal reference (1.024 V)</description>
119460 <description>External reference given at PADC_EXT_REF_1V2</description>
119467 <description>Enable differential mode</description>
119473 …<description>Single ended, PSELN will be ignored, negative input to ADC shorted to GND</descriptio…
119478 <description>Differential</description>
119485 …<description>Acquisition time, the time the ADC uses to sample the input voltage. Resulting acquis…
119491 … <description>Conversion time. Resulting conversion time is ((TCONV+1) x 250 ns)</description>
119499 … <description>Description cluster: High/low limits for event monitoring a channel</description>
119507 <description>Low level limit</description>
119513 <description>High level limit</description>
119522 <description>Resolution configuration</description>
119530 <description>Set the resolution</description>
119536 <description>8 bit</description>
119541 <description>10 bit</description>
119546 <description>12 bit</description>
119551 <description>14 bit</description>
119560 …description>Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTIO…
119568 <description>Oversample control</description>
119574 <description>Bypass oversampling</description>
119579 <description>Oversample 2x</description>
119584 <description>Oversample 4x</description>
119589 <description>Oversample 8x</description>
119594 <description>Oversample 16x</description>
119599 <description>Oversample 32x</description>
119604 <description>Oversample 64x</description>
119609 <description>Oversample 128x</description>
119614 <description>Oversample 256x</description>
119623 <description>Controls normal or continuous sample rate</description>
119631 <description>Capture and compare value. Sample rate is 16 MHz/CC</description>
119637 <description>Select mode for sample rate control</description>
119643 <description>Rate is controlled from SAMPLE task</description>
119648 … <description>Rate is controlled from local timer (use CC to control the rate)</description>
119657 <description>RESULT EasyDMA channel</description>
119663 <description>Data pointer</description>
119671 <description>Data pointer</description>
119679 <description>Maximum number of buffer bytes to transfer</description>
119687 <description>Maximum number of buffer bytes to transfer</description>
119695 …<description>Number of buffer bytes transferred since last START, updated after the END or STOPPED…
119703 …<description>Number of buffer bytes transferred since last START, updated after the END or STOPPED…
119711 …<description>Number of buffer bytes transferred since last START, continuously updated</descriptio…
119719 …<description>Number of buffer bytes transferred since last START, continuously updated.</descripti…
119728 <description>Enable noise shaping</description>
119736 <description>Enable noise shaping</description>
119742 … <description>Disable noiseshaping. Oversampling based on accumulate and average.</description>
119747 …description>Noiseshaping and decimating. Larger passband. Provides a 100kS/s cut off frequency, 8x…
119752 …description>Noiseshaping and decimating. Smaller passband. Recommended resolution setting is 14 bi…
119763 <description>Comparator</description>
119781 <description>Start comparator</description>
119789 <description>Start comparator</description>
119795 <description>Trigger task</description>
119804 <description>Stop comparator</description>
119812 <description>Stop comparator</description>
119818 <description>Trigger task</description>
119827 …<description>Sample comparator value. This task requires that COMP has been started by the START T…
119835 …<description>Sample comparator value. This task requires that COMP has been started by the START T…
119841 <description>Trigger task</description>
119850 <description>Subscribe configuration for task START</description>
119858 <description>DPPI channel that task START will subscribe to</description>
119869 <description>Disable subscription</description>
119874 <description>Enable subscription</description>
119883 <description>Subscribe configuration for task STOP</description>
119891 <description>DPPI channel that task STOP will subscribe to</description>
119902 <description>Disable subscription</description>
119907 <description>Enable subscription</description>
119916 <description>Subscribe configuration for task SAMPLE</description>
119924 <description>DPPI channel that task SAMPLE will subscribe to</description>
119935 <description>Disable subscription</description>
119940 <description>Enable subscription</description>
119949 <description>COMP is ready and output is valid</description>
119957 <description>COMP is ready and output is valid</description>
119963 <description>Event not generated</description>
119968 <description>Event generated</description>
119977 <description>Downward crossing</description>
119985 <description>Downward crossing</description>
119991 <description>Event not generated</description>
119996 <description>Event generated</description>
120005 <description>Upward crossing</description>
120013 <description>Upward crossing</description>
120019 <description>Event not generated</description>
120024 <description>Event generated</description>
120033 <description>Downward or upward crossing</description>
120041 <description>Downward or upward crossing</description>
120047 <description>Event not generated</description>
120052 <description>Event generated</description>
120061 <description>Publish configuration for event READY</description>
120069 <description>DPPI channel that event READY will publish to</description>
120080 <description>Disable publishing</description>
120085 <description>Enable publishing</description>
120094 <description>Publish configuration for event DOWN</description>
120102 <description>DPPI channel that event DOWN will publish to</description>
120113 <description>Disable publishing</description>
120118 <description>Enable publishing</description>
120127 <description>Publish configuration for event UP</description>
120135 <description>DPPI channel that event UP will publish to</description>
120146 <description>Disable publishing</description>
120151 <description>Enable publishing</description>
120160 <description>Publish configuration for event CROSS</description>
120168 <description>DPPI channel that event CROSS will publish to</description>
120179 <description>Disable publishing</description>
120184 <description>Enable publishing</description>
120193 <description>Shortcuts between local events and tasks</description>
120201 <description>Shortcut between event READY and task SAMPLE</description>
120207 <description>Disable shortcut</description>
120212 <description>Enable shortcut</description>
120219 <description>Shortcut between event READY and task STOP</description>
120225 <description>Disable shortcut</description>
120230 <description>Enable shortcut</description>
120237 <description>Shortcut between event DOWN and task STOP</description>
120243 <description>Disable shortcut</description>
120248 <description>Enable shortcut</description>
120255 <description>Shortcut between event UP and task STOP</description>
120261 <description>Disable shortcut</description>
120266 <description>Enable shortcut</description>
120273 <description>Shortcut between event CROSS and task STOP</description>
120279 <description>Disable shortcut</description>
120284 <description>Enable shortcut</description>
120293 <description>Enable or disable interrupt</description>
120301 <description>Enable or disable interrupt for event READY</description>
120307 <description>Disable</description>
120312 <description>Enable</description>
120319 <description>Enable or disable interrupt for event DOWN</description>
120325 <description>Disable</description>
120330 <description>Enable</description>
120337 <description>Enable or disable interrupt for event UP</description>
120343 <description>Disable</description>
120348 <description>Enable</description>
120355 <description>Enable or disable interrupt for event CROSS</description>
120361 <description>Disable</description>
120366 <description>Enable</description>
120375 <description>Enable interrupt</description>
120383 <description>Write '1' to enable interrupt for event READY</description>
120390 <description>Read: Disabled</description>
120395 <description>Read: Enabled</description>
120403 <description>Enable</description>
120410 <description>Write '1' to enable interrupt for event DOWN</description>
120417 <description>Read: Disabled</description>
120422 <description>Read: Enabled</description>
120430 <description>Enable</description>
120437 <description>Write '1' to enable interrupt for event UP</description>
120444 <description>Read: Disabled</description>
120449 <description>Read: Enabled</description>
120457 <description>Enable</description>
120464 <description>Write '1' to enable interrupt for event CROSS</description>
120471 <description>Read: Disabled</description>
120476 <description>Read: Enabled</description>
120484 <description>Enable</description>
120493 <description>Disable interrupt</description>
120501 <description>Write '1' to disable interrupt for event READY</description>
120508 <description>Read: Disabled</description>
120513 <description>Read: Enabled</description>
120521 <description>Disable</description>
120528 <description>Write '1' to disable interrupt for event DOWN</description>
120535 <description>Read: Disabled</description>
120540 <description>Read: Enabled</description>
120548 <description>Disable</description>
120555 <description>Write '1' to disable interrupt for event UP</description>
120562 <description>Read: Disabled</description>
120567 <description>Read: Enabled</description>
120575 <description>Disable</description>
120582 <description>Write '1' to disable interrupt for event CROSS</description>
120589 <description>Read: Disabled</description>
120594 <description>Read: Enabled</description>
120602 <description>Disable</description>
120611 <description>Pending interrupts</description>
120619 <description>Read pending status of interrupt for event READY</description>
120626 <description>Read: Not pending</description>
120631 <description>Read: Pending</description>
120638 <description>Read pending status of interrupt for event DOWN</description>
120645 <description>Read: Not pending</description>
120650 <description>Read: Pending</description>
120657 <description>Read pending status of interrupt for event UP</description>
120664 <description>Read: Not pending</description>
120669 <description>Read: Pending</description>
120676 <description>Read pending status of interrupt for event CROSS</description>
120683 <description>Read: Not pending</description>
120688 <description>Read: Pending</description>
120697 <description>Compare result</description>
120705 <description>Result of last compare. Decision point SAMPLE task.</description>
120711 … <description>Input voltage is below the threshold (VIN+ &lt; VIN-)</description>
120716 … <description>Input voltage is above the threshold (VIN+ &gt; VIN-)</description>
120725 <description>COMP enable</description>
120733 <description>Enable or disable COMP</description>
120739 <description>Disable</description>
120744 <description>Enable</description>
120753 <description>Pin select</description>
120761 <description>Analog pin select</description>
120767 <description>GPIO Port selection</description>
120775 <description>Reference source select for single-ended mode</description>
120783 <description>Reference select</description>
120789 <description>VREF = internal 1.2 V reference</description>
120794 <description>VREF = internal 1.8 V reference</description>
120799 <description>VREF = AREF</description>
120808 <description>External reference select</description>
120816 <description>External analog reference pin select</description>
120822 <description>GPIO Port selection</description>
120830 <description>Threshold configuration for hysteresis unit</description>
120838 <description>VDOWN = (THDOWN+1)/64*VREF</description>
120844 <description>VUP = (THUP+1)/64*VREF</description>
120852 <description>Mode configuration</description>
120860 <description>Speed and power modes</description>
120866 <description>Low-power mode</description>
120871 <description>High-speed mode</description>
120878 <description>Main operation modes</description>
120884 <description>Single-ended mode</description>
120889 <description>Differential mode</description>
120898 <description>Comparator hysteresis enable</description>
120906 <description>Comparator hysteresis</description>
120912 <description>Comparator hysteresis disabled</description>
120917 <description>Comparator hysteresis enabled</description>
120926 <description>Current source select on analog input</description>
120934 <description>Current source select on analog input</description>
120940 <description>Current source disabled</description>
120945 <description>Current source enabled (+/- 2.5 uA)</description>
120950 <description>Current source enabled (+/- 5 uA)</description>
120955 <description>Current source enabled (+/- 10 uA)</description>
120964 <description>Trim internal band gap reference</description>
120972 <description>Trimming value in 2's complement</description>
120982 <description>Low-power comparator</description>
121001 <description>Start comparator</description>
121009 <description>Start comparator</description>
121015 <description>Trigger task</description>
121024 <description>Stop comparator</description>
121032 <description>Stop comparator</description>
121038 <description>Trigger task</description>
121047 …<description>Sample comparator value. This task requires that LPCOMP has been started by the START…
121055 …<description>Sample comparator value. This task requires that LPCOMP has been started by the START…
121061 <description>Trigger task</description>
121070 <description>Subscribe configuration for task START</description>
121078 <description>DPPI channel that task START will subscribe to</description>
121089 <description>Disable subscription</description>
121094 <description>Enable subscription</description>
121103 <description>Subscribe configuration for task STOP</description>
121111 <description>DPPI channel that task STOP will subscribe to</description>
121122 <description>Disable subscription</description>
121127 <description>Enable subscription</description>
121136 <description>Subscribe configuration for task SAMPLE</description>
121144 <description>DPPI channel that task SAMPLE will subscribe to</description>
121155 <description>Disable subscription</description>
121160 <description>Enable subscription</description>
121169 <description>LPCOMP is ready and output is valid</description>
121177 <description>LPCOMP is ready and output is valid</description>
121183 <description>Event not generated</description>
121188 <description>Event generated</description>
121197 <description>Downward crossing</description>
121205 <description>Downward crossing</description>
121211 <description>Event not generated</description>
121216 <description>Event generated</description>
121225 <description>Upward crossing</description>
121233 <description>Upward crossing</description>
121239 <description>Event not generated</description>
121244 <description>Event generated</description>
121253 <description>Downward or upward crossing</description>
121261 <description>Downward or upward crossing</description>
121267 <description>Event not generated</description>
121272 <description>Event generated</description>
121281 <description>Publish configuration for event READY</description>
121289 <description>DPPI channel that event READY will publish to</description>
121300 <description>Disable publishing</description>
121305 <description>Enable publishing</description>
121314 <description>Publish configuration for event DOWN</description>
121322 <description>DPPI channel that event DOWN will publish to</description>
121333 <description>Disable publishing</description>
121338 <description>Enable publishing</description>
121347 <description>Publish configuration for event UP</description>
121355 <description>DPPI channel that event UP will publish to</description>
121366 <description>Disable publishing</description>
121371 <description>Enable publishing</description>
121380 <description>Publish configuration for event CROSS</description>
121388 <description>DPPI channel that event CROSS will publish to</description>
121399 <description>Disable publishing</description>
121404 <description>Enable publishing</description>
121413 <description>Shortcuts between local events and tasks</description>
121421 <description>Shortcut between event READY and task SAMPLE</description>
121427 <description>Disable shortcut</description>
121432 <description>Enable shortcut</description>
121439 <description>Shortcut between event READY and task STOP</description>
121445 <description>Disable shortcut</description>
121450 <description>Enable shortcut</description>
121457 <description>Shortcut between event DOWN and task STOP</description>
121463 <description>Disable shortcut</description>
121468 <description>Enable shortcut</description>
121475 <description>Shortcut between event UP and task STOP</description>
121481 <description>Disable shortcut</description>
121486 <description>Enable shortcut</description>
121493 <description>Shortcut between event CROSS and task STOP</description>
121499 <description>Disable shortcut</description>
121504 <description>Enable shortcut</description>
121513 <description>Enable or disable interrupt</description>
121521 <description>Enable or disable interrupt for event READY</description>
121527 <description>Disable</description>
121532 <description>Enable</description>
121539 <description>Enable or disable interrupt for event DOWN</description>
121545 <description>Disable</description>
121550 <description>Enable</description>
121557 <description>Enable or disable interrupt for event UP</description>
121563 <description>Disable</description>
121568 <description>Enable</description>
121575 <description>Enable or disable interrupt for event CROSS</description>
121581 <description>Disable</description>
121586 <description>Enable</description>
121595 <description>Enable interrupt</description>
121603 <description>Write '1' to enable interrupt for event READY</description>
121610 <description>Read: Disabled</description>
121615 <description>Read: Enabled</description>
121623 <description>Enable</description>
121630 <description>Write '1' to enable interrupt for event DOWN</description>
121637 <description>Read: Disabled</description>
121642 <description>Read: Enabled</description>
121650 <description>Enable</description>
121657 <description>Write '1' to enable interrupt for event UP</description>
121664 <description>Read: Disabled</description>
121669 <description>Read: Enabled</description>
121677 <description>Enable</description>
121684 <description>Write '1' to enable interrupt for event CROSS</description>
121691 <description>Read: Disabled</description>
121696 <description>Read: Enabled</description>
121704 <description>Enable</description>
121713 <description>Disable interrupt</description>
121721 <description>Write '1' to disable interrupt for event READY</description>
121728 <description>Read: Disabled</description>
121733 <description>Read: Enabled</description>
121741 <description>Disable</description>
121748 <description>Write '1' to disable interrupt for event DOWN</description>
121755 <description>Read: Disabled</description>
121760 <description>Read: Enabled</description>
121768 <description>Disable</description>
121775 <description>Write '1' to disable interrupt for event UP</description>
121782 <description>Read: Disabled</description>
121787 <description>Read: Enabled</description>
121795 <description>Disable</description>
121802 <description>Write '1' to disable interrupt for event CROSS</description>
121809 <description>Read: Disabled</description>
121814 <description>Read: Enabled</description>
121822 <description>Disable</description>
121831 <description>Pending interrupts</description>
121839 <description>Read pending status of interrupt for event READY</description>
121846 <description>Read: Not pending</description>
121851 <description>Read: Pending</description>
121858 <description>Read pending status of interrupt for event DOWN</description>
121865 <description>Read: Not pending</description>
121870 <description>Read: Pending</description>
121877 <description>Read pending status of interrupt for event UP</description>
121884 <description>Read: Not pending</description>
121889 <description>Read: Pending</description>
121896 <description>Read pending status of interrupt for event CROSS</description>
121903 <description>Read: Not pending</description>
121908 <description>Read: Pending</description>
121917 <description>Compare result</description>
121925 <description>Result of last compare. Decision point SAMPLE task.</description>
121931 … <description>Input voltage is below the reference threshold (VIN+ &lt; VIN-)</description>
121936 … <description>Input voltage is above the reference threshold (VIN+ &gt; VIN-)</description>
121945 <description>Enable LPCOMP</description>
121953 <description>Enable or disable LPCOMP</description>
121959 <description>Disable</description>
121964 <description>Enable</description>
121973 <description>Input pin select</description>
121981 <description>Analog pin select</description>
121987 <description>GPIO Port selection</description>
121995 <description>Reference select</description>
122003 <description>Reference select</description>
122009 <description>VDD * 1/8 selected as reference</description>
122014 <description>VDD * 2/8 selected as reference</description>
122019 <description>VDD * 3/8 selected as reference</description>
122024 <description>VDD * 4/8 selected as reference</description>
122029 <description>VDD * 5/8 selected as reference</description>
122034 <description>VDD * 6/8 selected as reference</description>
122039 <description>VDD * 7/8 selected as reference</description>
122044 <description>External analog reference selected</description>
122049 <description>VDD * 1/16 selected as reference</description>
122054 <description>VDD * 3/16 selected as reference</description>
122059 <description>VDD * 5/16 selected as reference</description>
122064 <description>VDD * 7/16 selected as reference</description>
122069 <description>VDD * 9/16 selected as reference</description>
122074 <description>VDD * 11/16 selected as reference</description>
122079 <description>VDD * 13/16 selected as reference</description>
122084 <description>VDD * 15/16 selected as reference</description>
122093 <description>External reference select</description>
122101 <description>External analog reference pin select</description>
122107 <description>GPIO Port selection</description>
122115 <description>Analog detect configuration</description>
122123 <description>Analog detect configuration</description>
122129 …<description>Generate ANADETECT on crossing, both upward crossing and downward crossing</descripti…
122134 <description>Generate ANADETECT on upward crossing only</description>
122139 <description>Generate ANADETECT on downward crossing only</description>
122148 <description>Comparator hysteresis enable</description>
122156 <description>Comparator hysteresis enable</description>
122162 <description>Comparator hysteresis disabled</description>
122167 <description>Comparator hysteresis enabled</description>
122178 <description>Temperature Sensor</description>
122196 <description>Start temperature measurement</description>
122204 <description>Start temperature measurement</description>
122210 <description>Trigger task</description>
122219 <description>Stop temperature measurement</description>
122227 <description>Stop temperature measurement</description>
122233 <description>Trigger task</description>
122242 <description>Subscribe configuration for task START</description>
122250 <description>DPPI channel that task START will subscribe to</description>
122261 <description>Disable subscription</description>
122266 <description>Enable subscription</description>
122275 <description>Subscribe configuration for task STOP</description>
122283 <description>DPPI channel that task STOP will subscribe to</description>
122294 <description>Disable subscription</description>
122299 <description>Enable subscription</description>
122308 <description>Temperature measurement complete, data ready</description>
122316 <description>Temperature measurement complete, data ready</description>
122322 <description>Event not generated</description>
122327 <description>Event generated</description>
122336 <description>Publish configuration for event DATARDY</description>
122344 <description>DPPI channel that event DATARDY will publish to</description>
122355 <description>Disable publishing</description>
122360 <description>Enable publishing</description>
122369 <description>Enable interrupt</description>
122377 <description>Write '1' to enable interrupt for event DATARDY</description>
122384 <description>Read: Disabled</description>
122389 <description>Read: Enabled</description>
122397 <description>Enable</description>
122406 <description>Disable interrupt</description>
122414 <description>Write '1' to disable interrupt for event DATARDY</description>
122421 <description>Read: Disabled</description>
122426 <description>Read: Enabled</description>
122434 <description>Disable</description>
122443 <description>Temperature in degC (0.25deg steps)</description>
122452 <description>Temperature in degC (0.25deg steps)</description>
122460 <description>Slope of 1st piece wise linear function</description>
122468 <description>Slope of 1st piece wise linear function</description>
122476 <description>Slope of 2nd piece wise linear function</description>
122484 <description>Slope of 2nd piece wise linear function</description>
122492 <description>Slope of 3rd piece wise linear function</description>
122500 <description>Slope of 3rd piece wise linear function</description>
122508 <description>Slope of 4th piece wise linear function</description>
122516 <description>Slope of 4th piece wise linear function</description>
122524 <description>Slope of 5th piece wise linear function</description>
122532 <description>Slope of 5th piece wise linear function</description>
122540 <description>Slope of 6th piece wise linear function</description>
122548 <description>Slope of 6th piece wise linear function</description>
122556 <description>Slope of 7th piece wise linear function</description>
122564 <description>Slope of 7th piece wise linear function</description>
122572 <description>y-intercept of 1st piece wise linear function</description>
122580 <description>y-intercept of 1st piece wise linear function</description>
122588 <description>y-intercept of 2nd piece wise linear function</description>
122596 <description>y-intercept of 2nd piece wise linear function</description>
122604 <description>y-intercept of 3rd piece wise linear function</description>
122612 <description>y-intercept of 3rd piece wise linear function</description>
122620 <description>y-intercept of 4th piece wise linear function</description>
122628 <description>y-intercept of 4th piece wise linear function</description>
122636 <description>y-intercept of 5th piece wise linear function</description>
122644 <description>y-intercept of 5th piece wise linear function</description>
122652 <description>y-intercept of 6th piece wise linear function</description>
122660 <description>y-intercept of 6th piece wise linear function</description>
122668 <description>y-intercept of 7th piece wise linear function</description>
122676 <description>y-intercept of 7th piece wise linear function</description>
122684 <description>End point of 1st piece wise linear function</description>
122692 <description>End point of 1st piece wise linear function</description>
122700 <description>End point of 2nd piece wise linear function</description>
122708 <description>End point of 2nd piece wise linear function</description>
122716 <description>End point of 3rd piece wise linear function</description>
122724 <description>End point of 3rd piece wise linear function</description>
122732 <description>End point of 4th piece wise linear function</description>
122740 <description>End point of 4th piece wise linear function</description>
122748 <description>End point of 5th piece wise linear function</description>
122756 <description>End point of 5th piece wise linear function</description>
122764 <description>End point of 6th piece wise linear function</description>
122772 <description>End point of 6th piece wise linear function</description>
122782 <description>NFC-A compatible radio NFC-A compatible radio</description>
122800 …<description>Activate NFCT peripheral for incoming and outgoing frames, change state to activated<…
122808 …<description>Activate NFCT peripheral for incoming and outgoing frames, change state to activated<…
122814 <description>Trigger task</description>
122823 <description>Disable NFCT peripheral</description>
122831 <description>Disable NFCT peripheral</description>
122837 <description>Trigger task</description>
122846 <description>Enable NFC sense field mode, change state to sense mode</description>
122854 <description>Enable NFC sense field mode, change state to sense mode</description>
122860 <description>Trigger task</description>
122869 … <description>Start transmission of an outgoing frame, change state to transmit</description>
122877 … <description>Start transmission of an outgoing frame, change state to transmit</description>
122883 <description>Trigger task</description>
122892 <description>Stops an issued transmission of a frame</description>
122900 <description>Stops an issued transmission of a frame</description>
122906 <description>Trigger task</description>
122915 <description>Initializes the EasyDMA for receive.</description>
122923 <description>Initializes the EasyDMA for receive.</description>
122929 <description>Trigger task</description>
122938 <description>Force state machine to IDLE state</description>
122946 <description>Force state machine to IDLE state</description>
122952 <description>Trigger task</description>
122961 <description>Force state machine to SLEEP_A state</description>
122969 <description>Force state machine to SLEEP_A state</description>
122975 <description>Trigger task</description>
122984 <description>Subscribe configuration for task ACTIVATE</description>
122992 <description>DPPI channel that task ACTIVATE will subscribe to</description>
123003 <description>Disable subscription</description>
123008 <description>Enable subscription</description>
123017 <description>Subscribe configuration for task DISABLE</description>
123025 <description>DPPI channel that task DISABLE will subscribe to</description>
123036 <description>Disable subscription</description>
123041 <description>Enable subscription</description>
123050 <description>Subscribe configuration for task SENSE</description>
123058 <description>DPPI channel that task SENSE will subscribe to</description>
123069 <description>Disable subscription</description>
123074 <description>Enable subscription</description>
123083 <description>Subscribe configuration for task STARTTX</description>
123091 <description>DPPI channel that task STARTTX will subscribe to</description>
123102 <description>Disable subscription</description>
123107 <description>Enable subscription</description>
123116 <description>Subscribe configuration for task STOPTX</description>
123124 <description>DPPI channel that task STOPTX will subscribe to</description>
123135 <description>Disable subscription</description>
123140 <description>Enable subscription</description>
123149 <description>Subscribe configuration for task ENABLERXDATA</description>
123157 <description>DPPI channel that task ENABLERXDATA will subscribe to</description>
123168 <description>Disable subscription</description>
123173 <description>Enable subscription</description>
123182 <description>Subscribe configuration for task GOIDLE</description>
123190 <description>DPPI channel that task GOIDLE will subscribe to</description>
123201 <description>Disable subscription</description>
123206 <description>Enable subscription</description>
123215 <description>Subscribe configuration for task GOSLEEP</description>
123223 <description>DPPI channel that task GOSLEEP will subscribe to</description>
123234 <description>Disable subscription</description>
123239 <description>Enable subscription</description>
123248 <description>The NFCT peripheral is ready to receive and send frames</description>
123256 <description>The NFCT peripheral is ready to receive and send frames</description>
123262 <description>Event not generated</description>
123267 <description>Event generated</description>
123276 <description>Remote NFC field detected</description>
123284 <description>Remote NFC field detected</description>
123290 <description>Event not generated</description>
123295 <description>Event generated</description>
123304 <description>Remote NFC field lost</description>
123312 <description>Remote NFC field lost</description>
123318 <description>Event not generated</description>
123323 <description>Event generated</description>
123332 <description>Marks the start of the first symbol of a transmitted frame</description>
123340 <description>Marks the start of the first symbol of a transmitted frame</description>
123346 <description>Event not generated</description>
123351 <description>Event generated</description>
123360 <description>Marks the end of the last transmitted on-air symbol of a frame</description>
123368 … <description>Marks the end of the last transmitted on-air symbol of a frame</description>
123374 <description>Event not generated</description>
123379 <description>Event generated</description>
123388 <description>Marks the end of the first symbol of a received frame</description>
123396 <description>Marks the end of the first symbol of a received frame</description>
123402 <description>Event not generated</description>
123407 <description>Event generated</description>
123416 …<description>Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has …
123424 …<description>Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has …
123430 <description>Event not generated</description>
123435 <description>Event generated</description>
123444 …<description>NFC error reported. The ERRORSTATUS register contains details on the source of the er…
123452 …<description>NFC error reported. The ERRORSTATUS register contains details on the source of the er…
123458 <description>Event not generated</description>
123463 <description>Event generated</description>
123472 …<description>NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the sour…
123480 …<description>NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the sour…
123486 <description>Event not generated</description>
123491 <description>Event generated</description>
123500 … <description>RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full.</description>
123508 … <description>RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full.</description>
123514 <description>Event not generated</description>
123519 <description>Event generated</description>
123528 …<description>Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer<…
123536 …<description>Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer<…
123542 <description>Event not generated</description>
123547 <description>Event generated</description>
123556 <description>Auto collision resolution process has started</description>
123564 <description>Auto collision resolution process has started</description>
123570 <description>Event not generated</description>
123575 <description>Event generated</description>
123584 <description>NFC auto collision resolution error reported.</description>
123592 <description>NFC auto collision resolution error reported.</description>
123598 <description>Event not generated</description>
123603 <description>Event generated</description>
123612 <description>NFC auto collision resolution successfully completed</description>
123620 <description>NFC auto collision resolution successfully completed</description>
123626 <description>Event not generated</description>
123631 <description>Event generated</description>
123640 <description>EasyDMA is ready to receive or send frames.</description>
123648 <description>EasyDMA is ready to receive or send frames.</description>
123654 <description>Event not generated</description>
123659 <description>Event generated</description>
123668 <description>Publish configuration for event READY</description>
123676 <description>DPPI channel that event READY will publish to</description>
123687 <description>Disable publishing</description>
123692 <description>Enable publishing</description>
123701 <description>Publish configuration for event FIELDDETECTED</description>
123709 <description>DPPI channel that event FIELDDETECTED will publish to</description>
123720 <description>Disable publishing</description>
123725 <description>Enable publishing</description>
123734 <description>Publish configuration for event FIELDLOST</description>
123742 <description>DPPI channel that event FIELDLOST will publish to</description>
123753 <description>Disable publishing</description>
123758 <description>Enable publishing</description>
123767 <description>Publish configuration for event TXFRAMESTART</description>
123775 <description>DPPI channel that event TXFRAMESTART will publish to</description>
123786 <description>Disable publishing</description>
123791 <description>Enable publishing</description>
123800 <description>Publish configuration for event TXFRAMEEND</description>
123808 <description>DPPI channel that event TXFRAMEEND will publish to</description>
123819 <description>Disable publishing</description>
123824 <description>Enable publishing</description>
123833 <description>Publish configuration for event RXFRAMESTART</description>
123841 <description>DPPI channel that event RXFRAMESTART will publish to</description>
123852 <description>Disable publishing</description>
123857 <description>Enable publishing</description>
123866 <description>Publish configuration for event RXFRAMEEND</description>
123874 <description>DPPI channel that event RXFRAMEEND will publish to</description>
123885 <description>Disable publishing</description>
123890 <description>Enable publishing</description>
123899 <description>Publish configuration for event ERROR</description>
123907 <description>DPPI channel that event ERROR will publish to</description>
123918 <description>Disable publishing</description>
123923 <description>Enable publishing</description>
123932 <description>Publish configuration for event RXERROR</description>
123940 <description>DPPI channel that event RXERROR will publish to</description>
123951 <description>Disable publishing</description>
123956 <description>Enable publishing</description>
123965 <description>Publish configuration for event ENDRX</description>
123973 <description>DPPI channel that event ENDRX will publish to</description>
123984 <description>Disable publishing</description>
123989 <description>Enable publishing</description>
123998 <description>Publish configuration for event ENDTX</description>
124006 <description>DPPI channel that event ENDTX will publish to</description>
124017 <description>Disable publishing</description>
124022 <description>Enable publishing</description>
124031 <description>Publish configuration for event AUTOCOLRESSTARTED</description>
124039 <description>DPPI channel that event AUTOCOLRESSTARTED will publish to</description>
124050 <description>Disable publishing</description>
124055 <description>Enable publishing</description>
124064 <description>Publish configuration for event COLLISION</description>
124072 <description>DPPI channel that event COLLISION will publish to</description>
124083 <description>Disable publishing</description>
124088 <description>Enable publishing</description>
124097 <description>Publish configuration for event SELECTED</description>
124105 <description>DPPI channel that event SELECTED will publish to</description>
124116 <description>Disable publishing</description>
124121 <description>Enable publishing</description>
124130 <description>Publish configuration for event STARTED</description>
124138 <description>DPPI channel that event STARTED will publish to</description>
124149 <description>Disable publishing</description>
124154 <description>Enable publishing</description>
124163 <description>Shortcuts between local events and tasks</description>
124171 <description>Shortcut between event FIELDDETECTED and task ACTIVATE</description>
124177 <description>Disable shortcut</description>
124182 <description>Enable shortcut</description>
124189 <description>Shortcut between event FIELDLOST and task SENSE</description>
124195 <description>Disable shortcut</description>
124200 <description>Enable shortcut</description>
124207 <description>Shortcut between event TXFRAMEEND and task ENABLERXDATA</description>
124213 <description>Disable shortcut</description>
124218 <description>Enable shortcut</description>
124227 <description>Enable or disable interrupt</description>
124235 <description>Enable or disable interrupt for event READY</description>
124241 <description>Disable</description>
124246 <description>Enable</description>
124253 <description>Enable or disable interrupt for event FIELDDETECTED</description>
124259 <description>Disable</description>
124264 <description>Enable</description>
124271 <description>Enable or disable interrupt for event FIELDLOST</description>
124277 <description>Disable</description>
124282 <description>Enable</description>
124289 <description>Enable or disable interrupt for event TXFRAMESTART</description>
124295 <description>Disable</description>
124300 <description>Enable</description>
124307 <description>Enable or disable interrupt for event TXFRAMEEND</description>
124313 <description>Disable</description>
124318 <description>Enable</description>
124325 <description>Enable or disable interrupt for event RXFRAMESTART</description>
124331 <description>Disable</description>
124336 <description>Enable</description>
124343 <description>Enable or disable interrupt for event RXFRAMEEND</description>
124349 <description>Disable</description>
124354 <description>Enable</description>
124361 <description>Enable or disable interrupt for event ERROR</description>
124367 <description>Disable</description>
124372 <description>Enable</description>
124379 <description>Enable or disable interrupt for event RXERROR</description>
124385 <description>Disable</description>
124390 <description>Enable</description>
124397 <description>Enable or disable interrupt for event ENDRX</description>
124403 <description>Disable</description>
124408 <description>Enable</description>
124415 <description>Enable or disable interrupt for event ENDTX</description>
124421 <description>Disable</description>
124426 <description>Enable</description>
124433 <description>Enable or disable interrupt for event AUTOCOLRESSTARTED</description>
124439 <description>Disable</description>
124444 <description>Enable</description>
124451 <description>Enable or disable interrupt for event COLLISION</description>
124457 <description>Disable</description>
124462 <description>Enable</description>
124469 <description>Enable or disable interrupt for event SELECTED</description>
124475 <description>Disable</description>
124480 <description>Enable</description>
124487 <description>Enable or disable interrupt for event STARTED</description>
124493 <description>Disable</description>
124498 <description>Enable</description>
124507 <description>Enable interrupt</description>
124515 <description>Write '1' to enable interrupt for event READY</description>
124522 <description>Read: Disabled</description>
124527 <description>Read: Enabled</description>
124535 <description>Enable</description>
124542 <description>Write '1' to enable interrupt for event FIELDDETECTED</description>
124549 <description>Read: Disabled</description>
124554 <description>Read: Enabled</description>
124562 <description>Enable</description>
124569 <description>Write '1' to enable interrupt for event FIELDLOST</description>
124576 <description>Read: Disabled</description>
124581 <description>Read: Enabled</description>
124589 <description>Enable</description>
124596 <description>Write '1' to enable interrupt for event TXFRAMESTART</description>
124603 <description>Read: Disabled</description>
124608 <description>Read: Enabled</description>
124616 <description>Enable</description>
124623 <description>Write '1' to enable interrupt for event TXFRAMEEND</description>
124630 <description>Read: Disabled</description>
124635 <description>Read: Enabled</description>
124643 <description>Enable</description>
124650 <description>Write '1' to enable interrupt for event RXFRAMESTART</description>
124657 <description>Read: Disabled</description>
124662 <description>Read: Enabled</description>
124670 <description>Enable</description>
124677 <description>Write '1' to enable interrupt for event RXFRAMEEND</description>
124684 <description>Read: Disabled</description>
124689 <description>Read: Enabled</description>
124697 <description>Enable</description>
124704 <description>Write '1' to enable interrupt for event ERROR</description>
124711 <description>Read: Disabled</description>
124716 <description>Read: Enabled</description>
124724 <description>Enable</description>
124731 <description>Write '1' to enable interrupt for event RXERROR</description>
124738 <description>Read: Disabled</description>
124743 <description>Read: Enabled</description>
124751 <description>Enable</description>
124758 <description>Write '1' to enable interrupt for event ENDRX</description>
124765 <description>Read: Disabled</description>
124770 <description>Read: Enabled</description>
124778 <description>Enable</description>
124785 <description>Write '1' to enable interrupt for event ENDTX</description>
124792 <description>Read: Disabled</description>
124797 <description>Read: Enabled</description>
124805 <description>Enable</description>
124812 <description>Write '1' to enable interrupt for event AUTOCOLRESSTARTED</description>
124819 <description>Read: Disabled</description>
124824 <description>Read: Enabled</description>
124832 <description>Enable</description>
124839 <description>Write '1' to enable interrupt for event COLLISION</description>
124846 <description>Read: Disabled</description>
124851 <description>Read: Enabled</description>
124859 <description>Enable</description>
124866 <description>Write '1' to enable interrupt for event SELECTED</description>
124873 <description>Read: Disabled</description>
124878 <description>Read: Enabled</description>
124886 <description>Enable</description>
124893 <description>Write '1' to enable interrupt for event STARTED</description>
124900 <description>Read: Disabled</description>
124905 <description>Read: Enabled</description>
124913 <description>Enable</description>
124922 <description>Disable interrupt</description>
124930 <description>Write '1' to disable interrupt for event READY</description>
124937 <description>Read: Disabled</description>
124942 <description>Read: Enabled</description>
124950 <description>Disable</description>
124957 <description>Write '1' to disable interrupt for event FIELDDETECTED</description>
124964 <description>Read: Disabled</description>
124969 <description>Read: Enabled</description>
124977 <description>Disable</description>
124984 <description>Write '1' to disable interrupt for event FIELDLOST</description>
124991 <description>Read: Disabled</description>
124996 <description>Read: Enabled</description>
125004 <description>Disable</description>
125011 <description>Write '1' to disable interrupt for event TXFRAMESTART</description>
125018 <description>Read: Disabled</description>
125023 <description>Read: Enabled</description>
125031 <description>Disable</description>
125038 <description>Write '1' to disable interrupt for event TXFRAMEEND</description>
125045 <description>Read: Disabled</description>
125050 <description>Read: Enabled</description>
125058 <description>Disable</description>
125065 <description>Write '1' to disable interrupt for event RXFRAMESTART</description>
125072 <description>Read: Disabled</description>
125077 <description>Read: Enabled</description>
125085 <description>Disable</description>
125092 <description>Write '1' to disable interrupt for event RXFRAMEEND</description>
125099 <description>Read: Disabled</description>
125104 <description>Read: Enabled</description>
125112 <description>Disable</description>
125119 <description>Write '1' to disable interrupt for event ERROR</description>
125126 <description>Read: Disabled</description>
125131 <description>Read: Enabled</description>
125139 <description>Disable</description>
125146 <description>Write '1' to disable interrupt for event RXERROR</description>
125153 <description>Read: Disabled</description>
125158 <description>Read: Enabled</description>
125166 <description>Disable</description>
125173 <description>Write '1' to disable interrupt for event ENDRX</description>
125180 <description>Read: Disabled</description>
125185 <description>Read: Enabled</description>
125193 <description>Disable</description>
125200 <description>Write '1' to disable interrupt for event ENDTX</description>
125207 <description>Read: Disabled</description>
125212 <description>Read: Enabled</description>
125220 <description>Disable</description>
125227 <description>Write '1' to disable interrupt for event AUTOCOLRESSTARTED</description>
125234 <description>Read: Disabled</description>
125239 <description>Read: Enabled</description>
125247 <description>Disable</description>
125254 <description>Write '1' to disable interrupt for event COLLISION</description>
125261 <description>Read: Disabled</description>
125266 <description>Read: Enabled</description>
125274 <description>Disable</description>
125281 <description>Write '1' to disable interrupt for event SELECTED</description>
125288 <description>Read: Disabled</description>
125293 <description>Read: Enabled</description>
125301 <description>Disable</description>
125308 <description>Write '1' to disable interrupt for event STARTED</description>
125315 <description>Read: Disabled</description>
125320 <description>Read: Enabled</description>
125328 <description>Disable</description>
125337 <description>NFC Error Status register</description>
125346 …<description>No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX</descrip…
125354 <description>Unspecified</description>
125360 <description>Result of last incoming frame</description>
125369 <description>No valid end of frame (EoF) detected</description>
125375 <description>Valid CRC detected</description>
125380 <description>CRC received does not match local check</description>
125387 <description>Parity status of received frame</description>
125393 <description>Frame received with parity OK</description>
125398 <description>Frame received with parity error</description>
125405 <description>Overrun detected</description>
125411 <description>No overrun detected</description>
125416 <description>Overrun error</description>
125426 <description>Current operating state of NFC tag</description>
125434 <description>NfcTag state</description>
125440 <description>Disabled or sense</description>
125445 <description>RampUp</description>
125450 <description>Idle</description>
125455 <description>Receive</description>
125460 <description>FrameDelay</description>
125465 <description>Transmit</description>
125474 <description>Sleep state during automatic collision resolution</description>
125482 … <description>Reflects the sleep state during automatic collision resolution. Set to IDLE
125484 GOSLEEP task.</description>
125490 <description>State is IDLE.</description>
125495 <description>State is SLEEP_A.</description>
125504 <description>Indicates the presence or not of a valid field</description>
125512 …<description>Indicates if a valid field is present. Available only in the activated state.</descri…
125518 <description>No valid field detected</description>
125523 <description>Valid field detected</description>
125530 <description>Indicates if the low level has locked to the field</description>
125536 <description>Not locked to field</description>
125541 <description>Locked to field</description>
125550 <description>Minimum frame delay</description>
125558 <description>Minimum frame delay in number of 13.56 MHz clock cycles</description>
125566 <description>Maximum frame delay</description>
125574 <description>Maximum frame delay in number of 13.56 MHz clock cycles</description>
125582 <description>Configuration register for the Frame Delay Timer</description>
125590 <description>Configuration register for the Frame Delay Timer</description>
125596 …<description>Transmission is independent of frame timer and will start when the STARTTX task is tr…
125601 … <description>Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX</description>
125606 <description>Frame is transmitted exactly at FRAMEDELAYMAX</description>
125611 …<description>Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX</descripti…
125620 <description>Packet pointer for TXD and RXD data storage in Data RAM</description>
125628 …<description>Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-align…
125636 … <description>Size of the RAM buffer allocated to TXD and RXD data storage each</description>
125644 … <description>Size of the RAM buffer allocated to TXD and RXD data storage each</description>
125652 <description>Unspecified</description>
125658 <description>Configuration of outgoing frames</description>
125666 <description>Indicates if parity is added to the frame</description>
125672 <description>Parity is not added to TX frames</description>
125677 <description>Parity is added to TX frames</description>
125684 <description>Discarding unused bits at start or end of a frame</description>
125690 <description>Unused bits are discarded at end of frame (EoF)</description>
125695 <description>Unused bits are discarded at start of frame (SoF)</description>
125702 <description>Adding SoF or not in TX frames</description>
125708 <description>SoF symbol not added</description>
125713 <description>SoF symbol added</description>
125720 <description>CRC mode for outgoing frames</description>
125726 <description>CRC is not added to the frame</description>
125731 …<description>16 bit CRC added to the frame based on all the data read from RAM that is used in the…
125740 <description>Size of outgoing frame</description>
125748 …<description>Number of bits in the last or first byte read from RAM that shall be included in the …
125754 …<description>Number of complete bytes that shall be included in the frame, excluding CRC, parity, …
125763 <description>Unspecified</description>
125769 <description>Configuration of incoming frames</description>
125777 <description>Indicates if parity expected in RX frame</description>
125783 <description>Parity is not expected in RX frames</description>
125788 <description>Parity is expected in RX frames</description>
125795 <description>SoF expected or not in RX frames</description>
125801 <description>SoF symbol is not expected in RX frames</description>
125806 <description>SoF symbol is expected in RX frames</description>
125813 <description>CRC mode for incoming frames</description>
125819 <description>CRC is not expected in RX frames</description>
125824 … <description>Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated</description>
125833 <description>Size of last incoming frame</description>
125841 …<description>Number of bits in the last byte in the frame, if less than 8 (including CRC, but excl…
125847 …<description>Number of complete bytes received in the frame (including CRC, but excluding parity a…
125856 …<description>Enables the modulation output to a GPIO pin which can be connected to a second extern…
125864 <description>Configuration of modulation control.</description>
125870 <description>Invalid, defaults to same behaviour as for Internal</description>
125875 <description>Use internal modulator only</description>
125880 <description>Output digital modulation signal to a GPIO pin.</description>
125885 …<description>Use internal modulator and output digital modulation signal to a GPIO pin.</descripti…
125894 <description>Pin select for Modulation control</description>
125902 <description>Pin number</description>
125908 <description>Port number</description>
125914 <description>Connection</description>
125920 <description>Disconnect</description>
125925 <description>Connect</description>
125934 <description>Configure EasyDMA mode</description>
125942 <description>Enable low-power operation, or use low-latency</description>
125948 <description>Low-latency operation</description>
125953 <description>Low-power operation</description>
125958 <description>Full Low-power operation</description>
125967 <description>Unspecified</description>
125973 <description>Last NFCID1 part (4, 7 or 10 bytes ID)</description>
125981 <description>NFCID1 byte Z (very last byte sent)</description>
125987 <description>NFCID1 byte Y</description>
125993 <description>NFCID1 byte X</description>
125999 <description>NFCID1 byte W</description>
126007 <description>Second last NFCID1 part (7 or 10 bytes ID)</description>
126015 <description>NFCID1 byte V</description>
126021 <description>NFCID1 byte U</description>
126027 <description>NFCID1 byte T</description>
126035 <description>Third last NFCID1 part (10 bytes ID)</description>
126043 <description>NFCID1 byte S</description>
126049 <description>NFCID1 byte R</description>
126055 <description>NFCID1 byte Q</description>
126064 …<description>Controls the auto collision resolution function. This setting must be done before the…
126072 <description>Enables/disables auto collision resolution</description>
126078 <description>Auto collision resolution enabled</description>
126083 <description>Auto collision resolution disabled</description>
126092 <description>NFC-A SENS_RES auto-response settings</description>
126100 …description>Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum,…
126106 <description>SDD pattern 00000</description>
126111 <description>SDD pattern 00001</description>
126116 <description>SDD pattern 00010</description>
126121 <description>SDD pattern 00100</description>
126126 <description>SDD pattern 01000</description>
126131 <description>SDD pattern 10000</description>
126138 <description>Reserved for future use. Shall be 0.</description>
126144 …<description>NFCID1 size. This value is used by the auto collision resolution engine.</description>
126150 <description>NFCID1 size: single (4 bytes)</description>
126155 <description>NFCID1 size: double (7 bytes)</description>
126160 <description>NFCID1 size: triple (10 bytes)</description>
126167 …description>Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in t…
126173 <description>Reserved for future use. Shall be 0.</description>
126181 <description>NFC-A SEL_RES auto-response settings</description>
126189 <description>Reserved for future use. Shall be 0.</description>
126195 …description>Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protoco…
126201 <description>Reserved for future use. Shall be 0.</description>
126207 …<description>Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Pr…
126213 <description>Reserved for future use. Shall be 0.</description>
126221 <description>NFC pad configuration</description>
126229 <description>Enable NFC pads</description>
126235 <description>NFC pads are used as GPIO pins</description>
126240 <description>The NFC pads are configured as NFC antenna pins</description>
126251 <description>Distributed programmable peripheral interconnect controller 3</description>
126259 <description>Time division multiplexed audio interface 0</description>
126278 … <description>Starts continuous TDM transfer. Also starts MCK when this is enabled</description>
126286 … <description>Starts continuous TDM transfer. Also starts MCK when this is enabled</description>
126292 <description>Trigger task</description>
126301 <description>Stops TDM transfer after the completion of MAXCNT words. Triggering this
126302 task will cause the STOPPED event to be generated.</description>
126310 <description>Stops TDM transfer after the completion of MAXCNT words. Triggering this
126311 task will cause the STOPPED event to be generated.</description>
126317 <description>Trigger task</description>
126326 <description>Abort TDM transfer without completing MAXCNT words. Triggering this task
126327 will cause the ABORTED event to be generated.</description>
126335 <description>Abort TDM transfer without completing MAXCNT words. Triggering this task
126336 will cause the ABORTED event to be generated.</description>
126342 <description>Trigger task</description>
126351 <description>Subscribe configuration for task START</description>
126359 <description>DPPI channel that task START will subscribe to</description>
126370 <description>Disable subscription</description>
126375 <description>Enable subscription</description>
126384 <description>Subscribe configuration for task STOP</description>
126392 <description>DPPI channel that task STOP will subscribe to</description>
126403 <description>Disable subscription</description>
126408 <description>Enable subscription</description>
126417 <description>Subscribe configuration for task ABORT</description>
126425 <description>DPPI channel that task ABORT will subscribe to</description>
126436 <description>Disable subscription</description>
126441 <description>Enable subscription</description>
126450 <description>The RXD.PTR register has been copied to internal double-buffers.
126451 …, this event will be generated for every RXTXD.MAXCNT words received on the SDIN pin.</description>
126459 <description>The RXD.PTR register has been copied to internal double-buffers.
126460 …, this event will be generated for every RXTXD.MAXCNT words received on the SDIN pin.</description>
126466 <description>Event not generated</description>
126471 <description>Event generated</description>
126480 <description>Transfer stopped.</description>
126488 <description>Transfer stopped.</description>
126494 <description>Event not generated</description>
126499 <description>Event generated</description>
126508 <description>Transfer aborted.</description>
126516 <description>Transfer aborted.</description>
126522 <description>Event not generated</description>
126527 <description>Event generated</description>
126536 <description>The TDX.PTR register has been copied to internal double-buffers.
126537 … event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin.</description>
126545 <description>The TDX.PTR register has been copied to internal double-buffers.
126546 … event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin.</description>
126552 <description>Event not generated</description>
126557 <description>Event generated</description>
126566 …<description>MAXCNT block event, generated on the active edge of FSYNC of every MAXCNT block</desc…
126574 …<description>MAXCNT block event, generated on the active edge of FSYNC of every MAXCNT block</desc…
126580 <description>Event not generated</description>
126585 <description>Event generated</description>
126594 <description>Publish configuration for event RXPTRUPD</description>
126602 <description>DPPI channel that event RXPTRUPD will publish to</description>
126613 <description>Disable publishing</description>
126618 <description>Enable publishing</description>
126627 <description>Publish configuration for event STOPPED</description>
126635 <description>DPPI channel that event STOPPED will publish to</description>
126646 <description>Disable publishing</description>
126651 <description>Enable publishing</description>
126660 <description>Publish configuration for event ABORTED</description>
126668 <description>DPPI channel that event ABORTED will publish to</description>
126679 <description>Disable publishing</description>
126684 <description>Enable publishing</description>
126693 <description>Publish configuration for event TXPTRUPD</description>
126701 <description>DPPI channel that event TXPTRUPD will publish to</description>
126712 <description>Disable publishing</description>
126717 <description>Enable publishing</description>
126726 <description>Publish configuration for event MAXCNT</description>
126734 <description>DPPI channel that event MAXCNT will publish to</description>
126745 <description>Disable publishing</description>
126750 <description>Enable publishing</description>
126759 <description>Enable or disable interrupt</description>
126767 <description>Enable or disable interrupt for event RXPTRUPD</description>
126773 <description>Disable</description>
126778 <description>Enable</description>
126785 <description>Enable or disable interrupt for event STOPPED</description>
126791 <description>Disable</description>
126796 <description>Enable</description>
126803 <description>Enable or disable interrupt for event ABORTED</description>
126809 <description>Disable</description>
126814 <description>Enable</description>
126821 <description>Enable or disable interrupt for event TXPTRUPD</description>
126827 <description>Disable</description>
126832 <description>Enable</description>
126839 <description>Enable or disable interrupt for event MAXCNT</description>
126845 <description>Disable</description>
126850 <description>Enable</description>
126859 <description>Enable interrupt</description>
126867 <description>Write '1' to enable interrupt for event RXPTRUPD</description>
126874 <description>Read: Disabled</description>
126879 <description>Read: Enabled</description>
126887 <description>Enable</description>
126894 <description>Write '1' to enable interrupt for event STOPPED</description>
126901 <description>Read: Disabled</description>
126906 <description>Read: Enabled</description>
126914 <description>Enable</description>
126921 <description>Write '1' to enable interrupt for event ABORTED</description>
126928 <description>Read: Disabled</description>
126933 <description>Read: Enabled</description>
126941 <description>Enable</description>
126948 <description>Write '1' to enable interrupt for event TXPTRUPD</description>
126955 <description>Read: Disabled</description>
126960 <description>Read: Enabled</description>
126968 <description>Enable</description>
126975 <description>Write '1' to enable interrupt for event MAXCNT</description>
126982 <description>Read: Disabled</description>
126987 <description>Read: Enabled</description>
126995 <description>Enable</description>
127004 <description>Disable interrupt</description>
127012 <description>Write '1' to disable interrupt for event RXPTRUPD</description>
127019 <description>Read: Disabled</description>
127024 <description>Read: Enabled</description>
127032 <description>Disable</description>
127039 <description>Write '1' to disable interrupt for event STOPPED</description>
127046 <description>Read: Disabled</description>
127051 <description>Read: Enabled</description>
127059 <description>Disable</description>
127066 <description>Write '1' to disable interrupt for event ABORTED</description>
127073 <description>Read: Disabled</description>
127078 <description>Read: Enabled</description>
127086 <description>Disable</description>
127093 <description>Write '1' to disable interrupt for event TXPTRUPD</description>
127100 <description>Read: Disabled</description>
127105 <description>Read: Enabled</description>
127113 <description>Disable</description>
127120 <description>Write '1' to disable interrupt for event MAXCNT</description>
127127 <description>Read: Disabled</description>
127132 <description>Read: Enabled</description>
127140 <description>Disable</description>
127149 <description>Enable TDM</description>
127157 <description>Enable TDM</description>
127163 <description>Disable</description>
127168 <description>Enable</description>
127177 <description>Configuration registers.</description>
127183 <description>Mode configuration</description>
127191 <description>Mode configuration</description>
127197 …<description>Master mode. SCK and FSYNC generated from internal master clock (MCK) and output on P…
127202 …<description>Slave mode. SCK and FSYNC generated by external master and received on PSEL.SCK and P…
127211 <description>Reception (RX) and transmission (TX) enable.</description>
127219 <description>Enable reception or transmission.</description>
127225 …description>Enable both reception and transmission. Data will be written to the RXD.PTR address an…
127230 …<description>Enable reception, disable transmission. Data will be written to the RXD.PTR address.<…
127235 …<description>Enable transmission, disable reception. Data will be transmitted from the TXD.PTR add…
127244 <description>Unspecified</description>
127250 <description>Master clock generator enable.</description>
127258 <description>Master clock generator enable.</description>
127264 <description>Master clock generator disabled.</description>
127269 <description>Master clock generator enabled.</description>
127278 <description>MCK divider.</description>
127286 <description>MCK frequency configuration</description>
127292 <description>CK divided by 2</description>
127297 <description>CK divided by 3</description>
127302 <description>CK divided by 4</description>
127307 <description>CK divided by 5</description>
127312 <description>CK divided by 6</description>
127317 <description>CK divided by 8</description>
127322 <description>CK divided by 10</description>
127327 <description>CK divided by 11</description>
127332 <description>CK divided by 15</description>
127337 <description>CK divided by 16</description>
127342 <description>CK divided by 21</description>
127347 <description>CK divided by 23</description>
127352 <description>CK divided by 30</description>
127357 <description>CK divided by 31</description>
127362 <description>CK divided by 32</description>
127367 <description>CK divided by 42</description>
127372 <description>CK divided by 63</description>
127377 <description>CK divided by 125</description>
127386 <description>MCK clock source selection</description>
127394 <description>Clock source selection</description>
127400 <description>32MHz peripheral clock</description>
127405 <description>Audio PLL clock</description>
127412 …<description>Bypass clock generator. MCK will be equal to source input. If bypass is enabled the M…
127418 <description>Disable bypass</description>
127423 <description>Enable bypass</description>
127433 <description>Unspecified</description>
127439 <description>SCK divider.</description>
127447 <description>SCK frequency configuration</description>
127453 <description>CK divided by 2</description>
127458 <description>CK divided by 3</description>
127463 <description>CK divided by 4</description>
127468 <description>CK divided by 5</description>
127473 <description>CK divided by 6</description>
127478 <description>CK divided by 8</description>
127483 <description>CK divided by 10</description>
127488 <description>CK divided by 11</description>
127493 <description>CK divided by 15</description>
127498 <description>CK divided by 16</description>
127503 <description>CK divided by 21</description>
127508 <description>CK divided by 23</description>
127513 <description>CK divided by 30</description>
127518 <description>CK divided by 31</description>
127523 <description>CK divided by 32</description>
127528 <description>CK divided by 42</description>
127533 <description>CK divided by 63</description>
127538 <description>CK divided by 125</description>
127547 <description>SCK clock source selection</description>
127555 <description>Clock source selection</description>
127561 <description>32MHz peripheral clock</description>
127566 <description>Audio PLL clock</description>
127573 …<description>Bypass clock generator. SCK will be equal to source input. If bypass is enabled the S…
127579 <description>Disable bypass</description>
127584 <description>Enable bypass</description>
127593 <description>Set SCK Polarity.</description>
127601 <description>Set the polarity of the active SCK edge.</description>
127607 … <description>TX data is written to the SDOUT pin on the falling edge of SCK, ready to be
127608 received on the rising edge of SCK.</description>
127613 … <description>TX data is written to the SDOUT pin on the rising edge of SCK, ready to be
127614 received on the falling edge of SCK.</description>
127624 <description>Sample and word width configuration.</description>
127632 <description>Sample and word width</description>
127638 <description>8 bit sample in an 8-bit word.</description>
127643 <description>16 bit sample in a 16-bit word.</description>
127648 <description>24 bit sample in a 24-bit word.</description>
127653 <description>32 bit sample in a 32-bit word.</description>
127658 <description>8 bit sample in a 16-bit word.</description>
127663 <description>8 bit sample in a 32-bit word.</description>
127668 <description>16 bit sample in a 32-bit word.</description>
127673 <description>24 bit sample in a 32-bit word.</description>
127682 <description>Alignment of sample within the audio data word.</description>
127690 <description>Alignment of sample within the audio data word.</description>
127696 <description>Left-aligned.</description>
127701 <description>Right-aligned.</description>
127710 <description>Unspecified</description>
127716 <description>Select which channels are to be used.</description>
127729 <description>Disable Rx channel data.</description>
127734 <description>Enable Rx channel data.</description>
127746 <description>Disable Rx channel data.</description>
127751 <description>Enable Rx channel data.</description>
127763 <description>Disable Rx channel data.</description>
127768 <description>Enable Rx channel data.</description>
127780 <description>Disable Rx channel data.</description>
127785 <description>Enable Rx channel data.</description>
127797 <description>Disable Rx channel data.</description>
127802 <description>Enable Rx channel data.</description>
127814 <description>Disable Rx channel data.</description>
127819 <description>Enable Rx channel data.</description>
127831 <description>Disable Rx channel data.</description>
127836 <description>Enable Rx channel data.</description>
127848 <description>Disable Rx channel data.</description>
127853 <description>Enable Rx channel data.</description>
127865 <description>Disable Tx channel data.</description>
127870 <description>Enable Tx channel data.</description>
127882 <description>Disable Tx channel data.</description>
127887 <description>Enable Tx channel data.</description>
127899 <description>Disable Tx channel data.</description>
127904 <description>Enable Tx channel data.</description>
127916 <description>Disable Tx channel data.</description>
127921 <description>Enable Tx channel data.</description>
127933 <description>Disable Tx channel data.</description>
127938 <description>Enable Tx channel data.</description>
127950 <description>Disable Tx channel data.</description>
127955 <description>Enable Tx channel data.</description>
127967 <description>Disable Tx channel data.</description>
127972 <description>Enable Tx channel data.</description>
127984 <description>Disable Tx channel data.</description>
127989 <description>Enable Tx channel data.</description>
127998 <description>Select number of channels.</description>
128006 <description>Select number of channels.</description>
128012 <description>1-channel audio (mono).</description>
128017 <description>2-channel audio (stereo).</description>
128022 <description>3-channel audio.</description>
128027 <description>4-channel audio.</description>
128032 <description>5-channel audio.</description>
128037 <description>6-channel audio.</description>
128042 <description>7-channel audio.</description>
128047 <description>8-channel audio.</description>
128056 <description>Set channel delay.</description>
128064 …<description>Configure number of inactive SCK periods from edge of FSYNC until start of first data…
128070 <description>No delay. Used with I2S DSP/Aligned format.</description>
128075 … <description>One clock pulse delay. Used with Original I2S format.</description>
128080 <description>Two clock pulses delay.</description>
128090 <description>Unspecified</description>
128096 <description>Set FSYNC Polarity.</description>
128104 <description>Set the polarity of the active period of FSYNC.</description>
128110 <description>Frame starts at falling edge of FSYNC.</description>
128115 <description>Frame starts at rising edge of FSYNC.</description>
128124 <description>Set FSYNC Duration.</description>
128132 … <description>Set the duration of the active period of FSYNC in Master mode.</description>
128138 <description>FSYNC is active for the duration of one SCK pulse</description>
128143 <description>FSYNC is active for the duration of channel</description>
128153 … <description>Over-read sample: Extra sample bytes that are transmitted after TXD.MAXCNT bytes
128154 have been transmitted, in the case when RXD.MAXCNT is greater than TXD.MAXCNT.</description>
128162 … <description>Data transmitted after TXD.MAXCNT bytes have been transmitted in the case when
128163 RXD.MAXCNT is greater than TXD.MAXCNT.</description>
128172 <description>Unspecified</description>
128178 <description>Pin select for MCK signal</description>
128186 <description>Pin number</description>
128192 <description>Port number</description>
128198 <description>Connection</description>
128204 <description>Disconnect</description>
128209 <description>Connect</description>
128218 <description>Pin select for SCK signal</description>
128226 <description>Pin number</description>
128232 <description>Port number</description>
128238 <description>Connection</description>
128244 <description>Disconnect</description>
128249 <description>Connect</description>
128258 <description>Pin select for FSYNC signal</description>
128266 <description>Pin number</description>
128272 <description>Port number</description>
128278 <description>Connection</description>
128284 <description>Disconnect</description>
128289 <description>Connect</description>
128298 <description>Pin select for SDIN signal</description>
128306 <description>Pin number</description>
128312 <description>Port number</description>
128318 <description>Connection</description>
128324 <description>Disconnect</description>
128329 <description>Connect</description>
128338 <description>Pin select for SDOUT signal</description>
128346 <description>Pin number</description>
128352 <description>Port number</description>
128358 <description>Connection</description>
128364 <description>Disconnect</description>
128369 <description>Connect</description>
128379 <description>Unspecified</description>
128385 <description>RAM buffer start address</description>
128393 …<description>RAM buffer start address for this EasyDMA channel. This address is a word aligned Dat…
128401 <description>Maximum number of bytes in channel buffer</description>
128409 <description>Maximum number of bytes in channel buffer</description>
128417 …<description>Number of bytes transferred in the last transaction, updated after the END event.</de…
128425 …<description>Number of bytes transferred in the last transaction. In case of NACK error, includes …
128433 <description>Number of bytes transferred in the current transaction</description>
128441 …<description>Number of bytes transferred in the current transaction. Continuously updated.</descri…
128449 <description>Configure EasyDMA mode</description>
128457 <description>Enable low-power operation, or use low-latency</description>
128463 <description>Low-latency operation</description>
128468 <description>Low-power operation</description>
128477 <description>Terminate the transaction if a BUSERROR event is detected.</description>
128490 <description>Disable</description>
128495 <description>Enable</description>
128504 … <description>Address of transaction that generated the last BUSERROR event.</description>
128520 <description>Unspecified</description>
128526 <description>RAM buffer start address</description>
128534 …<description>RAM buffer start address for this EasyDMA channel. This address is a word aligned Dat…
128542 <description>Maximum number of bytes in channel buffer</description>
128550 <description>Maximum number of bytes in channel buffer</description>
128558 …<description>Number of bytes transferred in the last transaction, updated after the END event.</de…
128566 …<description>Number of bytes transferred in the last transaction. In case of NACK error, includes …
128574 <description>Number of bytes transferred in the current transaction</description>
128582 …<description>Number of bytes transferred in the current transaction. Continuously updated.</descri…
128590 <description>Configure EasyDMA mode</description>
128598 <description>Enable low-power operation, or use low-latency</description>
128604 <description>Low-latency operation</description>
128609 <description>Low-power operation</description>
128618 <description>Terminate the transaction if a BUSERROR event is detected.</description>
128631 <description>Disable</description>
128636 <description>Enable</description>
128645 … <description>Address of transaction that generated the last BUSERROR event.</description>
128663 <description>Pulse Density Modulation (Digital Microphone) Interface</description>
128681 <description>Starts continuous PDM transfer</description>
128689 <description>Starts continuous PDM transfer</description>
128695 <description>Trigger task</description>
128704 <description>Stops PDM transfer</description>
128712 <description>Stops PDM transfer</description>
128718 <description>Trigger task</description>
128727 <description>Subscribe configuration for task START</description>
128735 <description>DPPI channel that task START will subscribe to</description>
128746 <description>Disable subscription</description>
128751 <description>Enable subscription</description>
128760 <description>Subscribe configuration for task STOP</description>
128768 <description>DPPI channel that task STOP will subscribe to</description>
128779 <description>Disable subscription</description>
128784 <description>Enable subscription</description>
128793 <description>PDM transfer has started</description>
128801 <description>PDM transfer has started</description>
128807 <description>Event not generated</description>
128812 <description>Event generated</description>
128821 <description>PDM transfer has finished</description>
128829 <description>PDM transfer has finished</description>
128835 <description>Event not generated</description>
128840 <description>Event generated</description>
128849 …description>The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample aft…
128857 …description>The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample aft…
128863 <description>Event not generated</description>
128868 <description>Event generated</description>
128877 <description>Peripheral events.</description>
128883 … <description>This event is generated if an error occurs during the bus transfer.</description>
128891 … <description>This event is generated if an error occurs during the bus transfer.</description>
128897 <description>Event not generated</description>
128902 <description>Event generated</description>
128912 <description>Publish configuration for event STARTED</description>
128920 <description>DPPI channel that event STARTED will publish to</description>
128931 <description>Disable publishing</description>
128936 <description>Enable publishing</description>
128945 <description>Publish configuration for event STOPPED</description>
128953 <description>DPPI channel that event STOPPED will publish to</description>
128964 <description>Disable publishing</description>
128969 <description>Enable publishing</description>
128978 <description>Publish configuration for event END</description>
128986 <description>DPPI channel that event END will publish to</description>
128997 <description>Disable publishing</description>
129002 <description>Enable publishing</description>
129011 <description>Publish configuration for events</description>
129017 <description>Publish configuration for event DMA.BUSERROR</description>
129025 <description>DPPI channel that event DMA.BUSERROR will publish to</description>
129036 <description>Disable publishing</description>
129041 <description>Enable publishing</description>
129051 <description>Enable or disable interrupt</description>
129059 <description>Enable or disable interrupt for event STARTED</description>
129065 <description>Disable</description>
129070 <description>Enable</description>
129077 <description>Enable or disable interrupt for event STOPPED</description>
129083 <description>Disable</description>
129088 <description>Enable</description>
129095 <description>Enable or disable interrupt for event END</description>
129101 <description>Disable</description>
129106 <description>Enable</description>
129113 <description>Enable or disable interrupt for event DMABUSERROR</description>
129119 <description>Disable</description>
129124 <description>Enable</description>
129133 <description>Enable interrupt</description>
129141 <description>Write '1' to enable interrupt for event STARTED</description>
129148 <description>Read: Disabled</description>
129153 <description>Read: Enabled</description>
129161 <description>Enable</description>
129168 <description>Write '1' to enable interrupt for event STOPPED</description>
129175 <description>Read: Disabled</description>
129180 <description>Read: Enabled</description>
129188 <description>Enable</description>
129195 <description>Write '1' to enable interrupt for event END</description>
129202 <description>Read: Disabled</description>
129207 <description>Read: Enabled</description>
129215 <description>Enable</description>
129222 <description>Write '1' to enable interrupt for event DMABUSERROR</description>
129229 <description>Read: Disabled</description>
129234 <description>Read: Enabled</description>
129242 <description>Enable</description>
129251 <description>Disable interrupt</description>
129259 <description>Write '1' to disable interrupt for event STARTED</description>
129266 <description>Read: Disabled</description>
129271 <description>Read: Enabled</description>
129279 <description>Disable</description>
129286 <description>Write '1' to disable interrupt for event STOPPED</description>
129293 <description>Read: Disabled</description>
129298 <description>Read: Enabled</description>
129306 <description>Disable</description>
129313 <description>Write '1' to disable interrupt for event END</description>
129320 <description>Read: Disabled</description>
129325 <description>Read: Enabled</description>
129333 <description>Disable</description>
129340 <description>Write '1' to disable interrupt for event DMABUSERROR</description>
129347 <description>Read: Disabled</description>
129352 <description>Read: Enabled</description>
129360 <description>Disable</description>
129369 <description>Pending interrupts</description>
129377 <description>Read pending status of interrupt for event STARTED</description>
129384 <description>Read: Not pending</description>
129389 <description>Read: Pending</description>
129396 <description>Read pending status of interrupt for event STOPPED</description>
129403 <description>Read: Not pending</description>
129408 <description>Read: Pending</description>
129415 <description>Read pending status of interrupt for event END</description>
129422 <description>Read: Not pending</description>
129427 <description>Read: Pending</description>
129434 <description>Read pending status of interrupt for event DMABUSERROR</description>
129441 <description>Read: Not pending</description>
129446 <description>Read: Pending</description>
129455 <description>PDM module enable register</description>
129463 <description>Enable or disable PDM module</description>
129469 <description>Disable</description>
129474 <description>Enable</description>
129483 <description>PDM clock generator control</description>
129491 <description>PDM_CLK frequency configuration. Enumerations are deprecated, use
129493 register are ignored and shall be set to zero.</description>
129499 <description>PDM_CLK = 32 MHz / 32 = 1.000 MHz</description>
129504 … <description>PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64.</description>
129509 <description>PDM_CLK = 32 MHz / 30 = 1.067 MHz</description>
129514 <description>PDM_CLK = 32 MHz / 26 = 1.231 MHz</description>
129519 … <description>PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80.</description>
129524 <description>PDM_CLK = 32 MHz / 24 = 1.333 MHz</description>
129533 <description>Defines the routing of the connected PDM microphone signals</description>
129541 <description>Mono or stereo operation</description>
129547 …<description>Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=…
129552 …<description>Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; …
129559 <description>Defines on which PDM_CLK edge left (or mono) is sampled.</description>
129565 <description>Left (or mono) is sampled on falling edge of PDM_CLK</description>
129570 <description>Left (or mono) is sampled on rising edge of PDM_CLK</description>
129579 <description>Left output gain adjustment</description>
129587 …description>Left output gain adjustment, in 0.5 dB steps, around the default module gain (see elec…
129593 <description>-20 dB gain adjustment (minimum)</description>
129598 <description>0 dB gain adjustment</description>
129603 <description>+20 dB gain adjustment (maximum)</description>
129612 <description>Right output gain adjustment</description>
129620 …<description>Right output gain adjustment, in 0.5 dB steps, around the default module gain (see el…
129626 <description>-20 dB gain adjustment (minimum)</description>
129631 <description>0 dB gain adjustment</description>
129636 <description>+20 dB gain adjustment (maximum)</description>
129645 …<description>Selects the decimation ratio between PDM_CLK and output sample rate. Change PDMCLKCTR…
129653 … <description>Selects the decimation ratio between PDM_CLK and output sample rate</description>
129659 <description>Ratio of 32</description>
129664 <description>Ratio of 48</description>
129669 <description>Ratio of 50</description>
129674 <description>Ratio of 64</description>
129679 <description>Ratio of 80</description>
129684 <description>Ratio of 96</description>
129689 <description>Ratio of 100</description>
129694 <description>Ratio of 128</description>
129703 <description>Unspecified</description>
129709 <description>Pin number configuration for PDM CLK signal</description>
129717 <description>Pin number</description>
129723 <description>Port number</description>
129729 <description>Connection</description>
129735 <description>Disconnect</description>
129740 <description>Connect</description>
129749 <description>Pin number configuration for PDM DIN signal</description>
129757 <description>Pin number</description>
129763 <description>Port number</description>
129769 <description>Connection</description>
129775 <description>Disconnect</description>
129780 <description>Connect</description>
129790 <description>Master clock generator configuration</description>
129798 <description>Master clock source selection</description>
129804 <description>32 MHz peripheral clock</description>
129809 <description>Audio PLL clock</description>
129818 <description>Unspecified</description>
129824 <description>RAM address pointer to write samples to with EasyDMA</description>
129832 <description>Address to write PCM samples to over DMA</description>
129840 <description>Number of bytes to allocate memory for in EasyDMA mode</description>
129848 <description>Length of DMA RAM allocation in number of bytes</description>
129857 <description>Unspecified</description>
129863 <description>Terminate the transaction if a BUSERROR event is detected.</description>
129876 <description>Disable</description>
129881 <description>Enable</description>
129890 … <description>Address of transaction that generated the last BUSERROR event.</description>
129908 <description>Quadrature Decoder 0</description>
129927 <description>Task starting the quadrature decoder</description>
129935 <description>Task starting the quadrature decoder</description>
129941 <description>Trigger task</description>
129950 <description>Task stopping the quadrature decoder</description>
129958 <description>Task stopping the quadrature decoder</description>
129964 <description>Trigger task</description>
129973 <description>Read and clear ACC and ACCDBL</description>
129981 <description>Read and clear ACC and ACCDBL</description>
129987 <description>Trigger task</description>
129996 <description>Read and clear ACC</description>
130004 <description>Read and clear ACC</description>
130010 <description>Trigger task</description>
130019 <description>Read and clear ACCDBL</description>
130027 <description>Read and clear ACCDBL</description>
130033 <description>Trigger task</description>
130042 <description>Subscribe configuration for task START</description>
130050 <description>DPPI channel that task START will subscribe to</description>
130061 <description>Disable subscription</description>
130066 <description>Enable subscription</description>
130075 <description>Subscribe configuration for task STOP</description>
130083 <description>DPPI channel that task STOP will subscribe to</description>
130094 <description>Disable subscription</description>
130099 <description>Enable subscription</description>
130108 <description>Subscribe configuration for task READCLRACC</description>
130116 <description>DPPI channel that task READCLRACC will subscribe to</description>
130127 <description>Disable subscription</description>
130132 <description>Enable subscription</description>
130141 <description>Subscribe configuration for task RDCLRACC</description>
130149 <description>DPPI channel that task RDCLRACC will subscribe to</description>
130160 <description>Disable subscription</description>
130165 <description>Enable subscription</description>
130174 <description>Subscribe configuration for task RDCLRDBL</description>
130182 <description>DPPI channel that task RDCLRDBL will subscribe to</description>
130193 <description>Disable subscription</description>
130198 <description>Enable subscription</description>
130207 …<description>Event being generated for every new sample value written to the SAMPLE register</desc…
130215 …<description>Event being generated for every new sample value written to the SAMPLE register</desc…
130221 <description>Event not generated</description>
130226 <description>Event generated</description>
130235 <description>Non-null report ready</description>
130243 <description>Non-null report ready</description>
130249 <description>Event not generated</description>
130254 <description>Event generated</description>
130263 <description>ACC or ACCDBL register overflow</description>
130271 <description>ACC or ACCDBL register overflow</description>
130277 <description>Event not generated</description>
130282 <description>Event generated</description>
130291 <description>Double displacement(s) detected</description>
130299 <description>Double displacement(s) detected</description>
130305 <description>Event not generated</description>
130310 <description>Event generated</description>
130319 <description>QDEC has been stopped</description>
130327 <description>QDEC has been stopped</description>
130333 <description>Event not generated</description>
130338 <description>Event generated</description>
130347 <description>Publish configuration for event SAMPLERDY</description>
130355 <description>DPPI channel that event SAMPLERDY will publish to</description>
130366 <description>Disable publishing</description>
130371 <description>Enable publishing</description>
130380 <description>Publish configuration for event REPORTRDY</description>
130388 <description>DPPI channel that event REPORTRDY will publish to</description>
130399 <description>Disable publishing</description>
130404 <description>Enable publishing</description>
130413 <description>Publish configuration for event ACCOF</description>
130421 <description>DPPI channel that event ACCOF will publish to</description>
130432 <description>Disable publishing</description>
130437 <description>Enable publishing</description>
130446 <description>Publish configuration for event DBLRDY</description>
130454 <description>DPPI channel that event DBLRDY will publish to</description>
130465 <description>Disable publishing</description>
130470 <description>Enable publishing</description>
130479 <description>Publish configuration for event STOPPED</description>
130487 <description>DPPI channel that event STOPPED will publish to</description>
130498 <description>Disable publishing</description>
130503 <description>Enable publishing</description>
130512 <description>Shortcuts between local events and tasks</description>
130520 <description>Shortcut between event REPORTRDY and task READCLRACC</description>
130526 <description>Disable shortcut</description>
130531 <description>Enable shortcut</description>
130538 <description>Shortcut between event SAMPLERDY and task STOP</description>
130544 <description>Disable shortcut</description>
130549 <description>Enable shortcut</description>
130556 <description>Shortcut between event REPORTRDY and task RDCLRACC</description>
130562 <description>Disable shortcut</description>
130567 <description>Enable shortcut</description>
130574 <description>Shortcut between event REPORTRDY and task STOP</description>
130580 <description>Disable shortcut</description>
130585 <description>Enable shortcut</description>
130592 <description>Shortcut between event DBLRDY and task RDCLRDBL</description>
130598 <description>Disable shortcut</description>
130603 <description>Enable shortcut</description>
130610 <description>Shortcut between event DBLRDY and task STOP</description>
130616 <description>Disable shortcut</description>
130621 <description>Enable shortcut</description>
130628 <description>Shortcut between event SAMPLERDY and task READCLRACC</description>
130634 <description>Disable shortcut</description>
130639 <description>Enable shortcut</description>
130648 <description>Enable interrupt</description>
130656 <description>Write '1' to enable interrupt for event SAMPLERDY</description>
130663 <description>Read: Disabled</description>
130668 <description>Read: Enabled</description>
130676 <description>Enable</description>
130683 <description>Write '1' to enable interrupt for event REPORTRDY</description>
130690 <description>Read: Disabled</description>
130695 <description>Read: Enabled</description>
130703 <description>Enable</description>
130710 <description>Write '1' to enable interrupt for event ACCOF</description>
130717 <description>Read: Disabled</description>
130722 <description>Read: Enabled</description>
130730 <description>Enable</description>
130737 <description>Write '1' to enable interrupt for event DBLRDY</description>
130744 <description>Read: Disabled</description>
130749 <description>Read: Enabled</description>
130757 <description>Enable</description>
130764 <description>Write '1' to enable interrupt for event STOPPED</description>
130771 <description>Read: Disabled</description>
130776 <description>Read: Enabled</description>
130784 <description>Enable</description>
130793 <description>Disable interrupt</description>
130801 <description>Write '1' to disable interrupt for event SAMPLERDY</description>
130808 <description>Read: Disabled</description>
130813 <description>Read: Enabled</description>
130821 <description>Disable</description>
130828 <description>Write '1' to disable interrupt for event REPORTRDY</description>
130835 <description>Read: Disabled</description>
130840 <description>Read: Enabled</description>
130848 <description>Disable</description>
130855 <description>Write '1' to disable interrupt for event ACCOF</description>
130862 <description>Read: Disabled</description>
130867 <description>Read: Enabled</description>
130875 <description>Disable</description>
130882 <description>Write '1' to disable interrupt for event DBLRDY</description>
130889 <description>Read: Disabled</description>
130894 <description>Read: Enabled</description>
130902 <description>Disable</description>
130909 <description>Write '1' to disable interrupt for event STOPPED</description>
130916 <description>Read: Disabled</description>
130921 <description>Read: Enabled</description>
130929 <description>Disable</description>
130938 <description>Enable the quadrature decoder</description>
130946 <description>Enable or disable the quadrature decoder</description>
130952 <description>Disable</description>
130957 <description>Enable</description>
130966 <description>LED output pin polarity</description>
130974 <description>LED output pin polarity</description>
130980 <description>Led active on output pin low</description>
130985 <description>Led active on output pin high</description>
130994 <description>Sample period</description>
131002 … <description>Sample period. The SAMPLE register will be updated for every new sample</description>
131008 <description>128 us</description>
131013 <description>256 us</description>
131018 <description>512 us</description>
131023 <description>1024 us</description>
131028 <description>2048 us</description>
131033 <description>4096 us</description>
131038 <description>8192 us</description>
131043 <description>16384 us</description>
131048 <description>32768 us</description>
131053 <description>65536 us</description>
131058 <description>131072 us</description>
131067 <description>Motion sample value</description>
131076 <description>Last motion sample</description>
131084 …<description>Number of samples to be taken before REPORTRDY and DBLRDY events can be generated</de…
131092 …<description>Specifies the number of samples to be accumulated in the ACC register before the REPO…
131098 <description>10 samples/report</description>
131103 <description>40 samples/report</description>
131108 <description>80 samples/report</description>
131113 <description>120 samples/report</description>
131118 <description>160 samples/report</description>
131123 <description>200 samples/report</description>
131128 <description>240 samples/report</description>
131133 <description>280 samples/report</description>
131138 <description>1 sample/report</description>
131147 <description>Register accumulating the valid transitions</description>
131156 …<description>Register accumulating all valid samples (not double transition) read from the SAMPLE …
131164 …<description>Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task</description>
131173 <description>Snapshot of the ACC register.</description>
131181 <description>Unspecified</description>
131187 <description>Pin select for LED signal</description>
131195 <description>Pin number</description>
131201 <description>Port number</description>
131207 <description>Connection</description>
131213 <description>Disconnect</description>
131218 <description>Connect</description>
131227 <description>Pin select for A signal</description>
131235 <description>Pin number</description>
131241 <description>Port number</description>
131247 <description>Connection</description>
131253 <description>Disconnect</description>
131258 <description>Connect</description>
131267 <description>Pin select for B signal</description>
131275 <description>Pin number</description>
131281 <description>Port number</description>
131287 <description>Connection</description>
131293 <description>Disconnect</description>
131298 <description>Connect</description>
131308 <description>Enable input debounce filters</description>
131316 <description>Enable input debounce filters</description>
131322 <description>Debounce input filters disabled</description>
131327 <description>Debounce input filters enabled</description>
131336 <description>Time period the LED is switched ON prior to sampling</description>
131344 <description>Period in us the LED is switched on prior to sampling</description>
131352 <description>Register accumulating the number of detected double transitions</description>
131360 …<description>Register accumulating the number of detected double or illegal transitions. ( SAMPLE …
131368 … <description>Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task</description>
131376 …<description>Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDB…
131386 <description>Quadrature Decoder 1</description>
131397 <description>Time division multiplexed audio interface 1</description>
131408 <description>Distributed programmable peripheral interconnect controller 4</description>
131416 <description>Timer/Counter 2</description>
131427 <description>Timer/Counter 3</description>
131438 <description>Pulse width modulation unit 1</description>
131449 <description>Serial Peripheral Interface Master with EasyDMA 2</description>
131460 <description>SPI Slave 1</description>
131472 <description>I2C compatible Two-Wire Master Interface with EasyDMA 0</description>
131492 …<description>Stop TWI transaction. Must be issued while the TWI master is not suspended.</descript…
131500 …<description>Stop TWI transaction. Must be issued while the TWI master is not suspended.</descript…
131506 <description>Trigger task</description>
131515 <description>Suspend TWI transaction</description>
131523 <description>Suspend TWI transaction</description>
131529 <description>Trigger task</description>
131538 <description>Resume TWI transaction</description>
131546 <description>Resume TWI transaction</description>
131552 <description>Trigger task</description>
131561 <description>Peripheral tasks.</description>
131567 <description>Peripheral tasks.</description>
131573 …<description>Starts operation using easyDMA to load the values. See peripheral description for ope…
131581 …<description>Starts operation using easyDMA to load the values. See peripheral description for ope…
131587 <description>Trigger task</description>
131596 … <description>Stops operation using easyDMA. This does not trigger an END event.</description>
131604 … <description>Stops operation using easyDMA. This does not trigger an END event.</description>
131610 <description>Trigger task</description>
131621 …<description>Description collection: Enables the MATCH[n] event by setting the ENABLE[n] bit in th…
131629 …<description>Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register.</desc…
131635 <description>Trigger task</description>
131646 …<description>Description collection: Disables the MATCH[n] event by clearing the ENABLE[n] bit in …
131654 …<description>Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register.</de…
131660 <description>Trigger task</description>
131670 <description>Peripheral tasks.</description>
131676 …<description>Starts operation using easyDMA to load the values. See peripheral description for ope…
131684 …<description>Starts operation using easyDMA to load the values. See peripheral description for ope…
131690 <description>Trigger task</description>
131699 … <description>Stops operation using easyDMA. This does not trigger an END event.</description>
131707 … <description>Stops operation using easyDMA. This does not trigger an END event.</description>
131713 <description>Trigger task</description>
131724 <description>Subscribe configuration for task STOP</description>
131732 <description>DPPI channel that task STOP will subscribe to</description>
131743 <description>Disable subscription</description>
131748 <description>Enable subscription</description>
131757 <description>Subscribe configuration for task SUSPEND</description>
131765 <description>DPPI channel that task SUSPEND will subscribe to</description>
131776 <description>Disable subscription</description>
131781 <description>Enable subscription</description>
131790 <description>Subscribe configuration for task RESUME</description>
131798 <description>DPPI channel that task RESUME will subscribe to</description>
131809 <description>Disable subscription</description>
131814 <description>Enable subscription</description>
131823 <description>Subscribe configuration for tasks</description>
131829 <description>Subscribe configuration for tasks</description>
131835 <description>Subscribe configuration for task START</description>
131843 <description>DPPI channel that task START will subscribe to</description>
131854 <description>Disable subscription</description>
131859 <description>Enable subscription</description>
131868 <description>Subscribe configuration for task STOP</description>
131876 <description>DPPI channel that task STOP will subscribe to</description>
131887 <description>Disable subscription</description>
131892 <description>Enable subscription</description>
131903 … <description>Description collection: Subscribe configuration for task ENABLEMATCH[n]</description>
131911 <description>DPPI channel that task ENABLEMATCH[n] will subscribe to</description>
131922 <description>Disable subscription</description>
131927 <description>Enable subscription</description>
131938 …<description>Description collection: Subscribe configuration for task DISABLEMATCH[n]</description>
131946 … <description>DPPI channel that task DISABLEMATCH[n] will subscribe to</description>
131957 <description>Disable subscription</description>
131962 <description>Enable subscription</description>
131972 <description>Subscribe configuration for tasks</description>
131978 <description>Subscribe configuration for task START</description>
131986 <description>DPPI channel that task START will subscribe to</description>
131997 <description>Disable subscription</description>
132002 <description>Enable subscription</description>
132011 <description>Subscribe configuration for task STOP</description>
132019 <description>DPPI channel that task STOP will subscribe to</description>
132030 <description>Disable subscription</description>
132035 <description>Enable subscription</description>
132046 <description>TWI stopped</description>
132054 <description>TWI stopped</description>
132060 <description>Event not generated</description>
132065 <description>Event generated</description>
132074 <description>TWI error</description>
132082 <description>TWI error</description>
132088 <description>Event not generated</description>
132093 <description>Event generated</description>
132102 <description>SUSPEND task has been issued, TWI traffic is now suspended.</description>
132110 <description>SUSPEND task has been issued, TWI traffic is now suspended.</description>
132116 <description>Event not generated</description>
132121 <description>Event generated</description>
132130 <description>Byte boundary, starting to receive the last byte</description>
132138 <description>Byte boundary, starting to receive the last byte</description>
132144 <description>Event not generated</description>
132149 <description>Event generated</description>
132158 <description>Byte boundary, starting to transmit the last byte</description>
132166 <description>Byte boundary, starting to transmit the last byte</description>
132172 <description>Event not generated</description>
132177 <description>Event generated</description>
132186 <description>Peripheral events.</description>
132192 <description>Peripheral events.</description>
132198 <description>Generated after all MAXCNT bytes have been transferred</description>
132206 <description>Generated after all MAXCNT bytes have been transferred</description>
132212 <description>Event not generated</description>
132217 <description>Event generated</description>
132226 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
132234 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
132240 <description>Event not generated</description>
132245 <description>Event generated</description>
132254 <description>An error occured during the bus transfer.</description>
132262 <description>An error occured during the bus transfer.</description>
132268 <description>Event not generated</description>
132273 <description>Event generated</description>
132284 … <description>Description collection: Pattern match is detected on the DMA data bus.</description>
132292 <description>Pattern match is detected on the DMA data bus.</description>
132298 <description>Event not generated</description>
132303 <description>Event generated</description>
132313 <description>Peripheral events.</description>
132319 <description>Generated after all MAXCNT bytes have been transferred</description>
132327 <description>Generated after all MAXCNT bytes have been transferred</description>
132333 <description>Event not generated</description>
132338 <description>Event generated</description>
132347 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
132355 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
132361 <description>Event not generated</description>
132366 <description>Event generated</description>
132375 <description>An error occured during the bus transfer.</description>
132383 <description>An error occured during the bus transfer.</description>
132389 <description>Event not generated</description>
132394 <description>Event generated</description>
132405 <description>Publish configuration for event STOPPED</description>
132413 <description>DPPI channel that event STOPPED will publish to</description>
132424 <description>Disable publishing</description>
132429 <description>Enable publishing</description>
132438 <description>Publish configuration for event ERROR</description>
132446 <description>DPPI channel that event ERROR will publish to</description>
132457 <description>Disable publishing</description>
132462 <description>Enable publishing</description>
132471 <description>Publish configuration for event SUSPENDED</description>
132479 <description>DPPI channel that event SUSPENDED will publish to</description>
132490 <description>Disable publishing</description>
132495 <description>Enable publishing</description>
132504 <description>Publish configuration for event LASTRX</description>
132512 <description>DPPI channel that event LASTRX will publish to</description>
132523 <description>Disable publishing</description>
132528 <description>Enable publishing</description>
132537 <description>Publish configuration for event LASTTX</description>
132545 <description>DPPI channel that event LASTTX will publish to</description>
132556 <description>Disable publishing</description>
132561 <description>Enable publishing</description>
132570 <description>Publish configuration for events</description>
132576 <description>Publish configuration for events</description>
132582 <description>Publish configuration for event END</description>
132590 <description>DPPI channel that event END will publish to</description>
132601 <description>Disable publishing</description>
132606 <description>Enable publishing</description>
132615 <description>Publish configuration for event READY</description>
132623 <description>DPPI channel that event READY will publish to</description>
132634 <description>Disable publishing</description>
132639 <description>Enable publishing</description>
132648 <description>Publish configuration for event BUSERROR</description>
132656 <description>DPPI channel that event BUSERROR will publish to</description>
132667 <description>Disable publishing</description>
132672 <description>Enable publishing</description>
132683 … <description>Description collection: Publish configuration for event MATCH[n]</description>
132691 <description>DPPI channel that event MATCH[n] will publish to</description>
132702 <description>Disable publishing</description>
132707 <description>Enable publishing</description>
132717 <description>Publish configuration for events</description>
132723 <description>Publish configuration for event END</description>
132731 <description>DPPI channel that event END will publish to</description>
132742 <description>Disable publishing</description>
132747 <description>Enable publishing</description>
132756 <description>Publish configuration for event READY</description>
132764 <description>DPPI channel that event READY will publish to</description>
132775 <description>Disable publishing</description>
132780 <description>Enable publishing</description>
132789 <description>Publish configuration for event BUSERROR</description>
132797 <description>DPPI channel that event BUSERROR will publish to</description>
132808 <description>Disable publishing</description>
132813 <description>Enable publishing</description>
132824 <description>Shortcuts between local events and tasks</description>
132832 <description>Shortcut between event LASTTX and task DMA.RX.START</description>
132838 <description>Disable shortcut</description>
132843 <description>Enable shortcut</description>
132850 <description>Shortcut between event LASTTX and task SUSPEND</description>
132856 <description>Disable shortcut</description>
132861 <description>Enable shortcut</description>
132868 <description>Shortcut between event LASTTX and task STOP</description>
132874 <description>Disable shortcut</description>
132879 <description>Enable shortcut</description>
132886 <description>Shortcut between event LASTRX and task DMA.TX.START</description>
132892 <description>Disable shortcut</description>
132897 <description>Enable shortcut</description>
132904 <description>Shortcut between event LASTRX and task STOP</description>
132910 <description>Disable shortcut</description>
132915 <description>Enable shortcut</description>
132922 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows daisy-ch…
132928 <description>Disable shortcut</description>
132933 <description>Enable shortcut</description>
132940 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows daisy-ch…
132946 <description>Disable shortcut</description>
132951 <description>Enable shortcut</description>
132958 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows daisy-ch…
132964 <description>Disable shortcut</description>
132969 <description>Enable shortcut</description>
132976 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows daisy-ch…
132982 <description>Disable shortcut</description>
132987 <description>Enable shortcut</description>
132994 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
133000 <description>Disable shortcut</description>
133005 <description>Enable shortcut</description>
133012 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
133018 <description>Disable shortcut</description>
133023 <description>Enable shortcut</description>
133030 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
133036 <description>Disable shortcut</description>
133041 <description>Enable shortcut</description>
133048 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
133054 <description>Disable shortcut</description>
133059 <description>Enable shortcut</description>
133068 <description>Enable or disable interrupt</description>
133076 <description>Enable or disable interrupt for event STOPPED</description>
133082 <description>Disable</description>
133087 <description>Enable</description>
133094 <description>Enable or disable interrupt for event ERROR</description>
133100 <description>Disable</description>
133105 <description>Enable</description>
133112 <description>Enable or disable interrupt for event SUSPENDED</description>
133118 <description>Disable</description>
133123 <description>Enable</description>
133130 <description>Enable or disable interrupt for event LASTRX</description>
133136 <description>Disable</description>
133141 <description>Enable</description>
133148 <description>Enable or disable interrupt for event LASTTX</description>
133154 <description>Disable</description>
133159 <description>Enable</description>
133166 <description>Enable or disable interrupt for event DMARXEND</description>
133172 <description>Disable</description>
133177 <description>Enable</description>
133184 <description>Enable or disable interrupt for event DMARXREADY</description>
133190 <description>Disable</description>
133195 <description>Enable</description>
133202 <description>Enable or disable interrupt for event DMARXBUSERROR</description>
133208 <description>Disable</description>
133213 <description>Enable</description>
133220 <description>Enable or disable interrupt for event DMARXMATCH[0]</description>
133226 <description>Disable</description>
133231 <description>Enable</description>
133238 <description>Enable or disable interrupt for event DMARXMATCH[1]</description>
133244 <description>Disable</description>
133249 <description>Enable</description>
133256 <description>Enable or disable interrupt for event DMARXMATCH[2]</description>
133262 <description>Disable</description>
133267 <description>Enable</description>
133274 <description>Enable or disable interrupt for event DMARXMATCH[3]</description>
133280 <description>Disable</description>
133285 <description>Enable</description>
133292 <description>Enable or disable interrupt for event DMATXEND</description>
133298 <description>Disable</description>
133303 <description>Enable</description>
133310 <description>Enable or disable interrupt for event DMATXREADY</description>
133316 <description>Disable</description>
133321 <description>Enable</description>
133328 <description>Enable or disable interrupt for event DMATXBUSERROR</description>
133334 <description>Disable</description>
133339 <description>Enable</description>
133348 <description>Enable interrupt</description>
133356 <description>Write '1' to enable interrupt for event STOPPED</description>
133363 <description>Read: Disabled</description>
133368 <description>Read: Enabled</description>
133376 <description>Enable</description>
133383 <description>Write '1' to enable interrupt for event ERROR</description>
133390 <description>Read: Disabled</description>
133395 <description>Read: Enabled</description>
133403 <description>Enable</description>
133410 <description>Write '1' to enable interrupt for event SUSPENDED</description>
133417 <description>Read: Disabled</description>
133422 <description>Read: Enabled</description>
133430 <description>Enable</description>
133437 <description>Write '1' to enable interrupt for event LASTRX</description>
133444 <description>Read: Disabled</description>
133449 <description>Read: Enabled</description>
133457 <description>Enable</description>
133464 <description>Write '1' to enable interrupt for event LASTTX</description>
133471 <description>Read: Disabled</description>
133476 <description>Read: Enabled</description>
133484 <description>Enable</description>
133491 <description>Write '1' to enable interrupt for event DMARXEND</description>
133498 <description>Read: Disabled</description>
133503 <description>Read: Enabled</description>
133511 <description>Enable</description>
133518 <description>Write '1' to enable interrupt for event DMARXREADY</description>
133525 <description>Read: Disabled</description>
133530 <description>Read: Enabled</description>
133538 <description>Enable</description>
133545 <description>Write '1' to enable interrupt for event DMARXBUSERROR</description>
133552 <description>Read: Disabled</description>
133557 <description>Read: Enabled</description>
133565 <description>Enable</description>
133572 <description>Write '1' to enable interrupt for event DMARXMATCH[0]</description>
133579 <description>Read: Disabled</description>
133584 <description>Read: Enabled</description>
133592 <description>Enable</description>
133599 <description>Write '1' to enable interrupt for event DMARXMATCH[1]</description>
133606 <description>Read: Disabled</description>
133611 <description>Read: Enabled</description>
133619 <description>Enable</description>
133626 <description>Write '1' to enable interrupt for event DMARXMATCH[2]</description>
133633 <description>Read: Disabled</description>
133638 <description>Read: Enabled</description>
133646 <description>Enable</description>
133653 <description>Write '1' to enable interrupt for event DMARXMATCH[3]</description>
133660 <description>Read: Disabled</description>
133665 <description>Read: Enabled</description>
133673 <description>Enable</description>
133680 <description>Write '1' to enable interrupt for event DMATXEND</description>
133687 <description>Read: Disabled</description>
133692 <description>Read: Enabled</description>
133700 <description>Enable</description>
133707 <description>Write '1' to enable interrupt for event DMATXREADY</description>
133714 <description>Read: Disabled</description>
133719 <description>Read: Enabled</description>
133727 <description>Enable</description>
133734 <description>Write '1' to enable interrupt for event DMATXBUSERROR</description>
133741 <description>Read: Disabled</description>
133746 <description>Read: Enabled</description>
133754 <description>Enable</description>
133763 <description>Disable interrupt</description>
133771 <description>Write '1' to disable interrupt for event STOPPED</description>
133778 <description>Read: Disabled</description>
133783 <description>Read: Enabled</description>
133791 <description>Disable</description>
133798 <description>Write '1' to disable interrupt for event ERROR</description>
133805 <description>Read: Disabled</description>
133810 <description>Read: Enabled</description>
133818 <description>Disable</description>
133825 <description>Write '1' to disable interrupt for event SUSPENDED</description>
133832 <description>Read: Disabled</description>
133837 <description>Read: Enabled</description>
133845 <description>Disable</description>
133852 <description>Write '1' to disable interrupt for event LASTRX</description>
133859 <description>Read: Disabled</description>
133864 <description>Read: Enabled</description>
133872 <description>Disable</description>
133879 <description>Write '1' to disable interrupt for event LASTTX</description>
133886 <description>Read: Disabled</description>
133891 <description>Read: Enabled</description>
133899 <description>Disable</description>
133906 <description>Write '1' to disable interrupt for event DMARXEND</description>
133913 <description>Read: Disabled</description>
133918 <description>Read: Enabled</description>
133926 <description>Disable</description>
133933 <description>Write '1' to disable interrupt for event DMARXREADY</description>
133940 <description>Read: Disabled</description>
133945 <description>Read: Enabled</description>
133953 <description>Disable</description>
133960 <description>Write '1' to disable interrupt for event DMARXBUSERROR</description>
133967 <description>Read: Disabled</description>
133972 <description>Read: Enabled</description>
133980 <description>Disable</description>
133987 <description>Write '1' to disable interrupt for event DMARXMATCH[0]</description>
133994 <description>Read: Disabled</description>
133999 <description>Read: Enabled</description>
134007 <description>Disable</description>
134014 <description>Write '1' to disable interrupt for event DMARXMATCH[1]</description>
134021 <description>Read: Disabled</description>
134026 <description>Read: Enabled</description>
134034 <description>Disable</description>
134041 <description>Write '1' to disable interrupt for event DMARXMATCH[2]</description>
134048 <description>Read: Disabled</description>
134053 <description>Read: Enabled</description>
134061 <description>Disable</description>
134068 <description>Write '1' to disable interrupt for event DMARXMATCH[3]</description>
134075 <description>Read: Disabled</description>
134080 <description>Read: Enabled</description>
134088 <description>Disable</description>
134095 <description>Write '1' to disable interrupt for event DMATXEND</description>
134102 <description>Read: Disabled</description>
134107 <description>Read: Enabled</description>
134115 <description>Disable</description>
134122 <description>Write '1' to disable interrupt for event DMATXREADY</description>
134129 <description>Read: Disabled</description>
134134 <description>Read: Enabled</description>
134142 <description>Disable</description>
134149 <description>Write '1' to disable interrupt for event DMATXBUSERROR</description>
134156 <description>Read: Disabled</description>
134161 <description>Read: Enabled</description>
134169 <description>Disable</description>
134178 <description>Error source</description>
134187 <description>Overrun error</description>
134193 <description>Error did not occur</description>
134198 <description>Error occurred</description>
134205 … <description>NACK received after sending the address (write '1' to clear)</description>
134211 <description>Error did not occur</description>
134216 <description>Error occurred</description>
134223 … <description>NACK received after sending a data byte (write '1' to clear)</description>
134229 <description>Error did not occur</description>
134234 <description>Error occurred</description>
134243 <description>Enable TWIM</description>
134251 <description>Enable or disable TWIM</description>
134257 <description>Disable TWIM</description>
134262 <description>Enable TWIM</description>
134271 <description>TWI frequency. Accuracy depends on the HFCLK source selected.</description>
134279 <description>TWI master clock frequency</description>
134285 <description>100 kbps</description>
134290 <description>250 kbps</description>
134295 <description>400 kbps</description>
134300 <description>1000 kbps</description>
134309 <description>Address used in the TWI transfer</description>
134317 <description>Address used in the TWI transfer</description>
134325 <description>Unspecified</description>
134331 <description>Pin select for SCL signal</description>
134339 <description>Pin number</description>
134345 <description>Port number</description>
134351 <description>Connection</description>
134357 <description>Disconnect</description>
134362 <description>Connect</description>
134371 <description>Pin select for SDA signal</description>
134379 <description>Pin number</description>
134385 <description>Port number</description>
134391 <description>Connection</description>
134397 <description>Disconnect</description>
134402 <description>Connect</description>
134412 <description>Unspecified</description>
134418 <description>Unspecified</description>
134424 <description>RAM buffer start address</description>
134432 …<description>RAM buffer start address for this EasyDMA channel. This address is a word aligned Dat…
134440 <description>Maximum number of bytes in channel buffer</description>
134448 <description>Maximum number of bytes in channel buffer</description>
134456 …<description>Number of bytes transferred in the last transaction, updated after the END event. Als…
134464 …<description>Number of bytes transferred in the last transaction. In case of NACK error, includes …
134472 <description>Number of bytes transferred in the current transaction</description>
134480 …<description>Number of bytes transferred in the current transaction. Continuously updated.</descri…
134488 <description>EasyDMA list type</description>
134496 <description>List type</description>
134502 <description>Disable EasyDMA list</description>
134507 <description>Use array list</description>
134516 <description>Terminate the transaction if a BUSERROR event is detected.</description>
134529 <description>Disable</description>
134534 <description>Enable</description>
134543 … <description>Address of transaction that generated the last BUSERROR event.</description>
134558 … <description>Registers to control the behavior of the pattern matcher engine</description>
134564 <description>Configure individual match events</description>
134572 <description>Enable match filter 0</description>
134578 <description>Match filter disabled</description>
134583 <description>Match filter enabled</description>
134590 <description>Enable match filter 1</description>
134596 <description>Match filter disabled</description>
134601 <description>Match filter enabled</description>
134608 <description>Enable match filter 2</description>
134614 <description>Match filter disabled</description>
134619 <description>Match filter enabled</description>
134626 <description>Enable match filter 3</description>
134632 <description>Match filter disabled</description>
134637 <description>Match filter enabled</description>
134644 <description>Configure match filter 0 as one-shot or sticky</description>
134650 <description>Match filter stays enabled until disabled by task</description>
134655 … <description>Match filter stays enabled until next data word is received</description>
134662 <description>Configure match filter 1 as one-shot or sticky</description>
134668 <description>Match filter stays enabled until disabled by task</description>
134673 … <description>Match filter stays enabled until next data word is received</description>
134680 <description>Configure match filter 2 as one-shot or sticky</description>
134686 <description>Match filter stays enabled until disabled by task</description>
134691 … <description>Match filter stays enabled until next data word is received</description>
134698 <description>Configure match filter 3 as one-shot or sticky</description>
134704 <description>Match filter stays enabled until disabled by task</description>
134709 … <description>Match filter stays enabled until next data word is received</description>
134720 …<description>Description collection: The data to look for - any match will trigger the MATCH[n] ev…
134728 <description>Data to look for</description>
134738 <description>Unspecified</description>
134744 <description>RAM buffer start address</description>
134752 …<description>RAM buffer start address for this EasyDMA channel. This address is a word aligned Dat…
134760 <description>Maximum number of bytes in channel buffer</description>
134768 <description>Maximum number of bytes in channel buffer</description>
134776 …<description>Number of bytes transferred in the last transaction, updated after the END event. Als…
134784 …<description>Number of bytes transferred in the last transaction. In case of NACK error, includes …
134792 <description>Number of bytes transferred in the current transaction</description>
134800 …<description>Number of bytes transferred in the current transaction. Continuously updated.</descri…
134808 <description>EasyDMA list type</description>
134816 <description>List type</description>
134822 <description>Disable EasyDMA list</description>
134827 <description>Use array list</description>
134836 <description>Terminate the transaction if a BUSERROR event is detected.</description>
134849 <description>Disable</description>
134854 <description>Enable</description>
134863 … <description>Address of transaction that generated the last BUSERROR event.</description>
134882 <description>I2C compatible Two-Wire Slave Interface with EasyDMA 0</description>
134902 <description>Stop TWI transaction</description>
134910 <description>Stop TWI transaction</description>
134916 <description>Trigger task</description>
134925 <description>Suspend TWI transaction</description>
134933 <description>Suspend TWI transaction</description>
134939 <description>Trigger task</description>
134948 <description>Resume TWI transaction</description>
134956 <description>Resume TWI transaction</description>
134962 <description>Trigger task</description>
134971 <description>Prepare the TWI slave to respond to a write command</description>
134979 <description>Prepare the TWI slave to respond to a write command</description>
134985 <description>Trigger task</description>
134994 <description>Prepare the TWI slave to respond to a read command</description>
135002 <description>Prepare the TWI slave to respond to a read command</description>
135008 <description>Trigger task</description>
135017 <description>Peripheral tasks.</description>
135023 <description>Peripheral tasks.</description>
135031 …<description>Description collection: Enables the MATCH[n] event by setting the ENABLE[n] bit in th…
135039 …<description>Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register.</desc…
135045 <description>Trigger task</description>
135056 …<description>Description collection: Disables the MATCH[n] event by clearing the ENABLE[n] bit in …
135064 …<description>Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register.</de…
135070 <description>Trigger task</description>
135081 <description>Subscribe configuration for task STOP</description>
135089 <description>DPPI channel that task STOP will subscribe to</description>
135100 <description>Disable subscription</description>
135105 <description>Enable subscription</description>
135114 <description>Subscribe configuration for task SUSPEND</description>
135122 <description>DPPI channel that task SUSPEND will subscribe to</description>
135133 <description>Disable subscription</description>
135138 <description>Enable subscription</description>
135147 <description>Subscribe configuration for task RESUME</description>
135155 <description>DPPI channel that task RESUME will subscribe to</description>
135166 <description>Disable subscription</description>
135171 <description>Enable subscription</description>
135180 <description>Subscribe configuration for task PREPARERX</description>
135188 <description>DPPI channel that task PREPARERX will subscribe to</description>
135199 <description>Disable subscription</description>
135204 <description>Enable subscription</description>
135213 <description>Subscribe configuration for task PREPARETX</description>
135221 <description>DPPI channel that task PREPARETX will subscribe to</description>
135232 <description>Disable subscription</description>
135237 <description>Enable subscription</description>
135246 <description>Subscribe configuration for tasks</description>
135252 <description>Subscribe configuration for tasks</description>
135260 … <description>Description collection: Subscribe configuration for task ENABLEMATCH[n]</description>
135268 <description>DPPI channel that task ENABLEMATCH[n] will subscribe to</description>
135279 <description>Disable subscription</description>
135284 <description>Enable subscription</description>
135295 …<description>Description collection: Subscribe configuration for task DISABLEMATCH[n]</description>
135303 … <description>DPPI channel that task DISABLEMATCH[n] will subscribe to</description>
135314 <description>Disable subscription</description>
135319 <description>Enable subscription</description>
135330 <description>TWI stopped</description>
135338 <description>TWI stopped</description>
135344 <description>Event not generated</description>
135349 <description>Event generated</description>
135358 <description>TWI error</description>
135366 <description>TWI error</description>
135372 <description>Event not generated</description>
135377 <description>Event generated</description>
135386 <description>Write command received</description>
135394 <description>Write command received</description>
135400 <description>Event not generated</description>
135405 <description>Event generated</description>
135414 <description>Read command received</description>
135422 <description>Read command received</description>
135428 <description>Event not generated</description>
135433 <description>Event generated</description>
135442 <description>Peripheral events.</description>
135448 <description>Peripheral events.</description>
135454 <description>Generated after all MAXCNT bytes have been transferred</description>
135462 <description>Generated after all MAXCNT bytes have been transferred</description>
135468 <description>Event not generated</description>
135473 <description>Event generated</description>
135482 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
135490 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
135496 <description>Event not generated</description>
135501 <description>Event generated</description>
135510 <description>An error occured during the bus transfer.</description>
135518 <description>An error occured during the bus transfer.</description>
135524 <description>Event not generated</description>
135529 <description>Event generated</description>
135540 … <description>Description collection: Pattern match is detected on the DMA data bus.</description>
135548 <description>Pattern match is detected on the DMA data bus.</description>
135554 <description>Event not generated</description>
135559 <description>Event generated</description>
135569 <description>Peripheral events.</description>
135575 <description>Generated after all MAXCNT bytes have been transferred</description>
135583 <description>Generated after all MAXCNT bytes have been transferred</description>
135589 <description>Event not generated</description>
135594 <description>Event generated</description>
135603 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
135611 …description>Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, al…
135617 <description>Event not generated</description>
135622 <description>Event generated</description>
135631 <description>An error occured during the bus transfer.</description>
135639 <description>An error occured during the bus transfer.</description>
135645 <description>Event not generated</description>
135650 <description>Event generated</description>
135661 <description>Publish configuration for event STOPPED</description>
135669 <description>DPPI channel that event STOPPED will publish to</description>
135680 <description>Disable publishing</description>
135685 <description>Enable publishing</description>
135694 <description>Publish configuration for event ERROR</description>
135702 <description>DPPI channel that event ERROR will publish to</description>
135713 <description>Disable publishing</description>
135718 <description>Enable publishing</description>
135727 <description>Publish configuration for event WRITE</description>
135735 <description>DPPI channel that event WRITE will publish to</description>
135746 <description>Disable publishing</description>
135751 <description>Enable publishing</description>
135760 <description>Publish configuration for event READ</description>
135768 <description>DPPI channel that event READ will publish to</description>
135779 <description>Disable publishing</description>
135784 <description>Enable publishing</description>
135793 <description>Publish configuration for events</description>
135799 <description>Publish configuration for events</description>
135805 <description>Publish configuration for event END</description>
135813 <description>DPPI channel that event END will publish to</description>
135824 <description>Disable publishing</description>
135829 <description>Enable publishing</description>
135838 <description>Publish configuration for event READY</description>
135846 <description>DPPI channel that event READY will publish to</description>
135857 <description>Disable publishing</description>
135862 <description>Enable publishing</description>
135871 <description>Publish configuration for event BUSERROR</description>
135879 <description>DPPI channel that event BUSERROR will publish to</description>
135890 <description>Disable publishing</description>
135895 <description>Enable publishing</description>
135906 … <description>Description collection: Publish configuration for event MATCH[n]</description>
135914 <description>DPPI channel that event MATCH[n] will publish to</description>
135925 <description>Disable publishing</description>
135930 <description>Enable publishing</description>
135940 <description>Publish configuration for events</description>
135946 <description>Publish configuration for event END</description>
135954 <description>DPPI channel that event END will publish to</description>
135965 <description>Disable publishing</description>
135970 <description>Enable publishing</description>
135979 <description>Publish configuration for event READY</description>
135987 <description>DPPI channel that event READY will publish to</description>
135998 <description>Disable publishing</description>
136003 <description>Enable publishing</description>
136012 <description>Publish configuration for event BUSERROR</description>
136020 <description>DPPI channel that event BUSERROR will publish to</description>
136031 <description>Disable publishing</description>
136036 <description>Enable publishing</description>
136047 <description>Shortcuts between local events and tasks</description>
136055 <description>Shortcut between event WRITE and task SUSPEND</description>
136061 <description>Disable shortcut</description>
136066 <description>Enable shortcut</description>
136073 <description>Shortcut between event READ and task SUSPEND</description>
136079 <description>Disable shortcut</description>
136084 <description>Enable shortcut</description>
136091 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows daisy-ch…
136097 <description>Disable shortcut</description>
136102 <description>Enable shortcut</description>
136109 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows daisy-ch…
136115 <description>Disable shortcut</description>
136120 <description>Enable shortcut</description>
136127 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows daisy-ch…
136133 <description>Disable shortcut</description>
136138 <description>Enable shortcut</description>
136145 …<description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows daisy-ch…
136151 <description>Disable shortcut</description>
136156 <description>Enable shortcut</description>
136163 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
136169 <description>Disable shortcut</description>
136174 <description>Enable shortcut</description>
136181 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
136187 <description>Disable shortcut</description>
136192 <description>Enable shortcut</description>
136199 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
136205 <description>Disable shortcut</description>
136210 <description>Enable shortcut</description>
136217 … <description>Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n]</description>
136223 <description>Disable shortcut</description>
136228 <description>Enable shortcut</description>
136237 <description>Enable or disable interrupt</description>
136245 <description>Enable or disable interrupt for event STOPPED</description>
136251 <description>Disable</description>
136256 <description>Enable</description>
136263 <description>Enable or disable interrupt for event ERROR</description>
136269 <description>Disable</description>
136274 <description>Enable</description>
136281 <description>Enable or disable interrupt for event WRITE</description>
136287 <description>Disable</description>
136292 <description>Enable</description>
136299 <description>Enable or disable interrupt for event READ</description>
136305 <description>Disable</description>
136310 <description>Enable</description>
136317 <description>Enable or disable interrupt for event DMARXEND</description>
136323 <description>Disable</description>
136328 <description>Enable</description>
136335 <description>Enable or disable interrupt for event DMARXREADY</description>
136341 <description>Disable</description>
136346 <description>Enable</description>
136353 <description>Enable or disable interrupt for event DMARXBUSERROR</description>
136359 <description>Disable</description>
136364 <description>Enable</description>
136371 <description>Enable or disable interrupt for event DMARXMATCH[0]</description>
136377 <description>Disable</description>
136382 <description>Enable</description>
136389 <description>Enable or disable interrupt for event DMARXMATCH[1]</description>
136395 <description>Disable</description>
136400 <description>Enable</description>
136407 <description>Enable or disable interrupt for event DMARXMATCH[2]</description>
136413 <description>Disable</description>
136418 <description>Enable</description>
136425 <description>Enable or disable interrupt for event DMARXMATCH[3]</description>
136431 <description>Disable</description>
136436 <description>Enable</description>
136443 <description>Enable or disable interrupt for event DMATXEND</description>
136449 <description>Disable</description>
136454 <description>Enable</description>
136461 <description>Enable or disable interrupt for event DMATXREADY</description>
136467 <description>Disable</description>
136472 <description>Enable</description>
136479 <description>Enable or disable interrupt for event DMATXBUSERROR</description>
136485 <description>Disable</description>
136490 <description>Enable</description>
136499 <description>Enable interrupt</description>
136507 <description>Write '1' to enable interrupt for event STOPPED</description>
136514 <description>Read: Disabled</description>
136519 <description>Read: Enabled</description>
136527 <description>Enable</description>
136534 <description>Write '1' to enable interrupt for event ERROR</description>
136541 <description>Read: Disabled</description>
136546 <description>Read: Enabled</description>
136554 <description>Enable</description>
136561 <description>Write '1' to enable interrupt for event WRITE</description>
136568 <description>Read: Disabled</description>
136573 <description>Read: Enabled</description>
136581 <description>Enable</description>
136588 <description>Write '1' to enable interrupt for event READ</description>
136595 <description>Read: Disabled</description>
136600 <description>Read: Enabled</description>
136608 <description>Enable</description>
136615 <description>Write '1' to enable interrupt for event DMARXEND</description>
136622 <description>Read: Disabled</description>
136627 <description>Read: Enabled</description>
136635 <description>Enable</description>
136642 <description>Write '1' to enable interrupt for event DMARXREADY</description>
136649 <description>Read: Disabled</description>
136654 <description>Read: Enabled</description>
136662 <description>Enable</description>
136669 <description>Write '1' to enable interrupt for event DMARXBUSERROR</description>
136676 <description>Read: Disabled</description>
136681 <description>Read: Enabled</description>
136689 <description>Enable</description>
136696 <description>Write '1' to enable interrupt for event DMARXMATCH[0]</description>
136703 <description>Read: Disabled</description>
136708 <description>Read: Enabled</description>
136716 <description>Enable</description>
136723 <description>Write '1' to enable interrupt for event DMARXMATCH[1]</description>
136730 <description>Read: Disabled</description>
136735 <description>Read: Enabled</description>
136743 <description>Enable</description>
136750 <description>Write '1' to enable interrupt for event DMARXMATCH[2]</description>
136757 <description>Read: Disabled</description>
136762 <description>Read: Enabled</description>
136770 <description>Enable</description>
136777 <description>Write '1' to enable interrupt for event DMARXMATCH[3]</description>
136784 <description>Read: Disabled</description>
136789 <description>Read: Enabled</description>
136797 <description>Enable</description>
136804 <description>Write '1' to enable interrupt for event DMATXEND</description>
136811 <description>Read: Disabled</description>
136816 <description>Read: Enabled</description>
136824 <description>Enable</description>
136831 <description>Write '1' to enable interrupt for event DMATXREADY</description>
136838 <description>Read: Disabled</description>
136843 <description>Read: Enabled</description>
136851 <description>Enable</description>
136858 <description>Write '1' to enable interrupt for event DMATXBUSERROR</description>
136865 <description>Read: Disabled</description>
136870 <description>Read: Enabled</description>
136878 <description>Enable</description>
136887 <description>Disable interrupt</description>
136895 <description>Write '1' to disable interrupt for event STOPPED</description>
136902 <description>Read: Disabled</description>
136907 <description>Read: Enabled</description>
136915 <description>Disable</description>
136922 <description>Write '1' to disable interrupt for event ERROR</description>
136929 <description>Read: Disabled</description>
136934 <description>Read: Enabled</description>
136942 <description>Disable</description>
136949 <description>Write '1' to disable interrupt for event WRITE</description>
136956 <description>Read: Disabled</description>
136961 <description>Read: Enabled</description>
136969 <description>Disable</description>
136976 <description>Write '1' to disable interrupt for event READ</description>
136983 <description>Read: Disabled</description>
136988 <description>Read: Enabled</description>
136996 <description>Disable</description>
137003 <description>Write '1' to disable interrupt for event DMARXEND</description>
137010 <description>Read: Disabled</description>
137015 <description>Read: Enabled</description>
137023 <description>Disable</description>
137030 <description>Write '1' to disable interrupt for event DMARXREADY</description>
137037 <description>Read: Disabled</description>
137042 <description>Read: Enabled</description>
137050 <description>Disable</description>
137057 <description>Write '1' to disable interrupt for event DMARXBUSERROR</description>
137064 <description>Read: Disabled</description>
137069 <description>Read: Enabled</description>
137077 <description>Disable</description>
137084 <description>Write '1' to disable interrupt for event DMARXMATCH[0]</description>
137091 <description>Read: Disabled</description>
137096 <description>Read: Enabled</description>
137104 <description>Disable</description>
137111 <description>Write '1' to disable interrupt for event DMARXMATCH[1]</description>
137118 <description>Read: Disabled</description>
137123 <description>Read: Enabled</description>
137131 <description>Disable</description>
137138 <description>Write '1' to disable interrupt for event DMARXMATCH[2]</description>
137145 <description>Read: Disabled</description>
137150 <description>Read: Enabled</description>
137158 <description>Disable</description>
137165 <description>Write '1' to disable interrupt for event DMARXMATCH[3]</description>
137172 <description>Read: Disabled</description>
137177 <description>Read: Enabled</description>
137185 <description>Disable</description>
137192 <description>Write '1' to disable interrupt for event DMATXEND</description>
137199 <description>Read: Disabled</description>
137204 <description>Read: Enabled</description>
137212 <description>Disable</description>
137219 <description>Write '1' to disable interrupt for event DMATXREADY</description>
137226 <description>Read: Disabled</description>
137231 <description>Read: Enabled</description>
137239 <description>Disable</description>
137246 <description>Write '1' to disable interrupt for event DMATXBUSERROR</description>
137253 <description>Read: Disabled</description>
137258 <description>Read: Enabled</description>
137266 <description>Disable</description>
137275 <description>Error source</description>
137284 <description>RX buffer overflow detected, and prevented</description>
137290 <description>Error did not occur</description>
137295 <description>Error occurred</description>
137302 <description>NACK sent after receiving a data byte</description>
137308 <description>Error did not occur</description>
137313 <description>Error occurred</description>
137320 <description>TX buffer over-read detected, and prevented</description>
137326 <description>Error did not occur</description>
137331 <description>Error occurred</description>
137340 <description>Status register indicating which address had a match</description>
137348 …<description>Indication of which address in ADDRESS that matched the incoming address</description>
137356 <description>Enable TWIS</description>
137364 <description>Enable or disable TWIS</description>
137370 <description>Disable TWIS</description>
137375 <description>Enable TWIS</description>
137386 <description>Description collection: TWI slave address n</description>
137394 <description>TWI slave address</description>
137402 <description>Configuration register for the address match mechanism</description>
137410 <description>Enable or disable address matching on ADDRESS[0]</description>
137416 <description>Disabled</description>
137421 <description>Enabled</description>
137428 <description>Enable or disable address matching on ADDRESS[1]</description>
137434 <description>Disabled</description>
137439 <description>Enabled</description>
137448 …<description>Over-read character. Character sent out in case of an over-read of the transmit buffe…
137456 …<description>Over-read character. Character sent out in case of an over-read of the transmit buffe…
137464 <description>Unspecified</description>
137470 <description>Pin select for SCL signal</description>
137478 <description>Pin number</description>
137484 <description>Port number</description>
137490 <description>Connection</description>
137496 <description>Disconnect</description>
137501 <description>Connect</description>
137510 <description>Pin select for SDA signal</description>
137518 <description>Pin number</description>
137524 <description>Port number</description>
137530 <description>Connection</description>
137536 <description>Disconnect</description>
137541 <description>Connect</description>
137551 <description>Unspecified</description>
137557 <description>Unspecified</description>
137563 <description>RAM buffer start address</description>
137571 …<description>RAM buffer start address for this EasyDMA channel. This address is a word aligned Dat…
137579 <description>Maximum number of bytes in channel buffer</description>
137587 <description>Maximum number of bytes in channel buffer</description>
137595 …<description>Number of bytes transferred in the last transaction, updated after the END event. Als…
137603 …<description>Number of bytes transferred in the last transaction. In case of NACK error, includes …
137611 <description>Number of bytes transferred in the current transaction</description>
137619 …<description>Number of bytes transferred in the current transaction. Continuously updated.</descri…
137627 <description>EasyDMA list type</description>
137635 <description>List type</description>
137641 <description>Disable EasyDMA list</description>
137646 <description>Use array list</description>
137655 <description>Terminate the transaction if a BUSERROR event is detected.</description>
137668 <description>Disable</description>
137673 <description>Enable</description>
137682 … <description>Address of transaction that generated the last BUSERROR event.</description>
137697 … <description>Registers to control the behavior of the pattern matcher engine</description>
137703 <description>Configure individual match events</description>
137711 <description>Enable match filter 0</description>
137717 <description>Match filter disabled</description>
137722 <description>Match filter enabled</description>
137729 <description>Enable match filter 1</description>
137735 <description>Match filter disabled</description>
137740 <description>Match filter enabled</description>
137747 <description>Enable match filter 2</description>
137753 <description>Match filter disabled</description>
137758 <description>Match filter enabled</description>
137765 <description>Enable match filter 3</description>
137771 <description>Match filter disabled</description>
137776 <description>Match filter enabled</description>
137783 <description>Configure match filter 0 as one-shot or sticky</description>
137789 <description>Match filter stays enabled until disabled by task</description>
137794 … <description>Match filter stays enabled until next data word is received</description>
137801 <description>Configure match filter 1 as one-shot or sticky</description>
137807 <description>Match filter stays enabled until disabled by task</description>
137812 … <description>Match filter stays enabled until next data word is received</description>
137819 <description>Configure match filter 2 as one-shot or sticky</description>
137825 <description>Match filter stays enabled until disabled by task</description>
137830 … <description>Match filter stays enabled until next data word is received</description>
137837 <description>Configure match filter 3 as one-shot or sticky</description>
137843 <description>Match filter stays enabled until disabled by task</description>
137848 … <description>Match filter stays enabled until next data word is received</description>
137859 …<description>Description collection: The data to look for - any match will trigger the MATCH[n] ev…
137867 <description>Data to look for</description>
137877 <description>Unspecified</description>
137883 <description>RAM buffer start address</description>
137891 …<description>RAM buffer start address for this EasyDMA channel. This address is a word aligned Dat…
137899 <description>Maximum number of bytes in channel buffer</description>
137907 <description>Maximum number of bytes in channel buffer</description>
137915 …<description>Number of bytes transferred in the last transaction, updated after the END event. Als…
137923 …<description>Number of bytes transferred in the last transaction. In case of NACK error, includes …
137931 <description>Number of bytes transferred in the current transaction</description>
137939 …<description>Number of bytes transferred in the current transaction. Continuously updated.</descri…
137947 <description>EasyDMA list type</description>
137955 <description>List type</description>
137961 <description>Disable EasyDMA list</description>
137966 <description>Use array list</description>
137975 <description>Terminate the transaction if a BUSERROR event is detected.</description>
137988 <description>Disable</description>
137993 <description>Enable</description>
138002 … <description>Address of transaction that generated the last BUSERROR event.</description>
138021 <description>UART with EasyDMA 1</description>
138033 <description>Serial Peripheral Interface Master with EasyDMA 3</description>
138044 <description>SPI Slave 2</description>
138056 <description>I2C compatible Two-Wire Master Interface with EasyDMA 1</description>
138068 <description>I2C compatible Two-Wire Slave Interface with EasyDMA 1</description>
138080 <description>UART with EasyDMA 2</description>
138092 <description>Distributed programmable peripheral interconnect controller 5</description>
138100 <description>Timer/Counter 4</description>
138111 <description>Timer/Counter 5</description>
138122 <description>Pulse width modulation unit 2</description>
138133 <description>Serial Peripheral Interface Master with EasyDMA 4</description>
138144 <description>SPI Slave 3</description>
138156 <description>I2C compatible Two-Wire Master Interface with EasyDMA 2</description>
138168 <description>I2C compatible Two-Wire Slave Interface with EasyDMA 2</description>
138180 <description>UART with EasyDMA 3</description>
138192 <description>Serial Peripheral Interface Master with EasyDMA 5</description>
138203 <description>SPI Slave 4</description>
138215 <description>I2C compatible Two-Wire Master Interface with EasyDMA 3</description>
138227 <description>I2C compatible Two-Wire Slave Interface with EasyDMA 3</description>
138239 <description>UART with EasyDMA 4</description>
138251 <description>Distributed programmable peripheral interconnect controller 6</description>
138259 <description>Timer/Counter 6</description>
138270 <description>Timer/Counter 7</description>
138281 <description>Pulse width modulation unit 3</description>
138292 <description>Serial Peripheral Interface Master with EasyDMA 6</description>
138303 <description>SPI Slave 5</description>
138315 <description>I2C compatible Two-Wire Master Interface with EasyDMA 4</description>
138327 <description>I2C compatible Two-Wire Slave Interface with EasyDMA 4</description>
138339 <description>UART with EasyDMA 5</description>
138351 <description>Serial Peripheral Interface Master with EasyDMA 7</description>
138362 <description>SPI Slave 6</description>
138374 <description>I2C compatible Two-Wire Master Interface with EasyDMA 5</description>
138386 <description>I2C compatible Two-Wire Slave Interface with EasyDMA 5</description>
138398 <description>UART with EasyDMA 6</description>
138410 <description>Distributed programmable peripheral interconnect controller 7</description>
138418 <description>Timer/Counter 8</description>
138429 <description>Timer/Counter 9</description>
138440 <description>Pulse width modulation unit 4</description>
138451 <description>Serial Peripheral Interface Master with EasyDMA 8</description>
138462 <description>SPI Slave 7</description>
138474 <description>I2C compatible Two-Wire Master Interface with EasyDMA 6</description>
138486 <description>I2C compatible Two-Wire Slave Interface with EasyDMA 6</description>
138498 <description>UART with EasyDMA 7</description>
138510 <description>Serial Peripheral Interface Master with EasyDMA 9</description>
138521 <description>SPI Slave 8</description>
138533 <description>I2C compatible Two-Wire Master Interface with EasyDMA 7</description>
138545 <description>I2C compatible Two-Wire Slave Interface with EasyDMA 7</description>
138557 <description>UART with EasyDMA 8</description>