Lines Matching refs:index
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1020 uint8_t index) in nrf_spu_periph_perm_present_get() argument
1022 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT); in nrf_spu_periph_perm_present_get()
1023 return (p_reg->PERIPH[index].PERM & SPU_PERIPH_PERM_PRESENT_Msk) >> in nrf_spu_periph_perm_present_get()
1029 uint8_t index) in nrf_spu_periph_perm_ownerprog_get() argument
1031 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT); in nrf_spu_periph_perm_ownerprog_get()
1032 return (p_reg->PERIPH[index].PERM & SPU_PERIPH_PERM_OWNERPROG_Msk) >> in nrf_spu_periph_perm_ownerprog_get()
1038 uint8_t index) in nrf_spu_periph_perm_lock_get() argument
1040 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT); in nrf_spu_periph_perm_lock_get()
1041 return (p_reg->PERIPH[index].PERM & SPU_PERIPH_PERM_LOCK_Msk) >> in nrf_spu_periph_perm_lock_get()
1047 uint8_t index) in nrf_spu_periph_perm_block_get() argument
1049 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT); in nrf_spu_periph_perm_block_get()
1050 return (p_reg->PERIPH[index].PERM & SPU_PERIPH_PERM_BLOCK_Msk) >> in nrf_spu_periph_perm_block_get()
1056 uint8_t index) in nrf_spu_periph_perm_dmasec_get() argument
1058 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT); in nrf_spu_periph_perm_dmasec_get()
1059 return (p_reg->PERIPH[index].PERM & SPU_PERIPH_PERM_DMASEC_Msk) >> in nrf_spu_periph_perm_dmasec_get()
1064 uint8_t index) in nrf_spu_periph_perm_secattr_get() argument
1066 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT); in nrf_spu_periph_perm_secattr_get()
1067 return (p_reg->PERIPH[index].PERM & SPU_PERIPH_PERM_SECATTR_Msk) >> in nrf_spu_periph_perm_secattr_get()
1072 uint8_t index) in nrf_spu_periph_perm_lock_enable() argument
1074 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT); in nrf_spu_periph_perm_lock_enable()
1075 p_reg->PERIPH[index].PERM = ((p_reg->PERIPH[index].PERM & ~SPU_PERIPH_PERM_LOCK_Msk) in nrf_spu_periph_perm_lock_enable()
1082 uint8_t index) in nrf_spu_periph_perm_block_enable() argument
1084 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT); in nrf_spu_periph_perm_block_enable()
1085 p_reg->PERIPH[index].PERM = ((p_reg->PERIPH[index].PERM & ~SPU_PERIPH_PERM_BLOCK_Msk) in nrf_spu_periph_perm_block_enable()
1092 uint8_t index, in nrf_spu_periph_perm_dmasec_set() argument
1095 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT); in nrf_spu_periph_perm_dmasec_set()
1096 p_reg->PERIPH[index].PERM = ((p_reg->PERIPH[index].PERM & ~SPU_PERIPH_PERM_DMASEC_Msk) in nrf_spu_periph_perm_dmasec_set()
1103 uint8_t index, in nrf_spu_periph_perm_secattr_set() argument
1106 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT); in nrf_spu_periph_perm_secattr_set()
1107 p_reg->PERIPH[index].PERM = ((p_reg->PERIPH[index].PERM & ~SPU_PERIPH_PERM_SECATTR_Msk) in nrf_spu_periph_perm_secattr_set()
1115 uint8_t index) in nrf_spu_periph_perm_securemapping_get() argument
1117 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT); in nrf_spu_periph_perm_securemapping_get()
1119 return (nrf_spu_securemapping_t)((p_reg->PERIPH[index].PERM in nrf_spu_periph_perm_securemapping_get()
1125 uint8_t index) in nrf_spu_periph_perm_dma_get() argument
1127 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT); in nrf_spu_periph_perm_dma_get()
1129 return (nrf_spu_dma_t)((p_reg->PERIPH[index].PERM & SPU_PERIPH_PERM_DMA_Msk) >> in nrf_spu_periph_perm_dma_get()
1135 uint8_t index) in nrf_spu_periph_perm_ownerid_get() argument
1137 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT); in nrf_spu_periph_perm_ownerid_get()
1139 return (nrf_owner_t)((p_reg->PERIPH[index].PERM & SPU_PERIPH_PERM_OWNERID_Msk) >> in nrf_spu_periph_perm_ownerid_get()
1144 uint8_t index, in nrf_spu_periph_perm_ownerid_set() argument
1147 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT); in nrf_spu_periph_perm_ownerid_set()
1149 p_reg->PERIPH[index].PERM = ((p_reg->PERIPH[index].PERM & ~SPU_PERIPH_PERM_OWNERID_Msk) | in nrf_spu_periph_perm_ownerid_set()
1157 uint8_t index, in nrf_spu_feature_secattr_get() argument
1164 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_CHANNEL_COUNT); in nrf_spu_feature_secattr_get()
1165 return (p_reg->FEATURE.IPCT.CH[index] in nrf_spu_feature_secattr_get()
1170 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_INTERRUPT_COUNT); in nrf_spu_feature_secattr_get()
1171 return (p_reg->FEATURE.IPCT.INTERRUPT[index] in nrf_spu_feature_secattr_get()
1177 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_COUNT); in nrf_spu_feature_secattr_get()
1178 return (p_reg->FEATURE.DPPIC.CH[index] in nrf_spu_feature_secattr_get()
1183 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP_COUNT); in nrf_spu_feature_secattr_get()
1184 return (p_reg->FEATURE.DPPIC.CHG[index] in nrf_spu_feature_secattr_get()
1189 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_secattr_get()
1191 return (p_reg->FEATURE.GPIOTE[index].CH[subindex] in nrf_spu_feature_secattr_get()
1196 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_secattr_get()
1198 return (p_reg->FEATURE.GPIOTE[index].INTERRUPT[subindex] in nrf_spu_feature_secattr_get()
1203 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIO_COUNT); in nrf_spu_feature_secattr_get()
1205 return (p_reg->FEATURE.GPIO[index].PIN[subindex] in nrf_spu_feature_secattr_get()
1210 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_CC_COUNT); in nrf_spu_feature_secattr_get()
1211 return (p_reg->FEATURE.GRTC.CC[index] in nrf_spu_feature_secattr_get()
1221 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_INTERRUPT_COUNT); in nrf_spu_feature_secattr_get()
1222 return (p_reg->FEATURE.GRTC.INTERRUPT[index] in nrf_spu_feature_secattr_get()
1229 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELL_BELL_COUNT); in nrf_spu_feature_secattr_get()
1230 return (p_reg->FEATURE.BELLS.DOMAIN[index].BELL[subindex] in nrf_spu_feature_secattr_get()
1235 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_TASKS_COUNT); in nrf_spu_feature_secattr_get()
1236 return (p_reg->FEATURE.BELLS.PROCESSOR[index].TASKS[subindex] in nrf_spu_feature_secattr_get()
1241 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_EVENTS_COUNT); in nrf_spu_feature_secattr_get()
1242 return (p_reg->FEATURE.BELLS.PROCESSOR[index].EVENTS[subindex] in nrf_spu_feature_secattr_get()
1247 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_INTERRUPT_COUNT); in nrf_spu_feature_secattr_get()
1248 return (p_reg->FEATURE.BELLS.PROCESSOR[index].INTERRUPT[subindex] in nrf_spu_feature_secattr_get()
1256 NRFX_ASSERT(index < NRF_SPU_FEATURE_TDD_COUNT); in nrf_spu_feature_secattr_get()
1257 return (p_reg->FEATURE.TDD[index] in nrf_spu_feature_secattr_get()
1264 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_secattr_get()
1265 return (p_reg->FEATURE.MRAMC[index].WAITSTATES in nrf_spu_feature_secattr_get()
1270 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_secattr_get()
1271 return (p_reg->FEATURE.MRAMC[index].AUTODPOWERDOWN in nrf_spu_feature_secattr_get()
1276 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_secattr_get()
1277 return (p_reg->FEATURE.MRAMC[index].READY in nrf_spu_feature_secattr_get()
1290 uint8_t index, in nrf_spu_feature_lock_get() argument
1297 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_CHANNEL_COUNT); in nrf_spu_feature_lock_get()
1298 return (p_reg->FEATURE.IPCT.CH[index] in nrf_spu_feature_lock_get()
1303 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_INTERRUPT_COUNT); in nrf_spu_feature_lock_get()
1304 return (p_reg->FEATURE.IPCT.INTERRUPT[index] in nrf_spu_feature_lock_get()
1310 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_COUNT); in nrf_spu_feature_lock_get()
1311 return (p_reg->FEATURE.DPPIC.CH[index] in nrf_spu_feature_lock_get()
1316 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP_COUNT); in nrf_spu_feature_lock_get()
1317 return (p_reg->FEATURE.DPPIC.CHG[index] in nrf_spu_feature_lock_get()
1322 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_lock_get()
1324 return (p_reg->FEATURE.GPIOTE[index].CH[subindex] in nrf_spu_feature_lock_get()
1329 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_lock_get()
1331 return (p_reg->FEATURE.GPIOTE[index].INTERRUPT[subindex] in nrf_spu_feature_lock_get()
1336 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIO_COUNT); in nrf_spu_feature_lock_get()
1338 return (p_reg->FEATURE.GPIO[index].PIN[subindex] in nrf_spu_feature_lock_get()
1343 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_CC_COUNT); in nrf_spu_feature_lock_get()
1344 return (p_reg->FEATURE.GRTC.CC[index] in nrf_spu_feature_lock_get()
1354 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_INTERRUPT_COUNT); in nrf_spu_feature_lock_get()
1355 return (p_reg->FEATURE.GRTC.INTERRUPT[index] in nrf_spu_feature_lock_get()
1362 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELL_BELL_COUNT); in nrf_spu_feature_lock_get()
1363 return (p_reg->FEATURE.BELLS.DOMAIN[index].BELL[subindex] in nrf_spu_feature_lock_get()
1368 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_TASKS_COUNT); in nrf_spu_feature_lock_get()
1369 return (p_reg->FEATURE.BELLS.PROCESSOR[index].TASKS[subindex] in nrf_spu_feature_lock_get()
1374 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_EVENTS_COUNT); in nrf_spu_feature_lock_get()
1375 return (p_reg->FEATURE.BELLS.PROCESSOR[index].EVENTS[subindex] in nrf_spu_feature_lock_get()
1380 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_INTERRUPT_COUNT); in nrf_spu_feature_lock_get()
1381 return (p_reg->FEATURE.BELLS.PROCESSOR[index].INTERRUPT[subindex] in nrf_spu_feature_lock_get()
1389 NRFX_ASSERT(index < NRF_SPU_FEATURE_TDD_COUNT); in nrf_spu_feature_lock_get()
1390 return (p_reg->FEATURE.TDD[index] in nrf_spu_feature_lock_get()
1397 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_lock_get()
1398 return (p_reg->FEATURE.MRAMC[index].WAITSTATES in nrf_spu_feature_lock_get()
1403 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_lock_get()
1404 return (p_reg->FEATURE.MRAMC[index].AUTODPOWERDOWN in nrf_spu_feature_lock_get()
1409 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_lock_get()
1410 return (p_reg->FEATURE.MRAMC[index].READY in nrf_spu_feature_lock_get()
1424 uint8_t index, in nrf_spu_feature_block_get() argument
1431 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_CHANNEL_COUNT); in nrf_spu_feature_block_get()
1432 return (p_reg->FEATURE.IPCT.CH[index] in nrf_spu_feature_block_get()
1437 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_INTERRUPT_COUNT); in nrf_spu_feature_block_get()
1438 return (p_reg->FEATURE.IPCT.INTERRUPT[index] in nrf_spu_feature_block_get()
1444 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_COUNT); in nrf_spu_feature_block_get()
1445 return (p_reg->FEATURE.DPPIC.CH[index] in nrf_spu_feature_block_get()
1450 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP_COUNT); in nrf_spu_feature_block_get()
1451 return (p_reg->FEATURE.DPPIC.CHG[index] in nrf_spu_feature_block_get()
1456 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_block_get()
1458 return (p_reg->FEATURE.GPIOTE[index].CH[subindex] in nrf_spu_feature_block_get()
1463 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_block_get()
1465 return (p_reg->FEATURE.GPIOTE[index].INTERRUPT[subindex] in nrf_spu_feature_block_get()
1470 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIO_COUNT); in nrf_spu_feature_block_get()
1472 return (p_reg->FEATURE.GPIO[index].PIN[subindex] in nrf_spu_feature_block_get()
1477 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_CC_COUNT); in nrf_spu_feature_block_get()
1478 return (p_reg->FEATURE.GRTC.CC[index] in nrf_spu_feature_block_get()
1488 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_INTERRUPT_COUNT); in nrf_spu_feature_block_get()
1489 return (p_reg->FEATURE.GRTC.INTERRUPT[index] in nrf_spu_feature_block_get()
1496 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELL_BELL_COUNT); in nrf_spu_feature_block_get()
1497 return (p_reg->FEATURE.BELLS.DOMAIN[index].BELL[subindex] in nrf_spu_feature_block_get()
1502 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_TASKS_COUNT); in nrf_spu_feature_block_get()
1503 return (p_reg->FEATURE.BELLS.PROCESSOR[index].TASKS[subindex] in nrf_spu_feature_block_get()
1508 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_EVENTS_COUNT); in nrf_spu_feature_block_get()
1509 return (p_reg->FEATURE.BELLS.PROCESSOR[index].EVENTS[subindex] in nrf_spu_feature_block_get()
1514 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_INTERRUPT_COUNT); in nrf_spu_feature_block_get()
1515 return (p_reg->FEATURE.BELLS.PROCESSOR[index].INTERRUPT[subindex] in nrf_spu_feature_block_get()
1523 NRFX_ASSERT(index < NRF_SPU_FEATURE_TDD_COUNT); in nrf_spu_feature_block_get()
1524 return (p_reg->FEATURE.TDD[index] in nrf_spu_feature_block_get()
1531 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_block_get()
1532 return (p_reg->FEATURE.MRAMC[index].WAITSTATES in nrf_spu_feature_block_get()
1537 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_block_get()
1538 return (p_reg->FEATURE.MRAMC[index].AUTODPOWERDOWN in nrf_spu_feature_block_get()
1543 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_block_get()
1544 return (p_reg->FEATURE.MRAMC[index].READY in nrf_spu_feature_block_get()
1559 uint8_t index, in nrf_spu_feature_ownerid_get() argument
1566 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_CHANNEL_COUNT); in nrf_spu_feature_ownerid_get()
1567 return (nrf_owner_t)((p_reg->FEATURE.IPCT.CH[index] in nrf_spu_feature_ownerid_get()
1572 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_INTERRUPT_COUNT); in nrf_spu_feature_ownerid_get()
1573 return (nrf_owner_t)((p_reg->FEATURE.IPCT.INTERRUPT[index] in nrf_spu_feature_ownerid_get()
1579 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_COUNT); in nrf_spu_feature_ownerid_get()
1580 return (nrf_owner_t)((p_reg->FEATURE.DPPIC.CH[index] in nrf_spu_feature_ownerid_get()
1585 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP_COUNT); in nrf_spu_feature_ownerid_get()
1586 return (nrf_owner_t)((p_reg->FEATURE.DPPIC.CHG[index] in nrf_spu_feature_ownerid_get()
1591 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_ownerid_get()
1593 return (nrf_owner_t)((p_reg->FEATURE.GPIOTE[index].CH[subindex] in nrf_spu_feature_ownerid_get()
1598 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_ownerid_get()
1600 return (nrf_owner_t)((p_reg->FEATURE.GPIOTE[index].INTERRUPT[subindex] in nrf_spu_feature_ownerid_get()
1605 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIO_COUNT); in nrf_spu_feature_ownerid_get()
1607 return (nrf_owner_t)((p_reg->FEATURE.GPIO[index].PIN[subindex] in nrf_spu_feature_ownerid_get()
1612 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_CC_COUNT); in nrf_spu_feature_ownerid_get()
1613 return (nrf_owner_t)((p_reg->FEATURE.GRTC.CC[index] in nrf_spu_feature_ownerid_get()
1623 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_INTERRUPT_COUNT); in nrf_spu_feature_ownerid_get()
1624 return (nrf_owner_t)((p_reg->FEATURE.GRTC.INTERRUPT[index] in nrf_spu_feature_ownerid_get()
1631 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELL_BELL_COUNT); in nrf_spu_feature_ownerid_get()
1632 return (nrf_owner_t)((p_reg->FEATURE.BELLS.DOMAIN[index].BELL[subindex] in nrf_spu_feature_ownerid_get()
1637 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_TASKS_COUNT); in nrf_spu_feature_ownerid_get()
1638 return (nrf_owner_t)((p_reg->FEATURE.BELLS.PROCESSOR[index].TASKS[subindex] in nrf_spu_feature_ownerid_get()
1643 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_EVENTS_COUNT); in nrf_spu_feature_ownerid_get()
1644 return (nrf_owner_t)((p_reg->FEATURE.BELLS.PROCESSOR[index].EVENTS[subindex] in nrf_spu_feature_ownerid_get()
1649 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_INTERRUPT_COUNT); in nrf_spu_feature_ownerid_get()
1650 return (nrf_owner_t)((p_reg->FEATURE.BELLS.PROCESSOR[index].INTERRUPT[subindex] in nrf_spu_feature_ownerid_get()
1658 NRFX_ASSERT(index < NRF_SPU_FEATURE_TDD_COUNT); in nrf_spu_feature_ownerid_get()
1659 return (nrf_owner_t)((p_reg->FEATURE.TDD[index] in nrf_spu_feature_ownerid_get()
1666 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_ownerid_get()
1667 return (nrf_owner_t)((p_reg->FEATURE.MRAMC[index].WAITSTATES in nrf_spu_feature_ownerid_get()
1672 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_ownerid_get()
1673 return (nrf_owner_t)((p_reg->FEATURE.MRAMC[index].AUTODPOWERDOWN in nrf_spu_feature_ownerid_get()
1678 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_ownerid_get()
1679 return (nrf_owner_t)((p_reg->FEATURE.MRAMC[index].READY in nrf_spu_feature_ownerid_get()
1693 uint8_t index, in nrf_spu_feature_secattr_set() argument
1701 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_CHANNEL_COUNT); in nrf_spu_feature_secattr_set()
1702 p_reg->FEATURE.IPCT.CH[index] = in nrf_spu_feature_secattr_set()
1703 ((p_reg->FEATURE.IPCT.CH[index] & in nrf_spu_feature_secattr_set()
1712 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_INTERRUPT_COUNT); in nrf_spu_feature_secattr_set()
1713 p_reg->FEATURE.IPCT.INTERRUPT[index] = in nrf_spu_feature_secattr_set()
1714 ((p_reg->FEATURE.IPCT.INTERRUPT[index] & in nrf_spu_feature_secattr_set()
1724 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_COUNT); in nrf_spu_feature_secattr_set()
1725 p_reg->FEATURE.DPPIC.CH[index] = in nrf_spu_feature_secattr_set()
1726 ((p_reg->FEATURE.DPPIC.CH[index] & in nrf_spu_feature_secattr_set()
1735 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP_COUNT); in nrf_spu_feature_secattr_set()
1736 p_reg->FEATURE.DPPIC.CHG[index] = in nrf_spu_feature_secattr_set()
1737 ((p_reg->FEATURE.DPPIC.CHG[index] & in nrf_spu_feature_secattr_set()
1746 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_secattr_set()
1748 p_reg->FEATURE.GPIOTE[index].CH[subindex] = in nrf_spu_feature_secattr_set()
1749 ((p_reg->FEATURE.GPIOTE[index].CH[subindex] & in nrf_spu_feature_secattr_set()
1758 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_secattr_set()
1760 p_reg->FEATURE.GPIOTE[index].INTERRUPT[subindex] = in nrf_spu_feature_secattr_set()
1761 ((p_reg->FEATURE.GPIOTE[index].INTERRUPT[subindex] & in nrf_spu_feature_secattr_set()
1770 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIO_COUNT); in nrf_spu_feature_secattr_set()
1772 p_reg->FEATURE.GPIO[index].PIN[subindex] = in nrf_spu_feature_secattr_set()
1773 ((p_reg->FEATURE.GPIO[index].PIN[subindex] & in nrf_spu_feature_secattr_set()
1782 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_CC_COUNT); in nrf_spu_feature_secattr_set()
1783 p_reg->FEATURE.GRTC.CC[index] = in nrf_spu_feature_secattr_set()
1784 ((p_reg->FEATURE.GRTC.CC[index] & in nrf_spu_feature_secattr_set()
1803 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_INTERRUPT_COUNT); in nrf_spu_feature_secattr_set()
1804 p_reg->FEATURE.GRTC.INTERRUPT[index] = in nrf_spu_feature_secattr_set()
1805 ((p_reg->FEATURE.GRTC.INTERRUPT[index] & in nrf_spu_feature_secattr_set()
1816 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELL_BELL_COUNT); in nrf_spu_feature_secattr_set()
1817 p_reg->FEATURE.BELLS.DOMAIN[index].BELL[subindex] = in nrf_spu_feature_secattr_set()
1818 ((p_reg->FEATURE.BELLS.DOMAIN[index].BELL[subindex] & in nrf_spu_feature_secattr_set()
1827 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_TASKS_COUNT); in nrf_spu_feature_secattr_set()
1828 p_reg->FEATURE.BELLS.PROCESSOR[index].TASKS[subindex] = in nrf_spu_feature_secattr_set()
1829 ((p_reg->FEATURE.BELLS.PROCESSOR[index].TASKS[subindex] & in nrf_spu_feature_secattr_set()
1838 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_EVENTS_COUNT); in nrf_spu_feature_secattr_set()
1839 p_reg->FEATURE.BELLS.PROCESSOR[index].EVENTS[subindex] = in nrf_spu_feature_secattr_set()
1840 ((p_reg->FEATURE.BELLS.PROCESSOR[index].EVENTS[subindex] & in nrf_spu_feature_secattr_set()
1849 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_INTERRUPT_COUNT); in nrf_spu_feature_secattr_set()
1850 p_reg->FEATURE.BELLS.PROCESSOR[index].INTERRUPT[subindex] = in nrf_spu_feature_secattr_set()
1851 ((p_reg->FEATURE.BELLS.PROCESSOR[index].INTERRUPT[subindex] & in nrf_spu_feature_secattr_set()
1863 NRFX_ASSERT(index < NRF_SPU_FEATURE_TDD_COUNT); in nrf_spu_feature_secattr_set()
1864 p_reg->FEATURE.TDD[index] = in nrf_spu_feature_secattr_set()
1865 ((p_reg->FEATURE.TDD[index] & in nrf_spu_feature_secattr_set()
1876 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_secattr_set()
1877 p_reg->FEATURE.MRAMC[index].WAITSTATES = in nrf_spu_feature_secattr_set()
1878 ((p_reg->FEATURE.MRAMC[index].WAITSTATES & in nrf_spu_feature_secattr_set()
1887 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_secattr_set()
1888 p_reg->FEATURE.MRAMC[index].AUTODPOWERDOWN = in nrf_spu_feature_secattr_set()
1889 ((p_reg->FEATURE.MRAMC[index].AUTODPOWERDOWN & in nrf_spu_feature_secattr_set()
1898 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_secattr_set()
1899 p_reg->FEATURE.MRAMC[index].READY = in nrf_spu_feature_secattr_set()
1900 ((p_reg->FEATURE.MRAMC[index].READY & in nrf_spu_feature_secattr_set()
1917 uint8_t index, in nrf_spu_feature_lock_enable() argument
1924 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_CHANNEL_COUNT); in nrf_spu_feature_lock_enable()
1925 p_reg->FEATURE.IPCT.CH[index] = in nrf_spu_feature_lock_enable()
1926 ((p_reg->FEATURE.IPCT.CH[index] & in nrf_spu_feature_lock_enable()
1933 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_INTERRUPT_COUNT); in nrf_spu_feature_lock_enable()
1934 p_reg->FEATURE.IPCT.INTERRUPT[index] = in nrf_spu_feature_lock_enable()
1935 ((p_reg->FEATURE.IPCT.INTERRUPT[index] & in nrf_spu_feature_lock_enable()
1943 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_COUNT); in nrf_spu_feature_lock_enable()
1944 p_reg->FEATURE.DPPIC.CH[index] = in nrf_spu_feature_lock_enable()
1945 ((p_reg->FEATURE.DPPIC.CH[index] & in nrf_spu_feature_lock_enable()
1952 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP_COUNT); in nrf_spu_feature_lock_enable()
1953 p_reg->FEATURE.DPPIC.CHG[index] = in nrf_spu_feature_lock_enable()
1954 ((p_reg->FEATURE.DPPIC.CHG[index] & in nrf_spu_feature_lock_enable()
1961 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_lock_enable()
1963 p_reg->FEATURE.GPIOTE[index].CH[subindex] = in nrf_spu_feature_lock_enable()
1964 ((p_reg->FEATURE.GPIOTE[index].CH[subindex] & in nrf_spu_feature_lock_enable()
1971 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_lock_enable()
1973 p_reg->FEATURE.GPIOTE[index].INTERRUPT[subindex] = in nrf_spu_feature_lock_enable()
1974 ((p_reg->FEATURE.GPIOTE[index].INTERRUPT[subindex] & in nrf_spu_feature_lock_enable()
1981 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIO_COUNT); in nrf_spu_feature_lock_enable()
1983 p_reg->FEATURE.GPIO[index].PIN[subindex] = in nrf_spu_feature_lock_enable()
1984 ((p_reg->FEATURE.GPIO[index].PIN[subindex] & in nrf_spu_feature_lock_enable()
1991 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_CC_COUNT); in nrf_spu_feature_lock_enable()
1992 p_reg->FEATURE.GRTC.CC[index] = in nrf_spu_feature_lock_enable()
1993 ((p_reg->FEATURE.GRTC.CC[index] & in nrf_spu_feature_lock_enable()
2008 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_INTERRUPT_COUNT); in nrf_spu_feature_lock_enable()
2009 p_reg->FEATURE.GRTC.INTERRUPT[index] = in nrf_spu_feature_lock_enable()
2010 ((p_reg->FEATURE.GRTC.INTERRUPT[index] & in nrf_spu_feature_lock_enable()
2019 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELL_BELL_COUNT); in nrf_spu_feature_lock_enable()
2020 p_reg->FEATURE.BELLS.DOMAIN[index].BELL[subindex] = in nrf_spu_feature_lock_enable()
2021 ((p_reg->FEATURE.BELLS.DOMAIN[index].BELL[subindex] & in nrf_spu_feature_lock_enable()
2028 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_TASKS_COUNT); in nrf_spu_feature_lock_enable()
2029 p_reg->FEATURE.BELLS.PROCESSOR[index].TASKS[subindex] = in nrf_spu_feature_lock_enable()
2030 ((p_reg->FEATURE.BELLS.PROCESSOR[index].TASKS[subindex] & in nrf_spu_feature_lock_enable()
2037 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_EVENTS_COUNT); in nrf_spu_feature_lock_enable()
2038 p_reg->FEATURE.BELLS.PROCESSOR[index].EVENTS[subindex] = in nrf_spu_feature_lock_enable()
2039 ((p_reg->FEATURE.BELLS.PROCESSOR[index].EVENTS[subindex] & in nrf_spu_feature_lock_enable()
2046 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_INTERRUPT_COUNT); in nrf_spu_feature_lock_enable()
2047 p_reg->FEATURE.BELLS.PROCESSOR[index].INTERRUPT[subindex] = in nrf_spu_feature_lock_enable()
2048 ((p_reg->FEATURE.BELLS.PROCESSOR[index].INTERRUPT[subindex] & in nrf_spu_feature_lock_enable()
2058 NRFX_ASSERT(index < NRF_SPU_FEATURE_TDD_COUNT); in nrf_spu_feature_lock_enable()
2059 p_reg->FEATURE.TDD[index] = in nrf_spu_feature_lock_enable()
2060 ((p_reg->FEATURE.TDD[index] & in nrf_spu_feature_lock_enable()
2069 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_lock_enable()
2070 p_reg->FEATURE.MRAMC[index].WAITSTATES = in nrf_spu_feature_lock_enable()
2071 ((p_reg->FEATURE.MRAMC[index].WAITSTATES & in nrf_spu_feature_lock_enable()
2078 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_lock_enable()
2079 p_reg->FEATURE.MRAMC[index].AUTODPOWERDOWN = in nrf_spu_feature_lock_enable()
2080 ((p_reg->FEATURE.MRAMC[index].AUTODPOWERDOWN & in nrf_spu_feature_lock_enable()
2087 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_lock_enable()
2088 p_reg->FEATURE.MRAMC[index].READY = in nrf_spu_feature_lock_enable()
2089 ((p_reg->FEATURE.MRAMC[index].READY & in nrf_spu_feature_lock_enable()
2105 uint8_t index, in nrf_spu_feature_block_enable() argument
2112 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_CHANNEL_COUNT); in nrf_spu_feature_block_enable()
2113 p_reg->FEATURE.IPCT.CH[index] = in nrf_spu_feature_block_enable()
2114 ((p_reg->FEATURE.IPCT.CH[index] & in nrf_spu_feature_block_enable()
2121 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_INTERRUPT_COUNT); in nrf_spu_feature_block_enable()
2122 p_reg->FEATURE.IPCT.INTERRUPT[index] = in nrf_spu_feature_block_enable()
2123 ((p_reg->FEATURE.IPCT.INTERRUPT[index] & in nrf_spu_feature_block_enable()
2131 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_COUNT); in nrf_spu_feature_block_enable()
2132 p_reg->FEATURE.DPPIC.CH[index] = in nrf_spu_feature_block_enable()
2133 ((p_reg->FEATURE.DPPIC.CH[index] & in nrf_spu_feature_block_enable()
2140 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP_COUNT); in nrf_spu_feature_block_enable()
2141 p_reg->FEATURE.DPPIC.CHG[index] = in nrf_spu_feature_block_enable()
2142 ((p_reg->FEATURE.DPPIC.CHG[index] & in nrf_spu_feature_block_enable()
2149 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_block_enable()
2151 p_reg->FEATURE.GPIOTE[index].CH[subindex] = in nrf_spu_feature_block_enable()
2152 ((p_reg->FEATURE.GPIOTE[index].CH[subindex] & in nrf_spu_feature_block_enable()
2159 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_block_enable()
2161 p_reg->FEATURE.GPIOTE[index].INTERRUPT[subindex] = in nrf_spu_feature_block_enable()
2162 ((p_reg->FEATURE.GPIOTE[index].INTERRUPT[subindex] & in nrf_spu_feature_block_enable()
2169 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIO_COUNT); in nrf_spu_feature_block_enable()
2171 p_reg->FEATURE.GPIO[index].PIN[subindex] = in nrf_spu_feature_block_enable()
2172 ((p_reg->FEATURE.GPIO[index].PIN[subindex] & in nrf_spu_feature_block_enable()
2179 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_CC_COUNT); in nrf_spu_feature_block_enable()
2180 p_reg->FEATURE.GRTC.CC[index] = in nrf_spu_feature_block_enable()
2181 ((p_reg->FEATURE.GRTC.CC[index] & in nrf_spu_feature_block_enable()
2196 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_INTERRUPT_COUNT); in nrf_spu_feature_block_enable()
2197 p_reg->FEATURE.GRTC.INTERRUPT[index] = in nrf_spu_feature_block_enable()
2198 ((p_reg->FEATURE.GRTC.INTERRUPT[index] & in nrf_spu_feature_block_enable()
2207 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELL_BELL_COUNT); in nrf_spu_feature_block_enable()
2208 p_reg->FEATURE.BELLS.DOMAIN[index].BELL[subindex] = in nrf_spu_feature_block_enable()
2209 ((p_reg->FEATURE.BELLS.DOMAIN[index].BELL[subindex] & in nrf_spu_feature_block_enable()
2216 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_TASKS_COUNT); in nrf_spu_feature_block_enable()
2217 p_reg->FEATURE.BELLS.PROCESSOR[index].TASKS[subindex] = in nrf_spu_feature_block_enable()
2218 ((p_reg->FEATURE.BELLS.PROCESSOR[index].TASKS[subindex] & in nrf_spu_feature_block_enable()
2225 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_EVENTS_COUNT); in nrf_spu_feature_block_enable()
2226 p_reg->FEATURE.BELLS.PROCESSOR[index].EVENTS[subindex] = in nrf_spu_feature_block_enable()
2227 ((p_reg->FEATURE.BELLS.PROCESSOR[index].EVENTS[subindex] & in nrf_spu_feature_block_enable()
2234 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_INTERRUPT_COUNT); in nrf_spu_feature_block_enable()
2235 p_reg->FEATURE.BELLS.PROCESSOR[index].INTERRUPT[subindex] = in nrf_spu_feature_block_enable()
2236 ((p_reg->FEATURE.BELLS.PROCESSOR[index].INTERRUPT[subindex] & in nrf_spu_feature_block_enable()
2246 NRFX_ASSERT(index < NRF_SPU_FEATURE_TDD_COUNT); in nrf_spu_feature_block_enable()
2247 p_reg->FEATURE.TDD[index] = in nrf_spu_feature_block_enable()
2248 ((p_reg->FEATURE.TDD[index] & in nrf_spu_feature_block_enable()
2257 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_block_enable()
2258 p_reg->FEATURE.MRAMC[index].WAITSTATES = in nrf_spu_feature_block_enable()
2259 ((p_reg->FEATURE.MRAMC[index].WAITSTATES & in nrf_spu_feature_block_enable()
2266 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_block_enable()
2267 p_reg->FEATURE.MRAMC[index].AUTODPOWERDOWN = in nrf_spu_feature_block_enable()
2268 ((p_reg->FEATURE.MRAMC[index].AUTODPOWERDOWN & in nrf_spu_feature_block_enable()
2275 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_block_enable()
2276 p_reg->FEATURE.MRAMC[index].READY = in nrf_spu_feature_block_enable()
2277 ((p_reg->FEATURE.MRAMC[index].READY & in nrf_spu_feature_block_enable()
2294 uint8_t index, in nrf_spu_feature_ownerid_set() argument
2302 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_CHANNEL_COUNT); in nrf_spu_feature_ownerid_set()
2303 p_reg->FEATURE.IPCT.CH[index] = in nrf_spu_feature_ownerid_set()
2304 ((p_reg->FEATURE.IPCT.CH[index] & in nrf_spu_feature_ownerid_set()
2312 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_INTERRUPT_COUNT); in nrf_spu_feature_ownerid_set()
2313 p_reg->FEATURE.IPCT.INTERRUPT[index] = in nrf_spu_feature_ownerid_set()
2314 ((p_reg->FEATURE.IPCT.INTERRUPT[index] & in nrf_spu_feature_ownerid_set()
2323 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_COUNT); in nrf_spu_feature_ownerid_set()
2324 p_reg->FEATURE.DPPIC.CH[index] = in nrf_spu_feature_ownerid_set()
2325 ((p_reg->FEATURE.DPPIC.CH[index] & in nrf_spu_feature_ownerid_set()
2333 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP_COUNT); in nrf_spu_feature_ownerid_set()
2334 p_reg->FEATURE.DPPIC.CHG[index] = in nrf_spu_feature_ownerid_set()
2335 ((p_reg->FEATURE.DPPIC.CHG[index] & in nrf_spu_feature_ownerid_set()
2343 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_ownerid_set()
2345 p_reg->FEATURE.GPIOTE[index].CH[subindex] = in nrf_spu_feature_ownerid_set()
2346 ((p_reg->FEATURE.GPIOTE[index].CH[subindex] & in nrf_spu_feature_ownerid_set()
2354 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_ownerid_set()
2356 p_reg->FEATURE.GPIOTE[index].INTERRUPT[subindex] = in nrf_spu_feature_ownerid_set()
2357 ((p_reg->FEATURE.GPIOTE[index].INTERRUPT[subindex] & in nrf_spu_feature_ownerid_set()
2365 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIO_COUNT); in nrf_spu_feature_ownerid_set()
2367 p_reg->FEATURE.GPIO[index].PIN[subindex] = in nrf_spu_feature_ownerid_set()
2368 ((p_reg->FEATURE.GPIO[index].PIN[subindex] & in nrf_spu_feature_ownerid_set()
2376 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_CC_COUNT); in nrf_spu_feature_ownerid_set()
2377 p_reg->FEATURE.GRTC.CC[index] = in nrf_spu_feature_ownerid_set()
2378 ((p_reg->FEATURE.GRTC.CC[index] & in nrf_spu_feature_ownerid_set()
2395 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_INTERRUPT_COUNT); in nrf_spu_feature_ownerid_set()
2396 p_reg->FEATURE.GRTC.INTERRUPT[index] = in nrf_spu_feature_ownerid_set()
2397 ((p_reg->FEATURE.GRTC.INTERRUPT[index] & in nrf_spu_feature_ownerid_set()
2407 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELL_BELL_COUNT); in nrf_spu_feature_ownerid_set()
2408 p_reg->FEATURE.BELLS.DOMAIN[index].BELL[subindex] = in nrf_spu_feature_ownerid_set()
2409 ((p_reg->FEATURE.BELLS.DOMAIN[index].BELL[subindex] & in nrf_spu_feature_ownerid_set()
2417 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_TASKS_COUNT); in nrf_spu_feature_ownerid_set()
2418 p_reg->FEATURE.BELLS.PROCESSOR[index].TASKS[subindex] = in nrf_spu_feature_ownerid_set()
2419 ((p_reg->FEATURE.BELLS.PROCESSOR[index].TASKS[subindex] & in nrf_spu_feature_ownerid_set()
2427 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_EVENTS_COUNT); in nrf_spu_feature_ownerid_set()
2428 p_reg->FEATURE.BELLS.PROCESSOR[index].EVENTS[subindex] = in nrf_spu_feature_ownerid_set()
2429 ((p_reg->FEATURE.BELLS.PROCESSOR[index].EVENTS[subindex] & in nrf_spu_feature_ownerid_set()
2437 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_INTERRUPT_COUNT); in nrf_spu_feature_ownerid_set()
2438 p_reg->FEATURE.BELLS.PROCESSOR[index].INTERRUPT[subindex] = in nrf_spu_feature_ownerid_set()
2439 ((p_reg->FEATURE.BELLS.PROCESSOR[index].INTERRUPT[subindex] & in nrf_spu_feature_ownerid_set()
2450 NRFX_ASSERT(index < NRF_SPU_FEATURE_TDD_COUNT); in nrf_spu_feature_ownerid_set()
2451 p_reg->FEATURE.TDD[index] = in nrf_spu_feature_ownerid_set()
2452 ((p_reg->FEATURE.TDD[index] & in nrf_spu_feature_ownerid_set()
2462 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_ownerid_set()
2463 p_reg->FEATURE.MRAMC[index].WAITSTATES = in nrf_spu_feature_ownerid_set()
2464 ((p_reg->FEATURE.MRAMC[index].WAITSTATES & in nrf_spu_feature_ownerid_set()
2472 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_ownerid_set()
2473 p_reg->FEATURE.MRAMC[index].AUTODPOWERDOWN = in nrf_spu_feature_ownerid_set()
2474 ((p_reg->FEATURE.MRAMC[index].AUTODPOWERDOWN & in nrf_spu_feature_ownerid_set()
2482 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_ownerid_set()
2483 p_reg->FEATURE.MRAMC[index].READY = in nrf_spu_feature_ownerid_set()
2484 ((p_reg->FEATURE.MRAMC[index].READY & in nrf_spu_feature_ownerid_set()