Lines Matching refs:NRFX_ASSERT
897 NRFX_ASSERT(!(p_reg->DPPI[dppi_id].LOCK & SPU_DPPI_LOCK_LOCK_Msk)); in nrf_spu_dppi_config_set()
912 NRFX_ASSERT(!(p_reg->GPIOPORT[gpio_port].LOCK & SPU_GPIOPORT_LOCK_LOCK_Msk)); in nrf_spu_gpio_config_set()
928 NRFX_ASSERT(!(p_reg->FLASHNSC[flash_nsc_id].REGION & SPU_FLASHNSC_REGION_LOCK_Msk)); in nrf_spu_flashnsc_set()
929 NRFX_ASSERT(!(p_reg->FLASHNSC[flash_nsc_id].SIZE & SPU_FLASHNSC_SIZE_LOCK_Msk)); in nrf_spu_flashnsc_set()
943 NRFX_ASSERT(!(p_reg->RAMNSC[ram_nsc_id].REGION & SPU_RAMNSC_REGION_LOCK_Msk)); in nrf_spu_ramnsc_set()
944 NRFX_ASSERT(!(p_reg->RAMNSC[ram_nsc_id].SIZE & SPU_RAMNSC_SIZE_LOCK_Msk)); in nrf_spu_ramnsc_set()
958 NRFX_ASSERT(!(p_reg->FLASHREGION[region_id].PERM & SPU_FLASHREGION_PERM_LOCK_Msk)); in nrf_spu_flashregion_set()
971 NRFX_ASSERT(!(p_reg->RAMREGION[region_id].PERM & SPU_RAMREGION_PERM_LOCK_Msk)); in nrf_spu_ramregion_set()
984 NRFX_ASSERT(p_reg->PERIPHID[peripheral_id].PERM & SPU_PERIPHID_PERM_PRESENT_Msk); in nrf_spu_peripheral_set()
985 NRFX_ASSERT(!(p_reg->PERIPHID[peripheral_id].PERM & SPU_PERIPHID_PERM_LOCK_Msk)); in nrf_spu_peripheral_set()
998 NRFX_ASSERT(!(p_reg->EXTDOMAIN[domain_id].PERM & SPU_EXTDOMAIN_PERM_LOCK_Msk)); in nrf_spu_extdomain_set()
1022 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT); in nrf_spu_periph_perm_present_get()
1031 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT); in nrf_spu_periph_perm_ownerprog_get()
1040 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT); in nrf_spu_periph_perm_lock_get()
1049 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT); in nrf_spu_periph_perm_block_get()
1058 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT); in nrf_spu_periph_perm_dmasec_get()
1066 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT); in nrf_spu_periph_perm_secattr_get()
1074 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT); in nrf_spu_periph_perm_lock_enable()
1084 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT); in nrf_spu_periph_perm_block_enable()
1095 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT); in nrf_spu_periph_perm_dmasec_set()
1106 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT); in nrf_spu_periph_perm_secattr_set()
1117 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT); in nrf_spu_periph_perm_securemapping_get()
1127 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT); in nrf_spu_periph_perm_dma_get()
1137 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT); in nrf_spu_periph_perm_ownerid_get()
1147 NRFX_ASSERT(index < NRF_SPU_PERIPH_COUNT); in nrf_spu_periph_perm_ownerid_set()
1164 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_CHANNEL_COUNT); in nrf_spu_feature_secattr_get()
1170 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_INTERRUPT_COUNT); in nrf_spu_feature_secattr_get()
1177 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_COUNT); in nrf_spu_feature_secattr_get()
1183 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP_COUNT); in nrf_spu_feature_secattr_get()
1189 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_secattr_get()
1190 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_CHANNEL_COUNT); in nrf_spu_feature_secattr_get()
1196 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_secattr_get()
1197 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_INTERRUPT_COUNT); in nrf_spu_feature_secattr_get()
1203 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIO_COUNT); in nrf_spu_feature_secattr_get()
1204 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIO_PIN_COUNT); in nrf_spu_feature_secattr_get()
1210 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_CC_COUNT); in nrf_spu_feature_secattr_get()
1221 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_INTERRUPT_COUNT); in nrf_spu_feature_secattr_get()
1229 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELL_BELL_COUNT); in nrf_spu_feature_secattr_get()
1235 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_TASKS_COUNT); in nrf_spu_feature_secattr_get()
1241 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_EVENTS_COUNT); in nrf_spu_feature_secattr_get()
1247 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_INTERRUPT_COUNT); in nrf_spu_feature_secattr_get()
1256 NRFX_ASSERT(index < NRF_SPU_FEATURE_TDD_COUNT); in nrf_spu_feature_secattr_get()
1264 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_secattr_get()
1270 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_secattr_get()
1276 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_secattr_get()
1283 NRFX_ASSERT(0); in nrf_spu_feature_secattr_get()
1297 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_CHANNEL_COUNT); in nrf_spu_feature_lock_get()
1303 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_INTERRUPT_COUNT); in nrf_spu_feature_lock_get()
1310 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_COUNT); in nrf_spu_feature_lock_get()
1316 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP_COUNT); in nrf_spu_feature_lock_get()
1322 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_lock_get()
1323 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_CHANNEL_COUNT); in nrf_spu_feature_lock_get()
1329 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_lock_get()
1330 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_INTERRUPT_COUNT); in nrf_spu_feature_lock_get()
1336 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIO_COUNT); in nrf_spu_feature_lock_get()
1337 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIO_PIN_COUNT); in nrf_spu_feature_lock_get()
1343 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_CC_COUNT); in nrf_spu_feature_lock_get()
1354 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_INTERRUPT_COUNT); in nrf_spu_feature_lock_get()
1362 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELL_BELL_COUNT); in nrf_spu_feature_lock_get()
1368 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_TASKS_COUNT); in nrf_spu_feature_lock_get()
1374 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_EVENTS_COUNT); in nrf_spu_feature_lock_get()
1380 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_INTERRUPT_COUNT); in nrf_spu_feature_lock_get()
1389 NRFX_ASSERT(index < NRF_SPU_FEATURE_TDD_COUNT); in nrf_spu_feature_lock_get()
1397 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_lock_get()
1403 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_lock_get()
1409 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_lock_get()
1416 NRFX_ASSERT(0); in nrf_spu_feature_lock_get()
1431 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_CHANNEL_COUNT); in nrf_spu_feature_block_get()
1437 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_INTERRUPT_COUNT); in nrf_spu_feature_block_get()
1444 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_COUNT); in nrf_spu_feature_block_get()
1450 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP_COUNT); in nrf_spu_feature_block_get()
1456 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_block_get()
1457 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_CHANNEL_COUNT); in nrf_spu_feature_block_get()
1463 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_block_get()
1464 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_INTERRUPT_COUNT); in nrf_spu_feature_block_get()
1470 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIO_COUNT); in nrf_spu_feature_block_get()
1471 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIO_PIN_COUNT); in nrf_spu_feature_block_get()
1477 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_CC_COUNT); in nrf_spu_feature_block_get()
1488 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_INTERRUPT_COUNT); in nrf_spu_feature_block_get()
1496 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELL_BELL_COUNT); in nrf_spu_feature_block_get()
1502 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_TASKS_COUNT); in nrf_spu_feature_block_get()
1508 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_EVENTS_COUNT); in nrf_spu_feature_block_get()
1514 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_INTERRUPT_COUNT); in nrf_spu_feature_block_get()
1523 NRFX_ASSERT(index < NRF_SPU_FEATURE_TDD_COUNT); in nrf_spu_feature_block_get()
1531 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_block_get()
1537 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_block_get()
1543 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_block_get()
1550 NRFX_ASSERT(0); in nrf_spu_feature_block_get()
1566 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_CHANNEL_COUNT); in nrf_spu_feature_ownerid_get()
1572 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_INTERRUPT_COUNT); in nrf_spu_feature_ownerid_get()
1579 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_COUNT); in nrf_spu_feature_ownerid_get()
1585 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP_COUNT); in nrf_spu_feature_ownerid_get()
1591 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_ownerid_get()
1592 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_CHANNEL_COUNT); in nrf_spu_feature_ownerid_get()
1598 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_ownerid_get()
1599 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_INTERRUPT_COUNT); in nrf_spu_feature_ownerid_get()
1605 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIO_COUNT); in nrf_spu_feature_ownerid_get()
1606 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIO_PIN_COUNT); in nrf_spu_feature_ownerid_get()
1612 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_CC_COUNT); in nrf_spu_feature_ownerid_get()
1623 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_INTERRUPT_COUNT); in nrf_spu_feature_ownerid_get()
1631 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELL_BELL_COUNT); in nrf_spu_feature_ownerid_get()
1637 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_TASKS_COUNT); in nrf_spu_feature_ownerid_get()
1643 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_EVENTS_COUNT); in nrf_spu_feature_ownerid_get()
1649 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_INTERRUPT_COUNT); in nrf_spu_feature_ownerid_get()
1658 NRFX_ASSERT(index < NRF_SPU_FEATURE_TDD_COUNT); in nrf_spu_feature_ownerid_get()
1666 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_ownerid_get()
1672 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_ownerid_get()
1678 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_ownerid_get()
1685 NRFX_ASSERT(0); in nrf_spu_feature_ownerid_get()
1701 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_CHANNEL_COUNT); in nrf_spu_feature_secattr_set()
1712 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_INTERRUPT_COUNT); in nrf_spu_feature_secattr_set()
1724 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_COUNT); in nrf_spu_feature_secattr_set()
1735 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP_COUNT); in nrf_spu_feature_secattr_set()
1746 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_secattr_set()
1747 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_CHANNEL_COUNT); in nrf_spu_feature_secattr_set()
1758 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_secattr_set()
1759 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_INTERRUPT_COUNT); in nrf_spu_feature_secattr_set()
1770 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIO_COUNT); in nrf_spu_feature_secattr_set()
1771 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIO_PIN_COUNT); in nrf_spu_feature_secattr_set()
1782 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_CC_COUNT); in nrf_spu_feature_secattr_set()
1803 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_INTERRUPT_COUNT); in nrf_spu_feature_secattr_set()
1816 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELL_BELL_COUNT); in nrf_spu_feature_secattr_set()
1827 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_TASKS_COUNT); in nrf_spu_feature_secattr_set()
1838 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_EVENTS_COUNT); in nrf_spu_feature_secattr_set()
1849 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_INTERRUPT_COUNT); in nrf_spu_feature_secattr_set()
1863 NRFX_ASSERT(index < NRF_SPU_FEATURE_TDD_COUNT); in nrf_spu_feature_secattr_set()
1876 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_secattr_set()
1887 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_secattr_set()
1898 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_secattr_set()
1910 NRFX_ASSERT(0); in nrf_spu_feature_secattr_set()
1924 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_CHANNEL_COUNT); in nrf_spu_feature_lock_enable()
1933 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_INTERRUPT_COUNT); in nrf_spu_feature_lock_enable()
1943 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_COUNT); in nrf_spu_feature_lock_enable()
1952 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP_COUNT); in nrf_spu_feature_lock_enable()
1961 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_lock_enable()
1962 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_CHANNEL_COUNT); in nrf_spu_feature_lock_enable()
1971 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_lock_enable()
1972 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_INTERRUPT_COUNT); in nrf_spu_feature_lock_enable()
1981 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIO_COUNT); in nrf_spu_feature_lock_enable()
1982 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIO_PIN_COUNT); in nrf_spu_feature_lock_enable()
1991 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_CC_COUNT); in nrf_spu_feature_lock_enable()
2008 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_INTERRUPT_COUNT); in nrf_spu_feature_lock_enable()
2019 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELL_BELL_COUNT); in nrf_spu_feature_lock_enable()
2028 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_TASKS_COUNT); in nrf_spu_feature_lock_enable()
2037 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_EVENTS_COUNT); in nrf_spu_feature_lock_enable()
2046 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_INTERRUPT_COUNT); in nrf_spu_feature_lock_enable()
2058 NRFX_ASSERT(index < NRF_SPU_FEATURE_TDD_COUNT); in nrf_spu_feature_lock_enable()
2069 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_lock_enable()
2078 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_lock_enable()
2087 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_lock_enable()
2097 NRFX_ASSERT(0); in nrf_spu_feature_lock_enable()
2112 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_CHANNEL_COUNT); in nrf_spu_feature_block_enable()
2121 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_INTERRUPT_COUNT); in nrf_spu_feature_block_enable()
2131 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_COUNT); in nrf_spu_feature_block_enable()
2140 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP_COUNT); in nrf_spu_feature_block_enable()
2149 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_block_enable()
2150 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_CHANNEL_COUNT); in nrf_spu_feature_block_enable()
2159 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_block_enable()
2160 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_INTERRUPT_COUNT); in nrf_spu_feature_block_enable()
2169 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIO_COUNT); in nrf_spu_feature_block_enable()
2170 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIO_PIN_COUNT); in nrf_spu_feature_block_enable()
2179 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_CC_COUNT); in nrf_spu_feature_block_enable()
2196 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_INTERRUPT_COUNT); in nrf_spu_feature_block_enable()
2207 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELL_BELL_COUNT); in nrf_spu_feature_block_enable()
2216 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_TASKS_COUNT); in nrf_spu_feature_block_enable()
2225 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_EVENTS_COUNT); in nrf_spu_feature_block_enable()
2234 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_INTERRUPT_COUNT); in nrf_spu_feature_block_enable()
2246 NRFX_ASSERT(index < NRF_SPU_FEATURE_TDD_COUNT); in nrf_spu_feature_block_enable()
2257 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_block_enable()
2266 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_block_enable()
2275 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_block_enable()
2285 NRFX_ASSERT(0); in nrf_spu_feature_block_enable()
2302 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_CHANNEL_COUNT); in nrf_spu_feature_ownerid_set()
2312 NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_INTERRUPT_COUNT); in nrf_spu_feature_ownerid_set()
2323 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_COUNT); in nrf_spu_feature_ownerid_set()
2333 NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP_COUNT); in nrf_spu_feature_ownerid_set()
2343 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_ownerid_set()
2344 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_CHANNEL_COUNT); in nrf_spu_feature_ownerid_set()
2354 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIOTE_COUNT); in nrf_spu_feature_ownerid_set()
2355 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIOTE_INTERRUPT_COUNT); in nrf_spu_feature_ownerid_set()
2365 NRFX_ASSERT(index < NRF_SPU_FEATURE_GPIO_COUNT); in nrf_spu_feature_ownerid_set()
2366 NRFX_ASSERT(subindex < NRF_SPU_FEATURE_GPIO_PIN_COUNT); in nrf_spu_feature_ownerid_set()
2376 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_CC_COUNT); in nrf_spu_feature_ownerid_set()
2395 NRFX_ASSERT(index < NRF_SPU_FEATURE_GRTC_INTERRUPT_COUNT); in nrf_spu_feature_ownerid_set()
2407 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELL_BELL_COUNT); in nrf_spu_feature_ownerid_set()
2417 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_TASKS_COUNT); in nrf_spu_feature_ownerid_set()
2427 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_EVENTS_COUNT); in nrf_spu_feature_ownerid_set()
2437 NRFX_ASSERT(index < NRF_SPU_FEATURE_BELLS_INTERRUPT_COUNT); in nrf_spu_feature_ownerid_set()
2450 NRFX_ASSERT(index < NRF_SPU_FEATURE_TDD_COUNT); in nrf_spu_feature_ownerid_set()
2462 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_ownerid_set()
2472 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_ownerid_set()
2482 NRFX_ASSERT(index < NRF_SPU_FEATURE_MRAMC_COUNT); in nrf_spu_feature_ownerid_set()
2493 NRFX_ASSERT(0); in nrf_spu_feature_ownerid_set()