Lines Matching refs:LENGTH
40 envm (rx) : ORIGIN = 0x20220100, LENGTH = 128k - 0x100
41 dtim (rwx) : ORIGIN = 0x01000000, LENGTH = 7k
42 switch_code (rx) : ORIGIN = 0x01001c00, LENGTH = 1k
43 e51_itim (rwx) : ORIGIN = 0x01800000, LENGTH = 28k
44 u54_1_itim (rwx) : ORIGIN = 0x01808000, LENGTH = 28k
45 u54_2_itim (rwx) : ORIGIN = 0x01810000, LENGTH = 28k
46 u54_3_itim (rwx) : ORIGIN = 0x01818000, LENGTH = 28k
47 u54_4_itim (rwx) : ORIGIN = 0x01820000, LENGTH = 28k
48 l2lim (rwx) : ORIGIN = 0x08000000, LENGTH = 256k
49 scratchpad(rwx) : ORIGIN = 0x0A000000, LENGTH = 256k
51 ddr_cached_32bit (rwx) : ORIGIN = 0x80000000, LENGTH = 768M
52 ddr_non_cached_32bit (rwx) : ORIGIN = 0xC0000000, LENGTH = 256M
53 ddr_wcb_32bit (rwx) : ORIGIN = 0xD0000000, LENGTH = 256M
54 ddr_cached_38bit (rwx) : ORIGIN = 0x1000000000, LENGTH = 1024M
55 ddr_non_cached_38bit (rwx) : ORIGIN = 0x1400000000, LENGTH = 0k
56 ddr_wcb_38bit (rwx) : ORIGIN = 0x1800000000, LENGTH = 0k
95 PROVIDE(__envm_end = ORIGIN(envm) + LENGTH(envm));
97 PROVIDE(__l2lim_end = ORIGIN(l2lim) + LENGTH(l2lim));
99 PROVIDE(__ddr_cached_32bit_end = ORIGIN(ddr_cached_32bit) + LENGTH(ddr_cached_32bit));
101 … PROVIDE(__ddr_non_cached_32bit_end = ORIGIN(ddr_non_cached_32bit) + LENGTH(ddr_non_cached_32bit));
103 PROVIDE(__ddr_wcb_32bit_end = ORIGIN(ddr_wcb_32bit) + LENGTH(ddr_wcb_32bit));
105 PROVIDE(__ddr_cached_38bit_end = ORIGIN(ddr_cached_38bit) + LENGTH(ddr_cached_38bit));
107 … PROVIDE(__ddr_non_cached_38bit_end = ORIGIN(ddr_non_cached_38bit) + LENGTH(ddr_non_cached_38bit));
109 PROVIDE(__ddr_wcb_38bit_end = ORIGIN(ddr_wcb_38bit) + LENGTH(ddr_wcb_38bit));
111 PROVIDE(__dtim_end = ORIGIN(dtim) + LENGTH(dtim));
113 PROVIDE(__e51itim_end = ORIGIN(e51_itim) + LENGTH(e51_itim));
115 PROVIDE(__u54_1_itim_end = ORIGIN(u54_1_itim) + LENGTH(u54_1_itim));
117 PROVIDE(__u54_2_itim_end = ORIGIN(u54_2_itim) + LENGTH(u54_2_itim));
119 PROVIDE(__u54_3_itim_end = ORIGIN(u54_3_itim) + LENGTH(u54_3_itim));
121 PROVIDE(__u54_4_itim_end = ORIGIN(u54_4_itim) + LENGTH(u54_4_itim));