Lines Matching refs:LENGTH
51 envm (rx) : ORIGIN = 0x20220100, LENGTH = 128k - 0x100
52 dtim (rwx) : ORIGIN = 0x01000000, LENGTH = 7k
53 e51_itim (rwx) : ORIGIN = 0x01800000, LENGTH = 28k
54 u54_1_itim (rwx) : ORIGIN = 0x01808000, LENGTH = 28k
55 u54_2_itim (rwx) : ORIGIN = 0x01810000, LENGTH = 28k
56 u54_3_itim (rwx) : ORIGIN = 0x01818000, LENGTH = 28k
57 u54_4_itim (rwx) : ORIGIN = 0x01820000, LENGTH = 28k
58 l2lim (rwx) : ORIGIN = 0x08000000, LENGTH = 256k
59 scratchpad(rwx) : ORIGIN = 0x0A000000, LENGTH = 256k
61 switch_code_dtim (rx) : ORIGIN = 0x01001c00, LENGTH = 1k
63 ddr_cached_32bit (rwx) : ORIGIN = 0x80000000, LENGTH = 768M
64 ddr_non_cached_32bit (rwx) : ORIGIN = 0xC0000000, LENGTH = 256M
65 ddr_wcb_32bit (rwx) : ORIGIN = 0xD0000000, LENGTH = 256M
66 ddr_cached_38bit (rwx) : ORIGIN = 0x1000000000, LENGTH = 1024M
67 ddr_non_cached_38bit (rwx) : ORIGIN = 0x1400000000, LENGTH = 0k
68 ddr_wcb_38bit (rwx) : ORIGIN = 0x1800000000, LENGTH = 0k
106 PROVIDE(__envm_end = ORIGIN(envm) + LENGTH(envm));
108 PROVIDE(__l2lim_end = ORIGIN(l2lim) + LENGTH(l2lim));
110 PROVIDE(__ddr_cached_32bit_end = ORIGIN(ddr_cached_32bit) + LENGTH(ddr_cached_32bit));
112 … PROVIDE(__ddr_non_cached_32bit_end = ORIGIN(ddr_non_cached_32bit) + LENGTH(ddr_non_cached_32bit));
114 PROVIDE(__ddr_wcb_32bit_end = ORIGIN(ddr_wcb_32bit) + LENGTH(ddr_wcb_32bit));
116 PROVIDE(__ddr_cached_38bit_end = ORIGIN(ddr_cached_38bit) + LENGTH(ddr_cached_38bit));
118 … PROVIDE(__ddr_non_cached_38bit_end = ORIGIN(ddr_non_cached_38bit) + LENGTH(ddr_non_cached_38bit));
120 PROVIDE(__ddr_wcb_38bit_end = ORIGIN(ddr_wcb_38bit) + LENGTH(ddr_wcb_38bit));
122 PROVIDE(__dtim_end = ORIGIN(dtim) + LENGTH(dtim));
124 PROVIDE(__e51itim_end = ORIGIN(e51_itim) + LENGTH(e51_itim));
126 PROVIDE(__u54_1_itim_end = ORIGIN(u54_1_itim) + LENGTH(u54_1_itim));
128 PROVIDE(__u54_2_itim_end = ORIGIN(u54_2_itim) + LENGTH(u54_2_itim));
130 PROVIDE(__u54_3_itim_end = ORIGIN(u54_3_itim) + LENGTH(u54_3_itim));
132 PROVIDE(__u54_4_itim_end = ORIGIN(u54_4_itim) + LENGTH(u54_4_itim));