Lines Matching refs:uprint32
289 (void)uprint32(g_debug_uart, "\n\r Start training. TIP_CFG_PARAMS:"\ in ddr_setup()
308 (void)uprint32(g_debug_uart, "\n\r SM2_VERIFY: ",addr_cmd_value); in ddr_setup()
314 (void)uprint32(g_debug_uart, "\n\r SM_VERIFY: ",addr_cmd_value); in ddr_setup()
320 (void)uprint32(g_debug_uart, "\n\r SM_DQ_DQS: ",addr_cmd_value); in ddr_setup()
326 (void)uprint32(g_debug_uart, "\n\r SM_RDGATE: ",addr_cmd_value); in ddr_setup()
332 (void)uprint32(g_debug_uart, "\n\r SM_WRLVL: ",addr_cmd_value); in ddr_setup()
338 (void)uprint32(g_debug_uart, "\n\r SM_ADDCMD: ",addr_cmd_value); in ddr_setup()
344 (void)uprint32(g_debug_uart, "\n\r BCLKSCLK_SWY: ",addr_cmd_value); in ddr_setup()
350 (void)uprint32(g_debug_uart, "\n\r BCLKSCLK_SW: ",addr_cmd_value); in ddr_setup()
356 (void)uprint32(g_debug_uart, "\n\r 32BIT_NC_CHECK: ",addr_cmd_value); in ddr_setup()
362 (void)uprint32(g_debug_uart, "\n\r 32BIT_CACHE_CHECK: ",addr_cmd_value); in ddr_setup()
368 (void)uprint32(g_debug_uart, "\n\r MIN_LATENCY: ",addr_cmd_value); in ddr_setup()
374 (void)uprint32(g_debug_uart, "\n\r START_CHECK: ",addr_cmd_value); in ddr_setup()
380 (void)uprint32(g_debug_uart, "\n\r PLL LOCK FAIL: ",addr_cmd_value); in ddr_setup()
386 (void)uprint32(g_debug_uart, "\n\r DDR_SANITY_CHECKS FAIL: ",\ in ddr_setup()
395 (void)uprint32(g_debug_uart, "\n\r\n\r DDR_SWEEP_AGAIN: ",\ in ddr_setup()
404 … (void)uprint32(g_debug_uart, "\n\r ****************************************************", 0U); in ddr_setup()
414 (void)uprint32(g_debug_uart, "\n\r\n\r DDR_TRAINING_FAIL: ",\ in ddr_setup()
416 (void)uprint32(g_debug_uart, "\n\r Retry Count: ", retry_count); in ddr_setup()
444 (void)uprint32(g_debug_uart, "\n\r sweep success: ",\ in ddr_setup()
761 (void)uprint32(g_debug_uart, "\n\r dpc_bits: ",\ in ddr_setup()
810 (void)uprint32(g_debug_uart, "\n\r PCODE = ",\ in ddr_setup()
812 (void)uprint32(g_debug_uart, "\n\r NCODE = ", \ in ddr_setup()
814 (void)uprint32(g_debug_uart, "\n\r addr_cmd_value: ",\ in ddr_setup()
816 (void)uprint32(g_debug_uart, "\n\r bclk_sclk_offset_value: ",\ in ddr_setup()
818 (void)uprint32(g_debug_uart, "\n\r dpc_vrgen_v_value: ",\ in ddr_setup()
820 (void)uprint32(g_debug_uart, "\n\r dpc_vrgen_h_value: ",\ in ddr_setup()
822 (void)uprint32(g_debug_uart, "\n\r dpc_vrgen_vs_value: ",\ in ddr_setup()
1008 (void)uprint32(g_debug_uart, "\n\r tip_cfg_params: ",\ in ddr_setup()
1269 (void)uprint32(g_debug_uart, "\n\r ca_indly ", ca_indly); in ddr_setup()
1270 (void)uprint32(g_debug_uart, " vref ", vref); in ddr_setup()
1271 (void)uprint32(g_debug_uart, " a5_dly_max:", transition_a5_max); in ddr_setup()
1272 (void)uprint32(g_debug_uart, " a5_dly_min:", transition_a5_min); in ddr_setup()
1273 … (void)uprint32(g_debug_uart, " a5_dly_min_last:", transition_a5_min_last); in ddr_setup()
1274 (void)uprint32(g_debug_uart, " range_a5:", range_a5); in ddr_setup()
1275 (void)uprint32(g_debug_uart, " deltat:", deltat); in ddr_setup()
1276 (void)uprint32(g_debug_uart, " in_window:", in_window); in ddr_setup()
1277 (void)uprint32(g_debug_uart, " vref_answer:", vref_answer); in ddr_setup()
1299 (void)uprint32(g_debug_uart, "\n\r vref_answer found", vref_answer); in ddr_setup()
1303 … (void)uprint32(g_debug_uart, "\n\r CA_VREF training failed! ", vref_answer); in ddr_setup()
1455 (void)uprint32(g_debug_uart, \ in ddr_setup()
1458 (void)uprint32(g_debug_uart, \ in ddr_setup()
1461 (void)uprint32(g_debug_uart, \ in ddr_setup()
1464 (void)uprint32(g_debug_uart, \ in ddr_setup()
1467 (void)uprint32(g_debug_uart, \ in ddr_setup()
1470 (void)uprint32(g_debug_uart, \ in ddr_setup()
1473 (void)uprint32(g_debug_uart, \ in ddr_setup()
1513 … (void)uprint32(g_debug_uart, "\n\r difference ", difference[k]); in ddr_setup()
1514 (void)uprint32(g_debug_uart, " REFCLK_PHASE ", k); in ddr_setup()
1566 …(void)uprint32(g_debug_uart, "\n\r MANUAL ADDCMD TRAINING Results:\r\n PLL OFFSET: ",mi… in ddr_setup()
1567 … (void)uprint32(g_debug_uart, "\n\r transition_a5_max: ", transition_a5_max); in ddr_setup()
1568 … (void)uprint32(g_debug_uart, "\n\r CA Output Delay: ", min_diff); in ddr_setup()
1598 …(void)uprint32(g_debug_uart, "\n\r Returning FPGA CA VREF & CA drive to user setting.\n\r ", 0x0); in ddr_setup()
1661 (void)uprint32(g_debug_uart, "\n\r\n\r ADDCMD_OFFSET ", refclk_offset); in ddr_setup()
1677 (void)uprint32(g_debug_uart, \ in ddr_setup()
1680 (void)uprint32(g_debug_uart, \ in ddr_setup()
1953 (void)uprint32(g_debug_uart, "\n\r\n\r DDR FINAL_MODE: ",\ in ddr_setup()
1967 … (void)uprint32(g_debug_uart, "\n\r ****************************************************", 0U); in ddr_setup()
2012 (void)uprint32(g_debug_uart, "\n\r dq_dly ",\ in ddr_setup()
2014 (void)uprint32(g_debug_uart, " pass ",\ in ddr_setup()
2016 (void)uprint32(g_debug_uart, " wr calib result ",\ in ddr_setup()
2044 (void)uprint32(g_debug_uart, "\n\r dq_dly_answer ",\ in ddr_setup()
2047 (void)uprint32(g_debug_uart, " wr calib result ",\ in ddr_setup()
2094 (void)uprint32(g_debug_uart, "\n\r\n\r wr calib result ",\ in ddr_setup()
2130 (void)uprint32(g_debug_uart, "\n\r\n\r wr write latency ",\ in ddr_setup()
2155 (void)uprint32(g_debug_uart, "\n\r\n\r DDR SANITY_CHECKS: ",\ in ddr_setup()
2211 (void)uprint32(g_debug_uart, "\n\r\n\r Passed MTC full check ", error); in ddr_setup()
2218 (void)uprint32(g_debug_uart, "\n\r\n\r Failed MTC full check ", error); in ddr_setup()
2279 (void)uprint32(g_debug_uart, "\n\r\n\r wr write latency ",\ in ddr_setup()
2282 (void)uprint32(g_debug_uart, "\n\r rpc_166_fifo_offset: ",\ in ddr_setup()
2293 (void)uprint32(g_debug_uart, "\n\r rpc_166_fifo_offset: ",\ in ddr_setup()
2433 … (void)uprint32(g_debug_uart, "\n ****************************************************", 0); in ddr_setup()
2434 … (void)uprint32(g_debug_uart, "\n\r ****************************************************", 0U); in ddr_setup()
2435 …(void)uprint32(g_debug_uart, "\n\r ***************PHY PARAMETERS After training pass**************… in ddr_setup()
2439 …(void)uprint32(g_debug_uart, "\n\r ***************CTRLR PARAMETERS After training pass************… in ddr_setup()
3497 (void)uprint32(g_debug_uart, "\n\rCalibration offset used:",cal_data &0xFUL); in write_calibration_using_mtc()
3532 (void)uprint32(g_debug_uart, "\n\rLane passed:",laneToTest); in write_calibration_using_mtc()
3533 … (void)uprint32(g_debug_uart, " All lanes status:",calib_data.write_cal.status_lower); in write_calibration_using_mtc()
3556 (void)uprint32(g_debug_uart, "\n\rLane failed:",laneToTest); in write_calibration_using_mtc()
3557 … (void)uprint32(g_debug_uart, " All lanes status:",calib_data.write_cal.status_lower); in write_calibration_using_mtc()
4083 (void)uprint32(g_debug_uart, "\n\rmtc test error:",MTC_TIMEOUT_ERROR); in MTC_test()