3395         temp = calib_data.write_cal.lower[lane_to_set];  in set_write_calib()
3430             calib_data.dq_cal.lower[lane_to_set]  ) >> 1U) +\  in set_calc_dq_delay_offset()
3431             calib_data.dq_cal.lower[lane_to_set];  in set_calc_dq_delay_offset()
3525                     calib_data.write_cal.lower[laneToTest]  = (cal_data & 0xFU);  in write_calibration_using_mtc()
3570     SIM_FEEDBACK1(calib_data.write_cal.lower[0]);  in write_calibration_using_mtc()
3572     SIM_FEEDBACK1(calib_data.write_cal.lower[1]);  in write_calibration_using_mtc()
3574     SIM_FEEDBACK1(calib_data.write_cal.lower[2]);  in write_calibration_using_mtc()
3576     SIM_FEEDBACK1(calib_data.write_cal.lower[3]);  in write_calibration_using_mtc()
3578     SIM_FEEDBACK1(calib_data.write_cal.lower[4]);  in write_calibration_using_mtc()
3580     SIM_FEEDBACK1(calib_data.write_cal.lower[5]);  in write_calibration_using_mtc()
3683     calib_data.fpga_vref.lower = VREF_INVALID;  in FPGA_VREFDQ_calibration_using_mtc()
3712         if((result == 0U)&&(calib_data.fpga_vref.lower == VREF_INVALID))  in FPGA_VREFDQ_calibration_using_mtc()
3714             calib_data.fpga_vref.lower = vRef;  in FPGA_VREFDQ_calibration_using_mtc()
3718         else if((result == 0U)&&(calib_data.fpga_vref.lower != VREF_INVALID))  in FPGA_VREFDQ_calibration_using_mtc()
3740         vRef = ((calib_data.fpga_vref.lower + calib_data.fpga_vref.upper)>>1U);  in FPGA_VREFDQ_calibration_using_mtc()
3817     calib_data.mem_vref.lower = MEM_VREF_INVALID;  in VREFDQ_calibration_using_mtc()
3840         if((result == 0U)&&(calib_data.mem_vref.lower == MEM_VREF_INVALID))  in VREFDQ_calibration_using_mtc()
3842             calib_data.mem_vref.lower = vRef;  in VREFDQ_calibration_using_mtc()
3846         else if((result == 0U)&&(calib_data.mem_vref.lower != MEM_VREF_INVALID))  in VREFDQ_calibration_using_mtc()
3869         vRef = ((calib_data.mem_vref.lower + calib_data.mem_vref.lower)>1U);  in VREFDQ_calibration_using_mtc()