3473     uint8_t laneToTest;  in write_calibration_using_mtc()  local
3501         for (laneToTest = 0x00U; laneToTest<number_of_lanes_to_calibrate;\  in write_calibration_using_mtc()
3502                                                                 laneToTest++)  in write_calibration_using_mtc()
3508             uint8_t mask = (uint8_t)(1U<<laneToTest);  in write_calibration_using_mtc()
3522                 if((calib_data.write_cal.status_lower & (0x01U<<laneToTest)) \  in write_calibration_using_mtc()
3525                     calib_data.write_cal.lower[laneToTest]  = (cal_data & 0xFU);  in write_calibration_using_mtc()
3526                     calib_data.write_cal.status_lower |= (0x01U<<laneToTest);  in write_calibration_using_mtc()
3532                 (void)uprint32(g_debug_uart, "\n\rLane passed:",laneToTest);  in write_calibration_using_mtc()
3556                 (void)uprint32(g_debug_uart, "\n\rLane failed:",laneToTest);  in write_calibration_using_mtc()
3650     uint8_t laneToTest, result = 0U;  in FPGA_VREFDQ_calibration_using_mtc()  local
3708         result = MTC_test(1U<<laneToTest, start_address, size);  in FPGA_VREFDQ_calibration_using_mtc()
3710         result = MTC_test(1U<<laneToTest, start_address, size);  in FPGA_VREFDQ_calibration_using_mtc()
3711         result |= MTC_test(1U<<laneToTest, start_address, size);  in FPGA_VREFDQ_calibration_using_mtc()
3775     uint8_t laneToTest, result = 0U;  in VREFDQ_calibration_using_mtc()  local
3836         result = MTC_test(1U<<laneToTest, start_address, size);  in VREFDQ_calibration_using_mtc()
3838         result = MTC_test(1U<<laneToTest, start_address, size);  in VREFDQ_calibration_using_mtc()
3839         result |= MTC_test(1U<<laneToTest, start_address, size);  in VREFDQ_calibration_using_mtc()