Lines Matching refs:DDRCFG
494 DDRCFG->DFI.PHY_DFI_INIT_START.PHY_DFI_INIT_START = 0x0U; in ddr_setup()
496 DDRCFG->MC_BASE2.CTRLR_INIT.CTRLR_INIT = 0x0U; in ddr_setup()
503 DDRCFG->DFI.PHY_DFI_INIT_START.PHY_DFI_INIT_START = 0x0U; in ddr_setup()
505 DDRCFG->MC_BASE2.CTRLR_INIT.CTRLR_INIT = 0x0U; in ddr_setup()
578 DDRCFG->DFI.PHY_DFI_INIT_START.PHY_DFI_INIT_START = 0x00000000U; in ddr_setup()
580 DDRCFG->MC_BASE2.CTRLR_INIT.CTRLR_INIT = 0x00000000U; in ddr_setup()
883 DDRCFG->MC_BASE2.CTRLR_SOFT_RESET_N.CTRLR_SOFT_RESET_N =\ in ddr_setup()
885 DDRCFG->MC_BASE2.CTRLR_SOFT_RESET_N.CTRLR_SOFT_RESET_N =\ in ddr_setup()
890 DDRCFG->MC_BASE2.INIT_DISABLE_CKE.INIT_DISABLE_CKE = 0x1; in ddr_setup()
893 DDRCFG->MC_BASE2.INIT_FORCE_RESET.INIT_FORCE_RESET = 0x1; in ddr_setup()
896 DDRCFG->MC_BASE2.INIT_FORCE_RESET.INIT_FORCE_RESET = 0x0; in ddr_setup()
900 DDRCFG->MC_BASE2.INIT_DISABLE_CKE.INIT_DISABLE_CKE = 0x0; in ddr_setup()
1022 DDRCFG->MC_BASE2.CTRLR_SOFT_RESET_N.CTRLR_SOFT_RESET_N =\ in ddr_setup()
1040 DDRCFG->MC_BASE2.CTRLR_SOFT_RESET_N.CTRLR_SOFT_RESET_N =\ in ddr_setup()
1648 DDRCFG->DFI.PHY_DFI_INIT_START.PHY_DFI_INIT_START =\ in ddr_setup()
1651 DDRCFG->DFI.PHY_DFI_INIT_START.PHY_DFI_INIT_START =\ in ddr_setup()
1653 DDRCFG->MC_BASE2.CTRLR_INIT.CTRLR_INIT = 0x00000000U; in ddr_setup()
1654 DDRCFG->MC_BASE2.CTRLR_INIT.CTRLR_INIT = 0x00000001U; in ddr_setup()
1667 if((DDRCFG->DFI.STAT_DFI_INIT_COMPLETE.STAT_DFI_INIT_COMPLETE\ in ddr_setup()
1791 … if ((DDRCFG->DFI.STAT_DFI_TRAINING_COMPLETE.STAT_DFI_TRAINING_COMPLETE & 0x01U) == 0x01U) in ddr_setup()
2127 DDRCFG->DFI.CFG_DFI_T_PHY_WRLAT.CFG_DFI_T_PHY_WRLAT =\ in ddr_setup()
3612 DDRCFG->MC_BASE2.INIT_MR_ADDR.INIT_MR_ADDR = MR_ADDR ; in mode_register_write()
3619 DDRCFG->MC_BASE2.INIT_MR_WR_DATA.INIT_MR_WR_DATA = MR_DATA; in mode_register_write()
3620 DDRCFG->MC_BASE2.INIT_MR_WR_MASK.INIT_MR_WR_MASK = 0U; in mode_register_write()
3622 DDRCFG->MC_BASE2.INIT_MR_W_REQ.INIT_MR_W_REQ = 0x01U; in mode_register_write()
3623 while((DDRCFG->MC_BASE2.INIT_ACK.INIT_ACK & 0x01U) == 0U) /* wait for ack- in mode_register_write()
3789 DDRCFG->MC_BASE2.INIT_MRR_MODE.INIT_MRR_MODE = 0x01U; in VREFDQ_calibration_using_mtc()
3790 DDRCFG->MC_BASE2.INIT_MR_ADDR.INIT_MR_ADDR = 6U ; in VREFDQ_calibration_using_mtc()
3797 DDRCFG->MC_BASE2.INIT_MR_WR_DATA.INIT_MR_WR_DATA = 0U; in VREFDQ_calibration_using_mtc()
3798 DDRCFG->MC_BASE2.INIT_MR_WR_MASK.INIT_MR_WR_MASK = (0x01U <<6U) |\ in VREFDQ_calibration_using_mtc()
3801 DDRCFG->MC_BASE2.INIT_MR_W_REQ.INIT_MR_W_REQ = 0x01U; in VREFDQ_calibration_using_mtc()
3802 if((DDRCFG->MC_BASE2.INIT_ACK.INIT_ACK & 0x01U) == 0U) /* wait for ack- in VREFDQ_calibration_using_mtc()
3910 DDRCFG->MEM_TEST.MT_STOP_ON_ERROR.MT_STOP_ON_ERROR = 0U; in MTC_test()
3912 DDRCFG->MEM_TEST.MT_EN_SINGLE.MT_EN_SINGLE = 0x00U; in MTC_test()
3933 DDRCFG->MEM_TEST.MT_DATA_PATTERN.MT_DATA_PATTERN = data_pattern; in MTC_test()
3943 DDRCFG->MEM_TEST.MT_ADDR_PATTERN.MT_ADDR_PATTERN = 1U; in MTC_test()
3947 DDRCFG->MEM_TEST.MT_ADDR_PATTERN.MT_ADDR_PATTERN = 0U; in MTC_test()
3961 DDRCFG->MEM_TEST.MT_START_ADDR_0.MT_START_ADDR_0 =\ in MTC_test()
3964 DDRCFG->MEM_TEST.MT_START_ADDR_1.MT_START_ADDR_1 =\ in MTC_test()
3969 DDRCFG->MEM_TEST.MT_START_ADDR_0.MT_START_ADDR_0 = 0U; in MTC_test()
3970 DDRCFG->MEM_TEST.MT_START_ADDR_1.MT_START_ADDR_1 = 0U; in MTC_test()
3972 DDRCFG->MEM_TEST.MT_ADDR_BITS.MT_ADDR_BITS =\ in MTC_test()
4012 DDRCFG->MEM_TEST.MT_ERROR_MASK_0.MT_ERROR_MASK_0 = 0xFFFFFFFFU; in MTC_test()
4013 DDRCFG->MEM_TEST.MT_ERROR_MASK_1.MT_ERROR_MASK_1 = 0xFFFFFFFFU; in MTC_test()
4014 DDRCFG->MEM_TEST.MT_ERROR_MASK_2.MT_ERROR_MASK_2 = 0xFFFFFFFFU; in MTC_test()
4015 DDRCFG->MEM_TEST.MT_ERROR_MASK_3.MT_ERROR_MASK_3 = 0xFFFFFFFFU; in MTC_test()
4016 DDRCFG->MEM_TEST.MT_ERROR_MASK_4.MT_ERROR_MASK_4 = 0xFFFFFFFFU; in MTC_test()
4020 DDRCFG->MEM_TEST.MT_ERROR_MASK_0.MT_ERROR_MASK_0 &= 0xFFFFFF00U; in MTC_test()
4021 DDRCFG->MEM_TEST.MT_ERROR_MASK_1.MT_ERROR_MASK_1 &= 0xFFFFF00FU; in MTC_test()
4022 DDRCFG->MEM_TEST.MT_ERROR_MASK_2.MT_ERROR_MASK_2 &= 0xFFFF00FFU; in MTC_test()
4023 DDRCFG->MEM_TEST.MT_ERROR_MASK_3.MT_ERROR_MASK_3 &= 0xFFF00FFFU; in MTC_test()
4024 DDRCFG->MEM_TEST.MT_ERROR_MASK_4.MT_ERROR_MASK_4 &= 0xFFFFFFFFU; in MTC_test()
4028 DDRCFG->MEM_TEST.MT_ERROR_MASK_0.MT_ERROR_MASK_0 &= 0xFFFF00FFU; in MTC_test()
4029 DDRCFG->MEM_TEST.MT_ERROR_MASK_1.MT_ERROR_MASK_1 &= 0xFFF00FFFU; in MTC_test()
4030 DDRCFG->MEM_TEST.MT_ERROR_MASK_2.MT_ERROR_MASK_2 &= 0xFF00FFFFU; in MTC_test()
4031 DDRCFG->MEM_TEST.MT_ERROR_MASK_3.MT_ERROR_MASK_3 &= 0xF00FFFFFU; in MTC_test()
4032 DDRCFG->MEM_TEST.MT_ERROR_MASK_4.MT_ERROR_MASK_4 &= 0xFFFFFFFFU; in MTC_test()
4036 DDRCFG->MEM_TEST.MT_ERROR_MASK_0.MT_ERROR_MASK_0 &= 0xFF00FFFFU; in MTC_test()
4037 DDRCFG->MEM_TEST.MT_ERROR_MASK_1.MT_ERROR_MASK_1 &= 0xF00FFFFFU; in MTC_test()
4038 DDRCFG->MEM_TEST.MT_ERROR_MASK_2.MT_ERROR_MASK_2 &= 0x00FFFFFFU; in MTC_test()
4039 DDRCFG->MEM_TEST.MT_ERROR_MASK_3.MT_ERROR_MASK_3 &= 0x0FFFFFFFU; in MTC_test()
4040 DDRCFG->MEM_TEST.MT_ERROR_MASK_4.MT_ERROR_MASK_4 &= 0xFFFFFFF0U; in MTC_test()
4044 DDRCFG->MEM_TEST.MT_ERROR_MASK_0.MT_ERROR_MASK_0 &= 0x00FFFFFFU; in MTC_test()
4045 DDRCFG->MEM_TEST.MT_ERROR_MASK_1.MT_ERROR_MASK_1 &= 0x0FFFFFFFU; in MTC_test()
4046 DDRCFG->MEM_TEST.MT_ERROR_MASK_2.MT_ERROR_MASK_2 &= 0xFFFFFFF0U; in MTC_test()
4047 DDRCFG->MEM_TEST.MT_ERROR_MASK_3.MT_ERROR_MASK_3 &= 0xFFFFFF00U; in MTC_test()
4048 DDRCFG->MEM_TEST.MT_ERROR_MASK_4.MT_ERROR_MASK_4 &= 0xFFFFF00FU; in MTC_test()
4052 DDRCFG->MEM_TEST.MT_ERROR_MASK_0.MT_ERROR_MASK_0 &= 0xFFFFFFFFU; in MTC_test()
4053 DDRCFG->MEM_TEST.MT_ERROR_MASK_1.MT_ERROR_MASK_1 &= 0xFFFFFFF0U; in MTC_test()
4054 DDRCFG->MEM_TEST.MT_ERROR_MASK_2.MT_ERROR_MASK_2 &= 0xFFFFFF0FU; in MTC_test()
4055 DDRCFG->MEM_TEST.MT_ERROR_MASK_3.MT_ERROR_MASK_3 &= 0xFFFFF0FFU; in MTC_test()
4056 DDRCFG->MEM_TEST.MT_ERROR_MASK_4.MT_ERROR_MASK_4 &= 0xFFFF0FFFU; in MTC_test()
4064 DDRCFG->MEM_TEST.MT_EN.MT_EN = 0U; in MTC_test()
4069 DDRCFG->MEM_TEST.MT_EN_SINGLE.MT_EN_SINGLE = 0x00U; in MTC_test()
4070 DDRCFG->MEM_TEST.MT_EN_SINGLE.MT_EN_SINGLE = 0x01U; in MTC_test()
4077 while (( DDRCFG->MEM_TEST.MT_DONE_ACK.MT_DONE_ACK & 0x01U) == 0U) in MTC_test()
4100 return (DDRCFG->MEM_TEST.MT_ERROR_STS.MT_ERROR_STS & 0x01U); in MTC_test()
4114 DDRCFG->ADDR_MAP.CFG_MANUAL_ADDRESS_MAP.CFG_MANUAL_ADDRESS_MAP =\ in init_ddrc()
4116 DDRCFG->ADDR_MAP.CFG_CHIPADDR_MAP.CFG_CHIPADDR_MAP =\ in init_ddrc()
4118 DDRCFG->ADDR_MAP.CFG_CIDADDR_MAP.CFG_CIDADDR_MAP =\ in init_ddrc()
4120 DDRCFG->ADDR_MAP.CFG_MB_AUTOPCH_COL_BIT_POS_LOW.CFG_MB_AUTOPCH_COL_BIT_POS_LOW =\ in init_ddrc()
4122 DDRCFG->ADDR_MAP.CFG_MB_AUTOPCH_COL_BIT_POS_HIGH.CFG_MB_AUTOPCH_COL_BIT_POS_HIGH =\ in init_ddrc()
4124 DDRCFG->ADDR_MAP.CFG_BANKADDR_MAP_0.CFG_BANKADDR_MAP_0 =\ in init_ddrc()
4126 DDRCFG->ADDR_MAP.CFG_BANKADDR_MAP_1.CFG_BANKADDR_MAP_1 =\ in init_ddrc()
4128 DDRCFG->ADDR_MAP.CFG_ROWADDR_MAP_0.CFG_ROWADDR_MAP_0 =\ in init_ddrc()
4130 DDRCFG->ADDR_MAP.CFG_ROWADDR_MAP_1.CFG_ROWADDR_MAP_1 =\ in init_ddrc()
4132 DDRCFG->ADDR_MAP.CFG_ROWADDR_MAP_2.CFG_ROWADDR_MAP_2 =\ in init_ddrc()
4134 DDRCFG->ADDR_MAP.CFG_ROWADDR_MAP_3.CFG_ROWADDR_MAP_3 =\ in init_ddrc()
4136 DDRCFG->ADDR_MAP.CFG_COLADDR_MAP_0.CFG_COLADDR_MAP_0 =\ in init_ddrc()
4138 DDRCFG->ADDR_MAP.CFG_COLADDR_MAP_1.CFG_COLADDR_MAP_1 =\ in init_ddrc()
4140 DDRCFG->ADDR_MAP.CFG_COLADDR_MAP_2.CFG_COLADDR_MAP_2 =\ in init_ddrc()
4142 DDRCFG->MC_BASE3.CFG_VRCG_ENABLE.CFG_VRCG_ENABLE =\ in init_ddrc()
4144 DDRCFG->MC_BASE3.CFG_VRCG_DISABLE.CFG_VRCG_DISABLE =\ in init_ddrc()
4146 DDRCFG->MC_BASE3.CFG_WRITE_LATENCY_SET.CFG_WRITE_LATENCY_SET =\ in init_ddrc()
4148 DDRCFG->MC_BASE3.CFG_THERMAL_OFFSET.CFG_THERMAL_OFFSET =\ in init_ddrc()
4150 DDRCFG->MC_BASE3.CFG_SOC_ODT.CFG_SOC_ODT = LIBERO_SETTING_CFG_SOC_ODT; in init_ddrc()
4151 DDRCFG->MC_BASE3.CFG_ODTE_CK.CFG_ODTE_CK = LIBERO_SETTING_CFG_ODTE_CK; in init_ddrc()
4152 DDRCFG->MC_BASE3.CFG_ODTE_CS.CFG_ODTE_CS = LIBERO_SETTING_CFG_ODTE_CS; in init_ddrc()
4153 DDRCFG->MC_BASE3.CFG_ODTD_CA.CFG_ODTD_CA = LIBERO_SETTING_CFG_ODTD_CA; in init_ddrc()
4154 DDRCFG->MC_BASE3.CFG_LPDDR4_FSP_OP.CFG_LPDDR4_FSP_OP =\ in init_ddrc()
4156 DDRCFG->MC_BASE3.CFG_GENERATE_REFRESH_ON_SRX.CFG_GENERATE_REFRESH_ON_SRX =\ in init_ddrc()
4158 DDRCFG->MC_BASE3.CFG_DBI_CL.CFG_DBI_CL = LIBERO_SETTING_CFG_DBI_CL; in init_ddrc()
4159 DDRCFG->MC_BASE3.CFG_NON_DBI_CL.CFG_NON_DBI_CL =\ in init_ddrc()
4161 DDRCFG->MC_BASE3.INIT_FORCE_WRITE_DATA_0.INIT_FORCE_WRITE_DATA_0 =\ in init_ddrc()
4163 DDRCFG->MC_BASE1.CFG_WRITE_CRC.CFG_WRITE_CRC =\ in init_ddrc()
4165 DDRCFG->MC_BASE1.CFG_MPR_READ_FORMAT.CFG_MPR_READ_FORMAT =\ in init_ddrc()
4167 DDRCFG->MC_BASE1.CFG_WR_CMD_LAT_CRC_DM.CFG_WR_CMD_LAT_CRC_DM =\ in init_ddrc()
4169 DDRCFG->MC_BASE1.CFG_FINE_GRAN_REF_MODE.CFG_FINE_GRAN_REF_MODE =\ in init_ddrc()
4171 DDRCFG->MC_BASE1.CFG_TEMP_SENSOR_READOUT.CFG_TEMP_SENSOR_READOUT =\ in init_ddrc()
4173 DDRCFG->MC_BASE1.CFG_PER_DRAM_ADDR_EN.CFG_PER_DRAM_ADDR_EN =\ in init_ddrc()
4175 DDRCFG->MC_BASE1.CFG_GEARDOWN_MODE.CFG_GEARDOWN_MODE =\ in init_ddrc()
4177 DDRCFG->MC_BASE1.CFG_WR_PREAMBLE.CFG_WR_PREAMBLE =\ in init_ddrc()
4179 DDRCFG->MC_BASE1.CFG_RD_PREAMBLE.CFG_RD_PREAMBLE =\ in init_ddrc()
4181 DDRCFG->MC_BASE1.CFG_RD_PREAMB_TRN_MODE.CFG_RD_PREAMB_TRN_MODE =\ in init_ddrc()
4183 DDRCFG->MC_BASE1.CFG_SR_ABORT.CFG_SR_ABORT = LIBERO_SETTING_CFG_SR_ABORT; in init_ddrc()
4184 DDRCFG->MC_BASE1.CFG_CS_TO_CMDADDR_LATENCY.CFG_CS_TO_CMDADDR_LATENCY =\ in init_ddrc()
4186 DDRCFG->MC_BASE1.CFG_INT_VREF_MON.CFG_INT_VREF_MON =\ in init_ddrc()
4188 DDRCFG->MC_BASE1.CFG_TEMP_CTRL_REF_MODE.CFG_TEMP_CTRL_REF_MODE =\ in init_ddrc()
4190 DDRCFG->MC_BASE1.CFG_TEMP_CTRL_REF_RANGE.CFG_TEMP_CTRL_REF_RANGE =\ in init_ddrc()
4192 DDRCFG->MC_BASE1.CFG_MAX_PWR_DOWN_MODE.CFG_MAX_PWR_DOWN_MODE =\ in init_ddrc()
4194 DDRCFG->MC_BASE1.CFG_READ_DBI.CFG_READ_DBI = LIBERO_SETTING_CFG_READ_DBI; in init_ddrc()
4195 DDRCFG->MC_BASE1.CFG_WRITE_DBI.CFG_WRITE_DBI =\ in init_ddrc()
4197 DDRCFG->MC_BASE1.CFG_DATA_MASK.CFG_DATA_MASK =\ in init_ddrc()
4199 DDRCFG->MC_BASE1.CFG_CA_PARITY_PERSIST_ERR.CFG_CA_PARITY_PERSIST_ERR =\ in init_ddrc()
4201 DDRCFG->MC_BASE1.CFG_RTT_PARK.CFG_RTT_PARK = LIBERO_SETTING_CFG_RTT_PARK; in init_ddrc()
4202 DDRCFG->MC_BASE1.CFG_ODT_INBUF_4_PD.CFG_ODT_INBUF_4_PD =\ in init_ddrc()
4204 DDRCFG->MC_BASE1.CFG_CA_PARITY_ERR_STATUS.CFG_CA_PARITY_ERR_STATUS =\ in init_ddrc()
4206 DDRCFG->MC_BASE1.CFG_CRC_ERROR_CLEAR.CFG_CRC_ERROR_CLEAR =\ in init_ddrc()
4208 DDRCFG->MC_BASE1.CFG_CA_PARITY_LATENCY.CFG_CA_PARITY_LATENCY =\ in init_ddrc()
4210 DDRCFG->MC_BASE1.CFG_CCD_S.CFG_CCD_S = LIBERO_SETTING_CFG_CCD_S; in init_ddrc()
4211 DDRCFG->MC_BASE1.CFG_CCD_L.CFG_CCD_L = LIBERO_SETTING_CFG_CCD_L; in init_ddrc()
4212 DDRCFG->MC_BASE1.CFG_VREFDQ_TRN_ENABLE.CFG_VREFDQ_TRN_ENABLE =\ in init_ddrc()
4214 DDRCFG->MC_BASE1.CFG_VREFDQ_TRN_RANGE.CFG_VREFDQ_TRN_RANGE =\ in init_ddrc()
4216 DDRCFG->MC_BASE1.CFG_VREFDQ_TRN_VALUE.CFG_VREFDQ_TRN_VALUE =\ in init_ddrc()
4218 DDRCFG->MC_BASE1.CFG_RRD_S.CFG_RRD_S = LIBERO_SETTING_CFG_RRD_S; in init_ddrc()
4219 DDRCFG->MC_BASE1.CFG_RRD_L.CFG_RRD_L = LIBERO_SETTING_CFG_RRD_L; in init_ddrc()
4220 DDRCFG->MC_BASE1.CFG_WTR_S.CFG_WTR_S = LIBERO_SETTING_CFG_WTR_S; in init_ddrc()
4221 DDRCFG->MC_BASE1.CFG_WTR_L.CFG_WTR_L = LIBERO_SETTING_CFG_WTR_L; in init_ddrc()
4222 DDRCFG->MC_BASE1.CFG_WTR_S_CRC_DM.CFG_WTR_S_CRC_DM =\ in init_ddrc()
4224 DDRCFG->MC_BASE1.CFG_WTR_L_CRC_DM.CFG_WTR_L_CRC_DM =\ in init_ddrc()
4226 DDRCFG->MC_BASE1.CFG_WR_CRC_DM.CFG_WR_CRC_DM =\ in init_ddrc()
4228 DDRCFG->MC_BASE1.CFG_RFC1.CFG_RFC1 = LIBERO_SETTING_CFG_RFC1; in init_ddrc()
4229 DDRCFG->MC_BASE1.CFG_RFC2.CFG_RFC2 = LIBERO_SETTING_CFG_RFC2; in init_ddrc()
4230 DDRCFG->MC_BASE1.CFG_RFC4.CFG_RFC4 = LIBERO_SETTING_CFG_RFC4; in init_ddrc()
4231 DDRCFG->MC_BASE1.CFG_NIBBLE_DEVICES.CFG_NIBBLE_DEVICES =\ in init_ddrc()
4233 DDRCFG->MC_BASE1.CFG_BIT_MAP_INDEX_CS0_0.CFG_BIT_MAP_INDEX_CS0_0 =\ in init_ddrc()
4235 DDRCFG->MC_BASE1.CFG_BIT_MAP_INDEX_CS0_1.CFG_BIT_MAP_INDEX_CS0_1 =\ in init_ddrc()
4237 DDRCFG->MC_BASE1.CFG_BIT_MAP_INDEX_CS1_0.CFG_BIT_MAP_INDEX_CS1_0 =\ in init_ddrc()
4239 DDRCFG->MC_BASE1.CFG_BIT_MAP_INDEX_CS1_1.CFG_BIT_MAP_INDEX_CS1_1 =\ in init_ddrc()
4241 DDRCFG->MC_BASE1.CFG_BIT_MAP_INDEX_CS2_0.CFG_BIT_MAP_INDEX_CS2_0 =\ in init_ddrc()
4243 DDRCFG->MC_BASE1.CFG_BIT_MAP_INDEX_CS2_1.CFG_BIT_MAP_INDEX_CS2_1 =\ in init_ddrc()
4245 DDRCFG->MC_BASE1.CFG_BIT_MAP_INDEX_CS3_0.CFG_BIT_MAP_INDEX_CS3_0 =\ in init_ddrc()
4247 DDRCFG->MC_BASE1.CFG_BIT_MAP_INDEX_CS3_1.CFG_BIT_MAP_INDEX_CS3_1 =\ in init_ddrc()
4249 DDRCFG->MC_BASE1.CFG_BIT_MAP_INDEX_CS4_0.CFG_BIT_MAP_INDEX_CS4_0 =\ in init_ddrc()
4251 DDRCFG->MC_BASE1.CFG_BIT_MAP_INDEX_CS4_1.CFG_BIT_MAP_INDEX_CS4_1 =\ in init_ddrc()
4253 DDRCFG->MC_BASE1.CFG_BIT_MAP_INDEX_CS5_0.CFG_BIT_MAP_INDEX_CS5_0 =\ in init_ddrc()
4255 DDRCFG->MC_BASE1.CFG_BIT_MAP_INDEX_CS5_1.CFG_BIT_MAP_INDEX_CS5_1 =\ in init_ddrc()
4257 DDRCFG->MC_BASE1.CFG_BIT_MAP_INDEX_CS6_0.CFG_BIT_MAP_INDEX_CS6_0 =\ in init_ddrc()
4259 DDRCFG->MC_BASE1.CFG_BIT_MAP_INDEX_CS6_1.CFG_BIT_MAP_INDEX_CS6_1 =\ in init_ddrc()
4261 DDRCFG->MC_BASE1.CFG_BIT_MAP_INDEX_CS7_0.CFG_BIT_MAP_INDEX_CS7_0 =\ in init_ddrc()
4263 DDRCFG->MC_BASE1.CFG_BIT_MAP_INDEX_CS7_1.CFG_BIT_MAP_INDEX_CS7_1 =\ in init_ddrc()
4265 DDRCFG->MC_BASE1.CFG_BIT_MAP_INDEX_CS8_0.CFG_BIT_MAP_INDEX_CS8_0 =\ in init_ddrc()
4267 DDRCFG->MC_BASE1.CFG_BIT_MAP_INDEX_CS8_1.CFG_BIT_MAP_INDEX_CS8_1 =\ in init_ddrc()
4269 DDRCFG->MC_BASE1.CFG_BIT_MAP_INDEX_CS9_0.CFG_BIT_MAP_INDEX_CS9_0 =\ in init_ddrc()
4271 DDRCFG->MC_BASE1.CFG_BIT_MAP_INDEX_CS9_1.CFG_BIT_MAP_INDEX_CS9_1 =\ in init_ddrc()
4273 DDRCFG->MC_BASE1.CFG_BIT_MAP_INDEX_CS10_0.CFG_BIT_MAP_INDEX_CS10_0 =\ in init_ddrc()
4275 DDRCFG->MC_BASE1.CFG_BIT_MAP_INDEX_CS10_1.CFG_BIT_MAP_INDEX_CS10_1 =\ in init_ddrc()
4277 DDRCFG->MC_BASE1.CFG_BIT_MAP_INDEX_CS11_0.CFG_BIT_MAP_INDEX_CS11_0 =\ in init_ddrc()
4279 DDRCFG->MC_BASE1.CFG_BIT_MAP_INDEX_CS11_1.CFG_BIT_MAP_INDEX_CS11_1 =\ in init_ddrc()
4281 DDRCFG->MC_BASE1.CFG_BIT_MAP_INDEX_CS12_0.CFG_BIT_MAP_INDEX_CS12_0 =\ in init_ddrc()
4283 DDRCFG->MC_BASE1.CFG_BIT_MAP_INDEX_CS12_1.CFG_BIT_MAP_INDEX_CS12_1 =\ in init_ddrc()
4285 DDRCFG->MC_BASE1.CFG_BIT_MAP_INDEX_CS13_0.CFG_BIT_MAP_INDEX_CS13_0 =\ in init_ddrc()
4287 DDRCFG->MC_BASE1.CFG_BIT_MAP_INDEX_CS13_1.CFG_BIT_MAP_INDEX_CS13_1 =\ in init_ddrc()
4289 DDRCFG->MC_BASE1.CFG_BIT_MAP_INDEX_CS14_0.CFG_BIT_MAP_INDEX_CS14_0 =\ in init_ddrc()
4291 DDRCFG->MC_BASE1.CFG_BIT_MAP_INDEX_CS14_1.CFG_BIT_MAP_INDEX_CS14_1 =\ in init_ddrc()
4293 DDRCFG->MC_BASE1.CFG_BIT_MAP_INDEX_CS15_0.CFG_BIT_MAP_INDEX_CS15_0 =\ in init_ddrc()
4295 DDRCFG->MC_BASE1.CFG_BIT_MAP_INDEX_CS15_1.CFG_BIT_MAP_INDEX_CS15_1 =\ in init_ddrc()
4297 DDRCFG->MC_BASE1.CFG_NUM_LOGICAL_RANKS_PER_3DS.CFG_NUM_LOGICAL_RANKS_PER_3DS =\ in init_ddrc()
4299 DDRCFG->MC_BASE1.CFG_RFC_DLR1.CFG_RFC_DLR1 = LIBERO_SETTING_CFG_RFC_DLR1; in init_ddrc()
4300 DDRCFG->MC_BASE1.CFG_RFC_DLR2.CFG_RFC_DLR2 = LIBERO_SETTING_CFG_RFC_DLR2; in init_ddrc()
4301 DDRCFG->MC_BASE1.CFG_RFC_DLR4.CFG_RFC_DLR4 = LIBERO_SETTING_CFG_RFC_DLR4; in init_ddrc()
4302 DDRCFG->MC_BASE1.CFG_RRD_DLR.CFG_RRD_DLR = LIBERO_SETTING_CFG_RRD_DLR; in init_ddrc()
4303 DDRCFG->MC_BASE1.CFG_FAW_DLR.CFG_FAW_DLR = LIBERO_SETTING_CFG_FAW_DLR; in init_ddrc()
4304 DDRCFG->MC_BASE1.CFG_ADVANCE_ACTIVATE_READY.CFG_ADVANCE_ACTIVATE_READY =\ in init_ddrc()
4306 DDRCFG->MC_BASE2.CTRLR_SOFT_RESET_N.CTRLR_SOFT_RESET_N =\ in init_ddrc()
4308 DDRCFG->MC_BASE2.CFG_LOOKAHEAD_PCH.CFG_LOOKAHEAD_PCH =\ in init_ddrc()
4310 DDRCFG->MC_BASE2.CFG_LOOKAHEAD_ACT.CFG_LOOKAHEAD_ACT =\ in init_ddrc()
4312 DDRCFG->MC_BASE2.INIT_AUTOINIT_DISABLE.INIT_AUTOINIT_DISABLE =\ in init_ddrc()
4314 DDRCFG->MC_BASE2.INIT_FORCE_RESET.INIT_FORCE_RESET =\ in init_ddrc()
4316 DDRCFG->MC_BASE2.INIT_GEARDOWN_EN.INIT_GEARDOWN_EN =\ in init_ddrc()
4318 DDRCFG->MC_BASE2.INIT_DISABLE_CKE.INIT_DISABLE_CKE =\ in init_ddrc()
4320 DDRCFG->MC_BASE2.INIT_CS.INIT_CS = LIBERO_SETTING_INIT_CS; in init_ddrc()
4321 DDRCFG->MC_BASE2.INIT_PRECHARGE_ALL.INIT_PRECHARGE_ALL =\ in init_ddrc()
4323 DDRCFG->MC_BASE2.INIT_REFRESH.INIT_REFRESH = LIBERO_SETTING_INIT_REFRESH; in init_ddrc()
4324 DDRCFG->MC_BASE2.INIT_ZQ_CAL_REQ.INIT_ZQ_CAL_REQ =\ in init_ddrc()
4326 DDRCFG->MC_BASE2.CFG_BL.CFG_BL = LIBERO_SETTING_CFG_BL; in init_ddrc()
4327 DDRCFG->MC_BASE2.CTRLR_INIT.CTRLR_INIT = LIBERO_SETTING_CTRLR_INIT; in init_ddrc()
4328 DDRCFG->MC_BASE2.CFG_AUTO_REF_EN.CFG_AUTO_REF_EN =\ in init_ddrc()
4330 DDRCFG->MC_BASE2.CFG_RAS.CFG_RAS = LIBERO_SETTING_CFG_RAS; in init_ddrc()
4331 DDRCFG->MC_BASE2.CFG_RCD.CFG_RCD = LIBERO_SETTING_CFG_RCD; in init_ddrc()
4332 DDRCFG->MC_BASE2.CFG_RRD.CFG_RRD = LIBERO_SETTING_CFG_RRD; in init_ddrc()
4333 DDRCFG->MC_BASE2.CFG_RP.CFG_RP = LIBERO_SETTING_CFG_RP; in init_ddrc()
4334 DDRCFG->MC_BASE2.CFG_RC.CFG_RC = LIBERO_SETTING_CFG_RC; in init_ddrc()
4335 DDRCFG->MC_BASE2.CFG_FAW.CFG_FAW = LIBERO_SETTING_CFG_FAW; in init_ddrc()
4336 DDRCFG->MC_BASE2.CFG_RFC.CFG_RFC = LIBERO_SETTING_CFG_RFC; in init_ddrc()
4337 DDRCFG->MC_BASE2.CFG_RTP.CFG_RTP = LIBERO_SETTING_CFG_RTP; in init_ddrc()
4338 DDRCFG->MC_BASE2.CFG_WR.CFG_WR = LIBERO_SETTING_CFG_WR; in init_ddrc()
4339 DDRCFG->MC_BASE2.CFG_WTR.CFG_WTR = LIBERO_SETTING_CFG_WTR; in init_ddrc()
4340 DDRCFG->MC_BASE2.CFG_PASR.CFG_PASR = LIBERO_SETTING_CFG_PASR; in init_ddrc()
4341 DDRCFG->MC_BASE2.CFG_XP.CFG_XP = LIBERO_SETTING_CFG_XP; in init_ddrc()
4342 DDRCFG->MC_BASE2.CFG_XSR.CFG_XSR = LIBERO_SETTING_CFG_XSR; in init_ddrc()
4343 DDRCFG->MC_BASE2.CFG_CL.CFG_CL = LIBERO_SETTING_CFG_CL; in init_ddrc()
4344 DDRCFG->MC_BASE2.CFG_READ_TO_WRITE.CFG_READ_TO_WRITE =\ in init_ddrc()
4346 DDRCFG->MC_BASE2.CFG_WRITE_TO_WRITE.CFG_WRITE_TO_WRITE =\ in init_ddrc()
4348 DDRCFG->MC_BASE2.CFG_READ_TO_READ.CFG_READ_TO_READ =\ in init_ddrc()
4350 DDRCFG->MC_BASE2.CFG_WRITE_TO_READ.CFG_WRITE_TO_READ =\ in init_ddrc()
4352 DDRCFG->MC_BASE2.CFG_READ_TO_WRITE_ODT.CFG_READ_TO_WRITE_ODT =\ in init_ddrc()
4354 DDRCFG->MC_BASE2.CFG_WRITE_TO_WRITE_ODT.CFG_WRITE_TO_WRITE_ODT =\ in init_ddrc()
4356 DDRCFG->MC_BASE2.CFG_READ_TO_READ_ODT.CFG_READ_TO_READ_ODT =\ in init_ddrc()
4358 DDRCFG->MC_BASE2.CFG_WRITE_TO_READ_ODT.CFG_WRITE_TO_READ_ODT =\ in init_ddrc()
4360 DDRCFG->MC_BASE2.CFG_MIN_READ_IDLE.CFG_MIN_READ_IDLE =\ in init_ddrc()
4362 DDRCFG->MC_BASE2.CFG_MRD.CFG_MRD = LIBERO_SETTING_CFG_MRD; in init_ddrc()
4363 DDRCFG->MC_BASE2.CFG_BT.CFG_BT = LIBERO_SETTING_CFG_BT; in init_ddrc()
4364 DDRCFG->MC_BASE2.CFG_DS.CFG_DS = LIBERO_SETTING_CFG_DS; in init_ddrc()
4365 DDRCFG->MC_BASE2.CFG_QOFF.CFG_QOFF = LIBERO_SETTING_CFG_QOFF; in init_ddrc()
4366 DDRCFG->MC_BASE2.CFG_RTT.CFG_RTT = LIBERO_SETTING_CFG_RTT; in init_ddrc()
4367 DDRCFG->MC_BASE2.CFG_DLL_DISABLE.CFG_DLL_DISABLE =\ in init_ddrc()
4369 DDRCFG->MC_BASE2.CFG_REF_PER.CFG_REF_PER = LIBERO_SETTING_CFG_REF_PER; in init_ddrc()
4370 DDRCFG->MC_BASE2.CFG_STARTUP_DELAY.CFG_STARTUP_DELAY =\ in init_ddrc()
4372 DDRCFG->MC_BASE2.CFG_MEM_COLBITS.CFG_MEM_COLBITS =\ in init_ddrc()
4374 DDRCFG->MC_BASE2.CFG_MEM_ROWBITS.CFG_MEM_ROWBITS =\ in init_ddrc()
4376 DDRCFG->MC_BASE2.CFG_MEM_BANKBITS.CFG_MEM_BANKBITS =\ in init_ddrc()
4378 DDRCFG->MC_BASE2.CFG_ODT_RD_MAP_CS0.CFG_ODT_RD_MAP_CS0 =\ in init_ddrc()
4380 DDRCFG->MC_BASE2.CFG_ODT_RD_MAP_CS1.CFG_ODT_RD_MAP_CS1 =\ in init_ddrc()
4382 DDRCFG->MC_BASE2.CFG_ODT_RD_MAP_CS2.CFG_ODT_RD_MAP_CS2 =\ in init_ddrc()
4384 DDRCFG->MC_BASE2.CFG_ODT_RD_MAP_CS3.CFG_ODT_RD_MAP_CS3 =\ in init_ddrc()
4386 DDRCFG->MC_BASE2.CFG_ODT_RD_MAP_CS4.CFG_ODT_RD_MAP_CS4 =\ in init_ddrc()
4388 DDRCFG->MC_BASE2.CFG_ODT_RD_MAP_CS5.CFG_ODT_RD_MAP_CS5 =\ in init_ddrc()
4390 DDRCFG->MC_BASE2.CFG_ODT_RD_MAP_CS6.CFG_ODT_RD_MAP_CS6 =\ in init_ddrc()
4392 DDRCFG->MC_BASE2.CFG_ODT_RD_MAP_CS7.CFG_ODT_RD_MAP_CS7 =\ in init_ddrc()
4394 DDRCFG->MC_BASE2.CFG_ODT_WR_MAP_CS0.CFG_ODT_WR_MAP_CS0 =\ in init_ddrc()
4396 DDRCFG->MC_BASE2.CFG_ODT_WR_MAP_CS1.CFG_ODT_WR_MAP_CS1 =\ in init_ddrc()
4398 DDRCFG->MC_BASE2.CFG_ODT_WR_MAP_CS2.CFG_ODT_WR_MAP_CS2 =\ in init_ddrc()
4400 DDRCFG->MC_BASE2.CFG_ODT_WR_MAP_CS3.CFG_ODT_WR_MAP_CS3 =\ in init_ddrc()
4402 DDRCFG->MC_BASE2.CFG_ODT_WR_MAP_CS4.CFG_ODT_WR_MAP_CS4 =\ in init_ddrc()
4404 DDRCFG->MC_BASE2.CFG_ODT_WR_MAP_CS5.CFG_ODT_WR_MAP_CS5 =\ in init_ddrc()
4406 DDRCFG->MC_BASE2.CFG_ODT_WR_MAP_CS6.CFG_ODT_WR_MAP_CS6 =\ in init_ddrc()
4408 DDRCFG->MC_BASE2.CFG_ODT_WR_MAP_CS7.CFG_ODT_WR_MAP_CS7 =\ in init_ddrc()
4410 DDRCFG->MC_BASE2.CFG_ODT_RD_TURN_ON.CFG_ODT_RD_TURN_ON =\ in init_ddrc()
4412 DDRCFG->MC_BASE2.CFG_ODT_WR_TURN_ON.CFG_ODT_WR_TURN_ON =\ in init_ddrc()
4414 DDRCFG->MC_BASE2.CFG_ODT_RD_TURN_OFF.CFG_ODT_RD_TURN_OFF =\ in init_ddrc()
4416 DDRCFG->MC_BASE2.CFG_ODT_WR_TURN_OFF.CFG_ODT_WR_TURN_OFF =\ in init_ddrc()
4418 DDRCFG->MC_BASE2.CFG_EMR3.CFG_EMR3 = LIBERO_SETTING_CFG_EMR3; in init_ddrc()
4419 DDRCFG->MC_BASE2.CFG_TWO_T.CFG_TWO_T = LIBERO_SETTING_CFG_TWO_T; in init_ddrc()
4420 DDRCFG->MC_BASE2.CFG_TWO_T_SEL_CYCLE.CFG_TWO_T_SEL_CYCLE =\ in init_ddrc()
4422 DDRCFG->MC_BASE2.CFG_REGDIMM.CFG_REGDIMM = LIBERO_SETTING_CFG_REGDIMM; in init_ddrc()
4423 DDRCFG->MC_BASE2.CFG_MOD.CFG_MOD = LIBERO_SETTING_CFG_MOD; in init_ddrc()
4424 DDRCFG->MC_BASE2.CFG_XS.CFG_XS = LIBERO_SETTING_CFG_XS; in init_ddrc()
4425 DDRCFG->MC_BASE2.CFG_XSDLL.CFG_XSDLL = LIBERO_SETTING_CFG_XSDLL; in init_ddrc()
4426 DDRCFG->MC_BASE2.CFG_XPR.CFG_XPR = LIBERO_SETTING_CFG_XPR; in init_ddrc()
4427 DDRCFG->MC_BASE2.CFG_AL_MODE.CFG_AL_MODE = LIBERO_SETTING_CFG_AL_MODE; in init_ddrc()
4428 DDRCFG->MC_BASE2.CFG_CWL.CFG_CWL = LIBERO_SETTING_CFG_CWL; in init_ddrc()
4429 DDRCFG->MC_BASE2.CFG_BL_MODE.CFG_BL_MODE = LIBERO_SETTING_CFG_BL_MODE; in init_ddrc()
4430 DDRCFG->MC_BASE2.CFG_TDQS.CFG_TDQS = LIBERO_SETTING_CFG_TDQS; in init_ddrc()
4431 DDRCFG->MC_BASE2.CFG_RTT_WR.CFG_RTT_WR = LIBERO_SETTING_CFG_RTT_WR; in init_ddrc()
4432 DDRCFG->MC_BASE2.CFG_LP_ASR.CFG_LP_ASR = LIBERO_SETTING_CFG_LP_ASR; in init_ddrc()
4433 DDRCFG->MC_BASE2.CFG_AUTO_SR.CFG_AUTO_SR = LIBERO_SETTING_CFG_AUTO_SR; in init_ddrc()
4434 DDRCFG->MC_BASE2.CFG_SRT.CFG_SRT = LIBERO_SETTING_CFG_SRT; in init_ddrc()
4435 DDRCFG->MC_BASE2.CFG_ADDR_MIRROR.CFG_ADDR_MIRROR =\ in init_ddrc()
4437 DDRCFG->MC_BASE2.CFG_ZQ_CAL_TYPE.CFG_ZQ_CAL_TYPE =\ in init_ddrc()
4439 DDRCFG->MC_BASE2.CFG_ZQ_CAL_PER.CFG_ZQ_CAL_PER =\ in init_ddrc()
4441 DDRCFG->MC_BASE2.CFG_AUTO_ZQ_CAL_EN.CFG_AUTO_ZQ_CAL_EN =\ in init_ddrc()
4443 DDRCFG->MC_BASE2.CFG_MEMORY_TYPE.CFG_MEMORY_TYPE =\ in init_ddrc()
4445 DDRCFG->MC_BASE2.CFG_ONLY_SRANK_CMDS.CFG_ONLY_SRANK_CMDS =\ in init_ddrc()
4447 DDRCFG->MC_BASE2.CFG_NUM_RANKS.CFG_NUM_RANKS =\ in init_ddrc()
4449 DDRCFG->MC_BASE2.CFG_QUAD_RANK.CFG_QUAD_RANK =\ in init_ddrc()
4451 DDRCFG->MC_BASE2.CFG_EARLY_RANK_TO_WR_START.CFG_EARLY_RANK_TO_WR_START =\ in init_ddrc()
4453 DDRCFG->MC_BASE2.CFG_EARLY_RANK_TO_RD_START.CFG_EARLY_RANK_TO_RD_START =\ in init_ddrc()
4455 DDRCFG->MC_BASE2.CFG_PASR_BANK.CFG_PASR_BANK =\ in init_ddrc()
4457 DDRCFG->MC_BASE2.CFG_PASR_SEG.CFG_PASR_SEG = LIBERO_SETTING_CFG_PASR_SEG; in init_ddrc()
4458 DDRCFG->MC_BASE2.INIT_MRR_MODE.INIT_MRR_MODE =\ in init_ddrc()
4460 DDRCFG->MC_BASE2.INIT_MR_W_REQ.INIT_MR_W_REQ =\ in init_ddrc()
4462 DDRCFG->MC_BASE2.INIT_MR_ADDR.INIT_MR_ADDR = LIBERO_SETTING_INIT_MR_ADDR; in init_ddrc()
4463 DDRCFG->MC_BASE2.INIT_MR_WR_DATA.INIT_MR_WR_DATA =\ in init_ddrc()
4465 DDRCFG->MC_BASE2.INIT_MR_WR_MASK.INIT_MR_WR_MASK =\ in init_ddrc()
4467 DDRCFG->MC_BASE2.INIT_NOP.INIT_NOP = LIBERO_SETTING_INIT_NOP; in init_ddrc()
4468 DDRCFG->MC_BASE2.CFG_INIT_DURATION.CFG_INIT_DURATION =\ in init_ddrc()
4470 DDRCFG->MC_BASE2.CFG_ZQINIT_CAL_DURATION.CFG_ZQINIT_CAL_DURATION =\ in init_ddrc()
4472 DDRCFG->MC_BASE2.CFG_ZQ_CAL_L_DURATION.CFG_ZQ_CAL_L_DURATION =\ in init_ddrc()
4474 DDRCFG->MC_BASE2.CFG_ZQ_CAL_S_DURATION.CFG_ZQ_CAL_S_DURATION =\ in init_ddrc()
4476 DDRCFG->MC_BASE2.CFG_ZQ_CAL_R_DURATION.CFG_ZQ_CAL_R_DURATION =\ in init_ddrc()
4478 DDRCFG->MC_BASE2.CFG_MRR.CFG_MRR = LIBERO_SETTING_CFG_MRR; in init_ddrc()
4479 DDRCFG->MC_BASE2.CFG_MRW.CFG_MRW = LIBERO_SETTING_CFG_MRW; in init_ddrc()
4480 DDRCFG->MC_BASE2.CFG_ODT_POWERDOWN.CFG_ODT_POWERDOWN =\ in init_ddrc()
4482 DDRCFG->MC_BASE2.CFG_WL.CFG_WL = LIBERO_SETTING_CFG_WL; in init_ddrc()
4483 DDRCFG->MC_BASE2.CFG_RL.CFG_RL = LIBERO_SETTING_CFG_RL; in init_ddrc()
4484 DDRCFG->MC_BASE2.CFG_CAL_READ_PERIOD.CFG_CAL_READ_PERIOD =\ in init_ddrc()
4486 DDRCFG->MC_BASE2.CFG_NUM_CAL_READS.CFG_NUM_CAL_READS =\ in init_ddrc()
4488 DDRCFG->MC_BASE2.INIT_SELF_REFRESH.INIT_SELF_REFRESH =\ in init_ddrc()
4490 DDRCFG->MC_BASE2.INIT_POWER_DOWN.INIT_POWER_DOWN =\ in init_ddrc()
4492 DDRCFG->MC_BASE2.INIT_FORCE_WRITE.INIT_FORCE_WRITE =\ in init_ddrc()
4494 DDRCFG->MC_BASE2.INIT_FORCE_WRITE_CS.INIT_FORCE_WRITE_CS =\ in init_ddrc()
4496 DDRCFG->MC_BASE2.CFG_CTRLR_INIT_DISABLE.CFG_CTRLR_INIT_DISABLE =\ in init_ddrc()
4498 DDRCFG->MC_BASE2.INIT_RDIMM_COMPLETE.INIT_RDIMM_COMPLETE =\ in init_ddrc()
4500 DDRCFG->MC_BASE2.CFG_RDIMM_LAT.CFG_RDIMM_LAT =\ in init_ddrc()
4502 DDRCFG->MC_BASE2.CFG_RDIMM_BSIDE_INVERT.CFG_RDIMM_BSIDE_INVERT =\ in init_ddrc()
4504 DDRCFG->MC_BASE2.CFG_LRDIMM.CFG_LRDIMM = LIBERO_SETTING_CFG_LRDIMM; in init_ddrc()
4505 DDRCFG->MC_BASE2.INIT_MEMORY_RESET_MASK.INIT_MEMORY_RESET_MASK =\ in init_ddrc()
4507 DDRCFG->MC_BASE2.CFG_RD_PREAMB_TOGGLE.CFG_RD_PREAMB_TOGGLE =\ in init_ddrc()
4509 DDRCFG->MC_BASE2.CFG_RD_POSTAMBLE.CFG_RD_POSTAMBLE =\ in init_ddrc()
4511 DDRCFG->MC_BASE2.CFG_PU_CAL.CFG_PU_CAL = LIBERO_SETTING_CFG_PU_CAL; in init_ddrc()
4512 DDRCFG->MC_BASE2.CFG_DQ_ODT.CFG_DQ_ODT = LIBERO_SETTING_CFG_DQ_ODT; in init_ddrc()
4513 DDRCFG->MC_BASE2.CFG_CA_ODT.CFG_CA_ODT = LIBERO_SETTING_CFG_CA_ODT; in init_ddrc()
4514 DDRCFG->MC_BASE2.CFG_ZQLATCH_DURATION.CFG_ZQLATCH_DURATION =\ in init_ddrc()
4516 DDRCFG->MC_BASE2.INIT_CAL_SELECT.INIT_CAL_SELECT =\ in init_ddrc()
4518 DDRCFG->MC_BASE2.INIT_CAL_L_R_REQ.INIT_CAL_L_R_REQ =\ in init_ddrc()
4520 DDRCFG->MC_BASE2.INIT_CAL_L_B_SIZE.INIT_CAL_L_B_SIZE =\ in init_ddrc()
4522 DDRCFG->MC_BASE2.INIT_RWFIFO.INIT_RWFIFO = LIBERO_SETTING_INIT_RWFIFO; in init_ddrc()
4523 DDRCFG->MC_BASE2.INIT_RD_DQCAL.INIT_RD_DQCAL =\ in init_ddrc()
4525 DDRCFG->MC_BASE2.INIT_START_DQSOSC.INIT_START_DQSOSC =\ in init_ddrc()
4527 DDRCFG->MC_BASE2.INIT_STOP_DQSOSC.INIT_STOP_DQSOSC =\ in init_ddrc()
4529 DDRCFG->MC_BASE2.INIT_ZQ_CAL_START.INIT_ZQ_CAL_START =\ in init_ddrc()
4531 DDRCFG->MC_BASE2.CFG_WR_POSTAMBLE.CFG_WR_POSTAMBLE =\ in init_ddrc()
4533 DDRCFG->MC_BASE2.INIT_CAL_L_ADDR_0.INIT_CAL_L_ADDR_0 =\ in init_ddrc()
4535 DDRCFG->MC_BASE2.INIT_CAL_L_ADDR_1.INIT_CAL_L_ADDR_1 =\ in init_ddrc()
4537 DDRCFG->MC_BASE2.CFG_CTRLUPD_TRIG.CFG_CTRLUPD_TRIG =\ in init_ddrc()
4539 DDRCFG->MC_BASE2.CFG_CTRLUPD_START_DELAY.CFG_CTRLUPD_START_DELAY =\ in init_ddrc()
4541 DDRCFG->MC_BASE2.CFG_DFI_T_CTRLUPD_MAX.CFG_DFI_T_CTRLUPD_MAX =\ in init_ddrc()
4543 DDRCFG->MC_BASE2.CFG_CTRLR_BUSY_SEL.CFG_CTRLR_BUSY_SEL =\ in init_ddrc()
4545 DDRCFG->MC_BASE2.CFG_CTRLR_BUSY_VALUE.CFG_CTRLR_BUSY_VALUE =\ in init_ddrc()
4547 DDRCFG->MC_BASE2.CFG_CTRLR_BUSY_TURN_OFF_DELAY.CFG_CTRLR_BUSY_TURN_OFF_DELAY =\ in init_ddrc()
4549 DDRCFG->MC_BASE2.CFG_CTRLR_BUSY_SLOW_RESTART_WINDOW.CFG_CTRLR_BUSY_SLOW_RESTART_WINDOW =\ in init_ddrc()
4551 DDRCFG->MC_BASE2.CFG_CTRLR_BUSY_RESTART_HOLDOFF.CFG_CTRLR_BUSY_RESTART_HOLDOFF =\ in init_ddrc()
4553 DDRCFG->MC_BASE2.CFG_PARITY_RDIMM_DELAY.CFG_PARITY_RDIMM_DELAY =\ in init_ddrc()
4555 DDRCFG->MC_BASE2.CFG_CTRLR_BUSY_ENABLE.CFG_CTRLR_BUSY_ENABLE =\ in init_ddrc()
4557 DDRCFG->MC_BASE2.CFG_ASYNC_ODT.CFG_ASYNC_ODT =\ in init_ddrc()
4559 DDRCFG->MC_BASE2.CFG_ZQ_CAL_DURATION.CFG_ZQ_CAL_DURATION =\ in init_ddrc()
4561 DDRCFG->MC_BASE2.CFG_MRRI.CFG_MRRI = LIBERO_SETTING_CFG_MRRI; in init_ddrc()
4562 DDRCFG->MC_BASE2.INIT_ODT_FORCE_EN.INIT_ODT_FORCE_EN =\ in init_ddrc()
4564 DDRCFG->MC_BASE2.INIT_ODT_FORCE_RANK.INIT_ODT_FORCE_RANK =\ in init_ddrc()
4566 DDRCFG->MC_BASE2.CFG_PHYUPD_ACK_DELAY.CFG_PHYUPD_ACK_DELAY =\ in init_ddrc()
4568 DDRCFG->MC_BASE2.CFG_MIRROR_X16_BG0_BG1.CFG_MIRROR_X16_BG0_BG1 =\ in init_ddrc()
4570 DDRCFG->MC_BASE2.INIT_PDA_MR_W_REQ.INIT_PDA_MR_W_REQ =\ in init_ddrc()
4572 DDRCFG->MC_BASE2.INIT_PDA_NIBBLE_SELECT.INIT_PDA_NIBBLE_SELECT =\ in init_ddrc()
4574 DDRCFG->MC_BASE2.CFG_DRAM_CLK_DISABLE_IN_SELF_REFRESH.CFG_DRAM_CLK_DISABLE_IN_SELF_REFRESH =\ in init_ddrc()
4576 DDRCFG->MC_BASE2.CFG_CKSRE.CFG_CKSRE = LIBERO_SETTING_CFG_CKSRE; in init_ddrc()
4577 DDRCFG->MC_BASE2.CFG_CKSRX.CFG_CKSRX = LIBERO_SETTING_CFG_CKSRX; in init_ddrc()
4578 DDRCFG->MC_BASE2.CFG_RCD_STAB.CFG_RCD_STAB = LIBERO_SETTING_CFG_RCD_STAB; in init_ddrc()
4579 DDRCFG->MC_BASE2.CFG_DFI_T_CTRL_DELAY.CFG_DFI_T_CTRL_DELAY =\ in init_ddrc()
4581 DDRCFG->MC_BASE2.CFG_DFI_T_DRAM_CLK_ENABLE.CFG_DFI_T_DRAM_CLK_ENABLE =\ in init_ddrc()
4583 DDRCFG->MC_BASE2.CFG_IDLE_TIME_TO_SELF_REFRESH.CFG_IDLE_TIME_TO_SELF_REFRESH =\ in init_ddrc()
4585 DDRCFG->MC_BASE2.CFG_IDLE_TIME_TO_POWER_DOWN.CFG_IDLE_TIME_TO_POWER_DOWN =\ in init_ddrc()
4587 DDRCFG->MC_BASE2.CFG_BURST_RW_REFRESH_HOLDOFF.CFG_BURST_RW_REFRESH_HOLDOFF =\ in init_ddrc()
4589 DDRCFG->MC_BASE2.CFG_BG_INTERLEAVE.CFG_BG_INTERLEAVE =\ in init_ddrc()
4591 DDRCFG->MC_BASE2.CFG_REFRESH_DURING_PHY_TRAINING.CFG_REFRESH_DURING_PHY_TRAINING =\ in init_ddrc()
4593 DDRCFG->MPFE.CFG_STARVE_TIMEOUT_P0.CFG_STARVE_TIMEOUT_P0 =\ in init_ddrc()
4595 DDRCFG->MPFE.CFG_STARVE_TIMEOUT_P1.CFG_STARVE_TIMEOUT_P1 =\ in init_ddrc()
4597 DDRCFG->MPFE.CFG_STARVE_TIMEOUT_P2.CFG_STARVE_TIMEOUT_P2 =\ in init_ddrc()
4599 DDRCFG->MPFE.CFG_STARVE_TIMEOUT_P3.CFG_STARVE_TIMEOUT_P3 =\ in init_ddrc()
4601 DDRCFG->MPFE.CFG_STARVE_TIMEOUT_P4.CFG_STARVE_TIMEOUT_P4 =\ in init_ddrc()
4603 DDRCFG->MPFE.CFG_STARVE_TIMEOUT_P5.CFG_STARVE_TIMEOUT_P5 =\ in init_ddrc()
4605 DDRCFG->MPFE.CFG_STARVE_TIMEOUT_P6.CFG_STARVE_TIMEOUT_P6 =\ in init_ddrc()
4607 DDRCFG->MPFE.CFG_STARVE_TIMEOUT_P7.CFG_STARVE_TIMEOUT_P7 =\ in init_ddrc()
4609 DDRCFG->REORDER.CFG_REORDER_EN.CFG_REORDER_EN =\ in init_ddrc()
4611 DDRCFG->REORDER.CFG_REORDER_QUEUE_EN.CFG_REORDER_QUEUE_EN =\ in init_ddrc()
4613 DDRCFG->REORDER.CFG_INTRAPORT_REORDER_EN.CFG_INTRAPORT_REORDER_EN =\ in init_ddrc()
4615 DDRCFG->REORDER.CFG_MAINTAIN_COHERENCY.CFG_MAINTAIN_COHERENCY =\ in init_ddrc()
4617 DDRCFG->REORDER.CFG_Q_AGE_LIMIT.CFG_Q_AGE_LIMIT =\ in init_ddrc()
4619 DDRCFG->REORDER.CFG_RO_CLOSED_PAGE_POLICY.CFG_RO_CLOSED_PAGE_POLICY =\ in init_ddrc()
4621 DDRCFG->REORDER.CFG_REORDER_RW_ONLY.CFG_REORDER_RW_ONLY =\ in init_ddrc()
4623 DDRCFG->REORDER.CFG_RO_PRIORITY_EN.CFG_RO_PRIORITY_EN =\ in init_ddrc()
4625 DDRCFG->RMW.CFG_DM_EN.CFG_DM_EN = LIBERO_SETTING_CFG_DM_EN; in init_ddrc()
4626 DDRCFG->RMW.CFG_RMW_EN.CFG_RMW_EN = LIBERO_SETTING_CFG_RMW_EN; in init_ddrc()
4627 DDRCFG->ECC.CFG_ECC_CORRECTION_EN.CFG_ECC_CORRECTION_EN =\ in init_ddrc()
4629 DDRCFG->ECC.CFG_ECC_BYPASS.CFG_ECC_BYPASS = LIBERO_SETTING_CFG_ECC_BYPASS; in init_ddrc()
4630 DDRCFG->ECC.INIT_WRITE_DATA_1B_ECC_ERROR_GEN.INIT_WRITE_DATA_1B_ECC_ERROR_GEN =\ in init_ddrc()
4632 DDRCFG->ECC.INIT_WRITE_DATA_2B_ECC_ERROR_GEN.INIT_WRITE_DATA_2B_ECC_ERROR_GEN =\ in init_ddrc()
4634 DDRCFG->ECC.CFG_ECC_1BIT_INT_THRESH.CFG_ECC_1BIT_INT_THRESH =\ in init_ddrc()
4636 DDRCFG->READ_CAPT.INIT_READ_CAPTURE_ADDR.INIT_READ_CAPTURE_ADDR =\ in init_ddrc()
4638 DDRCFG->MTA.CFG_ERROR_GROUP_SEL.CFG_ERROR_GROUP_SEL =\ in init_ddrc()
4640 DDRCFG->MTA.CFG_DATA_SEL.CFG_DATA_SEL = LIBERO_SETTING_CFG_DATA_SEL; in init_ddrc()
4641 DDRCFG->MTA.CFG_TRIG_MODE.CFG_TRIG_MODE = LIBERO_SETTING_CFG_TRIG_MODE; in init_ddrc()
4642 DDRCFG->MTA.CFG_POST_TRIG_CYCS.CFG_POST_TRIG_CYCS =\ in init_ddrc()
4644 DDRCFG->MTA.CFG_TRIG_MASK.CFG_TRIG_MASK = LIBERO_SETTING_CFG_TRIG_MASK; in init_ddrc()
4645 DDRCFG->MTA.CFG_EN_MASK.CFG_EN_MASK = LIBERO_SETTING_CFG_EN_MASK; in init_ddrc()
4646 DDRCFG->MTA.MTC_ACQ_ADDR.MTC_ACQ_ADDR = LIBERO_SETTING_MTC_ACQ_ADDR; in init_ddrc()
4647 DDRCFG->MTA.CFG_TRIG_MT_ADDR_0.CFG_TRIG_MT_ADDR_0 =\ in init_ddrc()
4649 DDRCFG->MTA.CFG_TRIG_MT_ADDR_1.CFG_TRIG_MT_ADDR_1 =\ in init_ddrc()
4651 DDRCFG->MTA.CFG_TRIG_ERR_MASK_0.CFG_TRIG_ERR_MASK_0 =\ in init_ddrc()
4653 DDRCFG->MTA.CFG_TRIG_ERR_MASK_1.CFG_TRIG_ERR_MASK_1 =\ in init_ddrc()
4655 DDRCFG->MTA.CFG_TRIG_ERR_MASK_2.CFG_TRIG_ERR_MASK_2 =\ in init_ddrc()
4657 DDRCFG->MTA.CFG_TRIG_ERR_MASK_3.CFG_TRIG_ERR_MASK_3 =\ in init_ddrc()
4659 DDRCFG->MTA.CFG_TRIG_ERR_MASK_4.CFG_TRIG_ERR_MASK_4 =\ in init_ddrc()
4661 DDRCFG->MTA.MTC_ACQ_WR_DATA_0.MTC_ACQ_WR_DATA_0 =\ in init_ddrc()
4663 DDRCFG->MTA.MTC_ACQ_WR_DATA_1.MTC_ACQ_WR_DATA_1 =\ in init_ddrc()
4665 DDRCFG->MTA.MTC_ACQ_WR_DATA_2.MTC_ACQ_WR_DATA_2 =\ in init_ddrc()
4667 DDRCFG->MTA.CFG_PRE_TRIG_CYCS.CFG_PRE_TRIG_CYCS =\ in init_ddrc()
4669 DDRCFG->MTA.CFG_DATA_SEL_FIRST_ERROR.CFG_DATA_SEL_FIRST_ERROR =\ in init_ddrc()
4671 DDRCFG->DYN_WIDTH_ADJ.CFG_DQ_WIDTH.CFG_DQ_WIDTH =\ in init_ddrc()
4673 DDRCFG->DYN_WIDTH_ADJ.CFG_ACTIVE_DQ_SEL.CFG_ACTIVE_DQ_SEL =\ in init_ddrc()
4675 DDRCFG->CA_PAR_ERR.INIT_CA_PARITY_ERROR_GEN_REQ.INIT_CA_PARITY_ERROR_GEN_REQ =\ in init_ddrc()
4677 DDRCFG->CA_PAR_ERR.INIT_CA_PARITY_ERROR_GEN_CMD.INIT_CA_PARITY_ERROR_GEN_CMD =\ in init_ddrc()
4679 DDRCFG->DFI.CFG_DFI_T_RDDATA_EN.CFG_DFI_T_RDDATA_EN =\ in init_ddrc()
4681 DDRCFG->DFI.CFG_DFI_T_PHY_RDLAT.CFG_DFI_T_PHY_RDLAT =\ in init_ddrc()
4683 DDRCFG->DFI.CFG_DFI_T_PHY_WRLAT.CFG_DFI_T_PHY_WRLAT =\ in init_ddrc()
4685 DDRCFG->DFI.CFG_DFI_PHYUPD_EN.CFG_DFI_PHYUPD_EN =\ in init_ddrc()
4687 DDRCFG->DFI.INIT_DFI_LP_DATA_REQ.INIT_DFI_LP_DATA_REQ =\ in init_ddrc()
4689 DDRCFG->DFI.INIT_DFI_LP_CTRL_REQ.INIT_DFI_LP_CTRL_REQ =\ in init_ddrc()
4691 DDRCFG->DFI.INIT_DFI_LP_WAKEUP.INIT_DFI_LP_WAKEUP =\ in init_ddrc()
4693 DDRCFG->DFI.INIT_DFI_DRAM_CLK_DISABLE.INIT_DFI_DRAM_CLK_DISABLE =\ in init_ddrc()
4695 DDRCFG->DFI.CFG_DFI_DATA_BYTE_DISABLE.CFG_DFI_DATA_BYTE_DISABLE =\ in init_ddrc()
4697 DDRCFG->DFI.CFG_DFI_LVL_SEL.CFG_DFI_LVL_SEL =\ in init_ddrc()
4699 DDRCFG->DFI.CFG_DFI_LVL_PERIODIC.CFG_DFI_LVL_PERIODIC =\ in init_ddrc()
4701 DDRCFG->DFI.CFG_DFI_LVL_PATTERN.CFG_DFI_LVL_PATTERN =\ in init_ddrc()
4703 DDRCFG->DFI.PHY_DFI_INIT_START.PHY_DFI_INIT_START =\ in init_ddrc()
4705 DDRCFG->AXI_IF.CFG_AXI_START_ADDRESS_AXI1_0.CFG_AXI_START_ADDRESS_AXI1_0 =\ in init_ddrc()
4707 DDRCFG->AXI_IF.CFG_AXI_START_ADDRESS_AXI1_1.CFG_AXI_START_ADDRESS_AXI1_1 =\ in init_ddrc()
4709 DDRCFG->AXI_IF.CFG_AXI_START_ADDRESS_AXI2_0.CFG_AXI_START_ADDRESS_AXI2_0 =\ in init_ddrc()
4711 DDRCFG->AXI_IF.CFG_AXI_START_ADDRESS_AXI2_1.CFG_AXI_START_ADDRESS_AXI2_1 =\ in init_ddrc()
4713 DDRCFG->AXI_IF.CFG_AXI_END_ADDRESS_AXI1_0.CFG_AXI_END_ADDRESS_AXI1_0 =\ in init_ddrc()
4715 DDRCFG->AXI_IF.CFG_AXI_END_ADDRESS_AXI1_1.CFG_AXI_END_ADDRESS_AXI1_1 =\ in init_ddrc()
4717 DDRCFG->AXI_IF.CFG_AXI_END_ADDRESS_AXI2_0.CFG_AXI_END_ADDRESS_AXI2_0 =\ in init_ddrc()
4719 DDRCFG->AXI_IF.CFG_AXI_END_ADDRESS_AXI2_1.CFG_AXI_END_ADDRESS_AXI2_1 =\ in init_ddrc()
4721 DDRCFG->AXI_IF.CFG_MEM_START_ADDRESS_AXI1_0.CFG_MEM_START_ADDRESS_AXI1_0 =\ in init_ddrc()
4723 DDRCFG->AXI_IF.CFG_MEM_START_ADDRESS_AXI1_1.CFG_MEM_START_ADDRESS_AXI1_1 =\ in init_ddrc()
4725 DDRCFG->AXI_IF.CFG_MEM_START_ADDRESS_AXI2_0.CFG_MEM_START_ADDRESS_AXI2_0 =\ in init_ddrc()
4727 DDRCFG->AXI_IF.CFG_MEM_START_ADDRESS_AXI2_1.CFG_MEM_START_ADDRESS_AXI2_1 =\ in init_ddrc()
4729 DDRCFG->AXI_IF.CFG_ENABLE_BUS_HOLD_AXI1.CFG_ENABLE_BUS_HOLD_AXI1 =\ in init_ddrc()
4731 DDRCFG->AXI_IF.CFG_ENABLE_BUS_HOLD_AXI2.CFG_ENABLE_BUS_HOLD_AXI2 =\ in init_ddrc()
4733 DDRCFG->AXI_IF.CFG_AXI_AUTO_PCH.CFG_AXI_AUTO_PCH =\ in init_ddrc()
4735 DDRCFG->csr_custom.PHY_RESET_CONTROL.PHY_RESET_CONTROL =\ in init_ddrc()
4737 DDRCFG->csr_custom.PHY_RESET_CONTROL.PHY_RESET_CONTROL =\ in init_ddrc()
4739 DDRCFG->csr_custom.PHY_PC_RANK.PHY_PC_RANK = LIBERO_SETTING_PHY_PC_RANK; in init_ddrc()
4740 DDRCFG->csr_custom.PHY_RANKS_TO_TRAIN.PHY_RANKS_TO_TRAIN =\ in init_ddrc()
4742 DDRCFG->csr_custom.PHY_WRITE_REQUEST.PHY_WRITE_REQUEST =\ in init_ddrc()
4744 DDRCFG->csr_custom.PHY_READ_REQUEST.PHY_READ_REQUEST =\ in init_ddrc()
4746 DDRCFG->csr_custom.PHY_WRITE_LEVEL_DELAY.PHY_WRITE_LEVEL_DELAY =\ in init_ddrc()
4748 DDRCFG->csr_custom.PHY_GATE_TRAIN_DELAY.PHY_GATE_TRAIN_DELAY =\ in init_ddrc()
4750 DDRCFG->csr_custom.PHY_EYE_TRAIN_DELAY.PHY_EYE_TRAIN_DELAY =\ in init_ddrc()
4752 DDRCFG->csr_custom.PHY_EYE_PAT.PHY_EYE_PAT = LIBERO_SETTING_PHY_EYE_PAT; in init_ddrc()
4753 DDRCFG->csr_custom.PHY_START_RECAL.PHY_START_RECAL =\ in init_ddrc()
4755 DDRCFG->csr_custom.PHY_CLR_DFI_LVL_PERIODIC.PHY_CLR_DFI_LVL_PERIODIC =\ in init_ddrc()
4757 DDRCFG->csr_custom.PHY_TRAIN_STEP_ENABLE.PHY_TRAIN_STEP_ENABLE =\ in init_ddrc()
4759 DDRCFG->csr_custom.PHY_LPDDR_DQ_CAL_PAT.PHY_LPDDR_DQ_CAL_PAT =\ in init_ddrc()
4761 DDRCFG->csr_custom.PHY_INDPNDT_TRAINING.PHY_INDPNDT_TRAINING =\ in init_ddrc()
4763 DDRCFG->csr_custom.PHY_ENCODED_QUAD_CS.PHY_ENCODED_QUAD_CS =\ in init_ddrc()
4765 DDRCFG->csr_custom.PHY_HALF_CLK_DLY_ENABLE.PHY_HALF_CLK_DLY_ENABLE =\ in init_ddrc()
5140 (uint32_t *)&DDRCFG->ADDR_MAP,\ in debug_read_ddrcfg()
5141 (sizeof(DDRCFG->ADDR_MAP)/4U)); in debug_read_ddrcfg()
5143 (uint32_t *)&DDRCFG->MC_BASE3,\ in debug_read_ddrcfg()
5144 (sizeof(DDRCFG->MC_BASE3)/4U)); in debug_read_ddrcfg()
5146 (uint32_t *)&DDRCFG->MC_BASE1,\ in debug_read_ddrcfg()
5147 (sizeof(DDRCFG->MC_BASE1)/4U)); in debug_read_ddrcfg()
5149 (uint32_t *)&DDRCFG->MC_BASE2,\ in debug_read_ddrcfg()
5150 (sizeof(DDRCFG->MC_BASE2)/4U)); in debug_read_ddrcfg()
5152 (uint32_t *)&DDRCFG->MPFE,\ in debug_read_ddrcfg()
5153 (sizeof(DDRCFG->MPFE)/4U)); in debug_read_ddrcfg()
5155 (uint32_t *)&DDRCFG->REORDER,\ in debug_read_ddrcfg()
5156 (sizeof(DDRCFG->REORDER)/4U)); in debug_read_ddrcfg()
5158 (uint32_t *)&DDRCFG->RMW,\ in debug_read_ddrcfg()
5159 (sizeof(DDRCFG->RMW)/4U)); in debug_read_ddrcfg()
5161 (uint32_t *)&DDRCFG->ECC,\ in debug_read_ddrcfg()
5162 (sizeof(DDRCFG->ECC)/4U)); in debug_read_ddrcfg()
5164 (uint32_t *)&DDRCFG->READ_CAPT,\ in debug_read_ddrcfg()
5165 (sizeof(DDRCFG->READ_CAPT)/4U)); in debug_read_ddrcfg()
5167 (uint32_t *)&DDRCFG->MTA,\ in debug_read_ddrcfg()
5168 (sizeof(DDRCFG->MTA)/4U)); in debug_read_ddrcfg()
5170 (uint32_t *)&DDRCFG->DYN_WIDTH_ADJ,\ in debug_read_ddrcfg()
5171 (sizeof(DDRCFG->DYN_WIDTH_ADJ)/4U)); in debug_read_ddrcfg()
5173 (uint32_t *)&DDRCFG->CA_PAR_ERR,\ in debug_read_ddrcfg()
5174 (sizeof(DDRCFG->CA_PAR_ERR)/4U)); in debug_read_ddrcfg()
5176 (uint32_t *)&DDRCFG->DFI,\ in debug_read_ddrcfg()
5177 (sizeof(DDRCFG->DFI)/4U)); in debug_read_ddrcfg()
5179 (uint32_t *)&DDRCFG->AXI_IF,\ in debug_read_ddrcfg()
5180 (sizeof(DDRCFG->AXI_IF)/4U)); in debug_read_ddrcfg()
5182 (uint32_t *)&DDRCFG->csr_custom,\ in debug_read_ddrcfg()
5183 (sizeof(DDRCFG->csr_custom)/4U)); in debug_read_ddrcfg()