Lines Matching refs:PLIC
707 #define PLIC ((PLIC_Type * const)PLIC_BASE_ADDR) macro
727 PLIC->HART0_MMODE_ENA[inc] = 0U; in PLIC_init()
737 PLIC->TARGET[TARGET_OFFSET_HART0_M].PRIORITY_THRESHOLD = 0U; in PLIC_init()
742 PLIC->HART1_MMODE_ENA[inc] = 0U; in PLIC_init()
743 PLIC->HART1_SMODE_ENA[inc] = 0U; in PLIC_init()
746 PLIC->TARGET[TARGET_OFFSET_HART1_M].PRIORITY_THRESHOLD = 0U; in PLIC_init()
748 PLIC->TARGET[TARGET_OFFSET_HART1_S].PRIORITY_THRESHOLD = 7U; in PLIC_init()
753 PLIC->HART2_MMODE_ENA[inc] = 0U; in PLIC_init()
754 PLIC->HART2_SMODE_ENA[inc] = 0U; in PLIC_init()
757 PLIC->TARGET[TARGET_OFFSET_HART2_M].PRIORITY_THRESHOLD = 0U; in PLIC_init()
759 PLIC->TARGET[TARGET_OFFSET_HART2_S].PRIORITY_THRESHOLD = 7U; in PLIC_init()
764 PLIC->HART3_MMODE_ENA[inc] = 0U; in PLIC_init()
765 PLIC->HART3_SMODE_ENA[inc] = 0U; in PLIC_init()
768 PLIC->TARGET[TARGET_OFFSET_HART3_M].PRIORITY_THRESHOLD = 0U; in PLIC_init()
770 PLIC->TARGET[TARGET_OFFSET_HART3_S].PRIORITY_THRESHOLD = 7U; in PLIC_init()
775 PLIC->HART4_MMODE_ENA[inc] = 0U; in PLIC_init()
776 PLIC->HART4_SMODE_ENA[inc] = 0U; in PLIC_init()
779 PLIC->TARGET[TARGET_OFFSET_HART4_M].PRIORITY_THRESHOLD = 0U; in PLIC_init()
781 PLIC->TARGET[TARGET_OFFSET_HART4_S].PRIORITY_THRESHOLD = 7U; in PLIC_init()
805 current = PLIC->HART0_MMODE_ENA[IRQn / 32U]; in PLIC_EnableIRQ()
807 PLIC->HART0_MMODE_ENA[IRQn / 32U] = current; in PLIC_EnableIRQ()
810 current = PLIC->HART1_MMODE_ENA[IRQn / 32U]; in PLIC_EnableIRQ()
812 PLIC->HART1_MMODE_ENA[IRQn / 32U] = current; in PLIC_EnableIRQ()
815 current = PLIC->HART2_MMODE_ENA[IRQn / 32U]; in PLIC_EnableIRQ()
817 PLIC->HART2_MMODE_ENA[IRQn / 32U] = current; in PLIC_EnableIRQ()
820 current = PLIC->HART3_MMODE_ENA[IRQn / 32U]; in PLIC_EnableIRQ()
822 PLIC->HART3_MMODE_ENA[IRQn / 32U] = current; in PLIC_EnableIRQ()
825 current = PLIC->HART4_MMODE_ENA[IRQn / 32U]; in PLIC_EnableIRQ()
827 PLIC->HART4_MMODE_ENA[IRQn / 32U] = current; in PLIC_EnableIRQ()
855 current = PLIC->HART0_MMODE_ENA[IRQn / 32U]; in PLIC_DisableIRQ()
857 PLIC->HART0_MMODE_ENA[IRQn / 32U] = current; in PLIC_DisableIRQ()
860 current = PLIC->HART1_MMODE_ENA[IRQn / 32U]; in PLIC_DisableIRQ()
862 PLIC->HART1_MMODE_ENA[IRQn / 32U] = current; in PLIC_DisableIRQ()
865 current = PLIC->HART2_MMODE_ENA[IRQn / 32U]; in PLIC_DisableIRQ()
867 PLIC->HART2_MMODE_ENA[IRQn / 32U] = current; in PLIC_DisableIRQ()
870 current = PLIC->HART3_MMODE_ENA[IRQn / 32U]; in PLIC_DisableIRQ()
872 PLIC->HART3_MMODE_ENA[IRQn / 32U] = current; in PLIC_DisableIRQ()
875 current = PLIC->HART4_MMODE_ENA[IRQn / 32U]; in PLIC_DisableIRQ()
877 PLIC->HART4_MMODE_ENA[IRQn / 32U] = current; in PLIC_DisableIRQ()
892 PLIC->SOURCE_PRIORITY[IRQn-1] = priority; in PLIC_SetPriority()
906 ret_val = PLIC->SOURCE_PRIORITY[IRQn-1]; in PLIC_GetPriority()
915 return (PLIC->PENDING_ARRAY[IRQn/32U] & (0x01U<<(IRQn%32U))); in PLIC_pending()
925 return (PLIC->TARGET[plic_hart_lookup[hart_id]].CLAIM_COMPLETE); in PLIC_ClaimIRQ()
938 PLIC->TARGET[plic_hart_lookup[hart_id]].CLAIM_COMPLETE = source; in PLIC_CompleteIRQ()
959 PLIC->TARGET[plic_hart_lookup[hart_id]].PRIORITY_THRESHOLD = threshold; in PLIC_SetPriority_Threshold()
996 PLIC->SOURCE_PRIORITY[inc] = 0U; in PLIC_init_on_reset()
1001 PLIC->TARGET[inc].PRIORITY_THRESHOLD = 7U; in PLIC_init_on_reset()
1007 PLIC->HART0_MMODE_ENA[inc] = 0U; in PLIC_init_on_reset()
1008 PLIC->HART1_MMODE_ENA[inc] = 0U; in PLIC_init_on_reset()
1009 PLIC->HART1_SMODE_ENA[inc] = 0U; in PLIC_init_on_reset()
1010 PLIC->HART2_MMODE_ENA[inc] = 0U; in PLIC_init_on_reset()
1011 PLIC->HART2_SMODE_ENA[inc] = 0U; in PLIC_init_on_reset()
1012 PLIC->HART3_MMODE_ENA[inc] = 0U; in PLIC_init_on_reset()
1013 PLIC->HART3_SMODE_ENA[inc] = 0U; in PLIC_init_on_reset()
1014 PLIC->HART4_MMODE_ENA[inc] = 0U; in PLIC_init_on_reset()
1015 PLIC->HART4_SMODE_ENA[inc] = 0U; in PLIC_init_on_reset()