27     return (AXISW->HWCFG);  in MSS_AXISW_get_hwcfg()
33     return (AXISW->VID);  in MSS_AXISW_get_vid()
54     while(AXISW->CMD & AXISW_CMD_EN_MASK);  /*make sure previous command completed*/  in MSS_AXISW_write_qos_val()
56     AXISW->DATA = data & AXISW_DATA_QOSVAL_MASK;  /*only valid values of bits[3:0]*/  in MSS_AXISW_write_qos_val()
58     AXISW->CMD = (AXISW_CMD_RW_MASK |  in MSS_AXISW_write_qos_val()
63     while(AXISW->CMD & AXISW_CMD_EN_MASK);    /*Wait for command to complete*/  in MSS_AXISW_write_qos_val()
65     return ((AXISW->CMD & AXISW_CMD_ERR_MASK) >> AXISW_CMD_ERR);   /*return error bit value*/  in MSS_AXISW_write_qos_val()
84     while(AXISW->CMD & AXISW_CMD_EN_MASK);  in MSS_AXISW_read_qos_val()
86     AXISW->CMD &= ~(AXISW_CMD_RW_MASK);  /*Clear read/write bit*/  in MSS_AXISW_read_qos_val()
88     AXISW->CMD = ((master_port_num << AXISW_CMD_RWCHAN) | (MSS_AXISW_QOS_VAL) | AXISW_CMD_EN_MASK);  in MSS_AXISW_read_qos_val()
90     while(AXISW->CMD & AXISW_CMD_EN_MASK);  in MSS_AXISW_read_qos_val()
92     *rd_data = AXISW->DATA & AXISW_DATA_QOSVAL_MASK;  in MSS_AXISW_read_qos_val()
94     return ((AXISW->CMD & AXISW_CMD_ERR_MASK) >> AXISW_CMD_ERR);   /*return error bit value*/  in MSS_AXISW_read_qos_val()
110     while(AXISW->CMD & AXISW_CMD_EN_MASK);  /*make sure previous command completed*/  in MSS_AXISW_write_rate()
111     AXISW->DATA = ((peak_rate) << AXISW_DATA_PEAKRT) | ((xct_rate) << AXISW_DATA_XCTRT) ;  in MSS_AXISW_write_rate()
113     AXISW->CMD = (AXISW_CMD_RW_MASK |  in MSS_AXISW_write_rate()
118     while(AXISW->CMD & AXISW_CMD_EN_MASK);    /*Wait for command to complete*/  in MSS_AXISW_write_rate()
120     return ((AXISW->CMD & AXISW_CMD_ERR_MASK) >> AXISW_CMD_ERR);   /*return error bit value*/  in MSS_AXISW_write_rate()
135     while(AXISW->CMD & AXISW_CMD_EN_MASK);  in MSS_AXISW_read_rate()
137     AXISW->CMD &= ~(AXISW_CMD_RW_MASK);  /*Clear read/write and command EN bit*/  in MSS_AXISW_read_rate()
139     AXISW->CMD = ((master_port_num << AXISW_CMD_RWCHAN) |  in MSS_AXISW_read_rate()
143     while(AXISW->CMD & AXISW_CMD_EN_MASK);  in MSS_AXISW_read_rate()
145     temp = AXISW->DATA;  in MSS_AXISW_read_rate()
150     return ((AXISW->CMD & AXISW_CMD_ERR_MASK) >> AXISW_CMD_ERR);   /*return error bit value*/  in MSS_AXISW_read_rate()
167     while(AXISW->CMD & AXISW_CMD_EN_MASK);  /*make sure previous command completed*/  in MSS_AXISW_write_burstiness()
179         AXISW->DATA = ((burstiness_val - 1u) << AXISW_DATA_BURSTI) | (regulator_en & 0x01);  in MSS_AXISW_write_burstiness()
182     AXISW->CMD = (AXISW_CMD_RW_MASK |  in MSS_AXISW_write_burstiness()
187     while(AXISW->CMD & AXISW_CMD_EN_MASK);      /*Wait for command to complete*/  in MSS_AXISW_write_burstiness()
189     return ((AXISW->CMD & AXISW_CMD_ERR_MASK) >> AXISW_CMD_ERR);   /*return error bit value*/  in MSS_AXISW_write_burstiness()
202     while(AXISW->CMD & AXISW_CMD_EN_MASK);  in MSS_AXISW_read_burstiness()
204     AXISW->CMD &= ~(AXISW_CMD_RW_MASK);  /*Clear read/write and command EN bit*/  in MSS_AXISW_read_burstiness()
206     AXISW->CMD = ((master_port_num << AXISW_CMD_RWCHAN) |  in MSS_AXISW_read_burstiness()
210     while(AXISW->CMD & AXISW_CMD_EN_MASK);  in MSS_AXISW_read_burstiness()
212     *burstiness_val = ((AXISW->DATA & AXISW_DATA_BURSTI_MASK) >> AXISW_DATA_BURSTI) + 1u;  in MSS_AXISW_read_burstiness()
214     return ((AXISW->CMD & AXISW_CMD_ERR_MASK) >> AXISW_CMD_ERR);   /*return error bit value*/  in MSS_AXISW_read_burstiness()
220     while(AXISW->CMD & AXISW_CMD_EN_MASK);  /*make sure previous command completed*/  in MSS_AXISW_write_slave_ready()
222     AXISW->DATA = slave_ready_en & 0x01;  /*only valid value of bit0*/  in MSS_AXISW_write_slave_ready()
224     AXISW->CMD = (AXISW_CMD_RW_MASK |  in MSS_AXISW_write_slave_ready()
229     while(AXISW->CMD & AXISW_CMD_EN_MASK);    /*Wait for command to complete*/  in MSS_AXISW_write_slave_ready()
231     return ((AXISW->CMD & AXISW_CMD_ERR_MASK) >> AXISW_CMD_ERR);   /*return error bit value*/  in MSS_AXISW_write_slave_ready()
247     while(AXISW->CMD & AXISW_CMD_EN_MASK);  in MSS_AXISW_read_slave_ready()
249     AXISW->CMD &= ~(AXISW_CMD_RW_MASK);  /*Clear read/write bit*/  in MSS_AXISW_read_slave_ready()
251     AXISW->CMD = ((master_port_num << AXISW_CMD_RWCHAN) |  in MSS_AXISW_read_slave_ready()
255     while(AXISW->CMD & AXISW_CMD_EN_MASK);  in MSS_AXISW_read_slave_ready()
257     *slave_ready_en = AXISW->DATA & 0x01;  in MSS_AXISW_read_slave_ready()
259     return ((AXISW->CMD & AXISW_CMD_ERR_MASK) >> AXISW_CMD_ERR);   /*return error bit value*/  in MSS_AXISW_read_slave_ready()