183     this_spi->hw_reg->CONTROL &= ~CTRL_REG_RESET_MASK;  in MSS_SPI_init()
212     this_spi->hw_reg->CONTROL &= ~(uint32_t)CTRL_MASTER_MASK;  in MSS_SPI_configure_slave_mode()
215     this_spi->hw_reg->CONTROL &= ~(uint32_t)CTRL_ENABLE_MASK;  in MSS_SPI_configure_slave_mode()
216     this_spi->hw_reg->CONTROL = (this_spi->hw_reg->CONTROL & ~PROTOCOL_MODE_MASK)  in MSS_SPI_configure_slave_mode()
221     this_spi->hw_reg->CONTROL = (this_spi->hw_reg->CONTROL & ~TXRXDFCOUNT_MASK)  in MSS_SPI_configure_slave_mode()
225     this_spi->hw_reg->CONTROL |= CTRL_ENABLE_MASK;  in MSS_SPI_configure_slave_mode()
265     this_spi->hw_reg->CONTROL &= ~(uint32_t)CTRL_ENABLE_MASK;  in MSS_SPI_configure_master_mode()
266     this_spi->hw_reg->CONTROL |= CTRL_MASTER_MASK;  in MSS_SPI_configure_master_mode()
267     this_spi->hw_reg->CONTROL |= CTRL_ENABLE_MASK;  in MSS_SPI_configure_master_mode()
322     ASSERT((this_spi->hw_reg->CONTROL & CTRL_MASTER_MASK)  in MSS_SPI_set_slave_select()
338     this_spi->hw_reg->CONTROL &= ~(uint32_t)CTRL_ENABLE_MASK;  in MSS_SPI_set_slave_select()
339     this_spi->hw_reg->CONTROL = this_spi->slaves_cfg[slave].ctrl_reg;  in MSS_SPI_set_slave_select()
344     this_spi->hw_reg->CONTROL |= CTRL_ENABLE_MASK;  in MSS_SPI_set_slave_select()
368     ASSERT((this_spi->hw_reg->CONTROL & CTRL_MASTER_MASK)  in MSS_SPI_clear_slave_select()
402     ASSERT((this_spi->hw_reg->CONTROL & CTRL_MASTER_MASK)  in MSS_SPI_transfer_frame()
407     this_spi->hw_reg->CONTROL = (this_spi->hw_reg->CONTROL & ~TXRXDFCOUNT_MASK)  in MSS_SPI_transfer_frame()
465     ASSERT((this_spi->hw_reg->CONTROL & CTRL_MASTER_MASK)  in MSS_SPI_transfer_block()
493     this_spi->hw_reg->CONTROL &= ~(uint32_t)CTRL_ENABLE_MASK;  in MSS_SPI_transfer_block()
495     this_spi->hw_reg->CONTROL = (this_spi->hw_reg->CONTROL & ~TXRXDFCOUNT_MASK) |  in MSS_SPI_transfer_block()
500     this_spi->hw_reg->CONTROL |= CTRL_ENABLE_MASK;  in MSS_SPI_transfer_block()
589     ASSERT((this_spi->hw_reg->CONTROL & CTRL_MASTER_MASK)  in MSS_SPI_set_frame_rx_handler()
614     this_spi->hw_reg->CONTROL = (this_spi->hw_reg->CONTROL & ~TXRXDFCOUNT_MASK)  in MSS_SPI_set_frame_rx_handler()
629     this_spi->hw_reg->CONTROL |= ((uint32_t)CTRL_URUN_IRQ_EN_MASK |  in MSS_SPI_set_frame_rx_handler()
650     ASSERT((this_spi->hw_reg->CONTROL & CTRL_MASTER_MASK)  in MSS_SPI_set_slave_tx_frame()
682     this_spi->hw_reg->CONTROL = (this_spi->hw_reg->CONTROL & ~TXRXDFCOUNT_MASK)  in MSS_SPI_set_slave_tx_frame()
704     this_spi->hw_reg->CONTROL |= ((uint32_t)CTRL_URUN_IRQ_EN_MASK |  in MSS_SPI_set_slave_tx_frame()
731     ASSERT((this_spi->hw_reg->CONTROL & CTRL_MASTER_MASK) != CTRL_MASTER_MASK);  in MSS_SPI_set_slave_block_buffers()
787     this_spi->hw_reg->CONTROL &= ~(uint32_t)CTRL_ENABLE_MASK;  in MSS_SPI_set_slave_block_buffers()
789     this_spi->hw_reg->CONTROL = (this_spi->hw_reg->CONTROL & ~TXRXDFCOUNT_MASK)  in MSS_SPI_set_slave_block_buffers()
792     this_spi->hw_reg->CONTROL |= CTRL_ENABLE_MASK;  in MSS_SPI_set_slave_block_buffers()
821         this_spi->hw_reg->CONTROL |= CTRL_TX_IRQ_EN_MASK;  in MSS_SPI_set_slave_block_buffers()
849     this_spi->hw_reg->CONTROL |= ((uint32_t)CTRL_URUN_IRQ_EN_MASK |  in MSS_SPI_set_slave_block_buffers()
946     this_spi->hw_reg->CONTROL |= CTRL_ENABLE_MASK;  in MSS_SPI_enable()
964     this_spi->hw_reg->CONTROL &= ~(uint32_t)CTRL_ENABLE_MASK;  in MSS_SPI_disable()
1199             this_spi->hw_reg->CONTROL = (this_spi->hw_reg->CONTROL  in mss_spi_isr()
1294     control_reg = this_spi->hw_reg->CONTROL;  in recover_from_rx_overflow()
1310         this_spi->hw_reg->CONTROL &= ~CTRL_REG_RESET_MASK;  in recover_from_rx_overflow()
1319         this_spi->hw_reg->CONTROL &= ~CTRL_REG_RESET_MASK;  in recover_from_rx_overflow()
1328         this_spi->hw_reg->CONTROL &= ~CTRL_REG_RESET_MASK;  in recover_from_rx_overflow()
1337         this_spi->hw_reg->CONTROL &= ~CTRL_REG_RESET_MASK;  in recover_from_rx_overflow()
1346     this_spi->hw_reg->CONTROL = control_reg;  in recover_from_rx_overflow()
1349     this_spi->hw_reg->CONTROL |= CTRL_ENABLE_MASK;  in recover_from_rx_overflow()