Lines Matching refs:mec_qspi_regs

151 struct mec_qspi_regs;
156 bool mec_hal_qspi_is_enabled(struct mec_qspi_regs *regs);
159 uint32_t mec_hal_qspi_get_freq(struct mec_qspi_regs *base);
160 uint32_t mec_hal_qspi_freq_div(struct mec_qspi_regs *base);
161 uint16_t mec_hal_qspi_freq_div_raw(struct mec_qspi_regs *base);
162 int mec_hal_qspi_set_freq(struct mec_qspi_regs *base, uint32_t freqhz);
163 int mec_hal_qspi_byte_time_ns(struct mec_qspi_regs *base, uint32_t *btime_ns);
166 int mec_hal_qspi_reset(struct mec_qspi_regs *base);
171 int mec_hal_qspi_reset_sr(struct mec_qspi_regs *base);
173 void mec_hal_qspi_girq_clr(struct mec_qspi_regs *base);
174 void mec_hal_qspi_girq_ctrl(struct mec_qspi_regs *base, uint8_t enable);
175 uint32_t mec_hal_qspi_girq_is_result(struct mec_qspi_regs *base);
180 int mec_hal_qspi_clk_gate(struct mec_qspi_regs *base, uint8_t gate_clocks_on);
182 int mec_hal_qspi_init(struct mec_qspi_regs *base,
188 int mec_hal_qspi_options(struct mec_qspi_regs *regs, uint8_t en, uint32_t options);
190 int mec_hal_qspi_cs_select(struct mec_qspi_regs *base, enum mec_qspi_cs cs);
192 int mec_hal_qspi_spi_signal_mode(struct mec_qspi_regs *base, enum mec_qspi_signal_mode spi_mode);
193 int mec_hal_qspi_sampling_phase_pol(struct mec_qspi_regs *base, uint8_t phpol);
195 int mec_hal_qspi_io(struct mec_qspi_regs *base, enum mec_qspi_io io);
197 int mec_hal_qspi_cs_timing_adjust(struct mec_qspi_regs *base,
200 int mec_hal_qspi_cs_timing(struct mec_qspi_regs *base, uint32_t cs_timing);
202 int mec_hal_qspi_tap_select(struct mec_qspi_regs *base, uint8_t sel_sck_tap, uint8_t sel_ctrl_tap);
204 int mec_hal_qspi_cs1_freq(struct mec_qspi_regs *base, uint32_t freq);
206 int mec_hal_qspi_force_stop(struct mec_qspi_regs *base);
208 int mec_hal_qspi_done(struct mec_qspi_regs *base);
210 uint32_t mec_hal_qspi_hw_status(struct mec_qspi_regs *base);
211 int mec_hal_qspi_hw_status_clr(struct mec_qspi_regs *base, uint32_t msk);
212 int mec_hal_qspi_intr_ctrl(struct mec_qspi_regs *base, int enable);
213 int mec_hal_qspi_intr_ctrl_msk(struct mec_qspi_regs *base, int enable, uint32_t msk);
215 int mec_hal_qspi_tx_fifo_is_empty(struct mec_qspi_regs *base);
216 int mec_hal_qspi_tx_fifo_is_full(struct mec_qspi_regs *base);
217 int mec_hal_qspi_rx_fifo_is_empty(struct mec_qspi_regs *base);
218 int mec_hal_qspi_rx_fifo_is_full(struct mec_qspi_regs *base);
224 int mec_hal_qspi_start(struct mec_qspi_regs *base, uint32_t ien_mask);
229 int mec_hal_qspi_wr_tx_fifo(struct mec_qspi_regs *regs, const uint8_t *buf, uint32_t bufsz,
232 int mec_hal_qspi_rd_rx_fifo(struct mec_qspi_regs *regs, uint8_t *buf, uint32_t bufsz,
256 int mec_hal_qspi_ldma(struct mec_qspi_regs *base, const uint8_t *txb,
301 int mec_hal_qspi_ldma_cfg1(struct mec_qspi_regs *regs, uintptr_t buf_addr,
317 int mec_hal_qspi_load_descrs(struct mec_qspi_regs *regs, struct mec_qspi_context *ctx,
320 int mec_hal_qspi_load_descrs_at(struct mec_qspi_regs *regs, const uint32_t *descrs, uint8_t ndescr,