84     uint32_t fdiv = (base->MODE & MEC_QSPI_MODE_CLKDIV_Msk) >> MEC_QSPI_MODE_CLKDIV_Pos;  in qspi_get_freq()  local
86     if (fdiv == 0u) { /* zero is maximum clock divider */  in qspi_get_freq()
87         fdiv = MEC_QSPI_M_FDIV_MAX;  in qspi_get_freq()
90     return (srcfreq / fdiv);  in qspi_get_freq()
104     uint32_t fdiv = 0;  in mec_hal_qspi_freq_div()  local
107         fdiv = (base->MODE & MEC_QSPI_MODE_CLKDIV_Msk) >> MEC_QSPI_MODE_CLKDIV_Pos;  in mec_hal_qspi_freq_div()
110     if (fdiv == 0) {  in mec_hal_qspi_freq_div()
111         fdiv = 0x10000u;  in mec_hal_qspi_freq_div()
114     return fdiv;  in mec_hal_qspi_freq_div()
207     uint32_t fdiv;  in compute_freq_divisor()  local
210         fdiv = 0u; /* HW divider of 0 is divide by MEC_QSPI_M_FDIV_MAX */  in compute_freq_divisor()
212         fdiv = 1u;  in compute_freq_divisor()
214         fdiv = src_freq / freq_hz;  in compute_freq_divisor()
217     return fdiv;  in compute_freq_divisor()
222     uint32_t fdiv = compute_freq_divisor(freqhz);  in qspi_set_freq()  local
225                   | (fdiv << MEC_QSPI_MODE_CLKDIV_Pos));  in qspi_set_freq()
330     uint32_t fdiv;  in qspi_cs1_freq()  local
333         fdiv = compute_freq_divisor(freq);  in qspi_cs1_freq()
334         base->ALT1_MODE = (fdiv << MEC_QSPI_MODE_CLKDIV_Pos) & MEC_QSPI_MODE_CLKDIV_Msk;  in qspi_cs1_freq()
355     uint32_t fdiv = (base->MODE & MEC_QSPI_MODE_CLKDIV_Msk) >> MEC_QSPI_MODE_CLKDIV_Pos;  in qspi_compute_byte_time_ns()  local
361         fdiv = ((base->ALT1_MODE & MEC_QSPI_ALT1_MODE_CS1_ALT_CLKDIV_Msk)  in qspi_compute_byte_time_ns()
365     if (!fdiv) { /* divider reg field = 0 is maximum divider */  in qspi_compute_byte_time_ns()
366         fdiv = MEC_QSPI_M_FDIV_MAX;  in qspi_compute_byte_time_ns()
369     freq /= fdiv;  in qspi_compute_byte_time_ns()