Lines Matching refs:val
586 void _i3c_cmd_queue_buf_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val);
587 void _i3c_tx_fifo_empty_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val);
588 void _i3c_rx_buf_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val);
589 void _i3c_tx_buf_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val);
590 void _i3c_tx_start_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val);
591 void _i3c_rx_start_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val);
598 void _i3c_cmd_queue_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val);
599 void _i3c_ibi_data_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val);
600 void _i3c_ibi_status_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val);
643 void _i3c_host_dma_tx_burst_length_set(struct mec_i3c_host_regs *regs, uint32_t val);
644 void _i3c_host_dma_rx_burst_length_set(struct mec_i3c_host_regs *regs, uint32_t val);
645 void _i3c_host_port_set(struct mec_i3c_host_regs *regs, uint32_t val);
646 void _i3c_host_stuck_sda_config(struct mec_i3c_host_regs *regs, uint32_t val,
648 void _i3c_host_tx_dma_tout_config(struct mec_i3c_host_regs *regs, uint32_t val,
650 void _i3c_host_rx_dma_tout_config(struct mec_i3c_host_regs *regs, uint32_t val,
653 void _i3c_sec_host_dma_tx_burst_length_set(struct mec_i3c_sec_regs *regs, uint32_t val);
654 void _i3c_sec_host_dma_rx_burst_length_set(struct mec_i3c_sec_regs *regs, uint32_t val);
655 void _i3c_sec_host_port_set(struct mec_i3c_sec_regs *regs, uint32_t val);
658 void _i3c_sec_host_tx_dma_tout_config(struct mec_i3c_sec_regs *regs, uint32_t val,
660 void _i3c_sec_host_rx_dma_tout_config(struct mec_i3c_sec_regs *regs, uint32_t val,
676 uint32_t val);