Lines Matching refs:val
238 void _i3c_cmd_queue_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val) in _i3c_cmd_queue_threshold_set() argument
241 regs->QUE_THLD_CTRL |= (val << QUEUE_THLD_CMD_QUEUE_BITPOS); in _i3c_cmd_queue_threshold_set()
249 void _i3c_ibi_data_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val) in _i3c_ibi_data_threshold_set() argument
252 regs->QUE_THLD_CTRL |= (val << QUEUE_THLD_IBI_DATA_BITPOS); in _i3c_ibi_data_threshold_set()
260 void _i3c_ibi_status_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val) in _i3c_ibi_status_threshold_set() argument
263 regs->QUE_THLD_CTRL |= (val << QUEUE_THLD_IBI_STATUS_BITPOS); in _i3c_ibi_status_threshold_set()
271 void _i3c_tx_buf_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val) in _i3c_tx_buf_threshold_set() argument
274 regs->DB_THLD_CTRL |= (val << DATA_BUF_THLD_TX_FIFO_EMPTY_BITPOS); in _i3c_tx_buf_threshold_set()
282 void _i3c_rx_buf_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val) in _i3c_rx_buf_threshold_set() argument
285 regs->DB_THLD_CTRL |= (val << DATA_BUF_THLD_RX_FIFO_BITPOS); in _i3c_rx_buf_threshold_set()
293 void _i3c_tx_start_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val) in _i3c_tx_start_threshold_set() argument
296 regs->DB_THLD_CTRL |= (val << DATA_BUF_THLD_TX_FIFO_START_BITPOS); in _i3c_tx_start_threshold_set()
304 void _i3c_rx_start_threshold_set(struct mec_i3c_host_regs *regs, uint32_t val) in _i3c_rx_start_threshold_set() argument
307 regs->DB_THLD_CTRL |= (val << DATA_BUF_THLD_RX_FIFO_START_BITPOS); in _i3c_rx_start_threshold_set()
388 uint32_t val; in _i3c_enable() local
391 val = regs->DEV_CTRL; in _i3c_enable()
393 val |= sbit_ENABLE; in _i3c_enable()
398 val |= sbit_IBA_INCLUDE; in _i3c_enable()
402 val |= sbit_DMA_ENABLE; in _i3c_enable()
405 regs->DEV_CTRL = val; in _i3c_enable()
415 volatile uint32_t val = 0; in _i3c_disable() local
418 val = regs->DEV_CTRL; in _i3c_disable()
420 val &= ~sbit_ENABLE; in _i3c_disable()
422 regs->DEV_CTRL = val; in _i3c_disable()
460 volatile uint32_t val = 0; in _i3c_hot_join_disable() local
463 val = regs->DEV_CTRL; in _i3c_hot_join_disable()
467 val |= sbit_HOT_JOIN_CTRL; in _i3c_hot_join_disable()
469 regs->DEV_CTRL = val; in _i3c_hot_join_disable()
480 volatile uint32_t val = 0; in _i3c_tgt_hot_join_disable() local
483 val = regs->TGT_EVT_STS; in _i3c_tgt_hot_join_disable()
485 val &= (uint32_t)~sbit_HJ_ENABLE; in _i3c_tgt_hot_join_disable()
487 regs->DEV_CTRL = val; in _i3c_tgt_hot_join_disable()
498 volatile uint32_t val = 0; in _i3c_hot_join_enable() local
501 val = regs->DEV_CTRL; in _i3c_hot_join_enable()
504 val &= ~sbit_HOT_JOIN_CTRL; in _i3c_hot_join_enable()
506 regs->DEV_CTRL = val; in _i3c_hot_join_enable()
786 void _i3c_host_dma_tx_burst_length_set(struct mec_i3c_host_regs *regs, uint32_t val) in _i3c_host_dma_tx_burst_length_set() argument
789 regs->HOST_CFG |= (val << HOST_CFG_DMA_TX_BURST_LENGTH_BIT_POS); in _i3c_host_dma_tx_burst_length_set()
797 void _i3c_host_dma_rx_burst_length_set(struct mec_i3c_host_regs *regs, uint32_t val) in _i3c_host_dma_rx_burst_length_set() argument
800 regs->HOST_CFG |= (val << HOST_CFG_DMA_RX_BURST_LENGTH_BIT_POS); in _i3c_host_dma_rx_burst_length_set()
808 void _i3c_host_port_set(struct mec_i3c_host_regs *regs, uint32_t val) in _i3c_host_port_set() argument
811 regs->HOST_CFG |= (val << HOST_CFG_PORT_SEL_BIT_POS); in _i3c_host_port_set()
867 void _i3c_sec_host_dma_tx_burst_length_set(struct mec_i3c_sec_regs *regs, uint32_t val) in _i3c_sec_host_dma_tx_burst_length_set() argument
870 regs->SEC_CFG |= (val << SEC_HOST_CFG_DMA_TX_BURST_LENGTH_BIT_POS); in _i3c_sec_host_dma_tx_burst_length_set()
878 void _i3c_sec_host_dma_rx_burst_length_set(struct mec_i3c_sec_regs *regs, uint32_t val) in _i3c_sec_host_dma_rx_burst_length_set() argument
881 regs->SEC_CFG |= (val << SEC_HOST_CFG_DMA_RX_BURST_LENGTH_BIT_POS); in _i3c_sec_host_dma_rx_burst_length_set()
889 void _i3c_sec_host_port_set(struct mec_i3c_sec_regs *regs, uint32_t val) in _i3c_sec_host_port_set() argument
892 regs->SEC_CFG |= (val << SEC_HOST_CFG_PORT_SEL_BIT_POS); in _i3c_sec_host_port_set()
968 uint32_t val; in _i3c_dev_addr_table_ptr_get() local
970 val = regs->DAT_PTR; in _i3c_dev_addr_table_ptr_get()
972 *start_addr = val & 0xFFFFu; in _i3c_dev_addr_table_ptr_get()
973 *depth = (uint16_t)((val >> 16) & 0xFFFFu); in _i3c_dev_addr_table_ptr_get()
986 uint32_t val; in _i3c_dev_char_table_ptr_get() local
988 val = regs->DCT_PTR; in _i3c_dev_char_table_ptr_get()
990 *start_addr = val & 0xFFFu; /* Bits 0 to 11 */ in _i3c_dev_char_table_ptr_get()
991 *depth = (val >> 12) & 0x7Fu; /* Bits 12 to 18 */ in _i3c_dev_char_table_ptr_get()
1035 uint32_t val) in _i3c_DAT_write() argument
1041 *entry_addr = val; in _i3c_DAT_write()
1055 uint32_t val; in _i3c_DAT_read() local
1059 val = *entry_addr; in _i3c_DAT_read()
1061 return val; in _i3c_DAT_read()